1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 31 * 32 * The XHCI 1.0 spec can be found at 33 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 34 * and the USB 3.0 spec at 35 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 36 */ 37 38 /* 39 * A few words about the design implementation: This driver emulates 40 * the concept about TDs which is found in EHCI specification. This 41 * way we achieve that the USB controller drivers look similar to 42 * eachother which makes it easier to understand the code. 43 */ 44 45 #ifdef USB_GLOBAL_INCLUDE_FILE 46 #include USB_GLOBAL_INCLUDE_FILE 47 #else 48 #include <sys/stdint.h> 49 #include <sys/stddef.h> 50 #include <sys/param.h> 51 #include <sys/queue.h> 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/bus.h> 56 #include <sys/module.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/condvar.h> 60 #include <sys/sysctl.h> 61 #include <sys/sx.h> 62 #include <sys/unistd.h> 63 #include <sys/callout.h> 64 #include <sys/malloc.h> 65 #include <sys/priv.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 70 #define USB_DEBUG_VAR xhcidebug 71 72 #include <dev/usb/usb_core.h> 73 #include <dev/usb/usb_debug.h> 74 #include <dev/usb/usb_busdma.h> 75 #include <dev/usb/usb_process.h> 76 #include <dev/usb/usb_transfer.h> 77 #include <dev/usb/usb_device.h> 78 #include <dev/usb/usb_hub.h> 79 #include <dev/usb/usb_util.h> 80 81 #include <dev/usb/usb_controller.h> 82 #include <dev/usb/usb_bus.h> 83 #endif /* USB_GLOBAL_INCLUDE_FILE */ 84 85 #include <dev/usb/controller/xhci.h> 86 #include <dev/usb/controller/xhcireg.h> 87 88 #define XHCI_BUS2SC(bus) \ 89 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 90 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 91 92 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 93 "USB XHCI"); 94 95 static int xhcistreams; 96 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN, 97 &xhcistreams, 0, "Set to enable streams mode support"); 98 99 static int xhcictlquirk = 1; 100 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlquirk, CTLFLAG_RWTUN, 101 &xhcictlquirk, 0, "Set to enable control endpoint quirk"); 102 103 #ifdef USB_DEBUG 104 static int xhcidebug; 105 static int xhciroute; 106 static int xhcipolling; 107 static int xhcidma32; 108 static int xhcictlstep; 109 110 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN, 111 &xhcidebug, 0, "Debug level"); 112 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN, 113 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller"); 114 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN, 115 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller"); 116 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN, 117 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller"); 118 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN, 119 &xhcictlstep, 0, "Set to enable control endpoint status stage stepping"); 120 #else 121 #define xhciroute 0 122 #define xhcidma32 0 123 #define xhcictlstep 0 124 #endif 125 126 #define XHCI_INTR_ENDPT 1 127 128 struct xhci_std_temp { 129 struct xhci_softc *sc; 130 struct usb_page_cache *pc; 131 struct xhci_td *td; 132 struct xhci_td *td_next; 133 uint32_t len; 134 uint32_t offset; 135 uint32_t max_packet_size; 136 uint32_t average; 137 uint16_t isoc_delta; 138 uint16_t isoc_frame; 139 uint8_t shortpkt; 140 uint8_t multishort; 141 uint8_t last_frame; 142 uint8_t trb_type; 143 uint8_t direction; 144 uint8_t tbc; 145 uint8_t tlbpc; 146 uint8_t step_td; 147 uint8_t do_isoc_sync; 148 }; 149 150 static void xhci_do_poll(struct usb_bus *); 151 static void xhci_device_done(struct usb_xfer *, usb_error_t); 152 static void xhci_root_intr(struct xhci_softc *); 153 static void xhci_free_device_ext(struct usb_device *); 154 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 155 struct usb_endpoint_descriptor *); 156 static usb_proc_callback_t xhci_configure_msg; 157 static usb_error_t xhci_configure_device(struct usb_device *); 158 static usb_error_t xhci_configure_endpoint(struct usb_device *, 159 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 160 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 161 uint8_t); 162 static usb_error_t xhci_configure_mask(struct usb_device *, 163 uint32_t, uint8_t); 164 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 165 uint64_t, uint8_t); 166 static void xhci_endpoint_doorbell(struct usb_xfer *); 167 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 168 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 169 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 170 #ifdef USB_DEBUG 171 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 172 #endif 173 174 static const struct usb_bus_methods xhci_bus_methods; 175 176 #ifdef USB_DEBUG 177 static void 178 xhci_dump_trb(struct xhci_trb *trb) 179 { 180 DPRINTFN(5, "trb = %p\n", trb); 181 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 182 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 183 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 184 } 185 186 static void 187 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 188 { 189 DPRINTFN(5, "pep = %p\n", pep); 190 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 191 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 192 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 193 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 194 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 195 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 196 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 197 } 198 199 static void 200 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 201 { 202 DPRINTFN(5, "psl = %p\n", psl); 203 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 204 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 205 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 206 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 207 } 208 #endif 209 210 uint8_t 211 xhci_use_polling(void) 212 { 213 #ifdef USB_DEBUG 214 return (xhcipolling != 0); 215 #else 216 return (0); 217 #endif 218 } 219 220 static void 221 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 222 { 223 struct xhci_softc *sc = XHCI_BUS2SC(bus); 224 uint16_t i; 225 226 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 227 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 228 229 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 230 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 231 232 for (i = 0; i != sc->sc_noscratch; i++) { 233 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 234 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 235 } 236 } 237 238 static void 239 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 240 { 241 if (sc->sc_ctx_is_64_byte) { 242 uint32_t offset; 243 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 244 /* all contexts are initially 32-bytes */ 245 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 246 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 247 } 248 *ptr = htole32(val); 249 } 250 251 static uint32_t 252 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 253 { 254 if (sc->sc_ctx_is_64_byte) { 255 uint32_t offset; 256 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 257 /* all contexts are initially 32-bytes */ 258 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 259 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 260 } 261 return (le32toh(*ptr)); 262 } 263 264 static void 265 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 266 { 267 if (sc->sc_ctx_is_64_byte) { 268 uint32_t offset; 269 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 270 /* all contexts are initially 32-bytes */ 271 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 272 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 273 } 274 *ptr = htole64(val); 275 } 276 277 #ifdef USB_DEBUG 278 static uint64_t 279 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 280 { 281 if (sc->sc_ctx_is_64_byte) { 282 uint32_t offset; 283 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 284 /* all contexts are initially 32-bytes */ 285 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 286 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 287 } 288 return (le64toh(*ptr)); 289 } 290 #endif 291 292 static int 293 xhci_reset_command_queue_locked(struct xhci_softc *sc) 294 { 295 struct usb_page_search buf_res; 296 struct xhci_hw_root *phwr; 297 uint64_t addr; 298 uint32_t temp; 299 300 DPRINTF("\n"); 301 302 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 303 if (temp & XHCI_CRCR_LO_CRR) { 304 DPRINTF("Command ring running\n"); 305 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 306 307 /* 308 * Try to abort the last command as per section 309 * 4.6.1.2 "Aborting a Command" of the XHCI 310 * specification: 311 */ 312 313 /* stop and cancel */ 314 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 315 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 316 317 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 318 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 319 320 /* wait 250ms */ 321 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 322 323 /* check if command ring is still running */ 324 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 325 if (temp & XHCI_CRCR_LO_CRR) { 326 DPRINTF("Comand ring still running\n"); 327 return (USB_ERR_IOERROR); 328 } 329 } 330 331 /* reset command ring */ 332 sc->sc_command_ccs = 1; 333 sc->sc_command_idx = 0; 334 335 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 336 337 /* set up command ring control base address */ 338 addr = buf_res.physaddr; 339 phwr = buf_res.buffer; 340 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 341 342 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 343 344 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 345 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 346 347 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 348 349 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 350 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 351 352 return (0); 353 } 354 355 usb_error_t 356 xhci_start_controller(struct xhci_softc *sc) 357 { 358 struct usb_page_search buf_res; 359 struct xhci_hw_root *phwr; 360 struct xhci_dev_ctx_addr *pdctxa; 361 usb_error_t err; 362 uint64_t addr; 363 uint32_t temp; 364 uint16_t i; 365 366 DPRINTF("\n"); 367 368 sc->sc_event_ccs = 1; 369 sc->sc_event_idx = 0; 370 sc->sc_command_ccs = 1; 371 sc->sc_command_idx = 0; 372 373 err = xhci_reset_controller(sc); 374 if (err) 375 return (err); 376 377 /* set up number of device slots */ 378 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 379 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 380 381 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 382 383 temp = XREAD4(sc, oper, XHCI_USBSTS); 384 385 /* clear interrupts */ 386 XWRITE4(sc, oper, XHCI_USBSTS, temp); 387 /* disable all device notifications */ 388 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 389 390 /* set up device context base address */ 391 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 392 pdctxa = buf_res.buffer; 393 memset(pdctxa, 0, sizeof(*pdctxa)); 394 395 addr = buf_res.physaddr; 396 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 397 398 /* slot 0 points to the table of scratchpad pointers */ 399 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 400 401 for (i = 0; i != sc->sc_noscratch; i++) { 402 struct usb_page_search buf_scp; 403 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 404 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 405 } 406 407 addr = buf_res.physaddr; 408 409 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 410 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 411 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 412 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 413 414 /* set up event table size */ 415 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 416 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max); 417 418 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max)); 419 420 /* set up interrupt rate */ 421 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 422 423 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 424 425 phwr = buf_res.buffer; 426 addr = buf_res.physaddr; 427 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 428 429 /* reset hardware root structure */ 430 memset(phwr, 0, sizeof(*phwr)); 431 432 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 433 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 434 435 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 436 437 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 438 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 439 440 addr = buf_res.physaddr; 441 442 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 443 444 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 445 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 446 447 /* set up interrupter registers */ 448 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 449 temp |= XHCI_IMAN_INTR_ENA; 450 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 451 452 /* set up command ring control base address */ 453 addr = buf_res.physaddr; 454 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 455 456 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 457 458 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 459 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 460 461 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 462 463 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 464 465 /* Go! */ 466 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 467 XHCI_CMD_INTE | XHCI_CMD_HSEE); 468 469 for (i = 0; i != 100; i++) { 470 usb_pause_mtx(NULL, hz / 100); 471 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 472 if (!temp) 473 break; 474 } 475 if (temp) { 476 XWRITE4(sc, oper, XHCI_USBCMD, 0); 477 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 478 return (USB_ERR_IOERROR); 479 } 480 481 /* catch any lost interrupts */ 482 xhci_do_poll(&sc->sc_bus); 483 484 if (sc->sc_port_route != NULL) { 485 /* Route all ports to the XHCI by default */ 486 sc->sc_port_route(sc->sc_bus.parent, 487 ~xhciroute, xhciroute); 488 } 489 return (0); 490 } 491 492 usb_error_t 493 xhci_halt_controller(struct xhci_softc *sc) 494 { 495 uint32_t temp; 496 uint16_t i; 497 498 DPRINTF("\n"); 499 500 sc->sc_capa_off = 0; 501 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 502 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 503 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 504 505 /* Halt controller */ 506 XWRITE4(sc, oper, XHCI_USBCMD, 0); 507 508 for (i = 0; i != 100; i++) { 509 usb_pause_mtx(NULL, hz / 100); 510 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 511 if (temp) 512 break; 513 } 514 515 if (!temp) { 516 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 517 return (USB_ERR_IOERROR); 518 } 519 return (0); 520 } 521 522 usb_error_t 523 xhci_reset_controller(struct xhci_softc *sc) 524 { 525 uint32_t temp = 0; 526 uint16_t i; 527 528 DPRINTF("\n"); 529 530 /* Reset controller */ 531 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 532 533 for (i = 0; i != 100; i++) { 534 usb_pause_mtx(NULL, hz / 100); 535 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 536 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 537 if (!temp) 538 break; 539 } 540 541 if (temp) { 542 device_printf(sc->sc_bus.parent, "Controller " 543 "reset timeout.\n"); 544 return (USB_ERR_IOERROR); 545 } 546 return (0); 547 } 548 549 usb_error_t 550 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32) 551 { 552 uint32_t temp; 553 554 DPRINTF("\n"); 555 556 /* initialize some bus fields */ 557 sc->sc_bus.parent = self; 558 559 /* set the bus revision */ 560 sc->sc_bus.usbrev = USB_REV_3_0; 561 562 /* set up the bus struct */ 563 sc->sc_bus.methods = &xhci_bus_methods; 564 565 /* set up devices array */ 566 sc->sc_bus.devices = sc->sc_devices; 567 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 568 569 /* set default cycle state in case of early interrupts */ 570 sc->sc_event_ccs = 1; 571 sc->sc_command_ccs = 1; 572 573 /* set up bus space offsets */ 574 sc->sc_capa_off = 0; 575 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 576 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 577 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 578 579 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 580 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 581 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 582 583 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 584 585 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 586 device_printf(sc->sc_bus.parent, "Controller does " 587 "not support 4K page size.\n"); 588 return (ENXIO); 589 } 590 591 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 592 593 DPRINTF("HCS0 = 0x%08x\n", temp); 594 595 /* set up context size */ 596 if (XHCI_HCS0_CSZ(temp)) { 597 sc->sc_ctx_is_64_byte = 1; 598 } else { 599 sc->sc_ctx_is_64_byte = 0; 600 } 601 602 /* get DMA bits */ 603 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && 604 xhcidma32 == 0 && dma32 == 0) ? 64 : 32; 605 606 device_printf(self, "%d bytes context size, %d-bit DMA\n", 607 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); 608 609 /* enable 64Kbyte control endpoint quirk */ 610 sc->sc_bus.control_ep_quirk = (xhcictlquirk ? 1 : 0); 611 612 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 613 614 /* get number of device slots */ 615 sc->sc_noport = XHCI_HCS1_N_PORTS(temp); 616 617 if (sc->sc_noport == 0) { 618 device_printf(sc->sc_bus.parent, "Invalid number " 619 "of ports: %u\n", sc->sc_noport); 620 return (ENXIO); 621 } 622 623 sc->sc_noport = sc->sc_noport; 624 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 625 626 DPRINTF("Max slots: %u\n", sc->sc_noslot); 627 628 if (sc->sc_noslot > XHCI_MAX_DEVICES) 629 sc->sc_noslot = XHCI_MAX_DEVICES; 630 631 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 632 633 DPRINTF("HCS2=0x%08x\n", temp); 634 635 /* get number of scratchpads */ 636 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 637 638 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 639 device_printf(sc->sc_bus.parent, "XHCI request " 640 "too many scratchpads\n"); 641 return (ENOMEM); 642 } 643 644 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 645 646 /* get event table size */ 647 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); 648 if (sc->sc_erst_max > XHCI_MAX_RSEG) 649 sc->sc_erst_max = XHCI_MAX_RSEG; 650 651 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 652 653 /* get maximum exit latency */ 654 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 655 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 656 657 /* Check if we should use the default IMOD value. */ 658 if (sc->sc_imod_default == 0) 659 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 660 661 /* get all DMA memory */ 662 if (usb_bus_mem_alloc_all(&sc->sc_bus, 663 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 664 return (ENOMEM); 665 } 666 667 /* set up command queue mutex and condition varible */ 668 cv_init(&sc->sc_cmd_cv, "CMDQ"); 669 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 670 671 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 672 sc->sc_config_msg[0].bus = &sc->sc_bus; 673 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 674 sc->sc_config_msg[1].bus = &sc->sc_bus; 675 676 return (0); 677 } 678 679 void 680 xhci_uninit(struct xhci_softc *sc) 681 { 682 /* 683 * NOTE: At this point the control transfer process is gone 684 * and "xhci_configure_msg" is no longer called. Consequently 685 * waiting for the configuration messages to complete is not 686 * needed. 687 */ 688 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 689 690 cv_destroy(&sc->sc_cmd_cv); 691 sx_destroy(&sc->sc_cmd_sx); 692 } 693 694 static void 695 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 696 { 697 struct xhci_softc *sc = XHCI_BUS2SC(bus); 698 699 switch (state) { 700 case USB_HW_POWER_SUSPEND: 701 DPRINTF("Stopping the XHCI\n"); 702 xhci_halt_controller(sc); 703 xhci_reset_controller(sc); 704 break; 705 case USB_HW_POWER_SHUTDOWN: 706 DPRINTF("Stopping the XHCI\n"); 707 xhci_halt_controller(sc); 708 xhci_reset_controller(sc); 709 break; 710 case USB_HW_POWER_RESUME: 711 DPRINTF("Starting the XHCI\n"); 712 xhci_start_controller(sc); 713 break; 714 default: 715 break; 716 } 717 } 718 719 static usb_error_t 720 xhci_generic_done_sub(struct usb_xfer *xfer) 721 { 722 struct xhci_td *td; 723 struct xhci_td *td_alt_next; 724 uint32_t len; 725 uint8_t status; 726 727 td = xfer->td_transfer_cache; 728 td_alt_next = td->alt_next; 729 730 if (xfer->aframes != xfer->nframes) 731 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 732 733 while (1) { 734 735 usb_pc_cpu_invalidate(td->page_cache); 736 737 status = td->status; 738 len = td->remainder; 739 740 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 741 xfer, (unsigned int)xfer->aframes, 742 (unsigned int)xfer->nframes, 743 (unsigned int)len, (unsigned int)td->len, 744 (unsigned int)status); 745 746 /* 747 * Verify the status length and 748 * add the length to "frlengths[]": 749 */ 750 if (len > td->len) { 751 /* should not happen */ 752 DPRINTF("Invalid status length, " 753 "0x%04x/0x%04x bytes\n", len, td->len); 754 status = XHCI_TRB_ERROR_LENGTH; 755 } else if (xfer->aframes != xfer->nframes) { 756 xfer->frlengths[xfer->aframes] += td->len - len; 757 } 758 /* Check for last transfer */ 759 if (((void *)td) == xfer->td_transfer_last) { 760 td = NULL; 761 break; 762 } 763 /* Check for transfer error */ 764 if (status != XHCI_TRB_ERROR_SHORT_PKT && 765 status != XHCI_TRB_ERROR_SUCCESS) { 766 /* the transfer is finished */ 767 td = NULL; 768 break; 769 } 770 /* Check for short transfer */ 771 if (len > 0) { 772 if (xfer->flags_int.short_frames_ok || 773 xfer->flags_int.isochronous_xfr || 774 xfer->flags_int.control_xfr) { 775 /* follow alt next */ 776 td = td->alt_next; 777 } else { 778 /* the transfer is finished */ 779 td = NULL; 780 } 781 break; 782 } 783 td = td->obj_next; 784 785 if (td->alt_next != td_alt_next) { 786 /* this USB frame is complete */ 787 break; 788 } 789 } 790 791 /* update transfer cache */ 792 793 xfer->td_transfer_cache = td; 794 795 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 796 (status != XHCI_TRB_ERROR_SHORT_PKT && 797 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 798 USB_ERR_NORMAL_COMPLETION); 799 } 800 801 static void 802 xhci_generic_done(struct usb_xfer *xfer) 803 { 804 usb_error_t err = 0; 805 806 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 807 xfer, xfer->endpoint); 808 809 /* reset scanner */ 810 811 xfer->td_transfer_cache = xfer->td_transfer_first; 812 813 if (xfer->flags_int.control_xfr) { 814 815 if (xfer->flags_int.control_hdr) 816 err = xhci_generic_done_sub(xfer); 817 818 xfer->aframes = 1; 819 820 if (xfer->td_transfer_cache == NULL) 821 goto done; 822 } 823 824 while (xfer->aframes != xfer->nframes) { 825 826 err = xhci_generic_done_sub(xfer); 827 xfer->aframes++; 828 829 if (xfer->td_transfer_cache == NULL) 830 goto done; 831 } 832 833 if (xfer->flags_int.control_xfr && 834 !xfer->flags_int.control_act) 835 err = xhci_generic_done_sub(xfer); 836 done: 837 /* transfer is complete */ 838 xhci_device_done(xfer, err); 839 } 840 841 static void 842 xhci_activate_transfer(struct usb_xfer *xfer) 843 { 844 struct xhci_td *td; 845 846 td = xfer->td_transfer_cache; 847 848 usb_pc_cpu_invalidate(td->page_cache); 849 850 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 851 852 /* activate the transfer */ 853 854 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 855 usb_pc_cpu_flush(td->page_cache); 856 857 xhci_endpoint_doorbell(xfer); 858 } 859 } 860 861 static void 862 xhci_skip_transfer(struct usb_xfer *xfer) 863 { 864 struct xhci_td *td; 865 struct xhci_td *td_last; 866 867 td = xfer->td_transfer_cache; 868 td_last = xfer->td_transfer_last; 869 870 td = td->alt_next; 871 872 usb_pc_cpu_invalidate(td->page_cache); 873 874 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 875 876 usb_pc_cpu_invalidate(td_last->page_cache); 877 878 /* copy LINK TRB to current waiting location */ 879 880 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 881 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 882 usb_pc_cpu_flush(td->page_cache); 883 884 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 885 usb_pc_cpu_flush(td->page_cache); 886 887 xhci_endpoint_doorbell(xfer); 888 } 889 } 890 891 /*------------------------------------------------------------------------* 892 * xhci_check_transfer 893 *------------------------------------------------------------------------*/ 894 static void 895 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 896 { 897 struct xhci_endpoint_ext *pepext; 898 int64_t offset; 899 uint64_t td_event; 900 uint32_t temp; 901 uint32_t remainder; 902 uint16_t stream_id = 0; 903 uint16_t i; 904 uint8_t status; 905 uint8_t halted; 906 uint8_t epno; 907 uint8_t index; 908 909 /* decode TRB */ 910 td_event = le64toh(trb->qwTrb0); 911 temp = le32toh(trb->dwTrb2); 912 913 remainder = XHCI_TRB_2_REM_GET(temp); 914 status = XHCI_TRB_2_ERROR_GET(temp); 915 916 temp = le32toh(trb->dwTrb3); 917 epno = XHCI_TRB_3_EP_GET(temp); 918 index = XHCI_TRB_3_SLOT_GET(temp); 919 920 /* check if error means halted */ 921 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 922 status != XHCI_TRB_ERROR_SUCCESS); 923 924 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 925 index, epno, remainder, status); 926 927 if (index > sc->sc_noslot) { 928 DPRINTF("Invalid slot.\n"); 929 return; 930 } 931 932 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 933 DPRINTF("Invalid endpoint.\n"); 934 return; 935 } 936 937 pepext = &sc->sc_hw.devs[index].endp[epno]; 938 939 /* try to find the USB transfer that generated the event */ 940 for (i = 0;; i++) { 941 struct usb_xfer *xfer; 942 struct xhci_td *td; 943 944 if (i == (XHCI_MAX_TRANSFERS - 1)) { 945 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS || 946 stream_id == (XHCI_MAX_STREAMS - 1)) 947 break; 948 stream_id++; 949 i = 0; 950 DPRINTFN(5, "stream_id=%u\n", stream_id); 951 } 952 953 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 954 if (xfer == NULL) 955 continue; 956 957 td = xfer->td_transfer_cache; 958 959 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 960 (long long)td_event, 961 (long long)td->td_self, 962 (long long)td->td_self + sizeof(td->td_trb)); 963 964 /* 965 * NOTE: Some XHCI implementations might not trigger 966 * an event on the last LINK TRB so we need to 967 * consider both the last and second last event 968 * address as conditions for a successful transfer. 969 * 970 * NOTE: We assume that the XHCI will only trigger one 971 * event per chain of TRBs. 972 */ 973 974 offset = td_event - td->td_self; 975 976 if (offset >= 0 && 977 offset < (int64_t)sizeof(td->td_trb)) { 978 979 usb_pc_cpu_invalidate(td->page_cache); 980 981 /* compute rest of remainder, if any */ 982 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 983 temp = le32toh(td->td_trb[i].dwTrb2); 984 remainder += XHCI_TRB_2_BYTES_GET(temp); 985 } 986 987 DPRINTFN(5, "New remainder: %u\n", remainder); 988 989 /* clear isochronous transfer errors */ 990 if (xfer->flags_int.isochronous_xfr) { 991 if (halted) { 992 halted = 0; 993 status = XHCI_TRB_ERROR_SUCCESS; 994 remainder = td->len; 995 } 996 } 997 998 /* "td->remainder" is verified later */ 999 td->remainder = remainder; 1000 td->status = status; 1001 1002 usb_pc_cpu_flush(td->page_cache); 1003 1004 /* 1005 * 1) Last transfer descriptor makes the 1006 * transfer done 1007 */ 1008 if (((void *)td) == xfer->td_transfer_last) { 1009 DPRINTF("TD is last\n"); 1010 xhci_generic_done(xfer); 1011 break; 1012 } 1013 1014 /* 1015 * 2) Any kind of error makes the transfer 1016 * done 1017 */ 1018 if (halted) { 1019 DPRINTF("TD has I/O error\n"); 1020 xhci_generic_done(xfer); 1021 break; 1022 } 1023 1024 /* 1025 * 3) If there is no alternate next transfer, 1026 * a short packet also makes the transfer done 1027 */ 1028 if (td->remainder > 0) { 1029 if (td->alt_next == NULL) { 1030 DPRINTF( 1031 "short TD has no alternate next\n"); 1032 xhci_generic_done(xfer); 1033 break; 1034 } 1035 DPRINTF("TD has short pkt\n"); 1036 if (xfer->flags_int.short_frames_ok || 1037 xfer->flags_int.isochronous_xfr || 1038 xfer->flags_int.control_xfr) { 1039 /* follow the alt next */ 1040 xfer->td_transfer_cache = td->alt_next; 1041 xhci_activate_transfer(xfer); 1042 break; 1043 } 1044 xhci_skip_transfer(xfer); 1045 xhci_generic_done(xfer); 1046 break; 1047 } 1048 1049 /* 1050 * 4) Transfer complete - go to next TD 1051 */ 1052 DPRINTF("Following next TD\n"); 1053 xfer->td_transfer_cache = td->obj_next; 1054 xhci_activate_transfer(xfer); 1055 break; /* there should only be one match */ 1056 } 1057 } 1058 } 1059 1060 static int 1061 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1062 { 1063 if (sc->sc_cmd_addr == trb->qwTrb0) { 1064 DPRINTF("Received command event\n"); 1065 sc->sc_cmd_result[0] = trb->dwTrb2; 1066 sc->sc_cmd_result[1] = trb->dwTrb3; 1067 cv_signal(&sc->sc_cmd_cv); 1068 return (1); /* command match */ 1069 } 1070 return (0); 1071 } 1072 1073 static int 1074 xhci_interrupt_poll(struct xhci_softc *sc) 1075 { 1076 struct usb_page_search buf_res; 1077 struct xhci_hw_root *phwr; 1078 uint64_t addr; 1079 uint32_t temp; 1080 int retval = 0; 1081 uint16_t i; 1082 uint8_t event; 1083 uint8_t j; 1084 uint8_t k; 1085 uint8_t t; 1086 1087 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1088 1089 phwr = buf_res.buffer; 1090 1091 /* Receive any events */ 1092 1093 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1094 1095 i = sc->sc_event_idx; 1096 j = sc->sc_event_ccs; 1097 t = 2; 1098 1099 while (1) { 1100 1101 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1102 1103 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1104 1105 if (j != k) 1106 break; 1107 1108 event = XHCI_TRB_3_TYPE_GET(temp); 1109 1110 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1111 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1112 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1113 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1114 1115 switch (event) { 1116 case XHCI_TRB_EVENT_TRANSFER: 1117 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1118 break; 1119 case XHCI_TRB_EVENT_CMD_COMPLETE: 1120 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1121 break; 1122 default: 1123 DPRINTF("Unhandled event = %u\n", event); 1124 break; 1125 } 1126 1127 i++; 1128 1129 if (i == XHCI_MAX_EVENTS) { 1130 i = 0; 1131 j ^= 1; 1132 1133 /* check for timeout */ 1134 if (!--t) 1135 break; 1136 } 1137 } 1138 1139 sc->sc_event_idx = i; 1140 sc->sc_event_ccs = j; 1141 1142 /* 1143 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1144 * latched. That means to activate the register we need to 1145 * write both the low and high double word of the 64-bit 1146 * register. 1147 */ 1148 1149 addr = buf_res.physaddr; 1150 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1151 1152 /* try to clear busy bit */ 1153 addr |= XHCI_ERDP_LO_BUSY; 1154 1155 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1156 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1157 1158 return (retval); 1159 } 1160 1161 static usb_error_t 1162 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1163 uint16_t timeout_ms) 1164 { 1165 struct usb_page_search buf_res; 1166 struct xhci_hw_root *phwr; 1167 uint64_t addr; 1168 uint32_t temp; 1169 uint8_t i; 1170 uint8_t j; 1171 uint8_t timeout = 0; 1172 int err; 1173 1174 XHCI_CMD_ASSERT_LOCKED(sc); 1175 1176 /* get hardware root structure */ 1177 1178 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1179 1180 phwr = buf_res.buffer; 1181 1182 /* Queue command */ 1183 1184 USB_BUS_LOCK(&sc->sc_bus); 1185 retry: 1186 i = sc->sc_command_idx; 1187 j = sc->sc_command_ccs; 1188 1189 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1190 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1191 (long long)le64toh(trb->qwTrb0), 1192 (long)le32toh(trb->dwTrb2), 1193 (long)le32toh(trb->dwTrb3)); 1194 1195 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1196 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1197 1198 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1199 1200 temp = trb->dwTrb3; 1201 1202 if (j) 1203 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1204 else 1205 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1206 1207 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1208 1209 phwr->hwr_commands[i].dwTrb3 = temp; 1210 1211 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1212 1213 addr = buf_res.physaddr; 1214 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1215 1216 sc->sc_cmd_addr = htole64(addr); 1217 1218 i++; 1219 1220 if (i == (XHCI_MAX_COMMANDS - 1)) { 1221 1222 if (j) { 1223 temp = htole32(XHCI_TRB_3_TC_BIT | 1224 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1225 XHCI_TRB_3_CYCLE_BIT); 1226 } else { 1227 temp = htole32(XHCI_TRB_3_TC_BIT | 1228 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1229 } 1230 1231 phwr->hwr_commands[i].dwTrb3 = temp; 1232 1233 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1234 1235 i = 0; 1236 j ^= 1; 1237 } 1238 1239 sc->sc_command_idx = i; 1240 sc->sc_command_ccs = j; 1241 1242 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1243 1244 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1245 USB_MS_TO_TICKS(timeout_ms)); 1246 1247 /* 1248 * In some error cases event interrupts are not generated. 1249 * Poll one time to see if the command has completed. 1250 */ 1251 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1252 DPRINTF("Command was completed when polling\n"); 1253 err = 0; 1254 } 1255 if (err != 0) { 1256 DPRINTF("Command timeout!\n"); 1257 /* 1258 * After some weeks of continuous operation, it has 1259 * been observed that the ASMedia Technology, ASM1042 1260 * SuperSpeed USB Host Controller can suddenly stop 1261 * accepting commands via the command queue. Try to 1262 * first reset the command queue. If that fails do a 1263 * host controller reset. 1264 */ 1265 if (timeout == 0 && 1266 xhci_reset_command_queue_locked(sc) == 0) { 1267 temp = le32toh(trb->dwTrb3); 1268 1269 /* 1270 * Avoid infinite XHCI reset loops if the set 1271 * address command fails to respond due to a 1272 * non-enumerating device: 1273 */ 1274 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1275 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1276 DPRINTF("Set address timeout\n"); 1277 } else { 1278 timeout = 1; 1279 goto retry; 1280 } 1281 } else { 1282 DPRINTF("Controller reset!\n"); 1283 usb_bus_reset_async_locked(&sc->sc_bus); 1284 } 1285 err = USB_ERR_TIMEOUT; 1286 trb->dwTrb2 = 0; 1287 trb->dwTrb3 = 0; 1288 } else { 1289 temp = le32toh(sc->sc_cmd_result[0]); 1290 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1291 err = USB_ERR_IOERROR; 1292 1293 trb->dwTrb2 = sc->sc_cmd_result[0]; 1294 trb->dwTrb3 = sc->sc_cmd_result[1]; 1295 } 1296 1297 USB_BUS_UNLOCK(&sc->sc_bus); 1298 1299 return (err); 1300 } 1301 1302 #if 0 1303 static usb_error_t 1304 xhci_cmd_nop(struct xhci_softc *sc) 1305 { 1306 struct xhci_trb trb; 1307 uint32_t temp; 1308 1309 DPRINTF("\n"); 1310 1311 trb.qwTrb0 = 0; 1312 trb.dwTrb2 = 0; 1313 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1314 1315 trb.dwTrb3 = htole32(temp); 1316 1317 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1318 } 1319 #endif 1320 1321 static usb_error_t 1322 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1323 { 1324 struct xhci_trb trb; 1325 uint32_t temp; 1326 usb_error_t err; 1327 1328 DPRINTF("\n"); 1329 1330 trb.qwTrb0 = 0; 1331 trb.dwTrb2 = 0; 1332 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1333 1334 err = xhci_do_command(sc, &trb, 100 /* ms */); 1335 if (err) 1336 goto done; 1337 1338 temp = le32toh(trb.dwTrb3); 1339 1340 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1341 1342 done: 1343 return (err); 1344 } 1345 1346 static usb_error_t 1347 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1348 { 1349 struct xhci_trb trb; 1350 uint32_t temp; 1351 1352 DPRINTF("\n"); 1353 1354 trb.qwTrb0 = 0; 1355 trb.dwTrb2 = 0; 1356 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1357 XHCI_TRB_3_SLOT_SET(slot_id); 1358 1359 trb.dwTrb3 = htole32(temp); 1360 1361 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1362 } 1363 1364 static usb_error_t 1365 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1366 uint8_t bsr, uint8_t slot_id) 1367 { 1368 struct xhci_trb trb; 1369 uint32_t temp; 1370 1371 DPRINTF("\n"); 1372 1373 trb.qwTrb0 = htole64(input_ctx); 1374 trb.dwTrb2 = 0; 1375 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1376 XHCI_TRB_3_SLOT_SET(slot_id); 1377 1378 if (bsr) 1379 temp |= XHCI_TRB_3_BSR_BIT; 1380 1381 trb.dwTrb3 = htole32(temp); 1382 1383 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1384 } 1385 1386 static usb_error_t 1387 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1388 { 1389 struct usb_page_search buf_inp; 1390 struct usb_page_search buf_dev; 1391 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1392 struct xhci_hw_dev *hdev; 1393 struct xhci_dev_ctx *pdev; 1394 struct xhci_endpoint_ext *pepext; 1395 uint32_t temp; 1396 uint16_t mps; 1397 usb_error_t err; 1398 uint8_t index; 1399 1400 /* the root HUB case is not handled here */ 1401 if (udev->parent_hub == NULL) 1402 return (USB_ERR_INVAL); 1403 1404 index = udev->controller_slot_id; 1405 1406 hdev = &sc->sc_hw.devs[index]; 1407 1408 if (mtx != NULL) 1409 mtx_unlock(mtx); 1410 1411 XHCI_CMD_LOCK(sc); 1412 1413 switch (hdev->state) { 1414 case XHCI_ST_DEFAULT: 1415 case XHCI_ST_ENABLED: 1416 1417 hdev->state = XHCI_ST_ENABLED; 1418 1419 /* set configure mask to slot and EP0 */ 1420 xhci_configure_mask(udev, 3, 0); 1421 1422 /* configure input slot context structure */ 1423 err = xhci_configure_device(udev); 1424 1425 if (err != 0) { 1426 DPRINTF("Could not configure device\n"); 1427 break; 1428 } 1429 1430 /* configure input endpoint context structure */ 1431 switch (udev->speed) { 1432 case USB_SPEED_LOW: 1433 case USB_SPEED_FULL: 1434 mps = 8; 1435 break; 1436 case USB_SPEED_HIGH: 1437 mps = 64; 1438 break; 1439 default: 1440 mps = 512; 1441 break; 1442 } 1443 1444 pepext = xhci_get_endpoint_ext(udev, 1445 &udev->ctrl_ep_desc); 1446 1447 /* ensure the control endpoint is setup again */ 1448 USB_BUS_LOCK(udev->bus); 1449 pepext->trb_halted = 1; 1450 pepext->trb_running = 0; 1451 USB_BUS_UNLOCK(udev->bus); 1452 1453 err = xhci_configure_endpoint(udev, 1454 &udev->ctrl_ep_desc, pepext, 1455 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1456 1457 if (err != 0) { 1458 DPRINTF("Could not configure default endpoint\n"); 1459 break; 1460 } 1461 1462 /* execute set address command */ 1463 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1464 1465 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1466 (address == 0), index); 1467 1468 if (err != 0) { 1469 temp = le32toh(sc->sc_cmd_result[0]); 1470 if (address == 0 && sc->sc_port_route != NULL && 1471 XHCI_TRB_2_ERROR_GET(temp) == 1472 XHCI_TRB_ERROR_PARAMETER) { 1473 /* LynxPoint XHCI - ports are not switchable */ 1474 /* Un-route all ports from the XHCI */ 1475 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1476 } 1477 DPRINTF("Could not set address " 1478 "for slot %u.\n", index); 1479 if (address != 0) 1480 break; 1481 } 1482 1483 /* update device address to new value */ 1484 1485 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1486 pdev = buf_dev.buffer; 1487 usb_pc_cpu_invalidate(&hdev->device_pc); 1488 1489 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1490 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1491 1492 /* update device state to new value */ 1493 1494 if (address != 0) 1495 hdev->state = XHCI_ST_ADDRESSED; 1496 else 1497 hdev->state = XHCI_ST_DEFAULT; 1498 break; 1499 1500 default: 1501 DPRINTF("Wrong state for set address.\n"); 1502 err = USB_ERR_IOERROR; 1503 break; 1504 } 1505 XHCI_CMD_UNLOCK(sc); 1506 1507 if (mtx != NULL) 1508 mtx_lock(mtx); 1509 1510 return (err); 1511 } 1512 1513 static usb_error_t 1514 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1515 uint8_t deconfigure, uint8_t slot_id) 1516 { 1517 struct xhci_trb trb; 1518 uint32_t temp; 1519 1520 DPRINTF("\n"); 1521 1522 trb.qwTrb0 = htole64(input_ctx); 1523 trb.dwTrb2 = 0; 1524 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1525 XHCI_TRB_3_SLOT_SET(slot_id); 1526 1527 if (deconfigure) 1528 temp |= XHCI_TRB_3_DCEP_BIT; 1529 1530 trb.dwTrb3 = htole32(temp); 1531 1532 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1533 } 1534 1535 static usb_error_t 1536 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1537 uint8_t slot_id) 1538 { 1539 struct xhci_trb trb; 1540 uint32_t temp; 1541 1542 DPRINTF("\n"); 1543 1544 trb.qwTrb0 = htole64(input_ctx); 1545 trb.dwTrb2 = 0; 1546 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1547 XHCI_TRB_3_SLOT_SET(slot_id); 1548 trb.dwTrb3 = htole32(temp); 1549 1550 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1551 } 1552 1553 static usb_error_t 1554 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1555 uint8_t ep_id, uint8_t slot_id) 1556 { 1557 struct xhci_trb trb; 1558 uint32_t temp; 1559 1560 DPRINTF("\n"); 1561 1562 trb.qwTrb0 = 0; 1563 trb.dwTrb2 = 0; 1564 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1565 XHCI_TRB_3_SLOT_SET(slot_id) | 1566 XHCI_TRB_3_EP_SET(ep_id); 1567 1568 if (preserve) 1569 temp |= XHCI_TRB_3_PRSV_BIT; 1570 1571 trb.dwTrb3 = htole32(temp); 1572 1573 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1574 } 1575 1576 static usb_error_t 1577 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1578 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1579 { 1580 struct xhci_trb trb; 1581 uint32_t temp; 1582 1583 DPRINTF("\n"); 1584 1585 trb.qwTrb0 = htole64(dequeue_ptr); 1586 1587 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1588 trb.dwTrb2 = htole32(temp); 1589 1590 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1591 XHCI_TRB_3_SLOT_SET(slot_id) | 1592 XHCI_TRB_3_EP_SET(ep_id); 1593 trb.dwTrb3 = htole32(temp); 1594 1595 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1596 } 1597 1598 static usb_error_t 1599 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1600 uint8_t ep_id, uint8_t slot_id) 1601 { 1602 struct xhci_trb trb; 1603 uint32_t temp; 1604 1605 DPRINTF("\n"); 1606 1607 trb.qwTrb0 = 0; 1608 trb.dwTrb2 = 0; 1609 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1610 XHCI_TRB_3_SLOT_SET(slot_id) | 1611 XHCI_TRB_3_EP_SET(ep_id); 1612 1613 if (suspend) 1614 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1615 1616 trb.dwTrb3 = htole32(temp); 1617 1618 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1619 } 1620 1621 static usb_error_t 1622 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1623 { 1624 struct xhci_trb trb; 1625 uint32_t temp; 1626 1627 DPRINTF("\n"); 1628 1629 trb.qwTrb0 = 0; 1630 trb.dwTrb2 = 0; 1631 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1632 XHCI_TRB_3_SLOT_SET(slot_id); 1633 1634 trb.dwTrb3 = htole32(temp); 1635 1636 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1637 } 1638 1639 /*------------------------------------------------------------------------* 1640 * xhci_interrupt - XHCI interrupt handler 1641 *------------------------------------------------------------------------*/ 1642 void 1643 xhci_interrupt(struct xhci_softc *sc) 1644 { 1645 uint32_t status; 1646 uint32_t temp; 1647 1648 USB_BUS_LOCK(&sc->sc_bus); 1649 1650 status = XREAD4(sc, oper, XHCI_USBSTS); 1651 1652 /* acknowledge interrupts, if any */ 1653 if (status != 0) { 1654 XWRITE4(sc, oper, XHCI_USBSTS, status); 1655 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1656 } 1657 1658 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1659 1660 /* force clearing of pending interrupts */ 1661 if (temp & XHCI_IMAN_INTR_PEND) 1662 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1663 1664 /* check for event(s) */ 1665 xhci_interrupt_poll(sc); 1666 1667 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1668 XHCI_STS_HSE | XHCI_STS_HCE)) { 1669 1670 if (status & XHCI_STS_PCD) { 1671 xhci_root_intr(sc); 1672 } 1673 1674 if (status & XHCI_STS_HCH) { 1675 printf("%s: host controller halted\n", 1676 __FUNCTION__); 1677 } 1678 1679 if (status & XHCI_STS_HSE) { 1680 printf("%s: host system error\n", 1681 __FUNCTION__); 1682 } 1683 1684 if (status & XHCI_STS_HCE) { 1685 printf("%s: host controller error\n", 1686 __FUNCTION__); 1687 } 1688 } 1689 USB_BUS_UNLOCK(&sc->sc_bus); 1690 } 1691 1692 /*------------------------------------------------------------------------* 1693 * xhci_timeout - XHCI timeout handler 1694 *------------------------------------------------------------------------*/ 1695 static void 1696 xhci_timeout(void *arg) 1697 { 1698 struct usb_xfer *xfer = arg; 1699 1700 DPRINTF("xfer=%p\n", xfer); 1701 1702 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1703 1704 /* transfer is transferred */ 1705 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1706 } 1707 1708 static void 1709 xhci_do_poll(struct usb_bus *bus) 1710 { 1711 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1712 1713 USB_BUS_LOCK(&sc->sc_bus); 1714 xhci_interrupt_poll(sc); 1715 USB_BUS_UNLOCK(&sc->sc_bus); 1716 } 1717 1718 static void 1719 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1720 { 1721 struct usb_page_search buf_res; 1722 struct xhci_td *td; 1723 struct xhci_td *td_next; 1724 struct xhci_td *td_alt_next; 1725 struct xhci_td *td_first; 1726 uint32_t buf_offset; 1727 uint32_t average; 1728 uint32_t len_old; 1729 uint32_t npkt_off; 1730 uint32_t dword; 1731 uint8_t shortpkt_old; 1732 uint8_t precompute; 1733 uint8_t x; 1734 1735 td_alt_next = NULL; 1736 buf_offset = 0; 1737 shortpkt_old = temp->shortpkt; 1738 len_old = temp->len; 1739 npkt_off = 0; 1740 precompute = 1; 1741 1742 restart: 1743 1744 td = temp->td; 1745 td_next = td_first = temp->td_next; 1746 1747 while (1) { 1748 1749 if (temp->len == 0) { 1750 1751 if (temp->shortpkt) 1752 break; 1753 1754 /* send a Zero Length Packet, ZLP, last */ 1755 1756 temp->shortpkt = 1; 1757 average = 0; 1758 1759 } else { 1760 1761 average = temp->average; 1762 1763 if (temp->len < average) { 1764 if (temp->len % temp->max_packet_size) { 1765 temp->shortpkt = 1; 1766 } 1767 average = temp->len; 1768 } 1769 } 1770 1771 if (td_next == NULL) 1772 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1773 1774 /* get next TD */ 1775 1776 td = td_next; 1777 td_next = td->obj_next; 1778 1779 /* check if we are pre-computing */ 1780 1781 if (precompute) { 1782 1783 /* update remaining length */ 1784 1785 temp->len -= average; 1786 1787 continue; 1788 } 1789 /* fill out current TD */ 1790 1791 td->len = average; 1792 td->remainder = 0; 1793 td->status = 0; 1794 1795 /* update remaining length */ 1796 1797 temp->len -= average; 1798 1799 /* reset TRB index */ 1800 1801 x = 0; 1802 1803 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1804 /* immediate data */ 1805 1806 if (average > 8) 1807 average = 8; 1808 1809 td->td_trb[0].qwTrb0 = 0; 1810 1811 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1812 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1813 average); 1814 1815 dword = XHCI_TRB_2_BYTES_SET(8) | 1816 XHCI_TRB_2_TDSZ_SET(0) | 1817 XHCI_TRB_2_IRQ_SET(0); 1818 1819 td->td_trb[0].dwTrb2 = htole32(dword); 1820 1821 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1822 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1823 1824 /* check wLength */ 1825 if (td->td_trb[0].qwTrb0 & 1826 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1827 if (td->td_trb[0].qwTrb0 & 1828 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1829 dword |= XHCI_TRB_3_TRT_IN; 1830 else 1831 dword |= XHCI_TRB_3_TRT_OUT; 1832 } 1833 1834 td->td_trb[0].dwTrb3 = htole32(dword); 1835 #ifdef USB_DEBUG 1836 xhci_dump_trb(&td->td_trb[x]); 1837 #endif 1838 x++; 1839 1840 } else do { 1841 1842 uint32_t npkt; 1843 1844 /* fill out buffer pointers */ 1845 1846 if (average == 0) { 1847 memset(&buf_res, 0, sizeof(buf_res)); 1848 } else { 1849 usbd_get_page(temp->pc, temp->offset + 1850 buf_offset, &buf_res); 1851 1852 /* get length to end of page */ 1853 if (buf_res.length > average) 1854 buf_res.length = average; 1855 1856 /* check for maximum length */ 1857 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1858 buf_res.length = XHCI_TD_PAGE_SIZE; 1859 1860 npkt_off += buf_res.length; 1861 } 1862 1863 /* set up npkt */ 1864 npkt = howmany(len_old - npkt_off, 1865 temp->max_packet_size); 1866 1867 if (npkt == 0) 1868 npkt = 1; 1869 else if (npkt > 31) 1870 npkt = 31; 1871 1872 /* fill out TRB's */ 1873 td->td_trb[x].qwTrb0 = 1874 htole64((uint64_t)buf_res.physaddr); 1875 1876 dword = 1877 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1878 XHCI_TRB_2_TDSZ_SET(npkt) | 1879 XHCI_TRB_2_IRQ_SET(0); 1880 1881 td->td_trb[x].dwTrb2 = htole32(dword); 1882 1883 switch (temp->trb_type) { 1884 case XHCI_TRB_TYPE_ISOCH: 1885 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1886 XHCI_TRB_3_TBC_SET(temp->tbc) | 1887 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1888 if (td != td_first) { 1889 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1890 } else if (temp->do_isoc_sync != 0) { 1891 temp->do_isoc_sync = 0; 1892 /* wait until "isoc_frame" */ 1893 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1894 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1895 } else { 1896 /* start data transfer at next interval */ 1897 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1898 XHCI_TRB_3_ISO_SIA_BIT; 1899 } 1900 if (temp->direction == UE_DIR_IN) 1901 dword |= XHCI_TRB_3_ISP_BIT; 1902 break; 1903 case XHCI_TRB_TYPE_DATA_STAGE: 1904 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1905 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1906 if (temp->direction == UE_DIR_IN) 1907 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1908 /* 1909 * Section 3.2.9 in the XHCI 1910 * specification about control 1911 * transfers says that we should use a 1912 * normal-TRB if there are more TRBs 1913 * extending the data-stage 1914 * TRB. Update the "trb_type". 1915 */ 1916 temp->trb_type = XHCI_TRB_TYPE_NORMAL; 1917 break; 1918 case XHCI_TRB_TYPE_STATUS_STAGE: 1919 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1920 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1921 if (temp->direction == UE_DIR_IN) 1922 dword |= XHCI_TRB_3_DIR_IN; 1923 break; 1924 default: /* XHCI_TRB_TYPE_NORMAL */ 1925 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1926 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1927 if (temp->direction == UE_DIR_IN) 1928 dword |= XHCI_TRB_3_ISP_BIT; 1929 break; 1930 } 1931 td->td_trb[x].dwTrb3 = htole32(dword); 1932 1933 average -= buf_res.length; 1934 buf_offset += buf_res.length; 1935 #ifdef USB_DEBUG 1936 xhci_dump_trb(&td->td_trb[x]); 1937 #endif 1938 x++; 1939 1940 } while (average != 0); 1941 1942 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1943 1944 /* store number of data TRB's */ 1945 1946 td->ntrb = x; 1947 1948 DPRINTF("NTRB=%u\n", x); 1949 1950 /* fill out link TRB */ 1951 1952 if (td_next != NULL) { 1953 /* link the current TD with the next one */ 1954 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1955 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1956 } else { 1957 /* this field will get updated later */ 1958 DPRINTF("NOLINK\n"); 1959 } 1960 1961 dword = XHCI_TRB_2_IRQ_SET(0); 1962 1963 td->td_trb[x].dwTrb2 = htole32(dword); 1964 1965 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1966 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1967 /* 1968 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1969 * frame only receives a single short packet event 1970 * by setting the CHAIN bit in the LINK field. In 1971 * addition some XHCI controllers have problems 1972 * sending a ZLP unless the CHAIN-BIT is set in 1973 * the LINK TRB. 1974 */ 1975 XHCI_TRB_3_CHAIN_BIT; 1976 1977 td->td_trb[x].dwTrb3 = htole32(dword); 1978 1979 td->alt_next = td_alt_next; 1980 #ifdef USB_DEBUG 1981 xhci_dump_trb(&td->td_trb[x]); 1982 #endif 1983 usb_pc_cpu_flush(td->page_cache); 1984 } 1985 1986 if (precompute) { 1987 precompute = 0; 1988 1989 /* set up alt next pointer, if any */ 1990 if (temp->last_frame) { 1991 td_alt_next = NULL; 1992 } else { 1993 /* we use this field internally */ 1994 td_alt_next = td_next; 1995 } 1996 1997 /* restore */ 1998 temp->shortpkt = shortpkt_old; 1999 temp->len = len_old; 2000 goto restart; 2001 } 2002 2003 /* 2004 * Remove cycle bit from the first TRB if we are 2005 * stepping them: 2006 */ 2007 if (temp->step_td != 0) { 2008 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2009 usb_pc_cpu_flush(td_first->page_cache); 2010 } 2011 2012 /* clear TD SIZE to zero, hence this is the last TRB */ 2013 /* remove chain bit because this is the last data TRB in the chain */ 2014 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31)); 2015 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 2016 /* remove CHAIN-BIT from last LINK TRB */ 2017 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 2018 2019 usb_pc_cpu_flush(td->page_cache); 2020 2021 temp->td = td; 2022 temp->td_next = td_next; 2023 } 2024 2025 static void 2026 xhci_setup_generic_chain(struct usb_xfer *xfer) 2027 { 2028 struct xhci_std_temp temp; 2029 struct xhci_td *td; 2030 uint32_t x; 2031 uint32_t y; 2032 uint8_t mult; 2033 2034 temp.do_isoc_sync = 0; 2035 temp.step_td = 0; 2036 temp.tbc = 0; 2037 temp.tlbpc = 0; 2038 temp.average = xfer->max_hc_frame_size; 2039 temp.max_packet_size = xfer->max_packet_size; 2040 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 2041 temp.pc = NULL; 2042 temp.last_frame = 0; 2043 temp.offset = 0; 2044 temp.multishort = xfer->flags_int.isochronous_xfr || 2045 xfer->flags_int.control_xfr || 2046 xfer->flags_int.short_frames_ok; 2047 2048 /* toggle the DMA set we are using */ 2049 xfer->flags_int.curr_dma_set ^= 1; 2050 2051 /* get next DMA set */ 2052 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2053 2054 temp.td = NULL; 2055 temp.td_next = td; 2056 2057 xfer->td_transfer_first = td; 2058 xfer->td_transfer_cache = td; 2059 2060 if (xfer->flags_int.isochronous_xfr) { 2061 uint8_t shift; 2062 2063 /* compute multiplier for ISOCHRONOUS transfers */ 2064 mult = xfer->endpoint->ecomp ? 2065 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2066 : 0; 2067 /* check for USB 2.0 multiplier */ 2068 if (mult == 0) { 2069 mult = (xfer->endpoint->edesc-> 2070 wMaxPacketSize[1] >> 3) & 3; 2071 } 2072 /* range check */ 2073 if (mult > 2) 2074 mult = 3; 2075 else 2076 mult++; 2077 2078 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2079 2080 DPRINTF("MFINDEX=0x%08x\n", x); 2081 2082 switch (usbd_get_speed(xfer->xroot->udev)) { 2083 case USB_SPEED_FULL: 2084 shift = 3; 2085 temp.isoc_delta = 8; /* 1ms */ 2086 x += temp.isoc_delta - 1; 2087 x &= ~(temp.isoc_delta - 1); 2088 break; 2089 default: 2090 shift = usbd_xfer_get_fps_shift(xfer); 2091 temp.isoc_delta = 1U << shift; 2092 x += temp.isoc_delta - 1; 2093 x &= ~(temp.isoc_delta - 1); 2094 /* simple frame load balancing */ 2095 x += xfer->endpoint->usb_uframe; 2096 break; 2097 } 2098 2099 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2100 2101 if ((xfer->endpoint->is_synced == 0) || 2102 (y < (xfer->nframes << shift)) || 2103 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2104 /* 2105 * If there is data underflow or the pipe 2106 * queue is empty we schedule the transfer a 2107 * few frames ahead of the current frame 2108 * position. Else two isochronous transfers 2109 * might overlap. 2110 */ 2111 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2112 xfer->endpoint->is_synced = 1; 2113 temp.do_isoc_sync = 1; 2114 2115 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2116 } 2117 2118 /* compute isochronous completion time */ 2119 2120 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2121 2122 xfer->isoc_time_complete = 2123 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2124 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2125 2126 x = 0; 2127 temp.isoc_frame = xfer->endpoint->isoc_next; 2128 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2129 2130 xfer->endpoint->isoc_next += xfer->nframes << shift; 2131 2132 } else if (xfer->flags_int.control_xfr) { 2133 2134 /* check if we should prepend a setup message */ 2135 2136 if (xfer->flags_int.control_hdr) { 2137 2138 temp.len = xfer->frlengths[0]; 2139 temp.pc = xfer->frbuffers + 0; 2140 temp.shortpkt = temp.len ? 1 : 0; 2141 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2142 temp.direction = 0; 2143 2144 /* check for last frame */ 2145 if (xfer->nframes == 1) { 2146 /* no STATUS stage yet, SETUP is last */ 2147 if (xfer->flags_int.control_act) 2148 temp.last_frame = 1; 2149 } 2150 2151 xhci_setup_generic_chain_sub(&temp); 2152 } 2153 x = 1; 2154 mult = 1; 2155 temp.isoc_delta = 0; 2156 temp.isoc_frame = 0; 2157 temp.trb_type = xfer->flags_int.control_did_data ? 2158 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE; 2159 } else { 2160 x = 0; 2161 mult = 1; 2162 temp.isoc_delta = 0; 2163 temp.isoc_frame = 0; 2164 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2165 } 2166 2167 if (x != xfer->nframes) { 2168 /* set up page_cache pointer */ 2169 temp.pc = xfer->frbuffers + x; 2170 /* set endpoint direction */ 2171 temp.direction = UE_GET_DIR(xfer->endpointno); 2172 } 2173 2174 while (x != xfer->nframes) { 2175 2176 /* DATA0 / DATA1 message */ 2177 2178 temp.len = xfer->frlengths[x]; 2179 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2180 x != 0 && temp.multishort == 0); 2181 2182 x++; 2183 2184 if (x == xfer->nframes) { 2185 if (xfer->flags_int.control_xfr) { 2186 /* no STATUS stage yet, DATA is last */ 2187 if (xfer->flags_int.control_act) 2188 temp.last_frame = 1; 2189 } else { 2190 temp.last_frame = 1; 2191 } 2192 } 2193 if (temp.len == 0) { 2194 2195 /* make sure that we send an USB packet */ 2196 2197 temp.shortpkt = 0; 2198 2199 temp.tbc = 0; 2200 temp.tlbpc = mult - 1; 2201 2202 } else if (xfer->flags_int.isochronous_xfr) { 2203 2204 uint8_t tdpc; 2205 2206 /* 2207 * Isochronous transfers don't have short 2208 * packet termination: 2209 */ 2210 2211 temp.shortpkt = 1; 2212 2213 /* isochronous transfers have a transfer limit */ 2214 2215 if (temp.len > xfer->max_frame_size) 2216 temp.len = xfer->max_frame_size; 2217 2218 /* compute TD packet count */ 2219 tdpc = howmany(temp.len, xfer->max_packet_size); 2220 2221 temp.tbc = howmany(tdpc, mult) - 1; 2222 temp.tlbpc = (tdpc % mult); 2223 2224 if (temp.tlbpc == 0) 2225 temp.tlbpc = mult - 1; 2226 else 2227 temp.tlbpc--; 2228 } else { 2229 2230 /* regular data transfer */ 2231 2232 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2233 } 2234 2235 xhci_setup_generic_chain_sub(&temp); 2236 2237 if (xfer->flags_int.isochronous_xfr) { 2238 temp.offset += xfer->frlengths[x - 1]; 2239 temp.isoc_frame += temp.isoc_delta; 2240 } else { 2241 /* get next Page Cache pointer */ 2242 temp.pc = xfer->frbuffers + x; 2243 } 2244 } 2245 2246 /* check if we should append a status stage */ 2247 2248 if (xfer->flags_int.control_xfr && 2249 !xfer->flags_int.control_act) { 2250 2251 /* 2252 * Send a DATA1 message and invert the current 2253 * endpoint direction. 2254 */ 2255 if (xhcictlstep || temp.sc->sc_ctlstep) { 2256 /* 2257 * Some XHCI controllers will not delay the 2258 * status stage until the next SOF. Force this 2259 * behaviour to avoid failed control 2260 * transfers. 2261 */ 2262 temp.step_td = (xfer->nframes != 0); 2263 } else { 2264 temp.step_td = 0; 2265 } 2266 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2267 temp.len = 0; 2268 temp.pc = NULL; 2269 temp.shortpkt = 0; 2270 temp.last_frame = 1; 2271 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2272 2273 xhci_setup_generic_chain_sub(&temp); 2274 } 2275 2276 td = temp.td; 2277 2278 /* must have at least one frame! */ 2279 2280 xfer->td_transfer_last = td; 2281 2282 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2283 } 2284 2285 static void 2286 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2287 { 2288 struct usb_page_search buf_res; 2289 struct xhci_dev_ctx_addr *pdctxa; 2290 2291 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2292 2293 pdctxa = buf_res.buffer; 2294 2295 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2296 2297 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2298 2299 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2300 } 2301 2302 static usb_error_t 2303 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2304 { 2305 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2306 struct usb_page_search buf_inp; 2307 struct xhci_input_dev_ctx *pinp; 2308 uint32_t temp; 2309 uint8_t index; 2310 uint8_t x; 2311 2312 index = udev->controller_slot_id; 2313 2314 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2315 2316 pinp = buf_inp.buffer; 2317 2318 if (drop) { 2319 mask &= XHCI_INCTX_NON_CTRL_MASK; 2320 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2321 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2322 } else { 2323 /* 2324 * Some hardware requires that we drop the endpoint 2325 * context before adding it again: 2326 */ 2327 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 2328 mask & XHCI_INCTX_NON_CTRL_MASK); 2329 2330 /* Add new endpoint context */ 2331 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2332 2333 /* find most significant set bit */ 2334 for (x = 31; x != 1; x--) { 2335 if (mask & (1 << x)) 2336 break; 2337 } 2338 2339 /* adjust */ 2340 x--; 2341 2342 /* figure out the maximum number of contexts */ 2343 if (x > sc->sc_hw.devs[index].context_num) 2344 sc->sc_hw.devs[index].context_num = x; 2345 else 2346 x = sc->sc_hw.devs[index].context_num; 2347 2348 /* update number of contexts */ 2349 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2350 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2351 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2352 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2353 } 2354 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2355 return (0); 2356 } 2357 2358 static usb_error_t 2359 xhci_configure_endpoint(struct usb_device *udev, 2360 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2361 uint16_t interval, uint8_t max_packet_count, 2362 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2363 uint16_t max_frame_size, uint8_t ep_mode) 2364 { 2365 struct usb_page_search buf_inp; 2366 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2367 struct xhci_input_dev_ctx *pinp; 2368 uint64_t ring_addr = pepext->physaddr; 2369 uint32_t temp; 2370 uint8_t index; 2371 uint8_t epno; 2372 uint8_t type; 2373 2374 index = udev->controller_slot_id; 2375 2376 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2377 2378 pinp = buf_inp.buffer; 2379 2380 epno = edesc->bEndpointAddress; 2381 type = edesc->bmAttributes & UE_XFERTYPE; 2382 2383 if (type == UE_CONTROL) 2384 epno |= UE_DIR_IN; 2385 2386 epno = XHCI_EPNO2EPID(epno); 2387 2388 if (epno == 0) 2389 return (USB_ERR_NO_PIPE); /* invalid */ 2390 2391 if (max_packet_count == 0) 2392 return (USB_ERR_BAD_BUFSIZE); 2393 2394 max_packet_count--; 2395 2396 if (mult == 0) 2397 return (USB_ERR_BAD_BUFSIZE); 2398 2399 /* store endpoint mode */ 2400 pepext->trb_ep_mode = ep_mode; 2401 /* store bMaxPacketSize for control endpoints */ 2402 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0]; 2403 usb_pc_cpu_flush(pepext->page_cache); 2404 2405 if (ep_mode == USB_EP_MODE_STREAMS) { 2406 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2407 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2408 XHCI_EPCTX_0_LSA_SET(1); 2409 2410 ring_addr += sizeof(struct xhci_trb) * 2411 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2412 } else { 2413 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2414 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2415 XHCI_EPCTX_0_LSA_SET(0); 2416 2417 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2418 } 2419 2420 switch (udev->speed) { 2421 case USB_SPEED_FULL: 2422 case USB_SPEED_LOW: 2423 /* 1ms -> 125us */ 2424 fps_shift += 3; 2425 break; 2426 default: 2427 break; 2428 } 2429 2430 switch (type) { 2431 case UE_INTERRUPT: 2432 if (fps_shift > 3) 2433 fps_shift--; 2434 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2435 break; 2436 case UE_ISOCHRONOUS: 2437 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2438 2439 switch (udev->speed) { 2440 case USB_SPEED_SUPER: 2441 if (mult > 3) 2442 mult = 3; 2443 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2444 max_packet_count /= mult; 2445 break; 2446 default: 2447 break; 2448 } 2449 break; 2450 default: 2451 break; 2452 } 2453 2454 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2455 2456 temp = 2457 XHCI_EPCTX_1_HID_SET(0) | 2458 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2459 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2460 2461 /* 2462 * Always enable the "three strikes and you are gone" feature 2463 * except for ISOCHRONOUS endpoints. This is suggested by 2464 * section 4.3.3 in the XHCI specification about device slot 2465 * initialisation. 2466 */ 2467 if (type != UE_ISOCHRONOUS) 2468 temp |= XHCI_EPCTX_1_CERR_SET(3); 2469 2470 switch (type) { 2471 case UE_CONTROL: 2472 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2473 break; 2474 case UE_ISOCHRONOUS: 2475 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2476 break; 2477 case UE_BULK: 2478 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2479 break; 2480 default: 2481 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2482 break; 2483 } 2484 2485 /* check for IN direction */ 2486 if (epno & 1) 2487 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2488 2489 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2490 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2491 2492 switch (edesc->bmAttributes & UE_XFERTYPE) { 2493 case UE_INTERRUPT: 2494 case UE_ISOCHRONOUS: 2495 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2496 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2497 max_frame_size)); 2498 break; 2499 case UE_CONTROL: 2500 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2501 break; 2502 default: 2503 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2504 break; 2505 } 2506 2507 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2508 2509 #ifdef USB_DEBUG 2510 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2511 #endif 2512 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2513 2514 return (0); /* success */ 2515 } 2516 2517 static usb_error_t 2518 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2519 { 2520 struct xhci_endpoint_ext *pepext; 2521 struct usb_endpoint_ss_comp_descriptor *ecomp; 2522 usb_stream_t x; 2523 2524 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2525 xfer->endpoint->edesc); 2526 2527 ecomp = xfer->endpoint->ecomp; 2528 2529 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2530 uint64_t temp; 2531 2532 /* halt any transfers */ 2533 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2534 2535 /* compute start of TRB ring for stream "x" */ 2536 temp = pepext->physaddr + 2537 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2538 XHCI_SCTX_0_SCT_SEC_TR_RING; 2539 2540 /* make tree structure */ 2541 pepext->trb[(XHCI_MAX_TRANSFERS * 2542 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2543 2544 /* reserved fields */ 2545 pepext->trb[(XHCI_MAX_TRANSFERS * 2546 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2547 pepext->trb[(XHCI_MAX_TRANSFERS * 2548 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2549 } 2550 usb_pc_cpu_flush(pepext->page_cache); 2551 2552 return (xhci_configure_endpoint(xfer->xroot->udev, 2553 xfer->endpoint->edesc, pepext, 2554 xfer->interval, xfer->max_packet_count, 2555 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2556 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2557 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2558 } 2559 2560 static usb_error_t 2561 xhci_configure_device(struct usb_device *udev) 2562 { 2563 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2564 struct usb_page_search buf_inp; 2565 struct usb_page_cache *pcinp; 2566 struct xhci_input_dev_ctx *pinp; 2567 struct usb_device *hubdev; 2568 uint32_t temp; 2569 uint32_t route; 2570 uint32_t rh_port; 2571 uint8_t is_hub; 2572 uint8_t index; 2573 uint8_t depth; 2574 2575 index = udev->controller_slot_id; 2576 2577 DPRINTF("index=%u\n", index); 2578 2579 pcinp = &sc->sc_hw.devs[index].input_pc; 2580 2581 usbd_get_page(pcinp, 0, &buf_inp); 2582 2583 pinp = buf_inp.buffer; 2584 2585 rh_port = 0; 2586 route = 0; 2587 2588 /* figure out route string and root HUB port number */ 2589 2590 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2591 2592 if (hubdev->parent_hub == NULL) 2593 break; 2594 2595 depth = hubdev->parent_hub->depth; 2596 2597 /* 2598 * NOTE: HS/FS/LS devices and the SS root HUB can have 2599 * more than 15 ports 2600 */ 2601 2602 rh_port = hubdev->port_no; 2603 2604 if (depth == 0) 2605 break; 2606 2607 if (rh_port > 15) 2608 rh_port = 15; 2609 2610 if (depth < 6) 2611 route |= rh_port << (4 * (depth - 1)); 2612 } 2613 2614 DPRINTF("Route=0x%08x\n", route); 2615 2616 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2617 XHCI_SCTX_0_CTX_NUM_SET( 2618 sc->sc_hw.devs[index].context_num + 1); 2619 2620 switch (udev->speed) { 2621 case USB_SPEED_LOW: 2622 temp |= XHCI_SCTX_0_SPEED_SET(2); 2623 if (udev->parent_hs_hub != NULL && 2624 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2625 UDPROTO_HSHUBMTT) { 2626 DPRINTF("Device inherits MTT\n"); 2627 temp |= XHCI_SCTX_0_MTT_SET(1); 2628 } 2629 break; 2630 case USB_SPEED_HIGH: 2631 temp |= XHCI_SCTX_0_SPEED_SET(3); 2632 if (sc->sc_hw.devs[index].nports != 0 && 2633 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2634 DPRINTF("HUB supports MTT\n"); 2635 temp |= XHCI_SCTX_0_MTT_SET(1); 2636 } 2637 break; 2638 case USB_SPEED_FULL: 2639 temp |= XHCI_SCTX_0_SPEED_SET(1); 2640 if (udev->parent_hs_hub != NULL && 2641 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2642 UDPROTO_HSHUBMTT) { 2643 DPRINTF("Device inherits MTT\n"); 2644 temp |= XHCI_SCTX_0_MTT_SET(1); 2645 } 2646 break; 2647 default: 2648 temp |= XHCI_SCTX_0_SPEED_SET(4); 2649 break; 2650 } 2651 2652 is_hub = sc->sc_hw.devs[index].nports != 0 && 2653 (udev->speed == USB_SPEED_SUPER || 2654 udev->speed == USB_SPEED_HIGH); 2655 2656 if (is_hub) 2657 temp |= XHCI_SCTX_0_HUB_SET(1); 2658 2659 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2660 2661 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2662 2663 if (is_hub) { 2664 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2665 sc->sc_hw.devs[index].nports); 2666 } 2667 2668 switch (udev->speed) { 2669 case USB_SPEED_SUPER: 2670 switch (sc->sc_hw.devs[index].state) { 2671 case XHCI_ST_ADDRESSED: 2672 case XHCI_ST_CONFIGURED: 2673 /* enable power save */ 2674 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2675 break; 2676 default: 2677 /* disable power save */ 2678 break; 2679 } 2680 break; 2681 default: 2682 break; 2683 } 2684 2685 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2686 2687 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2688 2689 if (is_hub) { 2690 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2691 sc->sc_hw.devs[index].tt); 2692 } 2693 2694 hubdev = udev->parent_hs_hub; 2695 2696 /* check if we should activate the transaction translator */ 2697 switch (udev->speed) { 2698 case USB_SPEED_FULL: 2699 case USB_SPEED_LOW: 2700 if (hubdev != NULL) { 2701 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2702 hubdev->controller_slot_id); 2703 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2704 udev->hs_port_no); 2705 } 2706 break; 2707 default: 2708 break; 2709 } 2710 2711 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2712 2713 /* 2714 * These fields should be initialized to zero, according to 2715 * XHCI section 6.2.2 - slot context: 2716 */ 2717 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2718 XHCI_SCTX_3_SLOT_STATE_SET(0); 2719 2720 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2721 2722 #ifdef USB_DEBUG 2723 xhci_dump_device(sc, &pinp->ctx_slot); 2724 #endif 2725 usb_pc_cpu_flush(pcinp); 2726 2727 return (0); /* success */ 2728 } 2729 2730 static usb_error_t 2731 xhci_alloc_device_ext(struct usb_device *udev) 2732 { 2733 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2734 struct usb_page_search buf_dev; 2735 struct usb_page_search buf_ep; 2736 struct xhci_trb *trb; 2737 struct usb_page_cache *pc; 2738 struct usb_page *pg; 2739 uint64_t addr; 2740 uint8_t index; 2741 uint8_t i; 2742 2743 index = udev->controller_slot_id; 2744 2745 pc = &sc->sc_hw.devs[index].device_pc; 2746 pg = &sc->sc_hw.devs[index].device_pg; 2747 2748 /* need to initialize the page cache */ 2749 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2750 2751 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2752 (2 * sizeof(struct xhci_dev_ctx)) : 2753 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2754 goto error; 2755 2756 usbd_get_page(pc, 0, &buf_dev); 2757 2758 pc = &sc->sc_hw.devs[index].input_pc; 2759 pg = &sc->sc_hw.devs[index].input_pg; 2760 2761 /* need to initialize the page cache */ 2762 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2763 2764 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2765 (2 * sizeof(struct xhci_input_dev_ctx)) : 2766 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2767 goto error; 2768 } 2769 2770 /* initialize all endpoint LINK TRBs */ 2771 2772 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2773 2774 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2775 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2776 2777 /* need to initialize the page cache */ 2778 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2779 2780 if (usb_pc_alloc_mem(pc, pg, 2781 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2782 goto error; 2783 } 2784 2785 /* lookup endpoint TRB ring */ 2786 usbd_get_page(pc, 0, &buf_ep); 2787 2788 /* get TRB pointer */ 2789 trb = buf_ep.buffer; 2790 trb += XHCI_MAX_TRANSFERS - 1; 2791 2792 /* get TRB start address */ 2793 addr = buf_ep.physaddr; 2794 2795 /* create LINK TRB */ 2796 trb->qwTrb0 = htole64(addr); 2797 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2798 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2799 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2800 2801 usb_pc_cpu_flush(pc); 2802 } 2803 2804 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2805 2806 return (0); 2807 2808 error: 2809 xhci_free_device_ext(udev); 2810 2811 return (USB_ERR_NOMEM); 2812 } 2813 2814 static void 2815 xhci_free_device_ext(struct usb_device *udev) 2816 { 2817 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2818 uint8_t index; 2819 uint8_t i; 2820 2821 index = udev->controller_slot_id; 2822 xhci_set_slot_pointer(sc, index, 0); 2823 2824 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2825 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2826 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2827 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2828 } 2829 2830 static struct xhci_endpoint_ext * 2831 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2832 { 2833 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2834 struct xhci_endpoint_ext *pepext; 2835 struct usb_page_cache *pc; 2836 struct usb_page_search buf_ep; 2837 uint8_t epno; 2838 uint8_t index; 2839 2840 epno = edesc->bEndpointAddress; 2841 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2842 epno |= UE_DIR_IN; 2843 2844 epno = XHCI_EPNO2EPID(epno); 2845 2846 index = udev->controller_slot_id; 2847 2848 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2849 2850 usbd_get_page(pc, 0, &buf_ep); 2851 2852 pepext = &sc->sc_hw.devs[index].endp[epno]; 2853 pepext->page_cache = pc; 2854 pepext->trb = buf_ep.buffer; 2855 pepext->physaddr = buf_ep.physaddr; 2856 2857 return (pepext); 2858 } 2859 2860 static void 2861 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2862 { 2863 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2864 uint8_t epno; 2865 uint8_t index; 2866 2867 epno = xfer->endpointno; 2868 if (xfer->flags_int.control_xfr) 2869 epno |= UE_DIR_IN; 2870 2871 epno = XHCI_EPNO2EPID(epno); 2872 index = xfer->xroot->udev->controller_slot_id; 2873 2874 if (xfer->xroot->udev->flags.self_suspended == 0) { 2875 XWRITE4(sc, door, XHCI_DOORBELL(index), 2876 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2877 } 2878 } 2879 2880 static void 2881 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2882 { 2883 struct xhci_endpoint_ext *pepext; 2884 2885 if (xfer->flags_int.bandwidth_reclaimed) { 2886 xfer->flags_int.bandwidth_reclaimed = 0; 2887 2888 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2889 xfer->endpoint->edesc); 2890 2891 pepext->trb_used[xfer->stream_id]--; 2892 2893 pepext->xfer[xfer->qh_pos] = NULL; 2894 2895 if (error && pepext->trb_running != 0) { 2896 pepext->trb_halted = 1; 2897 pepext->trb_running = 0; 2898 } 2899 } 2900 } 2901 2902 static usb_error_t 2903 xhci_transfer_insert(struct usb_xfer *xfer) 2904 { 2905 struct xhci_td *td_first; 2906 struct xhci_td *td_last; 2907 struct xhci_trb *trb_link; 2908 struct xhci_endpoint_ext *pepext; 2909 uint64_t addr; 2910 usb_stream_t id; 2911 uint8_t i; 2912 uint8_t inext; 2913 uint8_t trb_limit; 2914 2915 DPRINTFN(8, "\n"); 2916 2917 id = xfer->stream_id; 2918 2919 /* check if already inserted */ 2920 if (xfer->flags_int.bandwidth_reclaimed) { 2921 DPRINTFN(8, "Already in schedule\n"); 2922 return (0); 2923 } 2924 2925 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2926 xfer->endpoint->edesc); 2927 2928 td_first = xfer->td_transfer_first; 2929 td_last = xfer->td_transfer_last; 2930 addr = pepext->physaddr; 2931 2932 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2933 case UE_CONTROL: 2934 case UE_INTERRUPT: 2935 /* single buffered */ 2936 trb_limit = 1; 2937 break; 2938 default: 2939 /* multi buffered */ 2940 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2941 break; 2942 } 2943 2944 if (pepext->trb_used[id] >= trb_limit) { 2945 DPRINTFN(8, "Too many TDs queued.\n"); 2946 return (USB_ERR_NOMEM); 2947 } 2948 2949 /* check if bMaxPacketSize changed */ 2950 if (xfer->flags_int.control_xfr != 0 && 2951 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) { 2952 2953 DPRINTFN(8, "Reconfigure control endpoint\n"); 2954 2955 /* force driver to reconfigure endpoint */ 2956 pepext->trb_halted = 1; 2957 pepext->trb_running = 0; 2958 } 2959 2960 /* check for stopped condition, after putting transfer on interrupt queue */ 2961 if (pepext->trb_running == 0) { 2962 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2963 2964 DPRINTFN(8, "Not running\n"); 2965 2966 /* start configuration */ 2967 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2968 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2969 return (0); 2970 } 2971 2972 pepext->trb_used[id]++; 2973 2974 /* get current TRB index */ 2975 i = pepext->trb_index[id]; 2976 2977 /* get next TRB index */ 2978 inext = (i + 1); 2979 2980 /* the last entry of the ring is a hardcoded link TRB */ 2981 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2982 inext = 0; 2983 2984 /* store next TRB index, before stream ID offset is added */ 2985 pepext->trb_index[id] = inext; 2986 2987 /* offset for stream */ 2988 i += id * XHCI_MAX_TRANSFERS; 2989 inext += id * XHCI_MAX_TRANSFERS; 2990 2991 /* compute terminating return address */ 2992 addr += (inext * sizeof(struct xhci_trb)); 2993 2994 /* compute link TRB pointer */ 2995 trb_link = td_last->td_trb + td_last->ntrb; 2996 2997 /* update next pointer of last link TRB */ 2998 trb_link->qwTrb0 = htole64(addr); 2999 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 3000 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 3001 XHCI_TRB_3_CYCLE_BIT | 3002 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 3003 3004 #ifdef USB_DEBUG 3005 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 3006 #endif 3007 usb_pc_cpu_flush(td_last->page_cache); 3008 3009 /* write ahead chain end marker */ 3010 3011 pepext->trb[inext].qwTrb0 = 0; 3012 pepext->trb[inext].dwTrb2 = 0; 3013 pepext->trb[inext].dwTrb3 = 0; 3014 3015 /* update next pointer of link TRB */ 3016 3017 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 3018 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 3019 3020 #ifdef USB_DEBUG 3021 xhci_dump_trb(&pepext->trb[i]); 3022 #endif 3023 usb_pc_cpu_flush(pepext->page_cache); 3024 3025 /* toggle cycle bit which activates the transfer chain */ 3026 3027 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 3028 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 3029 3030 usb_pc_cpu_flush(pepext->page_cache); 3031 3032 DPRINTF("qh_pos = %u\n", i); 3033 3034 pepext->xfer[i] = xfer; 3035 3036 xfer->qh_pos = i; 3037 3038 xfer->flags_int.bandwidth_reclaimed = 1; 3039 3040 xhci_endpoint_doorbell(xfer); 3041 3042 return (0); 3043 } 3044 3045 static void 3046 xhci_root_intr(struct xhci_softc *sc) 3047 { 3048 uint16_t i; 3049 3050 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3051 3052 /* clear any old interrupt data */ 3053 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 3054 3055 for (i = 1; i <= sc->sc_noport; i++) { 3056 /* pick out CHANGE bits from the status register */ 3057 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 3058 XHCI_PS_CSC | XHCI_PS_PEC | 3059 XHCI_PS_OCC | XHCI_PS_WRC | 3060 XHCI_PS_PRC | XHCI_PS_PLC | 3061 XHCI_PS_CEC)) { 3062 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 3063 DPRINTF("port %d changed\n", i); 3064 } 3065 } 3066 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3067 sizeof(sc->sc_hub_idata)); 3068 } 3069 3070 /*------------------------------------------------------------------------* 3071 * xhci_device_done - XHCI done handler 3072 * 3073 * NOTE: This function can be called two times in a row on 3074 * the same USB transfer. From close and from interrupt. 3075 *------------------------------------------------------------------------*/ 3076 static void 3077 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 3078 { 3079 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 3080 xfer, xfer->endpoint, error); 3081 3082 /* remove transfer from HW queue */ 3083 xhci_transfer_remove(xfer, error); 3084 3085 /* dequeue transfer and start next transfer */ 3086 usbd_transfer_done(xfer, error); 3087 } 3088 3089 /*------------------------------------------------------------------------* 3090 * XHCI data transfer support (generic type) 3091 *------------------------------------------------------------------------*/ 3092 static void 3093 xhci_device_generic_open(struct usb_xfer *xfer) 3094 { 3095 if (xfer->flags_int.isochronous_xfr) { 3096 switch (xfer->xroot->udev->speed) { 3097 case USB_SPEED_FULL: 3098 break; 3099 default: 3100 usb_hs_bandwidth_alloc(xfer); 3101 break; 3102 } 3103 } 3104 } 3105 3106 static void 3107 xhci_device_generic_close(struct usb_xfer *xfer) 3108 { 3109 DPRINTF("\n"); 3110 3111 xhci_device_done(xfer, USB_ERR_CANCELLED); 3112 3113 if (xfer->flags_int.isochronous_xfr) { 3114 switch (xfer->xroot->udev->speed) { 3115 case USB_SPEED_FULL: 3116 break; 3117 default: 3118 usb_hs_bandwidth_free(xfer); 3119 break; 3120 } 3121 } 3122 } 3123 3124 static void 3125 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3126 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3127 { 3128 struct usb_xfer *xfer; 3129 3130 /* check if there is a current transfer */ 3131 xfer = ep->endpoint_q[stream_id].curr; 3132 if (xfer == NULL) 3133 return; 3134 3135 /* 3136 * Check if the current transfer is started and then pickup 3137 * the next one, if any. Else wait for next start event due to 3138 * block on failure feature. 3139 */ 3140 if (!xfer->flags_int.bandwidth_reclaimed) 3141 return; 3142 3143 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3144 if (xfer == NULL) { 3145 /* 3146 * In case of enter we have to consider that the 3147 * transfer is queued by the USB core after the enter 3148 * method is called. 3149 */ 3150 xfer = enter_xfer; 3151 3152 if (xfer == NULL) 3153 return; 3154 } 3155 3156 /* try to multi buffer */ 3157 xhci_transfer_insert(xfer); 3158 } 3159 3160 static void 3161 xhci_device_generic_enter(struct usb_xfer *xfer) 3162 { 3163 DPRINTF("\n"); 3164 3165 /* set up TD's and QH */ 3166 xhci_setup_generic_chain(xfer); 3167 3168 xhci_device_generic_multi_enter(xfer->endpoint, 3169 xfer->stream_id, xfer); 3170 } 3171 3172 static void 3173 xhci_device_generic_start(struct usb_xfer *xfer) 3174 { 3175 DPRINTF("\n"); 3176 3177 /* try to insert xfer on HW queue */ 3178 xhci_transfer_insert(xfer); 3179 3180 /* try to multi buffer */ 3181 xhci_device_generic_multi_enter(xfer->endpoint, 3182 xfer->stream_id, NULL); 3183 3184 /* add transfer last on interrupt queue */ 3185 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3186 3187 /* start timeout, if any */ 3188 if (xfer->timeout != 0) 3189 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3190 } 3191 3192 static const struct usb_pipe_methods xhci_device_generic_methods = 3193 { 3194 .open = xhci_device_generic_open, 3195 .close = xhci_device_generic_close, 3196 .enter = xhci_device_generic_enter, 3197 .start = xhci_device_generic_start, 3198 }; 3199 3200 /*------------------------------------------------------------------------* 3201 * xhci root HUB support 3202 *------------------------------------------------------------------------* 3203 * Simulate a hardware HUB by handling all the necessary requests. 3204 *------------------------------------------------------------------------*/ 3205 3206 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3207 3208 static const 3209 struct usb_device_descriptor xhci_devd = 3210 { 3211 .bLength = sizeof(xhci_devd), 3212 .bDescriptorType = UDESC_DEVICE, /* type */ 3213 HSETW(.bcdUSB, 0x0300), /* USB version */ 3214 .bDeviceClass = UDCLASS_HUB, /* class */ 3215 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3216 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3217 .bMaxPacketSize = 9, /* max packet size */ 3218 HSETW(.idVendor, 0x0000), /* vendor */ 3219 HSETW(.idProduct, 0x0000), /* product */ 3220 HSETW(.bcdDevice, 0x0100), /* device version */ 3221 .iManufacturer = 1, 3222 .iProduct = 2, 3223 .iSerialNumber = 0, 3224 .bNumConfigurations = 1, /* # of configurations */ 3225 }; 3226 3227 static const 3228 struct xhci_bos_desc xhci_bosd = { 3229 .bosd = { 3230 .bLength = sizeof(xhci_bosd.bosd), 3231 .bDescriptorType = UDESC_BOS, 3232 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3233 .bNumDeviceCaps = 3, 3234 }, 3235 .usb2extd = { 3236 .bLength = sizeof(xhci_bosd.usb2extd), 3237 .bDescriptorType = 1, 3238 .bDevCapabilityType = 2, 3239 .bmAttributes[0] = 2, 3240 }, 3241 .usbdcd = { 3242 .bLength = sizeof(xhci_bosd.usbdcd), 3243 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3244 .bDevCapabilityType = 3, 3245 .bmAttributes = 0, /* XXX */ 3246 HSETW(.wSpeedsSupported, 0x000C), 3247 .bFunctionalitySupport = 8, 3248 .bU1DevExitLat = 255, /* dummy - not used */ 3249 .wU2DevExitLat = { 0x00, 0x08 }, 3250 }, 3251 .cidd = { 3252 .bLength = sizeof(xhci_bosd.cidd), 3253 .bDescriptorType = 1, 3254 .bDevCapabilityType = 4, 3255 .bReserved = 0, 3256 .bContainerID = 0, /* XXX */ 3257 }, 3258 }; 3259 3260 static const 3261 struct xhci_config_desc xhci_confd = { 3262 .confd = { 3263 .bLength = sizeof(xhci_confd.confd), 3264 .bDescriptorType = UDESC_CONFIG, 3265 .wTotalLength[0] = sizeof(xhci_confd), 3266 .bNumInterface = 1, 3267 .bConfigurationValue = 1, 3268 .iConfiguration = 0, 3269 .bmAttributes = UC_SELF_POWERED, 3270 .bMaxPower = 0 /* max power */ 3271 }, 3272 .ifcd = { 3273 .bLength = sizeof(xhci_confd.ifcd), 3274 .bDescriptorType = UDESC_INTERFACE, 3275 .bNumEndpoints = 1, 3276 .bInterfaceClass = UICLASS_HUB, 3277 .bInterfaceSubClass = UISUBCLASS_HUB, 3278 .bInterfaceProtocol = 0, 3279 }, 3280 .endpd = { 3281 .bLength = sizeof(xhci_confd.endpd), 3282 .bDescriptorType = UDESC_ENDPOINT, 3283 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3284 .bmAttributes = UE_INTERRUPT, 3285 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3286 .bInterval = 255, 3287 }, 3288 .endpcd = { 3289 .bLength = sizeof(xhci_confd.endpcd), 3290 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3291 .bMaxBurst = 0, 3292 .bmAttributes = 0, 3293 }, 3294 }; 3295 3296 static const 3297 struct usb_hub_ss_descriptor xhci_hubd = { 3298 .bLength = sizeof(xhci_hubd), 3299 .bDescriptorType = UDESC_SS_HUB, 3300 }; 3301 3302 static usb_error_t 3303 xhci_roothub_exec(struct usb_device *udev, 3304 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3305 { 3306 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3307 const char *str_ptr; 3308 const void *ptr; 3309 uint32_t port; 3310 uint32_t v; 3311 uint16_t len; 3312 uint16_t i; 3313 uint16_t value; 3314 uint16_t index; 3315 uint8_t j; 3316 usb_error_t err; 3317 3318 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3319 3320 /* buffer reset */ 3321 ptr = (const void *)&sc->sc_hub_desc; 3322 len = 0; 3323 err = 0; 3324 3325 value = UGETW(req->wValue); 3326 index = UGETW(req->wIndex); 3327 3328 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3329 "wValue=0x%04x wIndex=0x%04x\n", 3330 req->bmRequestType, req->bRequest, 3331 UGETW(req->wLength), value, index); 3332 3333 #define C(x,y) ((x) | ((y) << 8)) 3334 switch (C(req->bRequest, req->bmRequestType)) { 3335 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3336 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3337 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3338 /* 3339 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3340 * for the integrated root hub. 3341 */ 3342 break; 3343 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3344 len = 1; 3345 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3346 break; 3347 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3348 switch (value >> 8) { 3349 case UDESC_DEVICE: 3350 if ((value & 0xff) != 0) { 3351 err = USB_ERR_IOERROR; 3352 goto done; 3353 } 3354 len = sizeof(xhci_devd); 3355 ptr = (const void *)&xhci_devd; 3356 break; 3357 3358 case UDESC_BOS: 3359 if ((value & 0xff) != 0) { 3360 err = USB_ERR_IOERROR; 3361 goto done; 3362 } 3363 len = sizeof(xhci_bosd); 3364 ptr = (const void *)&xhci_bosd; 3365 break; 3366 3367 case UDESC_CONFIG: 3368 if ((value & 0xff) != 0) { 3369 err = USB_ERR_IOERROR; 3370 goto done; 3371 } 3372 len = sizeof(xhci_confd); 3373 ptr = (const void *)&xhci_confd; 3374 break; 3375 3376 case UDESC_STRING: 3377 switch (value & 0xff) { 3378 case 0: /* Language table */ 3379 str_ptr = "\001"; 3380 break; 3381 3382 case 1: /* Vendor */ 3383 str_ptr = sc->sc_vendor; 3384 break; 3385 3386 case 2: /* Product */ 3387 str_ptr = "XHCI root HUB"; 3388 break; 3389 3390 default: 3391 str_ptr = ""; 3392 break; 3393 } 3394 3395 len = usb_make_str_desc( 3396 sc->sc_hub_desc.temp, 3397 sizeof(sc->sc_hub_desc.temp), 3398 str_ptr); 3399 break; 3400 3401 default: 3402 err = USB_ERR_IOERROR; 3403 goto done; 3404 } 3405 break; 3406 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3407 len = 1; 3408 sc->sc_hub_desc.temp[0] = 0; 3409 break; 3410 case C(UR_GET_STATUS, UT_READ_DEVICE): 3411 len = 2; 3412 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3413 break; 3414 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3415 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3416 len = 2; 3417 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3418 break; 3419 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3420 if (value >= XHCI_MAX_DEVICES) { 3421 err = USB_ERR_IOERROR; 3422 goto done; 3423 } 3424 break; 3425 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3426 if (value != 0 && value != 1) { 3427 err = USB_ERR_IOERROR; 3428 goto done; 3429 } 3430 sc->sc_conf = value; 3431 break; 3432 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3433 break; 3434 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3435 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3436 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3437 err = USB_ERR_IOERROR; 3438 goto done; 3439 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3440 break; 3441 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3442 break; 3443 /* Hub requests */ 3444 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3445 break; 3446 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3447 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3448 3449 if ((index < 1) || 3450 (index > sc->sc_noport)) { 3451 err = USB_ERR_IOERROR; 3452 goto done; 3453 } 3454 port = XHCI_PORTSC(index); 3455 3456 v = XREAD4(sc, oper, port); 3457 i = XHCI_PS_PLS_GET(v); 3458 v &= ~XHCI_PS_CLEAR; 3459 3460 switch (value) { 3461 case UHF_C_BH_PORT_RESET: 3462 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3463 break; 3464 case UHF_C_PORT_CONFIG_ERROR: 3465 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3466 break; 3467 case UHF_C_PORT_SUSPEND: 3468 case UHF_C_PORT_LINK_STATE: 3469 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3470 break; 3471 case UHF_C_PORT_CONNECTION: 3472 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3473 break; 3474 case UHF_C_PORT_ENABLE: 3475 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3476 break; 3477 case UHF_C_PORT_OVER_CURRENT: 3478 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3479 break; 3480 case UHF_C_PORT_RESET: 3481 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3482 break; 3483 case UHF_PORT_ENABLE: 3484 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3485 break; 3486 case UHF_PORT_POWER: 3487 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3488 break; 3489 case UHF_PORT_INDICATOR: 3490 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3491 break; 3492 case UHF_PORT_SUSPEND: 3493 3494 /* U3 -> U15 */ 3495 if (i == 3) { 3496 XWRITE4(sc, oper, port, v | 3497 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3498 } 3499 3500 /* wait 20ms for resume sequence to complete */ 3501 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3502 3503 /* U0 */ 3504 XWRITE4(sc, oper, port, v | 3505 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3506 break; 3507 default: 3508 err = USB_ERR_IOERROR; 3509 goto done; 3510 } 3511 break; 3512 3513 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3514 if ((value & 0xff) != 0) { 3515 err = USB_ERR_IOERROR; 3516 goto done; 3517 } 3518 3519 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3520 3521 sc->sc_hub_desc.hubd = xhci_hubd; 3522 3523 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3524 3525 if (XHCI_HCS0_PPC(v)) 3526 i = UHD_PWR_INDIVIDUAL; 3527 else 3528 i = UHD_PWR_GANGED; 3529 3530 if (XHCI_HCS0_PIND(v)) 3531 i |= UHD_PORT_IND; 3532 3533 i |= UHD_OC_INDIVIDUAL; 3534 3535 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3536 3537 /* see XHCI section 5.4.9: */ 3538 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3539 3540 for (j = 1; j <= sc->sc_noport; j++) { 3541 3542 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3543 if (v & XHCI_PS_DR) { 3544 sc->sc_hub_desc.hubd. 3545 DeviceRemovable[j / 8] |= 1U << (j % 8); 3546 } 3547 } 3548 len = sc->sc_hub_desc.hubd.bLength; 3549 break; 3550 3551 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3552 len = 16; 3553 memset(sc->sc_hub_desc.temp, 0, 16); 3554 break; 3555 3556 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3557 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3558 3559 if ((index < 1) || 3560 (index > sc->sc_noport)) { 3561 err = USB_ERR_IOERROR; 3562 goto done; 3563 } 3564 3565 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3566 3567 DPRINTFN(9, "port status=0x%08x\n", v); 3568 3569 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3570 3571 switch (XHCI_PS_SPEED_GET(v)) { 3572 case 3: 3573 i |= UPS_HIGH_SPEED; 3574 break; 3575 case 2: 3576 i |= UPS_LOW_SPEED; 3577 break; 3578 case 1: 3579 /* FULL speed */ 3580 break; 3581 default: 3582 i |= UPS_OTHER_SPEED; 3583 break; 3584 } 3585 3586 if (v & XHCI_PS_CCS) 3587 i |= UPS_CURRENT_CONNECT_STATUS; 3588 if (v & XHCI_PS_PED) 3589 i |= UPS_PORT_ENABLED; 3590 if (v & XHCI_PS_OCA) 3591 i |= UPS_OVERCURRENT_INDICATOR; 3592 if (v & XHCI_PS_PR) 3593 i |= UPS_RESET; 3594 #if 0 3595 if (v & XHCI_PS_PP) 3596 /* XXX undefined */ 3597 #endif 3598 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3599 3600 i = 0; 3601 if (v & XHCI_PS_CSC) 3602 i |= UPS_C_CONNECT_STATUS; 3603 if (v & XHCI_PS_PEC) 3604 i |= UPS_C_PORT_ENABLED; 3605 if (v & XHCI_PS_OCC) 3606 i |= UPS_C_OVERCURRENT_INDICATOR; 3607 if (v & XHCI_PS_WRC) 3608 i |= UPS_C_BH_PORT_RESET; 3609 if (v & XHCI_PS_PRC) 3610 i |= UPS_C_PORT_RESET; 3611 if (v & XHCI_PS_PLC) 3612 i |= UPS_C_PORT_LINK_STATE; 3613 if (v & XHCI_PS_CEC) 3614 i |= UPS_C_PORT_CONFIG_ERROR; 3615 3616 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3617 len = sizeof(sc->sc_hub_desc.ps); 3618 break; 3619 3620 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3621 err = USB_ERR_IOERROR; 3622 goto done; 3623 3624 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3625 break; 3626 3627 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3628 3629 i = index >> 8; 3630 index &= 0x00FF; 3631 3632 if ((index < 1) || 3633 (index > sc->sc_noport)) { 3634 err = USB_ERR_IOERROR; 3635 goto done; 3636 } 3637 3638 port = XHCI_PORTSC(index); 3639 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3640 3641 switch (value) { 3642 case UHF_PORT_U1_TIMEOUT: 3643 if (XHCI_PS_SPEED_GET(v) != 4) { 3644 err = USB_ERR_IOERROR; 3645 goto done; 3646 } 3647 port = XHCI_PORTPMSC(index); 3648 v = XREAD4(sc, oper, port); 3649 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3650 v |= XHCI_PM3_U1TO_SET(i); 3651 XWRITE4(sc, oper, port, v); 3652 break; 3653 case UHF_PORT_U2_TIMEOUT: 3654 if (XHCI_PS_SPEED_GET(v) != 4) { 3655 err = USB_ERR_IOERROR; 3656 goto done; 3657 } 3658 port = XHCI_PORTPMSC(index); 3659 v = XREAD4(sc, oper, port); 3660 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3661 v |= XHCI_PM3_U2TO_SET(i); 3662 XWRITE4(sc, oper, port, v); 3663 break; 3664 case UHF_BH_PORT_RESET: 3665 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3666 break; 3667 case UHF_PORT_LINK_STATE: 3668 XWRITE4(sc, oper, port, v | 3669 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3670 /* 4ms settle time */ 3671 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3672 break; 3673 case UHF_PORT_ENABLE: 3674 DPRINTFN(3, "set port enable %d\n", index); 3675 break; 3676 case UHF_PORT_SUSPEND: 3677 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3678 j = XHCI_PS_SPEED_GET(v); 3679 if ((j < 1) || (j > 3)) { 3680 /* non-supported speed */ 3681 err = USB_ERR_IOERROR; 3682 goto done; 3683 } 3684 XWRITE4(sc, oper, port, v | 3685 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3686 break; 3687 case UHF_PORT_RESET: 3688 DPRINTFN(6, "reset port %d\n", index); 3689 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3690 break; 3691 case UHF_PORT_POWER: 3692 DPRINTFN(3, "set port power %d\n", index); 3693 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3694 break; 3695 case UHF_PORT_TEST: 3696 DPRINTFN(3, "set port test %d\n", index); 3697 break; 3698 case UHF_PORT_INDICATOR: 3699 DPRINTFN(3, "set port indicator %d\n", index); 3700 3701 v &= ~XHCI_PS_PIC_SET(3); 3702 v |= XHCI_PS_PIC_SET(1); 3703 3704 XWRITE4(sc, oper, port, v); 3705 break; 3706 default: 3707 err = USB_ERR_IOERROR; 3708 goto done; 3709 } 3710 break; 3711 3712 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3713 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3714 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3715 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3716 break; 3717 default: 3718 err = USB_ERR_IOERROR; 3719 goto done; 3720 } 3721 done: 3722 *plength = len; 3723 *pptr = ptr; 3724 return (err); 3725 } 3726 3727 static void 3728 xhci_xfer_setup(struct usb_setup_params *parm) 3729 { 3730 struct usb_page_search page_info; 3731 struct usb_page_cache *pc; 3732 struct usb_xfer *xfer; 3733 void *last_obj; 3734 uint32_t ntd; 3735 uint32_t n; 3736 3737 xfer = parm->curr_xfer; 3738 3739 /* 3740 * The proof for the "ntd" formula is illustrated like this: 3741 * 3742 * +------------------------------------+ 3743 * | | 3744 * | |remainder -> | 3745 * | +-----+---+ | 3746 * | | xxx | x | frm 0 | 3747 * | +-----+---++ | 3748 * | | xxx | xx | frm 1 | 3749 * | +-----+----+ | 3750 * | ... | 3751 * +------------------------------------+ 3752 * 3753 * "xxx" means a completely full USB transfer descriptor 3754 * 3755 * "x" and "xx" means a short USB packet 3756 * 3757 * For the remainder of an USB transfer modulo 3758 * "max_data_length" we need two USB transfer descriptors. 3759 * One to transfer the remaining data and one to finalise with 3760 * a zero length packet in case the "force_short_xfer" flag is 3761 * set. We only need two USB transfer descriptors in the case 3762 * where the transfer length of the first one is a factor of 3763 * "max_frame_size". The rest of the needed USB transfer 3764 * descriptors is given by the buffer size divided by the 3765 * maximum data payload. 3766 */ 3767 parm->hc_max_packet_size = 0x400; 3768 parm->hc_max_packet_count = 16 * 3; 3769 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3770 3771 xfer->flags_int.bdma_enable = 1; 3772 3773 usbd_transfer_setup_sub(parm); 3774 3775 if (xfer->flags_int.isochronous_xfr) { 3776 ntd = ((1 * xfer->nframes) 3777 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3778 } else if (xfer->flags_int.control_xfr) { 3779 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3780 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3781 } else { 3782 ntd = ((2 * xfer->nframes) 3783 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3784 } 3785 3786 alloc_dma_set: 3787 3788 if (parm->err) 3789 return; 3790 3791 /* 3792 * Allocate queue heads and transfer descriptors 3793 */ 3794 last_obj = NULL; 3795 3796 if (usbd_transfer_setup_sub_malloc( 3797 parm, &pc, sizeof(struct xhci_td), 3798 XHCI_TD_ALIGN, ntd)) { 3799 parm->err = USB_ERR_NOMEM; 3800 return; 3801 } 3802 if (parm->buf) { 3803 for (n = 0; n != ntd; n++) { 3804 struct xhci_td *td; 3805 3806 usbd_get_page(pc + n, 0, &page_info); 3807 3808 td = page_info.buffer; 3809 3810 /* init TD */ 3811 td->td_self = page_info.physaddr; 3812 td->obj_next = last_obj; 3813 td->page_cache = pc + n; 3814 3815 last_obj = td; 3816 3817 usb_pc_cpu_flush(pc + n); 3818 } 3819 } 3820 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3821 3822 if (!xfer->flags_int.curr_dma_set) { 3823 xfer->flags_int.curr_dma_set = 1; 3824 goto alloc_dma_set; 3825 } 3826 } 3827 3828 static usb_error_t 3829 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3830 { 3831 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3832 struct usb_page_search buf_inp; 3833 struct usb_device *udev; 3834 struct xhci_endpoint_ext *pepext; 3835 struct usb_endpoint_descriptor *edesc; 3836 struct usb_page_cache *pcinp; 3837 usb_error_t err; 3838 usb_stream_t stream_id; 3839 uint32_t mask; 3840 uint8_t index; 3841 uint8_t epno; 3842 3843 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3844 xfer->endpoint->edesc); 3845 3846 udev = xfer->xroot->udev; 3847 index = udev->controller_slot_id; 3848 3849 pcinp = &sc->sc_hw.devs[index].input_pc; 3850 3851 usbd_get_page(pcinp, 0, &buf_inp); 3852 3853 edesc = xfer->endpoint->edesc; 3854 3855 epno = edesc->bEndpointAddress; 3856 stream_id = xfer->stream_id; 3857 3858 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3859 epno |= UE_DIR_IN; 3860 3861 epno = XHCI_EPNO2EPID(epno); 3862 3863 if (epno == 0) 3864 return (USB_ERR_NO_PIPE); /* invalid */ 3865 3866 XHCI_CMD_LOCK(sc); 3867 3868 /* configure endpoint */ 3869 3870 err = xhci_configure_endpoint_by_xfer(xfer); 3871 3872 if (err != 0) { 3873 XHCI_CMD_UNLOCK(sc); 3874 return (err); 3875 } 3876 3877 /* 3878 * Get the endpoint into the stopped state according to the 3879 * endpoint context state diagram in the XHCI specification: 3880 */ 3881 3882 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3883 3884 if (err != 0) 3885 DPRINTF("Could not stop endpoint %u\n", epno); 3886 3887 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3888 3889 if (err != 0) 3890 DPRINTF("Could not reset endpoint %u\n", epno); 3891 3892 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3893 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3894 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3895 stream_id, epno, index); 3896 3897 if (err != 0) 3898 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3899 3900 /* 3901 * Get the endpoint into the running state according to the 3902 * endpoint context state diagram in the XHCI specification: 3903 */ 3904 3905 mask = (1U << epno); 3906 xhci_configure_mask(udev, mask | 1U, 0); 3907 3908 if (!(sc->sc_hw.devs[index].ep_configured & mask)) { 3909 sc->sc_hw.devs[index].ep_configured |= mask; 3910 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3911 } else { 3912 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3913 } 3914 3915 if (err != 0) { 3916 DPRINTF("Could not configure " 3917 "endpoint %u at slot %u.\n", epno, index); 3918 } 3919 XHCI_CMD_UNLOCK(sc); 3920 3921 return (0); 3922 } 3923 3924 static void 3925 xhci_xfer_unsetup(struct usb_xfer *xfer) 3926 { 3927 return; 3928 } 3929 3930 static void 3931 xhci_start_dma_delay(struct usb_xfer *xfer) 3932 { 3933 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3934 3935 /* put transfer on interrupt queue (again) */ 3936 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3937 3938 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3939 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3940 } 3941 3942 static void 3943 xhci_configure_msg(struct usb_proc_msg *pm) 3944 { 3945 struct xhci_softc *sc; 3946 struct xhci_endpoint_ext *pepext; 3947 struct usb_xfer *xfer; 3948 3949 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3950 3951 restart: 3952 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3953 3954 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3955 xfer->endpoint->edesc); 3956 3957 if ((pepext->trb_halted != 0) || 3958 (pepext->trb_running == 0)) { 3959 3960 uint16_t i; 3961 3962 /* clear halted and running */ 3963 pepext->trb_halted = 0; 3964 pepext->trb_running = 0; 3965 3966 /* nuke remaining buffered transfers */ 3967 3968 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3969 XHCI_MAX_STREAMS); i++) { 3970 /* 3971 * NOTE: We need to use the timeout 3972 * error code here else existing 3973 * isochronous clients can get 3974 * confused: 3975 */ 3976 if (pepext->xfer[i] != NULL) { 3977 xhci_device_done(pepext->xfer[i], 3978 USB_ERR_TIMEOUT); 3979 } 3980 } 3981 3982 /* 3983 * NOTE: The USB transfer cannot vanish in 3984 * this state! 3985 */ 3986 3987 USB_BUS_UNLOCK(&sc->sc_bus); 3988 3989 xhci_configure_reset_endpoint(xfer); 3990 3991 USB_BUS_LOCK(&sc->sc_bus); 3992 3993 /* check if halted is still cleared */ 3994 if (pepext->trb_halted == 0) { 3995 pepext->trb_running = 1; 3996 memset(pepext->trb_index, 0, 3997 sizeof(pepext->trb_index)); 3998 } 3999 goto restart; 4000 } 4001 4002 if (xfer->flags_int.did_dma_delay) { 4003 4004 /* remove transfer from interrupt queue (again) */ 4005 usbd_transfer_dequeue(xfer); 4006 4007 /* we are finally done */ 4008 usb_dma_delay_done_cb(xfer); 4009 4010 /* queue changed - restart */ 4011 goto restart; 4012 } 4013 } 4014 4015 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4016 4017 /* try to insert xfer on HW queue */ 4018 xhci_transfer_insert(xfer); 4019 4020 /* try to multi buffer */ 4021 xhci_device_generic_multi_enter(xfer->endpoint, 4022 xfer->stream_id, NULL); 4023 } 4024 } 4025 4026 static void 4027 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4028 struct usb_endpoint *ep) 4029 { 4030 struct xhci_endpoint_ext *pepext; 4031 4032 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 4033 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 4034 4035 if (udev->parent_hub == NULL) { 4036 /* root HUB has special endpoint handling */ 4037 return; 4038 } 4039 4040 ep->methods = &xhci_device_generic_methods; 4041 4042 pepext = xhci_get_endpoint_ext(udev, edesc); 4043 4044 USB_BUS_LOCK(udev->bus); 4045 pepext->trb_halted = 1; 4046 pepext->trb_running = 0; 4047 USB_BUS_UNLOCK(udev->bus); 4048 } 4049 4050 static void 4051 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 4052 { 4053 4054 } 4055 4056 static void 4057 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 4058 { 4059 struct xhci_endpoint_ext *pepext; 4060 4061 DPRINTF("\n"); 4062 4063 if (udev->flags.usb_mode != USB_MODE_HOST) { 4064 /* not supported */ 4065 return; 4066 } 4067 if (udev->parent_hub == NULL) { 4068 /* root HUB has special endpoint handling */ 4069 return; 4070 } 4071 4072 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 4073 4074 USB_BUS_LOCK(udev->bus); 4075 pepext->trb_halted = 1; 4076 pepext->trb_running = 0; 4077 USB_BUS_UNLOCK(udev->bus); 4078 } 4079 4080 static usb_error_t 4081 xhci_device_init(struct usb_device *udev) 4082 { 4083 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4084 usb_error_t err; 4085 uint8_t temp; 4086 4087 /* no init for root HUB */ 4088 if (udev->parent_hub == NULL) 4089 return (0); 4090 4091 XHCI_CMD_LOCK(sc); 4092 4093 /* set invalid default */ 4094 4095 udev->controller_slot_id = sc->sc_noslot + 1; 4096 4097 /* try to get a new slot ID from the XHCI */ 4098 4099 err = xhci_cmd_enable_slot(sc, &temp); 4100 4101 if (err) { 4102 XHCI_CMD_UNLOCK(sc); 4103 return (err); 4104 } 4105 4106 if (temp > sc->sc_noslot) { 4107 XHCI_CMD_UNLOCK(sc); 4108 return (USB_ERR_BAD_ADDRESS); 4109 } 4110 4111 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4112 DPRINTF("slot %u already allocated.\n", temp); 4113 XHCI_CMD_UNLOCK(sc); 4114 return (USB_ERR_BAD_ADDRESS); 4115 } 4116 4117 /* store slot ID for later reference */ 4118 4119 udev->controller_slot_id = temp; 4120 4121 /* reset data structure */ 4122 4123 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4124 4125 /* set mark slot allocated */ 4126 4127 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4128 4129 err = xhci_alloc_device_ext(udev); 4130 4131 XHCI_CMD_UNLOCK(sc); 4132 4133 /* get device into default state */ 4134 4135 if (err == 0) 4136 err = xhci_set_address(udev, NULL, 0); 4137 4138 return (err); 4139 } 4140 4141 static void 4142 xhci_device_uninit(struct usb_device *udev) 4143 { 4144 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4145 uint8_t index; 4146 4147 /* no init for root HUB */ 4148 if (udev->parent_hub == NULL) 4149 return; 4150 4151 XHCI_CMD_LOCK(sc); 4152 4153 index = udev->controller_slot_id; 4154 4155 if (index <= sc->sc_noslot) { 4156 xhci_cmd_disable_slot(sc, index); 4157 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4158 4159 /* free device extension */ 4160 xhci_free_device_ext(udev); 4161 } 4162 4163 XHCI_CMD_UNLOCK(sc); 4164 } 4165 4166 static void 4167 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4168 { 4169 /* 4170 * Wait until the hardware has finished any possible use of 4171 * the transfer descriptor(s) 4172 */ 4173 *pus = 2048; /* microseconds */ 4174 } 4175 4176 static void 4177 xhci_device_resume(struct usb_device *udev) 4178 { 4179 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4180 uint8_t index; 4181 uint8_t n; 4182 uint8_t p; 4183 4184 DPRINTF("\n"); 4185 4186 /* check for root HUB */ 4187 if (udev->parent_hub == NULL) 4188 return; 4189 4190 index = udev->controller_slot_id; 4191 4192 XHCI_CMD_LOCK(sc); 4193 4194 /* blindly resume all endpoints */ 4195 4196 USB_BUS_LOCK(udev->bus); 4197 4198 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4199 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4200 XWRITE4(sc, door, XHCI_DOORBELL(index), 4201 n | XHCI_DB_SID_SET(p)); 4202 } 4203 } 4204 4205 USB_BUS_UNLOCK(udev->bus); 4206 4207 XHCI_CMD_UNLOCK(sc); 4208 } 4209 4210 static void 4211 xhci_device_suspend(struct usb_device *udev) 4212 { 4213 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4214 uint8_t index; 4215 uint8_t n; 4216 usb_error_t err; 4217 4218 DPRINTF("\n"); 4219 4220 /* check for root HUB */ 4221 if (udev->parent_hub == NULL) 4222 return; 4223 4224 index = udev->controller_slot_id; 4225 4226 XHCI_CMD_LOCK(sc); 4227 4228 /* blindly suspend all endpoints */ 4229 4230 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4231 err = xhci_cmd_stop_ep(sc, 1, n, index); 4232 if (err != 0) { 4233 DPRINTF("Failed to suspend endpoint " 4234 "%u on slot %u (ignored).\n", n, index); 4235 } 4236 } 4237 4238 XHCI_CMD_UNLOCK(sc); 4239 } 4240 4241 static void 4242 xhci_set_hw_power(struct usb_bus *bus) 4243 { 4244 DPRINTF("\n"); 4245 } 4246 4247 static void 4248 xhci_device_state_change(struct usb_device *udev) 4249 { 4250 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4251 struct usb_page_search buf_inp; 4252 usb_error_t err; 4253 uint8_t index; 4254 4255 /* check for root HUB */ 4256 if (udev->parent_hub == NULL) 4257 return; 4258 4259 index = udev->controller_slot_id; 4260 4261 DPRINTF("\n"); 4262 4263 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4264 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4265 &sc->sc_hw.devs[index].tt); 4266 if (err != 0) 4267 sc->sc_hw.devs[index].nports = 0; 4268 } 4269 4270 XHCI_CMD_LOCK(sc); 4271 4272 switch (usb_get_device_state(udev)) { 4273 case USB_STATE_POWERED: 4274 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4275 break; 4276 4277 /* set default state */ 4278 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4279 sc->sc_hw.devs[index].ep_configured = 3U; 4280 4281 /* reset number of contexts */ 4282 sc->sc_hw.devs[index].context_num = 0; 4283 4284 err = xhci_cmd_reset_dev(sc, index); 4285 4286 if (err != 0) { 4287 DPRINTF("Device reset failed " 4288 "for slot %u.\n", index); 4289 } 4290 break; 4291 4292 case USB_STATE_ADDRESSED: 4293 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4294 break; 4295 4296 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4297 sc->sc_hw.devs[index].ep_configured = 3U; 4298 4299 /* set configure mask to slot only */ 4300 xhci_configure_mask(udev, 1, 0); 4301 4302 /* deconfigure all endpoints, except EP0 */ 4303 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4304 4305 if (err) { 4306 DPRINTF("Failed to deconfigure " 4307 "slot %u.\n", index); 4308 } 4309 break; 4310 4311 case USB_STATE_CONFIGURED: 4312 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) { 4313 /* deconfigure all endpoints, except EP0 */ 4314 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4315 4316 if (err) { 4317 DPRINTF("Failed to deconfigure " 4318 "slot %u.\n", index); 4319 } 4320 } 4321 4322 /* set configured state */ 4323 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4324 sc->sc_hw.devs[index].ep_configured = 3U; 4325 4326 /* reset number of contexts */ 4327 sc->sc_hw.devs[index].context_num = 0; 4328 4329 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4330 4331 xhci_configure_mask(udev, 3, 0); 4332 4333 err = xhci_configure_device(udev); 4334 if (err != 0) { 4335 DPRINTF("Could not configure device " 4336 "at slot %u.\n", index); 4337 } 4338 4339 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4340 if (err != 0) { 4341 DPRINTF("Could not evaluate device " 4342 "context at slot %u.\n", index); 4343 } 4344 break; 4345 4346 default: 4347 break; 4348 } 4349 XHCI_CMD_UNLOCK(sc); 4350 } 4351 4352 static usb_error_t 4353 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4354 uint8_t ep_mode) 4355 { 4356 switch (ep_mode) { 4357 case USB_EP_MODE_DEFAULT: 4358 return (0); 4359 case USB_EP_MODE_STREAMS: 4360 if (xhcistreams == 0 || 4361 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4362 udev->speed != USB_SPEED_SUPER) 4363 return (USB_ERR_INVAL); 4364 return (0); 4365 default: 4366 return (USB_ERR_INVAL); 4367 } 4368 } 4369 4370 static const struct usb_bus_methods xhci_bus_methods = { 4371 .endpoint_init = xhci_ep_init, 4372 .endpoint_uninit = xhci_ep_uninit, 4373 .xfer_setup = xhci_xfer_setup, 4374 .xfer_unsetup = xhci_xfer_unsetup, 4375 .get_dma_delay = xhci_get_dma_delay, 4376 .device_init = xhci_device_init, 4377 .device_uninit = xhci_device_uninit, 4378 .device_resume = xhci_device_resume, 4379 .device_suspend = xhci_device_suspend, 4380 .set_hw_power = xhci_set_hw_power, 4381 .roothub_exec = xhci_roothub_exec, 4382 .xfer_poll = xhci_do_poll, 4383 .start_dma_delay = xhci_start_dma_delay, 4384 .set_address = xhci_set_address, 4385 .clear_stall = xhci_ep_clear_stall, 4386 .device_state_change = xhci_device_state_change, 4387 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4388 .set_endpoint_mode = xhci_set_endpoint_mode, 4389 }; 4390