1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36 /* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43 #ifdef USB_GLOBAL_INCLUDE_FILE 44 #include USB_GLOBAL_INCLUDE_FILE 45 #else 46 #include <sys/stdint.h> 47 #include <sys/stddef.h> 48 #include <sys/param.h> 49 #include <sys/queue.h> 50 #include <sys/types.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/bus.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/condvar.h> 58 #include <sys/sysctl.h> 59 #include <sys/sx.h> 60 #include <sys/unistd.h> 61 #include <sys/callout.h> 62 #include <sys/malloc.h> 63 #include <sys/priv.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 68 #define USB_DEBUG_VAR xhcidebug 69 70 #include <dev/usb/usb_core.h> 71 #include <dev/usb/usb_debug.h> 72 #include <dev/usb/usb_busdma.h> 73 #include <dev/usb/usb_process.h> 74 #include <dev/usb/usb_transfer.h> 75 #include <dev/usb/usb_device.h> 76 #include <dev/usb/usb_hub.h> 77 #include <dev/usb/usb_util.h> 78 79 #include <dev/usb/usb_controller.h> 80 #include <dev/usb/usb_bus.h> 81 #endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83 #include <dev/usb/controller/xhci.h> 84 #include <dev/usb/controller/xhcireg.h> 85 86 #define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 92 static int xhcistreams; 93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN, 94 &xhcistreams, 0, "Set to enable streams mode support"); 95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams); 96 97 #ifdef USB_DEBUG 98 static int xhcidebug; 99 static int xhciroute; 100 static int xhcipolling; 101 102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 103 &xhcidebug, 0, "Debug level"); 104 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN, 106 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 107 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN, 109 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller"); 110 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling); 111 #else 112 #define xhciroute 0 113 #endif 114 115 #define XHCI_INTR_ENDPT 1 116 117 struct xhci_std_temp { 118 struct xhci_softc *sc; 119 struct usb_page_cache *pc; 120 struct xhci_td *td; 121 struct xhci_td *td_next; 122 uint32_t len; 123 uint32_t offset; 124 uint32_t max_packet_size; 125 uint32_t average; 126 uint16_t isoc_delta; 127 uint16_t isoc_frame; 128 uint8_t shortpkt; 129 uint8_t multishort; 130 uint8_t last_frame; 131 uint8_t trb_type; 132 uint8_t direction; 133 uint8_t tbc; 134 uint8_t tlbpc; 135 uint8_t step_td; 136 uint8_t do_isoc_sync; 137 }; 138 139 static void xhci_do_poll(struct usb_bus *); 140 static void xhci_device_done(struct usb_xfer *, usb_error_t); 141 static void xhci_root_intr(struct xhci_softc *); 142 static void xhci_free_device_ext(struct usb_device *); 143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 144 struct usb_endpoint_descriptor *); 145 static usb_proc_callback_t xhci_configure_msg; 146 static usb_error_t xhci_configure_device(struct usb_device *); 147 static usb_error_t xhci_configure_endpoint(struct usb_device *, 148 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 149 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 150 uint8_t); 151 static usb_error_t xhci_configure_mask(struct usb_device *, 152 uint32_t, uint8_t); 153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 154 uint64_t, uint8_t); 155 static void xhci_endpoint_doorbell(struct usb_xfer *); 156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 159 #ifdef USB_DEBUG 160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 161 #endif 162 163 static const struct usb_bus_methods xhci_bus_methods; 164 165 #ifdef USB_DEBUG 166 static void 167 xhci_dump_trb(struct xhci_trb *trb) 168 { 169 DPRINTFN(5, "trb = %p\n", trb); 170 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 171 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 172 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 173 } 174 175 static void 176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 177 { 178 DPRINTFN(5, "pep = %p\n", pep); 179 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 180 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 181 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 182 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 183 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 184 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 185 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 186 } 187 188 static void 189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 190 { 191 DPRINTFN(5, "psl = %p\n", psl); 192 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 193 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 194 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 195 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 196 } 197 #endif 198 199 uint8_t 200 xhci_use_polling(void) 201 { 202 #ifdef USB_DEBUG 203 return (xhcipolling != 0); 204 #else 205 return (0); 206 #endif 207 } 208 209 static void 210 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 211 { 212 struct xhci_softc *sc = XHCI_BUS2SC(bus); 213 uint8_t i; 214 215 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 216 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 217 218 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 219 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 220 221 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 222 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 223 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 224 } 225 } 226 227 static void 228 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 229 { 230 if (sc->sc_ctx_is_64_byte) { 231 uint32_t offset; 232 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 233 /* all contexts are initially 32-bytes */ 234 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 235 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 236 } 237 *ptr = htole32(val); 238 } 239 240 static uint32_t 241 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 242 { 243 if (sc->sc_ctx_is_64_byte) { 244 uint32_t offset; 245 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 246 /* all contexts are initially 32-bytes */ 247 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 248 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 249 } 250 return (le32toh(*ptr)); 251 } 252 253 static void 254 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 255 { 256 if (sc->sc_ctx_is_64_byte) { 257 uint32_t offset; 258 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 259 /* all contexts are initially 32-bytes */ 260 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 261 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 262 } 263 *ptr = htole64(val); 264 } 265 266 #ifdef USB_DEBUG 267 static uint64_t 268 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 269 { 270 if (sc->sc_ctx_is_64_byte) { 271 uint32_t offset; 272 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 273 /* all contexts are initially 32-bytes */ 274 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 275 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 276 } 277 return (le64toh(*ptr)); 278 } 279 #endif 280 281 static int 282 xhci_reset_command_queue_locked(struct xhci_softc *sc) 283 { 284 struct usb_page_search buf_res; 285 struct xhci_hw_root *phwr; 286 uint64_t addr; 287 uint32_t temp; 288 289 DPRINTF("\n"); 290 291 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 292 if (temp & XHCI_CRCR_LO_CRR) { 293 DPRINTF("Command ring running\n"); 294 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 295 296 /* 297 * Try to abort the last command as per section 298 * 4.6.1.2 "Aborting a Command" of the XHCI 299 * specification: 300 */ 301 302 /* stop and cancel */ 303 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 304 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 305 306 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 307 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 308 309 /* wait 250ms */ 310 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 311 312 /* check if command ring is still running */ 313 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 314 if (temp & XHCI_CRCR_LO_CRR) { 315 DPRINTF("Comand ring still running\n"); 316 return (USB_ERR_IOERROR); 317 } 318 } 319 320 /* reset command ring */ 321 sc->sc_command_ccs = 1; 322 sc->sc_command_idx = 0; 323 324 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 325 326 /* setup command ring control base address */ 327 addr = buf_res.physaddr; 328 phwr = buf_res.buffer; 329 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 330 331 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 332 333 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 334 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 335 336 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 337 338 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 339 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 340 341 return (0); 342 } 343 344 usb_error_t 345 xhci_start_controller(struct xhci_softc *sc) 346 { 347 struct usb_page_search buf_res; 348 struct xhci_hw_root *phwr; 349 struct xhci_dev_ctx_addr *pdctxa; 350 uint64_t addr; 351 uint32_t temp; 352 uint16_t i; 353 354 DPRINTF("\n"); 355 356 sc->sc_capa_off = 0; 357 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 358 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 359 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 360 361 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 362 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 363 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 364 365 sc->sc_event_ccs = 1; 366 sc->sc_event_idx = 0; 367 sc->sc_command_ccs = 1; 368 sc->sc_command_idx = 0; 369 370 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 371 372 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 373 374 DPRINTF("HCS0 = 0x%08x\n", temp); 375 376 if (XHCI_HCS0_CSZ(temp)) { 377 sc->sc_ctx_is_64_byte = 1; 378 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 379 } else { 380 sc->sc_ctx_is_64_byte = 0; 381 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 382 } 383 384 /* Reset controller */ 385 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 386 387 for (i = 0; i != 100; i++) { 388 usb_pause_mtx(NULL, hz / 100); 389 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 390 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 391 if (!temp) 392 break; 393 } 394 395 if (temp) { 396 device_printf(sc->sc_bus.parent, "Controller " 397 "reset timeout.\n"); 398 return (USB_ERR_IOERROR); 399 } 400 401 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 402 device_printf(sc->sc_bus.parent, "Controller does " 403 "not support 4K page size.\n"); 404 return (USB_ERR_IOERROR); 405 } 406 407 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 408 409 i = XHCI_HCS1_N_PORTS(temp); 410 411 if (i == 0) { 412 device_printf(sc->sc_bus.parent, "Invalid number " 413 "of ports: %u\n", i); 414 return (USB_ERR_IOERROR); 415 } 416 417 sc->sc_noport = i; 418 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 419 420 if (sc->sc_noslot > XHCI_MAX_DEVICES) 421 sc->sc_noslot = XHCI_MAX_DEVICES; 422 423 /* setup number of device slots */ 424 425 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 426 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 427 428 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 429 430 DPRINTF("Max slots: %u\n", sc->sc_noslot); 431 432 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 433 434 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 435 436 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 437 device_printf(sc->sc_bus.parent, "XHCI request " 438 "too many scratchpads\n"); 439 return (USB_ERR_NOMEM); 440 } 441 442 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 443 444 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 445 446 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 447 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 448 449 temp = XREAD4(sc, oper, XHCI_USBSTS); 450 451 /* clear interrupts */ 452 XWRITE4(sc, oper, XHCI_USBSTS, temp); 453 /* disable all device notifications */ 454 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 455 456 /* setup device context base address */ 457 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 458 pdctxa = buf_res.buffer; 459 memset(pdctxa, 0, sizeof(*pdctxa)); 460 461 addr = buf_res.physaddr; 462 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 463 464 /* slot 0 points to the table of scratchpad pointers */ 465 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 466 467 for (i = 0; i != sc->sc_noscratch; i++) { 468 struct usb_page_search buf_scp; 469 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 470 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 471 } 472 473 addr = buf_res.physaddr; 474 475 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 476 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 477 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 478 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 479 480 /* Setup event table size */ 481 482 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 483 484 DPRINTF("HCS2=0x%08x\n", temp); 485 486 temp = XHCI_HCS2_ERST_MAX(temp); 487 temp = 1U << temp; 488 if (temp > XHCI_MAX_RSEG) 489 temp = XHCI_MAX_RSEG; 490 491 sc->sc_erst_max = temp; 492 493 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 494 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 495 496 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 497 498 /* Setup interrupt rate */ 499 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 500 501 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 502 503 phwr = buf_res.buffer; 504 addr = buf_res.physaddr; 505 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 506 507 /* reset hardware root structure */ 508 memset(phwr, 0, sizeof(*phwr)); 509 510 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 511 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 512 513 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 514 515 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 516 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 517 518 addr = (uint64_t)buf_res.physaddr; 519 520 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 521 522 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 523 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 524 525 /* Setup interrupter registers */ 526 527 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 528 temp |= XHCI_IMAN_INTR_ENA; 529 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 530 531 /* setup command ring control base address */ 532 addr = buf_res.physaddr; 533 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 534 535 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 536 537 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 538 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 539 540 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 541 542 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 543 544 /* Go! */ 545 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 546 XHCI_CMD_INTE | XHCI_CMD_HSEE); 547 548 for (i = 0; i != 100; i++) { 549 usb_pause_mtx(NULL, hz / 100); 550 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 551 if (!temp) 552 break; 553 } 554 if (temp) { 555 XWRITE4(sc, oper, XHCI_USBCMD, 0); 556 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 557 return (USB_ERR_IOERROR); 558 } 559 560 /* catch any lost interrupts */ 561 xhci_do_poll(&sc->sc_bus); 562 563 if (sc->sc_port_route != NULL) { 564 /* Route all ports to the XHCI by default */ 565 sc->sc_port_route(sc->sc_bus.parent, 566 ~xhciroute, xhciroute); 567 } 568 return (0); 569 } 570 571 usb_error_t 572 xhci_halt_controller(struct xhci_softc *sc) 573 { 574 uint32_t temp; 575 uint16_t i; 576 577 DPRINTF("\n"); 578 579 sc->sc_capa_off = 0; 580 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 581 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 582 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 583 584 /* Halt controller */ 585 XWRITE4(sc, oper, XHCI_USBCMD, 0); 586 587 for (i = 0; i != 100; i++) { 588 usb_pause_mtx(NULL, hz / 100); 589 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 590 if (temp) 591 break; 592 } 593 594 if (!temp) { 595 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 596 return (USB_ERR_IOERROR); 597 } 598 return (0); 599 } 600 601 usb_error_t 602 xhci_init(struct xhci_softc *sc, device_t self) 603 { 604 /* initialise some bus fields */ 605 sc->sc_bus.parent = self; 606 607 /* set the bus revision */ 608 sc->sc_bus.usbrev = USB_REV_3_0; 609 610 /* set up the bus struct */ 611 sc->sc_bus.methods = &xhci_bus_methods; 612 613 /* setup devices array */ 614 sc->sc_bus.devices = sc->sc_devices; 615 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 616 617 /* setup command queue mutex and condition varible */ 618 cv_init(&sc->sc_cmd_cv, "CMDQ"); 619 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 620 621 /* get all DMA memory */ 622 if (usb_bus_mem_alloc_all(&sc->sc_bus, 623 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 624 return (ENOMEM); 625 } 626 627 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 628 sc->sc_config_msg[0].bus = &sc->sc_bus; 629 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 630 sc->sc_config_msg[1].bus = &sc->sc_bus; 631 632 return (0); 633 } 634 635 void 636 xhci_uninit(struct xhci_softc *sc) 637 { 638 /* 639 * NOTE: At this point the control transfer process is gone 640 * and "xhci_configure_msg" is no longer called. Consequently 641 * waiting for the configuration messages to complete is not 642 * needed. 643 */ 644 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 645 646 cv_destroy(&sc->sc_cmd_cv); 647 sx_destroy(&sc->sc_cmd_sx); 648 } 649 650 static void 651 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 652 { 653 struct xhci_softc *sc = XHCI_BUS2SC(bus); 654 655 switch (state) { 656 case USB_HW_POWER_SUSPEND: 657 DPRINTF("Stopping the XHCI\n"); 658 xhci_halt_controller(sc); 659 break; 660 case USB_HW_POWER_SHUTDOWN: 661 DPRINTF("Stopping the XHCI\n"); 662 xhci_halt_controller(sc); 663 break; 664 case USB_HW_POWER_RESUME: 665 DPRINTF("Starting the XHCI\n"); 666 xhci_start_controller(sc); 667 break; 668 default: 669 break; 670 } 671 } 672 673 static usb_error_t 674 xhci_generic_done_sub(struct usb_xfer *xfer) 675 { 676 struct xhci_td *td; 677 struct xhci_td *td_alt_next; 678 uint32_t len; 679 uint8_t status; 680 681 td = xfer->td_transfer_cache; 682 td_alt_next = td->alt_next; 683 684 if (xfer->aframes != xfer->nframes) 685 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 686 687 while (1) { 688 689 usb_pc_cpu_invalidate(td->page_cache); 690 691 status = td->status; 692 len = td->remainder; 693 694 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 695 xfer, (unsigned int)xfer->aframes, 696 (unsigned int)xfer->nframes, 697 (unsigned int)len, (unsigned int)td->len, 698 (unsigned int)status); 699 700 /* 701 * Verify the status length and 702 * add the length to "frlengths[]": 703 */ 704 if (len > td->len) { 705 /* should not happen */ 706 DPRINTF("Invalid status length, " 707 "0x%04x/0x%04x bytes\n", len, td->len); 708 status = XHCI_TRB_ERROR_LENGTH; 709 } else if (xfer->aframes != xfer->nframes) { 710 xfer->frlengths[xfer->aframes] += td->len - len; 711 } 712 /* Check for last transfer */ 713 if (((void *)td) == xfer->td_transfer_last) { 714 td = NULL; 715 break; 716 } 717 /* Check for transfer error */ 718 if (status != XHCI_TRB_ERROR_SHORT_PKT && 719 status != XHCI_TRB_ERROR_SUCCESS) { 720 /* the transfer is finished */ 721 td = NULL; 722 break; 723 } 724 /* Check for short transfer */ 725 if (len > 0) { 726 if (xfer->flags_int.short_frames_ok || 727 xfer->flags_int.isochronous_xfr || 728 xfer->flags_int.control_xfr) { 729 /* follow alt next */ 730 td = td->alt_next; 731 } else { 732 /* the transfer is finished */ 733 td = NULL; 734 } 735 break; 736 } 737 td = td->obj_next; 738 739 if (td->alt_next != td_alt_next) { 740 /* this USB frame is complete */ 741 break; 742 } 743 } 744 745 /* update transfer cache */ 746 747 xfer->td_transfer_cache = td; 748 749 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 750 (status != XHCI_TRB_ERROR_SHORT_PKT && 751 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 752 USB_ERR_NORMAL_COMPLETION); 753 } 754 755 static void 756 xhci_generic_done(struct usb_xfer *xfer) 757 { 758 usb_error_t err = 0; 759 760 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 761 xfer, xfer->endpoint); 762 763 /* reset scanner */ 764 765 xfer->td_transfer_cache = xfer->td_transfer_first; 766 767 if (xfer->flags_int.control_xfr) { 768 769 if (xfer->flags_int.control_hdr) 770 err = xhci_generic_done_sub(xfer); 771 772 xfer->aframes = 1; 773 774 if (xfer->td_transfer_cache == NULL) 775 goto done; 776 } 777 778 while (xfer->aframes != xfer->nframes) { 779 780 err = xhci_generic_done_sub(xfer); 781 xfer->aframes++; 782 783 if (xfer->td_transfer_cache == NULL) 784 goto done; 785 } 786 787 if (xfer->flags_int.control_xfr && 788 !xfer->flags_int.control_act) 789 err = xhci_generic_done_sub(xfer); 790 done: 791 /* transfer is complete */ 792 xhci_device_done(xfer, err); 793 } 794 795 static void 796 xhci_activate_transfer(struct usb_xfer *xfer) 797 { 798 struct xhci_td *td; 799 800 td = xfer->td_transfer_cache; 801 802 usb_pc_cpu_invalidate(td->page_cache); 803 804 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 805 806 /* activate the transfer */ 807 808 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 809 usb_pc_cpu_flush(td->page_cache); 810 811 xhci_endpoint_doorbell(xfer); 812 } 813 } 814 815 static void 816 xhci_skip_transfer(struct usb_xfer *xfer) 817 { 818 struct xhci_td *td; 819 struct xhci_td *td_last; 820 821 td = xfer->td_transfer_cache; 822 td_last = xfer->td_transfer_last; 823 824 td = td->alt_next; 825 826 usb_pc_cpu_invalidate(td->page_cache); 827 828 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 829 830 usb_pc_cpu_invalidate(td_last->page_cache); 831 832 /* copy LINK TRB to current waiting location */ 833 834 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 835 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 836 usb_pc_cpu_flush(td->page_cache); 837 838 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 839 usb_pc_cpu_flush(td->page_cache); 840 841 xhci_endpoint_doorbell(xfer); 842 } 843 } 844 845 /*------------------------------------------------------------------------* 846 * xhci_check_transfer 847 *------------------------------------------------------------------------*/ 848 static void 849 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 850 { 851 struct xhci_endpoint_ext *pepext; 852 int64_t offset; 853 uint64_t td_event; 854 uint32_t temp; 855 uint32_t remainder; 856 uint16_t stream_id; 857 uint16_t i; 858 uint8_t status; 859 uint8_t halted; 860 uint8_t epno; 861 uint8_t index; 862 863 /* decode TRB */ 864 td_event = le64toh(trb->qwTrb0); 865 temp = le32toh(trb->dwTrb2); 866 867 remainder = XHCI_TRB_2_REM_GET(temp); 868 status = XHCI_TRB_2_ERROR_GET(temp); 869 stream_id = XHCI_TRB_2_STREAM_GET(temp); 870 871 temp = le32toh(trb->dwTrb3); 872 epno = XHCI_TRB_3_EP_GET(temp); 873 index = XHCI_TRB_3_SLOT_GET(temp); 874 875 /* check if error means halted */ 876 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 877 status != XHCI_TRB_ERROR_SUCCESS); 878 879 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 880 index, epno, stream_id, remainder, status); 881 882 if (index > sc->sc_noslot) { 883 DPRINTF("Invalid slot.\n"); 884 return; 885 } 886 887 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 888 DPRINTF("Invalid endpoint.\n"); 889 return; 890 } 891 892 pepext = &sc->sc_hw.devs[index].endp[epno]; 893 894 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 895 stream_id = 0; 896 DPRINTF("stream_id=0\n"); 897 } else if (stream_id >= XHCI_MAX_STREAMS) { 898 DPRINTF("Invalid stream ID.\n"); 899 return; 900 } 901 902 /* try to find the USB transfer that generated the event */ 903 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 904 struct usb_xfer *xfer; 905 struct xhci_td *td; 906 907 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 908 if (xfer == NULL) 909 continue; 910 911 td = xfer->td_transfer_cache; 912 913 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 914 (long long)td_event, 915 (long long)td->td_self, 916 (long long)td->td_self + sizeof(td->td_trb)); 917 918 /* 919 * NOTE: Some XHCI implementations might not trigger 920 * an event on the last LINK TRB so we need to 921 * consider both the last and second last event 922 * address as conditions for a successful transfer. 923 * 924 * NOTE: We assume that the XHCI will only trigger one 925 * event per chain of TRBs. 926 */ 927 928 offset = td_event - td->td_self; 929 930 if (offset >= 0 && 931 offset < (int64_t)sizeof(td->td_trb)) { 932 933 usb_pc_cpu_invalidate(td->page_cache); 934 935 /* compute rest of remainder, if any */ 936 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 937 temp = le32toh(td->td_trb[i].dwTrb2); 938 remainder += XHCI_TRB_2_BYTES_GET(temp); 939 } 940 941 DPRINTFN(5, "New remainder: %u\n", remainder); 942 943 /* clear isochronous transfer errors */ 944 if (xfer->flags_int.isochronous_xfr) { 945 if (halted) { 946 halted = 0; 947 status = XHCI_TRB_ERROR_SUCCESS; 948 remainder = td->len; 949 } 950 } 951 952 /* "td->remainder" is verified later */ 953 td->remainder = remainder; 954 td->status = status; 955 956 usb_pc_cpu_flush(td->page_cache); 957 958 /* 959 * 1) Last transfer descriptor makes the 960 * transfer done 961 */ 962 if (((void *)td) == xfer->td_transfer_last) { 963 DPRINTF("TD is last\n"); 964 xhci_generic_done(xfer); 965 break; 966 } 967 968 /* 969 * 2) Any kind of error makes the transfer 970 * done 971 */ 972 if (halted) { 973 DPRINTF("TD has I/O error\n"); 974 xhci_generic_done(xfer); 975 break; 976 } 977 978 /* 979 * 3) If there is no alternate next transfer, 980 * a short packet also makes the transfer done 981 */ 982 if (td->remainder > 0) { 983 if (td->alt_next == NULL) { 984 DPRINTF( 985 "short TD has no alternate next\n"); 986 xhci_generic_done(xfer); 987 break; 988 } 989 DPRINTF("TD has short pkt\n"); 990 if (xfer->flags_int.short_frames_ok || 991 xfer->flags_int.isochronous_xfr || 992 xfer->flags_int.control_xfr) { 993 /* follow the alt next */ 994 xfer->td_transfer_cache = td->alt_next; 995 xhci_activate_transfer(xfer); 996 break; 997 } 998 xhci_skip_transfer(xfer); 999 xhci_generic_done(xfer); 1000 break; 1001 } 1002 1003 /* 1004 * 4) Transfer complete - go to next TD 1005 */ 1006 DPRINTF("Following next TD\n"); 1007 xfer->td_transfer_cache = td->obj_next; 1008 xhci_activate_transfer(xfer); 1009 break; /* there should only be one match */ 1010 } 1011 } 1012 } 1013 1014 static int 1015 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1016 { 1017 if (sc->sc_cmd_addr == trb->qwTrb0) { 1018 DPRINTF("Received command event\n"); 1019 sc->sc_cmd_result[0] = trb->dwTrb2; 1020 sc->sc_cmd_result[1] = trb->dwTrb3; 1021 cv_signal(&sc->sc_cmd_cv); 1022 return (1); /* command match */ 1023 } 1024 return (0); 1025 } 1026 1027 static int 1028 xhci_interrupt_poll(struct xhci_softc *sc) 1029 { 1030 struct usb_page_search buf_res; 1031 struct xhci_hw_root *phwr; 1032 uint64_t addr; 1033 uint32_t temp; 1034 int retval = 0; 1035 uint16_t i; 1036 uint8_t event; 1037 uint8_t j; 1038 uint8_t k; 1039 uint8_t t; 1040 1041 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1042 1043 phwr = buf_res.buffer; 1044 1045 /* Receive any events */ 1046 1047 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1048 1049 i = sc->sc_event_idx; 1050 j = sc->sc_event_ccs; 1051 t = 2; 1052 1053 while (1) { 1054 1055 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1056 1057 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1058 1059 if (j != k) 1060 break; 1061 1062 event = XHCI_TRB_3_TYPE_GET(temp); 1063 1064 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1065 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1066 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1067 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1068 1069 switch (event) { 1070 case XHCI_TRB_EVENT_TRANSFER: 1071 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1072 break; 1073 case XHCI_TRB_EVENT_CMD_COMPLETE: 1074 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1075 break; 1076 default: 1077 DPRINTF("Unhandled event = %u\n", event); 1078 break; 1079 } 1080 1081 i++; 1082 1083 if (i == XHCI_MAX_EVENTS) { 1084 i = 0; 1085 j ^= 1; 1086 1087 /* check for timeout */ 1088 if (!--t) 1089 break; 1090 } 1091 } 1092 1093 sc->sc_event_idx = i; 1094 sc->sc_event_ccs = j; 1095 1096 /* 1097 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1098 * latched. That means to activate the register we need to 1099 * write both the low and high double word of the 64-bit 1100 * register. 1101 */ 1102 1103 addr = (uint32_t)buf_res.physaddr; 1104 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1105 1106 /* try to clear busy bit */ 1107 addr |= XHCI_ERDP_LO_BUSY; 1108 1109 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1110 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1111 1112 return (retval); 1113 } 1114 1115 static usb_error_t 1116 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1117 uint16_t timeout_ms) 1118 { 1119 struct usb_page_search buf_res; 1120 struct xhci_hw_root *phwr; 1121 uint64_t addr; 1122 uint32_t temp; 1123 uint8_t i; 1124 uint8_t j; 1125 uint8_t timeout = 0; 1126 int err; 1127 1128 XHCI_CMD_ASSERT_LOCKED(sc); 1129 1130 /* get hardware root structure */ 1131 1132 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1133 1134 phwr = buf_res.buffer; 1135 1136 /* Queue command */ 1137 1138 USB_BUS_LOCK(&sc->sc_bus); 1139 retry: 1140 i = sc->sc_command_idx; 1141 j = sc->sc_command_ccs; 1142 1143 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1144 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1145 (long long)le64toh(trb->qwTrb0), 1146 (long)le32toh(trb->dwTrb2), 1147 (long)le32toh(trb->dwTrb3)); 1148 1149 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1150 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1151 1152 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1153 1154 temp = trb->dwTrb3; 1155 1156 if (j) 1157 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1158 else 1159 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1160 1161 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1162 1163 phwr->hwr_commands[i].dwTrb3 = temp; 1164 1165 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1166 1167 addr = buf_res.physaddr; 1168 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1169 1170 sc->sc_cmd_addr = htole64(addr); 1171 1172 i++; 1173 1174 if (i == (XHCI_MAX_COMMANDS - 1)) { 1175 1176 if (j) { 1177 temp = htole32(XHCI_TRB_3_TC_BIT | 1178 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1179 XHCI_TRB_3_CYCLE_BIT); 1180 } else { 1181 temp = htole32(XHCI_TRB_3_TC_BIT | 1182 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1183 } 1184 1185 phwr->hwr_commands[i].dwTrb3 = temp; 1186 1187 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1188 1189 i = 0; 1190 j ^= 1; 1191 } 1192 1193 sc->sc_command_idx = i; 1194 sc->sc_command_ccs = j; 1195 1196 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1197 1198 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1199 USB_MS_TO_TICKS(timeout_ms)); 1200 1201 /* 1202 * In some error cases event interrupts are not generated. 1203 * Poll one time to see if the command has completed. 1204 */ 1205 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1206 DPRINTF("Command was completed when polling\n"); 1207 err = 0; 1208 } 1209 if (err != 0) { 1210 DPRINTF("Command timeout!\n"); 1211 /* 1212 * After some weeks of continuous operation, it has 1213 * been observed that the ASMedia Technology, ASM1042 1214 * SuperSpeed USB Host Controller can suddenly stop 1215 * accepting commands via the command queue. Try to 1216 * first reset the command queue. If that fails do a 1217 * host controller reset. 1218 */ 1219 if (timeout == 0 && 1220 xhci_reset_command_queue_locked(sc) == 0) { 1221 temp = le32toh(trb->dwTrb3); 1222 1223 /* 1224 * Avoid infinite XHCI reset loops if the set 1225 * address command fails to respond due to a 1226 * non-enumerating device: 1227 */ 1228 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1229 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1230 DPRINTF("Set address timeout\n"); 1231 } else { 1232 timeout = 1; 1233 goto retry; 1234 } 1235 } else { 1236 DPRINTF("Controller reset!\n"); 1237 usb_bus_reset_async_locked(&sc->sc_bus); 1238 } 1239 err = USB_ERR_TIMEOUT; 1240 trb->dwTrb2 = 0; 1241 trb->dwTrb3 = 0; 1242 } else { 1243 temp = le32toh(sc->sc_cmd_result[0]); 1244 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1245 err = USB_ERR_IOERROR; 1246 1247 trb->dwTrb2 = sc->sc_cmd_result[0]; 1248 trb->dwTrb3 = sc->sc_cmd_result[1]; 1249 } 1250 1251 USB_BUS_UNLOCK(&sc->sc_bus); 1252 1253 return (err); 1254 } 1255 1256 #if 0 1257 static usb_error_t 1258 xhci_cmd_nop(struct xhci_softc *sc) 1259 { 1260 struct xhci_trb trb; 1261 uint32_t temp; 1262 1263 DPRINTF("\n"); 1264 1265 trb.qwTrb0 = 0; 1266 trb.dwTrb2 = 0; 1267 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1268 1269 trb.dwTrb3 = htole32(temp); 1270 1271 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1272 } 1273 #endif 1274 1275 static usb_error_t 1276 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1277 { 1278 struct xhci_trb trb; 1279 uint32_t temp; 1280 usb_error_t err; 1281 1282 DPRINTF("\n"); 1283 1284 trb.qwTrb0 = 0; 1285 trb.dwTrb2 = 0; 1286 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1287 1288 err = xhci_do_command(sc, &trb, 100 /* ms */); 1289 if (err) 1290 goto done; 1291 1292 temp = le32toh(trb.dwTrb3); 1293 1294 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1295 1296 done: 1297 return (err); 1298 } 1299 1300 static usb_error_t 1301 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1302 { 1303 struct xhci_trb trb; 1304 uint32_t temp; 1305 1306 DPRINTF("\n"); 1307 1308 trb.qwTrb0 = 0; 1309 trb.dwTrb2 = 0; 1310 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1311 XHCI_TRB_3_SLOT_SET(slot_id); 1312 1313 trb.dwTrb3 = htole32(temp); 1314 1315 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1316 } 1317 1318 static usb_error_t 1319 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1320 uint8_t bsr, uint8_t slot_id) 1321 { 1322 struct xhci_trb trb; 1323 uint32_t temp; 1324 1325 DPRINTF("\n"); 1326 1327 trb.qwTrb0 = htole64(input_ctx); 1328 trb.dwTrb2 = 0; 1329 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1330 XHCI_TRB_3_SLOT_SET(slot_id); 1331 1332 if (bsr) 1333 temp |= XHCI_TRB_3_BSR_BIT; 1334 1335 trb.dwTrb3 = htole32(temp); 1336 1337 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1338 } 1339 1340 static usb_error_t 1341 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1342 { 1343 struct usb_page_search buf_inp; 1344 struct usb_page_search buf_dev; 1345 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1346 struct xhci_hw_dev *hdev; 1347 struct xhci_dev_ctx *pdev; 1348 struct xhci_endpoint_ext *pepext; 1349 uint32_t temp; 1350 uint16_t mps; 1351 usb_error_t err; 1352 uint8_t index; 1353 1354 /* the root HUB case is not handled here */ 1355 if (udev->parent_hub == NULL) 1356 return (USB_ERR_INVAL); 1357 1358 index = udev->controller_slot_id; 1359 1360 hdev = &sc->sc_hw.devs[index]; 1361 1362 if (mtx != NULL) 1363 mtx_unlock(mtx); 1364 1365 XHCI_CMD_LOCK(sc); 1366 1367 switch (hdev->state) { 1368 case XHCI_ST_DEFAULT: 1369 case XHCI_ST_ENABLED: 1370 1371 hdev->state = XHCI_ST_ENABLED; 1372 1373 /* set configure mask to slot and EP0 */ 1374 xhci_configure_mask(udev, 3, 0); 1375 1376 /* configure input slot context structure */ 1377 err = xhci_configure_device(udev); 1378 1379 if (err != 0) { 1380 DPRINTF("Could not configure device\n"); 1381 break; 1382 } 1383 1384 /* configure input endpoint context structure */ 1385 switch (udev->speed) { 1386 case USB_SPEED_LOW: 1387 case USB_SPEED_FULL: 1388 mps = 8; 1389 break; 1390 case USB_SPEED_HIGH: 1391 mps = 64; 1392 break; 1393 default: 1394 mps = 512; 1395 break; 1396 } 1397 1398 pepext = xhci_get_endpoint_ext(udev, 1399 &udev->ctrl_ep_desc); 1400 err = xhci_configure_endpoint(udev, 1401 &udev->ctrl_ep_desc, pepext, 1402 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1403 1404 if (err != 0) { 1405 DPRINTF("Could not configure default endpoint\n"); 1406 break; 1407 } 1408 1409 /* execute set address command */ 1410 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1411 1412 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1413 (address == 0), index); 1414 1415 if (err != 0) { 1416 temp = le32toh(sc->sc_cmd_result[0]); 1417 if (address == 0 && sc->sc_port_route != NULL && 1418 XHCI_TRB_2_ERROR_GET(temp) == 1419 XHCI_TRB_ERROR_PARAMETER) { 1420 /* LynxPoint XHCI - ports are not switchable */ 1421 /* Un-route all ports from the XHCI */ 1422 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1423 } 1424 DPRINTF("Could not set address " 1425 "for slot %u.\n", index); 1426 if (address != 0) 1427 break; 1428 } 1429 1430 /* update device address to new value */ 1431 1432 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1433 pdev = buf_dev.buffer; 1434 usb_pc_cpu_invalidate(&hdev->device_pc); 1435 1436 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1437 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1438 1439 /* update device state to new value */ 1440 1441 if (address != 0) 1442 hdev->state = XHCI_ST_ADDRESSED; 1443 else 1444 hdev->state = XHCI_ST_DEFAULT; 1445 break; 1446 1447 default: 1448 DPRINTF("Wrong state for set address.\n"); 1449 err = USB_ERR_IOERROR; 1450 break; 1451 } 1452 XHCI_CMD_UNLOCK(sc); 1453 1454 if (mtx != NULL) 1455 mtx_lock(mtx); 1456 1457 return (err); 1458 } 1459 1460 static usb_error_t 1461 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1462 uint8_t deconfigure, uint8_t slot_id) 1463 { 1464 struct xhci_trb trb; 1465 uint32_t temp; 1466 1467 DPRINTF("\n"); 1468 1469 trb.qwTrb0 = htole64(input_ctx); 1470 trb.dwTrb2 = 0; 1471 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1472 XHCI_TRB_3_SLOT_SET(slot_id); 1473 1474 if (deconfigure) 1475 temp |= XHCI_TRB_3_DCEP_BIT; 1476 1477 trb.dwTrb3 = htole32(temp); 1478 1479 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1480 } 1481 1482 static usb_error_t 1483 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1484 uint8_t slot_id) 1485 { 1486 struct xhci_trb trb; 1487 uint32_t temp; 1488 1489 DPRINTF("\n"); 1490 1491 trb.qwTrb0 = htole64(input_ctx); 1492 trb.dwTrb2 = 0; 1493 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1494 XHCI_TRB_3_SLOT_SET(slot_id); 1495 trb.dwTrb3 = htole32(temp); 1496 1497 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1498 } 1499 1500 static usb_error_t 1501 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1502 uint8_t ep_id, uint8_t slot_id) 1503 { 1504 struct xhci_trb trb; 1505 uint32_t temp; 1506 1507 DPRINTF("\n"); 1508 1509 trb.qwTrb0 = 0; 1510 trb.dwTrb2 = 0; 1511 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1512 XHCI_TRB_3_SLOT_SET(slot_id) | 1513 XHCI_TRB_3_EP_SET(ep_id); 1514 1515 if (preserve) 1516 temp |= XHCI_TRB_3_PRSV_BIT; 1517 1518 trb.dwTrb3 = htole32(temp); 1519 1520 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1521 } 1522 1523 static usb_error_t 1524 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1525 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1526 { 1527 struct xhci_trb trb; 1528 uint32_t temp; 1529 1530 DPRINTF("\n"); 1531 1532 trb.qwTrb0 = htole64(dequeue_ptr); 1533 1534 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1535 trb.dwTrb2 = htole32(temp); 1536 1537 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1538 XHCI_TRB_3_SLOT_SET(slot_id) | 1539 XHCI_TRB_3_EP_SET(ep_id); 1540 trb.dwTrb3 = htole32(temp); 1541 1542 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1543 } 1544 1545 static usb_error_t 1546 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1547 uint8_t ep_id, uint8_t slot_id) 1548 { 1549 struct xhci_trb trb; 1550 uint32_t temp; 1551 1552 DPRINTF("\n"); 1553 1554 trb.qwTrb0 = 0; 1555 trb.dwTrb2 = 0; 1556 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1557 XHCI_TRB_3_SLOT_SET(slot_id) | 1558 XHCI_TRB_3_EP_SET(ep_id); 1559 1560 if (suspend) 1561 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1562 1563 trb.dwTrb3 = htole32(temp); 1564 1565 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1566 } 1567 1568 static usb_error_t 1569 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1570 { 1571 struct xhci_trb trb; 1572 uint32_t temp; 1573 1574 DPRINTF("\n"); 1575 1576 trb.qwTrb0 = 0; 1577 trb.dwTrb2 = 0; 1578 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1579 XHCI_TRB_3_SLOT_SET(slot_id); 1580 1581 trb.dwTrb3 = htole32(temp); 1582 1583 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1584 } 1585 1586 /*------------------------------------------------------------------------* 1587 * xhci_interrupt - XHCI interrupt handler 1588 *------------------------------------------------------------------------*/ 1589 void 1590 xhci_interrupt(struct xhci_softc *sc) 1591 { 1592 uint32_t status; 1593 uint32_t temp; 1594 1595 USB_BUS_LOCK(&sc->sc_bus); 1596 1597 status = XREAD4(sc, oper, XHCI_USBSTS); 1598 1599 /* acknowledge interrupts, if any */ 1600 if (status != 0) { 1601 XWRITE4(sc, oper, XHCI_USBSTS, status); 1602 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1603 } 1604 1605 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1606 1607 /* force clearing of pending interrupts */ 1608 if (temp & XHCI_IMAN_INTR_PEND) 1609 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1610 1611 /* check for event(s) */ 1612 xhci_interrupt_poll(sc); 1613 1614 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1615 XHCI_STS_HSE | XHCI_STS_HCE)) { 1616 1617 if (status & XHCI_STS_PCD) { 1618 xhci_root_intr(sc); 1619 } 1620 1621 if (status & XHCI_STS_HCH) { 1622 printf("%s: host controller halted\n", 1623 __FUNCTION__); 1624 } 1625 1626 if (status & XHCI_STS_HSE) { 1627 printf("%s: host system error\n", 1628 __FUNCTION__); 1629 } 1630 1631 if (status & XHCI_STS_HCE) { 1632 printf("%s: host controller error\n", 1633 __FUNCTION__); 1634 } 1635 } 1636 USB_BUS_UNLOCK(&sc->sc_bus); 1637 } 1638 1639 /*------------------------------------------------------------------------* 1640 * xhci_timeout - XHCI timeout handler 1641 *------------------------------------------------------------------------*/ 1642 static void 1643 xhci_timeout(void *arg) 1644 { 1645 struct usb_xfer *xfer = arg; 1646 1647 DPRINTF("xfer=%p\n", xfer); 1648 1649 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1650 1651 /* transfer is transferred */ 1652 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1653 } 1654 1655 static void 1656 xhci_do_poll(struct usb_bus *bus) 1657 { 1658 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1659 1660 USB_BUS_LOCK(&sc->sc_bus); 1661 xhci_interrupt_poll(sc); 1662 USB_BUS_UNLOCK(&sc->sc_bus); 1663 } 1664 1665 static void 1666 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1667 { 1668 struct usb_page_search buf_res; 1669 struct xhci_td *td; 1670 struct xhci_td *td_next; 1671 struct xhci_td *td_alt_next; 1672 struct xhci_td *td_first; 1673 uint32_t buf_offset; 1674 uint32_t average; 1675 uint32_t len_old; 1676 uint32_t npkt_off; 1677 uint32_t dword; 1678 uint8_t shortpkt_old; 1679 uint8_t precompute; 1680 uint8_t x; 1681 1682 td_alt_next = NULL; 1683 buf_offset = 0; 1684 shortpkt_old = temp->shortpkt; 1685 len_old = temp->len; 1686 npkt_off = 0; 1687 precompute = 1; 1688 1689 restart: 1690 1691 td = temp->td; 1692 td_next = td_first = temp->td_next; 1693 1694 while (1) { 1695 1696 if (temp->len == 0) { 1697 1698 if (temp->shortpkt) 1699 break; 1700 1701 /* send a Zero Length Packet, ZLP, last */ 1702 1703 temp->shortpkt = 1; 1704 average = 0; 1705 1706 } else { 1707 1708 average = temp->average; 1709 1710 if (temp->len < average) { 1711 if (temp->len % temp->max_packet_size) { 1712 temp->shortpkt = 1; 1713 } 1714 average = temp->len; 1715 } 1716 } 1717 1718 if (td_next == NULL) 1719 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1720 1721 /* get next TD */ 1722 1723 td = td_next; 1724 td_next = td->obj_next; 1725 1726 /* check if we are pre-computing */ 1727 1728 if (precompute) { 1729 1730 /* update remaining length */ 1731 1732 temp->len -= average; 1733 1734 continue; 1735 } 1736 /* fill out current TD */ 1737 1738 td->len = average; 1739 td->remainder = 0; 1740 td->status = 0; 1741 1742 /* update remaining length */ 1743 1744 temp->len -= average; 1745 1746 /* reset TRB index */ 1747 1748 x = 0; 1749 1750 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1751 /* immediate data */ 1752 1753 if (average > 8) 1754 average = 8; 1755 1756 td->td_trb[0].qwTrb0 = 0; 1757 1758 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1759 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1760 average); 1761 1762 dword = XHCI_TRB_2_BYTES_SET(8) | 1763 XHCI_TRB_2_TDSZ_SET(0) | 1764 XHCI_TRB_2_IRQ_SET(0); 1765 1766 td->td_trb[0].dwTrb2 = htole32(dword); 1767 1768 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1769 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1770 1771 /* check wLength */ 1772 if (td->td_trb[0].qwTrb0 & 1773 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1774 if (td->td_trb[0].qwTrb0 & 1775 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1776 dword |= XHCI_TRB_3_TRT_IN; 1777 else 1778 dword |= XHCI_TRB_3_TRT_OUT; 1779 } 1780 1781 td->td_trb[0].dwTrb3 = htole32(dword); 1782 #ifdef USB_DEBUG 1783 xhci_dump_trb(&td->td_trb[x]); 1784 #endif 1785 x++; 1786 1787 } else do { 1788 1789 uint32_t npkt; 1790 1791 /* fill out buffer pointers */ 1792 1793 if (average == 0) { 1794 memset(&buf_res, 0, sizeof(buf_res)); 1795 } else { 1796 usbd_get_page(temp->pc, temp->offset + 1797 buf_offset, &buf_res); 1798 1799 /* get length to end of page */ 1800 if (buf_res.length > average) 1801 buf_res.length = average; 1802 1803 /* check for maximum length */ 1804 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1805 buf_res.length = XHCI_TD_PAGE_SIZE; 1806 1807 npkt_off += buf_res.length; 1808 } 1809 1810 /* setup npkt */ 1811 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1812 temp->max_packet_size; 1813 1814 if (npkt == 0) 1815 npkt = 1; 1816 else if (npkt > 31) 1817 npkt = 31; 1818 1819 /* fill out TRB's */ 1820 td->td_trb[x].qwTrb0 = 1821 htole64((uint64_t)buf_res.physaddr); 1822 1823 dword = 1824 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1825 XHCI_TRB_2_TDSZ_SET(npkt) | 1826 XHCI_TRB_2_IRQ_SET(0); 1827 1828 td->td_trb[x].dwTrb2 = htole32(dword); 1829 1830 switch (temp->trb_type) { 1831 case XHCI_TRB_TYPE_ISOCH: 1832 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1833 XHCI_TRB_3_TBC_SET(temp->tbc) | 1834 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1835 if (td != td_first) { 1836 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1837 } else if (temp->do_isoc_sync != 0) { 1838 temp->do_isoc_sync = 0; 1839 /* wait until "isoc_frame" */ 1840 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1841 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1842 } else { 1843 /* start data transfer at next interval */ 1844 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1845 XHCI_TRB_3_ISO_SIA_BIT; 1846 } 1847 if (temp->direction == UE_DIR_IN) 1848 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1849 break; 1850 case XHCI_TRB_TYPE_DATA_STAGE: 1851 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1852 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 1853 XHCI_TRB_3_TBC_SET(temp->tbc) | 1854 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1855 if (temp->direction == UE_DIR_IN) 1856 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1857 break; 1858 case XHCI_TRB_TYPE_STATUS_STAGE: 1859 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1860 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 1861 XHCI_TRB_3_TBC_SET(temp->tbc) | 1862 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1863 if (temp->direction == UE_DIR_IN) 1864 dword |= XHCI_TRB_3_DIR_IN; 1865 break; 1866 default: /* XHCI_TRB_TYPE_NORMAL */ 1867 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1868 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 1869 XHCI_TRB_3_TBC_SET(temp->tbc) | 1870 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1871 if (temp->direction == UE_DIR_IN) 1872 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1873 break; 1874 } 1875 td->td_trb[x].dwTrb3 = htole32(dword); 1876 1877 average -= buf_res.length; 1878 buf_offset += buf_res.length; 1879 #ifdef USB_DEBUG 1880 xhci_dump_trb(&td->td_trb[x]); 1881 #endif 1882 x++; 1883 1884 } while (average != 0); 1885 1886 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1887 1888 /* store number of data TRB's */ 1889 1890 td->ntrb = x; 1891 1892 DPRINTF("NTRB=%u\n", x); 1893 1894 /* fill out link TRB */ 1895 1896 if (td_next != NULL) { 1897 /* link the current TD with the next one */ 1898 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1899 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1900 } else { 1901 /* this field will get updated later */ 1902 DPRINTF("NOLINK\n"); 1903 } 1904 1905 dword = XHCI_TRB_2_IRQ_SET(0); 1906 1907 td->td_trb[x].dwTrb2 = htole32(dword); 1908 1909 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1910 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1911 /* 1912 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1913 * frame only receives a single short packet event 1914 * by setting the CHAIN bit in the LINK field. In 1915 * addition some XHCI controllers have problems 1916 * sending a ZLP unless the CHAIN-BIT is set in 1917 * the LINK TRB. 1918 */ 1919 XHCI_TRB_3_CHAIN_BIT; 1920 1921 td->td_trb[x].dwTrb3 = htole32(dword); 1922 1923 td->alt_next = td_alt_next; 1924 #ifdef USB_DEBUG 1925 xhci_dump_trb(&td->td_trb[x]); 1926 #endif 1927 usb_pc_cpu_flush(td->page_cache); 1928 } 1929 1930 if (precompute) { 1931 precompute = 0; 1932 1933 /* setup alt next pointer, if any */ 1934 if (temp->last_frame) { 1935 td_alt_next = NULL; 1936 } else { 1937 /* we use this field internally */ 1938 td_alt_next = td_next; 1939 } 1940 1941 /* restore */ 1942 temp->shortpkt = shortpkt_old; 1943 temp->len = len_old; 1944 goto restart; 1945 } 1946 1947 /* 1948 * Remove cycle bit from the first TRB if we are 1949 * stepping them: 1950 */ 1951 if (temp->step_td != 0) { 1952 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1953 usb_pc_cpu_flush(td_first->page_cache); 1954 } 1955 1956 /* clear TD SIZE to zero, hence this is the last TRB */ 1957 /* remove chain bit because this is the last data TRB in the chain */ 1958 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1959 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1960 /* remove CHAIN-BIT from last LINK TRB */ 1961 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1962 1963 usb_pc_cpu_flush(td->page_cache); 1964 1965 temp->td = td; 1966 temp->td_next = td_next; 1967 } 1968 1969 static void 1970 xhci_setup_generic_chain(struct usb_xfer *xfer) 1971 { 1972 struct xhci_std_temp temp; 1973 struct xhci_td *td; 1974 uint32_t x; 1975 uint32_t y; 1976 uint8_t mult; 1977 1978 temp.do_isoc_sync = 0; 1979 temp.step_td = 0; 1980 temp.tbc = 0; 1981 temp.tlbpc = 0; 1982 temp.average = xfer->max_hc_frame_size; 1983 temp.max_packet_size = xfer->max_packet_size; 1984 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1985 temp.pc = NULL; 1986 temp.last_frame = 0; 1987 temp.offset = 0; 1988 temp.multishort = xfer->flags_int.isochronous_xfr || 1989 xfer->flags_int.control_xfr || 1990 xfer->flags_int.short_frames_ok; 1991 1992 /* toggle the DMA set we are using */ 1993 xfer->flags_int.curr_dma_set ^= 1; 1994 1995 /* get next DMA set */ 1996 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1997 1998 temp.td = NULL; 1999 temp.td_next = td; 2000 2001 xfer->td_transfer_first = td; 2002 xfer->td_transfer_cache = td; 2003 2004 if (xfer->flags_int.isochronous_xfr) { 2005 uint8_t shift; 2006 2007 /* compute multiplier for ISOCHRONOUS transfers */ 2008 mult = xfer->endpoint->ecomp ? 2009 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2010 : 0; 2011 /* check for USB 2.0 multiplier */ 2012 if (mult == 0) { 2013 mult = (xfer->endpoint->edesc-> 2014 wMaxPacketSize[1] >> 3) & 3; 2015 } 2016 /* range check */ 2017 if (mult > 2) 2018 mult = 3; 2019 else 2020 mult++; 2021 2022 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2023 2024 DPRINTF("MFINDEX=0x%08x\n", x); 2025 2026 switch (usbd_get_speed(xfer->xroot->udev)) { 2027 case USB_SPEED_FULL: 2028 shift = 3; 2029 temp.isoc_delta = 8; /* 1ms */ 2030 x += temp.isoc_delta - 1; 2031 x &= ~(temp.isoc_delta - 1); 2032 break; 2033 default: 2034 shift = usbd_xfer_get_fps_shift(xfer); 2035 temp.isoc_delta = 1U << shift; 2036 x += temp.isoc_delta - 1; 2037 x &= ~(temp.isoc_delta - 1); 2038 /* simple frame load balancing */ 2039 x += xfer->endpoint->usb_uframe; 2040 break; 2041 } 2042 2043 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2044 2045 if ((xfer->endpoint->is_synced == 0) || 2046 (y < (xfer->nframes << shift)) || 2047 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2048 /* 2049 * If there is data underflow or the pipe 2050 * queue is empty we schedule the transfer a 2051 * few frames ahead of the current frame 2052 * position. Else two isochronous transfers 2053 * might overlap. 2054 */ 2055 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2056 xfer->endpoint->is_synced = 1; 2057 temp.do_isoc_sync = 1; 2058 2059 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2060 } 2061 2062 /* compute isochronous completion time */ 2063 2064 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2065 2066 xfer->isoc_time_complete = 2067 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2068 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2069 2070 x = 0; 2071 temp.isoc_frame = xfer->endpoint->isoc_next; 2072 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2073 2074 xfer->endpoint->isoc_next += xfer->nframes << shift; 2075 2076 } else if (xfer->flags_int.control_xfr) { 2077 2078 /* check if we should prepend a setup message */ 2079 2080 if (xfer->flags_int.control_hdr) { 2081 2082 temp.len = xfer->frlengths[0]; 2083 temp.pc = xfer->frbuffers + 0; 2084 temp.shortpkt = temp.len ? 1 : 0; 2085 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2086 temp.direction = 0; 2087 2088 /* check for last frame */ 2089 if (xfer->nframes == 1) { 2090 /* no STATUS stage yet, SETUP is last */ 2091 if (xfer->flags_int.control_act) 2092 temp.last_frame = 1; 2093 } 2094 2095 xhci_setup_generic_chain_sub(&temp); 2096 } 2097 x = 1; 2098 mult = 1; 2099 temp.isoc_delta = 0; 2100 temp.isoc_frame = 0; 2101 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 2102 } else { 2103 x = 0; 2104 mult = 1; 2105 temp.isoc_delta = 0; 2106 temp.isoc_frame = 0; 2107 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2108 } 2109 2110 if (x != xfer->nframes) { 2111 /* setup page_cache pointer */ 2112 temp.pc = xfer->frbuffers + x; 2113 /* set endpoint direction */ 2114 temp.direction = UE_GET_DIR(xfer->endpointno); 2115 } 2116 2117 while (x != xfer->nframes) { 2118 2119 /* DATA0 / DATA1 message */ 2120 2121 temp.len = xfer->frlengths[x]; 2122 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2123 x != 0 && temp.multishort == 0); 2124 2125 x++; 2126 2127 if (x == xfer->nframes) { 2128 if (xfer->flags_int.control_xfr) { 2129 /* no STATUS stage yet, DATA is last */ 2130 if (xfer->flags_int.control_act) 2131 temp.last_frame = 1; 2132 } else { 2133 temp.last_frame = 1; 2134 } 2135 } 2136 if (temp.len == 0) { 2137 2138 /* make sure that we send an USB packet */ 2139 2140 temp.shortpkt = 0; 2141 2142 temp.tbc = 0; 2143 temp.tlbpc = mult - 1; 2144 2145 } else if (xfer->flags_int.isochronous_xfr) { 2146 2147 uint8_t tdpc; 2148 2149 /* 2150 * Isochronous transfers don't have short 2151 * packet termination: 2152 */ 2153 2154 temp.shortpkt = 1; 2155 2156 /* isochronous transfers have a transfer limit */ 2157 2158 if (temp.len > xfer->max_frame_size) 2159 temp.len = xfer->max_frame_size; 2160 2161 /* compute TD packet count */ 2162 tdpc = (temp.len + xfer->max_packet_size - 1) / 2163 xfer->max_packet_size; 2164 2165 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2166 temp.tlbpc = (tdpc % mult); 2167 2168 if (temp.tlbpc == 0) 2169 temp.tlbpc = mult - 1; 2170 else 2171 temp.tlbpc--; 2172 } else { 2173 2174 /* regular data transfer */ 2175 2176 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2177 } 2178 2179 xhci_setup_generic_chain_sub(&temp); 2180 2181 if (xfer->flags_int.isochronous_xfr) { 2182 temp.offset += xfer->frlengths[x - 1]; 2183 temp.isoc_frame += temp.isoc_delta; 2184 } else { 2185 /* get next Page Cache pointer */ 2186 temp.pc = xfer->frbuffers + x; 2187 } 2188 } 2189 2190 /* check if we should append a status stage */ 2191 2192 if (xfer->flags_int.control_xfr && 2193 !xfer->flags_int.control_act) { 2194 2195 /* 2196 * Send a DATA1 message and invert the current 2197 * endpoint direction. 2198 */ 2199 temp.step_td = (xfer->nframes != 0); 2200 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2201 temp.len = 0; 2202 temp.pc = NULL; 2203 temp.shortpkt = 0; 2204 temp.last_frame = 1; 2205 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2206 2207 xhci_setup_generic_chain_sub(&temp); 2208 } 2209 2210 td = temp.td; 2211 2212 /* must have at least one frame! */ 2213 2214 xfer->td_transfer_last = td; 2215 2216 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2217 } 2218 2219 static void 2220 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2221 { 2222 struct usb_page_search buf_res; 2223 struct xhci_dev_ctx_addr *pdctxa; 2224 2225 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2226 2227 pdctxa = buf_res.buffer; 2228 2229 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2230 2231 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2232 2233 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2234 } 2235 2236 static usb_error_t 2237 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2238 { 2239 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2240 struct usb_page_search buf_inp; 2241 struct xhci_input_dev_ctx *pinp; 2242 uint32_t temp; 2243 uint8_t index; 2244 uint8_t x; 2245 2246 index = udev->controller_slot_id; 2247 2248 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2249 2250 pinp = buf_inp.buffer; 2251 2252 if (drop) { 2253 mask &= XHCI_INCTX_NON_CTRL_MASK; 2254 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2255 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2256 } else { 2257 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2258 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2259 2260 /* find most significant set bit */ 2261 for (x = 31; x != 1; x--) { 2262 if (mask & (1 << x)) 2263 break; 2264 } 2265 2266 /* adjust */ 2267 x--; 2268 2269 /* figure out maximum */ 2270 if (x > sc->sc_hw.devs[index].context_num) { 2271 sc->sc_hw.devs[index].context_num = x; 2272 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2273 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2274 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2275 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2276 } 2277 } 2278 return (0); 2279 } 2280 2281 static usb_error_t 2282 xhci_configure_endpoint(struct usb_device *udev, 2283 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2284 uint16_t interval, uint8_t max_packet_count, 2285 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2286 uint16_t max_frame_size, uint8_t ep_mode) 2287 { 2288 struct usb_page_search buf_inp; 2289 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2290 struct xhci_input_dev_ctx *pinp; 2291 uint64_t ring_addr = pepext->physaddr; 2292 uint32_t temp; 2293 uint8_t index; 2294 uint8_t epno; 2295 uint8_t type; 2296 2297 index = udev->controller_slot_id; 2298 2299 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2300 2301 pinp = buf_inp.buffer; 2302 2303 epno = edesc->bEndpointAddress; 2304 type = edesc->bmAttributes & UE_XFERTYPE; 2305 2306 if (type == UE_CONTROL) 2307 epno |= UE_DIR_IN; 2308 2309 epno = XHCI_EPNO2EPID(epno); 2310 2311 if (epno == 0) 2312 return (USB_ERR_NO_PIPE); /* invalid */ 2313 2314 if (max_packet_count == 0) 2315 return (USB_ERR_BAD_BUFSIZE); 2316 2317 max_packet_count--; 2318 2319 if (mult == 0) 2320 return (USB_ERR_BAD_BUFSIZE); 2321 2322 /* store endpoint mode */ 2323 pepext->trb_ep_mode = ep_mode; 2324 usb_pc_cpu_flush(pepext->page_cache); 2325 2326 if (ep_mode == USB_EP_MODE_STREAMS) { 2327 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2328 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2329 XHCI_EPCTX_0_LSA_SET(1); 2330 2331 ring_addr += sizeof(struct xhci_trb) * 2332 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2333 } else { 2334 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2335 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2336 XHCI_EPCTX_0_LSA_SET(0); 2337 2338 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2339 } 2340 2341 switch (udev->speed) { 2342 case USB_SPEED_FULL: 2343 case USB_SPEED_LOW: 2344 /* 1ms -> 125us */ 2345 fps_shift += 3; 2346 break; 2347 default: 2348 break; 2349 } 2350 2351 switch (type) { 2352 case UE_INTERRUPT: 2353 if (fps_shift > 3) 2354 fps_shift--; 2355 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2356 break; 2357 case UE_ISOCHRONOUS: 2358 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2359 2360 switch (udev->speed) { 2361 case USB_SPEED_SUPER: 2362 if (mult > 3) 2363 mult = 3; 2364 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2365 max_packet_count /= mult; 2366 break; 2367 default: 2368 break; 2369 } 2370 break; 2371 default: 2372 break; 2373 } 2374 2375 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2376 2377 temp = 2378 XHCI_EPCTX_1_HID_SET(0) | 2379 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2380 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2381 2382 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2383 if (type != UE_ISOCHRONOUS) 2384 temp |= XHCI_EPCTX_1_CERR_SET(3); 2385 } 2386 2387 switch (type) { 2388 case UE_CONTROL: 2389 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2390 break; 2391 case UE_ISOCHRONOUS: 2392 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2393 break; 2394 case UE_BULK: 2395 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2396 break; 2397 default: 2398 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2399 break; 2400 } 2401 2402 /* check for IN direction */ 2403 if (epno & 1) 2404 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2405 2406 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2407 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2408 2409 switch (edesc->bmAttributes & UE_XFERTYPE) { 2410 case UE_INTERRUPT: 2411 case UE_ISOCHRONOUS: 2412 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2413 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2414 max_frame_size)); 2415 break; 2416 case UE_CONTROL: 2417 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2418 break; 2419 default: 2420 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2421 break; 2422 } 2423 2424 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2425 2426 #ifdef USB_DEBUG 2427 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2428 #endif 2429 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2430 2431 return (0); /* success */ 2432 } 2433 2434 static usb_error_t 2435 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2436 { 2437 struct xhci_endpoint_ext *pepext; 2438 struct usb_endpoint_ss_comp_descriptor *ecomp; 2439 usb_stream_t x; 2440 2441 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2442 xfer->endpoint->edesc); 2443 2444 ecomp = xfer->endpoint->ecomp; 2445 2446 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2447 uint64_t temp; 2448 2449 /* halt any transfers */ 2450 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2451 2452 /* compute start of TRB ring for stream "x" */ 2453 temp = pepext->physaddr + 2454 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2455 XHCI_SCTX_0_SCT_SEC_TR_RING; 2456 2457 /* make tree structure */ 2458 pepext->trb[(XHCI_MAX_TRANSFERS * 2459 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2460 2461 /* reserved fields */ 2462 pepext->trb[(XHCI_MAX_TRANSFERS * 2463 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2464 pepext->trb[(XHCI_MAX_TRANSFERS * 2465 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2466 } 2467 usb_pc_cpu_flush(pepext->page_cache); 2468 2469 return (xhci_configure_endpoint(xfer->xroot->udev, 2470 xfer->endpoint->edesc, pepext, 2471 xfer->interval, xfer->max_packet_count, 2472 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2473 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2474 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2475 } 2476 2477 static usb_error_t 2478 xhci_configure_device(struct usb_device *udev) 2479 { 2480 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2481 struct usb_page_search buf_inp; 2482 struct usb_page_cache *pcinp; 2483 struct xhci_input_dev_ctx *pinp; 2484 struct usb_device *hubdev; 2485 uint32_t temp; 2486 uint32_t route; 2487 uint32_t rh_port; 2488 uint8_t is_hub; 2489 uint8_t index; 2490 uint8_t depth; 2491 2492 index = udev->controller_slot_id; 2493 2494 DPRINTF("index=%u\n", index); 2495 2496 pcinp = &sc->sc_hw.devs[index].input_pc; 2497 2498 usbd_get_page(pcinp, 0, &buf_inp); 2499 2500 pinp = buf_inp.buffer; 2501 2502 rh_port = 0; 2503 route = 0; 2504 2505 /* figure out route string and root HUB port number */ 2506 2507 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2508 2509 if (hubdev->parent_hub == NULL) 2510 break; 2511 2512 depth = hubdev->parent_hub->depth; 2513 2514 /* 2515 * NOTE: HS/FS/LS devices and the SS root HUB can have 2516 * more than 15 ports 2517 */ 2518 2519 rh_port = hubdev->port_no; 2520 2521 if (depth == 0) 2522 break; 2523 2524 if (rh_port > 15) 2525 rh_port = 15; 2526 2527 if (depth < 6) 2528 route |= rh_port << (4 * (depth - 1)); 2529 } 2530 2531 DPRINTF("Route=0x%08x\n", route); 2532 2533 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2534 XHCI_SCTX_0_CTX_NUM_SET( 2535 sc->sc_hw.devs[index].context_num + 1); 2536 2537 switch (udev->speed) { 2538 case USB_SPEED_LOW: 2539 temp |= XHCI_SCTX_0_SPEED_SET(2); 2540 if (udev->parent_hs_hub != NULL && 2541 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2542 UDPROTO_HSHUBMTT) { 2543 DPRINTF("Device inherits MTT\n"); 2544 temp |= XHCI_SCTX_0_MTT_SET(1); 2545 } 2546 break; 2547 case USB_SPEED_HIGH: 2548 temp |= XHCI_SCTX_0_SPEED_SET(3); 2549 if (sc->sc_hw.devs[index].nports != 0 && 2550 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2551 DPRINTF("HUB supports MTT\n"); 2552 temp |= XHCI_SCTX_0_MTT_SET(1); 2553 } 2554 break; 2555 case USB_SPEED_FULL: 2556 temp |= XHCI_SCTX_0_SPEED_SET(1); 2557 if (udev->parent_hs_hub != NULL && 2558 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2559 UDPROTO_HSHUBMTT) { 2560 DPRINTF("Device inherits MTT\n"); 2561 temp |= XHCI_SCTX_0_MTT_SET(1); 2562 } 2563 break; 2564 default: 2565 temp |= XHCI_SCTX_0_SPEED_SET(4); 2566 break; 2567 } 2568 2569 is_hub = sc->sc_hw.devs[index].nports != 0 && 2570 (udev->speed == USB_SPEED_SUPER || 2571 udev->speed == USB_SPEED_HIGH); 2572 2573 if (is_hub) 2574 temp |= XHCI_SCTX_0_HUB_SET(1); 2575 2576 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2577 2578 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2579 2580 if (is_hub) { 2581 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2582 sc->sc_hw.devs[index].nports); 2583 } 2584 2585 switch (udev->speed) { 2586 case USB_SPEED_SUPER: 2587 switch (sc->sc_hw.devs[index].state) { 2588 case XHCI_ST_ADDRESSED: 2589 case XHCI_ST_CONFIGURED: 2590 /* enable power save */ 2591 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2592 break; 2593 default: 2594 /* disable power save */ 2595 break; 2596 } 2597 break; 2598 default: 2599 break; 2600 } 2601 2602 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2603 2604 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2605 2606 if (is_hub) { 2607 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2608 sc->sc_hw.devs[index].tt); 2609 } 2610 2611 hubdev = udev->parent_hs_hub; 2612 2613 /* check if we should activate the transaction translator */ 2614 switch (udev->speed) { 2615 case USB_SPEED_FULL: 2616 case USB_SPEED_LOW: 2617 if (hubdev != NULL) { 2618 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2619 hubdev->controller_slot_id); 2620 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2621 udev->hs_port_no); 2622 } 2623 break; 2624 default: 2625 break; 2626 } 2627 2628 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2629 2630 /* 2631 * These fields should be initialized to zero, according to 2632 * XHCI section 6.2.2 - slot context: 2633 */ 2634 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2635 XHCI_SCTX_3_SLOT_STATE_SET(0); 2636 2637 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2638 2639 #ifdef USB_DEBUG 2640 xhci_dump_device(sc, &pinp->ctx_slot); 2641 #endif 2642 usb_pc_cpu_flush(pcinp); 2643 2644 return (0); /* success */ 2645 } 2646 2647 static usb_error_t 2648 xhci_alloc_device_ext(struct usb_device *udev) 2649 { 2650 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2651 struct usb_page_search buf_dev; 2652 struct usb_page_search buf_ep; 2653 struct xhci_trb *trb; 2654 struct usb_page_cache *pc; 2655 struct usb_page *pg; 2656 uint64_t addr; 2657 uint8_t index; 2658 uint8_t i; 2659 2660 index = udev->controller_slot_id; 2661 2662 pc = &sc->sc_hw.devs[index].device_pc; 2663 pg = &sc->sc_hw.devs[index].device_pg; 2664 2665 /* need to initialize the page cache */ 2666 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2667 2668 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2669 (2 * sizeof(struct xhci_dev_ctx)) : 2670 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2671 goto error; 2672 2673 usbd_get_page(pc, 0, &buf_dev); 2674 2675 pc = &sc->sc_hw.devs[index].input_pc; 2676 pg = &sc->sc_hw.devs[index].input_pg; 2677 2678 /* need to initialize the page cache */ 2679 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2680 2681 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2682 (2 * sizeof(struct xhci_input_dev_ctx)) : 2683 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2684 goto error; 2685 } 2686 2687 pc = &sc->sc_hw.devs[index].endpoint_pc; 2688 pg = &sc->sc_hw.devs[index].endpoint_pg; 2689 2690 /* need to initialize the page cache */ 2691 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2692 2693 if (usb_pc_alloc_mem(pc, pg, 2694 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) { 2695 goto error; 2696 } 2697 2698 /* initialise all endpoint LINK TRBs */ 2699 2700 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2701 2702 /* lookup endpoint TRB ring */ 2703 usbd_get_page(pc, (uintptr_t)& 2704 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2705 2706 /* get TRB pointer */ 2707 trb = buf_ep.buffer; 2708 trb += XHCI_MAX_TRANSFERS - 1; 2709 2710 /* get TRB start address */ 2711 addr = buf_ep.physaddr; 2712 2713 /* create LINK TRB */ 2714 trb->qwTrb0 = htole64(addr); 2715 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2716 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2717 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2718 } 2719 2720 usb_pc_cpu_flush(pc); 2721 2722 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2723 2724 return (0); 2725 2726 error: 2727 xhci_free_device_ext(udev); 2728 2729 return (USB_ERR_NOMEM); 2730 } 2731 2732 static void 2733 xhci_free_device_ext(struct usb_device *udev) 2734 { 2735 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2736 uint8_t index; 2737 2738 index = udev->controller_slot_id; 2739 xhci_set_slot_pointer(sc, index, 0); 2740 2741 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2742 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2743 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2744 } 2745 2746 static struct xhci_endpoint_ext * 2747 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2748 { 2749 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2750 struct xhci_endpoint_ext *pepext; 2751 struct usb_page_cache *pc; 2752 struct usb_page_search buf_ep; 2753 uint8_t epno; 2754 uint8_t index; 2755 2756 epno = edesc->bEndpointAddress; 2757 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2758 epno |= UE_DIR_IN; 2759 2760 epno = XHCI_EPNO2EPID(epno); 2761 2762 index = udev->controller_slot_id; 2763 2764 pc = &sc->sc_hw.devs[index].endpoint_pc; 2765 2766 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2767 trb[epno][0], &buf_ep); 2768 2769 pepext = &sc->sc_hw.devs[index].endp[epno]; 2770 pepext->page_cache = pc; 2771 pepext->trb = buf_ep.buffer; 2772 pepext->physaddr = buf_ep.physaddr; 2773 2774 return (pepext); 2775 } 2776 2777 static void 2778 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2779 { 2780 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2781 uint8_t epno; 2782 uint8_t index; 2783 2784 epno = xfer->endpointno; 2785 if (xfer->flags_int.control_xfr) 2786 epno |= UE_DIR_IN; 2787 2788 epno = XHCI_EPNO2EPID(epno); 2789 index = xfer->xroot->udev->controller_slot_id; 2790 2791 if (xfer->xroot->udev->flags.self_suspended == 0) { 2792 XWRITE4(sc, door, XHCI_DOORBELL(index), 2793 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2794 } 2795 } 2796 2797 static void 2798 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2799 { 2800 struct xhci_endpoint_ext *pepext; 2801 2802 if (xfer->flags_int.bandwidth_reclaimed) { 2803 xfer->flags_int.bandwidth_reclaimed = 0; 2804 2805 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2806 xfer->endpoint->edesc); 2807 2808 pepext->trb_used[xfer->stream_id]--; 2809 2810 pepext->xfer[xfer->qh_pos] = NULL; 2811 2812 if (error && pepext->trb_running != 0) { 2813 pepext->trb_halted = 1; 2814 pepext->trb_running = 0; 2815 } 2816 } 2817 } 2818 2819 static usb_error_t 2820 xhci_transfer_insert(struct usb_xfer *xfer) 2821 { 2822 struct xhci_td *td_first; 2823 struct xhci_td *td_last; 2824 struct xhci_trb *trb_link; 2825 struct xhci_endpoint_ext *pepext; 2826 uint64_t addr; 2827 usb_stream_t id; 2828 uint8_t i; 2829 uint8_t inext; 2830 uint8_t trb_limit; 2831 2832 DPRINTFN(8, "\n"); 2833 2834 id = xfer->stream_id; 2835 2836 /* check if already inserted */ 2837 if (xfer->flags_int.bandwidth_reclaimed) { 2838 DPRINTFN(8, "Already in schedule\n"); 2839 return (0); 2840 } 2841 2842 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2843 xfer->endpoint->edesc); 2844 2845 td_first = xfer->td_transfer_first; 2846 td_last = xfer->td_transfer_last; 2847 addr = pepext->physaddr; 2848 2849 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2850 case UE_CONTROL: 2851 case UE_INTERRUPT: 2852 /* single buffered */ 2853 trb_limit = 1; 2854 break; 2855 default: 2856 /* multi buffered */ 2857 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2858 break; 2859 } 2860 2861 if (pepext->trb_used[id] >= trb_limit) { 2862 DPRINTFN(8, "Too many TDs queued.\n"); 2863 return (USB_ERR_NOMEM); 2864 } 2865 2866 /* check for stopped condition, after putting transfer on interrupt queue */ 2867 if (pepext->trb_running == 0) { 2868 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2869 2870 DPRINTFN(8, "Not running\n"); 2871 2872 /* start configuration */ 2873 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2874 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2875 return (0); 2876 } 2877 2878 pepext->trb_used[id]++; 2879 2880 /* get current TRB index */ 2881 i = pepext->trb_index[id]; 2882 2883 /* get next TRB index */ 2884 inext = (i + 1); 2885 2886 /* the last entry of the ring is a hardcoded link TRB */ 2887 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2888 inext = 0; 2889 2890 /* store next TRB index, before stream ID offset is added */ 2891 pepext->trb_index[id] = inext; 2892 2893 /* offset for stream */ 2894 i += id * XHCI_MAX_TRANSFERS; 2895 inext += id * XHCI_MAX_TRANSFERS; 2896 2897 /* compute terminating return address */ 2898 addr += (inext * sizeof(struct xhci_trb)); 2899 2900 /* compute link TRB pointer */ 2901 trb_link = td_last->td_trb + td_last->ntrb; 2902 2903 /* update next pointer of last link TRB */ 2904 trb_link->qwTrb0 = htole64(addr); 2905 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2906 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2907 XHCI_TRB_3_CYCLE_BIT | 2908 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2909 2910 #ifdef USB_DEBUG 2911 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2912 #endif 2913 usb_pc_cpu_flush(td_last->page_cache); 2914 2915 /* write ahead chain end marker */ 2916 2917 pepext->trb[inext].qwTrb0 = 0; 2918 pepext->trb[inext].dwTrb2 = 0; 2919 pepext->trb[inext].dwTrb3 = 0; 2920 2921 /* update next pointer of link TRB */ 2922 2923 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2924 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2925 2926 #ifdef USB_DEBUG 2927 xhci_dump_trb(&pepext->trb[i]); 2928 #endif 2929 usb_pc_cpu_flush(pepext->page_cache); 2930 2931 /* toggle cycle bit which activates the transfer chain */ 2932 2933 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2934 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2935 2936 usb_pc_cpu_flush(pepext->page_cache); 2937 2938 DPRINTF("qh_pos = %u\n", i); 2939 2940 pepext->xfer[i] = xfer; 2941 2942 xfer->qh_pos = i; 2943 2944 xfer->flags_int.bandwidth_reclaimed = 1; 2945 2946 xhci_endpoint_doorbell(xfer); 2947 2948 return (0); 2949 } 2950 2951 static void 2952 xhci_root_intr(struct xhci_softc *sc) 2953 { 2954 uint16_t i; 2955 2956 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2957 2958 /* clear any old interrupt data */ 2959 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2960 2961 for (i = 1; i <= sc->sc_noport; i++) { 2962 /* pick out CHANGE bits from the status register */ 2963 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2964 XHCI_PS_CSC | XHCI_PS_PEC | 2965 XHCI_PS_OCC | XHCI_PS_WRC | 2966 XHCI_PS_PRC | XHCI_PS_PLC | 2967 XHCI_PS_CEC)) { 2968 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2969 DPRINTF("port %d changed\n", i); 2970 } 2971 } 2972 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2973 sizeof(sc->sc_hub_idata)); 2974 } 2975 2976 /*------------------------------------------------------------------------* 2977 * xhci_device_done - XHCI done handler 2978 * 2979 * NOTE: This function can be called two times in a row on 2980 * the same USB transfer. From close and from interrupt. 2981 *------------------------------------------------------------------------*/ 2982 static void 2983 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2984 { 2985 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2986 xfer, xfer->endpoint, error); 2987 2988 /* remove transfer from HW queue */ 2989 xhci_transfer_remove(xfer, error); 2990 2991 /* dequeue transfer and start next transfer */ 2992 usbd_transfer_done(xfer, error); 2993 } 2994 2995 /*------------------------------------------------------------------------* 2996 * XHCI data transfer support (generic type) 2997 *------------------------------------------------------------------------*/ 2998 static void 2999 xhci_device_generic_open(struct usb_xfer *xfer) 3000 { 3001 if (xfer->flags_int.isochronous_xfr) { 3002 switch (xfer->xroot->udev->speed) { 3003 case USB_SPEED_FULL: 3004 break; 3005 default: 3006 usb_hs_bandwidth_alloc(xfer); 3007 break; 3008 } 3009 } 3010 } 3011 3012 static void 3013 xhci_device_generic_close(struct usb_xfer *xfer) 3014 { 3015 DPRINTF("\n"); 3016 3017 xhci_device_done(xfer, USB_ERR_CANCELLED); 3018 3019 if (xfer->flags_int.isochronous_xfr) { 3020 switch (xfer->xroot->udev->speed) { 3021 case USB_SPEED_FULL: 3022 break; 3023 default: 3024 usb_hs_bandwidth_free(xfer); 3025 break; 3026 } 3027 } 3028 } 3029 3030 static void 3031 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3032 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3033 { 3034 struct usb_xfer *xfer; 3035 3036 /* check if there is a current transfer */ 3037 xfer = ep->endpoint_q[stream_id].curr; 3038 if (xfer == NULL) 3039 return; 3040 3041 /* 3042 * Check if the current transfer is started and then pickup 3043 * the next one, if any. Else wait for next start event due to 3044 * block on failure feature. 3045 */ 3046 if (!xfer->flags_int.bandwidth_reclaimed) 3047 return; 3048 3049 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3050 if (xfer == NULL) { 3051 /* 3052 * In case of enter we have to consider that the 3053 * transfer is queued by the USB core after the enter 3054 * method is called. 3055 */ 3056 xfer = enter_xfer; 3057 3058 if (xfer == NULL) 3059 return; 3060 } 3061 3062 /* try to multi buffer */ 3063 xhci_transfer_insert(xfer); 3064 } 3065 3066 static void 3067 xhci_device_generic_enter(struct usb_xfer *xfer) 3068 { 3069 DPRINTF("\n"); 3070 3071 /* setup TD's and QH */ 3072 xhci_setup_generic_chain(xfer); 3073 3074 xhci_device_generic_multi_enter(xfer->endpoint, 3075 xfer->stream_id, xfer); 3076 } 3077 3078 static void 3079 xhci_device_generic_start(struct usb_xfer *xfer) 3080 { 3081 DPRINTF("\n"); 3082 3083 /* try to insert xfer on HW queue */ 3084 xhci_transfer_insert(xfer); 3085 3086 /* try to multi buffer */ 3087 xhci_device_generic_multi_enter(xfer->endpoint, 3088 xfer->stream_id, NULL); 3089 3090 /* add transfer last on interrupt queue */ 3091 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3092 3093 /* start timeout, if any */ 3094 if (xfer->timeout != 0) 3095 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3096 } 3097 3098 static const struct usb_pipe_methods xhci_device_generic_methods = 3099 { 3100 .open = xhci_device_generic_open, 3101 .close = xhci_device_generic_close, 3102 .enter = xhci_device_generic_enter, 3103 .start = xhci_device_generic_start, 3104 }; 3105 3106 /*------------------------------------------------------------------------* 3107 * xhci root HUB support 3108 *------------------------------------------------------------------------* 3109 * Simulate a hardware HUB by handling all the necessary requests. 3110 *------------------------------------------------------------------------*/ 3111 3112 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3113 3114 static const 3115 struct usb_device_descriptor xhci_devd = 3116 { 3117 .bLength = sizeof(xhci_devd), 3118 .bDescriptorType = UDESC_DEVICE, /* type */ 3119 HSETW(.bcdUSB, 0x0300), /* USB version */ 3120 .bDeviceClass = UDCLASS_HUB, /* class */ 3121 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3122 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3123 .bMaxPacketSize = 9, /* max packet size */ 3124 HSETW(.idVendor, 0x0000), /* vendor */ 3125 HSETW(.idProduct, 0x0000), /* product */ 3126 HSETW(.bcdDevice, 0x0100), /* device version */ 3127 .iManufacturer = 1, 3128 .iProduct = 2, 3129 .iSerialNumber = 0, 3130 .bNumConfigurations = 1, /* # of configurations */ 3131 }; 3132 3133 static const 3134 struct xhci_bos_desc xhci_bosd = { 3135 .bosd = { 3136 .bLength = sizeof(xhci_bosd.bosd), 3137 .bDescriptorType = UDESC_BOS, 3138 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3139 .bNumDeviceCaps = 3, 3140 }, 3141 .usb2extd = { 3142 .bLength = sizeof(xhci_bosd.usb2extd), 3143 .bDescriptorType = 1, 3144 .bDevCapabilityType = 2, 3145 .bmAttributes[0] = 2, 3146 }, 3147 .usbdcd = { 3148 .bLength = sizeof(xhci_bosd.usbdcd), 3149 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3150 .bDevCapabilityType = 3, 3151 .bmAttributes = 0, /* XXX */ 3152 HSETW(.wSpeedsSupported, 0x000C), 3153 .bFunctionalitySupport = 8, 3154 .bU1DevExitLat = 255, /* dummy - not used */ 3155 .wU2DevExitLat = { 0x00, 0x08 }, 3156 }, 3157 .cidd = { 3158 .bLength = sizeof(xhci_bosd.cidd), 3159 .bDescriptorType = 1, 3160 .bDevCapabilityType = 4, 3161 .bReserved = 0, 3162 .bContainerID = 0, /* XXX */ 3163 }, 3164 }; 3165 3166 static const 3167 struct xhci_config_desc xhci_confd = { 3168 .confd = { 3169 .bLength = sizeof(xhci_confd.confd), 3170 .bDescriptorType = UDESC_CONFIG, 3171 .wTotalLength[0] = sizeof(xhci_confd), 3172 .bNumInterface = 1, 3173 .bConfigurationValue = 1, 3174 .iConfiguration = 0, 3175 .bmAttributes = UC_SELF_POWERED, 3176 .bMaxPower = 0 /* max power */ 3177 }, 3178 .ifcd = { 3179 .bLength = sizeof(xhci_confd.ifcd), 3180 .bDescriptorType = UDESC_INTERFACE, 3181 .bNumEndpoints = 1, 3182 .bInterfaceClass = UICLASS_HUB, 3183 .bInterfaceSubClass = UISUBCLASS_HUB, 3184 .bInterfaceProtocol = 0, 3185 }, 3186 .endpd = { 3187 .bLength = sizeof(xhci_confd.endpd), 3188 .bDescriptorType = UDESC_ENDPOINT, 3189 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3190 .bmAttributes = UE_INTERRUPT, 3191 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3192 .bInterval = 255, 3193 }, 3194 .endpcd = { 3195 .bLength = sizeof(xhci_confd.endpcd), 3196 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3197 .bMaxBurst = 0, 3198 .bmAttributes = 0, 3199 }, 3200 }; 3201 3202 static const 3203 struct usb_hub_ss_descriptor xhci_hubd = { 3204 .bLength = sizeof(xhci_hubd), 3205 .bDescriptorType = UDESC_SS_HUB, 3206 }; 3207 3208 static usb_error_t 3209 xhci_roothub_exec(struct usb_device *udev, 3210 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3211 { 3212 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3213 const char *str_ptr; 3214 const void *ptr; 3215 uint32_t port; 3216 uint32_t v; 3217 uint16_t len; 3218 uint16_t i; 3219 uint16_t value; 3220 uint16_t index; 3221 uint8_t j; 3222 usb_error_t err; 3223 3224 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3225 3226 /* buffer reset */ 3227 ptr = (const void *)&sc->sc_hub_desc; 3228 len = 0; 3229 err = 0; 3230 3231 value = UGETW(req->wValue); 3232 index = UGETW(req->wIndex); 3233 3234 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3235 "wValue=0x%04x wIndex=0x%04x\n", 3236 req->bmRequestType, req->bRequest, 3237 UGETW(req->wLength), value, index); 3238 3239 #define C(x,y) ((x) | ((y) << 8)) 3240 switch (C(req->bRequest, req->bmRequestType)) { 3241 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3242 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3243 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3244 /* 3245 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3246 * for the integrated root hub. 3247 */ 3248 break; 3249 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3250 len = 1; 3251 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3252 break; 3253 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3254 switch (value >> 8) { 3255 case UDESC_DEVICE: 3256 if ((value & 0xff) != 0) { 3257 err = USB_ERR_IOERROR; 3258 goto done; 3259 } 3260 len = sizeof(xhci_devd); 3261 ptr = (const void *)&xhci_devd; 3262 break; 3263 3264 case UDESC_BOS: 3265 if ((value & 0xff) != 0) { 3266 err = USB_ERR_IOERROR; 3267 goto done; 3268 } 3269 len = sizeof(xhci_bosd); 3270 ptr = (const void *)&xhci_bosd; 3271 break; 3272 3273 case UDESC_CONFIG: 3274 if ((value & 0xff) != 0) { 3275 err = USB_ERR_IOERROR; 3276 goto done; 3277 } 3278 len = sizeof(xhci_confd); 3279 ptr = (const void *)&xhci_confd; 3280 break; 3281 3282 case UDESC_STRING: 3283 switch (value & 0xff) { 3284 case 0: /* Language table */ 3285 str_ptr = "\001"; 3286 break; 3287 3288 case 1: /* Vendor */ 3289 str_ptr = sc->sc_vendor; 3290 break; 3291 3292 case 2: /* Product */ 3293 str_ptr = "XHCI root HUB"; 3294 break; 3295 3296 default: 3297 str_ptr = ""; 3298 break; 3299 } 3300 3301 len = usb_make_str_desc( 3302 sc->sc_hub_desc.temp, 3303 sizeof(sc->sc_hub_desc.temp), 3304 str_ptr); 3305 break; 3306 3307 default: 3308 err = USB_ERR_IOERROR; 3309 goto done; 3310 } 3311 break; 3312 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3313 len = 1; 3314 sc->sc_hub_desc.temp[0] = 0; 3315 break; 3316 case C(UR_GET_STATUS, UT_READ_DEVICE): 3317 len = 2; 3318 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3319 break; 3320 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3321 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3322 len = 2; 3323 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3324 break; 3325 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3326 if (value >= XHCI_MAX_DEVICES) { 3327 err = USB_ERR_IOERROR; 3328 goto done; 3329 } 3330 break; 3331 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3332 if (value != 0 && value != 1) { 3333 err = USB_ERR_IOERROR; 3334 goto done; 3335 } 3336 sc->sc_conf = value; 3337 break; 3338 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3339 break; 3340 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3341 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3342 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3343 err = USB_ERR_IOERROR; 3344 goto done; 3345 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3346 break; 3347 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3348 break; 3349 /* Hub requests */ 3350 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3351 break; 3352 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3353 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3354 3355 if ((index < 1) || 3356 (index > sc->sc_noport)) { 3357 err = USB_ERR_IOERROR; 3358 goto done; 3359 } 3360 port = XHCI_PORTSC(index); 3361 3362 v = XREAD4(sc, oper, port); 3363 i = XHCI_PS_PLS_GET(v); 3364 v &= ~XHCI_PS_CLEAR; 3365 3366 switch (value) { 3367 case UHF_C_BH_PORT_RESET: 3368 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3369 break; 3370 case UHF_C_PORT_CONFIG_ERROR: 3371 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3372 break; 3373 case UHF_C_PORT_SUSPEND: 3374 case UHF_C_PORT_LINK_STATE: 3375 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3376 break; 3377 case UHF_C_PORT_CONNECTION: 3378 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3379 break; 3380 case UHF_C_PORT_ENABLE: 3381 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3382 break; 3383 case UHF_C_PORT_OVER_CURRENT: 3384 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3385 break; 3386 case UHF_C_PORT_RESET: 3387 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3388 break; 3389 case UHF_PORT_ENABLE: 3390 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3391 break; 3392 case UHF_PORT_POWER: 3393 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3394 break; 3395 case UHF_PORT_INDICATOR: 3396 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3397 break; 3398 case UHF_PORT_SUSPEND: 3399 3400 /* U3 -> U15 */ 3401 if (i == 3) { 3402 XWRITE4(sc, oper, port, v | 3403 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3404 } 3405 3406 /* wait 20ms for resume sequence to complete */ 3407 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3408 3409 /* U0 */ 3410 XWRITE4(sc, oper, port, v | 3411 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3412 break; 3413 default: 3414 err = USB_ERR_IOERROR; 3415 goto done; 3416 } 3417 break; 3418 3419 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3420 if ((value & 0xff) != 0) { 3421 err = USB_ERR_IOERROR; 3422 goto done; 3423 } 3424 3425 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3426 3427 sc->sc_hub_desc.hubd = xhci_hubd; 3428 3429 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3430 3431 if (XHCI_HCS0_PPC(v)) 3432 i = UHD_PWR_INDIVIDUAL; 3433 else 3434 i = UHD_PWR_GANGED; 3435 3436 if (XHCI_HCS0_PIND(v)) 3437 i |= UHD_PORT_IND; 3438 3439 i |= UHD_OC_INDIVIDUAL; 3440 3441 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3442 3443 /* see XHCI section 5.4.9: */ 3444 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3445 3446 for (j = 1; j <= sc->sc_noport; j++) { 3447 3448 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3449 if (v & XHCI_PS_DR) { 3450 sc->sc_hub_desc.hubd. 3451 DeviceRemovable[j / 8] |= 1U << (j % 8); 3452 } 3453 } 3454 len = sc->sc_hub_desc.hubd.bLength; 3455 break; 3456 3457 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3458 len = 16; 3459 memset(sc->sc_hub_desc.temp, 0, 16); 3460 break; 3461 3462 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3463 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3464 3465 if ((index < 1) || 3466 (index > sc->sc_noport)) { 3467 err = USB_ERR_IOERROR; 3468 goto done; 3469 } 3470 3471 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3472 3473 DPRINTFN(9, "port status=0x%08x\n", v); 3474 3475 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3476 3477 switch (XHCI_PS_SPEED_GET(v)) { 3478 case 3: 3479 i |= UPS_HIGH_SPEED; 3480 break; 3481 case 2: 3482 i |= UPS_LOW_SPEED; 3483 break; 3484 case 1: 3485 /* FULL speed */ 3486 break; 3487 default: 3488 i |= UPS_OTHER_SPEED; 3489 break; 3490 } 3491 3492 if (v & XHCI_PS_CCS) 3493 i |= UPS_CURRENT_CONNECT_STATUS; 3494 if (v & XHCI_PS_PED) 3495 i |= UPS_PORT_ENABLED; 3496 if (v & XHCI_PS_OCA) 3497 i |= UPS_OVERCURRENT_INDICATOR; 3498 if (v & XHCI_PS_PR) 3499 i |= UPS_RESET; 3500 if (v & XHCI_PS_PP) { 3501 /* 3502 * The USB 3.0 RH is using the 3503 * USB 2.0's power bit 3504 */ 3505 i |= UPS_PORT_POWER; 3506 } 3507 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3508 3509 i = 0; 3510 if (v & XHCI_PS_CSC) 3511 i |= UPS_C_CONNECT_STATUS; 3512 if (v & XHCI_PS_PEC) 3513 i |= UPS_C_PORT_ENABLED; 3514 if (v & XHCI_PS_OCC) 3515 i |= UPS_C_OVERCURRENT_INDICATOR; 3516 if (v & XHCI_PS_WRC) 3517 i |= UPS_C_BH_PORT_RESET; 3518 if (v & XHCI_PS_PRC) 3519 i |= UPS_C_PORT_RESET; 3520 if (v & XHCI_PS_PLC) 3521 i |= UPS_C_PORT_LINK_STATE; 3522 if (v & XHCI_PS_CEC) 3523 i |= UPS_C_PORT_CONFIG_ERROR; 3524 3525 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3526 len = sizeof(sc->sc_hub_desc.ps); 3527 break; 3528 3529 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3530 err = USB_ERR_IOERROR; 3531 goto done; 3532 3533 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3534 break; 3535 3536 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3537 3538 i = index >> 8; 3539 index &= 0x00FF; 3540 3541 if ((index < 1) || 3542 (index > sc->sc_noport)) { 3543 err = USB_ERR_IOERROR; 3544 goto done; 3545 } 3546 3547 port = XHCI_PORTSC(index); 3548 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3549 3550 switch (value) { 3551 case UHF_PORT_U1_TIMEOUT: 3552 if (XHCI_PS_SPEED_GET(v) != 4) { 3553 err = USB_ERR_IOERROR; 3554 goto done; 3555 } 3556 port = XHCI_PORTPMSC(index); 3557 v = XREAD4(sc, oper, port); 3558 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3559 v |= XHCI_PM3_U1TO_SET(i); 3560 XWRITE4(sc, oper, port, v); 3561 break; 3562 case UHF_PORT_U2_TIMEOUT: 3563 if (XHCI_PS_SPEED_GET(v) != 4) { 3564 err = USB_ERR_IOERROR; 3565 goto done; 3566 } 3567 port = XHCI_PORTPMSC(index); 3568 v = XREAD4(sc, oper, port); 3569 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3570 v |= XHCI_PM3_U2TO_SET(i); 3571 XWRITE4(sc, oper, port, v); 3572 break; 3573 case UHF_BH_PORT_RESET: 3574 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3575 break; 3576 case UHF_PORT_LINK_STATE: 3577 XWRITE4(sc, oper, port, v | 3578 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3579 /* 4ms settle time */ 3580 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3581 break; 3582 case UHF_PORT_ENABLE: 3583 DPRINTFN(3, "set port enable %d\n", index); 3584 break; 3585 case UHF_PORT_SUSPEND: 3586 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3587 j = XHCI_PS_SPEED_GET(v); 3588 if ((j < 1) || (j > 3)) { 3589 /* non-supported speed */ 3590 err = USB_ERR_IOERROR; 3591 goto done; 3592 } 3593 XWRITE4(sc, oper, port, v | 3594 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3595 break; 3596 case UHF_PORT_RESET: 3597 DPRINTFN(6, "reset port %d\n", index); 3598 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3599 break; 3600 case UHF_PORT_POWER: 3601 DPRINTFN(3, "set port power %d\n", index); 3602 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3603 break; 3604 case UHF_PORT_TEST: 3605 DPRINTFN(3, "set port test %d\n", index); 3606 break; 3607 case UHF_PORT_INDICATOR: 3608 DPRINTFN(3, "set port indicator %d\n", index); 3609 3610 v &= ~XHCI_PS_PIC_SET(3); 3611 v |= XHCI_PS_PIC_SET(1); 3612 3613 XWRITE4(sc, oper, port, v); 3614 break; 3615 default: 3616 err = USB_ERR_IOERROR; 3617 goto done; 3618 } 3619 break; 3620 3621 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3622 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3623 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3624 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3625 break; 3626 default: 3627 err = USB_ERR_IOERROR; 3628 goto done; 3629 } 3630 done: 3631 *plength = len; 3632 *pptr = ptr; 3633 return (err); 3634 } 3635 3636 static void 3637 xhci_xfer_setup(struct usb_setup_params *parm) 3638 { 3639 struct usb_page_search page_info; 3640 struct usb_page_cache *pc; 3641 struct xhci_softc *sc; 3642 struct usb_xfer *xfer; 3643 void *last_obj; 3644 uint32_t ntd; 3645 uint32_t n; 3646 3647 sc = XHCI_BUS2SC(parm->udev->bus); 3648 xfer = parm->curr_xfer; 3649 3650 /* 3651 * The proof for the "ntd" formula is illustrated like this: 3652 * 3653 * +------------------------------------+ 3654 * | | 3655 * | |remainder -> | 3656 * | +-----+---+ | 3657 * | | xxx | x | frm 0 | 3658 * | +-----+---++ | 3659 * | | xxx | xx | frm 1 | 3660 * | +-----+----+ | 3661 * | ... | 3662 * +------------------------------------+ 3663 * 3664 * "xxx" means a completely full USB transfer descriptor 3665 * 3666 * "x" and "xx" means a short USB packet 3667 * 3668 * For the remainder of an USB transfer modulo 3669 * "max_data_length" we need two USB transfer descriptors. 3670 * One to transfer the remaining data and one to finalise with 3671 * a zero length packet in case the "force_short_xfer" flag is 3672 * set. We only need two USB transfer descriptors in the case 3673 * where the transfer length of the first one is a factor of 3674 * "max_frame_size". The rest of the needed USB transfer 3675 * descriptors is given by the buffer size divided by the 3676 * maximum data payload. 3677 */ 3678 parm->hc_max_packet_size = 0x400; 3679 parm->hc_max_packet_count = 16 * 3; 3680 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3681 3682 xfer->flags_int.bdma_enable = 1; 3683 3684 usbd_transfer_setup_sub(parm); 3685 3686 if (xfer->flags_int.isochronous_xfr) { 3687 ntd = ((1 * xfer->nframes) 3688 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3689 } else if (xfer->flags_int.control_xfr) { 3690 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3691 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3692 } else { 3693 ntd = ((2 * xfer->nframes) 3694 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3695 } 3696 3697 alloc_dma_set: 3698 3699 if (parm->err) 3700 return; 3701 3702 /* 3703 * Allocate queue heads and transfer descriptors 3704 */ 3705 last_obj = NULL; 3706 3707 if (usbd_transfer_setup_sub_malloc( 3708 parm, &pc, sizeof(struct xhci_td), 3709 XHCI_TD_ALIGN, ntd)) { 3710 parm->err = USB_ERR_NOMEM; 3711 return; 3712 } 3713 if (parm->buf) { 3714 for (n = 0; n != ntd; n++) { 3715 struct xhci_td *td; 3716 3717 usbd_get_page(pc + n, 0, &page_info); 3718 3719 td = page_info.buffer; 3720 3721 /* init TD */ 3722 td->td_self = page_info.physaddr; 3723 td->obj_next = last_obj; 3724 td->page_cache = pc + n; 3725 3726 last_obj = td; 3727 3728 usb_pc_cpu_flush(pc + n); 3729 } 3730 } 3731 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3732 3733 if (!xfer->flags_int.curr_dma_set) { 3734 xfer->flags_int.curr_dma_set = 1; 3735 goto alloc_dma_set; 3736 } 3737 } 3738 3739 static usb_error_t 3740 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3741 { 3742 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3743 struct usb_page_search buf_inp; 3744 struct usb_device *udev; 3745 struct xhci_endpoint_ext *pepext; 3746 struct usb_endpoint_descriptor *edesc; 3747 struct usb_page_cache *pcinp; 3748 usb_error_t err; 3749 usb_stream_t stream_id; 3750 uint8_t index; 3751 uint8_t epno; 3752 3753 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3754 xfer->endpoint->edesc); 3755 3756 udev = xfer->xroot->udev; 3757 index = udev->controller_slot_id; 3758 3759 pcinp = &sc->sc_hw.devs[index].input_pc; 3760 3761 usbd_get_page(pcinp, 0, &buf_inp); 3762 3763 edesc = xfer->endpoint->edesc; 3764 3765 epno = edesc->bEndpointAddress; 3766 stream_id = xfer->stream_id; 3767 3768 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3769 epno |= UE_DIR_IN; 3770 3771 epno = XHCI_EPNO2EPID(epno); 3772 3773 if (epno == 0) 3774 return (USB_ERR_NO_PIPE); /* invalid */ 3775 3776 XHCI_CMD_LOCK(sc); 3777 3778 /* configure endpoint */ 3779 3780 err = xhci_configure_endpoint_by_xfer(xfer); 3781 3782 if (err != 0) { 3783 XHCI_CMD_UNLOCK(sc); 3784 return (err); 3785 } 3786 3787 /* 3788 * Get the endpoint into the stopped state according to the 3789 * endpoint context state diagram in the XHCI specification: 3790 */ 3791 3792 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3793 3794 if (err != 0) 3795 DPRINTF("Could not stop endpoint %u\n", epno); 3796 3797 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3798 3799 if (err != 0) 3800 DPRINTF("Could not reset endpoint %u\n", epno); 3801 3802 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3803 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3804 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3805 stream_id, epno, index); 3806 3807 if (err != 0) 3808 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3809 3810 /* 3811 * Get the endpoint into the running state according to the 3812 * endpoint context state diagram in the XHCI specification: 3813 */ 3814 3815 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3816 3817 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3818 3819 if (err != 0) 3820 DPRINTF("Could not configure endpoint %u\n", epno); 3821 3822 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3823 3824 if (err != 0) 3825 DPRINTF("Could not configure endpoint %u\n", epno); 3826 3827 XHCI_CMD_UNLOCK(sc); 3828 3829 return (0); 3830 } 3831 3832 static void 3833 xhci_xfer_unsetup(struct usb_xfer *xfer) 3834 { 3835 return; 3836 } 3837 3838 static void 3839 xhci_start_dma_delay(struct usb_xfer *xfer) 3840 { 3841 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3842 3843 /* put transfer on interrupt queue (again) */ 3844 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3845 3846 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3847 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3848 } 3849 3850 static void 3851 xhci_configure_msg(struct usb_proc_msg *pm) 3852 { 3853 struct xhci_softc *sc; 3854 struct xhci_endpoint_ext *pepext; 3855 struct usb_xfer *xfer; 3856 3857 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3858 3859 restart: 3860 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3861 3862 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3863 xfer->endpoint->edesc); 3864 3865 if ((pepext->trb_halted != 0) || 3866 (pepext->trb_running == 0)) { 3867 3868 uint16_t i; 3869 3870 /* clear halted and running */ 3871 pepext->trb_halted = 0; 3872 pepext->trb_running = 0; 3873 3874 /* nuke remaining buffered transfers */ 3875 3876 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3877 XHCI_MAX_STREAMS); i++) { 3878 /* 3879 * NOTE: We need to use the timeout 3880 * error code here else existing 3881 * isochronous clients can get 3882 * confused: 3883 */ 3884 if (pepext->xfer[i] != NULL) { 3885 xhci_device_done(pepext->xfer[i], 3886 USB_ERR_TIMEOUT); 3887 } 3888 } 3889 3890 /* 3891 * NOTE: The USB transfer cannot vanish in 3892 * this state! 3893 */ 3894 3895 USB_BUS_UNLOCK(&sc->sc_bus); 3896 3897 xhci_configure_reset_endpoint(xfer); 3898 3899 USB_BUS_LOCK(&sc->sc_bus); 3900 3901 /* check if halted is still cleared */ 3902 if (pepext->trb_halted == 0) { 3903 pepext->trb_running = 1; 3904 memset(pepext->trb_index, 0, 3905 sizeof(pepext->trb_index)); 3906 } 3907 goto restart; 3908 } 3909 3910 if (xfer->flags_int.did_dma_delay) { 3911 3912 /* remove transfer from interrupt queue (again) */ 3913 usbd_transfer_dequeue(xfer); 3914 3915 /* we are finally done */ 3916 usb_dma_delay_done_cb(xfer); 3917 3918 /* queue changed - restart */ 3919 goto restart; 3920 } 3921 } 3922 3923 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3924 3925 /* try to insert xfer on HW queue */ 3926 xhci_transfer_insert(xfer); 3927 3928 /* try to multi buffer */ 3929 xhci_device_generic_multi_enter(xfer->endpoint, 3930 xfer->stream_id, NULL); 3931 } 3932 } 3933 3934 static void 3935 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3936 struct usb_endpoint *ep) 3937 { 3938 struct xhci_endpoint_ext *pepext; 3939 3940 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3941 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3942 3943 if (udev->parent_hub == NULL) { 3944 /* root HUB has special endpoint handling */ 3945 return; 3946 } 3947 3948 ep->methods = &xhci_device_generic_methods; 3949 3950 pepext = xhci_get_endpoint_ext(udev, edesc); 3951 3952 USB_BUS_LOCK(udev->bus); 3953 pepext->trb_halted = 1; 3954 pepext->trb_running = 0; 3955 USB_BUS_UNLOCK(udev->bus); 3956 } 3957 3958 static void 3959 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3960 { 3961 3962 } 3963 3964 static void 3965 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3966 { 3967 struct xhci_endpoint_ext *pepext; 3968 3969 DPRINTF("\n"); 3970 3971 if (udev->flags.usb_mode != USB_MODE_HOST) { 3972 /* not supported */ 3973 return; 3974 } 3975 if (udev->parent_hub == NULL) { 3976 /* root HUB has special endpoint handling */ 3977 return; 3978 } 3979 3980 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3981 3982 USB_BUS_LOCK(udev->bus); 3983 pepext->trb_halted = 1; 3984 pepext->trb_running = 0; 3985 USB_BUS_UNLOCK(udev->bus); 3986 } 3987 3988 static usb_error_t 3989 xhci_device_init(struct usb_device *udev) 3990 { 3991 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3992 usb_error_t err; 3993 uint8_t temp; 3994 3995 /* no init for root HUB */ 3996 if (udev->parent_hub == NULL) 3997 return (0); 3998 3999 XHCI_CMD_LOCK(sc); 4000 4001 /* set invalid default */ 4002 4003 udev->controller_slot_id = sc->sc_noslot + 1; 4004 4005 /* try to get a new slot ID from the XHCI */ 4006 4007 err = xhci_cmd_enable_slot(sc, &temp); 4008 4009 if (err) { 4010 XHCI_CMD_UNLOCK(sc); 4011 return (err); 4012 } 4013 4014 if (temp > sc->sc_noslot) { 4015 XHCI_CMD_UNLOCK(sc); 4016 return (USB_ERR_BAD_ADDRESS); 4017 } 4018 4019 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4020 DPRINTF("slot %u already allocated.\n", temp); 4021 XHCI_CMD_UNLOCK(sc); 4022 return (USB_ERR_BAD_ADDRESS); 4023 } 4024 4025 /* store slot ID for later reference */ 4026 4027 udev->controller_slot_id = temp; 4028 4029 /* reset data structure */ 4030 4031 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4032 4033 /* set mark slot allocated */ 4034 4035 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4036 4037 err = xhci_alloc_device_ext(udev); 4038 4039 XHCI_CMD_UNLOCK(sc); 4040 4041 /* get device into default state */ 4042 4043 if (err == 0) 4044 err = xhci_set_address(udev, NULL, 0); 4045 4046 return (err); 4047 } 4048 4049 static void 4050 xhci_device_uninit(struct usb_device *udev) 4051 { 4052 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4053 uint8_t index; 4054 4055 /* no init for root HUB */ 4056 if (udev->parent_hub == NULL) 4057 return; 4058 4059 XHCI_CMD_LOCK(sc); 4060 4061 index = udev->controller_slot_id; 4062 4063 if (index <= sc->sc_noslot) { 4064 xhci_cmd_disable_slot(sc, index); 4065 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4066 4067 /* free device extension */ 4068 xhci_free_device_ext(udev); 4069 } 4070 4071 XHCI_CMD_UNLOCK(sc); 4072 } 4073 4074 static void 4075 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4076 { 4077 /* 4078 * Wait until the hardware has finished any possible use of 4079 * the transfer descriptor(s) 4080 */ 4081 *pus = 2048; /* microseconds */ 4082 } 4083 4084 static void 4085 xhci_device_resume(struct usb_device *udev) 4086 { 4087 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4088 uint8_t index; 4089 uint8_t n; 4090 uint8_t p; 4091 4092 DPRINTF("\n"); 4093 4094 /* check for root HUB */ 4095 if (udev->parent_hub == NULL) 4096 return; 4097 4098 index = udev->controller_slot_id; 4099 4100 XHCI_CMD_LOCK(sc); 4101 4102 /* blindly resume all endpoints */ 4103 4104 USB_BUS_LOCK(udev->bus); 4105 4106 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4107 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4108 XWRITE4(sc, door, XHCI_DOORBELL(index), 4109 n | XHCI_DB_SID_SET(p)); 4110 } 4111 } 4112 4113 USB_BUS_UNLOCK(udev->bus); 4114 4115 XHCI_CMD_UNLOCK(sc); 4116 } 4117 4118 static void 4119 xhci_device_suspend(struct usb_device *udev) 4120 { 4121 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4122 uint8_t index; 4123 uint8_t n; 4124 usb_error_t err; 4125 4126 DPRINTF("\n"); 4127 4128 /* check for root HUB */ 4129 if (udev->parent_hub == NULL) 4130 return; 4131 4132 index = udev->controller_slot_id; 4133 4134 XHCI_CMD_LOCK(sc); 4135 4136 /* blindly suspend all endpoints */ 4137 4138 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4139 err = xhci_cmd_stop_ep(sc, 1, n, index); 4140 if (err != 0) { 4141 DPRINTF("Failed to suspend endpoint " 4142 "%u on slot %u (ignored).\n", n, index); 4143 } 4144 } 4145 4146 XHCI_CMD_UNLOCK(sc); 4147 } 4148 4149 static void 4150 xhci_set_hw_power(struct usb_bus *bus) 4151 { 4152 DPRINTF("\n"); 4153 } 4154 4155 static void 4156 xhci_device_state_change(struct usb_device *udev) 4157 { 4158 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4159 struct usb_page_search buf_inp; 4160 usb_error_t err; 4161 uint8_t index; 4162 4163 /* check for root HUB */ 4164 if (udev->parent_hub == NULL) 4165 return; 4166 4167 index = udev->controller_slot_id; 4168 4169 DPRINTF("\n"); 4170 4171 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4172 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4173 &sc->sc_hw.devs[index].tt); 4174 if (err != 0) 4175 sc->sc_hw.devs[index].nports = 0; 4176 } 4177 4178 XHCI_CMD_LOCK(sc); 4179 4180 switch (usb_get_device_state(udev)) { 4181 case USB_STATE_POWERED: 4182 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4183 break; 4184 4185 /* set default state */ 4186 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4187 4188 /* reset number of contexts */ 4189 sc->sc_hw.devs[index].context_num = 0; 4190 4191 err = xhci_cmd_reset_dev(sc, index); 4192 4193 if (err != 0) { 4194 DPRINTF("Device reset failed " 4195 "for slot %u.\n", index); 4196 } 4197 break; 4198 4199 case USB_STATE_ADDRESSED: 4200 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4201 break; 4202 4203 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4204 4205 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4206 4207 if (err) { 4208 DPRINTF("Failed to deconfigure " 4209 "slot %u.\n", index); 4210 } 4211 break; 4212 4213 case USB_STATE_CONFIGURED: 4214 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4215 break; 4216 4217 /* set configured state */ 4218 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4219 4220 /* reset number of contexts */ 4221 sc->sc_hw.devs[index].context_num = 0; 4222 4223 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4224 4225 xhci_configure_mask(udev, 3, 0); 4226 4227 err = xhci_configure_device(udev); 4228 if (err != 0) { 4229 DPRINTF("Could not configure device " 4230 "at slot %u.\n", index); 4231 } 4232 4233 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4234 if (err != 0) { 4235 DPRINTF("Could not evaluate device " 4236 "context at slot %u.\n", index); 4237 } 4238 break; 4239 4240 default: 4241 break; 4242 } 4243 XHCI_CMD_UNLOCK(sc); 4244 } 4245 4246 static usb_error_t 4247 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4248 uint8_t ep_mode) 4249 { 4250 switch (ep_mode) { 4251 case USB_EP_MODE_DEFAULT: 4252 return (0); 4253 case USB_EP_MODE_STREAMS: 4254 if (xhcistreams == 0 || 4255 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4256 udev->speed != USB_SPEED_SUPER) 4257 return (USB_ERR_INVAL); 4258 return (0); 4259 default: 4260 return (USB_ERR_INVAL); 4261 } 4262 } 4263 4264 static const struct usb_bus_methods xhci_bus_methods = { 4265 .endpoint_init = xhci_ep_init, 4266 .endpoint_uninit = xhci_ep_uninit, 4267 .xfer_setup = xhci_xfer_setup, 4268 .xfer_unsetup = xhci_xfer_unsetup, 4269 .get_dma_delay = xhci_get_dma_delay, 4270 .device_init = xhci_device_init, 4271 .device_uninit = xhci_device_uninit, 4272 .device_resume = xhci_device_resume, 4273 .device_suspend = xhci_device_suspend, 4274 .set_hw_power = xhci_set_hw_power, 4275 .roothub_exec = xhci_roothub_exec, 4276 .xfer_poll = xhci_do_poll, 4277 .start_dma_delay = xhci_start_dma_delay, 4278 .set_address = xhci_set_address, 4279 .clear_stall = xhci_ep_clear_stall, 4280 .device_state_change = xhci_device_state_change, 4281 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4282 .set_endpoint_mode = xhci_set_endpoint_mode, 4283 }; 4284