1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 28 * 29 * The XHCI 1.0 spec can be found at 30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 31 * and the USB 3.0 spec at 32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 33 */ 34 35 /* 36 * A few words about the design implementation: This driver emulates 37 * the concept about TDs which is found in EHCI specification. This 38 * way we avoid too much diveration among USB drivers. 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/stdint.h> 45 #include <sys/stddef.h> 46 #include <sys/param.h> 47 #include <sys/queue.h> 48 #include <sys/types.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/bus.h> 52 #include <sys/module.h> 53 #include <sys/lock.h> 54 #include <sys/mutex.h> 55 #include <sys/condvar.h> 56 #include <sys/sysctl.h> 57 #include <sys/sx.h> 58 #include <sys/unistd.h> 59 #include <sys/callout.h> 60 #include <sys/malloc.h> 61 #include <sys/priv.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 66 #define USB_DEBUG_VAR xhcidebug 67 68 #include <dev/usb/usb_core.h> 69 #include <dev/usb/usb_debug.h> 70 #include <dev/usb/usb_busdma.h> 71 #include <dev/usb/usb_process.h> 72 #include <dev/usb/usb_transfer.h> 73 #include <dev/usb/usb_device.h> 74 #include <dev/usb/usb_hub.h> 75 #include <dev/usb/usb_util.h> 76 77 #include <dev/usb/usb_controller.h> 78 #include <dev/usb/usb_bus.h> 79 #include <dev/usb/controller/xhci.h> 80 #include <dev/usb/controller/xhcireg.h> 81 82 #define XHCI_BUS2SC(bus) \ 83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 85 86 #ifdef USB_DEBUG 87 static int xhcidebug; 88 static int xhciroute; 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 92 &xhcidebug, 0, "Debug level"); 93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN, 95 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 97 #endif 98 99 #define XHCI_INTR_ENDPT 1 100 101 struct xhci_std_temp { 102 struct xhci_softc *sc; 103 struct usb_page_cache *pc; 104 struct xhci_td *td; 105 struct xhci_td *td_next; 106 uint32_t len; 107 uint32_t offset; 108 uint32_t max_packet_size; 109 uint32_t average; 110 uint16_t isoc_delta; 111 uint16_t isoc_frame; 112 uint8_t shortpkt; 113 uint8_t multishort; 114 uint8_t last_frame; 115 uint8_t trb_type; 116 uint8_t direction; 117 uint8_t tbc; 118 uint8_t tlbpc; 119 uint8_t step_td; 120 uint8_t do_isoc_sync; 121 }; 122 123 static void xhci_do_poll(struct usb_bus *); 124 static void xhci_device_done(struct usb_xfer *, usb_error_t); 125 static void xhci_root_intr(struct xhci_softc *); 126 static void xhci_free_device_ext(struct usb_device *); 127 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 128 struct usb_endpoint_descriptor *); 129 static usb_proc_callback_t xhci_configure_msg; 130 static usb_error_t xhci_configure_device(struct usb_device *); 131 static usb_error_t xhci_configure_endpoint(struct usb_device *, 132 struct usb_endpoint_descriptor *, uint64_t, uint16_t, 133 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, uint8_t); 134 static usb_error_t xhci_configure_mask(struct usb_device *, 135 uint32_t, uint8_t); 136 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 137 uint64_t, uint8_t); 138 static void xhci_endpoint_doorbell(struct usb_xfer *); 139 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 140 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 141 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 142 #ifdef USB_DEBUG 143 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 144 #endif 145 146 extern struct usb_bus_methods xhci_bus_methods; 147 148 #ifdef USB_DEBUG 149 static void 150 xhci_dump_trb(struct xhci_trb *trb) 151 { 152 DPRINTFN(5, "trb = %p\n", trb); 153 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 154 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 155 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 156 } 157 158 static void 159 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 160 { 161 DPRINTFN(5, "pep = %p\n", pep); 162 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 163 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 164 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 165 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 166 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 167 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 168 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 169 } 170 171 static void 172 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 173 { 174 DPRINTFN(5, "psl = %p\n", psl); 175 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 176 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 177 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 178 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 179 } 180 #endif 181 182 uint32_t 183 xhci_get_port_route(void) 184 { 185 #ifdef USB_DEBUG 186 return (0xFFFFFFFFU ^ ((uint32_t)xhciroute)); 187 #else 188 return (0xFFFFFFFFU); 189 #endif 190 } 191 192 static void 193 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 194 { 195 struct xhci_softc *sc = XHCI_BUS2SC(bus); 196 uint8_t i; 197 198 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 199 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 200 201 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 202 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 203 204 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 205 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 206 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 207 } 208 } 209 210 static void 211 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 212 { 213 if (sc->sc_ctx_is_64_byte) { 214 uint32_t offset; 215 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 216 /* all contexts are initially 32-bytes */ 217 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 218 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 219 } 220 *ptr = htole32(val); 221 } 222 223 static uint32_t 224 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 225 { 226 if (sc->sc_ctx_is_64_byte) { 227 uint32_t offset; 228 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 229 /* all contexts are initially 32-bytes */ 230 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 231 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 232 } 233 return (le32toh(*ptr)); 234 } 235 236 static void 237 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 238 { 239 if (sc->sc_ctx_is_64_byte) { 240 uint32_t offset; 241 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 242 /* all contexts are initially 32-bytes */ 243 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 244 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 245 } 246 *ptr = htole64(val); 247 } 248 249 #ifdef USB_DEBUG 250 static uint64_t 251 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 252 { 253 if (sc->sc_ctx_is_64_byte) { 254 uint32_t offset; 255 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 256 /* all contexts are initially 32-bytes */ 257 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 258 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 259 } 260 return (le64toh(*ptr)); 261 } 262 #endif 263 264 usb_error_t 265 xhci_start_controller(struct xhci_softc *sc) 266 { 267 struct usb_page_search buf_res; 268 struct xhci_hw_root *phwr; 269 struct xhci_dev_ctx_addr *pdctxa; 270 uint64_t addr; 271 uint32_t temp; 272 uint16_t i; 273 274 DPRINTF("\n"); 275 276 sc->sc_capa_off = 0; 277 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 278 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 279 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 280 281 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 282 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 283 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 284 285 sc->sc_event_ccs = 1; 286 sc->sc_event_idx = 0; 287 sc->sc_command_ccs = 1; 288 sc->sc_command_idx = 0; 289 290 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 291 292 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 293 294 DPRINTF("HCS0 = 0x%08x\n", temp); 295 296 if (XHCI_HCS0_CSZ(temp)) { 297 sc->sc_ctx_is_64_byte = 1; 298 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 299 } else { 300 sc->sc_ctx_is_64_byte = 0; 301 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 302 } 303 304 /* Reset controller */ 305 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 306 307 for (i = 0; i != 100; i++) { 308 usb_pause_mtx(NULL, hz / 100); 309 temp = XREAD4(sc, oper, XHCI_USBCMD) & 310 (XHCI_CMD_HCRST | XHCI_STS_CNR); 311 if (!temp) 312 break; 313 } 314 315 if (temp) { 316 device_printf(sc->sc_bus.parent, "Controller " 317 "reset timeout.\n"); 318 return (USB_ERR_IOERROR); 319 } 320 321 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 322 device_printf(sc->sc_bus.parent, "Controller does " 323 "not support 4K page size.\n"); 324 return (USB_ERR_IOERROR); 325 } 326 327 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 328 329 i = XHCI_HCS1_N_PORTS(temp); 330 331 if (i == 0) { 332 device_printf(sc->sc_bus.parent, "Invalid number " 333 "of ports: %u\n", i); 334 return (USB_ERR_IOERROR); 335 } 336 337 sc->sc_noport = i; 338 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 339 340 if (sc->sc_noslot > XHCI_MAX_DEVICES) 341 sc->sc_noslot = XHCI_MAX_DEVICES; 342 343 /* setup number of device slots */ 344 345 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 346 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 347 348 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 349 350 DPRINTF("Max slots: %u\n", sc->sc_noslot); 351 352 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 353 354 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 355 356 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 357 device_printf(sc->sc_bus.parent, "XHCI request " 358 "too many scratchpads\n"); 359 return (USB_ERR_NOMEM); 360 } 361 362 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 363 364 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 365 366 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 367 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 368 369 temp = XREAD4(sc, oper, XHCI_USBSTS); 370 371 /* clear interrupts */ 372 XWRITE4(sc, oper, XHCI_USBSTS, temp); 373 /* disable all device notifications */ 374 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 375 376 /* setup device context base address */ 377 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 378 pdctxa = buf_res.buffer; 379 memset(pdctxa, 0, sizeof(*pdctxa)); 380 381 addr = buf_res.physaddr; 382 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 383 384 /* slot 0 points to the table of scratchpad pointers */ 385 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 386 387 for (i = 0; i != sc->sc_noscratch; i++) { 388 struct usb_page_search buf_scp; 389 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 390 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 391 } 392 393 addr = buf_res.physaddr; 394 395 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 396 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 397 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 398 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 399 400 /* Setup event table size */ 401 402 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 403 404 DPRINTF("HCS2=0x%08x\n", temp); 405 406 temp = XHCI_HCS2_ERST_MAX(temp); 407 temp = 1U << temp; 408 if (temp > XHCI_MAX_RSEG) 409 temp = XHCI_MAX_RSEG; 410 411 sc->sc_erst_max = temp; 412 413 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 414 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 415 416 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 417 418 /* Setup interrupt rate */ 419 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 420 421 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 422 423 phwr = buf_res.buffer; 424 addr = buf_res.physaddr; 425 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 426 427 /* reset hardware root structure */ 428 memset(phwr, 0, sizeof(*phwr)); 429 430 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 431 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 432 433 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 434 435 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 436 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 437 438 addr = (uint64_t)buf_res.physaddr; 439 440 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 441 442 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 443 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 444 445 /* Setup interrupter registers */ 446 447 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 448 temp |= XHCI_IMAN_INTR_ENA; 449 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 450 451 /* setup command ring control base address */ 452 addr = buf_res.physaddr; 453 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 454 455 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 456 457 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 458 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 459 460 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 461 462 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 463 464 /* Go! */ 465 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 466 XHCI_CMD_INTE | XHCI_CMD_HSEE); 467 468 for (i = 0; i != 100; i++) { 469 usb_pause_mtx(NULL, hz / 100); 470 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 471 if (!temp) 472 break; 473 } 474 if (temp) { 475 XWRITE4(sc, oper, XHCI_USBCMD, 0); 476 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 477 return (USB_ERR_IOERROR); 478 } 479 480 /* catch any lost interrupts */ 481 xhci_do_poll(&sc->sc_bus); 482 483 return (0); 484 } 485 486 usb_error_t 487 xhci_halt_controller(struct xhci_softc *sc) 488 { 489 uint32_t temp; 490 uint16_t i; 491 492 DPRINTF("\n"); 493 494 sc->sc_capa_off = 0; 495 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 496 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 497 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 498 499 /* Halt controller */ 500 XWRITE4(sc, oper, XHCI_USBCMD, 0); 501 502 for (i = 0; i != 100; i++) { 503 usb_pause_mtx(NULL, hz / 100); 504 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 505 if (temp) 506 break; 507 } 508 509 if (!temp) { 510 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 511 return (USB_ERR_IOERROR); 512 } 513 return (0); 514 } 515 516 usb_error_t 517 xhci_init(struct xhci_softc *sc, device_t self) 518 { 519 /* initialise some bus fields */ 520 sc->sc_bus.parent = self; 521 522 /* set the bus revision */ 523 sc->sc_bus.usbrev = USB_REV_3_0; 524 525 /* set up the bus struct */ 526 sc->sc_bus.methods = &xhci_bus_methods; 527 528 /* setup devices array */ 529 sc->sc_bus.devices = sc->sc_devices; 530 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 531 532 /* setup command queue mutex and condition varible */ 533 cv_init(&sc->sc_cmd_cv, "CMDQ"); 534 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 535 536 /* get all DMA memory */ 537 if (usb_bus_mem_alloc_all(&sc->sc_bus, 538 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 539 return (ENOMEM); 540 } 541 542 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 543 sc->sc_config_msg[0].bus = &sc->sc_bus; 544 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 545 sc->sc_config_msg[1].bus = &sc->sc_bus; 546 547 if (usb_proc_create(&sc->sc_config_proc, 548 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) { 549 printf("WARNING: Creation of XHCI configure " 550 "callback process failed.\n"); 551 } 552 return (0); 553 } 554 555 void 556 xhci_uninit(struct xhci_softc *sc) 557 { 558 usb_proc_free(&sc->sc_config_proc); 559 560 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 561 562 cv_destroy(&sc->sc_cmd_cv); 563 sx_destroy(&sc->sc_cmd_sx); 564 } 565 566 static void 567 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 568 { 569 struct xhci_softc *sc = XHCI_BUS2SC(bus); 570 571 switch (state) { 572 case USB_HW_POWER_SUSPEND: 573 DPRINTF("Stopping the XHCI\n"); 574 xhci_halt_controller(sc); 575 break; 576 case USB_HW_POWER_SHUTDOWN: 577 DPRINTF("Stopping the XHCI\n"); 578 xhci_halt_controller(sc); 579 break; 580 case USB_HW_POWER_RESUME: 581 DPRINTF("Starting the XHCI\n"); 582 xhci_start_controller(sc); 583 break; 584 default: 585 break; 586 } 587 } 588 589 static usb_error_t 590 xhci_generic_done_sub(struct usb_xfer *xfer) 591 { 592 struct xhci_td *td; 593 struct xhci_td *td_alt_next; 594 uint32_t len; 595 uint8_t status; 596 597 td = xfer->td_transfer_cache; 598 td_alt_next = td->alt_next; 599 600 if (xfer->aframes != xfer->nframes) 601 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 602 603 while (1) { 604 605 usb_pc_cpu_invalidate(td->page_cache); 606 607 status = td->status; 608 len = td->remainder; 609 610 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 611 xfer, (unsigned int)xfer->aframes, 612 (unsigned int)xfer->nframes, 613 (unsigned int)len, (unsigned int)td->len, 614 (unsigned int)status); 615 616 /* 617 * Verify the status length and 618 * add the length to "frlengths[]": 619 */ 620 if (len > td->len) { 621 /* should not happen */ 622 DPRINTF("Invalid status length, " 623 "0x%04x/0x%04x bytes\n", len, td->len); 624 status = XHCI_TRB_ERROR_LENGTH; 625 } else if (xfer->aframes != xfer->nframes) { 626 xfer->frlengths[xfer->aframes] += td->len - len; 627 } 628 /* Check for last transfer */ 629 if (((void *)td) == xfer->td_transfer_last) { 630 td = NULL; 631 break; 632 } 633 /* Check for transfer error */ 634 if (status != XHCI_TRB_ERROR_SHORT_PKT && 635 status != XHCI_TRB_ERROR_SUCCESS) { 636 /* the transfer is finished */ 637 td = NULL; 638 break; 639 } 640 /* Check for short transfer */ 641 if (len > 0) { 642 if (xfer->flags_int.short_frames_ok || 643 xfer->flags_int.isochronous_xfr || 644 xfer->flags_int.control_xfr) { 645 /* follow alt next */ 646 td = td->alt_next; 647 } else { 648 /* the transfer is finished */ 649 td = NULL; 650 } 651 break; 652 } 653 td = td->obj_next; 654 655 if (td->alt_next != td_alt_next) { 656 /* this USB frame is complete */ 657 break; 658 } 659 } 660 661 /* update transfer cache */ 662 663 xfer->td_transfer_cache = td; 664 665 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 666 (status != XHCI_TRB_ERROR_SHORT_PKT && 667 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 668 USB_ERR_NORMAL_COMPLETION); 669 } 670 671 static void 672 xhci_generic_done(struct usb_xfer *xfer) 673 { 674 usb_error_t err = 0; 675 676 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 677 xfer, xfer->endpoint); 678 679 /* reset scanner */ 680 681 xfer->td_transfer_cache = xfer->td_transfer_first; 682 683 if (xfer->flags_int.control_xfr) { 684 685 if (xfer->flags_int.control_hdr) 686 err = xhci_generic_done_sub(xfer); 687 688 xfer->aframes = 1; 689 690 if (xfer->td_transfer_cache == NULL) 691 goto done; 692 } 693 694 while (xfer->aframes != xfer->nframes) { 695 696 err = xhci_generic_done_sub(xfer); 697 xfer->aframes++; 698 699 if (xfer->td_transfer_cache == NULL) 700 goto done; 701 } 702 703 if (xfer->flags_int.control_xfr && 704 !xfer->flags_int.control_act) 705 err = xhci_generic_done_sub(xfer); 706 done: 707 /* transfer is complete */ 708 xhci_device_done(xfer, err); 709 } 710 711 static void 712 xhci_activate_transfer(struct usb_xfer *xfer) 713 { 714 struct xhci_td *td; 715 716 td = xfer->td_transfer_cache; 717 718 usb_pc_cpu_invalidate(td->page_cache); 719 720 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 721 722 /* activate the transfer */ 723 724 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 725 usb_pc_cpu_flush(td->page_cache); 726 727 xhci_endpoint_doorbell(xfer); 728 } 729 } 730 731 static void 732 xhci_skip_transfer(struct usb_xfer *xfer) 733 { 734 struct xhci_td *td; 735 struct xhci_td *td_last; 736 737 td = xfer->td_transfer_cache; 738 td_last = xfer->td_transfer_last; 739 740 td = td->alt_next; 741 742 usb_pc_cpu_invalidate(td->page_cache); 743 744 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 745 746 usb_pc_cpu_invalidate(td_last->page_cache); 747 748 /* copy LINK TRB to current waiting location */ 749 750 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 751 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 752 usb_pc_cpu_flush(td->page_cache); 753 754 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 755 usb_pc_cpu_flush(td->page_cache); 756 757 xhci_endpoint_doorbell(xfer); 758 } 759 } 760 761 /*------------------------------------------------------------------------* 762 * xhci_check_transfer 763 *------------------------------------------------------------------------*/ 764 static void 765 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 766 { 767 int64_t offset; 768 uint64_t td_event; 769 uint32_t temp; 770 uint32_t remainder; 771 uint8_t status; 772 uint8_t halted; 773 uint8_t epno; 774 uint8_t index; 775 uint8_t i; 776 777 /* decode TRB */ 778 td_event = le64toh(trb->qwTrb0); 779 temp = le32toh(trb->dwTrb2); 780 781 remainder = XHCI_TRB_2_REM_GET(temp); 782 status = XHCI_TRB_2_ERROR_GET(temp); 783 784 temp = le32toh(trb->dwTrb3); 785 epno = XHCI_TRB_3_EP_GET(temp); 786 index = XHCI_TRB_3_SLOT_GET(temp); 787 788 /* check if error means halted */ 789 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 790 status != XHCI_TRB_ERROR_SUCCESS); 791 792 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 793 index, epno, remainder, status); 794 795 if (index > sc->sc_noslot) { 796 DPRINTF("Invalid slot.\n"); 797 return; 798 } 799 800 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 801 DPRINTF("Invalid endpoint.\n"); 802 return; 803 } 804 805 /* try to find the USB transfer that generated the event */ 806 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 807 struct usb_xfer *xfer; 808 struct xhci_td *td; 809 struct xhci_endpoint_ext *pepext; 810 811 pepext = &sc->sc_hw.devs[index].endp[epno]; 812 813 xfer = pepext->xfer[i]; 814 if (xfer == NULL) 815 continue; 816 817 td = xfer->td_transfer_cache; 818 819 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 820 (long long)td_event, 821 (long long)td->td_self, 822 (long long)td->td_self + sizeof(td->td_trb)); 823 824 /* 825 * NOTE: Some XHCI implementations might not trigger 826 * an event on the last LINK TRB so we need to 827 * consider both the last and second last event 828 * address as conditions for a successful transfer. 829 * 830 * NOTE: We assume that the XHCI will only trigger one 831 * event per chain of TRBs. 832 */ 833 834 offset = td_event - td->td_self; 835 836 if (offset >= 0 && 837 offset < (int64_t)sizeof(td->td_trb)) { 838 839 usb_pc_cpu_invalidate(td->page_cache); 840 841 /* compute rest of remainder, if any */ 842 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 843 temp = le32toh(td->td_trb[i].dwTrb2); 844 remainder += XHCI_TRB_2_BYTES_GET(temp); 845 } 846 847 DPRINTFN(5, "New remainder: %u\n", remainder); 848 849 /* clear isochronous transfer errors */ 850 if (xfer->flags_int.isochronous_xfr) { 851 if (halted) { 852 halted = 0; 853 status = XHCI_TRB_ERROR_SUCCESS; 854 remainder = td->len; 855 } 856 } 857 858 /* "td->remainder" is verified later */ 859 td->remainder = remainder; 860 td->status = status; 861 862 usb_pc_cpu_flush(td->page_cache); 863 864 /* 865 * 1) Last transfer descriptor makes the 866 * transfer done 867 */ 868 if (((void *)td) == xfer->td_transfer_last) { 869 DPRINTF("TD is last\n"); 870 xhci_generic_done(xfer); 871 break; 872 } 873 874 /* 875 * 2) Any kind of error makes the transfer 876 * done 877 */ 878 if (halted) { 879 DPRINTF("TD has I/O error\n"); 880 xhci_generic_done(xfer); 881 break; 882 } 883 884 /* 885 * 3) If there is no alternate next transfer, 886 * a short packet also makes the transfer done 887 */ 888 if (td->remainder > 0) { 889 DPRINTF("TD has short pkt\n"); 890 if (xfer->flags_int.short_frames_ok || 891 xfer->flags_int.isochronous_xfr || 892 xfer->flags_int.control_xfr) { 893 /* follow the alt next */ 894 xfer->td_transfer_cache = td->alt_next; 895 xhci_activate_transfer(xfer); 896 break; 897 } 898 xhci_skip_transfer(xfer); 899 xhci_generic_done(xfer); 900 break; 901 } 902 903 /* 904 * 4) Transfer complete - go to next TD 905 */ 906 DPRINTF("Following next TD\n"); 907 xfer->td_transfer_cache = td->obj_next; 908 xhci_activate_transfer(xfer); 909 break; /* there should only be one match */ 910 } 911 } 912 } 913 914 static void 915 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 916 { 917 if (sc->sc_cmd_addr == trb->qwTrb0) { 918 DPRINTF("Received command event\n"); 919 sc->sc_cmd_result[0] = trb->dwTrb2; 920 sc->sc_cmd_result[1] = trb->dwTrb3; 921 cv_signal(&sc->sc_cmd_cv); 922 } 923 } 924 925 static void 926 xhci_interrupt_poll(struct xhci_softc *sc) 927 { 928 struct usb_page_search buf_res; 929 struct xhci_hw_root *phwr; 930 uint64_t addr; 931 uint32_t temp; 932 uint16_t i; 933 uint8_t event; 934 uint8_t j; 935 uint8_t k; 936 uint8_t t; 937 938 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 939 940 phwr = buf_res.buffer; 941 942 /* Receive any events */ 943 944 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 945 946 i = sc->sc_event_idx; 947 j = sc->sc_event_ccs; 948 t = 2; 949 950 while (1) { 951 952 temp = le32toh(phwr->hwr_events[i].dwTrb3); 953 954 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 955 956 if (j != k) 957 break; 958 959 event = XHCI_TRB_3_TYPE_GET(temp); 960 961 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 962 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 963 (long)le32toh(phwr->hwr_events[i].dwTrb2), 964 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 965 966 switch (event) { 967 case XHCI_TRB_EVENT_TRANSFER: 968 xhci_check_transfer(sc, &phwr->hwr_events[i]); 969 break; 970 case XHCI_TRB_EVENT_CMD_COMPLETE: 971 xhci_check_command(sc, &phwr->hwr_events[i]); 972 break; 973 default: 974 DPRINTF("Unhandled event = %u\n", event); 975 break; 976 } 977 978 i++; 979 980 if (i == XHCI_MAX_EVENTS) { 981 i = 0; 982 j ^= 1; 983 984 /* check for timeout */ 985 if (!--t) 986 break; 987 } 988 } 989 990 sc->sc_event_idx = i; 991 sc->sc_event_ccs = j; 992 993 /* 994 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 995 * latched. That means to activate the register we need to 996 * write both the low and high double word of the 64-bit 997 * register. 998 */ 999 1000 addr = (uint32_t)buf_res.physaddr; 1001 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1002 1003 /* try to clear busy bit */ 1004 addr |= XHCI_ERDP_LO_BUSY; 1005 1006 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1007 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1008 } 1009 1010 static usb_error_t 1011 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1012 uint16_t timeout_ms) 1013 { 1014 struct usb_page_search buf_res; 1015 struct xhci_hw_root *phwr; 1016 uint64_t addr; 1017 uint32_t temp; 1018 uint8_t i; 1019 uint8_t j; 1020 int err; 1021 1022 XHCI_CMD_ASSERT_LOCKED(sc); 1023 1024 /* get hardware root structure */ 1025 1026 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1027 1028 phwr = buf_res.buffer; 1029 1030 /* Queue command */ 1031 1032 USB_BUS_LOCK(&sc->sc_bus); 1033 1034 i = sc->sc_command_idx; 1035 j = sc->sc_command_ccs; 1036 1037 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1038 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1039 (long long)le64toh(trb->qwTrb0), 1040 (long)le32toh(trb->dwTrb2), 1041 (long)le32toh(trb->dwTrb3)); 1042 1043 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1044 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1045 1046 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1047 1048 temp = trb->dwTrb3; 1049 1050 if (j) 1051 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1052 else 1053 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1054 1055 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1056 1057 phwr->hwr_commands[i].dwTrb3 = temp; 1058 1059 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1060 1061 addr = buf_res.physaddr; 1062 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1063 1064 sc->sc_cmd_addr = htole64(addr); 1065 1066 i++; 1067 1068 if (i == (XHCI_MAX_COMMANDS - 1)) { 1069 1070 if (j) { 1071 temp = htole32(XHCI_TRB_3_TC_BIT | 1072 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1073 XHCI_TRB_3_CYCLE_BIT); 1074 } else { 1075 temp = htole32(XHCI_TRB_3_TC_BIT | 1076 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1077 } 1078 1079 phwr->hwr_commands[i].dwTrb3 = temp; 1080 1081 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1082 1083 i = 0; 1084 j ^= 1; 1085 } 1086 1087 sc->sc_command_idx = i; 1088 sc->sc_command_ccs = j; 1089 1090 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1091 1092 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1093 USB_MS_TO_TICKS(timeout_ms)); 1094 1095 if (err) { 1096 DPRINTFN(0, "Command timeout!\n"); 1097 err = USB_ERR_TIMEOUT; 1098 trb->dwTrb2 = 0; 1099 trb->dwTrb3 = 0; 1100 } else { 1101 temp = le32toh(sc->sc_cmd_result[0]); 1102 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1103 err = USB_ERR_IOERROR; 1104 1105 trb->dwTrb2 = sc->sc_cmd_result[0]; 1106 trb->dwTrb3 = sc->sc_cmd_result[1]; 1107 } 1108 1109 USB_BUS_UNLOCK(&sc->sc_bus); 1110 1111 return (err); 1112 } 1113 1114 #if 0 1115 static usb_error_t 1116 xhci_cmd_nop(struct xhci_softc *sc) 1117 { 1118 struct xhci_trb trb; 1119 uint32_t temp; 1120 1121 DPRINTF("\n"); 1122 1123 trb.qwTrb0 = 0; 1124 trb.dwTrb2 = 0; 1125 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1126 1127 trb.dwTrb3 = htole32(temp); 1128 1129 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1130 } 1131 #endif 1132 1133 static usb_error_t 1134 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1135 { 1136 struct xhci_trb trb; 1137 uint32_t temp; 1138 usb_error_t err; 1139 1140 DPRINTF("\n"); 1141 1142 trb.qwTrb0 = 0; 1143 trb.dwTrb2 = 0; 1144 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1145 1146 err = xhci_do_command(sc, &trb, 100 /* ms */); 1147 if (err) 1148 goto done; 1149 1150 temp = le32toh(trb.dwTrb3); 1151 1152 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1153 1154 done: 1155 return (err); 1156 } 1157 1158 static usb_error_t 1159 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1160 { 1161 struct xhci_trb trb; 1162 uint32_t temp; 1163 1164 DPRINTF("\n"); 1165 1166 trb.qwTrb0 = 0; 1167 trb.dwTrb2 = 0; 1168 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1169 XHCI_TRB_3_SLOT_SET(slot_id); 1170 1171 trb.dwTrb3 = htole32(temp); 1172 1173 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1174 } 1175 1176 static usb_error_t 1177 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1178 uint8_t bsr, uint8_t slot_id) 1179 { 1180 struct xhci_trb trb; 1181 uint32_t temp; 1182 1183 DPRINTF("\n"); 1184 1185 trb.qwTrb0 = htole64(input_ctx); 1186 trb.dwTrb2 = 0; 1187 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1188 XHCI_TRB_3_SLOT_SET(slot_id); 1189 1190 if (bsr) 1191 temp |= XHCI_TRB_3_BSR_BIT; 1192 1193 trb.dwTrb3 = htole32(temp); 1194 1195 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1196 } 1197 1198 static usb_error_t 1199 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1200 { 1201 struct usb_page_search buf_inp; 1202 struct usb_page_search buf_dev; 1203 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1204 struct xhci_hw_dev *hdev; 1205 struct xhci_dev_ctx *pdev; 1206 struct xhci_endpoint_ext *pepext; 1207 uint32_t temp; 1208 uint16_t mps; 1209 usb_error_t err; 1210 uint8_t index; 1211 1212 /* the root HUB case is not handled here */ 1213 if (udev->parent_hub == NULL) 1214 return (USB_ERR_INVAL); 1215 1216 index = udev->controller_slot_id; 1217 1218 hdev = &sc->sc_hw.devs[index]; 1219 1220 if (mtx != NULL) 1221 mtx_unlock(mtx); 1222 1223 XHCI_CMD_LOCK(sc); 1224 1225 switch (hdev->state) { 1226 case XHCI_ST_DEFAULT: 1227 case XHCI_ST_ENABLED: 1228 1229 hdev->state = XHCI_ST_ENABLED; 1230 1231 /* set configure mask to slot and EP0 */ 1232 xhci_configure_mask(udev, 3, 0); 1233 1234 /* configure input slot context structure */ 1235 err = xhci_configure_device(udev); 1236 1237 if (err != 0) { 1238 DPRINTF("Could not configure device\n"); 1239 break; 1240 } 1241 1242 /* configure input endpoint context structure */ 1243 switch (udev->speed) { 1244 case USB_SPEED_LOW: 1245 case USB_SPEED_FULL: 1246 mps = 8; 1247 break; 1248 case USB_SPEED_HIGH: 1249 mps = 64; 1250 break; 1251 default: 1252 mps = 512; 1253 break; 1254 } 1255 1256 pepext = xhci_get_endpoint_ext(udev, 1257 &udev->ctrl_ep_desc); 1258 err = xhci_configure_endpoint(udev, 1259 &udev->ctrl_ep_desc, pepext->physaddr, 1260 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1261 1262 if (err != 0) { 1263 DPRINTF("Could not configure default endpoint\n"); 1264 break; 1265 } 1266 1267 /* execute set address command */ 1268 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1269 1270 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1271 (address == 0), index); 1272 1273 if (err != 0) { 1274 DPRINTF("Could not set address " 1275 "for slot %u.\n", index); 1276 if (address != 0) 1277 break; 1278 } 1279 1280 /* update device address to new value */ 1281 1282 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1283 pdev = buf_dev.buffer; 1284 usb_pc_cpu_invalidate(&hdev->device_pc); 1285 1286 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1287 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1288 1289 /* update device state to new value */ 1290 1291 if (address != 0) 1292 hdev->state = XHCI_ST_ADDRESSED; 1293 else 1294 hdev->state = XHCI_ST_DEFAULT; 1295 break; 1296 1297 default: 1298 DPRINTF("Wrong state for set address.\n"); 1299 err = USB_ERR_IOERROR; 1300 break; 1301 } 1302 XHCI_CMD_UNLOCK(sc); 1303 1304 if (mtx != NULL) 1305 mtx_lock(mtx); 1306 1307 return (err); 1308 } 1309 1310 static usb_error_t 1311 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1312 uint8_t deconfigure, uint8_t slot_id) 1313 { 1314 struct xhci_trb trb; 1315 uint32_t temp; 1316 1317 DPRINTF("\n"); 1318 1319 trb.qwTrb0 = htole64(input_ctx); 1320 trb.dwTrb2 = 0; 1321 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1322 XHCI_TRB_3_SLOT_SET(slot_id); 1323 1324 if (deconfigure) 1325 temp |= XHCI_TRB_3_DCEP_BIT; 1326 1327 trb.dwTrb3 = htole32(temp); 1328 1329 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1330 } 1331 1332 static usb_error_t 1333 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1334 uint8_t slot_id) 1335 { 1336 struct xhci_trb trb; 1337 uint32_t temp; 1338 1339 DPRINTF("\n"); 1340 1341 trb.qwTrb0 = htole64(input_ctx); 1342 trb.dwTrb2 = 0; 1343 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1344 XHCI_TRB_3_SLOT_SET(slot_id); 1345 trb.dwTrb3 = htole32(temp); 1346 1347 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1348 } 1349 1350 static usb_error_t 1351 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1352 uint8_t ep_id, uint8_t slot_id) 1353 { 1354 struct xhci_trb trb; 1355 uint32_t temp; 1356 1357 DPRINTF("\n"); 1358 1359 trb.qwTrb0 = 0; 1360 trb.dwTrb2 = 0; 1361 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1362 XHCI_TRB_3_SLOT_SET(slot_id) | 1363 XHCI_TRB_3_EP_SET(ep_id); 1364 1365 if (preserve) 1366 temp |= XHCI_TRB_3_PRSV_BIT; 1367 1368 trb.dwTrb3 = htole32(temp); 1369 1370 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1371 } 1372 1373 static usb_error_t 1374 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1375 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1376 { 1377 struct xhci_trb trb; 1378 uint32_t temp; 1379 1380 DPRINTF("\n"); 1381 1382 trb.qwTrb0 = htole64(dequeue_ptr); 1383 1384 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1385 trb.dwTrb2 = htole32(temp); 1386 1387 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1388 XHCI_TRB_3_SLOT_SET(slot_id) | 1389 XHCI_TRB_3_EP_SET(ep_id); 1390 trb.dwTrb3 = htole32(temp); 1391 1392 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1393 } 1394 1395 static usb_error_t 1396 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1397 uint8_t ep_id, uint8_t slot_id) 1398 { 1399 struct xhci_trb trb; 1400 uint32_t temp; 1401 1402 DPRINTF("\n"); 1403 1404 trb.qwTrb0 = 0; 1405 trb.dwTrb2 = 0; 1406 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1407 XHCI_TRB_3_SLOT_SET(slot_id) | 1408 XHCI_TRB_3_EP_SET(ep_id); 1409 1410 if (suspend) 1411 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1412 1413 trb.dwTrb3 = htole32(temp); 1414 1415 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1416 } 1417 1418 static usb_error_t 1419 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1420 { 1421 struct xhci_trb trb; 1422 uint32_t temp; 1423 1424 DPRINTF("\n"); 1425 1426 trb.qwTrb0 = 0; 1427 trb.dwTrb2 = 0; 1428 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1429 XHCI_TRB_3_SLOT_SET(slot_id); 1430 1431 trb.dwTrb3 = htole32(temp); 1432 1433 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1434 } 1435 1436 /*------------------------------------------------------------------------* 1437 * xhci_interrupt - XHCI interrupt handler 1438 *------------------------------------------------------------------------*/ 1439 void 1440 xhci_interrupt(struct xhci_softc *sc) 1441 { 1442 uint32_t status; 1443 uint32_t iman; 1444 1445 USB_BUS_LOCK(&sc->sc_bus); 1446 1447 status = XREAD4(sc, oper, XHCI_USBSTS); 1448 if (status == 0) 1449 goto done; 1450 1451 /* acknowledge interrupts */ 1452 1453 XWRITE4(sc, oper, XHCI_USBSTS, status); 1454 1455 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1456 1457 if (status & XHCI_STS_EINT) { 1458 1459 /* acknowledge pending event */ 1460 iman = XREAD4(sc, runt, XHCI_IMAN(0)); 1461 1462 /* reset interrupt */ 1463 XWRITE4(sc, runt, XHCI_IMAN(0), iman); 1464 1465 DPRINTFN(16, "real interrupt (iman=0x%08x)\n", iman); 1466 1467 /* check for event(s) */ 1468 xhci_interrupt_poll(sc); 1469 } 1470 1471 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1472 XHCI_STS_HSE | XHCI_STS_HCE)) { 1473 1474 if (status & XHCI_STS_PCD) { 1475 xhci_root_intr(sc); 1476 } 1477 1478 if (status & XHCI_STS_HCH) { 1479 printf("%s: host controller halted\n", 1480 __FUNCTION__); 1481 } 1482 1483 if (status & XHCI_STS_HSE) { 1484 printf("%s: host system error\n", 1485 __FUNCTION__); 1486 } 1487 1488 if (status & XHCI_STS_HCE) { 1489 printf("%s: host controller error\n", 1490 __FUNCTION__); 1491 } 1492 } 1493 done: 1494 USB_BUS_UNLOCK(&sc->sc_bus); 1495 } 1496 1497 /*------------------------------------------------------------------------* 1498 * xhci_timeout - XHCI timeout handler 1499 *------------------------------------------------------------------------*/ 1500 static void 1501 xhci_timeout(void *arg) 1502 { 1503 struct usb_xfer *xfer = arg; 1504 1505 DPRINTF("xfer=%p\n", xfer); 1506 1507 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1508 1509 /* transfer is transferred */ 1510 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1511 } 1512 1513 static void 1514 xhci_do_poll(struct usb_bus *bus) 1515 { 1516 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1517 1518 USB_BUS_LOCK(&sc->sc_bus); 1519 xhci_interrupt_poll(sc); 1520 USB_BUS_UNLOCK(&sc->sc_bus); 1521 } 1522 1523 static void 1524 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1525 { 1526 struct usb_page_search buf_res; 1527 struct xhci_td *td; 1528 struct xhci_td *td_next; 1529 struct xhci_td *td_alt_next; 1530 uint32_t buf_offset; 1531 uint32_t average; 1532 uint32_t len_old; 1533 uint32_t dword; 1534 uint8_t shortpkt_old; 1535 uint8_t precompute; 1536 uint8_t x; 1537 1538 td_alt_next = NULL; 1539 buf_offset = 0; 1540 shortpkt_old = temp->shortpkt; 1541 len_old = temp->len; 1542 precompute = 1; 1543 1544 restart: 1545 1546 td = temp->td; 1547 td_next = temp->td_next; 1548 1549 while (1) { 1550 1551 if (temp->len == 0) { 1552 1553 if (temp->shortpkt) 1554 break; 1555 1556 /* send a Zero Length Packet, ZLP, last */ 1557 1558 temp->shortpkt = 1; 1559 average = 0; 1560 1561 } else { 1562 1563 average = temp->average; 1564 1565 if (temp->len < average) { 1566 if (temp->len % temp->max_packet_size) { 1567 temp->shortpkt = 1; 1568 } 1569 average = temp->len; 1570 } 1571 } 1572 1573 if (td_next == NULL) 1574 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1575 1576 /* get next TD */ 1577 1578 td = td_next; 1579 td_next = td->obj_next; 1580 1581 /* check if we are pre-computing */ 1582 1583 if (precompute) { 1584 1585 /* update remaining length */ 1586 1587 temp->len -= average; 1588 1589 continue; 1590 } 1591 /* fill out current TD */ 1592 1593 td->len = average; 1594 td->remainder = 0; 1595 td->status = 0; 1596 1597 /* update remaining length */ 1598 1599 temp->len -= average; 1600 1601 /* reset TRB index */ 1602 1603 x = 0; 1604 1605 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1606 /* immediate data */ 1607 1608 if (average > 8) 1609 average = 8; 1610 1611 td->td_trb[0].qwTrb0 = 0; 1612 1613 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1614 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1615 average); 1616 1617 dword = XHCI_TRB_2_BYTES_SET(8) | 1618 XHCI_TRB_2_TDSZ_SET(0) | 1619 XHCI_TRB_2_IRQ_SET(0); 1620 1621 td->td_trb[0].dwTrb2 = htole32(dword); 1622 1623 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1624 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1625 1626 /* check wLength */ 1627 if (td->td_trb[0].qwTrb0 & 1628 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1629 if (td->td_trb[0].qwTrb0 & htole64(1)) 1630 dword |= XHCI_TRB_3_TRT_IN; 1631 else 1632 dword |= XHCI_TRB_3_TRT_OUT; 1633 } 1634 1635 td->td_trb[0].dwTrb3 = htole32(dword); 1636 #ifdef USB_DEBUG 1637 xhci_dump_trb(&td->td_trb[x]); 1638 #endif 1639 x++; 1640 1641 } else do { 1642 1643 uint32_t npkt; 1644 1645 /* fill out buffer pointers */ 1646 1647 if (average == 0) { 1648 npkt = 1; 1649 memset(&buf_res, 0, sizeof(buf_res)); 1650 } else { 1651 usbd_get_page(temp->pc, temp->offset + 1652 buf_offset, &buf_res); 1653 1654 /* get length to end of page */ 1655 if (buf_res.length > average) 1656 buf_res.length = average; 1657 1658 /* check for maximum length */ 1659 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1660 buf_res.length = XHCI_TD_PAGE_SIZE; 1661 1662 /* setup npkt */ 1663 npkt = (average + temp->max_packet_size - 1) / 1664 temp->max_packet_size; 1665 1666 if (npkt > 31) 1667 npkt = 31; 1668 } 1669 1670 /* fill out TRB's */ 1671 td->td_trb[x].qwTrb0 = 1672 htole64((uint64_t)buf_res.physaddr); 1673 1674 dword = 1675 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1676 XHCI_TRB_2_TDSZ_SET(npkt) | 1677 XHCI_TRB_2_IRQ_SET(0); 1678 1679 td->td_trb[x].dwTrb2 = htole32(dword); 1680 1681 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1682 XHCI_TRB_3_TYPE_SET(temp->trb_type) | 1683 (temp->do_isoc_sync ? 1684 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) : 1685 XHCI_TRB_3_ISO_SIA_BIT) | 1686 XHCI_TRB_3_TBC_SET(temp->tbc) | 1687 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1688 1689 temp->do_isoc_sync = 0; 1690 1691 if (temp->direction == UE_DIR_IN) { 1692 dword |= XHCI_TRB_3_DIR_IN; 1693 1694 /* 1695 * NOTE: Only the SETUP stage should 1696 * use the IDT bit. Else transactions 1697 * can be sent using the wrong data 1698 * toggle value. 1699 */ 1700 if (temp->trb_type != 1701 XHCI_TRB_TYPE_SETUP_STAGE && 1702 temp->trb_type != 1703 XHCI_TRB_TYPE_STATUS_STAGE) 1704 dword |= XHCI_TRB_3_ISP_BIT; 1705 } 1706 1707 td->td_trb[x].dwTrb3 = htole32(dword); 1708 1709 average -= buf_res.length; 1710 buf_offset += buf_res.length; 1711 #ifdef USB_DEBUG 1712 xhci_dump_trb(&td->td_trb[x]); 1713 #endif 1714 x++; 1715 1716 } while (average != 0); 1717 1718 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1719 1720 /* store number of data TRB's */ 1721 1722 td->ntrb = x; 1723 1724 DPRINTF("NTRB=%u\n", x); 1725 1726 /* fill out link TRB */ 1727 1728 if (td_next != NULL) { 1729 /* link the current TD with the next one */ 1730 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1731 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1732 } else { 1733 /* this field will get updated later */ 1734 DPRINTF("NOLINK\n"); 1735 } 1736 1737 dword = XHCI_TRB_2_IRQ_SET(0); 1738 1739 td->td_trb[x].dwTrb2 = htole32(dword); 1740 1741 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1742 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT; 1743 1744 td->td_trb[x].dwTrb3 = htole32(dword); 1745 1746 td->alt_next = td_alt_next; 1747 #ifdef USB_DEBUG 1748 xhci_dump_trb(&td->td_trb[x]); 1749 #endif 1750 usb_pc_cpu_flush(td->page_cache); 1751 } 1752 1753 if (precompute) { 1754 precompute = 0; 1755 1756 /* setup alt next pointer, if any */ 1757 if (temp->last_frame) { 1758 td_alt_next = NULL; 1759 } else { 1760 /* we use this field internally */ 1761 td_alt_next = td_next; 1762 } 1763 1764 /* restore */ 1765 temp->shortpkt = shortpkt_old; 1766 temp->len = len_old; 1767 goto restart; 1768 } 1769 1770 /* remove cycle bit from first if we are stepping the TRBs */ 1771 if (temp->step_td) 1772 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1773 1774 /* remove chain bit because this is the last TRB in the chain */ 1775 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1776 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1777 1778 usb_pc_cpu_flush(td->page_cache); 1779 1780 temp->td = td; 1781 temp->td_next = td_next; 1782 } 1783 1784 static void 1785 xhci_setup_generic_chain(struct usb_xfer *xfer) 1786 { 1787 struct xhci_std_temp temp; 1788 struct xhci_td *td; 1789 uint32_t x; 1790 uint32_t y; 1791 uint8_t mult; 1792 1793 temp.do_isoc_sync = 0; 1794 temp.step_td = 0; 1795 temp.tbc = 0; 1796 temp.tlbpc = 0; 1797 temp.average = xfer->max_hc_frame_size; 1798 temp.max_packet_size = xfer->max_packet_size; 1799 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1800 temp.pc = NULL; 1801 temp.last_frame = 0; 1802 temp.offset = 0; 1803 temp.multishort = xfer->flags_int.isochronous_xfr || 1804 xfer->flags_int.control_xfr || 1805 xfer->flags_int.short_frames_ok; 1806 1807 /* toggle the DMA set we are using */ 1808 xfer->flags_int.curr_dma_set ^= 1; 1809 1810 /* get next DMA set */ 1811 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1812 1813 temp.td = NULL; 1814 temp.td_next = td; 1815 1816 xfer->td_transfer_first = td; 1817 xfer->td_transfer_cache = td; 1818 1819 if (xfer->flags_int.isochronous_xfr) { 1820 uint8_t shift; 1821 1822 /* compute multiplier for ISOCHRONOUS transfers */ 1823 mult = xfer->endpoint->ecomp ? 1824 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 1825 : 0; 1826 /* check for USB 2.0 multiplier */ 1827 if (mult == 0) { 1828 mult = (xfer->endpoint->edesc-> 1829 wMaxPacketSize[1] >> 3) & 3; 1830 } 1831 /* range check */ 1832 if (mult > 2) 1833 mult = 3; 1834 else 1835 mult++; 1836 1837 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 1838 1839 DPRINTF("MFINDEX=0x%08x\n", x); 1840 1841 switch (usbd_get_speed(xfer->xroot->udev)) { 1842 case USB_SPEED_FULL: 1843 shift = 3; 1844 temp.isoc_delta = 8; /* 1ms */ 1845 x += temp.isoc_delta - 1; 1846 x &= ~(temp.isoc_delta - 1); 1847 break; 1848 default: 1849 shift = usbd_xfer_get_fps_shift(xfer); 1850 temp.isoc_delta = 1U << shift; 1851 x += temp.isoc_delta - 1; 1852 x &= ~(temp.isoc_delta - 1); 1853 /* simple frame load balancing */ 1854 x += xfer->endpoint->usb_uframe; 1855 break; 1856 } 1857 1858 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 1859 1860 if ((xfer->endpoint->is_synced == 0) || 1861 (y < (xfer->nframes << shift)) || 1862 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 1863 /* 1864 * If there is data underflow or the pipe 1865 * queue is empty we schedule the transfer a 1866 * few frames ahead of the current frame 1867 * position. Else two isochronous transfers 1868 * might overlap. 1869 */ 1870 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 1871 xfer->endpoint->is_synced = 1; 1872 temp.do_isoc_sync = 1; 1873 1874 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1875 } 1876 1877 /* compute isochronous completion time */ 1878 1879 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 1880 1881 xfer->isoc_time_complete = 1882 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 1883 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 1884 1885 x = 0; 1886 temp.isoc_frame = xfer->endpoint->isoc_next; 1887 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 1888 1889 xfer->endpoint->isoc_next += xfer->nframes << shift; 1890 1891 } else if (xfer->flags_int.control_xfr) { 1892 1893 /* check if we should prepend a setup message */ 1894 1895 if (xfer->flags_int.control_hdr) { 1896 1897 temp.len = xfer->frlengths[0]; 1898 temp.pc = xfer->frbuffers + 0; 1899 temp.shortpkt = temp.len ? 1 : 0; 1900 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 1901 temp.direction = 0; 1902 1903 /* check for last frame */ 1904 if (xfer->nframes == 1) { 1905 /* no STATUS stage yet, SETUP is last */ 1906 if (xfer->flags_int.control_act) 1907 temp.last_frame = 1; 1908 } 1909 1910 xhci_setup_generic_chain_sub(&temp); 1911 } 1912 x = 1; 1913 mult = 1; 1914 temp.isoc_delta = 0; 1915 temp.isoc_frame = 0; 1916 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 1917 } else { 1918 x = 0; 1919 mult = 1; 1920 temp.isoc_delta = 0; 1921 temp.isoc_frame = 0; 1922 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 1923 } 1924 1925 if (x != xfer->nframes) { 1926 /* setup page_cache pointer */ 1927 temp.pc = xfer->frbuffers + x; 1928 /* set endpoint direction */ 1929 temp.direction = UE_GET_DIR(xfer->endpointno); 1930 } 1931 1932 while (x != xfer->nframes) { 1933 1934 /* DATA0 / DATA1 message */ 1935 1936 temp.len = xfer->frlengths[x]; 1937 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 1938 x != 0 && temp.multishort == 0); 1939 1940 x++; 1941 1942 if (x == xfer->nframes) { 1943 if (xfer->flags_int.control_xfr) { 1944 /* no STATUS stage yet, DATA is last */ 1945 if (xfer->flags_int.control_act) 1946 temp.last_frame = 1; 1947 } else { 1948 temp.last_frame = 1; 1949 } 1950 } 1951 if (temp.len == 0) { 1952 1953 /* make sure that we send an USB packet */ 1954 1955 temp.shortpkt = 0; 1956 1957 temp.tbc = 0; 1958 temp.tlbpc = mult - 1; 1959 1960 } else if (xfer->flags_int.isochronous_xfr) { 1961 1962 uint8_t tdpc; 1963 1964 /* 1965 * Isochronous transfers don't have short 1966 * packet termination: 1967 */ 1968 1969 temp.shortpkt = 1; 1970 1971 /* isochronous transfers have a transfer limit */ 1972 1973 if (temp.len > xfer->max_frame_size) 1974 temp.len = xfer->max_frame_size; 1975 1976 /* compute TD packet count */ 1977 tdpc = (temp.len + xfer->max_packet_size - 1) / 1978 xfer->max_packet_size; 1979 1980 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 1981 temp.tlbpc = (tdpc % mult); 1982 1983 if (temp.tlbpc == 0) 1984 temp.tlbpc = mult - 1; 1985 else 1986 temp.tlbpc--; 1987 } else { 1988 1989 /* regular data transfer */ 1990 1991 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 1992 } 1993 1994 xhci_setup_generic_chain_sub(&temp); 1995 1996 if (xfer->flags_int.isochronous_xfr) { 1997 temp.offset += xfer->frlengths[x - 1]; 1998 temp.isoc_frame += temp.isoc_delta; 1999 } else { 2000 /* get next Page Cache pointer */ 2001 temp.pc = xfer->frbuffers + x; 2002 } 2003 } 2004 2005 /* check if we should append a status stage */ 2006 2007 if (xfer->flags_int.control_xfr && 2008 !xfer->flags_int.control_act) { 2009 2010 /* 2011 * Send a DATA1 message and invert the current 2012 * endpoint direction. 2013 */ 2014 temp.step_td = (xfer->nframes != 0); 2015 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2016 temp.len = 0; 2017 temp.pc = NULL; 2018 temp.shortpkt = 0; 2019 temp.last_frame = 1; 2020 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2021 2022 xhci_setup_generic_chain_sub(&temp); 2023 } 2024 2025 td = temp.td; 2026 2027 /* must have at least one frame! */ 2028 2029 xfer->td_transfer_last = td; 2030 2031 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2032 } 2033 2034 static void 2035 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2036 { 2037 struct usb_page_search buf_res; 2038 struct xhci_dev_ctx_addr *pdctxa; 2039 2040 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2041 2042 pdctxa = buf_res.buffer; 2043 2044 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2045 2046 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2047 2048 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2049 } 2050 2051 static usb_error_t 2052 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2053 { 2054 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2055 struct usb_page_search buf_inp; 2056 struct xhci_input_dev_ctx *pinp; 2057 uint32_t temp; 2058 uint8_t index; 2059 uint8_t x; 2060 2061 index = udev->controller_slot_id; 2062 2063 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2064 2065 pinp = buf_inp.buffer; 2066 2067 if (drop) { 2068 mask &= XHCI_INCTX_NON_CTRL_MASK; 2069 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2070 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2071 } else { 2072 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2073 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2074 2075 /* find most significant set bit */ 2076 for (x = 31; x != 1; x--) { 2077 if (mask & (1 << x)) 2078 break; 2079 } 2080 2081 /* adjust */ 2082 x--; 2083 2084 /* figure out maximum */ 2085 if (x > sc->sc_hw.devs[index].context_num) { 2086 sc->sc_hw.devs[index].context_num = x; 2087 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2088 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2089 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2090 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2091 } 2092 } 2093 return (0); 2094 } 2095 2096 static usb_error_t 2097 xhci_configure_endpoint(struct usb_device *udev, 2098 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr, 2099 uint16_t interval, uint8_t max_packet_count, uint8_t mult, 2100 uint8_t fps_shift, uint16_t max_packet_size, 2101 uint16_t max_frame_size, uint8_t ep_mode) 2102 { 2103 struct usb_page_search buf_inp; 2104 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2105 struct xhci_input_dev_ctx *pinp; 2106 uint32_t temp; 2107 uint8_t index; 2108 uint8_t epno; 2109 uint8_t type; 2110 2111 index = udev->controller_slot_id; 2112 2113 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2114 2115 pinp = buf_inp.buffer; 2116 2117 epno = edesc->bEndpointAddress; 2118 type = edesc->bmAttributes & UE_XFERTYPE; 2119 2120 if (type == UE_CONTROL) 2121 epno |= UE_DIR_IN; 2122 2123 epno = XHCI_EPNO2EPID(epno); 2124 2125 if (epno == 0) 2126 return (USB_ERR_NO_PIPE); /* invalid */ 2127 2128 if (max_packet_count == 0) 2129 return (USB_ERR_BAD_BUFSIZE); 2130 2131 max_packet_count--; 2132 2133 if (mult == 0) 2134 return (USB_ERR_BAD_BUFSIZE); 2135 2136 if (ep_mode == USB_EP_MODE_STREAMS) { 2137 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2138 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2139 XHCI_EPCTX_0_LSA_SET(1); 2140 2141 ring_addr += sizeof(struct xhci_trb) * 2142 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2143 } else { 2144 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2145 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2146 XHCI_EPCTX_0_LSA_SET(0); 2147 2148 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2149 } 2150 2151 switch (udev->speed) { 2152 case USB_SPEED_FULL: 2153 case USB_SPEED_LOW: 2154 /* 1ms -> 125us */ 2155 fps_shift += 3; 2156 break; 2157 default: 2158 break; 2159 } 2160 2161 switch (type) { 2162 case UE_INTERRUPT: 2163 if (fps_shift > 3) 2164 fps_shift--; 2165 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2166 break; 2167 case UE_ISOCHRONOUS: 2168 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2169 2170 switch (udev->speed) { 2171 case USB_SPEED_SUPER: 2172 if (mult > 3) 2173 mult = 3; 2174 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2175 max_packet_count /= mult; 2176 break; 2177 default: 2178 break; 2179 } 2180 break; 2181 default: 2182 break; 2183 } 2184 2185 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2186 2187 temp = 2188 XHCI_EPCTX_1_HID_SET(0) | 2189 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2190 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2191 2192 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2193 if (type != UE_ISOCHRONOUS) 2194 temp |= XHCI_EPCTX_1_CERR_SET(3); 2195 } 2196 2197 switch (type) { 2198 case UE_CONTROL: 2199 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2200 break; 2201 case UE_ISOCHRONOUS: 2202 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2203 break; 2204 case UE_BULK: 2205 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2206 break; 2207 default: 2208 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2209 break; 2210 } 2211 2212 /* check for IN direction */ 2213 if (epno & 1) 2214 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2215 2216 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2217 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2218 2219 switch (edesc->bmAttributes & UE_XFERTYPE) { 2220 case UE_INTERRUPT: 2221 case UE_ISOCHRONOUS: 2222 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2223 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2224 max_frame_size)); 2225 break; 2226 case UE_CONTROL: 2227 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2228 break; 2229 default: 2230 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2231 break; 2232 } 2233 2234 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2235 2236 #ifdef USB_DEBUG 2237 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2238 #endif 2239 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2240 2241 return (0); /* success */ 2242 } 2243 2244 static usb_error_t 2245 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2246 { 2247 struct xhci_endpoint_ext *pepext; 2248 struct usb_endpoint_ss_comp_descriptor *ecomp; 2249 usb_stream_t x; 2250 2251 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2252 xfer->endpoint->edesc); 2253 2254 ecomp = xfer->endpoint->ecomp; 2255 2256 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2257 uint64_t temp; 2258 2259 /* halt any transfers */ 2260 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2261 2262 /* compute start of TRB ring for stream "x" */ 2263 temp = pepext->physaddr + 2264 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2265 XHCI_SCTX_0_SCT_SEC_TR_RING; 2266 2267 /* make tree structure */ 2268 pepext->trb[(XHCI_MAX_TRANSFERS * 2269 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2270 2271 /* reserved fields */ 2272 pepext->trb[(XHCI_MAX_TRANSFERS * 2273 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2274 pepext->trb[(XHCI_MAX_TRANSFERS * 2275 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2276 } 2277 usb_pc_cpu_flush(pepext->page_cache); 2278 2279 return (xhci_configure_endpoint(xfer->xroot->udev, 2280 xfer->endpoint->edesc, pepext->physaddr, 2281 xfer->interval, xfer->max_packet_count, 2282 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2283 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2284 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2285 } 2286 2287 static usb_error_t 2288 xhci_configure_device(struct usb_device *udev) 2289 { 2290 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2291 struct usb_page_search buf_inp; 2292 struct usb_page_cache *pcinp; 2293 struct xhci_input_dev_ctx *pinp; 2294 struct usb_device *hubdev; 2295 uint32_t temp; 2296 uint32_t route; 2297 uint32_t rh_port; 2298 uint8_t is_hub; 2299 uint8_t index; 2300 uint8_t depth; 2301 2302 index = udev->controller_slot_id; 2303 2304 DPRINTF("index=%u\n", index); 2305 2306 pcinp = &sc->sc_hw.devs[index].input_pc; 2307 2308 usbd_get_page(pcinp, 0, &buf_inp); 2309 2310 pinp = buf_inp.buffer; 2311 2312 rh_port = 0; 2313 route = 0; 2314 2315 /* figure out route string and root HUB port number */ 2316 2317 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2318 2319 if (hubdev->parent_hub == NULL) 2320 break; 2321 2322 depth = hubdev->parent_hub->depth; 2323 2324 /* 2325 * NOTE: HS/FS/LS devices and the SS root HUB can have 2326 * more than 15 ports 2327 */ 2328 2329 rh_port = hubdev->port_no; 2330 2331 if (depth == 0) 2332 break; 2333 2334 if (rh_port > 15) 2335 rh_port = 15; 2336 2337 if (depth < 6) 2338 route |= rh_port << (4 * (depth - 1)); 2339 } 2340 2341 DPRINTF("Route=0x%08x\n", route); 2342 2343 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2344 XHCI_SCTX_0_CTX_NUM_SET( 2345 sc->sc_hw.devs[index].context_num + 1); 2346 2347 switch (udev->speed) { 2348 case USB_SPEED_LOW: 2349 temp |= XHCI_SCTX_0_SPEED_SET(2); 2350 if (udev->parent_hs_hub != NULL && 2351 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2352 UDPROTO_HSHUBMTT) { 2353 DPRINTF("Device inherits MTT\n"); 2354 temp |= XHCI_SCTX_0_MTT_SET(1); 2355 } 2356 break; 2357 case USB_SPEED_HIGH: 2358 temp |= XHCI_SCTX_0_SPEED_SET(3); 2359 if (sc->sc_hw.devs[index].nports != 0 && 2360 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2361 DPRINTF("HUB supports MTT\n"); 2362 temp |= XHCI_SCTX_0_MTT_SET(1); 2363 } 2364 break; 2365 case USB_SPEED_FULL: 2366 temp |= XHCI_SCTX_0_SPEED_SET(1); 2367 if (udev->parent_hs_hub != NULL && 2368 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2369 UDPROTO_HSHUBMTT) { 2370 DPRINTF("Device inherits MTT\n"); 2371 temp |= XHCI_SCTX_0_MTT_SET(1); 2372 } 2373 break; 2374 default: 2375 temp |= XHCI_SCTX_0_SPEED_SET(4); 2376 break; 2377 } 2378 2379 is_hub = sc->sc_hw.devs[index].nports != 0 && 2380 (udev->speed == USB_SPEED_SUPER || 2381 udev->speed == USB_SPEED_HIGH); 2382 2383 if (is_hub) 2384 temp |= XHCI_SCTX_0_HUB_SET(1); 2385 2386 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2387 2388 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2389 2390 if (is_hub) { 2391 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2392 sc->sc_hw.devs[index].nports); 2393 } 2394 2395 switch (udev->speed) { 2396 case USB_SPEED_SUPER: 2397 switch (sc->sc_hw.devs[index].state) { 2398 case XHCI_ST_ADDRESSED: 2399 case XHCI_ST_CONFIGURED: 2400 /* enable power save */ 2401 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2402 break; 2403 default: 2404 /* disable power save */ 2405 break; 2406 } 2407 break; 2408 default: 2409 break; 2410 } 2411 2412 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2413 2414 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2415 2416 if (is_hub) { 2417 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2418 sc->sc_hw.devs[index].tt); 2419 } 2420 2421 hubdev = udev->parent_hs_hub; 2422 2423 /* check if we should activate the transaction translator */ 2424 switch (udev->speed) { 2425 case USB_SPEED_FULL: 2426 case USB_SPEED_LOW: 2427 if (hubdev != NULL) { 2428 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2429 hubdev->controller_slot_id); 2430 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2431 udev->hs_port_no); 2432 } 2433 break; 2434 default: 2435 break; 2436 } 2437 2438 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2439 2440 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) | 2441 XHCI_SCTX_3_SLOT_STATE_SET(0); 2442 2443 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2444 2445 #ifdef USB_DEBUG 2446 xhci_dump_device(sc, &pinp->ctx_slot); 2447 #endif 2448 usb_pc_cpu_flush(pcinp); 2449 2450 return (0); /* success */ 2451 } 2452 2453 static usb_error_t 2454 xhci_alloc_device_ext(struct usb_device *udev) 2455 { 2456 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2457 struct usb_page_search buf_dev; 2458 struct usb_page_search buf_ep; 2459 struct xhci_trb *trb; 2460 struct usb_page_cache *pc; 2461 struct usb_page *pg; 2462 uint64_t addr; 2463 uint8_t index; 2464 uint8_t i; 2465 2466 index = udev->controller_slot_id; 2467 2468 pc = &sc->sc_hw.devs[index].device_pc; 2469 pg = &sc->sc_hw.devs[index].device_pg; 2470 2471 /* need to initialize the page cache */ 2472 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2473 2474 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2475 (2 * sizeof(struct xhci_dev_ctx)) : 2476 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2477 goto error; 2478 2479 usbd_get_page(pc, 0, &buf_dev); 2480 2481 pc = &sc->sc_hw.devs[index].input_pc; 2482 pg = &sc->sc_hw.devs[index].input_pg; 2483 2484 /* need to initialize the page cache */ 2485 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2486 2487 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2488 (2 * sizeof(struct xhci_input_dev_ctx)) : 2489 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2490 goto error; 2491 } 2492 2493 pc = &sc->sc_hw.devs[index].endpoint_pc; 2494 pg = &sc->sc_hw.devs[index].endpoint_pg; 2495 2496 /* need to initialize the page cache */ 2497 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2498 2499 if (usb_pc_alloc_mem(pc, pg, 2500 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) { 2501 goto error; 2502 } 2503 2504 /* initialise all endpoint LINK TRBs */ 2505 2506 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2507 2508 /* lookup endpoint TRB ring */ 2509 usbd_get_page(pc, (uintptr_t)& 2510 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2511 2512 /* get TRB pointer */ 2513 trb = buf_ep.buffer; 2514 trb += XHCI_MAX_TRANSFERS - 1; 2515 2516 /* get TRB start address */ 2517 addr = buf_ep.physaddr; 2518 2519 /* create LINK TRB */ 2520 trb->qwTrb0 = htole64(addr); 2521 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2522 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2523 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2524 } 2525 2526 usb_pc_cpu_flush(pc); 2527 2528 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2529 2530 return (0); 2531 2532 error: 2533 xhci_free_device_ext(udev); 2534 2535 return (USB_ERR_NOMEM); 2536 } 2537 2538 static void 2539 xhci_free_device_ext(struct usb_device *udev) 2540 { 2541 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2542 uint8_t index; 2543 2544 index = udev->controller_slot_id; 2545 xhci_set_slot_pointer(sc, index, 0); 2546 2547 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2548 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2549 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2550 } 2551 2552 static struct xhci_endpoint_ext * 2553 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2554 { 2555 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2556 struct xhci_endpoint_ext *pepext; 2557 struct usb_page_cache *pc; 2558 struct usb_page_search buf_ep; 2559 uint8_t epno; 2560 uint8_t index; 2561 2562 epno = edesc->bEndpointAddress; 2563 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2564 epno |= UE_DIR_IN; 2565 2566 epno = XHCI_EPNO2EPID(epno); 2567 2568 index = udev->controller_slot_id; 2569 2570 pc = &sc->sc_hw.devs[index].endpoint_pc; 2571 2572 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2573 trb[epno][0], &buf_ep); 2574 2575 pepext = &sc->sc_hw.devs[index].endp[epno]; 2576 pepext->page_cache = pc; 2577 pepext->trb = buf_ep.buffer; 2578 pepext->physaddr = buf_ep.physaddr; 2579 2580 return (pepext); 2581 } 2582 2583 static void 2584 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2585 { 2586 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2587 uint8_t epno; 2588 uint8_t index; 2589 2590 epno = xfer->endpointno; 2591 if (xfer->flags_int.control_xfr) 2592 epno |= UE_DIR_IN; 2593 2594 epno = XHCI_EPNO2EPID(epno); 2595 index = xfer->xroot->udev->controller_slot_id; 2596 2597 if (xfer->xroot->udev->flags.self_suspended == 0) { 2598 XWRITE4(sc, door, XHCI_DOORBELL(index), 2599 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2600 } 2601 } 2602 2603 static void 2604 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2605 { 2606 struct xhci_endpoint_ext *pepext; 2607 2608 if (xfer->flags_int.bandwidth_reclaimed) { 2609 xfer->flags_int.bandwidth_reclaimed = 0; 2610 2611 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2612 xfer->endpoint->edesc); 2613 2614 pepext->trb_used[xfer->stream_id]--; 2615 2616 pepext->xfer[xfer->qh_pos] = NULL; 2617 2618 if (error && pepext->trb_running != 0) { 2619 pepext->trb_halted = 1; 2620 pepext->trb_running = 0; 2621 } 2622 } 2623 } 2624 2625 static usb_error_t 2626 xhci_transfer_insert(struct usb_xfer *xfer) 2627 { 2628 struct xhci_td *td_first; 2629 struct xhci_td *td_last; 2630 struct xhci_endpoint_ext *pepext; 2631 uint64_t addr; 2632 usb_stream_t id; 2633 uint8_t i; 2634 uint8_t inext; 2635 uint8_t trb_limit; 2636 2637 DPRINTFN(8, "\n"); 2638 2639 id = xfer->stream_id; 2640 2641 /* check if already inserted */ 2642 if (xfer->flags_int.bandwidth_reclaimed) { 2643 DPRINTFN(8, "Already in schedule\n"); 2644 return (0); 2645 } 2646 2647 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2648 xfer->endpoint->edesc); 2649 2650 td_first = xfer->td_transfer_first; 2651 td_last = xfer->td_transfer_last; 2652 addr = pepext->physaddr; 2653 2654 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2655 case UE_CONTROL: 2656 case UE_INTERRUPT: 2657 /* single buffered */ 2658 trb_limit = 1; 2659 break; 2660 default: 2661 /* multi buffered */ 2662 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2663 break; 2664 } 2665 2666 if (pepext->trb_used[id] >= trb_limit) { 2667 DPRINTFN(8, "Too many TDs queued.\n"); 2668 return (USB_ERR_NOMEM); 2669 } 2670 2671 /* check for stopped condition, after putting transfer on interrupt queue */ 2672 if (pepext->trb_running == 0) { 2673 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2674 2675 DPRINTFN(8, "Not running\n"); 2676 2677 /* start configuration */ 2678 (void)usb_proc_msignal(&sc->sc_config_proc, 2679 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2680 return (0); 2681 } 2682 2683 pepext->trb_used[id]++; 2684 2685 /* get current TRB index */ 2686 i = pepext->trb_index[id]; 2687 2688 /* get next TRB index */ 2689 inext = (i + 1); 2690 2691 /* the last entry of the ring is a hardcoded link TRB */ 2692 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2693 inext = 0; 2694 2695 /* offset for stream */ 2696 i += id * XHCI_MAX_TRANSFERS; 2697 inext += id * XHCI_MAX_TRANSFERS; 2698 2699 /* compute terminating return address */ 2700 addr += (inext * sizeof(struct xhci_trb)); 2701 2702 /* update next pointer of last link TRB */ 2703 td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr); 2704 td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2705 td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2706 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2707 2708 #ifdef USB_DEBUG 2709 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2710 #endif 2711 usb_pc_cpu_flush(td_last->page_cache); 2712 2713 /* write ahead chain end marker */ 2714 2715 pepext->trb[inext].qwTrb0 = 0; 2716 pepext->trb[inext].dwTrb2 = 0; 2717 pepext->trb[inext].dwTrb3 = 0; 2718 2719 /* update next pointer of link TRB */ 2720 2721 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2722 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2723 2724 #ifdef USB_DEBUG 2725 xhci_dump_trb(&pepext->trb[i]); 2726 #endif 2727 usb_pc_cpu_flush(pepext->page_cache); 2728 2729 /* toggle cycle bit which activates the transfer chain */ 2730 2731 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2732 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2733 2734 usb_pc_cpu_flush(pepext->page_cache); 2735 2736 DPRINTF("qh_pos = %u\n", i); 2737 2738 pepext->xfer[i] = xfer; 2739 2740 xfer->qh_pos = i; 2741 2742 xfer->flags_int.bandwidth_reclaimed = 1; 2743 2744 pepext->trb_index[id] = inext; 2745 2746 xhci_endpoint_doorbell(xfer); 2747 2748 return (0); 2749 } 2750 2751 static void 2752 xhci_root_intr(struct xhci_softc *sc) 2753 { 2754 uint16_t i; 2755 2756 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2757 2758 /* clear any old interrupt data */ 2759 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2760 2761 for (i = 1; i <= sc->sc_noport; i++) { 2762 /* pick out CHANGE bits from the status register */ 2763 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2764 XHCI_PS_CSC | XHCI_PS_PEC | 2765 XHCI_PS_OCC | XHCI_PS_WRC | 2766 XHCI_PS_PRC | XHCI_PS_PLC | 2767 XHCI_PS_CEC)) { 2768 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2769 DPRINTF("port %d changed\n", i); 2770 } 2771 } 2772 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2773 sizeof(sc->sc_hub_idata)); 2774 } 2775 2776 /*------------------------------------------------------------------------* 2777 * xhci_device_done - XHCI done handler 2778 * 2779 * NOTE: This function can be called two times in a row on 2780 * the same USB transfer. From close and from interrupt. 2781 *------------------------------------------------------------------------*/ 2782 static void 2783 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2784 { 2785 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2786 xfer, xfer->endpoint, error); 2787 2788 /* remove transfer from HW queue */ 2789 xhci_transfer_remove(xfer, error); 2790 2791 /* dequeue transfer and start next transfer */ 2792 usbd_transfer_done(xfer, error); 2793 } 2794 2795 /*------------------------------------------------------------------------* 2796 * XHCI data transfer support (generic type) 2797 *------------------------------------------------------------------------*/ 2798 static void 2799 xhci_device_generic_open(struct usb_xfer *xfer) 2800 { 2801 if (xfer->flags_int.isochronous_xfr) { 2802 switch (xfer->xroot->udev->speed) { 2803 case USB_SPEED_FULL: 2804 break; 2805 default: 2806 usb_hs_bandwidth_alloc(xfer); 2807 break; 2808 } 2809 } 2810 } 2811 2812 static void 2813 xhci_device_generic_close(struct usb_xfer *xfer) 2814 { 2815 DPRINTF("\n"); 2816 2817 xhci_device_done(xfer, USB_ERR_CANCELLED); 2818 2819 if (xfer->flags_int.isochronous_xfr) { 2820 switch (xfer->xroot->udev->speed) { 2821 case USB_SPEED_FULL: 2822 break; 2823 default: 2824 usb_hs_bandwidth_free(xfer); 2825 break; 2826 } 2827 } 2828 } 2829 2830 static void 2831 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 2832 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 2833 { 2834 struct usb_xfer *xfer; 2835 2836 /* check if there is a current transfer */ 2837 xfer = ep->endpoint_q[stream_id].curr; 2838 if (xfer == NULL) 2839 return; 2840 2841 /* 2842 * Check if the current transfer is started and then pickup 2843 * the next one, if any. Else wait for next start event due to 2844 * block on failure feature. 2845 */ 2846 if (!xfer->flags_int.bandwidth_reclaimed) 2847 return; 2848 2849 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 2850 if (xfer == NULL) { 2851 /* 2852 * In case of enter we have to consider that the 2853 * transfer is queued by the USB core after the enter 2854 * method is called. 2855 */ 2856 xfer = enter_xfer; 2857 2858 if (xfer == NULL) 2859 return; 2860 } 2861 2862 /* try to multi buffer */ 2863 xhci_transfer_insert(xfer); 2864 } 2865 2866 static void 2867 xhci_device_generic_enter(struct usb_xfer *xfer) 2868 { 2869 DPRINTF("\n"); 2870 2871 /* setup TD's and QH */ 2872 xhci_setup_generic_chain(xfer); 2873 2874 xhci_device_generic_multi_enter(xfer->endpoint, 2875 xfer->stream_id, xfer); 2876 } 2877 2878 static void 2879 xhci_device_generic_start(struct usb_xfer *xfer) 2880 { 2881 DPRINTF("\n"); 2882 2883 /* try to insert xfer on HW queue */ 2884 xhci_transfer_insert(xfer); 2885 2886 /* try to multi buffer */ 2887 xhci_device_generic_multi_enter(xfer->endpoint, 2888 xfer->stream_id, NULL); 2889 2890 /* add transfer last on interrupt queue */ 2891 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2892 2893 /* start timeout, if any */ 2894 if (xfer->timeout != 0) 2895 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 2896 } 2897 2898 struct usb_pipe_methods xhci_device_generic_methods = 2899 { 2900 .open = xhci_device_generic_open, 2901 .close = xhci_device_generic_close, 2902 .enter = xhci_device_generic_enter, 2903 .start = xhci_device_generic_start, 2904 }; 2905 2906 /*------------------------------------------------------------------------* 2907 * xhci root HUB support 2908 *------------------------------------------------------------------------* 2909 * Simulate a hardware HUB by handling all the necessary requests. 2910 *------------------------------------------------------------------------*/ 2911 2912 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 2913 2914 static const 2915 struct usb_device_descriptor xhci_devd = 2916 { 2917 .bLength = sizeof(xhci_devd), 2918 .bDescriptorType = UDESC_DEVICE, /* type */ 2919 HSETW(.bcdUSB, 0x0300), /* USB version */ 2920 .bDeviceClass = UDCLASS_HUB, /* class */ 2921 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 2922 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 2923 .bMaxPacketSize = 9, /* max packet size */ 2924 HSETW(.idVendor, 0x0000), /* vendor */ 2925 HSETW(.idProduct, 0x0000), /* product */ 2926 HSETW(.bcdDevice, 0x0100), /* device version */ 2927 .iManufacturer = 1, 2928 .iProduct = 2, 2929 .iSerialNumber = 0, 2930 .bNumConfigurations = 1, /* # of configurations */ 2931 }; 2932 2933 static const 2934 struct xhci_bos_desc xhci_bosd = { 2935 .bosd = { 2936 .bLength = sizeof(xhci_bosd.bosd), 2937 .bDescriptorType = UDESC_BOS, 2938 HSETW(.wTotalLength, sizeof(xhci_bosd)), 2939 .bNumDeviceCaps = 3, 2940 }, 2941 .usb2extd = { 2942 .bLength = sizeof(xhci_bosd.usb2extd), 2943 .bDescriptorType = 1, 2944 .bDevCapabilityType = 2, 2945 .bmAttributes[0] = 2, 2946 }, 2947 .usbdcd = { 2948 .bLength = sizeof(xhci_bosd.usbdcd), 2949 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 2950 .bDevCapabilityType = 3, 2951 .bmAttributes = 0, /* XXX */ 2952 HSETW(.wSpeedsSupported, 0x000C), 2953 .bFunctionalitySupport = 8, 2954 .bU1DevExitLat = 255, /* dummy - not used */ 2955 .wU2DevExitLat = { 0x00, 0x08 }, 2956 }, 2957 .cidd = { 2958 .bLength = sizeof(xhci_bosd.cidd), 2959 .bDescriptorType = 1, 2960 .bDevCapabilityType = 4, 2961 .bReserved = 0, 2962 .bContainerID = 0, /* XXX */ 2963 }, 2964 }; 2965 2966 static const 2967 struct xhci_config_desc xhci_confd = { 2968 .confd = { 2969 .bLength = sizeof(xhci_confd.confd), 2970 .bDescriptorType = UDESC_CONFIG, 2971 .wTotalLength[0] = sizeof(xhci_confd), 2972 .bNumInterface = 1, 2973 .bConfigurationValue = 1, 2974 .iConfiguration = 0, 2975 .bmAttributes = UC_SELF_POWERED, 2976 .bMaxPower = 0 /* max power */ 2977 }, 2978 .ifcd = { 2979 .bLength = sizeof(xhci_confd.ifcd), 2980 .bDescriptorType = UDESC_INTERFACE, 2981 .bNumEndpoints = 1, 2982 .bInterfaceClass = UICLASS_HUB, 2983 .bInterfaceSubClass = UISUBCLASS_HUB, 2984 .bInterfaceProtocol = 0, 2985 }, 2986 .endpd = { 2987 .bLength = sizeof(xhci_confd.endpd), 2988 .bDescriptorType = UDESC_ENDPOINT, 2989 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 2990 .bmAttributes = UE_INTERRUPT, 2991 .wMaxPacketSize[0] = 2, /* max 15 ports */ 2992 .bInterval = 255, 2993 }, 2994 .endpcd = { 2995 .bLength = sizeof(xhci_confd.endpcd), 2996 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 2997 .bMaxBurst = 0, 2998 .bmAttributes = 0, 2999 }, 3000 }; 3001 3002 static const 3003 struct usb_hub_ss_descriptor xhci_hubd = { 3004 .bLength = sizeof(xhci_hubd), 3005 .bDescriptorType = UDESC_SS_HUB, 3006 }; 3007 3008 static usb_error_t 3009 xhci_roothub_exec(struct usb_device *udev, 3010 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3011 { 3012 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3013 const char *str_ptr; 3014 const void *ptr; 3015 uint32_t port; 3016 uint32_t v; 3017 uint16_t len; 3018 uint16_t i; 3019 uint16_t value; 3020 uint16_t index; 3021 uint8_t j; 3022 usb_error_t err; 3023 3024 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3025 3026 /* buffer reset */ 3027 ptr = (const void *)&sc->sc_hub_desc; 3028 len = 0; 3029 err = 0; 3030 3031 value = UGETW(req->wValue); 3032 index = UGETW(req->wIndex); 3033 3034 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3035 "wValue=0x%04x wIndex=0x%04x\n", 3036 req->bmRequestType, req->bRequest, 3037 UGETW(req->wLength), value, index); 3038 3039 #define C(x,y) ((x) | ((y) << 8)) 3040 switch (C(req->bRequest, req->bmRequestType)) { 3041 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3042 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3043 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3044 /* 3045 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3046 * for the integrated root hub. 3047 */ 3048 break; 3049 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3050 len = 1; 3051 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3052 break; 3053 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3054 switch (value >> 8) { 3055 case UDESC_DEVICE: 3056 if ((value & 0xff) != 0) { 3057 err = USB_ERR_IOERROR; 3058 goto done; 3059 } 3060 len = sizeof(xhci_devd); 3061 ptr = (const void *)&xhci_devd; 3062 break; 3063 3064 case UDESC_BOS: 3065 if ((value & 0xff) != 0) { 3066 err = USB_ERR_IOERROR; 3067 goto done; 3068 } 3069 len = sizeof(xhci_bosd); 3070 ptr = (const void *)&xhci_bosd; 3071 break; 3072 3073 case UDESC_CONFIG: 3074 if ((value & 0xff) != 0) { 3075 err = USB_ERR_IOERROR; 3076 goto done; 3077 } 3078 len = sizeof(xhci_confd); 3079 ptr = (const void *)&xhci_confd; 3080 break; 3081 3082 case UDESC_STRING: 3083 switch (value & 0xff) { 3084 case 0: /* Language table */ 3085 str_ptr = "\001"; 3086 break; 3087 3088 case 1: /* Vendor */ 3089 str_ptr = sc->sc_vendor; 3090 break; 3091 3092 case 2: /* Product */ 3093 str_ptr = "XHCI root HUB"; 3094 break; 3095 3096 default: 3097 str_ptr = ""; 3098 break; 3099 } 3100 3101 len = usb_make_str_desc( 3102 sc->sc_hub_desc.temp, 3103 sizeof(sc->sc_hub_desc.temp), 3104 str_ptr); 3105 break; 3106 3107 default: 3108 err = USB_ERR_IOERROR; 3109 goto done; 3110 } 3111 break; 3112 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3113 len = 1; 3114 sc->sc_hub_desc.temp[0] = 0; 3115 break; 3116 case C(UR_GET_STATUS, UT_READ_DEVICE): 3117 len = 2; 3118 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3119 break; 3120 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3121 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3122 len = 2; 3123 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3124 break; 3125 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3126 if (value >= XHCI_MAX_DEVICES) { 3127 err = USB_ERR_IOERROR; 3128 goto done; 3129 } 3130 break; 3131 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3132 if (value != 0 && value != 1) { 3133 err = USB_ERR_IOERROR; 3134 goto done; 3135 } 3136 sc->sc_conf = value; 3137 break; 3138 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3139 break; 3140 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3141 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3142 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3143 err = USB_ERR_IOERROR; 3144 goto done; 3145 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3146 break; 3147 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3148 break; 3149 /* Hub requests */ 3150 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3151 break; 3152 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3153 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3154 3155 if ((index < 1) || 3156 (index > sc->sc_noport)) { 3157 err = USB_ERR_IOERROR; 3158 goto done; 3159 } 3160 port = XHCI_PORTSC(index); 3161 3162 v = XREAD4(sc, oper, port); 3163 i = XHCI_PS_PLS_GET(v); 3164 v &= ~XHCI_PS_CLEAR; 3165 3166 switch (value) { 3167 case UHF_C_BH_PORT_RESET: 3168 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3169 break; 3170 case UHF_C_PORT_CONFIG_ERROR: 3171 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3172 break; 3173 case UHF_C_PORT_SUSPEND: 3174 case UHF_C_PORT_LINK_STATE: 3175 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3176 break; 3177 case UHF_C_PORT_CONNECTION: 3178 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3179 break; 3180 case UHF_C_PORT_ENABLE: 3181 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3182 break; 3183 case UHF_C_PORT_OVER_CURRENT: 3184 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3185 break; 3186 case UHF_C_PORT_RESET: 3187 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3188 break; 3189 case UHF_PORT_ENABLE: 3190 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3191 break; 3192 case UHF_PORT_POWER: 3193 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3194 break; 3195 case UHF_PORT_INDICATOR: 3196 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3197 break; 3198 case UHF_PORT_SUSPEND: 3199 3200 /* U3 -> U15 */ 3201 if (i == 3) { 3202 XWRITE4(sc, oper, port, v | 3203 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3204 } 3205 3206 /* wait 20ms for resume sequence to complete */ 3207 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3208 3209 /* U0 */ 3210 XWRITE4(sc, oper, port, v | 3211 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3212 break; 3213 default: 3214 err = USB_ERR_IOERROR; 3215 goto done; 3216 } 3217 break; 3218 3219 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3220 if ((value & 0xff) != 0) { 3221 err = USB_ERR_IOERROR; 3222 goto done; 3223 } 3224 3225 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3226 3227 sc->sc_hub_desc.hubd = xhci_hubd; 3228 3229 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3230 3231 if (XHCI_HCS0_PPC(v)) 3232 i = UHD_PWR_INDIVIDUAL; 3233 else 3234 i = UHD_PWR_GANGED; 3235 3236 if (XHCI_HCS0_PIND(v)) 3237 i |= UHD_PORT_IND; 3238 3239 i |= UHD_OC_INDIVIDUAL; 3240 3241 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3242 3243 /* see XHCI section 5.4.9: */ 3244 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3245 3246 for (j = 1; j <= sc->sc_noport; j++) { 3247 3248 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3249 if (v & XHCI_PS_DR) { 3250 sc->sc_hub_desc.hubd. 3251 DeviceRemovable[j / 8] |= 1U << (j % 8); 3252 } 3253 } 3254 len = sc->sc_hub_desc.hubd.bLength; 3255 break; 3256 3257 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3258 len = 16; 3259 memset(sc->sc_hub_desc.temp, 0, 16); 3260 break; 3261 3262 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3263 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3264 3265 if ((index < 1) || 3266 (index > sc->sc_noport)) { 3267 err = USB_ERR_IOERROR; 3268 goto done; 3269 } 3270 3271 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3272 3273 DPRINTFN(9, "port status=0x%08x\n", v); 3274 3275 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3276 3277 switch (XHCI_PS_SPEED_GET(v)) { 3278 case 3: 3279 i |= UPS_HIGH_SPEED; 3280 break; 3281 case 2: 3282 i |= UPS_LOW_SPEED; 3283 break; 3284 case 1: 3285 /* FULL speed */ 3286 break; 3287 default: 3288 i |= UPS_OTHER_SPEED; 3289 break; 3290 } 3291 3292 if (v & XHCI_PS_CCS) 3293 i |= UPS_CURRENT_CONNECT_STATUS; 3294 if (v & XHCI_PS_PED) 3295 i |= UPS_PORT_ENABLED; 3296 if (v & XHCI_PS_OCA) 3297 i |= UPS_OVERCURRENT_INDICATOR; 3298 if (v & XHCI_PS_PR) 3299 i |= UPS_RESET; 3300 if (v & XHCI_PS_PP) { 3301 /* 3302 * The USB 3.0 RH is using the 3303 * USB 2.0's power bit 3304 */ 3305 i |= UPS_PORT_POWER; 3306 } 3307 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3308 3309 i = 0; 3310 if (v & XHCI_PS_CSC) 3311 i |= UPS_C_CONNECT_STATUS; 3312 if (v & XHCI_PS_PEC) 3313 i |= UPS_C_PORT_ENABLED; 3314 if (v & XHCI_PS_OCC) 3315 i |= UPS_C_OVERCURRENT_INDICATOR; 3316 if (v & XHCI_PS_WRC) 3317 i |= UPS_C_BH_PORT_RESET; 3318 if (v & XHCI_PS_PRC) 3319 i |= UPS_C_PORT_RESET; 3320 if (v & XHCI_PS_PLC) 3321 i |= UPS_C_PORT_LINK_STATE; 3322 if (v & XHCI_PS_CEC) 3323 i |= UPS_C_PORT_CONFIG_ERROR; 3324 3325 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3326 len = sizeof(sc->sc_hub_desc.ps); 3327 break; 3328 3329 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3330 err = USB_ERR_IOERROR; 3331 goto done; 3332 3333 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3334 break; 3335 3336 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3337 3338 i = index >> 8; 3339 index &= 0x00FF; 3340 3341 if ((index < 1) || 3342 (index > sc->sc_noport)) { 3343 err = USB_ERR_IOERROR; 3344 goto done; 3345 } 3346 3347 port = XHCI_PORTSC(index); 3348 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3349 3350 switch (value) { 3351 case UHF_PORT_U1_TIMEOUT: 3352 if (XHCI_PS_SPEED_GET(v) != 4) { 3353 err = USB_ERR_IOERROR; 3354 goto done; 3355 } 3356 port = XHCI_PORTPMSC(index); 3357 v = XREAD4(sc, oper, port); 3358 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3359 v |= XHCI_PM3_U1TO_SET(i); 3360 XWRITE4(sc, oper, port, v); 3361 break; 3362 case UHF_PORT_U2_TIMEOUT: 3363 if (XHCI_PS_SPEED_GET(v) != 4) { 3364 err = USB_ERR_IOERROR; 3365 goto done; 3366 } 3367 port = XHCI_PORTPMSC(index); 3368 v = XREAD4(sc, oper, port); 3369 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3370 v |= XHCI_PM3_U2TO_SET(i); 3371 XWRITE4(sc, oper, port, v); 3372 break; 3373 case UHF_BH_PORT_RESET: 3374 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3375 break; 3376 case UHF_PORT_LINK_STATE: 3377 XWRITE4(sc, oper, port, v | 3378 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3379 /* 4ms settle time */ 3380 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3381 break; 3382 case UHF_PORT_ENABLE: 3383 DPRINTFN(3, "set port enable %d\n", index); 3384 break; 3385 case UHF_PORT_SUSPEND: 3386 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3387 j = XHCI_PS_SPEED_GET(v); 3388 if ((j < 1) || (j > 3)) { 3389 /* non-supported speed */ 3390 err = USB_ERR_IOERROR; 3391 goto done; 3392 } 3393 XWRITE4(sc, oper, port, v | 3394 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3395 break; 3396 case UHF_PORT_RESET: 3397 DPRINTFN(6, "reset port %d\n", index); 3398 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3399 break; 3400 case UHF_PORT_POWER: 3401 DPRINTFN(3, "set port power %d\n", index); 3402 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3403 break; 3404 case UHF_PORT_TEST: 3405 DPRINTFN(3, "set port test %d\n", index); 3406 break; 3407 case UHF_PORT_INDICATOR: 3408 DPRINTFN(3, "set port indicator %d\n", index); 3409 3410 v &= ~XHCI_PS_PIC_SET(3); 3411 v |= XHCI_PS_PIC_SET(1); 3412 3413 XWRITE4(sc, oper, port, v); 3414 break; 3415 default: 3416 err = USB_ERR_IOERROR; 3417 goto done; 3418 } 3419 break; 3420 3421 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3422 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3423 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3424 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3425 break; 3426 default: 3427 err = USB_ERR_IOERROR; 3428 goto done; 3429 } 3430 done: 3431 *plength = len; 3432 *pptr = ptr; 3433 return (err); 3434 } 3435 3436 static void 3437 xhci_xfer_setup(struct usb_setup_params *parm) 3438 { 3439 struct usb_page_search page_info; 3440 struct usb_page_cache *pc; 3441 struct xhci_softc *sc; 3442 struct usb_xfer *xfer; 3443 void *last_obj; 3444 uint32_t ntd; 3445 uint32_t n; 3446 3447 sc = XHCI_BUS2SC(parm->udev->bus); 3448 xfer = parm->curr_xfer; 3449 3450 /* 3451 * The proof for the "ntd" formula is illustrated like this: 3452 * 3453 * +------------------------------------+ 3454 * | | 3455 * | |remainder -> | 3456 * | +-----+---+ | 3457 * | | xxx | x | frm 0 | 3458 * | +-----+---++ | 3459 * | | xxx | xx | frm 1 | 3460 * | +-----+----+ | 3461 * | ... | 3462 * +------------------------------------+ 3463 * 3464 * "xxx" means a completely full USB transfer descriptor 3465 * 3466 * "x" and "xx" means a short USB packet 3467 * 3468 * For the remainder of an USB transfer modulo 3469 * "max_data_length" we need two USB transfer descriptors. 3470 * One to transfer the remaining data and one to finalise with 3471 * a zero length packet in case the "force_short_xfer" flag is 3472 * set. We only need two USB transfer descriptors in the case 3473 * where the transfer length of the first one is a factor of 3474 * "max_frame_size". The rest of the needed USB transfer 3475 * descriptors is given by the buffer size divided by the 3476 * maximum data payload. 3477 */ 3478 parm->hc_max_packet_size = 0x400; 3479 parm->hc_max_packet_count = 16 * 3; 3480 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3481 3482 xfer->flags_int.bdma_enable = 1; 3483 3484 usbd_transfer_setup_sub(parm); 3485 3486 if (xfer->flags_int.isochronous_xfr) { 3487 ntd = ((1 * xfer->nframes) 3488 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3489 } else if (xfer->flags_int.control_xfr) { 3490 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3491 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3492 } else { 3493 ntd = ((2 * xfer->nframes) 3494 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3495 } 3496 3497 alloc_dma_set: 3498 3499 if (parm->err) 3500 return; 3501 3502 /* 3503 * Allocate queue heads and transfer descriptors 3504 */ 3505 last_obj = NULL; 3506 3507 if (usbd_transfer_setup_sub_malloc( 3508 parm, &pc, sizeof(struct xhci_td), 3509 XHCI_TD_ALIGN, ntd)) { 3510 parm->err = USB_ERR_NOMEM; 3511 return; 3512 } 3513 if (parm->buf) { 3514 for (n = 0; n != ntd; n++) { 3515 struct xhci_td *td; 3516 3517 usbd_get_page(pc + n, 0, &page_info); 3518 3519 td = page_info.buffer; 3520 3521 /* init TD */ 3522 td->td_self = page_info.physaddr; 3523 td->obj_next = last_obj; 3524 td->page_cache = pc + n; 3525 3526 last_obj = td; 3527 3528 usb_pc_cpu_flush(pc + n); 3529 } 3530 } 3531 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3532 3533 if (!xfer->flags_int.curr_dma_set) { 3534 xfer->flags_int.curr_dma_set = 1; 3535 goto alloc_dma_set; 3536 } 3537 } 3538 3539 static usb_error_t 3540 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3541 { 3542 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3543 struct usb_page_search buf_inp; 3544 struct usb_device *udev; 3545 struct xhci_endpoint_ext *pepext; 3546 struct usb_endpoint_descriptor *edesc; 3547 struct usb_page_cache *pcinp; 3548 usb_error_t err; 3549 usb_stream_t stream_id; 3550 uint8_t index; 3551 uint8_t epno; 3552 3553 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3554 xfer->endpoint->edesc); 3555 3556 udev = xfer->xroot->udev; 3557 index = udev->controller_slot_id; 3558 3559 pcinp = &sc->sc_hw.devs[index].input_pc; 3560 3561 usbd_get_page(pcinp, 0, &buf_inp); 3562 3563 edesc = xfer->endpoint->edesc; 3564 3565 epno = edesc->bEndpointAddress; 3566 stream_id = xfer->stream_id; 3567 3568 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3569 epno |= UE_DIR_IN; 3570 3571 epno = XHCI_EPNO2EPID(epno); 3572 3573 if (epno == 0) 3574 return (USB_ERR_NO_PIPE); /* invalid */ 3575 3576 XHCI_CMD_LOCK(sc); 3577 3578 /* configure endpoint */ 3579 3580 err = xhci_configure_endpoint_by_xfer(xfer); 3581 3582 if (err != 0) { 3583 XHCI_CMD_UNLOCK(sc); 3584 return (err); 3585 } 3586 3587 /* 3588 * Get the endpoint into the stopped state according to the 3589 * endpoint context state diagram in the XHCI specification: 3590 */ 3591 3592 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3593 3594 if (err != 0) 3595 DPRINTF("Could not stop endpoint %u\n", epno); 3596 3597 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3598 3599 if (err != 0) 3600 DPRINTF("Could not reset endpoint %u\n", epno); 3601 3602 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3603 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3604 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3605 stream_id, epno, index); 3606 3607 if (err != 0) 3608 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3609 3610 /* 3611 * Get the endpoint into the running state according to the 3612 * endpoint context state diagram in the XHCI specification: 3613 */ 3614 3615 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3616 3617 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3618 3619 if (err != 0) 3620 DPRINTF("Could not configure endpoint %u\n", epno); 3621 3622 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3623 3624 if (err != 0) 3625 DPRINTF("Could not configure endpoint %u\n", epno); 3626 3627 XHCI_CMD_UNLOCK(sc); 3628 3629 return (0); 3630 } 3631 3632 static void 3633 xhci_xfer_unsetup(struct usb_xfer *xfer) 3634 { 3635 return; 3636 } 3637 3638 static void 3639 xhci_start_dma_delay(struct usb_xfer *xfer) 3640 { 3641 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3642 3643 /* put transfer on interrupt queue (again) */ 3644 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3645 3646 (void)usb_proc_msignal(&sc->sc_config_proc, 3647 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3648 } 3649 3650 static void 3651 xhci_configure_msg(struct usb_proc_msg *pm) 3652 { 3653 struct xhci_softc *sc; 3654 struct xhci_endpoint_ext *pepext; 3655 struct usb_xfer *xfer; 3656 3657 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3658 3659 restart: 3660 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3661 3662 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3663 xfer->endpoint->edesc); 3664 3665 if ((pepext->trb_halted != 0) || 3666 (pepext->trb_running == 0)) { 3667 3668 uint8_t i; 3669 3670 /* clear halted and running */ 3671 pepext->trb_halted = 0; 3672 pepext->trb_running = 0; 3673 3674 /* nuke remaining buffered transfers */ 3675 3676 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 3677 /* 3678 * NOTE: We need to use the timeout 3679 * error code here else existing 3680 * isochronous clients can get 3681 * confused: 3682 */ 3683 if (pepext->xfer[i] != NULL) { 3684 xhci_device_done(pepext->xfer[i], 3685 USB_ERR_TIMEOUT); 3686 } 3687 } 3688 3689 /* 3690 * NOTE: The USB transfer cannot vanish in 3691 * this state! 3692 */ 3693 3694 USB_BUS_UNLOCK(&sc->sc_bus); 3695 3696 xhci_configure_reset_endpoint(xfer); 3697 3698 USB_BUS_LOCK(&sc->sc_bus); 3699 3700 /* check if halted is still cleared */ 3701 if (pepext->trb_halted == 0) { 3702 pepext->trb_running = 1; 3703 memset(pepext->trb_index, 0, 3704 sizeof(pepext->trb_index)); 3705 } 3706 goto restart; 3707 } 3708 3709 if (xfer->flags_int.did_dma_delay) { 3710 3711 /* remove transfer from interrupt queue (again) */ 3712 usbd_transfer_dequeue(xfer); 3713 3714 /* we are finally done */ 3715 usb_dma_delay_done_cb(xfer); 3716 3717 /* queue changed - restart */ 3718 goto restart; 3719 } 3720 } 3721 3722 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3723 3724 /* try to insert xfer on HW queue */ 3725 xhci_transfer_insert(xfer); 3726 3727 /* try to multi buffer */ 3728 xhci_device_generic_multi_enter(xfer->endpoint, 3729 xfer->stream_id, NULL); 3730 } 3731 } 3732 3733 static void 3734 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3735 struct usb_endpoint *ep) 3736 { 3737 struct xhci_endpoint_ext *pepext; 3738 3739 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3740 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3741 3742 if (udev->parent_hub == NULL) { 3743 /* root HUB has special endpoint handling */ 3744 return; 3745 } 3746 3747 ep->methods = &xhci_device_generic_methods; 3748 3749 pepext = xhci_get_endpoint_ext(udev, edesc); 3750 3751 USB_BUS_LOCK(udev->bus); 3752 pepext->trb_halted = 1; 3753 pepext->trb_running = 0; 3754 USB_BUS_UNLOCK(udev->bus); 3755 } 3756 3757 static void 3758 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3759 { 3760 3761 } 3762 3763 static void 3764 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3765 { 3766 struct xhci_endpoint_ext *pepext; 3767 3768 DPRINTF("\n"); 3769 3770 if (udev->flags.usb_mode != USB_MODE_HOST) { 3771 /* not supported */ 3772 return; 3773 } 3774 if (udev->parent_hub == NULL) { 3775 /* root HUB has special endpoint handling */ 3776 return; 3777 } 3778 3779 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3780 3781 USB_BUS_LOCK(udev->bus); 3782 pepext->trb_halted = 1; 3783 pepext->trb_running = 0; 3784 USB_BUS_UNLOCK(udev->bus); 3785 } 3786 3787 static usb_error_t 3788 xhci_device_init(struct usb_device *udev) 3789 { 3790 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3791 usb_error_t err; 3792 uint8_t temp; 3793 3794 /* no init for root HUB */ 3795 if (udev->parent_hub == NULL) 3796 return (0); 3797 3798 XHCI_CMD_LOCK(sc); 3799 3800 /* set invalid default */ 3801 3802 udev->controller_slot_id = sc->sc_noslot + 1; 3803 3804 /* try to get a new slot ID from the XHCI */ 3805 3806 err = xhci_cmd_enable_slot(sc, &temp); 3807 3808 if (err) { 3809 XHCI_CMD_UNLOCK(sc); 3810 return (err); 3811 } 3812 3813 if (temp > sc->sc_noslot) { 3814 XHCI_CMD_UNLOCK(sc); 3815 return (USB_ERR_BAD_ADDRESS); 3816 } 3817 3818 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 3819 DPRINTF("slot %u already allocated.\n", temp); 3820 XHCI_CMD_UNLOCK(sc); 3821 return (USB_ERR_BAD_ADDRESS); 3822 } 3823 3824 /* store slot ID for later reference */ 3825 3826 udev->controller_slot_id = temp; 3827 3828 /* reset data structure */ 3829 3830 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 3831 3832 /* set mark slot allocated */ 3833 3834 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 3835 3836 err = xhci_alloc_device_ext(udev); 3837 3838 XHCI_CMD_UNLOCK(sc); 3839 3840 /* get device into default state */ 3841 3842 if (err == 0) 3843 err = xhci_set_address(udev, NULL, 0); 3844 3845 return (err); 3846 } 3847 3848 static void 3849 xhci_device_uninit(struct usb_device *udev) 3850 { 3851 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3852 uint8_t index; 3853 3854 /* no init for root HUB */ 3855 if (udev->parent_hub == NULL) 3856 return; 3857 3858 XHCI_CMD_LOCK(sc); 3859 3860 index = udev->controller_slot_id; 3861 3862 if (index <= sc->sc_noslot) { 3863 xhci_cmd_disable_slot(sc, index); 3864 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 3865 3866 /* free device extension */ 3867 xhci_free_device_ext(udev); 3868 } 3869 3870 XHCI_CMD_UNLOCK(sc); 3871 } 3872 3873 static void 3874 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3875 { 3876 /* 3877 * Wait until the hardware has finished any possible use of 3878 * the transfer descriptor(s) 3879 */ 3880 *pus = 2048; /* microseconds */ 3881 } 3882 3883 static void 3884 xhci_device_resume(struct usb_device *udev) 3885 { 3886 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3887 uint8_t index; 3888 uint8_t n; 3889 uint8_t p; 3890 3891 DPRINTF("\n"); 3892 3893 /* check for root HUB */ 3894 if (udev->parent_hub == NULL) 3895 return; 3896 3897 index = udev->controller_slot_id; 3898 3899 XHCI_CMD_LOCK(sc); 3900 3901 /* blindly resume all endpoints */ 3902 3903 USB_BUS_LOCK(udev->bus); 3904 3905 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3906 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 3907 XWRITE4(sc, door, XHCI_DOORBELL(index), 3908 n | XHCI_DB_SID_SET(p)); 3909 } 3910 } 3911 3912 USB_BUS_UNLOCK(udev->bus); 3913 3914 XHCI_CMD_UNLOCK(sc); 3915 } 3916 3917 static void 3918 xhci_device_suspend(struct usb_device *udev) 3919 { 3920 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3921 uint8_t index; 3922 uint8_t n; 3923 usb_error_t err; 3924 3925 DPRINTF("\n"); 3926 3927 /* check for root HUB */ 3928 if (udev->parent_hub == NULL) 3929 return; 3930 3931 index = udev->controller_slot_id; 3932 3933 XHCI_CMD_LOCK(sc); 3934 3935 /* blindly suspend all endpoints */ 3936 3937 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3938 err = xhci_cmd_stop_ep(sc, 1, n, index); 3939 if (err != 0) { 3940 DPRINTF("Failed to suspend endpoint " 3941 "%u on slot %u (ignored).\n", n, index); 3942 } 3943 } 3944 3945 XHCI_CMD_UNLOCK(sc); 3946 } 3947 3948 static void 3949 xhci_set_hw_power(struct usb_bus *bus) 3950 { 3951 DPRINTF("\n"); 3952 } 3953 3954 static void 3955 xhci_device_state_change(struct usb_device *udev) 3956 { 3957 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3958 struct usb_page_search buf_inp; 3959 usb_error_t err; 3960 uint8_t index; 3961 3962 /* check for root HUB */ 3963 if (udev->parent_hub == NULL) 3964 return; 3965 3966 index = udev->controller_slot_id; 3967 3968 DPRINTF("\n"); 3969 3970 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 3971 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 3972 &sc->sc_hw.devs[index].tt); 3973 if (err != 0) 3974 sc->sc_hw.devs[index].nports = 0; 3975 } 3976 3977 XHCI_CMD_LOCK(sc); 3978 3979 switch (usb_get_device_state(udev)) { 3980 case USB_STATE_POWERED: 3981 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 3982 break; 3983 3984 /* set default state */ 3985 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 3986 3987 /* reset number of contexts */ 3988 sc->sc_hw.devs[index].context_num = 0; 3989 3990 err = xhci_cmd_reset_dev(sc, index); 3991 3992 if (err != 0) { 3993 DPRINTF("Device reset failed " 3994 "for slot %u.\n", index); 3995 } 3996 break; 3997 3998 case USB_STATE_ADDRESSED: 3999 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4000 break; 4001 4002 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4003 4004 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4005 4006 if (err) { 4007 DPRINTF("Failed to deconfigure " 4008 "slot %u.\n", index); 4009 } 4010 break; 4011 4012 case USB_STATE_CONFIGURED: 4013 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4014 break; 4015 4016 /* set configured state */ 4017 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4018 4019 /* reset number of contexts */ 4020 sc->sc_hw.devs[index].context_num = 0; 4021 4022 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4023 4024 xhci_configure_mask(udev, 3, 0); 4025 4026 err = xhci_configure_device(udev); 4027 if (err != 0) { 4028 DPRINTF("Could not configure device " 4029 "at slot %u.\n", index); 4030 } 4031 4032 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4033 if (err != 0) { 4034 DPRINTF("Could not evaluate device " 4035 "context at slot %u.\n", index); 4036 } 4037 break; 4038 4039 default: 4040 break; 4041 } 4042 XHCI_CMD_UNLOCK(sc); 4043 } 4044 4045 static usb_error_t 4046 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4047 uint8_t ep_mode) 4048 { 4049 switch (ep_mode) { 4050 case USB_EP_MODE_DEFAULT: 4051 return (0); 4052 case USB_EP_MODE_STREAMS: 4053 if ((ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4054 udev->speed != USB_SPEED_SUPER) 4055 return (USB_ERR_INVAL); 4056 return (0); 4057 default: 4058 return (USB_ERR_INVAL); 4059 } 4060 } 4061 4062 struct usb_bus_methods xhci_bus_methods = { 4063 .endpoint_init = xhci_ep_init, 4064 .endpoint_uninit = xhci_ep_uninit, 4065 .xfer_setup = xhci_xfer_setup, 4066 .xfer_unsetup = xhci_xfer_unsetup, 4067 .get_dma_delay = xhci_get_dma_delay, 4068 .device_init = xhci_device_init, 4069 .device_uninit = xhci_device_uninit, 4070 .device_resume = xhci_device_resume, 4071 .device_suspend = xhci_device_suspend, 4072 .set_hw_power = xhci_set_hw_power, 4073 .roothub_exec = xhci_roothub_exec, 4074 .xfer_poll = xhci_do_poll, 4075 .start_dma_delay = xhci_start_dma_delay, 4076 .set_address = xhci_set_address, 4077 .clear_stall = xhci_ep_clear_stall, 4078 .device_state_change = xhci_device_state_change, 4079 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4080 .set_endpoint_mode = xhci_set_endpoint_mode, 4081 }; 4082