1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36 /* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43 #ifdef USB_GLOBAL_INCLUDE_FILE 44 #include USB_GLOBAL_INCLUDE_FILE 45 #else 46 #include <sys/stdint.h> 47 #include <sys/stddef.h> 48 #include <sys/param.h> 49 #include <sys/queue.h> 50 #include <sys/types.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/bus.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/condvar.h> 58 #include <sys/sysctl.h> 59 #include <sys/sx.h> 60 #include <sys/unistd.h> 61 #include <sys/callout.h> 62 #include <sys/malloc.h> 63 #include <sys/priv.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 68 #define USB_DEBUG_VAR xhcidebug 69 70 #include <dev/usb/usb_core.h> 71 #include <dev/usb/usb_debug.h> 72 #include <dev/usb/usb_busdma.h> 73 #include <dev/usb/usb_process.h> 74 #include <dev/usb/usb_transfer.h> 75 #include <dev/usb/usb_device.h> 76 #include <dev/usb/usb_hub.h> 77 #include <dev/usb/usb_util.h> 78 79 #include <dev/usb/usb_controller.h> 80 #include <dev/usb/usb_bus.h> 81 #endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83 #include <dev/usb/controller/xhci.h> 84 #include <dev/usb/controller/xhcireg.h> 85 86 #define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 92 static int xhcistreams; 93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN, 94 &xhcistreams, 0, "Set to enable streams mode support"); 95 96 #ifdef USB_DEBUG 97 static int xhcidebug; 98 static int xhciroute; 99 static int xhcipolling; 100 101 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN, 102 &xhcidebug, 0, "Debug level"); 103 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN, 104 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN, 106 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller"); 107 #else 108 #define xhciroute 0 109 #endif 110 111 #define XHCI_INTR_ENDPT 1 112 113 struct xhci_std_temp { 114 struct xhci_softc *sc; 115 struct usb_page_cache *pc; 116 struct xhci_td *td; 117 struct xhci_td *td_next; 118 uint32_t len; 119 uint32_t offset; 120 uint32_t max_packet_size; 121 uint32_t average; 122 uint16_t isoc_delta; 123 uint16_t isoc_frame; 124 uint8_t shortpkt; 125 uint8_t multishort; 126 uint8_t last_frame; 127 uint8_t trb_type; 128 uint8_t direction; 129 uint8_t tbc; 130 uint8_t tlbpc; 131 uint8_t step_td; 132 uint8_t do_isoc_sync; 133 }; 134 135 static void xhci_do_poll(struct usb_bus *); 136 static void xhci_device_done(struct usb_xfer *, usb_error_t); 137 static void xhci_root_intr(struct xhci_softc *); 138 static void xhci_free_device_ext(struct usb_device *); 139 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 140 struct usb_endpoint_descriptor *); 141 static usb_proc_callback_t xhci_configure_msg; 142 static usb_error_t xhci_configure_device(struct usb_device *); 143 static usb_error_t xhci_configure_endpoint(struct usb_device *, 144 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 145 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 146 uint8_t); 147 static usb_error_t xhci_configure_mask(struct usb_device *, 148 uint32_t, uint8_t); 149 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 150 uint64_t, uint8_t); 151 static void xhci_endpoint_doorbell(struct usb_xfer *); 152 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 153 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 154 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 155 #ifdef USB_DEBUG 156 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 157 #endif 158 159 static const struct usb_bus_methods xhci_bus_methods; 160 161 #ifdef USB_DEBUG 162 static void 163 xhci_dump_trb(struct xhci_trb *trb) 164 { 165 DPRINTFN(5, "trb = %p\n", trb); 166 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 167 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 168 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 169 } 170 171 static void 172 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 173 { 174 DPRINTFN(5, "pep = %p\n", pep); 175 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 176 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 177 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 178 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 179 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 180 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 181 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 182 } 183 184 static void 185 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 186 { 187 DPRINTFN(5, "psl = %p\n", psl); 188 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 189 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 190 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 191 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 192 } 193 #endif 194 195 uint8_t 196 xhci_use_polling(void) 197 { 198 #ifdef USB_DEBUG 199 return (xhcipolling != 0); 200 #else 201 return (0); 202 #endif 203 } 204 205 static void 206 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 207 { 208 struct xhci_softc *sc = XHCI_BUS2SC(bus); 209 uint8_t i; 210 211 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 212 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 213 214 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 215 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 216 217 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 218 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 219 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 220 } 221 } 222 223 static void 224 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 225 { 226 if (sc->sc_ctx_is_64_byte) { 227 uint32_t offset; 228 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 229 /* all contexts are initially 32-bytes */ 230 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 231 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 232 } 233 *ptr = htole32(val); 234 } 235 236 static uint32_t 237 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 238 { 239 if (sc->sc_ctx_is_64_byte) { 240 uint32_t offset; 241 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 242 /* all contexts are initially 32-bytes */ 243 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 244 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 245 } 246 return (le32toh(*ptr)); 247 } 248 249 static void 250 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 251 { 252 if (sc->sc_ctx_is_64_byte) { 253 uint32_t offset; 254 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 255 /* all contexts are initially 32-bytes */ 256 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 257 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 258 } 259 *ptr = htole64(val); 260 } 261 262 #ifdef USB_DEBUG 263 static uint64_t 264 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 265 { 266 if (sc->sc_ctx_is_64_byte) { 267 uint32_t offset; 268 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 269 /* all contexts are initially 32-bytes */ 270 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 271 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 272 } 273 return (le64toh(*ptr)); 274 } 275 #endif 276 277 static int 278 xhci_reset_command_queue_locked(struct xhci_softc *sc) 279 { 280 struct usb_page_search buf_res; 281 struct xhci_hw_root *phwr; 282 uint64_t addr; 283 uint32_t temp; 284 285 DPRINTF("\n"); 286 287 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 288 if (temp & XHCI_CRCR_LO_CRR) { 289 DPRINTF("Command ring running\n"); 290 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 291 292 /* 293 * Try to abort the last command as per section 294 * 4.6.1.2 "Aborting a Command" of the XHCI 295 * specification: 296 */ 297 298 /* stop and cancel */ 299 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 300 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 301 302 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 303 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 304 305 /* wait 250ms */ 306 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 307 308 /* check if command ring is still running */ 309 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 310 if (temp & XHCI_CRCR_LO_CRR) { 311 DPRINTF("Comand ring still running\n"); 312 return (USB_ERR_IOERROR); 313 } 314 } 315 316 /* reset command ring */ 317 sc->sc_command_ccs = 1; 318 sc->sc_command_idx = 0; 319 320 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 321 322 /* setup command ring control base address */ 323 addr = buf_res.physaddr; 324 phwr = buf_res.buffer; 325 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 326 327 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 328 329 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 330 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 331 332 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 333 334 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 335 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 336 337 return (0); 338 } 339 340 usb_error_t 341 xhci_start_controller(struct xhci_softc *sc) 342 { 343 struct usb_page_search buf_res; 344 struct xhci_hw_root *phwr; 345 struct xhci_dev_ctx_addr *pdctxa; 346 uint64_t addr; 347 uint32_t temp; 348 uint16_t i; 349 350 DPRINTF("\n"); 351 352 sc->sc_capa_off = 0; 353 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 354 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 355 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 356 357 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 358 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 359 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 360 361 sc->sc_event_ccs = 1; 362 sc->sc_event_idx = 0; 363 sc->sc_command_ccs = 1; 364 sc->sc_command_idx = 0; 365 366 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 367 368 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 369 370 DPRINTF("HCS0 = 0x%08x\n", temp); 371 372 if (XHCI_HCS0_CSZ(temp)) { 373 sc->sc_ctx_is_64_byte = 1; 374 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 375 } else { 376 sc->sc_ctx_is_64_byte = 0; 377 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 378 } 379 380 /* Reset controller */ 381 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 382 383 for (i = 0; i != 100; i++) { 384 usb_pause_mtx(NULL, hz / 100); 385 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 386 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 387 if (!temp) 388 break; 389 } 390 391 if (temp) { 392 device_printf(sc->sc_bus.parent, "Controller " 393 "reset timeout.\n"); 394 return (USB_ERR_IOERROR); 395 } 396 397 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 398 device_printf(sc->sc_bus.parent, "Controller does " 399 "not support 4K page size.\n"); 400 return (USB_ERR_IOERROR); 401 } 402 403 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 404 405 i = XHCI_HCS1_N_PORTS(temp); 406 407 if (i == 0) { 408 device_printf(sc->sc_bus.parent, "Invalid number " 409 "of ports: %u\n", i); 410 return (USB_ERR_IOERROR); 411 } 412 413 sc->sc_noport = i; 414 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 415 416 if (sc->sc_noslot > XHCI_MAX_DEVICES) 417 sc->sc_noslot = XHCI_MAX_DEVICES; 418 419 /* setup number of device slots */ 420 421 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 422 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 423 424 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 425 426 DPRINTF("Max slots: %u\n", sc->sc_noslot); 427 428 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 429 430 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 431 432 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 433 device_printf(sc->sc_bus.parent, "XHCI request " 434 "too many scratchpads\n"); 435 return (USB_ERR_NOMEM); 436 } 437 438 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 439 440 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 441 442 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 443 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 444 445 temp = XREAD4(sc, oper, XHCI_USBSTS); 446 447 /* clear interrupts */ 448 XWRITE4(sc, oper, XHCI_USBSTS, temp); 449 /* disable all device notifications */ 450 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 451 452 /* setup device context base address */ 453 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 454 pdctxa = buf_res.buffer; 455 memset(pdctxa, 0, sizeof(*pdctxa)); 456 457 addr = buf_res.physaddr; 458 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 459 460 /* slot 0 points to the table of scratchpad pointers */ 461 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 462 463 for (i = 0; i != sc->sc_noscratch; i++) { 464 struct usb_page_search buf_scp; 465 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 466 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 467 } 468 469 addr = buf_res.physaddr; 470 471 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 472 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 473 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 474 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 475 476 /* Setup event table size */ 477 478 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 479 480 DPRINTF("HCS2=0x%08x\n", temp); 481 482 temp = XHCI_HCS2_ERST_MAX(temp); 483 temp = 1U << temp; 484 if (temp > XHCI_MAX_RSEG) 485 temp = XHCI_MAX_RSEG; 486 487 sc->sc_erst_max = temp; 488 489 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 490 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 491 492 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 493 494 /* Check if we should use the default IMOD value */ 495 if (sc->sc_imod_default == 0) 496 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 497 498 /* Setup interrupt rate */ 499 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 500 501 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 502 503 phwr = buf_res.buffer; 504 addr = buf_res.physaddr; 505 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 506 507 /* reset hardware root structure */ 508 memset(phwr, 0, sizeof(*phwr)); 509 510 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 511 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 512 513 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 514 515 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 516 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 517 518 addr = (uint64_t)buf_res.physaddr; 519 520 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 521 522 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 523 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 524 525 /* Setup interrupter registers */ 526 527 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 528 temp |= XHCI_IMAN_INTR_ENA; 529 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 530 531 /* setup command ring control base address */ 532 addr = buf_res.physaddr; 533 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 534 535 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 536 537 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 538 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 539 540 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 541 542 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 543 544 /* Go! */ 545 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 546 XHCI_CMD_INTE | XHCI_CMD_HSEE); 547 548 for (i = 0; i != 100; i++) { 549 usb_pause_mtx(NULL, hz / 100); 550 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 551 if (!temp) 552 break; 553 } 554 if (temp) { 555 XWRITE4(sc, oper, XHCI_USBCMD, 0); 556 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 557 return (USB_ERR_IOERROR); 558 } 559 560 /* catch any lost interrupts */ 561 xhci_do_poll(&sc->sc_bus); 562 563 if (sc->sc_port_route != NULL) { 564 /* Route all ports to the XHCI by default */ 565 sc->sc_port_route(sc->sc_bus.parent, 566 ~xhciroute, xhciroute); 567 } 568 return (0); 569 } 570 571 usb_error_t 572 xhci_halt_controller(struct xhci_softc *sc) 573 { 574 uint32_t temp; 575 uint16_t i; 576 577 DPRINTF("\n"); 578 579 sc->sc_capa_off = 0; 580 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 581 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 582 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 583 584 /* Halt controller */ 585 XWRITE4(sc, oper, XHCI_USBCMD, 0); 586 587 for (i = 0; i != 100; i++) { 588 usb_pause_mtx(NULL, hz / 100); 589 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 590 if (temp) 591 break; 592 } 593 594 if (!temp) { 595 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 596 return (USB_ERR_IOERROR); 597 } 598 return (0); 599 } 600 601 usb_error_t 602 xhci_init(struct xhci_softc *sc, device_t self) 603 { 604 /* initialise some bus fields */ 605 sc->sc_bus.parent = self; 606 607 /* set the bus revision */ 608 sc->sc_bus.usbrev = USB_REV_3_0; 609 610 /* set up the bus struct */ 611 sc->sc_bus.methods = &xhci_bus_methods; 612 613 /* setup devices array */ 614 sc->sc_bus.devices = sc->sc_devices; 615 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 616 617 /* setup command queue mutex and condition varible */ 618 cv_init(&sc->sc_cmd_cv, "CMDQ"); 619 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 620 621 /* get all DMA memory */ 622 if (usb_bus_mem_alloc_all(&sc->sc_bus, 623 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 624 return (ENOMEM); 625 } 626 627 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 628 sc->sc_config_msg[0].bus = &sc->sc_bus; 629 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 630 sc->sc_config_msg[1].bus = &sc->sc_bus; 631 632 return (0); 633 } 634 635 void 636 xhci_uninit(struct xhci_softc *sc) 637 { 638 /* 639 * NOTE: At this point the control transfer process is gone 640 * and "xhci_configure_msg" is no longer called. Consequently 641 * waiting for the configuration messages to complete is not 642 * needed. 643 */ 644 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 645 646 cv_destroy(&sc->sc_cmd_cv); 647 sx_destroy(&sc->sc_cmd_sx); 648 } 649 650 static void 651 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 652 { 653 struct xhci_softc *sc = XHCI_BUS2SC(bus); 654 655 switch (state) { 656 case USB_HW_POWER_SUSPEND: 657 DPRINTF("Stopping the XHCI\n"); 658 xhci_halt_controller(sc); 659 break; 660 case USB_HW_POWER_SHUTDOWN: 661 DPRINTF("Stopping the XHCI\n"); 662 xhci_halt_controller(sc); 663 break; 664 case USB_HW_POWER_RESUME: 665 DPRINTF("Starting the XHCI\n"); 666 xhci_start_controller(sc); 667 break; 668 default: 669 break; 670 } 671 } 672 673 static usb_error_t 674 xhci_generic_done_sub(struct usb_xfer *xfer) 675 { 676 struct xhci_td *td; 677 struct xhci_td *td_alt_next; 678 uint32_t len; 679 uint8_t status; 680 681 td = xfer->td_transfer_cache; 682 td_alt_next = td->alt_next; 683 684 if (xfer->aframes != xfer->nframes) 685 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 686 687 while (1) { 688 689 usb_pc_cpu_invalidate(td->page_cache); 690 691 status = td->status; 692 len = td->remainder; 693 694 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 695 xfer, (unsigned int)xfer->aframes, 696 (unsigned int)xfer->nframes, 697 (unsigned int)len, (unsigned int)td->len, 698 (unsigned int)status); 699 700 /* 701 * Verify the status length and 702 * add the length to "frlengths[]": 703 */ 704 if (len > td->len) { 705 /* should not happen */ 706 DPRINTF("Invalid status length, " 707 "0x%04x/0x%04x bytes\n", len, td->len); 708 status = XHCI_TRB_ERROR_LENGTH; 709 } else if (xfer->aframes != xfer->nframes) { 710 xfer->frlengths[xfer->aframes] += td->len - len; 711 } 712 /* Check for last transfer */ 713 if (((void *)td) == xfer->td_transfer_last) { 714 td = NULL; 715 break; 716 } 717 /* Check for transfer error */ 718 if (status != XHCI_TRB_ERROR_SHORT_PKT && 719 status != XHCI_TRB_ERROR_SUCCESS) { 720 /* the transfer is finished */ 721 td = NULL; 722 break; 723 } 724 /* Check for short transfer */ 725 if (len > 0) { 726 if (xfer->flags_int.short_frames_ok || 727 xfer->flags_int.isochronous_xfr || 728 xfer->flags_int.control_xfr) { 729 /* follow alt next */ 730 td = td->alt_next; 731 } else { 732 /* the transfer is finished */ 733 td = NULL; 734 } 735 break; 736 } 737 td = td->obj_next; 738 739 if (td->alt_next != td_alt_next) { 740 /* this USB frame is complete */ 741 break; 742 } 743 } 744 745 /* update transfer cache */ 746 747 xfer->td_transfer_cache = td; 748 749 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 750 (status != XHCI_TRB_ERROR_SHORT_PKT && 751 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 752 USB_ERR_NORMAL_COMPLETION); 753 } 754 755 static void 756 xhci_generic_done(struct usb_xfer *xfer) 757 { 758 usb_error_t err = 0; 759 760 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 761 xfer, xfer->endpoint); 762 763 /* reset scanner */ 764 765 xfer->td_transfer_cache = xfer->td_transfer_first; 766 767 if (xfer->flags_int.control_xfr) { 768 769 if (xfer->flags_int.control_hdr) 770 err = xhci_generic_done_sub(xfer); 771 772 xfer->aframes = 1; 773 774 if (xfer->td_transfer_cache == NULL) 775 goto done; 776 } 777 778 while (xfer->aframes != xfer->nframes) { 779 780 err = xhci_generic_done_sub(xfer); 781 xfer->aframes++; 782 783 if (xfer->td_transfer_cache == NULL) 784 goto done; 785 } 786 787 if (xfer->flags_int.control_xfr && 788 !xfer->flags_int.control_act) 789 err = xhci_generic_done_sub(xfer); 790 done: 791 /* transfer is complete */ 792 xhci_device_done(xfer, err); 793 } 794 795 static void 796 xhci_activate_transfer(struct usb_xfer *xfer) 797 { 798 struct xhci_td *td; 799 800 td = xfer->td_transfer_cache; 801 802 usb_pc_cpu_invalidate(td->page_cache); 803 804 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 805 806 /* activate the transfer */ 807 808 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 809 usb_pc_cpu_flush(td->page_cache); 810 811 xhci_endpoint_doorbell(xfer); 812 } 813 } 814 815 static void 816 xhci_skip_transfer(struct usb_xfer *xfer) 817 { 818 struct xhci_td *td; 819 struct xhci_td *td_last; 820 821 td = xfer->td_transfer_cache; 822 td_last = xfer->td_transfer_last; 823 824 td = td->alt_next; 825 826 usb_pc_cpu_invalidate(td->page_cache); 827 828 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 829 830 usb_pc_cpu_invalidate(td_last->page_cache); 831 832 /* copy LINK TRB to current waiting location */ 833 834 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 835 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 836 usb_pc_cpu_flush(td->page_cache); 837 838 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 839 usb_pc_cpu_flush(td->page_cache); 840 841 xhci_endpoint_doorbell(xfer); 842 } 843 } 844 845 /*------------------------------------------------------------------------* 846 * xhci_check_transfer 847 *------------------------------------------------------------------------*/ 848 static void 849 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 850 { 851 struct xhci_endpoint_ext *pepext; 852 int64_t offset; 853 uint64_t td_event; 854 uint32_t temp; 855 uint32_t remainder; 856 uint16_t stream_id; 857 uint16_t i; 858 uint8_t status; 859 uint8_t halted; 860 uint8_t epno; 861 uint8_t index; 862 863 /* decode TRB */ 864 td_event = le64toh(trb->qwTrb0); 865 temp = le32toh(trb->dwTrb2); 866 867 remainder = XHCI_TRB_2_REM_GET(temp); 868 status = XHCI_TRB_2_ERROR_GET(temp); 869 stream_id = XHCI_TRB_2_STREAM_GET(temp); 870 871 temp = le32toh(trb->dwTrb3); 872 epno = XHCI_TRB_3_EP_GET(temp); 873 index = XHCI_TRB_3_SLOT_GET(temp); 874 875 /* check if error means halted */ 876 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 877 status != XHCI_TRB_ERROR_SUCCESS); 878 879 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 880 index, epno, stream_id, remainder, status); 881 882 if (index > sc->sc_noslot) { 883 DPRINTF("Invalid slot.\n"); 884 return; 885 } 886 887 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 888 DPRINTF("Invalid endpoint.\n"); 889 return; 890 } 891 892 pepext = &sc->sc_hw.devs[index].endp[epno]; 893 894 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 895 stream_id = 0; 896 DPRINTF("stream_id=0\n"); 897 } else if (stream_id >= XHCI_MAX_STREAMS) { 898 DPRINTF("Invalid stream ID.\n"); 899 return; 900 } 901 902 /* try to find the USB transfer that generated the event */ 903 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 904 struct usb_xfer *xfer; 905 struct xhci_td *td; 906 907 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 908 if (xfer == NULL) 909 continue; 910 911 td = xfer->td_transfer_cache; 912 913 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 914 (long long)td_event, 915 (long long)td->td_self, 916 (long long)td->td_self + sizeof(td->td_trb)); 917 918 /* 919 * NOTE: Some XHCI implementations might not trigger 920 * an event on the last LINK TRB so we need to 921 * consider both the last and second last event 922 * address as conditions for a successful transfer. 923 * 924 * NOTE: We assume that the XHCI will only trigger one 925 * event per chain of TRBs. 926 */ 927 928 offset = td_event - td->td_self; 929 930 if (offset >= 0 && 931 offset < (int64_t)sizeof(td->td_trb)) { 932 933 usb_pc_cpu_invalidate(td->page_cache); 934 935 /* compute rest of remainder, if any */ 936 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 937 temp = le32toh(td->td_trb[i].dwTrb2); 938 remainder += XHCI_TRB_2_BYTES_GET(temp); 939 } 940 941 DPRINTFN(5, "New remainder: %u\n", remainder); 942 943 /* clear isochronous transfer errors */ 944 if (xfer->flags_int.isochronous_xfr) { 945 if (halted) { 946 halted = 0; 947 status = XHCI_TRB_ERROR_SUCCESS; 948 remainder = td->len; 949 } 950 } 951 952 /* "td->remainder" is verified later */ 953 td->remainder = remainder; 954 td->status = status; 955 956 usb_pc_cpu_flush(td->page_cache); 957 958 /* 959 * 1) Last transfer descriptor makes the 960 * transfer done 961 */ 962 if (((void *)td) == xfer->td_transfer_last) { 963 DPRINTF("TD is last\n"); 964 xhci_generic_done(xfer); 965 break; 966 } 967 968 /* 969 * 2) Any kind of error makes the transfer 970 * done 971 */ 972 if (halted) { 973 DPRINTF("TD has I/O error\n"); 974 xhci_generic_done(xfer); 975 break; 976 } 977 978 /* 979 * 3) If there is no alternate next transfer, 980 * a short packet also makes the transfer done 981 */ 982 if (td->remainder > 0) { 983 if (td->alt_next == NULL) { 984 DPRINTF( 985 "short TD has no alternate next\n"); 986 xhci_generic_done(xfer); 987 break; 988 } 989 DPRINTF("TD has short pkt\n"); 990 if (xfer->flags_int.short_frames_ok || 991 xfer->flags_int.isochronous_xfr || 992 xfer->flags_int.control_xfr) { 993 /* follow the alt next */ 994 xfer->td_transfer_cache = td->alt_next; 995 xhci_activate_transfer(xfer); 996 break; 997 } 998 xhci_skip_transfer(xfer); 999 xhci_generic_done(xfer); 1000 break; 1001 } 1002 1003 /* 1004 * 4) Transfer complete - go to next TD 1005 */ 1006 DPRINTF("Following next TD\n"); 1007 xfer->td_transfer_cache = td->obj_next; 1008 xhci_activate_transfer(xfer); 1009 break; /* there should only be one match */ 1010 } 1011 } 1012 } 1013 1014 static int 1015 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1016 { 1017 if (sc->sc_cmd_addr == trb->qwTrb0) { 1018 DPRINTF("Received command event\n"); 1019 sc->sc_cmd_result[0] = trb->dwTrb2; 1020 sc->sc_cmd_result[1] = trb->dwTrb3; 1021 cv_signal(&sc->sc_cmd_cv); 1022 return (1); /* command match */ 1023 } 1024 return (0); 1025 } 1026 1027 static int 1028 xhci_interrupt_poll(struct xhci_softc *sc) 1029 { 1030 struct usb_page_search buf_res; 1031 struct xhci_hw_root *phwr; 1032 uint64_t addr; 1033 uint32_t temp; 1034 int retval = 0; 1035 uint16_t i; 1036 uint8_t event; 1037 uint8_t j; 1038 uint8_t k; 1039 uint8_t t; 1040 1041 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1042 1043 phwr = buf_res.buffer; 1044 1045 /* Receive any events */ 1046 1047 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1048 1049 i = sc->sc_event_idx; 1050 j = sc->sc_event_ccs; 1051 t = 2; 1052 1053 while (1) { 1054 1055 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1056 1057 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1058 1059 if (j != k) 1060 break; 1061 1062 event = XHCI_TRB_3_TYPE_GET(temp); 1063 1064 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1065 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1066 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1067 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1068 1069 switch (event) { 1070 case XHCI_TRB_EVENT_TRANSFER: 1071 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1072 break; 1073 case XHCI_TRB_EVENT_CMD_COMPLETE: 1074 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1075 break; 1076 default: 1077 DPRINTF("Unhandled event = %u\n", event); 1078 break; 1079 } 1080 1081 i++; 1082 1083 if (i == XHCI_MAX_EVENTS) { 1084 i = 0; 1085 j ^= 1; 1086 1087 /* check for timeout */ 1088 if (!--t) 1089 break; 1090 } 1091 } 1092 1093 sc->sc_event_idx = i; 1094 sc->sc_event_ccs = j; 1095 1096 /* 1097 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1098 * latched. That means to activate the register we need to 1099 * write both the low and high double word of the 64-bit 1100 * register. 1101 */ 1102 1103 addr = (uint32_t)buf_res.physaddr; 1104 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1105 1106 /* try to clear busy bit */ 1107 addr |= XHCI_ERDP_LO_BUSY; 1108 1109 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1110 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1111 1112 return (retval); 1113 } 1114 1115 static usb_error_t 1116 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1117 uint16_t timeout_ms) 1118 { 1119 struct usb_page_search buf_res; 1120 struct xhci_hw_root *phwr; 1121 uint64_t addr; 1122 uint32_t temp; 1123 uint8_t i; 1124 uint8_t j; 1125 uint8_t timeout = 0; 1126 int err; 1127 1128 XHCI_CMD_ASSERT_LOCKED(sc); 1129 1130 /* get hardware root structure */ 1131 1132 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1133 1134 phwr = buf_res.buffer; 1135 1136 /* Queue command */ 1137 1138 USB_BUS_LOCK(&sc->sc_bus); 1139 retry: 1140 i = sc->sc_command_idx; 1141 j = sc->sc_command_ccs; 1142 1143 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1144 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1145 (long long)le64toh(trb->qwTrb0), 1146 (long)le32toh(trb->dwTrb2), 1147 (long)le32toh(trb->dwTrb3)); 1148 1149 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1150 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1151 1152 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1153 1154 temp = trb->dwTrb3; 1155 1156 if (j) 1157 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1158 else 1159 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1160 1161 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1162 1163 phwr->hwr_commands[i].dwTrb3 = temp; 1164 1165 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1166 1167 addr = buf_res.physaddr; 1168 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1169 1170 sc->sc_cmd_addr = htole64(addr); 1171 1172 i++; 1173 1174 if (i == (XHCI_MAX_COMMANDS - 1)) { 1175 1176 if (j) { 1177 temp = htole32(XHCI_TRB_3_TC_BIT | 1178 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1179 XHCI_TRB_3_CYCLE_BIT); 1180 } else { 1181 temp = htole32(XHCI_TRB_3_TC_BIT | 1182 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1183 } 1184 1185 phwr->hwr_commands[i].dwTrb3 = temp; 1186 1187 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1188 1189 i = 0; 1190 j ^= 1; 1191 } 1192 1193 sc->sc_command_idx = i; 1194 sc->sc_command_ccs = j; 1195 1196 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1197 1198 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1199 USB_MS_TO_TICKS(timeout_ms)); 1200 1201 /* 1202 * In some error cases event interrupts are not generated. 1203 * Poll one time to see if the command has completed. 1204 */ 1205 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1206 DPRINTF("Command was completed when polling\n"); 1207 err = 0; 1208 } 1209 if (err != 0) { 1210 DPRINTF("Command timeout!\n"); 1211 /* 1212 * After some weeks of continuous operation, it has 1213 * been observed that the ASMedia Technology, ASM1042 1214 * SuperSpeed USB Host Controller can suddenly stop 1215 * accepting commands via the command queue. Try to 1216 * first reset the command queue. If that fails do a 1217 * host controller reset. 1218 */ 1219 if (timeout == 0 && 1220 xhci_reset_command_queue_locked(sc) == 0) { 1221 temp = le32toh(trb->dwTrb3); 1222 1223 /* 1224 * Avoid infinite XHCI reset loops if the set 1225 * address command fails to respond due to a 1226 * non-enumerating device: 1227 */ 1228 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1229 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1230 DPRINTF("Set address timeout\n"); 1231 } else { 1232 timeout = 1; 1233 goto retry; 1234 } 1235 } else { 1236 DPRINTF("Controller reset!\n"); 1237 usb_bus_reset_async_locked(&sc->sc_bus); 1238 } 1239 err = USB_ERR_TIMEOUT; 1240 trb->dwTrb2 = 0; 1241 trb->dwTrb3 = 0; 1242 } else { 1243 temp = le32toh(sc->sc_cmd_result[0]); 1244 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1245 err = USB_ERR_IOERROR; 1246 1247 trb->dwTrb2 = sc->sc_cmd_result[0]; 1248 trb->dwTrb3 = sc->sc_cmd_result[1]; 1249 } 1250 1251 USB_BUS_UNLOCK(&sc->sc_bus); 1252 1253 return (err); 1254 } 1255 1256 #if 0 1257 static usb_error_t 1258 xhci_cmd_nop(struct xhci_softc *sc) 1259 { 1260 struct xhci_trb trb; 1261 uint32_t temp; 1262 1263 DPRINTF("\n"); 1264 1265 trb.qwTrb0 = 0; 1266 trb.dwTrb2 = 0; 1267 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1268 1269 trb.dwTrb3 = htole32(temp); 1270 1271 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1272 } 1273 #endif 1274 1275 static usb_error_t 1276 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1277 { 1278 struct xhci_trb trb; 1279 uint32_t temp; 1280 usb_error_t err; 1281 1282 DPRINTF("\n"); 1283 1284 trb.qwTrb0 = 0; 1285 trb.dwTrb2 = 0; 1286 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1287 1288 err = xhci_do_command(sc, &trb, 100 /* ms */); 1289 if (err) 1290 goto done; 1291 1292 temp = le32toh(trb.dwTrb3); 1293 1294 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1295 1296 done: 1297 return (err); 1298 } 1299 1300 static usb_error_t 1301 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1302 { 1303 struct xhci_trb trb; 1304 uint32_t temp; 1305 1306 DPRINTF("\n"); 1307 1308 trb.qwTrb0 = 0; 1309 trb.dwTrb2 = 0; 1310 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1311 XHCI_TRB_3_SLOT_SET(slot_id); 1312 1313 trb.dwTrb3 = htole32(temp); 1314 1315 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1316 } 1317 1318 static usb_error_t 1319 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1320 uint8_t bsr, uint8_t slot_id) 1321 { 1322 struct xhci_trb trb; 1323 uint32_t temp; 1324 1325 DPRINTF("\n"); 1326 1327 trb.qwTrb0 = htole64(input_ctx); 1328 trb.dwTrb2 = 0; 1329 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1330 XHCI_TRB_3_SLOT_SET(slot_id); 1331 1332 if (bsr) 1333 temp |= XHCI_TRB_3_BSR_BIT; 1334 1335 trb.dwTrb3 = htole32(temp); 1336 1337 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1338 } 1339 1340 static usb_error_t 1341 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1342 { 1343 struct usb_page_search buf_inp; 1344 struct usb_page_search buf_dev; 1345 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1346 struct xhci_hw_dev *hdev; 1347 struct xhci_dev_ctx *pdev; 1348 struct xhci_endpoint_ext *pepext; 1349 uint32_t temp; 1350 uint16_t mps; 1351 usb_error_t err; 1352 uint8_t index; 1353 1354 /* the root HUB case is not handled here */ 1355 if (udev->parent_hub == NULL) 1356 return (USB_ERR_INVAL); 1357 1358 index = udev->controller_slot_id; 1359 1360 hdev = &sc->sc_hw.devs[index]; 1361 1362 if (mtx != NULL) 1363 mtx_unlock(mtx); 1364 1365 XHCI_CMD_LOCK(sc); 1366 1367 switch (hdev->state) { 1368 case XHCI_ST_DEFAULT: 1369 case XHCI_ST_ENABLED: 1370 1371 hdev->state = XHCI_ST_ENABLED; 1372 1373 /* set configure mask to slot and EP0 */ 1374 xhci_configure_mask(udev, 3, 0); 1375 1376 /* configure input slot context structure */ 1377 err = xhci_configure_device(udev); 1378 1379 if (err != 0) { 1380 DPRINTF("Could not configure device\n"); 1381 break; 1382 } 1383 1384 /* configure input endpoint context structure */ 1385 switch (udev->speed) { 1386 case USB_SPEED_LOW: 1387 case USB_SPEED_FULL: 1388 mps = 8; 1389 break; 1390 case USB_SPEED_HIGH: 1391 mps = 64; 1392 break; 1393 default: 1394 mps = 512; 1395 break; 1396 } 1397 1398 pepext = xhci_get_endpoint_ext(udev, 1399 &udev->ctrl_ep_desc); 1400 err = xhci_configure_endpoint(udev, 1401 &udev->ctrl_ep_desc, pepext, 1402 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1403 1404 if (err != 0) { 1405 DPRINTF("Could not configure default endpoint\n"); 1406 break; 1407 } 1408 1409 /* execute set address command */ 1410 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1411 1412 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1413 (address == 0), index); 1414 1415 if (err != 0) { 1416 temp = le32toh(sc->sc_cmd_result[0]); 1417 if (address == 0 && sc->sc_port_route != NULL && 1418 XHCI_TRB_2_ERROR_GET(temp) == 1419 XHCI_TRB_ERROR_PARAMETER) { 1420 /* LynxPoint XHCI - ports are not switchable */ 1421 /* Un-route all ports from the XHCI */ 1422 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1423 } 1424 DPRINTF("Could not set address " 1425 "for slot %u.\n", index); 1426 if (address != 0) 1427 break; 1428 } 1429 1430 /* update device address to new value */ 1431 1432 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1433 pdev = buf_dev.buffer; 1434 usb_pc_cpu_invalidate(&hdev->device_pc); 1435 1436 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1437 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1438 1439 /* update device state to new value */ 1440 1441 if (address != 0) 1442 hdev->state = XHCI_ST_ADDRESSED; 1443 else 1444 hdev->state = XHCI_ST_DEFAULT; 1445 break; 1446 1447 default: 1448 DPRINTF("Wrong state for set address.\n"); 1449 err = USB_ERR_IOERROR; 1450 break; 1451 } 1452 XHCI_CMD_UNLOCK(sc); 1453 1454 if (mtx != NULL) 1455 mtx_lock(mtx); 1456 1457 return (err); 1458 } 1459 1460 static usb_error_t 1461 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1462 uint8_t deconfigure, uint8_t slot_id) 1463 { 1464 struct xhci_trb trb; 1465 uint32_t temp; 1466 1467 DPRINTF("\n"); 1468 1469 trb.qwTrb0 = htole64(input_ctx); 1470 trb.dwTrb2 = 0; 1471 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1472 XHCI_TRB_3_SLOT_SET(slot_id); 1473 1474 if (deconfigure) 1475 temp |= XHCI_TRB_3_DCEP_BIT; 1476 1477 trb.dwTrb3 = htole32(temp); 1478 1479 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1480 } 1481 1482 static usb_error_t 1483 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1484 uint8_t slot_id) 1485 { 1486 struct xhci_trb trb; 1487 uint32_t temp; 1488 1489 DPRINTF("\n"); 1490 1491 trb.qwTrb0 = htole64(input_ctx); 1492 trb.dwTrb2 = 0; 1493 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1494 XHCI_TRB_3_SLOT_SET(slot_id); 1495 trb.dwTrb3 = htole32(temp); 1496 1497 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1498 } 1499 1500 static usb_error_t 1501 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1502 uint8_t ep_id, uint8_t slot_id) 1503 { 1504 struct xhci_trb trb; 1505 uint32_t temp; 1506 1507 DPRINTF("\n"); 1508 1509 trb.qwTrb0 = 0; 1510 trb.dwTrb2 = 0; 1511 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1512 XHCI_TRB_3_SLOT_SET(slot_id) | 1513 XHCI_TRB_3_EP_SET(ep_id); 1514 1515 if (preserve) 1516 temp |= XHCI_TRB_3_PRSV_BIT; 1517 1518 trb.dwTrb3 = htole32(temp); 1519 1520 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1521 } 1522 1523 static usb_error_t 1524 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1525 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1526 { 1527 struct xhci_trb trb; 1528 uint32_t temp; 1529 1530 DPRINTF("\n"); 1531 1532 trb.qwTrb0 = htole64(dequeue_ptr); 1533 1534 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1535 trb.dwTrb2 = htole32(temp); 1536 1537 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1538 XHCI_TRB_3_SLOT_SET(slot_id) | 1539 XHCI_TRB_3_EP_SET(ep_id); 1540 trb.dwTrb3 = htole32(temp); 1541 1542 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1543 } 1544 1545 static usb_error_t 1546 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1547 uint8_t ep_id, uint8_t slot_id) 1548 { 1549 struct xhci_trb trb; 1550 uint32_t temp; 1551 1552 DPRINTF("\n"); 1553 1554 trb.qwTrb0 = 0; 1555 trb.dwTrb2 = 0; 1556 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1557 XHCI_TRB_3_SLOT_SET(slot_id) | 1558 XHCI_TRB_3_EP_SET(ep_id); 1559 1560 if (suspend) 1561 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1562 1563 trb.dwTrb3 = htole32(temp); 1564 1565 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1566 } 1567 1568 static usb_error_t 1569 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1570 { 1571 struct xhci_trb trb; 1572 uint32_t temp; 1573 1574 DPRINTF("\n"); 1575 1576 trb.qwTrb0 = 0; 1577 trb.dwTrb2 = 0; 1578 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1579 XHCI_TRB_3_SLOT_SET(slot_id); 1580 1581 trb.dwTrb3 = htole32(temp); 1582 1583 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1584 } 1585 1586 /*------------------------------------------------------------------------* 1587 * xhci_interrupt - XHCI interrupt handler 1588 *------------------------------------------------------------------------*/ 1589 void 1590 xhci_interrupt(struct xhci_softc *sc) 1591 { 1592 uint32_t status; 1593 uint32_t temp; 1594 1595 USB_BUS_LOCK(&sc->sc_bus); 1596 1597 status = XREAD4(sc, oper, XHCI_USBSTS); 1598 1599 /* acknowledge interrupts, if any */ 1600 if (status != 0) { 1601 XWRITE4(sc, oper, XHCI_USBSTS, status); 1602 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1603 } 1604 1605 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1606 1607 /* force clearing of pending interrupts */ 1608 if (temp & XHCI_IMAN_INTR_PEND) 1609 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1610 1611 /* check for event(s) */ 1612 xhci_interrupt_poll(sc); 1613 1614 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1615 XHCI_STS_HSE | XHCI_STS_HCE)) { 1616 1617 if (status & XHCI_STS_PCD) { 1618 xhci_root_intr(sc); 1619 } 1620 1621 if (status & XHCI_STS_HCH) { 1622 printf("%s: host controller halted\n", 1623 __FUNCTION__); 1624 } 1625 1626 if (status & XHCI_STS_HSE) { 1627 printf("%s: host system error\n", 1628 __FUNCTION__); 1629 } 1630 1631 if (status & XHCI_STS_HCE) { 1632 printf("%s: host controller error\n", 1633 __FUNCTION__); 1634 } 1635 } 1636 USB_BUS_UNLOCK(&sc->sc_bus); 1637 } 1638 1639 /*------------------------------------------------------------------------* 1640 * xhci_timeout - XHCI timeout handler 1641 *------------------------------------------------------------------------*/ 1642 static void 1643 xhci_timeout(void *arg) 1644 { 1645 struct usb_xfer *xfer = arg; 1646 1647 DPRINTF("xfer=%p\n", xfer); 1648 1649 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1650 1651 /* transfer is transferred */ 1652 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1653 } 1654 1655 static void 1656 xhci_do_poll(struct usb_bus *bus) 1657 { 1658 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1659 1660 USB_BUS_LOCK(&sc->sc_bus); 1661 xhci_interrupt_poll(sc); 1662 USB_BUS_UNLOCK(&sc->sc_bus); 1663 } 1664 1665 static void 1666 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1667 { 1668 struct usb_page_search buf_res; 1669 struct xhci_td *td; 1670 struct xhci_td *td_next; 1671 struct xhci_td *td_alt_next; 1672 struct xhci_td *td_first; 1673 uint32_t buf_offset; 1674 uint32_t average; 1675 uint32_t len_old; 1676 uint32_t npkt_off; 1677 uint32_t dword; 1678 uint8_t shortpkt_old; 1679 uint8_t precompute; 1680 uint8_t x; 1681 1682 td_alt_next = NULL; 1683 buf_offset = 0; 1684 shortpkt_old = temp->shortpkt; 1685 len_old = temp->len; 1686 npkt_off = 0; 1687 precompute = 1; 1688 1689 restart: 1690 1691 td = temp->td; 1692 td_next = td_first = temp->td_next; 1693 1694 while (1) { 1695 1696 if (temp->len == 0) { 1697 1698 if (temp->shortpkt) 1699 break; 1700 1701 /* send a Zero Length Packet, ZLP, last */ 1702 1703 temp->shortpkt = 1; 1704 average = 0; 1705 1706 } else { 1707 1708 average = temp->average; 1709 1710 if (temp->len < average) { 1711 if (temp->len % temp->max_packet_size) { 1712 temp->shortpkt = 1; 1713 } 1714 average = temp->len; 1715 } 1716 } 1717 1718 if (td_next == NULL) 1719 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1720 1721 /* get next TD */ 1722 1723 td = td_next; 1724 td_next = td->obj_next; 1725 1726 /* check if we are pre-computing */ 1727 1728 if (precompute) { 1729 1730 /* update remaining length */ 1731 1732 temp->len -= average; 1733 1734 continue; 1735 } 1736 /* fill out current TD */ 1737 1738 td->len = average; 1739 td->remainder = 0; 1740 td->status = 0; 1741 1742 /* update remaining length */ 1743 1744 temp->len -= average; 1745 1746 /* reset TRB index */ 1747 1748 x = 0; 1749 1750 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1751 /* immediate data */ 1752 1753 if (average > 8) 1754 average = 8; 1755 1756 td->td_trb[0].qwTrb0 = 0; 1757 1758 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1759 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1760 average); 1761 1762 dword = XHCI_TRB_2_BYTES_SET(8) | 1763 XHCI_TRB_2_TDSZ_SET(0) | 1764 XHCI_TRB_2_IRQ_SET(0); 1765 1766 td->td_trb[0].dwTrb2 = htole32(dword); 1767 1768 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1769 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1770 1771 /* check wLength */ 1772 if (td->td_trb[0].qwTrb0 & 1773 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1774 if (td->td_trb[0].qwTrb0 & 1775 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1776 dword |= XHCI_TRB_3_TRT_IN; 1777 else 1778 dword |= XHCI_TRB_3_TRT_OUT; 1779 } 1780 1781 td->td_trb[0].dwTrb3 = htole32(dword); 1782 #ifdef USB_DEBUG 1783 xhci_dump_trb(&td->td_trb[x]); 1784 #endif 1785 x++; 1786 1787 } else do { 1788 1789 uint32_t npkt; 1790 1791 /* fill out buffer pointers */ 1792 1793 if (average == 0) { 1794 memset(&buf_res, 0, sizeof(buf_res)); 1795 } else { 1796 usbd_get_page(temp->pc, temp->offset + 1797 buf_offset, &buf_res); 1798 1799 /* get length to end of page */ 1800 if (buf_res.length > average) 1801 buf_res.length = average; 1802 1803 /* check for maximum length */ 1804 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1805 buf_res.length = XHCI_TD_PAGE_SIZE; 1806 1807 npkt_off += buf_res.length; 1808 } 1809 1810 /* setup npkt */ 1811 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1812 temp->max_packet_size; 1813 1814 if (npkt == 0) 1815 npkt = 1; 1816 else if (npkt > 31) 1817 npkt = 31; 1818 1819 /* fill out TRB's */ 1820 td->td_trb[x].qwTrb0 = 1821 htole64((uint64_t)buf_res.physaddr); 1822 1823 dword = 1824 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1825 XHCI_TRB_2_TDSZ_SET(npkt) | 1826 XHCI_TRB_2_IRQ_SET(0); 1827 1828 td->td_trb[x].dwTrb2 = htole32(dword); 1829 1830 switch (temp->trb_type) { 1831 case XHCI_TRB_TYPE_ISOCH: 1832 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1833 XHCI_TRB_3_TBC_SET(temp->tbc) | 1834 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1835 if (td != td_first) { 1836 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1837 } else if (temp->do_isoc_sync != 0) { 1838 temp->do_isoc_sync = 0; 1839 /* wait until "isoc_frame" */ 1840 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1841 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1842 } else { 1843 /* start data transfer at next interval */ 1844 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1845 XHCI_TRB_3_ISO_SIA_BIT; 1846 } 1847 if (temp->direction == UE_DIR_IN) 1848 dword |= XHCI_TRB_3_ISP_BIT; 1849 break; 1850 case XHCI_TRB_TYPE_DATA_STAGE: 1851 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1852 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1853 if (temp->direction == UE_DIR_IN) 1854 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1855 break; 1856 case XHCI_TRB_TYPE_STATUS_STAGE: 1857 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1858 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1859 if (temp->direction == UE_DIR_IN) 1860 dword |= XHCI_TRB_3_DIR_IN; 1861 break; 1862 default: /* XHCI_TRB_TYPE_NORMAL */ 1863 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1864 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1865 if (temp->direction == UE_DIR_IN) 1866 dword |= XHCI_TRB_3_ISP_BIT; 1867 break; 1868 } 1869 td->td_trb[x].dwTrb3 = htole32(dword); 1870 1871 average -= buf_res.length; 1872 buf_offset += buf_res.length; 1873 #ifdef USB_DEBUG 1874 xhci_dump_trb(&td->td_trb[x]); 1875 #endif 1876 x++; 1877 1878 } while (average != 0); 1879 1880 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1881 1882 /* store number of data TRB's */ 1883 1884 td->ntrb = x; 1885 1886 DPRINTF("NTRB=%u\n", x); 1887 1888 /* fill out link TRB */ 1889 1890 if (td_next != NULL) { 1891 /* link the current TD with the next one */ 1892 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1893 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1894 } else { 1895 /* this field will get updated later */ 1896 DPRINTF("NOLINK\n"); 1897 } 1898 1899 dword = XHCI_TRB_2_IRQ_SET(0); 1900 1901 td->td_trb[x].dwTrb2 = htole32(dword); 1902 1903 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1904 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1905 /* 1906 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1907 * frame only receives a single short packet event 1908 * by setting the CHAIN bit in the LINK field. In 1909 * addition some XHCI controllers have problems 1910 * sending a ZLP unless the CHAIN-BIT is set in 1911 * the LINK TRB. 1912 */ 1913 XHCI_TRB_3_CHAIN_BIT; 1914 1915 td->td_trb[x].dwTrb3 = htole32(dword); 1916 1917 td->alt_next = td_alt_next; 1918 #ifdef USB_DEBUG 1919 xhci_dump_trb(&td->td_trb[x]); 1920 #endif 1921 usb_pc_cpu_flush(td->page_cache); 1922 } 1923 1924 if (precompute) { 1925 precompute = 0; 1926 1927 /* setup alt next pointer, if any */ 1928 if (temp->last_frame) { 1929 td_alt_next = NULL; 1930 } else { 1931 /* we use this field internally */ 1932 td_alt_next = td_next; 1933 } 1934 1935 /* restore */ 1936 temp->shortpkt = shortpkt_old; 1937 temp->len = len_old; 1938 goto restart; 1939 } 1940 1941 /* 1942 * Remove cycle bit from the first TRB if we are 1943 * stepping them: 1944 */ 1945 if (temp->step_td != 0) { 1946 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1947 usb_pc_cpu_flush(td_first->page_cache); 1948 } 1949 1950 /* clear TD SIZE to zero, hence this is the last TRB */ 1951 /* remove chain bit because this is the last data TRB in the chain */ 1952 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1953 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1954 /* remove CHAIN-BIT from last LINK TRB */ 1955 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1956 1957 usb_pc_cpu_flush(td->page_cache); 1958 1959 temp->td = td; 1960 temp->td_next = td_next; 1961 } 1962 1963 static void 1964 xhci_setup_generic_chain(struct usb_xfer *xfer) 1965 { 1966 struct xhci_std_temp temp; 1967 struct xhci_td *td; 1968 uint32_t x; 1969 uint32_t y; 1970 uint8_t mult; 1971 1972 temp.do_isoc_sync = 0; 1973 temp.step_td = 0; 1974 temp.tbc = 0; 1975 temp.tlbpc = 0; 1976 temp.average = xfer->max_hc_frame_size; 1977 temp.max_packet_size = xfer->max_packet_size; 1978 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1979 temp.pc = NULL; 1980 temp.last_frame = 0; 1981 temp.offset = 0; 1982 temp.multishort = xfer->flags_int.isochronous_xfr || 1983 xfer->flags_int.control_xfr || 1984 xfer->flags_int.short_frames_ok; 1985 1986 /* toggle the DMA set we are using */ 1987 xfer->flags_int.curr_dma_set ^= 1; 1988 1989 /* get next DMA set */ 1990 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1991 1992 temp.td = NULL; 1993 temp.td_next = td; 1994 1995 xfer->td_transfer_first = td; 1996 xfer->td_transfer_cache = td; 1997 1998 if (xfer->flags_int.isochronous_xfr) { 1999 uint8_t shift; 2000 2001 /* compute multiplier for ISOCHRONOUS transfers */ 2002 mult = xfer->endpoint->ecomp ? 2003 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2004 : 0; 2005 /* check for USB 2.0 multiplier */ 2006 if (mult == 0) { 2007 mult = (xfer->endpoint->edesc-> 2008 wMaxPacketSize[1] >> 3) & 3; 2009 } 2010 /* range check */ 2011 if (mult > 2) 2012 mult = 3; 2013 else 2014 mult++; 2015 2016 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2017 2018 DPRINTF("MFINDEX=0x%08x\n", x); 2019 2020 switch (usbd_get_speed(xfer->xroot->udev)) { 2021 case USB_SPEED_FULL: 2022 shift = 3; 2023 temp.isoc_delta = 8; /* 1ms */ 2024 x += temp.isoc_delta - 1; 2025 x &= ~(temp.isoc_delta - 1); 2026 break; 2027 default: 2028 shift = usbd_xfer_get_fps_shift(xfer); 2029 temp.isoc_delta = 1U << shift; 2030 x += temp.isoc_delta - 1; 2031 x &= ~(temp.isoc_delta - 1); 2032 /* simple frame load balancing */ 2033 x += xfer->endpoint->usb_uframe; 2034 break; 2035 } 2036 2037 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2038 2039 if ((xfer->endpoint->is_synced == 0) || 2040 (y < (xfer->nframes << shift)) || 2041 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2042 /* 2043 * If there is data underflow or the pipe 2044 * queue is empty we schedule the transfer a 2045 * few frames ahead of the current frame 2046 * position. Else two isochronous transfers 2047 * might overlap. 2048 */ 2049 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2050 xfer->endpoint->is_synced = 1; 2051 temp.do_isoc_sync = 1; 2052 2053 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2054 } 2055 2056 /* compute isochronous completion time */ 2057 2058 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2059 2060 xfer->isoc_time_complete = 2061 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2062 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2063 2064 x = 0; 2065 temp.isoc_frame = xfer->endpoint->isoc_next; 2066 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2067 2068 xfer->endpoint->isoc_next += xfer->nframes << shift; 2069 2070 } else if (xfer->flags_int.control_xfr) { 2071 2072 /* check if we should prepend a setup message */ 2073 2074 if (xfer->flags_int.control_hdr) { 2075 2076 temp.len = xfer->frlengths[0]; 2077 temp.pc = xfer->frbuffers + 0; 2078 temp.shortpkt = temp.len ? 1 : 0; 2079 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2080 temp.direction = 0; 2081 2082 /* check for last frame */ 2083 if (xfer->nframes == 1) { 2084 /* no STATUS stage yet, SETUP is last */ 2085 if (xfer->flags_int.control_act) 2086 temp.last_frame = 1; 2087 } 2088 2089 xhci_setup_generic_chain_sub(&temp); 2090 } 2091 x = 1; 2092 mult = 1; 2093 temp.isoc_delta = 0; 2094 temp.isoc_frame = 0; 2095 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 2096 } else { 2097 x = 0; 2098 mult = 1; 2099 temp.isoc_delta = 0; 2100 temp.isoc_frame = 0; 2101 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2102 } 2103 2104 if (x != xfer->nframes) { 2105 /* setup page_cache pointer */ 2106 temp.pc = xfer->frbuffers + x; 2107 /* set endpoint direction */ 2108 temp.direction = UE_GET_DIR(xfer->endpointno); 2109 } 2110 2111 while (x != xfer->nframes) { 2112 2113 /* DATA0 / DATA1 message */ 2114 2115 temp.len = xfer->frlengths[x]; 2116 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2117 x != 0 && temp.multishort == 0); 2118 2119 x++; 2120 2121 if (x == xfer->nframes) { 2122 if (xfer->flags_int.control_xfr) { 2123 /* no STATUS stage yet, DATA is last */ 2124 if (xfer->flags_int.control_act) 2125 temp.last_frame = 1; 2126 } else { 2127 temp.last_frame = 1; 2128 } 2129 } 2130 if (temp.len == 0) { 2131 2132 /* make sure that we send an USB packet */ 2133 2134 temp.shortpkt = 0; 2135 2136 temp.tbc = 0; 2137 temp.tlbpc = mult - 1; 2138 2139 } else if (xfer->flags_int.isochronous_xfr) { 2140 2141 uint8_t tdpc; 2142 2143 /* 2144 * Isochronous transfers don't have short 2145 * packet termination: 2146 */ 2147 2148 temp.shortpkt = 1; 2149 2150 /* isochronous transfers have a transfer limit */ 2151 2152 if (temp.len > xfer->max_frame_size) 2153 temp.len = xfer->max_frame_size; 2154 2155 /* compute TD packet count */ 2156 tdpc = (temp.len + xfer->max_packet_size - 1) / 2157 xfer->max_packet_size; 2158 2159 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2160 temp.tlbpc = (tdpc % mult); 2161 2162 if (temp.tlbpc == 0) 2163 temp.tlbpc = mult - 1; 2164 else 2165 temp.tlbpc--; 2166 } else { 2167 2168 /* regular data transfer */ 2169 2170 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2171 } 2172 2173 xhci_setup_generic_chain_sub(&temp); 2174 2175 if (xfer->flags_int.isochronous_xfr) { 2176 temp.offset += xfer->frlengths[x - 1]; 2177 temp.isoc_frame += temp.isoc_delta; 2178 } else { 2179 /* get next Page Cache pointer */ 2180 temp.pc = xfer->frbuffers + x; 2181 } 2182 } 2183 2184 /* check if we should append a status stage */ 2185 2186 if (xfer->flags_int.control_xfr && 2187 !xfer->flags_int.control_act) { 2188 2189 /* 2190 * Send a DATA1 message and invert the current 2191 * endpoint direction. 2192 */ 2193 temp.step_td = (xfer->nframes != 0); 2194 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2195 temp.len = 0; 2196 temp.pc = NULL; 2197 temp.shortpkt = 0; 2198 temp.last_frame = 1; 2199 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2200 2201 xhci_setup_generic_chain_sub(&temp); 2202 } 2203 2204 td = temp.td; 2205 2206 /* must have at least one frame! */ 2207 2208 xfer->td_transfer_last = td; 2209 2210 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2211 } 2212 2213 static void 2214 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2215 { 2216 struct usb_page_search buf_res; 2217 struct xhci_dev_ctx_addr *pdctxa; 2218 2219 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2220 2221 pdctxa = buf_res.buffer; 2222 2223 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2224 2225 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2226 2227 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2228 } 2229 2230 static usb_error_t 2231 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2232 { 2233 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2234 struct usb_page_search buf_inp; 2235 struct xhci_input_dev_ctx *pinp; 2236 uint32_t temp; 2237 uint8_t index; 2238 uint8_t x; 2239 2240 index = udev->controller_slot_id; 2241 2242 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2243 2244 pinp = buf_inp.buffer; 2245 2246 if (drop) { 2247 mask &= XHCI_INCTX_NON_CTRL_MASK; 2248 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2249 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2250 } else { 2251 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2252 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2253 2254 /* find most significant set bit */ 2255 for (x = 31; x != 1; x--) { 2256 if (mask & (1 << x)) 2257 break; 2258 } 2259 2260 /* adjust */ 2261 x--; 2262 2263 /* figure out maximum */ 2264 if (x > sc->sc_hw.devs[index].context_num) { 2265 sc->sc_hw.devs[index].context_num = x; 2266 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2267 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2268 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2269 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2270 } 2271 } 2272 return (0); 2273 } 2274 2275 static usb_error_t 2276 xhci_configure_endpoint(struct usb_device *udev, 2277 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2278 uint16_t interval, uint8_t max_packet_count, 2279 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2280 uint16_t max_frame_size, uint8_t ep_mode) 2281 { 2282 struct usb_page_search buf_inp; 2283 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2284 struct xhci_input_dev_ctx *pinp; 2285 uint64_t ring_addr = pepext->physaddr; 2286 uint32_t temp; 2287 uint8_t index; 2288 uint8_t epno; 2289 uint8_t type; 2290 2291 index = udev->controller_slot_id; 2292 2293 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2294 2295 pinp = buf_inp.buffer; 2296 2297 epno = edesc->bEndpointAddress; 2298 type = edesc->bmAttributes & UE_XFERTYPE; 2299 2300 if (type == UE_CONTROL) 2301 epno |= UE_DIR_IN; 2302 2303 epno = XHCI_EPNO2EPID(epno); 2304 2305 if (epno == 0) 2306 return (USB_ERR_NO_PIPE); /* invalid */ 2307 2308 if (max_packet_count == 0) 2309 return (USB_ERR_BAD_BUFSIZE); 2310 2311 max_packet_count--; 2312 2313 if (mult == 0) 2314 return (USB_ERR_BAD_BUFSIZE); 2315 2316 /* store endpoint mode */ 2317 pepext->trb_ep_mode = ep_mode; 2318 usb_pc_cpu_flush(pepext->page_cache); 2319 2320 if (ep_mode == USB_EP_MODE_STREAMS) { 2321 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2322 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2323 XHCI_EPCTX_0_LSA_SET(1); 2324 2325 ring_addr += sizeof(struct xhci_trb) * 2326 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2327 } else { 2328 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2329 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2330 XHCI_EPCTX_0_LSA_SET(0); 2331 2332 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2333 } 2334 2335 switch (udev->speed) { 2336 case USB_SPEED_FULL: 2337 case USB_SPEED_LOW: 2338 /* 1ms -> 125us */ 2339 fps_shift += 3; 2340 break; 2341 default: 2342 break; 2343 } 2344 2345 switch (type) { 2346 case UE_INTERRUPT: 2347 if (fps_shift > 3) 2348 fps_shift--; 2349 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2350 break; 2351 case UE_ISOCHRONOUS: 2352 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2353 2354 switch (udev->speed) { 2355 case USB_SPEED_SUPER: 2356 if (mult > 3) 2357 mult = 3; 2358 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2359 max_packet_count /= mult; 2360 break; 2361 default: 2362 break; 2363 } 2364 break; 2365 default: 2366 break; 2367 } 2368 2369 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2370 2371 temp = 2372 XHCI_EPCTX_1_HID_SET(0) | 2373 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2374 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2375 2376 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2377 if (type != UE_ISOCHRONOUS) 2378 temp |= XHCI_EPCTX_1_CERR_SET(3); 2379 } 2380 2381 switch (type) { 2382 case UE_CONTROL: 2383 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2384 break; 2385 case UE_ISOCHRONOUS: 2386 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2387 break; 2388 case UE_BULK: 2389 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2390 break; 2391 default: 2392 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2393 break; 2394 } 2395 2396 /* check for IN direction */ 2397 if (epno & 1) 2398 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2399 2400 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2401 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2402 2403 switch (edesc->bmAttributes & UE_XFERTYPE) { 2404 case UE_INTERRUPT: 2405 case UE_ISOCHRONOUS: 2406 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2407 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2408 max_frame_size)); 2409 break; 2410 case UE_CONTROL: 2411 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2412 break; 2413 default: 2414 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2415 break; 2416 } 2417 2418 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2419 2420 #ifdef USB_DEBUG 2421 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2422 #endif 2423 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2424 2425 return (0); /* success */ 2426 } 2427 2428 static usb_error_t 2429 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2430 { 2431 struct xhci_endpoint_ext *pepext; 2432 struct usb_endpoint_ss_comp_descriptor *ecomp; 2433 usb_stream_t x; 2434 2435 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2436 xfer->endpoint->edesc); 2437 2438 ecomp = xfer->endpoint->ecomp; 2439 2440 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2441 uint64_t temp; 2442 2443 /* halt any transfers */ 2444 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2445 2446 /* compute start of TRB ring for stream "x" */ 2447 temp = pepext->physaddr + 2448 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2449 XHCI_SCTX_0_SCT_SEC_TR_RING; 2450 2451 /* make tree structure */ 2452 pepext->trb[(XHCI_MAX_TRANSFERS * 2453 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2454 2455 /* reserved fields */ 2456 pepext->trb[(XHCI_MAX_TRANSFERS * 2457 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2458 pepext->trb[(XHCI_MAX_TRANSFERS * 2459 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2460 } 2461 usb_pc_cpu_flush(pepext->page_cache); 2462 2463 return (xhci_configure_endpoint(xfer->xroot->udev, 2464 xfer->endpoint->edesc, pepext, 2465 xfer->interval, xfer->max_packet_count, 2466 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2467 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2468 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2469 } 2470 2471 static usb_error_t 2472 xhci_configure_device(struct usb_device *udev) 2473 { 2474 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2475 struct usb_page_search buf_inp; 2476 struct usb_page_cache *pcinp; 2477 struct xhci_input_dev_ctx *pinp; 2478 struct usb_device *hubdev; 2479 uint32_t temp; 2480 uint32_t route; 2481 uint32_t rh_port; 2482 uint8_t is_hub; 2483 uint8_t index; 2484 uint8_t depth; 2485 2486 index = udev->controller_slot_id; 2487 2488 DPRINTF("index=%u\n", index); 2489 2490 pcinp = &sc->sc_hw.devs[index].input_pc; 2491 2492 usbd_get_page(pcinp, 0, &buf_inp); 2493 2494 pinp = buf_inp.buffer; 2495 2496 rh_port = 0; 2497 route = 0; 2498 2499 /* figure out route string and root HUB port number */ 2500 2501 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2502 2503 if (hubdev->parent_hub == NULL) 2504 break; 2505 2506 depth = hubdev->parent_hub->depth; 2507 2508 /* 2509 * NOTE: HS/FS/LS devices and the SS root HUB can have 2510 * more than 15 ports 2511 */ 2512 2513 rh_port = hubdev->port_no; 2514 2515 if (depth == 0) 2516 break; 2517 2518 if (rh_port > 15) 2519 rh_port = 15; 2520 2521 if (depth < 6) 2522 route |= rh_port << (4 * (depth - 1)); 2523 } 2524 2525 DPRINTF("Route=0x%08x\n", route); 2526 2527 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2528 XHCI_SCTX_0_CTX_NUM_SET( 2529 sc->sc_hw.devs[index].context_num + 1); 2530 2531 switch (udev->speed) { 2532 case USB_SPEED_LOW: 2533 temp |= XHCI_SCTX_0_SPEED_SET(2); 2534 if (udev->parent_hs_hub != NULL && 2535 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2536 UDPROTO_HSHUBMTT) { 2537 DPRINTF("Device inherits MTT\n"); 2538 temp |= XHCI_SCTX_0_MTT_SET(1); 2539 } 2540 break; 2541 case USB_SPEED_HIGH: 2542 temp |= XHCI_SCTX_0_SPEED_SET(3); 2543 if (sc->sc_hw.devs[index].nports != 0 && 2544 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2545 DPRINTF("HUB supports MTT\n"); 2546 temp |= XHCI_SCTX_0_MTT_SET(1); 2547 } 2548 break; 2549 case USB_SPEED_FULL: 2550 temp |= XHCI_SCTX_0_SPEED_SET(1); 2551 if (udev->parent_hs_hub != NULL && 2552 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2553 UDPROTO_HSHUBMTT) { 2554 DPRINTF("Device inherits MTT\n"); 2555 temp |= XHCI_SCTX_0_MTT_SET(1); 2556 } 2557 break; 2558 default: 2559 temp |= XHCI_SCTX_0_SPEED_SET(4); 2560 break; 2561 } 2562 2563 is_hub = sc->sc_hw.devs[index].nports != 0 && 2564 (udev->speed == USB_SPEED_SUPER || 2565 udev->speed == USB_SPEED_HIGH); 2566 2567 if (is_hub) 2568 temp |= XHCI_SCTX_0_HUB_SET(1); 2569 2570 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2571 2572 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2573 2574 if (is_hub) { 2575 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2576 sc->sc_hw.devs[index].nports); 2577 } 2578 2579 switch (udev->speed) { 2580 case USB_SPEED_SUPER: 2581 switch (sc->sc_hw.devs[index].state) { 2582 case XHCI_ST_ADDRESSED: 2583 case XHCI_ST_CONFIGURED: 2584 /* enable power save */ 2585 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2586 break; 2587 default: 2588 /* disable power save */ 2589 break; 2590 } 2591 break; 2592 default: 2593 break; 2594 } 2595 2596 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2597 2598 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2599 2600 if (is_hub) { 2601 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2602 sc->sc_hw.devs[index].tt); 2603 } 2604 2605 hubdev = udev->parent_hs_hub; 2606 2607 /* check if we should activate the transaction translator */ 2608 switch (udev->speed) { 2609 case USB_SPEED_FULL: 2610 case USB_SPEED_LOW: 2611 if (hubdev != NULL) { 2612 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2613 hubdev->controller_slot_id); 2614 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2615 udev->hs_port_no); 2616 } 2617 break; 2618 default: 2619 break; 2620 } 2621 2622 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2623 2624 /* 2625 * These fields should be initialized to zero, according to 2626 * XHCI section 6.2.2 - slot context: 2627 */ 2628 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2629 XHCI_SCTX_3_SLOT_STATE_SET(0); 2630 2631 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2632 2633 #ifdef USB_DEBUG 2634 xhci_dump_device(sc, &pinp->ctx_slot); 2635 #endif 2636 usb_pc_cpu_flush(pcinp); 2637 2638 return (0); /* success */ 2639 } 2640 2641 static usb_error_t 2642 xhci_alloc_device_ext(struct usb_device *udev) 2643 { 2644 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2645 struct usb_page_search buf_dev; 2646 struct usb_page_search buf_ep; 2647 struct xhci_trb *trb; 2648 struct usb_page_cache *pc; 2649 struct usb_page *pg; 2650 uint64_t addr; 2651 uint8_t index; 2652 uint8_t i; 2653 2654 index = udev->controller_slot_id; 2655 2656 pc = &sc->sc_hw.devs[index].device_pc; 2657 pg = &sc->sc_hw.devs[index].device_pg; 2658 2659 /* need to initialize the page cache */ 2660 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2661 2662 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2663 (2 * sizeof(struct xhci_dev_ctx)) : 2664 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2665 goto error; 2666 2667 usbd_get_page(pc, 0, &buf_dev); 2668 2669 pc = &sc->sc_hw.devs[index].input_pc; 2670 pg = &sc->sc_hw.devs[index].input_pg; 2671 2672 /* need to initialize the page cache */ 2673 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2674 2675 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2676 (2 * sizeof(struct xhci_input_dev_ctx)) : 2677 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2678 goto error; 2679 } 2680 2681 pc = &sc->sc_hw.devs[index].endpoint_pc; 2682 pg = &sc->sc_hw.devs[index].endpoint_pg; 2683 2684 /* need to initialize the page cache */ 2685 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2686 2687 if (usb_pc_alloc_mem(pc, pg, 2688 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) { 2689 goto error; 2690 } 2691 2692 /* initialise all endpoint LINK TRBs */ 2693 2694 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2695 2696 /* lookup endpoint TRB ring */ 2697 usbd_get_page(pc, (uintptr_t)& 2698 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2699 2700 /* get TRB pointer */ 2701 trb = buf_ep.buffer; 2702 trb += XHCI_MAX_TRANSFERS - 1; 2703 2704 /* get TRB start address */ 2705 addr = buf_ep.physaddr; 2706 2707 /* create LINK TRB */ 2708 trb->qwTrb0 = htole64(addr); 2709 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2710 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2711 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2712 } 2713 2714 usb_pc_cpu_flush(pc); 2715 2716 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2717 2718 return (0); 2719 2720 error: 2721 xhci_free_device_ext(udev); 2722 2723 return (USB_ERR_NOMEM); 2724 } 2725 2726 static void 2727 xhci_free_device_ext(struct usb_device *udev) 2728 { 2729 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2730 uint8_t index; 2731 2732 index = udev->controller_slot_id; 2733 xhci_set_slot_pointer(sc, index, 0); 2734 2735 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2736 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2737 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2738 } 2739 2740 static struct xhci_endpoint_ext * 2741 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2742 { 2743 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2744 struct xhci_endpoint_ext *pepext; 2745 struct usb_page_cache *pc; 2746 struct usb_page_search buf_ep; 2747 uint8_t epno; 2748 uint8_t index; 2749 2750 epno = edesc->bEndpointAddress; 2751 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2752 epno |= UE_DIR_IN; 2753 2754 epno = XHCI_EPNO2EPID(epno); 2755 2756 index = udev->controller_slot_id; 2757 2758 pc = &sc->sc_hw.devs[index].endpoint_pc; 2759 2760 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2761 trb[epno][0], &buf_ep); 2762 2763 pepext = &sc->sc_hw.devs[index].endp[epno]; 2764 pepext->page_cache = pc; 2765 pepext->trb = buf_ep.buffer; 2766 pepext->physaddr = buf_ep.physaddr; 2767 2768 return (pepext); 2769 } 2770 2771 static void 2772 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2773 { 2774 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2775 uint8_t epno; 2776 uint8_t index; 2777 2778 epno = xfer->endpointno; 2779 if (xfer->flags_int.control_xfr) 2780 epno |= UE_DIR_IN; 2781 2782 epno = XHCI_EPNO2EPID(epno); 2783 index = xfer->xroot->udev->controller_slot_id; 2784 2785 if (xfer->xroot->udev->flags.self_suspended == 0) { 2786 XWRITE4(sc, door, XHCI_DOORBELL(index), 2787 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2788 } 2789 } 2790 2791 static void 2792 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2793 { 2794 struct xhci_endpoint_ext *pepext; 2795 2796 if (xfer->flags_int.bandwidth_reclaimed) { 2797 xfer->flags_int.bandwidth_reclaimed = 0; 2798 2799 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2800 xfer->endpoint->edesc); 2801 2802 pepext->trb_used[xfer->stream_id]--; 2803 2804 pepext->xfer[xfer->qh_pos] = NULL; 2805 2806 if (error && pepext->trb_running != 0) { 2807 pepext->trb_halted = 1; 2808 pepext->trb_running = 0; 2809 } 2810 } 2811 } 2812 2813 static usb_error_t 2814 xhci_transfer_insert(struct usb_xfer *xfer) 2815 { 2816 struct xhci_td *td_first; 2817 struct xhci_td *td_last; 2818 struct xhci_trb *trb_link; 2819 struct xhci_endpoint_ext *pepext; 2820 uint64_t addr; 2821 usb_stream_t id; 2822 uint8_t i; 2823 uint8_t inext; 2824 uint8_t trb_limit; 2825 2826 DPRINTFN(8, "\n"); 2827 2828 id = xfer->stream_id; 2829 2830 /* check if already inserted */ 2831 if (xfer->flags_int.bandwidth_reclaimed) { 2832 DPRINTFN(8, "Already in schedule\n"); 2833 return (0); 2834 } 2835 2836 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2837 xfer->endpoint->edesc); 2838 2839 td_first = xfer->td_transfer_first; 2840 td_last = xfer->td_transfer_last; 2841 addr = pepext->physaddr; 2842 2843 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2844 case UE_CONTROL: 2845 case UE_INTERRUPT: 2846 /* single buffered */ 2847 trb_limit = 1; 2848 break; 2849 default: 2850 /* multi buffered */ 2851 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2852 break; 2853 } 2854 2855 if (pepext->trb_used[id] >= trb_limit) { 2856 DPRINTFN(8, "Too many TDs queued.\n"); 2857 return (USB_ERR_NOMEM); 2858 } 2859 2860 /* check for stopped condition, after putting transfer on interrupt queue */ 2861 if (pepext->trb_running == 0) { 2862 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2863 2864 DPRINTFN(8, "Not running\n"); 2865 2866 /* start configuration */ 2867 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2868 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2869 return (0); 2870 } 2871 2872 pepext->trb_used[id]++; 2873 2874 /* get current TRB index */ 2875 i = pepext->trb_index[id]; 2876 2877 /* get next TRB index */ 2878 inext = (i + 1); 2879 2880 /* the last entry of the ring is a hardcoded link TRB */ 2881 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2882 inext = 0; 2883 2884 /* store next TRB index, before stream ID offset is added */ 2885 pepext->trb_index[id] = inext; 2886 2887 /* offset for stream */ 2888 i += id * XHCI_MAX_TRANSFERS; 2889 inext += id * XHCI_MAX_TRANSFERS; 2890 2891 /* compute terminating return address */ 2892 addr += (inext * sizeof(struct xhci_trb)); 2893 2894 /* compute link TRB pointer */ 2895 trb_link = td_last->td_trb + td_last->ntrb; 2896 2897 /* update next pointer of last link TRB */ 2898 trb_link->qwTrb0 = htole64(addr); 2899 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2900 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2901 XHCI_TRB_3_CYCLE_BIT | 2902 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2903 2904 #ifdef USB_DEBUG 2905 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2906 #endif 2907 usb_pc_cpu_flush(td_last->page_cache); 2908 2909 /* write ahead chain end marker */ 2910 2911 pepext->trb[inext].qwTrb0 = 0; 2912 pepext->trb[inext].dwTrb2 = 0; 2913 pepext->trb[inext].dwTrb3 = 0; 2914 2915 /* update next pointer of link TRB */ 2916 2917 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2918 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2919 2920 #ifdef USB_DEBUG 2921 xhci_dump_trb(&pepext->trb[i]); 2922 #endif 2923 usb_pc_cpu_flush(pepext->page_cache); 2924 2925 /* toggle cycle bit which activates the transfer chain */ 2926 2927 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2928 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2929 2930 usb_pc_cpu_flush(pepext->page_cache); 2931 2932 DPRINTF("qh_pos = %u\n", i); 2933 2934 pepext->xfer[i] = xfer; 2935 2936 xfer->qh_pos = i; 2937 2938 xfer->flags_int.bandwidth_reclaimed = 1; 2939 2940 xhci_endpoint_doorbell(xfer); 2941 2942 return (0); 2943 } 2944 2945 static void 2946 xhci_root_intr(struct xhci_softc *sc) 2947 { 2948 uint16_t i; 2949 2950 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2951 2952 /* clear any old interrupt data */ 2953 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2954 2955 for (i = 1; i <= sc->sc_noport; i++) { 2956 /* pick out CHANGE bits from the status register */ 2957 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2958 XHCI_PS_CSC | XHCI_PS_PEC | 2959 XHCI_PS_OCC | XHCI_PS_WRC | 2960 XHCI_PS_PRC | XHCI_PS_PLC | 2961 XHCI_PS_CEC)) { 2962 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2963 DPRINTF("port %d changed\n", i); 2964 } 2965 } 2966 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2967 sizeof(sc->sc_hub_idata)); 2968 } 2969 2970 /*------------------------------------------------------------------------* 2971 * xhci_device_done - XHCI done handler 2972 * 2973 * NOTE: This function can be called two times in a row on 2974 * the same USB transfer. From close and from interrupt. 2975 *------------------------------------------------------------------------*/ 2976 static void 2977 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2978 { 2979 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2980 xfer, xfer->endpoint, error); 2981 2982 /* remove transfer from HW queue */ 2983 xhci_transfer_remove(xfer, error); 2984 2985 /* dequeue transfer and start next transfer */ 2986 usbd_transfer_done(xfer, error); 2987 } 2988 2989 /*------------------------------------------------------------------------* 2990 * XHCI data transfer support (generic type) 2991 *------------------------------------------------------------------------*/ 2992 static void 2993 xhci_device_generic_open(struct usb_xfer *xfer) 2994 { 2995 if (xfer->flags_int.isochronous_xfr) { 2996 switch (xfer->xroot->udev->speed) { 2997 case USB_SPEED_FULL: 2998 break; 2999 default: 3000 usb_hs_bandwidth_alloc(xfer); 3001 break; 3002 } 3003 } 3004 } 3005 3006 static void 3007 xhci_device_generic_close(struct usb_xfer *xfer) 3008 { 3009 DPRINTF("\n"); 3010 3011 xhci_device_done(xfer, USB_ERR_CANCELLED); 3012 3013 if (xfer->flags_int.isochronous_xfr) { 3014 switch (xfer->xroot->udev->speed) { 3015 case USB_SPEED_FULL: 3016 break; 3017 default: 3018 usb_hs_bandwidth_free(xfer); 3019 break; 3020 } 3021 } 3022 } 3023 3024 static void 3025 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3026 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3027 { 3028 struct usb_xfer *xfer; 3029 3030 /* check if there is a current transfer */ 3031 xfer = ep->endpoint_q[stream_id].curr; 3032 if (xfer == NULL) 3033 return; 3034 3035 /* 3036 * Check if the current transfer is started and then pickup 3037 * the next one, if any. Else wait for next start event due to 3038 * block on failure feature. 3039 */ 3040 if (!xfer->flags_int.bandwidth_reclaimed) 3041 return; 3042 3043 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3044 if (xfer == NULL) { 3045 /* 3046 * In case of enter we have to consider that the 3047 * transfer is queued by the USB core after the enter 3048 * method is called. 3049 */ 3050 xfer = enter_xfer; 3051 3052 if (xfer == NULL) 3053 return; 3054 } 3055 3056 /* try to multi buffer */ 3057 xhci_transfer_insert(xfer); 3058 } 3059 3060 static void 3061 xhci_device_generic_enter(struct usb_xfer *xfer) 3062 { 3063 DPRINTF("\n"); 3064 3065 /* setup TD's and QH */ 3066 xhci_setup_generic_chain(xfer); 3067 3068 xhci_device_generic_multi_enter(xfer->endpoint, 3069 xfer->stream_id, xfer); 3070 } 3071 3072 static void 3073 xhci_device_generic_start(struct usb_xfer *xfer) 3074 { 3075 DPRINTF("\n"); 3076 3077 /* try to insert xfer on HW queue */ 3078 xhci_transfer_insert(xfer); 3079 3080 /* try to multi buffer */ 3081 xhci_device_generic_multi_enter(xfer->endpoint, 3082 xfer->stream_id, NULL); 3083 3084 /* add transfer last on interrupt queue */ 3085 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3086 3087 /* start timeout, if any */ 3088 if (xfer->timeout != 0) 3089 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3090 } 3091 3092 static const struct usb_pipe_methods xhci_device_generic_methods = 3093 { 3094 .open = xhci_device_generic_open, 3095 .close = xhci_device_generic_close, 3096 .enter = xhci_device_generic_enter, 3097 .start = xhci_device_generic_start, 3098 }; 3099 3100 /*------------------------------------------------------------------------* 3101 * xhci root HUB support 3102 *------------------------------------------------------------------------* 3103 * Simulate a hardware HUB by handling all the necessary requests. 3104 *------------------------------------------------------------------------*/ 3105 3106 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3107 3108 static const 3109 struct usb_device_descriptor xhci_devd = 3110 { 3111 .bLength = sizeof(xhci_devd), 3112 .bDescriptorType = UDESC_DEVICE, /* type */ 3113 HSETW(.bcdUSB, 0x0300), /* USB version */ 3114 .bDeviceClass = UDCLASS_HUB, /* class */ 3115 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3116 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3117 .bMaxPacketSize = 9, /* max packet size */ 3118 HSETW(.idVendor, 0x0000), /* vendor */ 3119 HSETW(.idProduct, 0x0000), /* product */ 3120 HSETW(.bcdDevice, 0x0100), /* device version */ 3121 .iManufacturer = 1, 3122 .iProduct = 2, 3123 .iSerialNumber = 0, 3124 .bNumConfigurations = 1, /* # of configurations */ 3125 }; 3126 3127 static const 3128 struct xhci_bos_desc xhci_bosd = { 3129 .bosd = { 3130 .bLength = sizeof(xhci_bosd.bosd), 3131 .bDescriptorType = UDESC_BOS, 3132 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3133 .bNumDeviceCaps = 3, 3134 }, 3135 .usb2extd = { 3136 .bLength = sizeof(xhci_bosd.usb2extd), 3137 .bDescriptorType = 1, 3138 .bDevCapabilityType = 2, 3139 .bmAttributes[0] = 2, 3140 }, 3141 .usbdcd = { 3142 .bLength = sizeof(xhci_bosd.usbdcd), 3143 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3144 .bDevCapabilityType = 3, 3145 .bmAttributes = 0, /* XXX */ 3146 HSETW(.wSpeedsSupported, 0x000C), 3147 .bFunctionalitySupport = 8, 3148 .bU1DevExitLat = 255, /* dummy - not used */ 3149 .wU2DevExitLat = { 0x00, 0x08 }, 3150 }, 3151 .cidd = { 3152 .bLength = sizeof(xhci_bosd.cidd), 3153 .bDescriptorType = 1, 3154 .bDevCapabilityType = 4, 3155 .bReserved = 0, 3156 .bContainerID = 0, /* XXX */ 3157 }, 3158 }; 3159 3160 static const 3161 struct xhci_config_desc xhci_confd = { 3162 .confd = { 3163 .bLength = sizeof(xhci_confd.confd), 3164 .bDescriptorType = UDESC_CONFIG, 3165 .wTotalLength[0] = sizeof(xhci_confd), 3166 .bNumInterface = 1, 3167 .bConfigurationValue = 1, 3168 .iConfiguration = 0, 3169 .bmAttributes = UC_SELF_POWERED, 3170 .bMaxPower = 0 /* max power */ 3171 }, 3172 .ifcd = { 3173 .bLength = sizeof(xhci_confd.ifcd), 3174 .bDescriptorType = UDESC_INTERFACE, 3175 .bNumEndpoints = 1, 3176 .bInterfaceClass = UICLASS_HUB, 3177 .bInterfaceSubClass = UISUBCLASS_HUB, 3178 .bInterfaceProtocol = 0, 3179 }, 3180 .endpd = { 3181 .bLength = sizeof(xhci_confd.endpd), 3182 .bDescriptorType = UDESC_ENDPOINT, 3183 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3184 .bmAttributes = UE_INTERRUPT, 3185 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3186 .bInterval = 255, 3187 }, 3188 .endpcd = { 3189 .bLength = sizeof(xhci_confd.endpcd), 3190 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3191 .bMaxBurst = 0, 3192 .bmAttributes = 0, 3193 }, 3194 }; 3195 3196 static const 3197 struct usb_hub_ss_descriptor xhci_hubd = { 3198 .bLength = sizeof(xhci_hubd), 3199 .bDescriptorType = UDESC_SS_HUB, 3200 }; 3201 3202 static usb_error_t 3203 xhci_roothub_exec(struct usb_device *udev, 3204 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3205 { 3206 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3207 const char *str_ptr; 3208 const void *ptr; 3209 uint32_t port; 3210 uint32_t v; 3211 uint16_t len; 3212 uint16_t i; 3213 uint16_t value; 3214 uint16_t index; 3215 uint8_t j; 3216 usb_error_t err; 3217 3218 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3219 3220 /* buffer reset */ 3221 ptr = (const void *)&sc->sc_hub_desc; 3222 len = 0; 3223 err = 0; 3224 3225 value = UGETW(req->wValue); 3226 index = UGETW(req->wIndex); 3227 3228 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3229 "wValue=0x%04x wIndex=0x%04x\n", 3230 req->bmRequestType, req->bRequest, 3231 UGETW(req->wLength), value, index); 3232 3233 #define C(x,y) ((x) | ((y) << 8)) 3234 switch (C(req->bRequest, req->bmRequestType)) { 3235 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3236 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3237 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3238 /* 3239 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3240 * for the integrated root hub. 3241 */ 3242 break; 3243 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3244 len = 1; 3245 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3246 break; 3247 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3248 switch (value >> 8) { 3249 case UDESC_DEVICE: 3250 if ((value & 0xff) != 0) { 3251 err = USB_ERR_IOERROR; 3252 goto done; 3253 } 3254 len = sizeof(xhci_devd); 3255 ptr = (const void *)&xhci_devd; 3256 break; 3257 3258 case UDESC_BOS: 3259 if ((value & 0xff) != 0) { 3260 err = USB_ERR_IOERROR; 3261 goto done; 3262 } 3263 len = sizeof(xhci_bosd); 3264 ptr = (const void *)&xhci_bosd; 3265 break; 3266 3267 case UDESC_CONFIG: 3268 if ((value & 0xff) != 0) { 3269 err = USB_ERR_IOERROR; 3270 goto done; 3271 } 3272 len = sizeof(xhci_confd); 3273 ptr = (const void *)&xhci_confd; 3274 break; 3275 3276 case UDESC_STRING: 3277 switch (value & 0xff) { 3278 case 0: /* Language table */ 3279 str_ptr = "\001"; 3280 break; 3281 3282 case 1: /* Vendor */ 3283 str_ptr = sc->sc_vendor; 3284 break; 3285 3286 case 2: /* Product */ 3287 str_ptr = "XHCI root HUB"; 3288 break; 3289 3290 default: 3291 str_ptr = ""; 3292 break; 3293 } 3294 3295 len = usb_make_str_desc( 3296 sc->sc_hub_desc.temp, 3297 sizeof(sc->sc_hub_desc.temp), 3298 str_ptr); 3299 break; 3300 3301 default: 3302 err = USB_ERR_IOERROR; 3303 goto done; 3304 } 3305 break; 3306 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3307 len = 1; 3308 sc->sc_hub_desc.temp[0] = 0; 3309 break; 3310 case C(UR_GET_STATUS, UT_READ_DEVICE): 3311 len = 2; 3312 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3313 break; 3314 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3315 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3316 len = 2; 3317 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3318 break; 3319 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3320 if (value >= XHCI_MAX_DEVICES) { 3321 err = USB_ERR_IOERROR; 3322 goto done; 3323 } 3324 break; 3325 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3326 if (value != 0 && value != 1) { 3327 err = USB_ERR_IOERROR; 3328 goto done; 3329 } 3330 sc->sc_conf = value; 3331 break; 3332 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3333 break; 3334 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3335 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3336 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3337 err = USB_ERR_IOERROR; 3338 goto done; 3339 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3340 break; 3341 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3342 break; 3343 /* Hub requests */ 3344 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3345 break; 3346 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3347 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3348 3349 if ((index < 1) || 3350 (index > sc->sc_noport)) { 3351 err = USB_ERR_IOERROR; 3352 goto done; 3353 } 3354 port = XHCI_PORTSC(index); 3355 3356 v = XREAD4(sc, oper, port); 3357 i = XHCI_PS_PLS_GET(v); 3358 v &= ~XHCI_PS_CLEAR; 3359 3360 switch (value) { 3361 case UHF_C_BH_PORT_RESET: 3362 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3363 break; 3364 case UHF_C_PORT_CONFIG_ERROR: 3365 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3366 break; 3367 case UHF_C_PORT_SUSPEND: 3368 case UHF_C_PORT_LINK_STATE: 3369 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3370 break; 3371 case UHF_C_PORT_CONNECTION: 3372 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3373 break; 3374 case UHF_C_PORT_ENABLE: 3375 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3376 break; 3377 case UHF_C_PORT_OVER_CURRENT: 3378 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3379 break; 3380 case UHF_C_PORT_RESET: 3381 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3382 break; 3383 case UHF_PORT_ENABLE: 3384 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3385 break; 3386 case UHF_PORT_POWER: 3387 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3388 break; 3389 case UHF_PORT_INDICATOR: 3390 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3391 break; 3392 case UHF_PORT_SUSPEND: 3393 3394 /* U3 -> U15 */ 3395 if (i == 3) { 3396 XWRITE4(sc, oper, port, v | 3397 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3398 } 3399 3400 /* wait 20ms for resume sequence to complete */ 3401 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3402 3403 /* U0 */ 3404 XWRITE4(sc, oper, port, v | 3405 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3406 break; 3407 default: 3408 err = USB_ERR_IOERROR; 3409 goto done; 3410 } 3411 break; 3412 3413 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3414 if ((value & 0xff) != 0) { 3415 err = USB_ERR_IOERROR; 3416 goto done; 3417 } 3418 3419 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3420 3421 sc->sc_hub_desc.hubd = xhci_hubd; 3422 3423 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3424 3425 if (XHCI_HCS0_PPC(v)) 3426 i = UHD_PWR_INDIVIDUAL; 3427 else 3428 i = UHD_PWR_GANGED; 3429 3430 if (XHCI_HCS0_PIND(v)) 3431 i |= UHD_PORT_IND; 3432 3433 i |= UHD_OC_INDIVIDUAL; 3434 3435 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3436 3437 /* see XHCI section 5.4.9: */ 3438 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3439 3440 for (j = 1; j <= sc->sc_noport; j++) { 3441 3442 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3443 if (v & XHCI_PS_DR) { 3444 sc->sc_hub_desc.hubd. 3445 DeviceRemovable[j / 8] |= 1U << (j % 8); 3446 } 3447 } 3448 len = sc->sc_hub_desc.hubd.bLength; 3449 break; 3450 3451 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3452 len = 16; 3453 memset(sc->sc_hub_desc.temp, 0, 16); 3454 break; 3455 3456 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3457 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3458 3459 if ((index < 1) || 3460 (index > sc->sc_noport)) { 3461 err = USB_ERR_IOERROR; 3462 goto done; 3463 } 3464 3465 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3466 3467 DPRINTFN(9, "port status=0x%08x\n", v); 3468 3469 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3470 3471 switch (XHCI_PS_SPEED_GET(v)) { 3472 case 3: 3473 i |= UPS_HIGH_SPEED; 3474 break; 3475 case 2: 3476 i |= UPS_LOW_SPEED; 3477 break; 3478 case 1: 3479 /* FULL speed */ 3480 break; 3481 default: 3482 i |= UPS_OTHER_SPEED; 3483 break; 3484 } 3485 3486 if (v & XHCI_PS_CCS) 3487 i |= UPS_CURRENT_CONNECT_STATUS; 3488 if (v & XHCI_PS_PED) 3489 i |= UPS_PORT_ENABLED; 3490 if (v & XHCI_PS_OCA) 3491 i |= UPS_OVERCURRENT_INDICATOR; 3492 if (v & XHCI_PS_PR) 3493 i |= UPS_RESET; 3494 if (v & XHCI_PS_PP) { 3495 /* 3496 * The USB 3.0 RH is using the 3497 * USB 2.0's power bit 3498 */ 3499 i |= UPS_PORT_POWER; 3500 } 3501 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3502 3503 i = 0; 3504 if (v & XHCI_PS_CSC) 3505 i |= UPS_C_CONNECT_STATUS; 3506 if (v & XHCI_PS_PEC) 3507 i |= UPS_C_PORT_ENABLED; 3508 if (v & XHCI_PS_OCC) 3509 i |= UPS_C_OVERCURRENT_INDICATOR; 3510 if (v & XHCI_PS_WRC) 3511 i |= UPS_C_BH_PORT_RESET; 3512 if (v & XHCI_PS_PRC) 3513 i |= UPS_C_PORT_RESET; 3514 if (v & XHCI_PS_PLC) 3515 i |= UPS_C_PORT_LINK_STATE; 3516 if (v & XHCI_PS_CEC) 3517 i |= UPS_C_PORT_CONFIG_ERROR; 3518 3519 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3520 len = sizeof(sc->sc_hub_desc.ps); 3521 break; 3522 3523 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3524 err = USB_ERR_IOERROR; 3525 goto done; 3526 3527 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3528 break; 3529 3530 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3531 3532 i = index >> 8; 3533 index &= 0x00FF; 3534 3535 if ((index < 1) || 3536 (index > sc->sc_noport)) { 3537 err = USB_ERR_IOERROR; 3538 goto done; 3539 } 3540 3541 port = XHCI_PORTSC(index); 3542 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3543 3544 switch (value) { 3545 case UHF_PORT_U1_TIMEOUT: 3546 if (XHCI_PS_SPEED_GET(v) != 4) { 3547 err = USB_ERR_IOERROR; 3548 goto done; 3549 } 3550 port = XHCI_PORTPMSC(index); 3551 v = XREAD4(sc, oper, port); 3552 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3553 v |= XHCI_PM3_U1TO_SET(i); 3554 XWRITE4(sc, oper, port, v); 3555 break; 3556 case UHF_PORT_U2_TIMEOUT: 3557 if (XHCI_PS_SPEED_GET(v) != 4) { 3558 err = USB_ERR_IOERROR; 3559 goto done; 3560 } 3561 port = XHCI_PORTPMSC(index); 3562 v = XREAD4(sc, oper, port); 3563 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3564 v |= XHCI_PM3_U2TO_SET(i); 3565 XWRITE4(sc, oper, port, v); 3566 break; 3567 case UHF_BH_PORT_RESET: 3568 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3569 break; 3570 case UHF_PORT_LINK_STATE: 3571 XWRITE4(sc, oper, port, v | 3572 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3573 /* 4ms settle time */ 3574 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3575 break; 3576 case UHF_PORT_ENABLE: 3577 DPRINTFN(3, "set port enable %d\n", index); 3578 break; 3579 case UHF_PORT_SUSPEND: 3580 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3581 j = XHCI_PS_SPEED_GET(v); 3582 if ((j < 1) || (j > 3)) { 3583 /* non-supported speed */ 3584 err = USB_ERR_IOERROR; 3585 goto done; 3586 } 3587 XWRITE4(sc, oper, port, v | 3588 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3589 break; 3590 case UHF_PORT_RESET: 3591 DPRINTFN(6, "reset port %d\n", index); 3592 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3593 break; 3594 case UHF_PORT_POWER: 3595 DPRINTFN(3, "set port power %d\n", index); 3596 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3597 break; 3598 case UHF_PORT_TEST: 3599 DPRINTFN(3, "set port test %d\n", index); 3600 break; 3601 case UHF_PORT_INDICATOR: 3602 DPRINTFN(3, "set port indicator %d\n", index); 3603 3604 v &= ~XHCI_PS_PIC_SET(3); 3605 v |= XHCI_PS_PIC_SET(1); 3606 3607 XWRITE4(sc, oper, port, v); 3608 break; 3609 default: 3610 err = USB_ERR_IOERROR; 3611 goto done; 3612 } 3613 break; 3614 3615 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3616 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3617 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3618 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3619 break; 3620 default: 3621 err = USB_ERR_IOERROR; 3622 goto done; 3623 } 3624 done: 3625 *plength = len; 3626 *pptr = ptr; 3627 return (err); 3628 } 3629 3630 static void 3631 xhci_xfer_setup(struct usb_setup_params *parm) 3632 { 3633 struct usb_page_search page_info; 3634 struct usb_page_cache *pc; 3635 struct xhci_softc *sc; 3636 struct usb_xfer *xfer; 3637 void *last_obj; 3638 uint32_t ntd; 3639 uint32_t n; 3640 3641 sc = XHCI_BUS2SC(parm->udev->bus); 3642 xfer = parm->curr_xfer; 3643 3644 /* 3645 * The proof for the "ntd" formula is illustrated like this: 3646 * 3647 * +------------------------------------+ 3648 * | | 3649 * | |remainder -> | 3650 * | +-----+---+ | 3651 * | | xxx | x | frm 0 | 3652 * | +-----+---++ | 3653 * | | xxx | xx | frm 1 | 3654 * | +-----+----+ | 3655 * | ... | 3656 * +------------------------------------+ 3657 * 3658 * "xxx" means a completely full USB transfer descriptor 3659 * 3660 * "x" and "xx" means a short USB packet 3661 * 3662 * For the remainder of an USB transfer modulo 3663 * "max_data_length" we need two USB transfer descriptors. 3664 * One to transfer the remaining data and one to finalise with 3665 * a zero length packet in case the "force_short_xfer" flag is 3666 * set. We only need two USB transfer descriptors in the case 3667 * where the transfer length of the first one is a factor of 3668 * "max_frame_size". The rest of the needed USB transfer 3669 * descriptors is given by the buffer size divided by the 3670 * maximum data payload. 3671 */ 3672 parm->hc_max_packet_size = 0x400; 3673 parm->hc_max_packet_count = 16 * 3; 3674 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3675 3676 xfer->flags_int.bdma_enable = 1; 3677 3678 usbd_transfer_setup_sub(parm); 3679 3680 if (xfer->flags_int.isochronous_xfr) { 3681 ntd = ((1 * xfer->nframes) 3682 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3683 } else if (xfer->flags_int.control_xfr) { 3684 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3685 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3686 } else { 3687 ntd = ((2 * xfer->nframes) 3688 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3689 } 3690 3691 alloc_dma_set: 3692 3693 if (parm->err) 3694 return; 3695 3696 /* 3697 * Allocate queue heads and transfer descriptors 3698 */ 3699 last_obj = NULL; 3700 3701 if (usbd_transfer_setup_sub_malloc( 3702 parm, &pc, sizeof(struct xhci_td), 3703 XHCI_TD_ALIGN, ntd)) { 3704 parm->err = USB_ERR_NOMEM; 3705 return; 3706 } 3707 if (parm->buf) { 3708 for (n = 0; n != ntd; n++) { 3709 struct xhci_td *td; 3710 3711 usbd_get_page(pc + n, 0, &page_info); 3712 3713 td = page_info.buffer; 3714 3715 /* init TD */ 3716 td->td_self = page_info.physaddr; 3717 td->obj_next = last_obj; 3718 td->page_cache = pc + n; 3719 3720 last_obj = td; 3721 3722 usb_pc_cpu_flush(pc + n); 3723 } 3724 } 3725 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3726 3727 if (!xfer->flags_int.curr_dma_set) { 3728 xfer->flags_int.curr_dma_set = 1; 3729 goto alloc_dma_set; 3730 } 3731 } 3732 3733 static usb_error_t 3734 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3735 { 3736 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3737 struct usb_page_search buf_inp; 3738 struct usb_device *udev; 3739 struct xhci_endpoint_ext *pepext; 3740 struct usb_endpoint_descriptor *edesc; 3741 struct usb_page_cache *pcinp; 3742 usb_error_t err; 3743 usb_stream_t stream_id; 3744 uint8_t index; 3745 uint8_t epno; 3746 3747 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3748 xfer->endpoint->edesc); 3749 3750 udev = xfer->xroot->udev; 3751 index = udev->controller_slot_id; 3752 3753 pcinp = &sc->sc_hw.devs[index].input_pc; 3754 3755 usbd_get_page(pcinp, 0, &buf_inp); 3756 3757 edesc = xfer->endpoint->edesc; 3758 3759 epno = edesc->bEndpointAddress; 3760 stream_id = xfer->stream_id; 3761 3762 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3763 epno |= UE_DIR_IN; 3764 3765 epno = XHCI_EPNO2EPID(epno); 3766 3767 if (epno == 0) 3768 return (USB_ERR_NO_PIPE); /* invalid */ 3769 3770 XHCI_CMD_LOCK(sc); 3771 3772 /* configure endpoint */ 3773 3774 err = xhci_configure_endpoint_by_xfer(xfer); 3775 3776 if (err != 0) { 3777 XHCI_CMD_UNLOCK(sc); 3778 return (err); 3779 } 3780 3781 /* 3782 * Get the endpoint into the stopped state according to the 3783 * endpoint context state diagram in the XHCI specification: 3784 */ 3785 3786 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3787 3788 if (err != 0) 3789 DPRINTF("Could not stop endpoint %u\n", epno); 3790 3791 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3792 3793 if (err != 0) 3794 DPRINTF("Could not reset endpoint %u\n", epno); 3795 3796 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3797 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3798 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3799 stream_id, epno, index); 3800 3801 if (err != 0) 3802 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3803 3804 /* 3805 * Get the endpoint into the running state according to the 3806 * endpoint context state diagram in the XHCI specification: 3807 */ 3808 3809 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3810 3811 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3812 3813 if (err != 0) 3814 DPRINTF("Could not configure endpoint %u\n", epno); 3815 3816 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3817 3818 if (err != 0) 3819 DPRINTF("Could not configure endpoint %u\n", epno); 3820 3821 XHCI_CMD_UNLOCK(sc); 3822 3823 return (0); 3824 } 3825 3826 static void 3827 xhci_xfer_unsetup(struct usb_xfer *xfer) 3828 { 3829 return; 3830 } 3831 3832 static void 3833 xhci_start_dma_delay(struct usb_xfer *xfer) 3834 { 3835 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3836 3837 /* put transfer on interrupt queue (again) */ 3838 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3839 3840 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3841 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3842 } 3843 3844 static void 3845 xhci_configure_msg(struct usb_proc_msg *pm) 3846 { 3847 struct xhci_softc *sc; 3848 struct xhci_endpoint_ext *pepext; 3849 struct usb_xfer *xfer; 3850 3851 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3852 3853 restart: 3854 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3855 3856 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3857 xfer->endpoint->edesc); 3858 3859 if ((pepext->trb_halted != 0) || 3860 (pepext->trb_running == 0)) { 3861 3862 uint16_t i; 3863 3864 /* clear halted and running */ 3865 pepext->trb_halted = 0; 3866 pepext->trb_running = 0; 3867 3868 /* nuke remaining buffered transfers */ 3869 3870 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3871 XHCI_MAX_STREAMS); i++) { 3872 /* 3873 * NOTE: We need to use the timeout 3874 * error code here else existing 3875 * isochronous clients can get 3876 * confused: 3877 */ 3878 if (pepext->xfer[i] != NULL) { 3879 xhci_device_done(pepext->xfer[i], 3880 USB_ERR_TIMEOUT); 3881 } 3882 } 3883 3884 /* 3885 * NOTE: The USB transfer cannot vanish in 3886 * this state! 3887 */ 3888 3889 USB_BUS_UNLOCK(&sc->sc_bus); 3890 3891 xhci_configure_reset_endpoint(xfer); 3892 3893 USB_BUS_LOCK(&sc->sc_bus); 3894 3895 /* check if halted is still cleared */ 3896 if (pepext->trb_halted == 0) { 3897 pepext->trb_running = 1; 3898 memset(pepext->trb_index, 0, 3899 sizeof(pepext->trb_index)); 3900 } 3901 goto restart; 3902 } 3903 3904 if (xfer->flags_int.did_dma_delay) { 3905 3906 /* remove transfer from interrupt queue (again) */ 3907 usbd_transfer_dequeue(xfer); 3908 3909 /* we are finally done */ 3910 usb_dma_delay_done_cb(xfer); 3911 3912 /* queue changed - restart */ 3913 goto restart; 3914 } 3915 } 3916 3917 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3918 3919 /* try to insert xfer on HW queue */ 3920 xhci_transfer_insert(xfer); 3921 3922 /* try to multi buffer */ 3923 xhci_device_generic_multi_enter(xfer->endpoint, 3924 xfer->stream_id, NULL); 3925 } 3926 } 3927 3928 static void 3929 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3930 struct usb_endpoint *ep) 3931 { 3932 struct xhci_endpoint_ext *pepext; 3933 3934 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3935 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3936 3937 if (udev->parent_hub == NULL) { 3938 /* root HUB has special endpoint handling */ 3939 return; 3940 } 3941 3942 ep->methods = &xhci_device_generic_methods; 3943 3944 pepext = xhci_get_endpoint_ext(udev, edesc); 3945 3946 USB_BUS_LOCK(udev->bus); 3947 pepext->trb_halted = 1; 3948 pepext->trb_running = 0; 3949 USB_BUS_UNLOCK(udev->bus); 3950 } 3951 3952 static void 3953 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3954 { 3955 3956 } 3957 3958 static void 3959 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3960 { 3961 struct xhci_endpoint_ext *pepext; 3962 3963 DPRINTF("\n"); 3964 3965 if (udev->flags.usb_mode != USB_MODE_HOST) { 3966 /* not supported */ 3967 return; 3968 } 3969 if (udev->parent_hub == NULL) { 3970 /* root HUB has special endpoint handling */ 3971 return; 3972 } 3973 3974 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3975 3976 USB_BUS_LOCK(udev->bus); 3977 pepext->trb_halted = 1; 3978 pepext->trb_running = 0; 3979 USB_BUS_UNLOCK(udev->bus); 3980 } 3981 3982 static usb_error_t 3983 xhci_device_init(struct usb_device *udev) 3984 { 3985 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3986 usb_error_t err; 3987 uint8_t temp; 3988 3989 /* no init for root HUB */ 3990 if (udev->parent_hub == NULL) 3991 return (0); 3992 3993 XHCI_CMD_LOCK(sc); 3994 3995 /* set invalid default */ 3996 3997 udev->controller_slot_id = sc->sc_noslot + 1; 3998 3999 /* try to get a new slot ID from the XHCI */ 4000 4001 err = xhci_cmd_enable_slot(sc, &temp); 4002 4003 if (err) { 4004 XHCI_CMD_UNLOCK(sc); 4005 return (err); 4006 } 4007 4008 if (temp > sc->sc_noslot) { 4009 XHCI_CMD_UNLOCK(sc); 4010 return (USB_ERR_BAD_ADDRESS); 4011 } 4012 4013 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4014 DPRINTF("slot %u already allocated.\n", temp); 4015 XHCI_CMD_UNLOCK(sc); 4016 return (USB_ERR_BAD_ADDRESS); 4017 } 4018 4019 /* store slot ID for later reference */ 4020 4021 udev->controller_slot_id = temp; 4022 4023 /* reset data structure */ 4024 4025 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4026 4027 /* set mark slot allocated */ 4028 4029 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4030 4031 err = xhci_alloc_device_ext(udev); 4032 4033 XHCI_CMD_UNLOCK(sc); 4034 4035 /* get device into default state */ 4036 4037 if (err == 0) 4038 err = xhci_set_address(udev, NULL, 0); 4039 4040 return (err); 4041 } 4042 4043 static void 4044 xhci_device_uninit(struct usb_device *udev) 4045 { 4046 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4047 uint8_t index; 4048 4049 /* no init for root HUB */ 4050 if (udev->parent_hub == NULL) 4051 return; 4052 4053 XHCI_CMD_LOCK(sc); 4054 4055 index = udev->controller_slot_id; 4056 4057 if (index <= sc->sc_noslot) { 4058 xhci_cmd_disable_slot(sc, index); 4059 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4060 4061 /* free device extension */ 4062 xhci_free_device_ext(udev); 4063 } 4064 4065 XHCI_CMD_UNLOCK(sc); 4066 } 4067 4068 static void 4069 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4070 { 4071 /* 4072 * Wait until the hardware has finished any possible use of 4073 * the transfer descriptor(s) 4074 */ 4075 *pus = 2048; /* microseconds */ 4076 } 4077 4078 static void 4079 xhci_device_resume(struct usb_device *udev) 4080 { 4081 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4082 uint8_t index; 4083 uint8_t n; 4084 uint8_t p; 4085 4086 DPRINTF("\n"); 4087 4088 /* check for root HUB */ 4089 if (udev->parent_hub == NULL) 4090 return; 4091 4092 index = udev->controller_slot_id; 4093 4094 XHCI_CMD_LOCK(sc); 4095 4096 /* blindly resume all endpoints */ 4097 4098 USB_BUS_LOCK(udev->bus); 4099 4100 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4101 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4102 XWRITE4(sc, door, XHCI_DOORBELL(index), 4103 n | XHCI_DB_SID_SET(p)); 4104 } 4105 } 4106 4107 USB_BUS_UNLOCK(udev->bus); 4108 4109 XHCI_CMD_UNLOCK(sc); 4110 } 4111 4112 static void 4113 xhci_device_suspend(struct usb_device *udev) 4114 { 4115 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4116 uint8_t index; 4117 uint8_t n; 4118 usb_error_t err; 4119 4120 DPRINTF("\n"); 4121 4122 /* check for root HUB */ 4123 if (udev->parent_hub == NULL) 4124 return; 4125 4126 index = udev->controller_slot_id; 4127 4128 XHCI_CMD_LOCK(sc); 4129 4130 /* blindly suspend all endpoints */ 4131 4132 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4133 err = xhci_cmd_stop_ep(sc, 1, n, index); 4134 if (err != 0) { 4135 DPRINTF("Failed to suspend endpoint " 4136 "%u on slot %u (ignored).\n", n, index); 4137 } 4138 } 4139 4140 XHCI_CMD_UNLOCK(sc); 4141 } 4142 4143 static void 4144 xhci_set_hw_power(struct usb_bus *bus) 4145 { 4146 DPRINTF("\n"); 4147 } 4148 4149 static void 4150 xhci_device_state_change(struct usb_device *udev) 4151 { 4152 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4153 struct usb_page_search buf_inp; 4154 usb_error_t err; 4155 uint8_t index; 4156 4157 /* check for root HUB */ 4158 if (udev->parent_hub == NULL) 4159 return; 4160 4161 index = udev->controller_slot_id; 4162 4163 DPRINTF("\n"); 4164 4165 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4166 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4167 &sc->sc_hw.devs[index].tt); 4168 if (err != 0) 4169 sc->sc_hw.devs[index].nports = 0; 4170 } 4171 4172 XHCI_CMD_LOCK(sc); 4173 4174 switch (usb_get_device_state(udev)) { 4175 case USB_STATE_POWERED: 4176 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4177 break; 4178 4179 /* set default state */ 4180 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4181 4182 /* reset number of contexts */ 4183 sc->sc_hw.devs[index].context_num = 0; 4184 4185 err = xhci_cmd_reset_dev(sc, index); 4186 4187 if (err != 0) { 4188 DPRINTF("Device reset failed " 4189 "for slot %u.\n", index); 4190 } 4191 break; 4192 4193 case USB_STATE_ADDRESSED: 4194 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4195 break; 4196 4197 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4198 4199 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4200 4201 if (err) { 4202 DPRINTF("Failed to deconfigure " 4203 "slot %u.\n", index); 4204 } 4205 break; 4206 4207 case USB_STATE_CONFIGURED: 4208 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4209 break; 4210 4211 /* set configured state */ 4212 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4213 4214 /* reset number of contexts */ 4215 sc->sc_hw.devs[index].context_num = 0; 4216 4217 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4218 4219 xhci_configure_mask(udev, 3, 0); 4220 4221 err = xhci_configure_device(udev); 4222 if (err != 0) { 4223 DPRINTF("Could not configure device " 4224 "at slot %u.\n", index); 4225 } 4226 4227 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4228 if (err != 0) { 4229 DPRINTF("Could not evaluate device " 4230 "context at slot %u.\n", index); 4231 } 4232 break; 4233 4234 default: 4235 break; 4236 } 4237 XHCI_CMD_UNLOCK(sc); 4238 } 4239 4240 static usb_error_t 4241 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4242 uint8_t ep_mode) 4243 { 4244 switch (ep_mode) { 4245 case USB_EP_MODE_DEFAULT: 4246 return (0); 4247 case USB_EP_MODE_STREAMS: 4248 if (xhcistreams == 0 || 4249 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4250 udev->speed != USB_SPEED_SUPER) 4251 return (USB_ERR_INVAL); 4252 return (0); 4253 default: 4254 return (USB_ERR_INVAL); 4255 } 4256 } 4257 4258 static const struct usb_bus_methods xhci_bus_methods = { 4259 .endpoint_init = xhci_ep_init, 4260 .endpoint_uninit = xhci_ep_uninit, 4261 .xfer_setup = xhci_xfer_setup, 4262 .xfer_unsetup = xhci_xfer_unsetup, 4263 .get_dma_delay = xhci_get_dma_delay, 4264 .device_init = xhci_device_init, 4265 .device_uninit = xhci_device_uninit, 4266 .device_resume = xhci_device_resume, 4267 .device_suspend = xhci_device_suspend, 4268 .set_hw_power = xhci_set_hw_power, 4269 .roothub_exec = xhci_roothub_exec, 4270 .xfer_poll = xhci_do_poll, 4271 .start_dma_delay = xhci_start_dma_delay, 4272 .set_address = xhci_set_address, 4273 .clear_stall = xhci_ep_clear_stall, 4274 .device_state_change = xhci_device_state_change, 4275 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4276 .set_endpoint_mode = xhci_set_endpoint_mode, 4277 }; 4278