1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2010-2022 Hans Petter Selasky 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 31 * 32 * The XHCI 1.0 spec can be found at 33 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 34 * and the USB 3.0 spec at 35 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 36 */ 37 38 /* 39 * A few words about the design implementation: This driver emulates 40 * the concept about TDs which is found in EHCI specification. This 41 * way we achieve that the USB controller drivers look similar to 42 * eachother which makes it easier to understand the code. 43 */ 44 45 #ifdef USB_GLOBAL_INCLUDE_FILE 46 #include USB_GLOBAL_INCLUDE_FILE 47 #else 48 #include <sys/stdint.h> 49 #include <sys/stddef.h> 50 #include <sys/param.h> 51 #include <sys/queue.h> 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/bus.h> 56 #include <sys/module.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/condvar.h> 60 #include <sys/sysctl.h> 61 #include <sys/sx.h> 62 #include <sys/unistd.h> 63 #include <sys/callout.h> 64 #include <sys/malloc.h> 65 #include <sys/priv.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 70 #define USB_DEBUG_VAR xhcidebug 71 72 #include <dev/usb/usb_core.h> 73 #include <dev/usb/usb_debug.h> 74 #include <dev/usb/usb_busdma.h> 75 #include <dev/usb/usb_process.h> 76 #include <dev/usb/usb_transfer.h> 77 #include <dev/usb/usb_device.h> 78 #include <dev/usb/usb_hub.h> 79 #include <dev/usb/usb_util.h> 80 81 #include <dev/usb/usb_controller.h> 82 #include <dev/usb/usb_bus.h> 83 #endif /* USB_GLOBAL_INCLUDE_FILE */ 84 85 #include <dev/usb/controller/xhci.h> 86 #include <dev/usb/controller/xhcireg.h> 87 88 #define XHCI_BUS2SC(bus) \ 89 __containerof(bus, struct xhci_softc, sc_bus) 90 91 #define XHCI_GET_CTX(sc, which, field, ptr) \ 92 ((sc)->sc_ctx_is_64_byte ? \ 93 &((struct which##64 *)(ptr))->field.ctx : \ 94 &((struct which *)(ptr))->field) 95 96 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 97 "USB XHCI"); 98 99 static int xhcistreams; 100 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN, 101 &xhcistreams, 0, "Set to enable streams mode support"); 102 103 static int xhcictlquirk = 1; 104 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlquirk, CTLFLAG_RWTUN, 105 &xhcictlquirk, 0, "Set to enable control endpoint quirk"); 106 107 static int xhcidcepquirk; 108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dcepquirk, CTLFLAG_RWTUN, 109 &xhcidcepquirk, 0, "Set to disable endpoint deconfigure command"); 110 111 #ifdef USB_DEBUG 112 static int xhcidebug; 113 static int xhciroute; 114 static int xhcipolling; 115 static int xhcidma32; 116 static int xhcictlstep; 117 118 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN, 119 &xhcidebug, 0, "Debug level"); 120 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN, 121 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller"); 122 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN, 123 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller"); 124 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN, 125 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller"); 126 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN, 127 &xhcictlstep, 0, "Set to enable control endpoint status stage stepping"); 128 #else 129 #define xhciroute 0 130 #define xhcidma32 0 131 #define xhcictlstep 0 132 #endif 133 134 #define XHCI_INTR_ENDPT 1 135 136 struct xhci_std_temp { 137 struct xhci_softc *sc; 138 struct usb_page_cache *pc; 139 struct xhci_td *td; 140 struct xhci_td *td_next; 141 uint32_t len; 142 uint32_t offset; 143 uint32_t max_packet_size; 144 uint32_t average; 145 uint32_t isoc_frame; 146 uint16_t isoc_delta; 147 uint8_t shortpkt; 148 uint8_t multishort; 149 uint8_t last_frame; 150 uint8_t trb_type; 151 uint8_t direction; 152 uint8_t tbc; 153 uint8_t tlbpc; 154 uint8_t step_td; 155 uint8_t do_isoc_sync; 156 }; 157 158 static void xhci_do_poll(struct usb_bus *); 159 static void xhci_device_done(struct usb_xfer *, usb_error_t); 160 static void xhci_root_intr(struct xhci_softc *); 161 static void xhci_free_device_ext(struct usb_device *); 162 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 163 struct usb_endpoint_descriptor *); 164 static usb_proc_callback_t xhci_configure_msg; 165 static usb_error_t xhci_configure_device(struct usb_device *); 166 static usb_error_t xhci_configure_endpoint(struct usb_device *, 167 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 168 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 169 uint8_t); 170 static usb_error_t xhci_configure_mask(struct usb_device *, 171 uint32_t, uint8_t); 172 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 173 uint64_t, uint8_t); 174 static void xhci_endpoint_doorbell(struct usb_xfer *); 175 176 static const struct usb_bus_methods xhci_bus_methods; 177 178 #ifdef USB_DEBUG 179 static void 180 xhci_dump_trb(struct xhci_trb *trb) 181 { 182 DPRINTFN(5, "trb = %p\n", trb); 183 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 184 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 185 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 186 } 187 188 static void 189 xhci_dump_endpoint(struct xhci_endp_ctx *pep) 190 { 191 DPRINTFN(5, "pep = %p\n", pep); 192 DPRINTFN(5, "dwEpCtx0=0x%08x\n", le32toh(pep->dwEpCtx0)); 193 DPRINTFN(5, "dwEpCtx1=0x%08x\n", le32toh(pep->dwEpCtx1)); 194 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)le64toh(pep->qwEpCtx2)); 195 DPRINTFN(5, "dwEpCtx4=0x%08x\n", le32toh(pep->dwEpCtx4)); 196 DPRINTFN(5, "dwEpCtx5=0x%08x\n", le32toh(pep->dwEpCtx5)); 197 DPRINTFN(5, "dwEpCtx6=0x%08x\n", le32toh(pep->dwEpCtx6)); 198 DPRINTFN(5, "dwEpCtx7=0x%08x\n", le32toh(pep->dwEpCtx7)); 199 } 200 201 static void 202 xhci_dump_device(struct xhci_slot_ctx *psl) 203 { 204 DPRINTFN(5, "psl = %p\n", psl); 205 DPRINTFN(5, "dwSctx0=0x%08x\n", le32toh(psl->dwSctx0)); 206 DPRINTFN(5, "dwSctx1=0x%08x\n", le32toh(psl->dwSctx1)); 207 DPRINTFN(5, "dwSctx2=0x%08x\n", le32toh(psl->dwSctx2)); 208 DPRINTFN(5, "dwSctx3=0x%08x\n", le32toh(psl->dwSctx3)); 209 } 210 #endif 211 212 uint8_t 213 xhci_use_polling(void) 214 { 215 #ifdef USB_DEBUG 216 return (xhcipolling != 0); 217 #else 218 return (0); 219 #endif 220 } 221 222 static void 223 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 224 { 225 struct xhci_softc *sc = XHCI_BUS2SC(bus); 226 uint16_t i; 227 228 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 229 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 230 231 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 232 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 233 234 for (i = 0; i != sc->sc_noscratch; i++) { 235 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 236 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 237 } 238 } 239 240 static int 241 xhci_reset_command_queue_locked(struct xhci_softc *sc) 242 { 243 struct usb_page_search buf_res; 244 struct xhci_hw_root *phwr; 245 uint64_t addr; 246 uint32_t temp; 247 248 DPRINTF("\n"); 249 250 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 251 if (temp & XHCI_CRCR_LO_CRR) { 252 DPRINTF("Command ring running\n"); 253 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 254 255 /* 256 * Try to abort the last command as per section 257 * 4.6.1.2 "Aborting a Command" of the XHCI 258 * specification: 259 */ 260 261 /* stop and cancel */ 262 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 263 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 264 265 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 266 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 267 268 /* wait 250ms */ 269 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 270 271 /* check if command ring is still running */ 272 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 273 if (temp & XHCI_CRCR_LO_CRR) { 274 DPRINTF("Comand ring still running\n"); 275 return (USB_ERR_IOERROR); 276 } 277 } 278 279 /* reset command ring */ 280 sc->sc_command_ccs = 1; 281 sc->sc_command_idx = 0; 282 283 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 284 285 /* set up command ring control base address */ 286 addr = buf_res.physaddr; 287 phwr = buf_res.buffer; 288 addr += __offsetof(struct xhci_hw_root, hwr_commands[0]); 289 290 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 291 292 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 293 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 294 295 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 296 297 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 298 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 299 300 return (0); 301 } 302 303 usb_error_t 304 xhci_start_controller(struct xhci_softc *sc) 305 { 306 struct usb_page_search buf_res; 307 struct xhci_hw_root *phwr; 308 struct xhci_dev_ctx_addr *pdctxa; 309 usb_error_t err; 310 uint64_t addr; 311 uint32_t temp; 312 uint16_t i; 313 314 DPRINTF("\n"); 315 316 sc->sc_event_ccs = 1; 317 sc->sc_event_idx = 0; 318 sc->sc_command_ccs = 1; 319 sc->sc_command_idx = 0; 320 321 err = xhci_reset_controller(sc); 322 if (err) 323 return (err); 324 325 /* set up number of device slots */ 326 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 327 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 328 329 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 330 331 temp = XREAD4(sc, oper, XHCI_USBSTS); 332 333 /* clear interrupts */ 334 XWRITE4(sc, oper, XHCI_USBSTS, temp); 335 /* disable all device notifications */ 336 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 337 338 /* set up device context base address */ 339 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 340 pdctxa = buf_res.buffer; 341 memset(pdctxa, 0, sizeof(*pdctxa)); 342 343 addr = buf_res.physaddr; 344 addr += __offsetof(struct xhci_dev_ctx_addr, qwSpBufPtr[0]); 345 346 /* slot 0 points to the table of scratchpad pointers */ 347 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 348 349 for (i = 0; i != sc->sc_noscratch; i++) { 350 struct usb_page_search buf_scp; 351 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 352 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 353 } 354 355 addr = buf_res.physaddr; 356 357 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 358 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 359 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 360 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 361 362 /* set up event table size */ 363 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 364 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max); 365 366 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max)); 367 368 /* set up interrupt rate */ 369 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 370 371 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 372 373 phwr = buf_res.buffer; 374 addr = buf_res.physaddr; 375 addr += __offsetof(struct xhci_hw_root, hwr_events[0]); 376 377 /* reset hardware root structure */ 378 memset(phwr, 0, sizeof(*phwr)); 379 380 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 381 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 382 383 /* 384 * PR 237666: 385 * 386 * According to the XHCI specification, the XWRITE4's to 387 * XHCI_ERSTBA_LO and _HI lead to the XHCI to copy the 388 * qwEvrsTablePtr and dwEvrsTableSize values above at that 389 * time, as the XHCI initializes its event ring support. This 390 * is before the event ring starts to pay attention to the 391 * RUN/STOP bit. Thus, make sure the values are observable to 392 * the XHCI before that point. 393 */ 394 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 395 396 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 397 398 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 399 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 400 401 addr = buf_res.physaddr; 402 403 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 404 405 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 406 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 407 408 /* set up interrupter registers */ 409 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 410 temp |= XHCI_IMAN_INTR_ENA; 411 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 412 413 /* set up command ring control base address */ 414 addr = buf_res.physaddr; 415 addr += __offsetof(struct xhci_hw_root, hwr_commands[0]); 416 417 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 418 419 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 420 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 421 422 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 423 424 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 425 426 /* Go! */ 427 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 428 XHCI_CMD_INTE | XHCI_CMD_HSEE); 429 430 for (i = 0; i != 100; i++) { 431 usb_pause_mtx(NULL, hz / 100); 432 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 433 if (!temp) 434 break; 435 } 436 if (temp) { 437 XWRITE4(sc, oper, XHCI_USBCMD, 0); 438 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 439 return (USB_ERR_IOERROR); 440 } 441 442 /* catch any lost interrupts */ 443 xhci_do_poll(&sc->sc_bus); 444 445 if (sc->sc_port_route != NULL) { 446 /* Route all ports to the XHCI by default */ 447 sc->sc_port_route(sc->sc_bus.parent, 448 ~xhciroute, xhciroute); 449 } 450 return (0); 451 } 452 453 usb_error_t 454 xhci_halt_controller(struct xhci_softc *sc) 455 { 456 uint32_t temp; 457 uint16_t i; 458 459 DPRINTF("\n"); 460 461 sc->sc_capa_off = 0; 462 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 463 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 464 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 465 466 /* Halt controller */ 467 XWRITE4(sc, oper, XHCI_USBCMD, 0); 468 469 for (i = 0; i != 100; i++) { 470 usb_pause_mtx(NULL, hz / 100); 471 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 472 if (temp) 473 break; 474 } 475 476 if (!temp) { 477 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 478 return (USB_ERR_IOERROR); 479 } 480 return (0); 481 } 482 483 usb_error_t 484 xhci_reset_controller(struct xhci_softc *sc) 485 { 486 uint32_t temp = 0; 487 uint16_t i; 488 489 DPRINTF("\n"); 490 491 /* Reset controller */ 492 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 493 494 for (i = 0; i != 100; i++) { 495 usb_pause_mtx(NULL, hz / 100); 496 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 497 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 498 if (!temp) 499 break; 500 } 501 502 if (temp) { 503 device_printf(sc->sc_bus.parent, "Controller " 504 "reset timeout.\n"); 505 return (USB_ERR_IOERROR); 506 } 507 return (0); 508 } 509 510 usb_error_t 511 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32) 512 { 513 uint32_t temp; 514 515 DPRINTF("\n"); 516 517 /* initialize some bus fields */ 518 sc->sc_bus.parent = self; 519 520 /* set the bus revision */ 521 sc->sc_bus.usbrev = USB_REV_3_0; 522 523 /* set up the bus struct */ 524 sc->sc_bus.methods = &xhci_bus_methods; 525 526 /* set up devices array */ 527 sc->sc_bus.devices = sc->sc_devices; 528 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 529 530 /* set default cycle state in case of early interrupts */ 531 sc->sc_event_ccs = 1; 532 sc->sc_command_ccs = 1; 533 534 /* set up bus space offsets */ 535 sc->sc_capa_off = 0; 536 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 537 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 538 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 539 540 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 541 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 542 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 543 544 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 545 546 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 547 device_printf(sc->sc_bus.parent, "Controller does " 548 "not support 4K page size.\n"); 549 return (ENXIO); 550 } 551 552 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 553 554 DPRINTF("HCS0 = 0x%08x\n", temp); 555 556 /* set up context size */ 557 if (XHCI_HCS0_CSZ(temp)) { 558 sc->sc_ctx_is_64_byte = 1; 559 } else { 560 sc->sc_ctx_is_64_byte = 0; 561 } 562 563 /* get DMA bits */ 564 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && 565 xhcidma32 == 0 && dma32 == 0) ? 64 : 32; 566 567 device_printf(self, "%d bytes context size, %d-bit DMA\n", 568 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); 569 570 /* enable 64Kbyte control endpoint quirk */ 571 sc->sc_bus.control_ep_quirk = (xhcictlquirk ? 1 : 0); 572 573 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 574 575 /* get number of device slots */ 576 sc->sc_noport = XHCI_HCS1_N_PORTS(temp); 577 578 if (sc->sc_noport == 0) { 579 device_printf(sc->sc_bus.parent, "Invalid number " 580 "of ports: %u\n", sc->sc_noport); 581 return (ENXIO); 582 } 583 584 sc->sc_noport = sc->sc_noport; 585 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 586 587 DPRINTF("Max slots: %u\n", sc->sc_noslot); 588 589 if (sc->sc_noslot > XHCI_MAX_DEVICES) 590 sc->sc_noslot = XHCI_MAX_DEVICES; 591 592 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 593 594 DPRINTF("HCS2=0x%08x\n", temp); 595 596 /* get isochronous scheduling threshold */ 597 sc->sc_ist = XHCI_HCS2_IST(temp); 598 599 /* get number of scratchpads */ 600 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 601 602 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 603 device_printf(sc->sc_bus.parent, "XHCI request " 604 "too many scratchpads\n"); 605 return (ENOMEM); 606 } 607 608 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 609 610 /* get event table size */ 611 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); 612 if (sc->sc_erst_max > XHCI_MAX_RSEG) 613 sc->sc_erst_max = XHCI_MAX_RSEG; 614 615 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 616 617 /* get maximum exit latency */ 618 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 619 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 620 621 /* Check if we should use the default IMOD value. */ 622 if (sc->sc_imod_default == 0) 623 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 624 625 /* get all DMA memory */ 626 if (usb_bus_mem_alloc_all(&sc->sc_bus, 627 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 628 return (ENOMEM); 629 } 630 631 /* set up command queue mutex and condition varible */ 632 cv_init(&sc->sc_cmd_cv, "CMDQ"); 633 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 634 635 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 636 sc->sc_config_msg[0].bus = &sc->sc_bus; 637 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 638 sc->sc_config_msg[1].bus = &sc->sc_bus; 639 640 return (0); 641 } 642 643 void 644 xhci_uninit(struct xhci_softc *sc) 645 { 646 /* 647 * NOTE: At this point the control transfer process is gone 648 * and "xhci_configure_msg" is no longer called. Consequently 649 * waiting for the configuration messages to complete is not 650 * needed. 651 */ 652 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 653 654 cv_destroy(&sc->sc_cmd_cv); 655 sx_destroy(&sc->sc_cmd_sx); 656 } 657 658 static void 659 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 660 { 661 struct xhci_softc *sc = XHCI_BUS2SC(bus); 662 663 switch (state) { 664 case USB_HW_POWER_SUSPEND: 665 DPRINTF("Stopping the XHCI\n"); 666 xhci_halt_controller(sc); 667 xhci_reset_controller(sc); 668 break; 669 case USB_HW_POWER_SHUTDOWN: 670 DPRINTF("Stopping the XHCI\n"); 671 xhci_halt_controller(sc); 672 xhci_reset_controller(sc); 673 break; 674 case USB_HW_POWER_RESUME: 675 DPRINTF("Starting the XHCI\n"); 676 xhci_start_controller(sc); 677 break; 678 default: 679 break; 680 } 681 } 682 683 static usb_error_t 684 xhci_generic_done_sub(struct usb_xfer *xfer) 685 { 686 struct xhci_td *td; 687 struct xhci_td *td_alt_next; 688 uint32_t len; 689 uint8_t status; 690 691 td = xfer->td_transfer_cache; 692 td_alt_next = td->alt_next; 693 694 if (xfer->aframes != xfer->nframes) 695 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 696 697 while (1) { 698 usb_pc_cpu_invalidate(td->page_cache); 699 700 status = td->status; 701 len = td->remainder; 702 703 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 704 xfer, (unsigned int)xfer->aframes, 705 (unsigned int)xfer->nframes, 706 (unsigned int)len, (unsigned int)td->len, 707 (unsigned int)status); 708 709 /* 710 * Verify the status length and 711 * add the length to "frlengths[]": 712 */ 713 if (len > td->len) { 714 /* should not happen */ 715 DPRINTF("Invalid status length, " 716 "0x%04x/0x%04x bytes\n", len, td->len); 717 status = XHCI_TRB_ERROR_LENGTH; 718 } else if (xfer->aframes != xfer->nframes) { 719 xfer->frlengths[xfer->aframes] += td->len - len; 720 } 721 /* Check for last transfer */ 722 if (((void *)td) == xfer->td_transfer_last) { 723 td = NULL; 724 break; 725 } 726 /* Check for transfer error */ 727 if (status != XHCI_TRB_ERROR_SHORT_PKT && 728 status != XHCI_TRB_ERROR_SUCCESS) { 729 /* the transfer is finished */ 730 td = NULL; 731 break; 732 } 733 /* Check for short transfer */ 734 if (len > 0) { 735 if (xfer->flags_int.short_frames_ok || 736 xfer->flags_int.isochronous_xfr || 737 xfer->flags_int.control_xfr) { 738 /* follow alt next */ 739 td = td->alt_next; 740 } else { 741 /* the transfer is finished */ 742 td = NULL; 743 } 744 break; 745 } 746 td = td->obj_next; 747 748 if (td->alt_next != td_alt_next) { 749 /* this USB frame is complete */ 750 break; 751 } 752 } 753 754 /* update transfer cache */ 755 756 xfer->td_transfer_cache = td; 757 758 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 759 (status != XHCI_TRB_ERROR_SHORT_PKT && 760 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 761 USB_ERR_NORMAL_COMPLETION); 762 } 763 764 static void 765 xhci_generic_done(struct usb_xfer *xfer) 766 { 767 usb_error_t err = 0; 768 769 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 770 xfer, xfer->endpoint); 771 772 /* reset scanner */ 773 774 xfer->td_transfer_cache = xfer->td_transfer_first; 775 776 if (xfer->flags_int.control_xfr) { 777 if (xfer->flags_int.control_hdr) 778 err = xhci_generic_done_sub(xfer); 779 780 xfer->aframes = 1; 781 782 if (xfer->td_transfer_cache == NULL) 783 goto done; 784 } 785 786 while (xfer->aframes != xfer->nframes) { 787 err = xhci_generic_done_sub(xfer); 788 xfer->aframes++; 789 790 if (xfer->td_transfer_cache == NULL) 791 goto done; 792 } 793 794 if (xfer->flags_int.control_xfr && 795 !xfer->flags_int.control_act) 796 err = xhci_generic_done_sub(xfer); 797 done: 798 /* transfer is complete */ 799 xhci_device_done(xfer, err); 800 } 801 802 static void 803 xhci_activate_transfer(struct usb_xfer *xfer) 804 { 805 struct xhci_td *td; 806 807 td = xfer->td_transfer_cache; 808 809 usb_pc_cpu_invalidate(td->page_cache); 810 811 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 812 /* activate the transfer */ 813 814 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 815 usb_pc_cpu_flush(td->page_cache); 816 817 xhci_endpoint_doorbell(xfer); 818 } 819 } 820 821 static void 822 xhci_skip_transfer(struct usb_xfer *xfer) 823 { 824 struct xhci_td *td; 825 struct xhci_td *td_last; 826 827 td = xfer->td_transfer_cache; 828 td_last = xfer->td_transfer_last; 829 830 td = td->alt_next; 831 832 usb_pc_cpu_invalidate(td->page_cache); 833 834 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 835 usb_pc_cpu_invalidate(td_last->page_cache); 836 837 /* copy LINK TRB to current waiting location */ 838 839 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 840 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 841 usb_pc_cpu_flush(td->page_cache); 842 843 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 844 usb_pc_cpu_flush(td->page_cache); 845 846 xhci_endpoint_doorbell(xfer); 847 } 848 } 849 850 /*------------------------------------------------------------------------* 851 * xhci_check_transfer 852 *------------------------------------------------------------------------*/ 853 static void 854 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 855 { 856 struct xhci_endpoint_ext *pepext; 857 int64_t offset; 858 uint64_t td_event; 859 uint32_t temp; 860 uint32_t remainder; 861 uint16_t stream_id = 0; 862 uint16_t i; 863 uint8_t status; 864 uint8_t halted; 865 uint8_t epno; 866 uint8_t index; 867 868 /* decode TRB */ 869 td_event = le64toh(trb->qwTrb0); 870 temp = le32toh(trb->dwTrb2); 871 872 remainder = XHCI_TRB_2_REM_GET(temp); 873 status = XHCI_TRB_2_ERROR_GET(temp); 874 875 temp = le32toh(trb->dwTrb3); 876 epno = XHCI_TRB_3_EP_GET(temp); 877 index = XHCI_TRB_3_SLOT_GET(temp); 878 879 /* check if error means halted */ 880 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 881 status != XHCI_TRB_ERROR_SUCCESS); 882 883 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 884 index, epno, remainder, status); 885 886 if (index > sc->sc_noslot) { 887 DPRINTF("Invalid slot.\n"); 888 return; 889 } 890 891 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 892 DPRINTF("Invalid endpoint.\n"); 893 return; 894 } 895 896 pepext = &sc->sc_hw.devs[index].endp[epno]; 897 898 /* try to find the USB transfer that generated the event */ 899 for (i = 0;; i++) { 900 struct usb_xfer *xfer; 901 struct xhci_td *td; 902 903 if (i == (XHCI_MAX_TRANSFERS - 1)) { 904 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS || 905 stream_id == (XHCI_MAX_STREAMS - 1)) 906 break; 907 stream_id++; 908 i = 0; 909 DPRINTFN(5, "stream_id=%u\n", stream_id); 910 } 911 912 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 913 if (xfer == NULL) 914 continue; 915 916 td = xfer->td_transfer_cache; 917 918 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 919 (long long)td_event, 920 (long long)td->td_self, 921 (long long)td->td_self + sizeof(td->td_trb)); 922 923 /* 924 * NOTE: Some XHCI implementations might not trigger 925 * an event on the last LINK TRB so we need to 926 * consider both the last and second last event 927 * address as conditions for a successful transfer. 928 * 929 * NOTE: We assume that the XHCI will only trigger one 930 * event per chain of TRBs. 931 */ 932 933 offset = td_event - td->td_self; 934 935 if (offset >= 0 && 936 offset < (int64_t)sizeof(td->td_trb)) { 937 usb_pc_cpu_invalidate(td->page_cache); 938 939 /* compute rest of remainder, if any */ 940 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 941 temp = le32toh(td->td_trb[i].dwTrb2); 942 remainder += XHCI_TRB_2_BYTES_GET(temp); 943 } 944 945 DPRINTFN(5, "New remainder: %u\n", remainder); 946 947 /* clear isochronous transfer errors */ 948 if (xfer->flags_int.isochronous_xfr) { 949 if (halted) { 950 halted = 0; 951 status = XHCI_TRB_ERROR_SUCCESS; 952 remainder = td->len; 953 } 954 } 955 956 /* "td->remainder" is verified later */ 957 td->remainder = remainder; 958 td->status = status; 959 960 usb_pc_cpu_flush(td->page_cache); 961 962 /* 963 * 1) Last transfer descriptor makes the 964 * transfer done 965 */ 966 if (((void *)td) == xfer->td_transfer_last) { 967 DPRINTF("TD is last\n"); 968 xhci_generic_done(xfer); 969 break; 970 } 971 972 /* 973 * 2) Any kind of error makes the transfer 974 * done 975 */ 976 if (halted) { 977 DPRINTF("TD has I/O error\n"); 978 xhci_generic_done(xfer); 979 break; 980 } 981 982 /* 983 * 3) If there is no alternate next transfer, 984 * a short packet also makes the transfer done 985 */ 986 if (td->remainder > 0) { 987 if (td->alt_next == NULL) { 988 DPRINTF( 989 "short TD has no alternate next\n"); 990 xhci_generic_done(xfer); 991 break; 992 } 993 DPRINTF("TD has short pkt\n"); 994 if (xfer->flags_int.short_frames_ok || 995 xfer->flags_int.isochronous_xfr || 996 xfer->flags_int.control_xfr) { 997 /* follow the alt next */ 998 xfer->td_transfer_cache = td->alt_next; 999 xhci_activate_transfer(xfer); 1000 break; 1001 } 1002 xhci_skip_transfer(xfer); 1003 xhci_generic_done(xfer); 1004 break; 1005 } 1006 1007 /* 1008 * 4) Transfer complete - go to next TD 1009 */ 1010 DPRINTF("Following next TD\n"); 1011 xfer->td_transfer_cache = td->obj_next; 1012 xhci_activate_transfer(xfer); 1013 break; /* there should only be one match */ 1014 } 1015 } 1016 } 1017 1018 static int 1019 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1020 { 1021 if (sc->sc_cmd_addr == trb->qwTrb0) { 1022 DPRINTF("Received command event\n"); 1023 sc->sc_cmd_result[0] = trb->dwTrb2; 1024 sc->sc_cmd_result[1] = trb->dwTrb3; 1025 cv_signal(&sc->sc_cmd_cv); 1026 return (1); /* command match */ 1027 } 1028 return (0); 1029 } 1030 1031 static int 1032 xhci_interrupt_poll(struct xhci_softc *sc) 1033 { 1034 struct usb_page_search buf_res; 1035 struct xhci_hw_root *phwr; 1036 uint64_t addr; 1037 uint32_t temp; 1038 int retval = 0; 1039 uint16_t i; 1040 uint8_t event; 1041 uint8_t j; 1042 uint8_t k; 1043 uint8_t t; 1044 1045 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1046 1047 phwr = buf_res.buffer; 1048 1049 /* Receive any events */ 1050 1051 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1052 1053 i = sc->sc_event_idx; 1054 j = sc->sc_event_ccs; 1055 t = 2; 1056 1057 while (1) { 1058 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1059 1060 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1061 1062 if (j != k) 1063 break; 1064 1065 event = XHCI_TRB_3_TYPE_GET(temp); 1066 1067 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1068 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1069 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1070 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1071 1072 switch (event) { 1073 case XHCI_TRB_EVENT_TRANSFER: 1074 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1075 break; 1076 case XHCI_TRB_EVENT_CMD_COMPLETE: 1077 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1078 break; 1079 default: 1080 DPRINTF("Unhandled event = %u\n", event); 1081 break; 1082 } 1083 1084 i++; 1085 1086 if (i == XHCI_MAX_EVENTS) { 1087 i = 0; 1088 j ^= 1; 1089 1090 /* check for timeout */ 1091 if (!--t) 1092 break; 1093 } 1094 } 1095 1096 sc->sc_event_idx = i; 1097 sc->sc_event_ccs = j; 1098 1099 /* 1100 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1101 * latched. That means to activate the register we need to 1102 * write both the low and high double word of the 64-bit 1103 * register. 1104 */ 1105 1106 addr = buf_res.physaddr; 1107 addr += __offsetof(struct xhci_hw_root, hwr_events[i]); 1108 1109 /* try to clear busy bit */ 1110 addr |= XHCI_ERDP_LO_BUSY; 1111 1112 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1113 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1114 1115 return (retval); 1116 } 1117 1118 static usb_error_t 1119 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1120 uint16_t timeout_ms) 1121 { 1122 struct usb_page_search buf_res; 1123 struct xhci_hw_root *phwr; 1124 uint64_t addr; 1125 uint32_t temp; 1126 uint8_t i; 1127 uint8_t j; 1128 uint8_t timeout = 0; 1129 int err; 1130 1131 XHCI_CMD_ASSERT_LOCKED(sc); 1132 1133 /* get hardware root structure */ 1134 1135 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1136 1137 phwr = buf_res.buffer; 1138 1139 /* Queue command */ 1140 1141 USB_BUS_LOCK(&sc->sc_bus); 1142 retry: 1143 i = sc->sc_command_idx; 1144 j = sc->sc_command_ccs; 1145 1146 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1147 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1148 (long long)le64toh(trb->qwTrb0), 1149 (long)le32toh(trb->dwTrb2), 1150 (long)le32toh(trb->dwTrb3)); 1151 1152 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1153 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1154 1155 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1156 1157 temp = trb->dwTrb3; 1158 1159 if (j) 1160 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1161 else 1162 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1163 1164 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1165 1166 phwr->hwr_commands[i].dwTrb3 = temp; 1167 1168 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1169 1170 addr = buf_res.physaddr; 1171 addr += __offsetof(struct xhci_hw_root, hwr_commands[i]); 1172 1173 sc->sc_cmd_addr = htole64(addr); 1174 1175 i++; 1176 1177 if (i == (XHCI_MAX_COMMANDS - 1)) { 1178 if (j) { 1179 temp = htole32(XHCI_TRB_3_TC_BIT | 1180 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1181 XHCI_TRB_3_CYCLE_BIT); 1182 } else { 1183 temp = htole32(XHCI_TRB_3_TC_BIT | 1184 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1185 } 1186 1187 phwr->hwr_commands[i].dwTrb3 = temp; 1188 1189 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1190 1191 i = 0; 1192 j ^= 1; 1193 } 1194 1195 sc->sc_command_idx = i; 1196 sc->sc_command_ccs = j; 1197 1198 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1199 1200 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1201 USB_MS_TO_TICKS(timeout_ms)); 1202 1203 /* 1204 * In some error cases event interrupts are not generated. 1205 * Poll one time to see if the command has completed. 1206 */ 1207 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1208 DPRINTF("Command was completed when polling\n"); 1209 err = 0; 1210 } 1211 if (err != 0) { 1212 DPRINTF("Command timeout!\n"); 1213 /* 1214 * After some weeks of continuous operation, it has 1215 * been observed that the ASMedia Technology, ASM1042 1216 * SuperSpeed USB Host Controller can suddenly stop 1217 * accepting commands via the command queue. Try to 1218 * first reset the command queue. If that fails do a 1219 * host controller reset. 1220 */ 1221 if (timeout == 0 && 1222 xhci_reset_command_queue_locked(sc) == 0) { 1223 temp = le32toh(trb->dwTrb3); 1224 1225 /* 1226 * Avoid infinite XHCI reset loops if the set 1227 * address command fails to respond due to a 1228 * non-enumerating device: 1229 */ 1230 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1231 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1232 DPRINTF("Set address timeout\n"); 1233 } else { 1234 timeout = 1; 1235 goto retry; 1236 } 1237 } else { 1238 DPRINTF("Controller reset!\n"); 1239 usb_bus_reset_async_locked(&sc->sc_bus); 1240 } 1241 err = USB_ERR_TIMEOUT; 1242 trb->dwTrb2 = 0; 1243 trb->dwTrb3 = 0; 1244 } else { 1245 temp = le32toh(sc->sc_cmd_result[0]); 1246 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1247 err = USB_ERR_IOERROR; 1248 1249 trb->dwTrb2 = sc->sc_cmd_result[0]; 1250 trb->dwTrb3 = sc->sc_cmd_result[1]; 1251 } 1252 1253 USB_BUS_UNLOCK(&sc->sc_bus); 1254 1255 return (err); 1256 } 1257 1258 #if 0 1259 static usb_error_t 1260 xhci_cmd_nop(struct xhci_softc *sc) 1261 { 1262 struct xhci_trb trb; 1263 uint32_t temp; 1264 1265 DPRINTF("\n"); 1266 1267 trb.qwTrb0 = 0; 1268 trb.dwTrb2 = 0; 1269 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1270 1271 trb.dwTrb3 = htole32(temp); 1272 1273 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1274 } 1275 #endif 1276 1277 static usb_error_t 1278 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1279 { 1280 struct xhci_trb trb; 1281 uint32_t temp; 1282 usb_error_t err; 1283 1284 DPRINTF("\n"); 1285 1286 trb.qwTrb0 = 0; 1287 trb.dwTrb2 = 0; 1288 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1289 1290 err = xhci_do_command(sc, &trb, 100 /* ms */); 1291 if (err) 1292 goto done; 1293 1294 temp = le32toh(trb.dwTrb3); 1295 1296 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1297 1298 done: 1299 return (err); 1300 } 1301 1302 static usb_error_t 1303 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1304 { 1305 struct xhci_trb trb; 1306 uint32_t temp; 1307 1308 DPRINTF("\n"); 1309 1310 trb.qwTrb0 = 0; 1311 trb.dwTrb2 = 0; 1312 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1313 XHCI_TRB_3_SLOT_SET(slot_id); 1314 1315 trb.dwTrb3 = htole32(temp); 1316 1317 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1318 } 1319 1320 static usb_error_t 1321 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1322 uint8_t bsr, uint8_t slot_id) 1323 { 1324 struct xhci_trb trb; 1325 uint32_t temp; 1326 1327 DPRINTF("\n"); 1328 1329 trb.qwTrb0 = htole64(input_ctx); 1330 trb.dwTrb2 = 0; 1331 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1332 XHCI_TRB_3_SLOT_SET(slot_id); 1333 1334 if (bsr) 1335 temp |= XHCI_TRB_3_BSR_BIT; 1336 1337 trb.dwTrb3 = htole32(temp); 1338 1339 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1340 } 1341 1342 static usb_error_t 1343 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1344 { 1345 struct usb_page_search buf_inp; 1346 struct usb_page_search buf_dev; 1347 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1348 struct xhci_hw_dev *hdev; 1349 struct xhci_slot_ctx *slot; 1350 struct xhci_endpoint_ext *pepext; 1351 uint32_t temp; 1352 uint16_t mps; 1353 usb_error_t err; 1354 uint8_t index; 1355 1356 /* the root HUB case is not handled here */ 1357 if (udev->parent_hub == NULL) 1358 return (USB_ERR_INVAL); 1359 1360 index = udev->controller_slot_id; 1361 1362 hdev = &sc->sc_hw.devs[index]; 1363 1364 if (mtx != NULL) 1365 mtx_unlock(mtx); 1366 1367 XHCI_CMD_LOCK(sc); 1368 1369 switch (hdev->state) { 1370 case XHCI_ST_DEFAULT: 1371 case XHCI_ST_ENABLED: 1372 1373 hdev->state = XHCI_ST_ENABLED; 1374 1375 /* set configure mask to slot and EP0 */ 1376 xhci_configure_mask(udev, 3, 0); 1377 1378 /* configure input slot context structure */ 1379 err = xhci_configure_device(udev); 1380 1381 if (err != 0) { 1382 DPRINTF("Could not configure device\n"); 1383 break; 1384 } 1385 1386 /* configure input endpoint context structure */ 1387 switch (udev->speed) { 1388 case USB_SPEED_LOW: 1389 case USB_SPEED_FULL: 1390 mps = 8; 1391 break; 1392 case USB_SPEED_HIGH: 1393 mps = 64; 1394 break; 1395 default: 1396 mps = 512; 1397 break; 1398 } 1399 1400 pepext = xhci_get_endpoint_ext(udev, 1401 &udev->ctrl_ep_desc); 1402 1403 /* ensure the control endpoint is setup again */ 1404 USB_BUS_LOCK(udev->bus); 1405 pepext->trb_halted = 1; 1406 pepext->trb_running = 0; 1407 USB_BUS_UNLOCK(udev->bus); 1408 1409 err = xhci_configure_endpoint(udev, 1410 &udev->ctrl_ep_desc, pepext, 1411 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1412 1413 if (err != 0) { 1414 DPRINTF("Could not configure default endpoint\n"); 1415 break; 1416 } 1417 1418 /* execute set address command */ 1419 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1420 1421 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1422 (address == 0), index); 1423 1424 if (err != 0) { 1425 temp = le32toh(sc->sc_cmd_result[0]); 1426 if (address == 0 && sc->sc_port_route != NULL && 1427 XHCI_TRB_2_ERROR_GET(temp) == 1428 XHCI_TRB_ERROR_PARAMETER) { 1429 /* LynxPoint XHCI - ports are not switchable */ 1430 /* Un-route all ports from the XHCI */ 1431 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1432 } 1433 DPRINTF("Could not set address " 1434 "for slot %u.\n", index); 1435 if (address != 0) 1436 break; 1437 } 1438 1439 /* update device address to new value */ 1440 1441 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1442 slot = XHCI_GET_CTX(sc, xhci_dev_ctx, ctx_slot, 1443 buf_dev.buffer); 1444 usb_pc_cpu_invalidate(&hdev->device_pc); 1445 1446 temp = le32toh(slot->dwSctx3); 1447 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1448 1449 /* update device state to new value */ 1450 1451 if (address != 0) 1452 hdev->state = XHCI_ST_ADDRESSED; 1453 else 1454 hdev->state = XHCI_ST_DEFAULT; 1455 break; 1456 1457 default: 1458 DPRINTF("Wrong state for set address.\n"); 1459 err = USB_ERR_IOERROR; 1460 break; 1461 } 1462 XHCI_CMD_UNLOCK(sc); 1463 1464 if (mtx != NULL) 1465 mtx_lock(mtx); 1466 1467 return (err); 1468 } 1469 1470 static usb_error_t 1471 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1472 uint8_t deconfigure, uint8_t slot_id) 1473 { 1474 struct xhci_trb trb; 1475 uint32_t temp; 1476 1477 DPRINTF("\n"); 1478 1479 trb.qwTrb0 = htole64(input_ctx); 1480 trb.dwTrb2 = 0; 1481 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1482 XHCI_TRB_3_SLOT_SET(slot_id); 1483 1484 if (deconfigure) { 1485 if (sc->sc_no_deconfigure != 0 || xhcidcepquirk != 0) 1486 return (0); /* Success */ 1487 temp |= XHCI_TRB_3_DCEP_BIT; 1488 } 1489 1490 trb.dwTrb3 = htole32(temp); 1491 1492 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1493 } 1494 1495 static usb_error_t 1496 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1497 uint8_t slot_id) 1498 { 1499 struct xhci_trb trb; 1500 uint32_t temp; 1501 1502 DPRINTF("\n"); 1503 1504 trb.qwTrb0 = htole64(input_ctx); 1505 trb.dwTrb2 = 0; 1506 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1507 XHCI_TRB_3_SLOT_SET(slot_id); 1508 trb.dwTrb3 = htole32(temp); 1509 1510 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1511 } 1512 1513 static usb_error_t 1514 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1515 uint8_t ep_id, uint8_t slot_id) 1516 { 1517 struct xhci_trb trb; 1518 uint32_t temp; 1519 1520 DPRINTF("\n"); 1521 1522 trb.qwTrb0 = 0; 1523 trb.dwTrb2 = 0; 1524 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1525 XHCI_TRB_3_SLOT_SET(slot_id) | 1526 XHCI_TRB_3_EP_SET(ep_id); 1527 1528 if (preserve) 1529 temp |= XHCI_TRB_3_PRSV_BIT; 1530 1531 trb.dwTrb3 = htole32(temp); 1532 1533 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1534 } 1535 1536 static usb_error_t 1537 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1538 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1539 { 1540 struct xhci_trb trb; 1541 uint32_t temp; 1542 1543 DPRINTF("\n"); 1544 1545 trb.qwTrb0 = htole64(dequeue_ptr); 1546 1547 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1548 trb.dwTrb2 = htole32(temp); 1549 1550 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1551 XHCI_TRB_3_SLOT_SET(slot_id) | 1552 XHCI_TRB_3_EP_SET(ep_id); 1553 trb.dwTrb3 = htole32(temp); 1554 1555 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1556 } 1557 1558 static usb_error_t 1559 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1560 uint8_t ep_id, uint8_t slot_id) 1561 { 1562 struct xhci_trb trb; 1563 uint32_t temp; 1564 1565 DPRINTF("\n"); 1566 1567 trb.qwTrb0 = 0; 1568 trb.dwTrb2 = 0; 1569 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1570 XHCI_TRB_3_SLOT_SET(slot_id) | 1571 XHCI_TRB_3_EP_SET(ep_id); 1572 1573 if (suspend) 1574 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1575 1576 trb.dwTrb3 = htole32(temp); 1577 1578 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1579 } 1580 1581 static usb_error_t 1582 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1583 { 1584 struct xhci_trb trb; 1585 uint32_t temp; 1586 1587 DPRINTF("\n"); 1588 1589 trb.qwTrb0 = 0; 1590 trb.dwTrb2 = 0; 1591 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1592 XHCI_TRB_3_SLOT_SET(slot_id); 1593 1594 trb.dwTrb3 = htole32(temp); 1595 1596 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1597 } 1598 1599 /*------------------------------------------------------------------------* 1600 * xhci_interrupt - XHCI interrupt handler 1601 *------------------------------------------------------------------------*/ 1602 void 1603 xhci_interrupt(struct xhci_softc *sc) 1604 { 1605 uint32_t status; 1606 uint32_t temp; 1607 1608 USB_BUS_LOCK(&sc->sc_bus); 1609 1610 status = XREAD4(sc, oper, XHCI_USBSTS); 1611 1612 /* acknowledge interrupts, if any */ 1613 if (status != 0) { 1614 XWRITE4(sc, oper, XHCI_USBSTS, status); 1615 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1616 } 1617 1618 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1619 1620 /* force clearing of pending interrupts */ 1621 if (temp & XHCI_IMAN_INTR_PEND) 1622 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1623 1624 /* check for event(s) */ 1625 xhci_interrupt_poll(sc); 1626 1627 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1628 XHCI_STS_HSE | XHCI_STS_HCE)) { 1629 if (status & XHCI_STS_PCD) { 1630 xhci_root_intr(sc); 1631 } 1632 1633 if (status & XHCI_STS_HCH) { 1634 printf("%s: host controller halted\n", 1635 __FUNCTION__); 1636 } 1637 1638 if (status & XHCI_STS_HSE) { 1639 printf("%s: host system error\n", 1640 __FUNCTION__); 1641 } 1642 1643 if (status & XHCI_STS_HCE) { 1644 printf("%s: host controller error\n", 1645 __FUNCTION__); 1646 } 1647 } 1648 USB_BUS_UNLOCK(&sc->sc_bus); 1649 } 1650 1651 /*------------------------------------------------------------------------* 1652 * xhci_timeout - XHCI timeout handler 1653 *------------------------------------------------------------------------*/ 1654 static void 1655 xhci_timeout(void *arg) 1656 { 1657 struct usb_xfer *xfer = arg; 1658 1659 DPRINTF("xfer=%p\n", xfer); 1660 1661 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1662 1663 /* transfer is transferred */ 1664 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1665 } 1666 1667 static void 1668 xhci_do_poll(struct usb_bus *bus) 1669 { 1670 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1671 1672 USB_BUS_LOCK(&sc->sc_bus); 1673 xhci_interrupt_poll(sc); 1674 USB_BUS_UNLOCK(&sc->sc_bus); 1675 } 1676 1677 static void 1678 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1679 { 1680 struct usb_page_search buf_res; 1681 struct xhci_td *td; 1682 struct xhci_td *td_next; 1683 struct xhci_td *td_alt_next; 1684 struct xhci_td *td_first; 1685 uint32_t buf_offset; 1686 uint32_t average; 1687 uint32_t len_old; 1688 uint32_t npkt_off; 1689 uint32_t dword; 1690 uint8_t shortpkt_old; 1691 uint8_t precompute; 1692 uint8_t x; 1693 1694 td_alt_next = NULL; 1695 buf_offset = 0; 1696 shortpkt_old = temp->shortpkt; 1697 len_old = temp->len; 1698 npkt_off = 0; 1699 precompute = 1; 1700 1701 restart: 1702 1703 td = temp->td; 1704 td_next = td_first = temp->td_next; 1705 1706 while (1) { 1707 if (temp->len == 0) { 1708 if (temp->shortpkt) 1709 break; 1710 1711 /* send a Zero Length Packet, ZLP, last */ 1712 1713 temp->shortpkt = 1; 1714 average = 0; 1715 1716 } else { 1717 average = temp->average; 1718 1719 if (temp->len < average) { 1720 if (temp->len % temp->max_packet_size) { 1721 temp->shortpkt = 1; 1722 } 1723 average = temp->len; 1724 } 1725 } 1726 1727 if (td_next == NULL) 1728 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1729 1730 /* get next TD */ 1731 1732 td = td_next; 1733 td_next = td->obj_next; 1734 1735 /* check if we are pre-computing */ 1736 1737 if (precompute) { 1738 /* update remaining length */ 1739 1740 temp->len -= average; 1741 1742 continue; 1743 } 1744 /* fill out current TD */ 1745 1746 td->len = average; 1747 td->remainder = 0; 1748 td->status = 0; 1749 1750 /* update remaining length */ 1751 1752 temp->len -= average; 1753 1754 /* reset TRB index */ 1755 1756 x = 0; 1757 1758 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1759 /* immediate data */ 1760 1761 if (average > 8) 1762 average = 8; 1763 1764 td->td_trb[0].qwTrb0 = 0; 1765 1766 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1767 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1768 average); 1769 1770 dword = XHCI_TRB_2_BYTES_SET(8) | 1771 XHCI_TRB_2_TDSZ_SET(0) | 1772 XHCI_TRB_2_IRQ_SET(0); 1773 1774 td->td_trb[0].dwTrb2 = htole32(dword); 1775 1776 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1777 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1778 1779 /* check wLength */ 1780 if (td->td_trb[0].qwTrb0 & 1781 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1782 if (td->td_trb[0].qwTrb0 & 1783 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1784 dword |= XHCI_TRB_3_TRT_IN; 1785 else 1786 dword |= XHCI_TRB_3_TRT_OUT; 1787 } 1788 1789 td->td_trb[0].dwTrb3 = htole32(dword); 1790 #ifdef USB_DEBUG 1791 xhci_dump_trb(&td->td_trb[x]); 1792 #endif 1793 x++; 1794 1795 } else do { 1796 uint32_t npkt; 1797 1798 /* fill out buffer pointers */ 1799 1800 if (average == 0) { 1801 memset(&buf_res, 0, sizeof(buf_res)); 1802 } else { 1803 usbd_get_page(temp->pc, temp->offset + 1804 buf_offset, &buf_res); 1805 1806 /* get length to end of page */ 1807 if (buf_res.length > average) 1808 buf_res.length = average; 1809 1810 /* check for maximum length */ 1811 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1812 buf_res.length = XHCI_TD_PAGE_SIZE; 1813 1814 npkt_off += buf_res.length; 1815 } 1816 1817 /* set up npkt */ 1818 npkt = howmany(len_old - npkt_off, 1819 temp->max_packet_size); 1820 1821 if (npkt == 0) 1822 npkt = 1; 1823 else if (npkt > 31) 1824 npkt = 31; 1825 1826 /* fill out TRB's */ 1827 td->td_trb[x].qwTrb0 = 1828 htole64((uint64_t)buf_res.physaddr); 1829 1830 dword = 1831 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1832 XHCI_TRB_2_TDSZ_SET(npkt) | 1833 XHCI_TRB_2_IRQ_SET(0); 1834 1835 td->td_trb[x].dwTrb2 = htole32(dword); 1836 1837 switch (temp->trb_type) { 1838 case XHCI_TRB_TYPE_ISOCH: 1839 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1840 XHCI_TRB_3_TBC_SET(temp->tbc) | 1841 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1842 if (td != td_first) { 1843 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1844 } else if (temp->do_isoc_sync != 0) { 1845 temp->do_isoc_sync = 0; 1846 /* wait until "isoc_frame" */ 1847 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1848 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1849 } else { 1850 /* start data transfer at next interval */ 1851 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1852 XHCI_TRB_3_ISO_SIA_BIT; 1853 } 1854 if (temp->direction == UE_DIR_IN) 1855 dword |= XHCI_TRB_3_ISP_BIT; 1856 break; 1857 case XHCI_TRB_TYPE_DATA_STAGE: 1858 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1859 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1860 if (temp->direction == UE_DIR_IN) 1861 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1862 /* 1863 * Section 3.2.9 in the XHCI 1864 * specification about control 1865 * transfers says that we should use a 1866 * normal-TRB if there are more TRBs 1867 * extending the data-stage 1868 * TRB. Update the "trb_type". 1869 */ 1870 temp->trb_type = XHCI_TRB_TYPE_NORMAL; 1871 break; 1872 case XHCI_TRB_TYPE_STATUS_STAGE: 1873 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1874 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1875 if (temp->direction == UE_DIR_IN) 1876 dword |= XHCI_TRB_3_DIR_IN; 1877 break; 1878 default: /* XHCI_TRB_TYPE_NORMAL */ 1879 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1880 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1881 if (temp->direction == UE_DIR_IN) 1882 dword |= XHCI_TRB_3_ISP_BIT; 1883 break; 1884 } 1885 td->td_trb[x].dwTrb3 = htole32(dword); 1886 1887 average -= buf_res.length; 1888 buf_offset += buf_res.length; 1889 #ifdef USB_DEBUG 1890 xhci_dump_trb(&td->td_trb[x]); 1891 #endif 1892 x++; 1893 1894 } while (average != 0); 1895 1896 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1897 1898 /* store number of data TRB's */ 1899 1900 td->ntrb = x; 1901 1902 DPRINTF("NTRB=%u\n", x); 1903 1904 /* fill out link TRB */ 1905 1906 if (td_next != NULL) { 1907 /* link the current TD with the next one */ 1908 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1909 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1910 } else { 1911 /* this field will get updated later */ 1912 DPRINTF("NOLINK\n"); 1913 } 1914 1915 dword = XHCI_TRB_2_IRQ_SET(0); 1916 1917 td->td_trb[x].dwTrb2 = htole32(dword); 1918 1919 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1920 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1921 /* 1922 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1923 * frame only receives a single short packet event 1924 * by setting the CHAIN bit in the LINK field. In 1925 * addition some XHCI controllers have problems 1926 * sending a ZLP unless the CHAIN-BIT is set in 1927 * the LINK TRB. 1928 */ 1929 XHCI_TRB_3_CHAIN_BIT; 1930 1931 td->td_trb[x].dwTrb3 = htole32(dword); 1932 1933 td->alt_next = td_alt_next; 1934 #ifdef USB_DEBUG 1935 xhci_dump_trb(&td->td_trb[x]); 1936 #endif 1937 usb_pc_cpu_flush(td->page_cache); 1938 } 1939 1940 if (precompute) { 1941 precompute = 0; 1942 1943 /* set up alt next pointer, if any */ 1944 if (temp->last_frame) { 1945 td_alt_next = NULL; 1946 } else { 1947 /* we use this field internally */ 1948 td_alt_next = td_next; 1949 } 1950 1951 /* restore */ 1952 temp->shortpkt = shortpkt_old; 1953 temp->len = len_old; 1954 goto restart; 1955 } 1956 1957 /* 1958 * Remove cycle bit from the first TRB if we are 1959 * stepping them: 1960 */ 1961 if (temp->step_td != 0) { 1962 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1963 usb_pc_cpu_flush(td_first->page_cache); 1964 } 1965 1966 /* clear TD SIZE to zero, hence this is the last TRB */ 1967 /* remove chain bit because this is the last data TRB in the chain */ 1968 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31)); 1969 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1970 /* remove CHAIN-BIT from last LINK TRB */ 1971 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1972 1973 usb_pc_cpu_flush(td->page_cache); 1974 1975 temp->td = td; 1976 temp->td_next = td_next; 1977 } 1978 1979 static void 1980 xhci_setup_generic_chain(struct usb_xfer *xfer) 1981 { 1982 struct xhci_std_temp temp; 1983 struct xhci_td *td; 1984 uint32_t x; 1985 uint32_t y; 1986 uint8_t mult; 1987 1988 temp.do_isoc_sync = 0; 1989 temp.step_td = 0; 1990 temp.tbc = 0; 1991 temp.tlbpc = 0; 1992 temp.average = xfer->max_hc_frame_size; 1993 temp.max_packet_size = xfer->max_packet_size; 1994 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1995 temp.pc = NULL; 1996 temp.last_frame = 0; 1997 temp.offset = 0; 1998 temp.multishort = xfer->flags_int.isochronous_xfr || 1999 xfer->flags_int.control_xfr || 2000 xfer->flags_int.short_frames_ok; 2001 2002 /* toggle the DMA set we are using */ 2003 xfer->flags_int.curr_dma_set ^= 1; 2004 2005 /* get next DMA set */ 2006 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2007 2008 temp.td = NULL; 2009 temp.td_next = td; 2010 2011 xfer->td_transfer_first = td; 2012 xfer->td_transfer_cache = td; 2013 2014 if (xfer->flags_int.isochronous_xfr) { 2015 uint8_t shift; 2016 2017 /* compute multiplier for ISOCHRONOUS transfers */ 2018 mult = xfer->endpoint->ecomp ? 2019 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2020 : 0; 2021 /* check for USB 2.0 multiplier */ 2022 if (mult == 0) { 2023 mult = (xfer->endpoint->edesc-> 2024 wMaxPacketSize[1] >> 3) & 3; 2025 } 2026 /* range check */ 2027 if (mult > 2) 2028 mult = 3; 2029 else 2030 mult++; 2031 2032 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2033 2034 DPRINTF("MFINDEX=0x%08x IST=0x%x\n", x, temp.sc->sc_ist); 2035 2036 switch (usbd_get_speed(xfer->xroot->udev)) { 2037 case USB_SPEED_FULL: 2038 shift = 3; 2039 temp.isoc_delta = 8; /* 1ms */ 2040 break; 2041 default: 2042 shift = usbd_xfer_get_fps_shift(xfer); 2043 temp.isoc_delta = 1U << shift; 2044 break; 2045 } 2046 2047 /* Compute isochronous scheduling threshold. */ 2048 if (temp.sc->sc_ist & 8) 2049 y = (temp.sc->sc_ist & 7) << 3; 2050 else 2051 y = (temp.sc->sc_ist & 7); 2052 2053 /* Range check the IST. */ 2054 if (y < 8) { 2055 y = 0; 2056 } else if (y > 15) { 2057 DPRINTFN(3, "IST(%d) is too big!\n", temp.sc->sc_ist); 2058 /* 2059 * The USB stack minimum isochronous transfer 2060 * size is typically 2x2 ms of payload. If the 2061 * IST makes is above 15 microframes, we have 2062 * an effective scheduling delay of more than 2063 * or equal to 2 milliseconds, which is too 2064 * much. 2065 */ 2066 y = 7; 2067 } else { 2068 /* 2069 * Subtract one millisecond, because the 2070 * generic code adds that to the latency. 2071 */ 2072 y -= 8; 2073 } 2074 2075 if (usbd_xfer_get_isochronous_start_frame( 2076 xfer, x, y, 8, XHCI_MFINDEX_GET(-1), &temp.isoc_frame)) { 2077 /* Start isochronous transfer at specified time. */ 2078 temp.do_isoc_sync = 1; 2079 2080 DPRINTFN(3, "start next=%d\n", temp.isoc_frame); 2081 } 2082 2083 x = 0; 2084 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2085 2086 } else if (xfer->flags_int.control_xfr) { 2087 /* check if we should prepend a setup message */ 2088 2089 if (xfer->flags_int.control_hdr) { 2090 temp.len = xfer->frlengths[0]; 2091 temp.pc = xfer->frbuffers + 0; 2092 temp.shortpkt = temp.len ? 1 : 0; 2093 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2094 temp.direction = 0; 2095 2096 /* check for last frame */ 2097 if (xfer->nframes == 1) { 2098 /* no STATUS stage yet, SETUP is last */ 2099 if (xfer->flags_int.control_act) 2100 temp.last_frame = 1; 2101 } 2102 2103 xhci_setup_generic_chain_sub(&temp); 2104 } 2105 x = 1; 2106 mult = 1; 2107 temp.isoc_delta = 0; 2108 temp.isoc_frame = 0; 2109 temp.trb_type = xfer->flags_int.control_did_data ? 2110 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE; 2111 } else { 2112 x = 0; 2113 mult = 1; 2114 temp.isoc_delta = 0; 2115 temp.isoc_frame = 0; 2116 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2117 } 2118 2119 if (x != xfer->nframes) { 2120 /* set up page_cache pointer */ 2121 temp.pc = xfer->frbuffers + x; 2122 /* set endpoint direction */ 2123 temp.direction = UE_GET_DIR(xfer->endpointno); 2124 } 2125 2126 while (x != xfer->nframes) { 2127 /* DATA0 / DATA1 message */ 2128 2129 temp.len = xfer->frlengths[x]; 2130 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2131 x != 0 && temp.multishort == 0); 2132 2133 x++; 2134 2135 if (x == xfer->nframes) { 2136 if (xfer->flags_int.control_xfr) { 2137 /* no STATUS stage yet, DATA is last */ 2138 if (xfer->flags_int.control_act) 2139 temp.last_frame = 1; 2140 } else { 2141 temp.last_frame = 1; 2142 } 2143 } 2144 if (temp.len == 0) { 2145 /* make sure that we send an USB packet */ 2146 2147 temp.shortpkt = 0; 2148 2149 temp.tbc = 0; 2150 temp.tlbpc = mult - 1; 2151 2152 } else if (xfer->flags_int.isochronous_xfr) { 2153 uint8_t tdpc; 2154 2155 /* 2156 * Isochronous transfers don't have short 2157 * packet termination: 2158 */ 2159 2160 temp.shortpkt = 1; 2161 2162 /* isochronous transfers have a transfer limit */ 2163 2164 if (temp.len > xfer->max_frame_size) 2165 temp.len = xfer->max_frame_size; 2166 2167 /* compute TD packet count */ 2168 tdpc = howmany(temp.len, xfer->max_packet_size); 2169 2170 temp.tbc = howmany(tdpc, mult) - 1; 2171 temp.tlbpc = (tdpc % mult); 2172 2173 if (temp.tlbpc == 0) 2174 temp.tlbpc = mult - 1; 2175 else 2176 temp.tlbpc--; 2177 } else { 2178 /* regular data transfer */ 2179 2180 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2181 } 2182 2183 xhci_setup_generic_chain_sub(&temp); 2184 2185 if (xfer->flags_int.isochronous_xfr) { 2186 temp.offset += xfer->frlengths[x - 1]; 2187 temp.isoc_frame += temp.isoc_delta; 2188 } else { 2189 /* get next Page Cache pointer */ 2190 temp.pc = xfer->frbuffers + x; 2191 } 2192 } 2193 2194 /* check if we should append a status stage */ 2195 2196 if (xfer->flags_int.control_xfr && 2197 !xfer->flags_int.control_act) { 2198 /* 2199 * Send a DATA1 message and invert the current 2200 * endpoint direction. 2201 */ 2202 if (xhcictlstep || temp.sc->sc_ctlstep) { 2203 /* 2204 * Some XHCI controllers will not delay the 2205 * status stage until the next SOF. Force this 2206 * behaviour to avoid failed control 2207 * transfers. 2208 */ 2209 temp.step_td = (xfer->nframes != 0); 2210 } else { 2211 temp.step_td = 0; 2212 } 2213 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2214 temp.len = 0; 2215 temp.pc = NULL; 2216 temp.shortpkt = 0; 2217 temp.last_frame = 1; 2218 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2219 2220 xhci_setup_generic_chain_sub(&temp); 2221 } 2222 2223 td = temp.td; 2224 2225 /* must have at least one frame! */ 2226 2227 xfer->td_transfer_last = td; 2228 2229 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2230 } 2231 2232 static void 2233 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2234 { 2235 struct usb_page_search buf_res; 2236 struct xhci_dev_ctx_addr *pdctxa; 2237 2238 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2239 2240 pdctxa = buf_res.buffer; 2241 2242 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2243 2244 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2245 2246 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2247 } 2248 2249 static usb_error_t 2250 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2251 { 2252 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2253 struct usb_page_search buf_inp; 2254 struct xhci_input_ctx *input; 2255 struct xhci_slot_ctx *slot; 2256 uint32_t temp; 2257 uint8_t index; 2258 uint8_t x; 2259 2260 index = udev->controller_slot_id; 2261 2262 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2263 2264 input = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_input, 2265 buf_inp.buffer); 2266 slot = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_slot, buf_inp.buffer); 2267 2268 if (drop) { 2269 mask &= XHCI_INCTX_NON_CTRL_MASK; 2270 input->dwInCtx0 = htole32(mask); 2271 input->dwInCtx1 = htole32(0); 2272 } else { 2273 /* 2274 * Some hardware requires that we drop the endpoint 2275 * context before adding it again: 2276 */ 2277 input->dwInCtx0 = htole32(mask & XHCI_INCTX_NON_CTRL_MASK); 2278 2279 /* Add new endpoint context */ 2280 input->dwInCtx1 = htole32(mask); 2281 2282 /* find most significant set bit */ 2283 for (x = 31; x != 1; x--) { 2284 if (mask & (1 << x)) 2285 break; 2286 } 2287 2288 /* adjust */ 2289 x--; 2290 2291 /* figure out the maximum number of contexts */ 2292 if (x > sc->sc_hw.devs[index].context_num) 2293 sc->sc_hw.devs[index].context_num = x; 2294 else 2295 x = sc->sc_hw.devs[index].context_num; 2296 2297 /* update number of contexts */ 2298 temp = le32toh(slot->dwSctx0); 2299 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2300 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2301 slot->dwSctx0 = htole32(temp); 2302 } 2303 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2304 return (0); 2305 } 2306 2307 static usb_error_t 2308 xhci_configure_endpoint(struct usb_device *udev, 2309 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2310 uint16_t interval, uint8_t max_packet_count, 2311 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2312 uint16_t max_frame_size, uint8_t ep_mode) 2313 { 2314 struct usb_page_search buf_inp; 2315 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2316 struct xhci_endp_ctx *endp; 2317 uint64_t ring_addr = pepext->physaddr; 2318 uint32_t temp; 2319 uint8_t index; 2320 uint8_t epno; 2321 uint8_t type; 2322 2323 index = udev->controller_slot_id; 2324 2325 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2326 2327 epno = edesc->bEndpointAddress; 2328 type = edesc->bmAttributes & UE_XFERTYPE; 2329 2330 if (type == UE_CONTROL) 2331 epno |= UE_DIR_IN; 2332 2333 epno = XHCI_EPNO2EPID(epno); 2334 2335 if (epno == 0) 2336 return (USB_ERR_NO_PIPE); /* invalid */ 2337 2338 if (max_packet_count == 0) 2339 return (USB_ERR_BAD_BUFSIZE); 2340 2341 max_packet_count--; 2342 2343 if (mult == 0) 2344 return (USB_ERR_BAD_BUFSIZE); 2345 2346 endp = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_ep[epno - 1], 2347 buf_inp.buffer); 2348 2349 /* store endpoint mode */ 2350 pepext->trb_ep_mode = ep_mode; 2351 /* store bMaxPacketSize for control endpoints */ 2352 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0]; 2353 usb_pc_cpu_flush(pepext->page_cache); 2354 2355 if (ep_mode == USB_EP_MODE_STREAMS) { 2356 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2357 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2358 XHCI_EPCTX_0_LSA_SET(1); 2359 2360 ring_addr += sizeof(struct xhci_trb) * 2361 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2362 } else { 2363 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2364 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2365 XHCI_EPCTX_0_LSA_SET(0); 2366 2367 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2368 } 2369 2370 switch (udev->speed) { 2371 case USB_SPEED_FULL: 2372 case USB_SPEED_LOW: 2373 /* 1ms -> 125us */ 2374 fps_shift += 3; 2375 break; 2376 default: 2377 break; 2378 } 2379 2380 switch (type) { 2381 case UE_INTERRUPT: 2382 if (fps_shift > 3) 2383 fps_shift--; 2384 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2385 break; 2386 case UE_ISOCHRONOUS: 2387 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2388 2389 switch (udev->speed) { 2390 case USB_SPEED_SUPER: 2391 if (mult > 3) 2392 mult = 3; 2393 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2394 max_packet_count /= mult; 2395 break; 2396 default: 2397 break; 2398 } 2399 break; 2400 default: 2401 break; 2402 } 2403 2404 endp->dwEpCtx0 = htole32(temp); 2405 2406 temp = 2407 XHCI_EPCTX_1_HID_SET(0) | 2408 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2409 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2410 2411 /* 2412 * Always enable the "three strikes and you are gone" feature 2413 * except for ISOCHRONOUS endpoints. This is suggested by 2414 * section 4.3.3 in the XHCI specification about device slot 2415 * initialisation. 2416 */ 2417 if (type != UE_ISOCHRONOUS) 2418 temp |= XHCI_EPCTX_1_CERR_SET(3); 2419 2420 switch (type) { 2421 case UE_CONTROL: 2422 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2423 break; 2424 case UE_ISOCHRONOUS: 2425 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2426 break; 2427 case UE_BULK: 2428 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2429 break; 2430 default: 2431 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2432 break; 2433 } 2434 2435 /* check for IN direction */ 2436 if (epno & 1) 2437 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2438 2439 endp->dwEpCtx1 = htole32(temp); 2440 endp->qwEpCtx2 = htole64(ring_addr); 2441 2442 switch (edesc->bmAttributes & UE_XFERTYPE) { 2443 case UE_INTERRUPT: 2444 case UE_ISOCHRONOUS: 2445 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2446 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2447 max_frame_size)); 2448 break; 2449 case UE_CONTROL: 2450 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2451 break; 2452 default: 2453 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2454 break; 2455 } 2456 2457 endp->dwEpCtx4 = htole32(temp); 2458 2459 #ifdef USB_DEBUG 2460 xhci_dump_endpoint(endp); 2461 #endif 2462 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2463 2464 return (0); /* success */ 2465 } 2466 2467 static usb_error_t 2468 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2469 { 2470 struct xhci_endpoint_ext *pepext; 2471 struct usb_endpoint_ss_comp_descriptor *ecomp; 2472 usb_stream_t x; 2473 2474 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2475 xfer->endpoint->edesc); 2476 2477 ecomp = xfer->endpoint->ecomp; 2478 2479 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2480 uint64_t temp; 2481 2482 /* halt any transfers */ 2483 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2484 2485 /* compute start of TRB ring for stream "x" */ 2486 temp = pepext->physaddr + 2487 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2488 XHCI_SCTX_0_SCT_SEC_TR_RING; 2489 2490 /* make tree structure */ 2491 pepext->trb[(XHCI_MAX_TRANSFERS * 2492 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2493 2494 /* reserved fields */ 2495 pepext->trb[(XHCI_MAX_TRANSFERS * 2496 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2497 pepext->trb[(XHCI_MAX_TRANSFERS * 2498 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2499 } 2500 usb_pc_cpu_flush(pepext->page_cache); 2501 2502 return (xhci_configure_endpoint(xfer->xroot->udev, 2503 xfer->endpoint->edesc, pepext, 2504 xfer->interval, xfer->max_packet_count, 2505 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2506 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2507 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2508 } 2509 2510 static usb_error_t 2511 xhci_configure_device(struct usb_device *udev) 2512 { 2513 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2514 struct usb_page_search buf_inp; 2515 struct usb_page_cache *pcinp; 2516 struct xhci_slot_ctx *slot; 2517 struct usb_device *hubdev; 2518 uint32_t temp; 2519 uint32_t route; 2520 uint32_t rh_port; 2521 uint8_t is_hub; 2522 uint8_t index; 2523 uint8_t depth; 2524 2525 index = udev->controller_slot_id; 2526 2527 DPRINTF("index=%u\n", index); 2528 2529 pcinp = &sc->sc_hw.devs[index].input_pc; 2530 2531 usbd_get_page(pcinp, 0, &buf_inp); 2532 2533 slot = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_slot, buf_inp.buffer); 2534 2535 rh_port = 0; 2536 route = 0; 2537 2538 /* figure out route string and root HUB port number */ 2539 2540 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2541 if (hubdev->parent_hub == NULL) 2542 break; 2543 2544 depth = hubdev->parent_hub->depth; 2545 2546 /* 2547 * NOTE: HS/FS/LS devices and the SS root HUB can have 2548 * more than 15 ports 2549 */ 2550 2551 rh_port = hubdev->port_no; 2552 2553 if (depth == 0) 2554 break; 2555 2556 if (rh_port > 15) 2557 rh_port = 15; 2558 2559 if (depth < 6) 2560 route |= rh_port << (4 * (depth - 1)); 2561 } 2562 2563 DPRINTF("Route=0x%08x\n", route); 2564 2565 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2566 XHCI_SCTX_0_CTX_NUM_SET( 2567 sc->sc_hw.devs[index].context_num + 1); 2568 2569 switch (udev->speed) { 2570 case USB_SPEED_LOW: 2571 temp |= XHCI_SCTX_0_SPEED_SET(2); 2572 if (udev->parent_hs_hub != NULL && 2573 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2574 UDPROTO_HSHUBMTT) { 2575 DPRINTF("Device inherits MTT\n"); 2576 temp |= XHCI_SCTX_0_MTT_SET(1); 2577 } 2578 break; 2579 case USB_SPEED_HIGH: 2580 temp |= XHCI_SCTX_0_SPEED_SET(3); 2581 if (sc->sc_hw.devs[index].nports != 0 && 2582 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2583 DPRINTF("HUB supports MTT\n"); 2584 temp |= XHCI_SCTX_0_MTT_SET(1); 2585 } 2586 break; 2587 case USB_SPEED_FULL: 2588 temp |= XHCI_SCTX_0_SPEED_SET(1); 2589 if (udev->parent_hs_hub != NULL && 2590 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2591 UDPROTO_HSHUBMTT) { 2592 DPRINTF("Device inherits MTT\n"); 2593 temp |= XHCI_SCTX_0_MTT_SET(1); 2594 } 2595 break; 2596 default: 2597 temp |= XHCI_SCTX_0_SPEED_SET(4); 2598 break; 2599 } 2600 2601 is_hub = sc->sc_hw.devs[index].nports != 0 && 2602 (udev->speed == USB_SPEED_SUPER || 2603 udev->speed == USB_SPEED_HIGH); 2604 2605 if (is_hub) 2606 temp |= XHCI_SCTX_0_HUB_SET(1); 2607 2608 slot->dwSctx0 = htole32(temp); 2609 2610 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2611 2612 if (is_hub) { 2613 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2614 sc->sc_hw.devs[index].nports); 2615 } 2616 2617 slot->dwSctx1 = htole32(temp); 2618 2619 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2620 2621 if (is_hub) { 2622 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2623 sc->sc_hw.devs[index].tt); 2624 } 2625 2626 hubdev = udev->parent_hs_hub; 2627 2628 /* check if we should activate the transaction translator */ 2629 switch (udev->speed) { 2630 case USB_SPEED_FULL: 2631 case USB_SPEED_LOW: 2632 if (hubdev != NULL) { 2633 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2634 hubdev->controller_slot_id); 2635 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2636 udev->hs_port_no); 2637 } 2638 break; 2639 default: 2640 break; 2641 } 2642 2643 slot->dwSctx2 = htole32(temp); 2644 2645 /* 2646 * These fields should be initialized to zero, according to 2647 * XHCI section 6.2.2 - slot context: 2648 */ 2649 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2650 XHCI_SCTX_3_SLOT_STATE_SET(0); 2651 2652 slot->dwSctx3 = htole32(temp); 2653 2654 #ifdef USB_DEBUG 2655 xhci_dump_device(slot); 2656 #endif 2657 usb_pc_cpu_flush(pcinp); 2658 2659 return (0); /* success */ 2660 } 2661 2662 static usb_error_t 2663 xhci_alloc_device_ext(struct usb_device *udev) 2664 { 2665 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2666 struct usb_page_search buf_dev; 2667 struct usb_page_search buf_ep; 2668 struct xhci_trb *trb; 2669 struct usb_page_cache *pc; 2670 struct usb_page *pg; 2671 uint64_t addr; 2672 uint8_t index; 2673 uint8_t i; 2674 2675 index = udev->controller_slot_id; 2676 2677 pc = &sc->sc_hw.devs[index].device_pc; 2678 pg = &sc->sc_hw.devs[index].device_pg; 2679 2680 /* need to initialize the page cache */ 2681 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2682 2683 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2684 sizeof(struct xhci_dev_ctx64) : 2685 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2686 goto error; 2687 2688 usbd_get_page(pc, 0, &buf_dev); 2689 2690 pc = &sc->sc_hw.devs[index].input_pc; 2691 pg = &sc->sc_hw.devs[index].input_pg; 2692 2693 /* need to initialize the page cache */ 2694 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2695 2696 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2697 sizeof(struct xhci_input_dev_ctx64) : 2698 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2699 goto error; 2700 } 2701 2702 /* initialize all endpoint LINK TRBs */ 2703 2704 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2705 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2706 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2707 2708 /* need to initialize the page cache */ 2709 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2710 2711 if (usb_pc_alloc_mem(pc, pg, 2712 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2713 goto error; 2714 } 2715 2716 /* lookup endpoint TRB ring */ 2717 usbd_get_page(pc, 0, &buf_ep); 2718 2719 /* get TRB pointer */ 2720 trb = buf_ep.buffer; 2721 trb += XHCI_MAX_TRANSFERS - 1; 2722 2723 /* get TRB start address */ 2724 addr = buf_ep.physaddr; 2725 2726 /* create LINK TRB */ 2727 trb->qwTrb0 = htole64(addr); 2728 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2729 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2730 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2731 2732 usb_pc_cpu_flush(pc); 2733 } 2734 2735 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2736 2737 return (0); 2738 2739 error: 2740 xhci_free_device_ext(udev); 2741 2742 return (USB_ERR_NOMEM); 2743 } 2744 2745 static void 2746 xhci_free_device_ext(struct usb_device *udev) 2747 { 2748 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2749 uint8_t index; 2750 uint8_t i; 2751 2752 index = udev->controller_slot_id; 2753 xhci_set_slot_pointer(sc, index, 0); 2754 2755 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2756 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2757 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2758 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2759 } 2760 2761 static struct xhci_endpoint_ext * 2762 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2763 { 2764 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2765 struct xhci_endpoint_ext *pepext; 2766 struct usb_page_cache *pc; 2767 struct usb_page_search buf_ep; 2768 uint8_t epno; 2769 uint8_t index; 2770 2771 epno = edesc->bEndpointAddress; 2772 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2773 epno |= UE_DIR_IN; 2774 2775 epno = XHCI_EPNO2EPID(epno); 2776 2777 index = udev->controller_slot_id; 2778 2779 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2780 2781 usbd_get_page(pc, 0, &buf_ep); 2782 2783 pepext = &sc->sc_hw.devs[index].endp[epno]; 2784 pepext->page_cache = pc; 2785 pepext->trb = buf_ep.buffer; 2786 pepext->physaddr = buf_ep.physaddr; 2787 2788 return (pepext); 2789 } 2790 2791 static void 2792 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2793 { 2794 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2795 uint8_t epno; 2796 uint8_t index; 2797 2798 epno = xfer->endpointno; 2799 if (xfer->flags_int.control_xfr) 2800 epno |= UE_DIR_IN; 2801 2802 epno = XHCI_EPNO2EPID(epno); 2803 index = xfer->xroot->udev->controller_slot_id; 2804 2805 if (xfer->xroot->udev->flags.self_suspended == 0) { 2806 XWRITE4(sc, door, XHCI_DOORBELL(index), 2807 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2808 } 2809 } 2810 2811 static void 2812 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2813 { 2814 struct xhci_endpoint_ext *pepext; 2815 2816 if (xfer->flags_int.bandwidth_reclaimed) { 2817 xfer->flags_int.bandwidth_reclaimed = 0; 2818 2819 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2820 xfer->endpoint->edesc); 2821 2822 pepext->trb_used[xfer->stream_id]--; 2823 2824 pepext->xfer[xfer->qh_pos] = NULL; 2825 2826 if (error && pepext->trb_running != 0) { 2827 pepext->trb_halted = 1; 2828 pepext->trb_running = 0; 2829 } 2830 } 2831 } 2832 2833 static usb_error_t 2834 xhci_transfer_insert(struct usb_xfer *xfer) 2835 { 2836 struct xhci_td *td_first; 2837 struct xhci_td *td_last; 2838 struct xhci_trb *trb_link; 2839 struct xhci_endpoint_ext *pepext; 2840 uint64_t addr; 2841 usb_stream_t id; 2842 uint8_t i; 2843 uint8_t inext; 2844 uint8_t trb_limit; 2845 2846 DPRINTFN(8, "\n"); 2847 2848 id = xfer->stream_id; 2849 2850 /* check if already inserted */ 2851 if (xfer->flags_int.bandwidth_reclaimed) { 2852 DPRINTFN(8, "Already in schedule\n"); 2853 return (0); 2854 } 2855 2856 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2857 xfer->endpoint->edesc); 2858 2859 td_first = xfer->td_transfer_first; 2860 td_last = xfer->td_transfer_last; 2861 addr = pepext->physaddr; 2862 2863 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2864 case UE_CONTROL: 2865 case UE_INTERRUPT: 2866 /* single buffered */ 2867 trb_limit = 1; 2868 break; 2869 default: 2870 /* multi buffered */ 2871 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2872 break; 2873 } 2874 2875 if (pepext->trb_used[id] >= trb_limit) { 2876 DPRINTFN(8, "Too many TDs queued.\n"); 2877 return (USB_ERR_NOMEM); 2878 } 2879 2880 /* check if bMaxPacketSize changed */ 2881 if (xfer->flags_int.control_xfr != 0 && 2882 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) { 2883 DPRINTFN(8, "Reconfigure control endpoint\n"); 2884 2885 /* force driver to reconfigure endpoint */ 2886 pepext->trb_halted = 1; 2887 pepext->trb_running = 0; 2888 } 2889 2890 /* check for stopped condition, after putting transfer on interrupt queue */ 2891 if (pepext->trb_running == 0) { 2892 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2893 2894 DPRINTFN(8, "Not running\n"); 2895 2896 /* start configuration */ 2897 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2898 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2899 return (0); 2900 } 2901 2902 pepext->trb_used[id]++; 2903 2904 /* get current TRB index */ 2905 i = pepext->trb_index[id]; 2906 2907 /* get next TRB index */ 2908 inext = (i + 1); 2909 2910 /* the last entry of the ring is a hardcoded link TRB */ 2911 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2912 inext = 0; 2913 2914 /* store next TRB index, before stream ID offset is added */ 2915 pepext->trb_index[id] = inext; 2916 2917 /* offset for stream */ 2918 i += id * XHCI_MAX_TRANSFERS; 2919 inext += id * XHCI_MAX_TRANSFERS; 2920 2921 /* compute terminating return address */ 2922 addr += (inext * sizeof(struct xhci_trb)); 2923 2924 /* compute link TRB pointer */ 2925 trb_link = td_last->td_trb + td_last->ntrb; 2926 2927 /* update next pointer of last link TRB */ 2928 trb_link->qwTrb0 = htole64(addr); 2929 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2930 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2931 XHCI_TRB_3_CYCLE_BIT | 2932 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2933 2934 #ifdef USB_DEBUG 2935 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2936 #endif 2937 usb_pc_cpu_flush(td_last->page_cache); 2938 2939 /* write ahead chain end marker */ 2940 2941 pepext->trb[inext].qwTrb0 = 0; 2942 pepext->trb[inext].dwTrb2 = 0; 2943 pepext->trb[inext].dwTrb3 = 0; 2944 2945 /* update next pointer of link TRB */ 2946 2947 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2948 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2949 2950 #ifdef USB_DEBUG 2951 xhci_dump_trb(&pepext->trb[i]); 2952 #endif 2953 usb_pc_cpu_flush(pepext->page_cache); 2954 2955 /* toggle cycle bit which activates the transfer chain */ 2956 2957 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2958 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2959 2960 usb_pc_cpu_flush(pepext->page_cache); 2961 2962 DPRINTF("qh_pos = %u\n", i); 2963 2964 pepext->xfer[i] = xfer; 2965 2966 xfer->qh_pos = i; 2967 2968 xfer->flags_int.bandwidth_reclaimed = 1; 2969 2970 xhci_endpoint_doorbell(xfer); 2971 2972 return (0); 2973 } 2974 2975 static void 2976 xhci_root_intr(struct xhci_softc *sc) 2977 { 2978 uint16_t i; 2979 2980 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2981 2982 /* clear any old interrupt data */ 2983 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2984 2985 for (i = 1; i <= sc->sc_noport; i++) { 2986 /* pick out CHANGE bits from the status register */ 2987 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2988 XHCI_PS_CSC | XHCI_PS_PEC | 2989 XHCI_PS_OCC | XHCI_PS_WRC | 2990 XHCI_PS_PRC | XHCI_PS_PLC | 2991 XHCI_PS_CEC)) { 2992 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2993 DPRINTF("port %d changed\n", i); 2994 } 2995 } 2996 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2997 sizeof(sc->sc_hub_idata)); 2998 } 2999 3000 /*------------------------------------------------------------------------* 3001 * xhci_device_done - XHCI done handler 3002 * 3003 * NOTE: This function can be called two times in a row on 3004 * the same USB transfer. From close and from interrupt. 3005 *------------------------------------------------------------------------*/ 3006 static void 3007 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 3008 { 3009 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 3010 xfer, xfer->endpoint, error); 3011 3012 /* remove transfer from HW queue */ 3013 xhci_transfer_remove(xfer, error); 3014 3015 /* dequeue transfer and start next transfer */ 3016 usbd_transfer_done(xfer, error); 3017 } 3018 3019 /*------------------------------------------------------------------------* 3020 * XHCI data transfer support (generic type) 3021 *------------------------------------------------------------------------*/ 3022 static void 3023 xhci_device_generic_open(struct usb_xfer *xfer) 3024 { 3025 DPRINTF("\n"); 3026 } 3027 3028 static void 3029 xhci_device_generic_close(struct usb_xfer *xfer) 3030 { 3031 DPRINTF("\n"); 3032 3033 xhci_device_done(xfer, USB_ERR_CANCELLED); 3034 } 3035 3036 static void 3037 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3038 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3039 { 3040 struct usb_xfer *xfer; 3041 3042 /* check if there is a current transfer */ 3043 xfer = ep->endpoint_q[stream_id].curr; 3044 if (xfer == NULL) 3045 return; 3046 3047 /* 3048 * Check if the current transfer is started and then pickup 3049 * the next one, if any. Else wait for next start event due to 3050 * block on failure feature. 3051 */ 3052 if (!xfer->flags_int.bandwidth_reclaimed) 3053 return; 3054 3055 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3056 if (xfer == NULL) { 3057 /* 3058 * In case of enter we have to consider that the 3059 * transfer is queued by the USB core after the enter 3060 * method is called. 3061 */ 3062 xfer = enter_xfer; 3063 3064 if (xfer == NULL) 3065 return; 3066 } 3067 3068 /* try to multi buffer */ 3069 xhci_transfer_insert(xfer); 3070 } 3071 3072 static void 3073 xhci_device_generic_enter(struct usb_xfer *xfer) 3074 { 3075 DPRINTF("\n"); 3076 3077 /* set up TD's and QH */ 3078 xhci_setup_generic_chain(xfer); 3079 3080 xhci_device_generic_multi_enter(xfer->endpoint, 3081 xfer->stream_id, xfer); 3082 } 3083 3084 static void 3085 xhci_device_generic_start(struct usb_xfer *xfer) 3086 { 3087 DPRINTF("\n"); 3088 3089 /* try to insert xfer on HW queue */ 3090 xhci_transfer_insert(xfer); 3091 3092 /* try to multi buffer */ 3093 xhci_device_generic_multi_enter(xfer->endpoint, 3094 xfer->stream_id, NULL); 3095 3096 /* add transfer last on interrupt queue */ 3097 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3098 3099 /* start timeout, if any */ 3100 if (xfer->timeout != 0) 3101 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3102 } 3103 3104 static const struct usb_pipe_methods xhci_device_generic_methods = 3105 { 3106 .open = xhci_device_generic_open, 3107 .close = xhci_device_generic_close, 3108 .enter = xhci_device_generic_enter, 3109 .start = xhci_device_generic_start, 3110 }; 3111 3112 /*------------------------------------------------------------------------* 3113 * xhci root HUB support 3114 *------------------------------------------------------------------------* 3115 * Simulate a hardware HUB by handling all the necessary requests. 3116 *------------------------------------------------------------------------*/ 3117 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3118 3119 static const 3120 struct usb_device_descriptor xhci_devd = 3121 { 3122 .bLength = sizeof(xhci_devd), 3123 .bDescriptorType = UDESC_DEVICE, /* type */ 3124 HSETW(.bcdUSB, 0x0300), /* USB version */ 3125 .bDeviceClass = UDCLASS_HUB, /* class */ 3126 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3127 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3128 .bMaxPacketSize = 9, /* max packet size */ 3129 HSETW(.idVendor, 0x0000), /* vendor */ 3130 HSETW(.idProduct, 0x0000), /* product */ 3131 HSETW(.bcdDevice, 0x0100), /* device version */ 3132 .iManufacturer = 1, 3133 .iProduct = 2, 3134 .iSerialNumber = 0, 3135 .bNumConfigurations = 1, /* # of configurations */ 3136 }; 3137 3138 static const 3139 struct xhci_bos_desc xhci_bosd = { 3140 .bosd = { 3141 .bLength = sizeof(xhci_bosd.bosd), 3142 .bDescriptorType = UDESC_BOS, 3143 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3144 .bNumDeviceCaps = 3, 3145 }, 3146 .usb2extd = { 3147 .bLength = sizeof(xhci_bosd.usb2extd), 3148 .bDescriptorType = 1, 3149 .bDevCapabilityType = 2, 3150 .bmAttributes[0] = 2, 3151 }, 3152 .usbdcd = { 3153 .bLength = sizeof(xhci_bosd.usbdcd), 3154 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3155 .bDevCapabilityType = 3, 3156 .bmAttributes = 0, /* XXX */ 3157 HSETW(.wSpeedsSupported, 0x000C), 3158 .bFunctionalitySupport = 8, 3159 .bU1DevExitLat = 255, /* dummy - not used */ 3160 .wU2DevExitLat = { 0x00, 0x08 }, 3161 }, 3162 .cidd = { 3163 .bLength = sizeof(xhci_bosd.cidd), 3164 .bDescriptorType = 1, 3165 .bDevCapabilityType = 4, 3166 .bReserved = 0, 3167 .bContainerID = 0, /* XXX */ 3168 }, 3169 }; 3170 3171 static const 3172 struct xhci_config_desc xhci_confd = { 3173 .confd = { 3174 .bLength = sizeof(xhci_confd.confd), 3175 .bDescriptorType = UDESC_CONFIG, 3176 .wTotalLength[0] = sizeof(xhci_confd), 3177 .bNumInterface = 1, 3178 .bConfigurationValue = 1, 3179 .iConfiguration = 0, 3180 .bmAttributes = UC_SELF_POWERED, 3181 .bMaxPower = 0 /* max power */ 3182 }, 3183 .ifcd = { 3184 .bLength = sizeof(xhci_confd.ifcd), 3185 .bDescriptorType = UDESC_INTERFACE, 3186 .bNumEndpoints = 1, 3187 .bInterfaceClass = UICLASS_HUB, 3188 .bInterfaceSubClass = UISUBCLASS_HUB, 3189 .bInterfaceProtocol = 0, 3190 }, 3191 .endpd = { 3192 .bLength = sizeof(xhci_confd.endpd), 3193 .bDescriptorType = UDESC_ENDPOINT, 3194 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3195 .bmAttributes = UE_INTERRUPT, 3196 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3197 .bInterval = 255, 3198 }, 3199 .endpcd = { 3200 .bLength = sizeof(xhci_confd.endpcd), 3201 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3202 .bMaxBurst = 0, 3203 .bmAttributes = 0, 3204 }, 3205 }; 3206 3207 static const 3208 struct usb_hub_ss_descriptor xhci_hubd = { 3209 .bLength = sizeof(xhci_hubd), 3210 .bDescriptorType = UDESC_SS_HUB, 3211 }; 3212 3213 static usb_error_t 3214 xhci_roothub_exec(struct usb_device *udev, 3215 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3216 { 3217 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3218 const char *str_ptr; 3219 const void *ptr; 3220 uint32_t port; 3221 uint32_t v; 3222 uint16_t len; 3223 uint16_t i; 3224 uint16_t value; 3225 uint16_t index; 3226 uint8_t j; 3227 usb_error_t err; 3228 3229 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3230 3231 /* buffer reset */ 3232 ptr = (const void *)&sc->sc_hub_desc; 3233 len = 0; 3234 err = 0; 3235 3236 value = UGETW(req->wValue); 3237 index = UGETW(req->wIndex); 3238 3239 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3240 "wValue=0x%04x wIndex=0x%04x\n", 3241 req->bmRequestType, req->bRequest, 3242 UGETW(req->wLength), value, index); 3243 3244 #define C(x,y) ((x) | ((y) << 8)) 3245 switch (C(req->bRequest, req->bmRequestType)) { 3246 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3247 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3248 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3249 /* 3250 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3251 * for the integrated root hub. 3252 */ 3253 break; 3254 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3255 len = 1; 3256 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3257 break; 3258 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3259 switch (value >> 8) { 3260 case UDESC_DEVICE: 3261 if ((value & 0xff) != 0) { 3262 err = USB_ERR_IOERROR; 3263 goto done; 3264 } 3265 len = sizeof(xhci_devd); 3266 ptr = (const void *)&xhci_devd; 3267 break; 3268 3269 case UDESC_BOS: 3270 if ((value & 0xff) != 0) { 3271 err = USB_ERR_IOERROR; 3272 goto done; 3273 } 3274 len = sizeof(xhci_bosd); 3275 ptr = (const void *)&xhci_bosd; 3276 break; 3277 3278 case UDESC_CONFIG: 3279 if ((value & 0xff) != 0) { 3280 err = USB_ERR_IOERROR; 3281 goto done; 3282 } 3283 len = sizeof(xhci_confd); 3284 ptr = (const void *)&xhci_confd; 3285 break; 3286 3287 case UDESC_STRING: 3288 switch (value & 0xff) { 3289 case 0: /* Language table */ 3290 str_ptr = "\001"; 3291 break; 3292 3293 case 1: /* Vendor */ 3294 str_ptr = sc->sc_vendor; 3295 break; 3296 3297 case 2: /* Product */ 3298 str_ptr = "XHCI root HUB"; 3299 break; 3300 3301 default: 3302 str_ptr = ""; 3303 break; 3304 } 3305 3306 len = usb_make_str_desc( 3307 sc->sc_hub_desc.temp, 3308 sizeof(sc->sc_hub_desc.temp), 3309 str_ptr); 3310 break; 3311 3312 default: 3313 err = USB_ERR_IOERROR; 3314 goto done; 3315 } 3316 break; 3317 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3318 len = 1; 3319 sc->sc_hub_desc.temp[0] = 0; 3320 break; 3321 case C(UR_GET_STATUS, UT_READ_DEVICE): 3322 len = 2; 3323 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3324 break; 3325 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3326 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3327 len = 2; 3328 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3329 break; 3330 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3331 if (value >= XHCI_MAX_DEVICES) { 3332 err = USB_ERR_IOERROR; 3333 goto done; 3334 } 3335 break; 3336 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3337 if (value != 0 && value != 1) { 3338 err = USB_ERR_IOERROR; 3339 goto done; 3340 } 3341 sc->sc_conf = value; 3342 break; 3343 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3344 break; 3345 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3346 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3347 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3348 err = USB_ERR_IOERROR; 3349 goto done; 3350 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3351 break; 3352 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3353 break; 3354 /* Hub requests */ 3355 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3356 break; 3357 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3358 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3359 3360 if ((index < 1) || 3361 (index > sc->sc_noport)) { 3362 err = USB_ERR_IOERROR; 3363 goto done; 3364 } 3365 port = XHCI_PORTSC(index); 3366 3367 v = XREAD4(sc, oper, port); 3368 i = XHCI_PS_PLS_GET(v); 3369 v &= ~XHCI_PS_CLEAR; 3370 3371 switch (value) { 3372 case UHF_C_BH_PORT_RESET: 3373 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3374 break; 3375 case UHF_C_PORT_CONFIG_ERROR: 3376 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3377 break; 3378 case UHF_C_PORT_SUSPEND: 3379 case UHF_C_PORT_LINK_STATE: 3380 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3381 break; 3382 case UHF_C_PORT_CONNECTION: 3383 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3384 break; 3385 case UHF_C_PORT_ENABLE: 3386 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3387 break; 3388 case UHF_C_PORT_OVER_CURRENT: 3389 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3390 break; 3391 case UHF_C_PORT_RESET: 3392 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3393 break; 3394 case UHF_PORT_ENABLE: 3395 if ((sc->sc_quirks & XHCI_QUIRK_DISABLE_PORT_PED) == 0) 3396 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3397 break; 3398 case UHF_PORT_POWER: 3399 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3400 break; 3401 case UHF_PORT_INDICATOR: 3402 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3403 break; 3404 case UHF_PORT_SUSPEND: 3405 3406 /* U3 -> U15 */ 3407 if (i == 3) { 3408 XWRITE4(sc, oper, port, v | 3409 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3410 } 3411 3412 /* wait 20ms for resume sequence to complete */ 3413 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3414 3415 /* U0 */ 3416 XWRITE4(sc, oper, port, v | 3417 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3418 break; 3419 default: 3420 err = USB_ERR_IOERROR; 3421 goto done; 3422 } 3423 break; 3424 3425 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3426 if ((value & 0xff) != 0) { 3427 err = USB_ERR_IOERROR; 3428 goto done; 3429 } 3430 3431 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3432 3433 sc->sc_hub_desc.hubd = xhci_hubd; 3434 3435 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3436 3437 if (XHCI_HCS0_PPC(v)) 3438 i = UHD_PWR_INDIVIDUAL; 3439 else 3440 i = UHD_PWR_GANGED; 3441 3442 if (XHCI_HCS0_PIND(v)) 3443 i |= UHD_PORT_IND; 3444 3445 i |= UHD_OC_INDIVIDUAL; 3446 3447 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3448 3449 /* see XHCI section 5.4.9: */ 3450 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3451 3452 for (j = 1; j <= sc->sc_noport; j++) { 3453 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3454 if (v & XHCI_PS_DR) { 3455 sc->sc_hub_desc.hubd. 3456 DeviceRemovable[j / 8] |= 1U << (j % 8); 3457 } 3458 } 3459 len = sc->sc_hub_desc.hubd.bLength; 3460 break; 3461 3462 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3463 len = 16; 3464 memset(sc->sc_hub_desc.temp, 0, 16); 3465 break; 3466 3467 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3468 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3469 3470 if ((index < 1) || 3471 (index > sc->sc_noport)) { 3472 err = USB_ERR_IOERROR; 3473 goto done; 3474 } 3475 3476 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3477 3478 DPRINTFN(9, "port status=0x%08x\n", v); 3479 3480 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3481 3482 switch (XHCI_PS_SPEED_GET(v)) { 3483 case XHCI_PS_SPEED_HIGH: 3484 i |= UPS_HIGH_SPEED; 3485 break; 3486 case XHCI_PS_SPEED_LOW: 3487 i |= UPS_LOW_SPEED; 3488 break; 3489 case XHCI_PS_SPEED_FULL: 3490 /* FULL speed */ 3491 break; 3492 default: 3493 i |= UPS_OTHER_SPEED; 3494 break; 3495 } 3496 3497 if (v & XHCI_PS_CCS) 3498 i |= UPS_CURRENT_CONNECT_STATUS; 3499 if (v & XHCI_PS_PED) 3500 i |= UPS_PORT_ENABLED; 3501 if (v & XHCI_PS_OCA) 3502 i |= UPS_OVERCURRENT_INDICATOR; 3503 if (v & XHCI_PS_PR) 3504 i |= UPS_RESET; 3505 #if 0 3506 if (v & XHCI_PS_PP) 3507 /* XXX undefined */ 3508 #endif 3509 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3510 3511 i = 0; 3512 if (v & XHCI_PS_CSC) 3513 i |= UPS_C_CONNECT_STATUS; 3514 if (v & XHCI_PS_PEC) 3515 i |= UPS_C_PORT_ENABLED; 3516 if (v & XHCI_PS_OCC) 3517 i |= UPS_C_OVERCURRENT_INDICATOR; 3518 if (v & XHCI_PS_WRC) 3519 i |= UPS_C_BH_PORT_RESET; 3520 if (v & XHCI_PS_PRC) 3521 i |= UPS_C_PORT_RESET; 3522 if (v & XHCI_PS_PLC) 3523 i |= UPS_C_PORT_LINK_STATE; 3524 if (v & XHCI_PS_CEC) 3525 i |= UPS_C_PORT_CONFIG_ERROR; 3526 3527 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3528 len = sizeof(sc->sc_hub_desc.ps); 3529 break; 3530 3531 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3532 err = USB_ERR_IOERROR; 3533 goto done; 3534 3535 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3536 break; 3537 3538 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3539 3540 i = index >> 8; 3541 index &= 0x00FF; 3542 3543 if ((index < 1) || 3544 (index > sc->sc_noport)) { 3545 err = USB_ERR_IOERROR; 3546 goto done; 3547 } 3548 3549 port = XHCI_PORTSC(index); 3550 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3551 3552 switch (value) { 3553 case UHF_PORT_U1_TIMEOUT: 3554 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3555 err = USB_ERR_IOERROR; 3556 goto done; 3557 } 3558 port = XHCI_PORTPMSC(index); 3559 v = XREAD4(sc, oper, port); 3560 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3561 v |= XHCI_PM3_U1TO_SET(i); 3562 XWRITE4(sc, oper, port, v); 3563 break; 3564 case UHF_PORT_U2_TIMEOUT: 3565 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3566 err = USB_ERR_IOERROR; 3567 goto done; 3568 } 3569 port = XHCI_PORTPMSC(index); 3570 v = XREAD4(sc, oper, port); 3571 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3572 v |= XHCI_PM3_U2TO_SET(i); 3573 XWRITE4(sc, oper, port, v); 3574 break; 3575 case UHF_BH_PORT_RESET: 3576 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3577 break; 3578 case UHF_PORT_LINK_STATE: 3579 XWRITE4(sc, oper, port, v | 3580 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3581 /* 4ms settle time */ 3582 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3583 break; 3584 case UHF_PORT_ENABLE: 3585 DPRINTFN(3, "set port enable %d\n", index); 3586 break; 3587 case UHF_PORT_SUSPEND: 3588 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3589 j = XHCI_PS_SPEED_GET(v); 3590 if (j == 0 || j >= XHCI_PS_SPEED_SS) { 3591 /* non-supported speed */ 3592 err = USB_ERR_IOERROR; 3593 goto done; 3594 } 3595 XWRITE4(sc, oper, port, v | 3596 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3597 break; 3598 case UHF_PORT_RESET: 3599 DPRINTFN(6, "reset port %d\n", index); 3600 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3601 break; 3602 case UHF_PORT_POWER: 3603 DPRINTFN(3, "set port power %d\n", index); 3604 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3605 break; 3606 case UHF_PORT_TEST: 3607 DPRINTFN(3, "set port test %d\n", index); 3608 break; 3609 case UHF_PORT_INDICATOR: 3610 DPRINTFN(3, "set port indicator %d\n", index); 3611 3612 v &= ~XHCI_PS_PIC_SET(3); 3613 v |= XHCI_PS_PIC_SET(1); 3614 3615 XWRITE4(sc, oper, port, v); 3616 break; 3617 default: 3618 err = USB_ERR_IOERROR; 3619 goto done; 3620 } 3621 break; 3622 3623 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3624 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3625 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3626 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3627 break; 3628 default: 3629 err = USB_ERR_IOERROR; 3630 goto done; 3631 } 3632 done: 3633 *plength = len; 3634 *pptr = ptr; 3635 return (err); 3636 } 3637 3638 static void 3639 xhci_xfer_setup(struct usb_setup_params *parm) 3640 { 3641 struct usb_page_search page_info; 3642 struct usb_page_cache *pc; 3643 struct usb_xfer *xfer; 3644 void *last_obj; 3645 uint32_t ntd; 3646 uint32_t n; 3647 3648 xfer = parm->curr_xfer; 3649 3650 /* 3651 * The proof for the "ntd" formula is illustrated like this: 3652 * 3653 * +------------------------------------+ 3654 * | | 3655 * | |remainder -> | 3656 * | +-----+---+ | 3657 * | | xxx | x | frm 0 | 3658 * | +-----+---++ | 3659 * | | xxx | xx | frm 1 | 3660 * | +-----+----+ | 3661 * | ... | 3662 * +------------------------------------+ 3663 * 3664 * "xxx" means a completely full USB transfer descriptor 3665 * 3666 * "x" and "xx" means a short USB packet 3667 * 3668 * For the remainder of an USB transfer modulo 3669 * "max_data_length" we need two USB transfer descriptors. 3670 * One to transfer the remaining data and one to finalise with 3671 * a zero length packet in case the "force_short_xfer" flag is 3672 * set. We only need two USB transfer descriptors in the case 3673 * where the transfer length of the first one is a factor of 3674 * "max_frame_size". The rest of the needed USB transfer 3675 * descriptors is given by the buffer size divided by the 3676 * maximum data payload. 3677 */ 3678 parm->hc_max_packet_size = 0x400; 3679 parm->hc_max_packet_count = 16 * 3; 3680 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3681 3682 xfer->flags_int.bdma_enable = 1; 3683 3684 usbd_transfer_setup_sub(parm); 3685 3686 if (xfer->flags_int.isochronous_xfr) { 3687 ntd = ((1 * xfer->nframes) 3688 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3689 } else if (xfer->flags_int.control_xfr) { 3690 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3691 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3692 } else { 3693 ntd = ((2 * xfer->nframes) 3694 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3695 } 3696 3697 alloc_dma_set: 3698 3699 if (parm->err) 3700 return; 3701 3702 /* 3703 * Allocate queue heads and transfer descriptors 3704 */ 3705 last_obj = NULL; 3706 3707 if (usbd_transfer_setup_sub_malloc( 3708 parm, &pc, sizeof(struct xhci_td), 3709 XHCI_TD_ALIGN, ntd)) { 3710 parm->err = USB_ERR_NOMEM; 3711 return; 3712 } 3713 if (parm->buf) { 3714 for (n = 0; n != ntd; n++) { 3715 struct xhci_td *td; 3716 3717 usbd_get_page(pc + n, 0, &page_info); 3718 3719 td = page_info.buffer; 3720 3721 /* init TD */ 3722 td->td_self = page_info.physaddr; 3723 td->obj_next = last_obj; 3724 td->page_cache = pc + n; 3725 3726 last_obj = td; 3727 3728 usb_pc_cpu_flush(pc + n); 3729 } 3730 } 3731 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3732 3733 if (!xfer->flags_int.curr_dma_set) { 3734 xfer->flags_int.curr_dma_set = 1; 3735 goto alloc_dma_set; 3736 } 3737 } 3738 3739 static uint8_t 3740 xhci_get_endpoint_state(struct usb_device *udev, uint8_t epno) 3741 { 3742 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3743 struct usb_page_search buf_dev; 3744 struct xhci_hw_dev *hdev; 3745 struct xhci_endp_ctx *endp; 3746 uint32_t temp; 3747 3748 MPASS(epno != 0); 3749 3750 hdev = &sc->sc_hw.devs[udev->controller_slot_id]; 3751 3752 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 3753 endp = XHCI_GET_CTX(sc, xhci_dev_ctx, ctx_ep[epno - 1], 3754 buf_dev.buffer); 3755 usb_pc_cpu_invalidate(&hdev->device_pc); 3756 3757 temp = le32toh(endp->dwEpCtx0); 3758 3759 return (XHCI_EPCTX_0_EPSTATE_GET(temp)); 3760 } 3761 3762 static usb_error_t 3763 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3764 { 3765 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3766 struct usb_page_search buf_inp; 3767 struct usb_device *udev; 3768 struct xhci_endpoint_ext *pepext; 3769 struct usb_endpoint_descriptor *edesc; 3770 struct usb_page_cache *pcinp; 3771 usb_error_t err; 3772 usb_stream_t stream_id; 3773 uint32_t mask; 3774 uint8_t index; 3775 uint8_t epno; 3776 uint8_t drop; 3777 3778 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3779 xfer->endpoint->edesc); 3780 3781 udev = xfer->xroot->udev; 3782 index = udev->controller_slot_id; 3783 3784 pcinp = &sc->sc_hw.devs[index].input_pc; 3785 3786 usbd_get_page(pcinp, 0, &buf_inp); 3787 3788 edesc = xfer->endpoint->edesc; 3789 3790 epno = edesc->bEndpointAddress; 3791 stream_id = xfer->stream_id; 3792 3793 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3794 epno |= UE_DIR_IN; 3795 3796 epno = XHCI_EPNO2EPID(epno); 3797 3798 if (epno == 0) 3799 return (USB_ERR_NO_PIPE); /* invalid */ 3800 3801 XHCI_CMD_LOCK(sc); 3802 3803 /* configure endpoint */ 3804 3805 err = xhci_configure_endpoint_by_xfer(xfer); 3806 3807 if (err != 0) { 3808 XHCI_CMD_UNLOCK(sc); 3809 return (err); 3810 } 3811 3812 /* 3813 * Get the endpoint into the stopped state according to the 3814 * endpoint context state diagram in the XHCI specification: 3815 */ 3816 switch (xhci_get_endpoint_state(udev, epno)) { 3817 case XHCI_EPCTX_0_EPSTATE_DISABLED: 3818 drop = 0; 3819 break; 3820 case XHCI_EPCTX_0_EPSTATE_STOPPED: 3821 drop = 1; 3822 break; 3823 case XHCI_EPCTX_0_EPSTATE_HALTED: 3824 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3825 drop = (err != 0); 3826 if (drop) 3827 DPRINTF("Could not reset endpoint %u\n", epno); 3828 break; 3829 default: 3830 drop = 1; 3831 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3832 if (err != 0) 3833 DPRINTF("Could not stop endpoint %u\n", epno); 3834 break; 3835 } 3836 3837 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3838 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3839 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3840 stream_id, epno, index); 3841 3842 if (err != 0) 3843 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3844 3845 /* 3846 * Get the endpoint into the running state according to the 3847 * endpoint context state diagram in the XHCI specification: 3848 */ 3849 3850 mask = (1U << epno); 3851 3852 /* 3853 * So-called control and isochronous transfer types have 3854 * predefined data toggles (USB 2.0) or sequence numbers (USB 3855 * 3.0) and does not need to be dropped. 3856 */ 3857 if (drop != 0 && 3858 (edesc->bmAttributes & UE_XFERTYPE) != UE_CONTROL && 3859 (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) { 3860 /* drop endpoint context to reset data toggle value, if any. */ 3861 xhci_configure_mask(udev, mask, 1); 3862 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3863 if (err != 0) { 3864 DPRINTF("Could not drop " 3865 "endpoint %u at slot %u.\n", epno, index); 3866 } else { 3867 sc->sc_hw.devs[index].ep_configured &= ~mask; 3868 } 3869 } 3870 3871 /* 3872 * Always need to evaluate the slot context, because the maximum 3873 * number of endpoint contexts is stored there. 3874 */ 3875 xhci_configure_mask(udev, mask | 1U, 0); 3876 3877 if (!(sc->sc_hw.devs[index].ep_configured & mask)) { 3878 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3879 if (err == 0) 3880 sc->sc_hw.devs[index].ep_configured |= mask; 3881 } else { 3882 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3883 } 3884 3885 if (err != 0) { 3886 DPRINTF("Could not configure " 3887 "endpoint %u at slot %u.\n", epno, index); 3888 } 3889 XHCI_CMD_UNLOCK(sc); 3890 3891 return (0); 3892 } 3893 3894 static void 3895 xhci_xfer_unsetup(struct usb_xfer *xfer) 3896 { 3897 return; 3898 } 3899 3900 static void 3901 xhci_start_dma_delay(struct usb_xfer *xfer) 3902 { 3903 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3904 3905 /* put transfer on interrupt queue (again) */ 3906 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3907 3908 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3909 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3910 } 3911 3912 static void 3913 xhci_configure_msg(struct usb_proc_msg *pm) 3914 { 3915 struct xhci_softc *sc; 3916 struct xhci_endpoint_ext *pepext; 3917 struct usb_xfer *xfer; 3918 3919 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3920 3921 restart: 3922 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3923 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3924 xfer->endpoint->edesc); 3925 3926 if ((pepext->trb_halted != 0) || 3927 (pepext->trb_running == 0)) { 3928 uint16_t i; 3929 3930 /* clear halted and running */ 3931 pepext->trb_halted = 0; 3932 pepext->trb_running = 0; 3933 3934 /* nuke remaining buffered transfers */ 3935 3936 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3937 XHCI_MAX_STREAMS); i++) { 3938 /* 3939 * NOTE: We need to use the timeout 3940 * error code here else existing 3941 * isochronous clients can get 3942 * confused: 3943 */ 3944 if (pepext->xfer[i] != NULL) { 3945 xhci_device_done(pepext->xfer[i], 3946 USB_ERR_TIMEOUT); 3947 } 3948 } 3949 3950 /* 3951 * NOTE: The USB transfer cannot vanish in 3952 * this state! 3953 */ 3954 3955 USB_BUS_UNLOCK(&sc->sc_bus); 3956 3957 xhci_configure_reset_endpoint(xfer); 3958 3959 USB_BUS_LOCK(&sc->sc_bus); 3960 3961 /* check if halted is still cleared */ 3962 if (pepext->trb_halted == 0) { 3963 pepext->trb_running = 1; 3964 memset(pepext->trb_index, 0, 3965 sizeof(pepext->trb_index)); 3966 } 3967 goto restart; 3968 } 3969 3970 if (xfer->flags_int.did_dma_delay) { 3971 /* remove transfer from interrupt queue (again) */ 3972 usbd_transfer_dequeue(xfer); 3973 3974 /* we are finally done */ 3975 usb_dma_delay_done_cb(xfer); 3976 3977 /* queue changed - restart */ 3978 goto restart; 3979 } 3980 } 3981 3982 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3983 /* try to insert xfer on HW queue */ 3984 xhci_transfer_insert(xfer); 3985 3986 /* try to multi buffer */ 3987 xhci_device_generic_multi_enter(xfer->endpoint, 3988 xfer->stream_id, NULL); 3989 } 3990 } 3991 3992 static void 3993 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3994 struct usb_endpoint *ep) 3995 { 3996 struct xhci_endpoint_ext *pepext; 3997 struct xhci_softc *sc; 3998 uint8_t index; 3999 uint8_t epno; 4000 4001 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 4002 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 4003 4004 if (udev->parent_hub == NULL) { 4005 /* root HUB has special endpoint handling */ 4006 return; 4007 } 4008 4009 ep->methods = &xhci_device_generic_methods; 4010 4011 pepext = xhci_get_endpoint_ext(udev, edesc); 4012 4013 USB_BUS_LOCK(udev->bus); 4014 pepext->trb_halted = 1; 4015 pepext->trb_running = 0; 4016 4017 /* 4018 * When doing an alternate setting, except for control 4019 * endpoints, we need to re-configure the XHCI endpoint 4020 * context: 4021 */ 4022 if ((edesc->bEndpointAddress & UE_ADDR) != 0) { 4023 sc = XHCI_BUS2SC(udev->bus); 4024 index = udev->controller_slot_id; 4025 epno = XHCI_EPNO2EPID(edesc->bEndpointAddress); 4026 sc->sc_hw.devs[index].ep_configured &= ~(1U << epno); 4027 } 4028 USB_BUS_UNLOCK(udev->bus); 4029 } 4030 4031 static void 4032 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 4033 { 4034 4035 } 4036 4037 static void 4038 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 4039 { 4040 struct xhci_endpoint_ext *pepext; 4041 4042 DPRINTF("\n"); 4043 4044 if (udev->flags.usb_mode != USB_MODE_HOST) { 4045 /* not supported */ 4046 return; 4047 } 4048 if (udev->parent_hub == NULL) { 4049 /* root HUB has special endpoint handling */ 4050 return; 4051 } 4052 4053 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 4054 4055 USB_BUS_LOCK(udev->bus); 4056 pepext->trb_halted = 1; 4057 pepext->trb_running = 0; 4058 USB_BUS_UNLOCK(udev->bus); 4059 } 4060 4061 static usb_error_t 4062 xhci_device_init(struct usb_device *udev) 4063 { 4064 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4065 usb_error_t err; 4066 uint8_t temp; 4067 4068 /* no init for root HUB */ 4069 if (udev->parent_hub == NULL) 4070 return (0); 4071 4072 XHCI_CMD_LOCK(sc); 4073 4074 /* set invalid default */ 4075 4076 udev->controller_slot_id = sc->sc_noslot + 1; 4077 4078 /* try to get a new slot ID from the XHCI */ 4079 4080 err = xhci_cmd_enable_slot(sc, &temp); 4081 4082 if (err) { 4083 XHCI_CMD_UNLOCK(sc); 4084 return (err); 4085 } 4086 4087 if (temp > sc->sc_noslot) { 4088 XHCI_CMD_UNLOCK(sc); 4089 return (USB_ERR_BAD_ADDRESS); 4090 } 4091 4092 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4093 DPRINTF("slot %u already allocated.\n", temp); 4094 XHCI_CMD_UNLOCK(sc); 4095 return (USB_ERR_BAD_ADDRESS); 4096 } 4097 4098 /* store slot ID for later reference */ 4099 4100 udev->controller_slot_id = temp; 4101 4102 /* reset data structure */ 4103 4104 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4105 4106 /* set mark slot allocated */ 4107 4108 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4109 4110 err = xhci_alloc_device_ext(udev); 4111 4112 XHCI_CMD_UNLOCK(sc); 4113 4114 /* get device into default state */ 4115 4116 if (err == 0) 4117 err = xhci_set_address(udev, NULL, 0); 4118 4119 return (err); 4120 } 4121 4122 static void 4123 xhci_device_uninit(struct usb_device *udev) 4124 { 4125 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4126 uint8_t index; 4127 4128 /* no init for root HUB */ 4129 if (udev->parent_hub == NULL) 4130 return; 4131 4132 XHCI_CMD_LOCK(sc); 4133 4134 index = udev->controller_slot_id; 4135 4136 if (index <= sc->sc_noslot) { 4137 xhci_cmd_disable_slot(sc, index); 4138 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4139 4140 /* free device extension */ 4141 xhci_free_device_ext(udev); 4142 } 4143 4144 XHCI_CMD_UNLOCK(sc); 4145 } 4146 4147 static void 4148 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4149 { 4150 /* 4151 * Wait until the hardware has finished any possible use of 4152 * the transfer descriptor(s) 4153 */ 4154 *pus = 2048; /* microseconds */ 4155 } 4156 4157 static void 4158 xhci_device_resume(struct usb_device *udev) 4159 { 4160 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4161 uint8_t index; 4162 uint8_t n; 4163 uint8_t p; 4164 4165 DPRINTF("\n"); 4166 4167 /* check for root HUB */ 4168 if (udev->parent_hub == NULL) 4169 return; 4170 4171 index = udev->controller_slot_id; 4172 4173 XHCI_CMD_LOCK(sc); 4174 4175 /* blindly resume all endpoints */ 4176 4177 USB_BUS_LOCK(udev->bus); 4178 4179 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4180 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4181 XWRITE4(sc, door, XHCI_DOORBELL(index), 4182 n | XHCI_DB_SID_SET(p)); 4183 } 4184 } 4185 4186 USB_BUS_UNLOCK(udev->bus); 4187 4188 XHCI_CMD_UNLOCK(sc); 4189 } 4190 4191 static void 4192 xhci_device_suspend(struct usb_device *udev) 4193 { 4194 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4195 uint8_t index; 4196 uint8_t n; 4197 usb_error_t err; 4198 4199 DPRINTF("\n"); 4200 4201 /* check for root HUB */ 4202 if (udev->parent_hub == NULL) 4203 return; 4204 4205 index = udev->controller_slot_id; 4206 4207 XHCI_CMD_LOCK(sc); 4208 4209 /* blindly suspend all endpoints */ 4210 4211 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4212 err = xhci_cmd_stop_ep(sc, 1, n, index); 4213 if (err != 0) { 4214 DPRINTF("Failed to suspend endpoint " 4215 "%u on slot %u (ignored).\n", n, index); 4216 } 4217 } 4218 4219 XHCI_CMD_UNLOCK(sc); 4220 } 4221 4222 static void 4223 xhci_set_hw_power(struct usb_bus *bus) 4224 { 4225 DPRINTF("\n"); 4226 } 4227 4228 static void 4229 xhci_device_state_change(struct usb_device *udev) 4230 { 4231 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4232 struct usb_page_search buf_inp; 4233 usb_error_t err; 4234 uint8_t index; 4235 4236 /* check for root HUB */ 4237 if (udev->parent_hub == NULL) 4238 return; 4239 4240 index = udev->controller_slot_id; 4241 4242 DPRINTF("\n"); 4243 4244 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4245 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4246 &sc->sc_hw.devs[index].tt); 4247 if (err != 0) 4248 sc->sc_hw.devs[index].nports = 0; 4249 } 4250 4251 XHCI_CMD_LOCK(sc); 4252 4253 switch (usb_get_device_state(udev)) { 4254 case USB_STATE_POWERED: 4255 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4256 break; 4257 4258 /* set default state */ 4259 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4260 sc->sc_hw.devs[index].ep_configured = 3U; 4261 4262 /* reset number of contexts */ 4263 sc->sc_hw.devs[index].context_num = 0; 4264 4265 err = xhci_cmd_reset_dev(sc, index); 4266 4267 if (err != 0) { 4268 DPRINTF("Device reset failed " 4269 "for slot %u.\n", index); 4270 } 4271 break; 4272 4273 case USB_STATE_ADDRESSED: 4274 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4275 break; 4276 4277 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4278 sc->sc_hw.devs[index].ep_configured = 3U; 4279 4280 /* set configure mask to slot only */ 4281 xhci_configure_mask(udev, 1, 0); 4282 4283 /* deconfigure all endpoints, except EP0 */ 4284 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4285 4286 if (err) { 4287 DPRINTF("Failed to deconfigure " 4288 "slot %u.\n", index); 4289 } 4290 break; 4291 4292 case USB_STATE_CONFIGURED: 4293 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) { 4294 /* deconfigure all endpoints, except EP0 */ 4295 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4296 4297 if (err) { 4298 DPRINTF("Failed to deconfigure " 4299 "slot %u.\n", index); 4300 } 4301 } 4302 4303 /* set configured state */ 4304 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4305 sc->sc_hw.devs[index].ep_configured = 3U; 4306 4307 /* reset number of contexts */ 4308 sc->sc_hw.devs[index].context_num = 0; 4309 4310 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4311 4312 xhci_configure_mask(udev, 3, 0); 4313 4314 err = xhci_configure_device(udev); 4315 if (err != 0) { 4316 DPRINTF("Could not configure device " 4317 "at slot %u.\n", index); 4318 } 4319 4320 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4321 if (err != 0) { 4322 DPRINTF("Could not evaluate device " 4323 "context at slot %u.\n", index); 4324 } 4325 break; 4326 4327 default: 4328 break; 4329 } 4330 XHCI_CMD_UNLOCK(sc); 4331 } 4332 4333 static usb_error_t 4334 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4335 uint8_t ep_mode) 4336 { 4337 switch (ep_mode) { 4338 case USB_EP_MODE_DEFAULT: 4339 return (0); 4340 case USB_EP_MODE_STREAMS: 4341 if (xhcistreams == 0 || 4342 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4343 udev->speed != USB_SPEED_SUPER) 4344 return (USB_ERR_INVAL); 4345 return (0); 4346 default: 4347 return (USB_ERR_INVAL); 4348 } 4349 } 4350 4351 static const struct usb_bus_methods xhci_bus_methods = { 4352 .endpoint_init = xhci_ep_init, 4353 .endpoint_uninit = xhci_ep_uninit, 4354 .xfer_setup = xhci_xfer_setup, 4355 .xfer_unsetup = xhci_xfer_unsetup, 4356 .get_dma_delay = xhci_get_dma_delay, 4357 .device_init = xhci_device_init, 4358 .device_uninit = xhci_device_uninit, 4359 .device_resume = xhci_device_resume, 4360 .device_suspend = xhci_device_suspend, 4361 .set_hw_power = xhci_set_hw_power, 4362 .roothub_exec = xhci_roothub_exec, 4363 .xfer_poll = xhci_do_poll, 4364 .start_dma_delay = xhci_start_dma_delay, 4365 .set_address = xhci_set_address, 4366 .clear_stall = xhci_ep_clear_stall, 4367 .device_state_change = xhci_device_state_change, 4368 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4369 .set_endpoint_mode = xhci_set_endpoint_mode, 4370 }; 4371