1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010-2022 Hans Petter Selasky 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 30 * 31 * The XHCI 1.0 spec can be found at 32 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 33 * and the USB 3.0 spec at 34 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 35 */ 36 37 /* 38 * A few words about the design implementation: This driver emulates 39 * the concept about TDs which is found in EHCI specification. This 40 * way we achieve that the USB controller drivers look similar to 41 * eachother which makes it easier to understand the code. 42 */ 43 44 #ifdef USB_GLOBAL_INCLUDE_FILE 45 #include USB_GLOBAL_INCLUDE_FILE 46 #else 47 #include <sys/stdint.h> 48 #include <sys/stddef.h> 49 #include <sys/param.h> 50 #include <sys/queue.h> 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 #include <sys/kernel.h> 54 #include <sys/bus.h> 55 #include <sys/module.h> 56 #include <sys/lock.h> 57 #include <sys/mutex.h> 58 #include <sys/condvar.h> 59 #include <sys/sysctl.h> 60 #include <sys/sx.h> 61 #include <sys/unistd.h> 62 #include <sys/callout.h> 63 #include <sys/malloc.h> 64 #include <sys/priv.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 69 #define USB_DEBUG_VAR xhcidebug 70 71 #include <dev/usb/usb_core.h> 72 #include <dev/usb/usb_debug.h> 73 #include <dev/usb/usb_busdma.h> 74 #include <dev/usb/usb_process.h> 75 #include <dev/usb/usb_transfer.h> 76 #include <dev/usb/usb_device.h> 77 #include <dev/usb/usb_hub.h> 78 #include <dev/usb/usb_util.h> 79 80 #include <dev/usb/usb_controller.h> 81 #include <dev/usb/usb_bus.h> 82 #endif /* USB_GLOBAL_INCLUDE_FILE */ 83 84 #include <dev/usb/controller/xhci.h> 85 #include <dev/usb/controller/xhcireg.h> 86 87 #define XHCI_BUS2SC(bus) \ 88 __containerof(bus, struct xhci_softc, sc_bus) 89 90 #define XHCI_GET_CTX(sc, which, field, ptr) \ 91 ((sc)->sc_ctx_is_64_byte ? \ 92 &((struct which##64 *)(ptr))->field.ctx : \ 93 &((struct which *)(ptr))->field) 94 95 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 96 "USB XHCI"); 97 98 static int xhcistreams; 99 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN, 100 &xhcistreams, 0, "Set to enable streams mode support"); 101 102 static int xhcictlquirk = 1; 103 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlquirk, CTLFLAG_RWTUN, 104 &xhcictlquirk, 0, "Set to enable control endpoint quirk"); 105 106 static int xhcidcepquirk; 107 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dcepquirk, CTLFLAG_RWTUN, 108 &xhcidcepquirk, 0, "Set to disable endpoint deconfigure command"); 109 110 #ifdef USB_DEBUG 111 static int xhcidebug; 112 static int xhciroute; 113 static int xhcipolling; 114 static int xhcidma32; 115 static int xhcictlstep; 116 117 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN, 118 &xhcidebug, 0, "Debug level"); 119 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN, 120 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller"); 121 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN, 122 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller"); 123 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN, 124 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller"); 125 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN, 126 &xhcictlstep, 0, "Set to enable control endpoint status stage stepping"); 127 #else 128 #define xhciroute 0 129 #define xhcidma32 0 130 #define xhcictlstep 0 131 #endif 132 133 #define XHCI_INTR_ENDPT 1 134 135 struct xhci_std_temp { 136 struct xhci_softc *sc; 137 struct usb_page_cache *pc; 138 struct xhci_td *td; 139 struct xhci_td *td_next; 140 uint32_t len; 141 uint32_t offset; 142 uint32_t max_packet_size; 143 uint32_t average; 144 uint32_t isoc_frame; 145 uint16_t isoc_delta; 146 uint8_t shortpkt; 147 uint8_t multishort; 148 uint8_t last_frame; 149 uint8_t trb_type; 150 uint8_t direction; 151 uint8_t tbc; 152 uint8_t tlbpc; 153 uint8_t step_td; 154 uint8_t do_isoc_sync; 155 }; 156 157 static void xhci_do_poll(struct usb_bus *); 158 static void xhci_device_done(struct usb_xfer *, usb_error_t); 159 static void xhci_get_xecp(struct xhci_softc *); 160 static void xhci_root_intr(struct xhci_softc *); 161 static void xhci_free_device_ext(struct usb_device *); 162 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 163 struct usb_endpoint_descriptor *); 164 static usb_proc_callback_t xhci_configure_msg; 165 static usb_error_t xhci_configure_device(struct usb_device *); 166 static usb_error_t xhci_configure_endpoint(struct usb_device *, 167 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 168 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 169 uint8_t); 170 static usb_error_t xhci_configure_mask(struct usb_device *, 171 uint32_t, uint8_t); 172 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 173 uint64_t, uint8_t); 174 static void xhci_endpoint_doorbell(struct usb_xfer *); 175 176 static const struct usb_bus_methods xhci_bus_methods; 177 178 #ifdef USB_DEBUG 179 static void 180 xhci_dump_trb(struct xhci_trb *trb) 181 { 182 DPRINTFN(5, "trb = %p\n", trb); 183 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 184 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 185 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 186 } 187 188 static void 189 xhci_dump_endpoint(struct xhci_endp_ctx *pep) 190 { 191 DPRINTFN(5, "pep = %p\n", pep); 192 DPRINTFN(5, "dwEpCtx0=0x%08x\n", le32toh(pep->dwEpCtx0)); 193 DPRINTFN(5, "dwEpCtx1=0x%08x\n", le32toh(pep->dwEpCtx1)); 194 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)le64toh(pep->qwEpCtx2)); 195 DPRINTFN(5, "dwEpCtx4=0x%08x\n", le32toh(pep->dwEpCtx4)); 196 DPRINTFN(5, "dwEpCtx5=0x%08x\n", le32toh(pep->dwEpCtx5)); 197 DPRINTFN(5, "dwEpCtx6=0x%08x\n", le32toh(pep->dwEpCtx6)); 198 DPRINTFN(5, "dwEpCtx7=0x%08x\n", le32toh(pep->dwEpCtx7)); 199 } 200 201 static void 202 xhci_dump_device(struct xhci_slot_ctx *psl) 203 { 204 DPRINTFN(5, "psl = %p\n", psl); 205 DPRINTFN(5, "dwSctx0=0x%08x\n", le32toh(psl->dwSctx0)); 206 DPRINTFN(5, "dwSctx1=0x%08x\n", le32toh(psl->dwSctx1)); 207 DPRINTFN(5, "dwSctx2=0x%08x\n", le32toh(psl->dwSctx2)); 208 DPRINTFN(5, "dwSctx3=0x%08x\n", le32toh(psl->dwSctx3)); 209 } 210 #endif 211 212 uint8_t 213 xhci_use_polling(void) 214 { 215 #ifdef USB_DEBUG 216 return (xhcipolling != 0); 217 #else 218 return (0); 219 #endif 220 } 221 222 static void 223 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 224 { 225 struct xhci_softc *sc = XHCI_BUS2SC(bus); 226 uint16_t i; 227 228 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 229 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 230 231 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 232 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 233 234 for (i = 0; i != sc->sc_noscratch; i++) { 235 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 236 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 237 } 238 } 239 240 static int 241 xhci_reset_command_queue_locked(struct xhci_softc *sc) 242 { 243 struct usb_page_search buf_res; 244 struct xhci_hw_root *phwr; 245 uint64_t addr; 246 uint32_t temp; 247 248 DPRINTF("\n"); 249 250 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 251 if (temp & XHCI_CRCR_LO_CRR) { 252 DPRINTF("Command ring running\n"); 253 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 254 255 /* 256 * Try to abort the last command as per section 257 * 4.6.1.2 "Aborting a Command" of the XHCI 258 * specification: 259 */ 260 261 /* stop and cancel */ 262 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 263 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 264 265 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 266 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 267 268 /* wait 250ms */ 269 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 270 271 /* check if command ring is still running */ 272 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 273 if (temp & XHCI_CRCR_LO_CRR) { 274 DPRINTF("Comand ring still running\n"); 275 return (USB_ERR_IOERROR); 276 } 277 } 278 279 /* reset command ring */ 280 sc->sc_command_ccs = 1; 281 sc->sc_command_idx = 0; 282 283 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 284 285 /* set up command ring control base address */ 286 addr = buf_res.physaddr; 287 phwr = buf_res.buffer; 288 addr += __offsetof(struct xhci_hw_root, hwr_commands[0]); 289 290 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 291 292 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 293 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 294 295 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 296 297 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 298 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 299 300 return (0); 301 } 302 303 usb_error_t 304 xhci_start_controller(struct xhci_softc *sc) 305 { 306 struct usb_page_search buf_res; 307 struct xhci_hw_root *phwr; 308 struct xhci_dev_ctx_addr *pdctxa; 309 usb_error_t err; 310 uint64_t addr; 311 uint32_t temp; 312 uint16_t i; 313 314 DPRINTF("\n"); 315 316 sc->sc_event_ccs = 1; 317 sc->sc_event_idx = 0; 318 sc->sc_command_ccs = 1; 319 sc->sc_command_idx = 0; 320 321 err = xhci_reset_controller(sc); 322 if (err) 323 return (err); 324 325 /* set up number of device slots */ 326 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 327 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 328 329 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 330 331 temp = XREAD4(sc, oper, XHCI_USBSTS); 332 333 /* clear interrupts */ 334 XWRITE4(sc, oper, XHCI_USBSTS, temp); 335 /* disable all device notifications */ 336 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 337 338 /* set up device context base address */ 339 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 340 pdctxa = buf_res.buffer; 341 memset(pdctxa, 0, sizeof(*pdctxa)); 342 343 addr = buf_res.physaddr; 344 addr += __offsetof(struct xhci_dev_ctx_addr, qwSpBufPtr[0]); 345 346 /* slot 0 points to the table of scratchpad pointers */ 347 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 348 349 for (i = 0; i != sc->sc_noscratch; i++) { 350 struct usb_page_search buf_scp; 351 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 352 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 353 } 354 355 addr = buf_res.physaddr; 356 357 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 358 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 359 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 360 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 361 362 /* set up event table size */ 363 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 364 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max); 365 366 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max)); 367 368 /* set up interrupt rate */ 369 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 370 371 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 372 373 phwr = buf_res.buffer; 374 addr = buf_res.physaddr; 375 addr += __offsetof(struct xhci_hw_root, hwr_events[0]); 376 377 /* reset hardware root structure */ 378 memset(phwr, 0, sizeof(*phwr)); 379 380 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 381 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 382 383 /* 384 * PR 237666: 385 * 386 * According to the XHCI specification, the XWRITE4's to 387 * XHCI_ERSTBA_LO and _HI lead to the XHCI to copy the 388 * qwEvrsTablePtr and dwEvrsTableSize values above at that 389 * time, as the XHCI initializes its event ring support. This 390 * is before the event ring starts to pay attention to the 391 * RUN/STOP bit. Thus, make sure the values are observable to 392 * the XHCI before that point. 393 */ 394 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 395 396 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 397 398 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 399 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 400 401 addr = buf_res.physaddr; 402 403 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 404 405 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 406 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 407 408 /* set up interrupter registers */ 409 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 410 temp |= XHCI_IMAN_INTR_ENA; 411 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 412 413 /* set up command ring control base address */ 414 addr = buf_res.physaddr; 415 addr += __offsetof(struct xhci_hw_root, hwr_commands[0]); 416 417 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 418 419 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 420 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 421 422 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 423 424 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 425 426 /* Go! */ 427 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 428 XHCI_CMD_INTE | XHCI_CMD_HSEE); 429 430 for (i = 0; i != 100; i++) { 431 usb_pause_mtx(NULL, hz / 100); 432 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 433 if (!temp) 434 break; 435 } 436 if (temp) { 437 XWRITE4(sc, oper, XHCI_USBCMD, 0); 438 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 439 return (USB_ERR_IOERROR); 440 } 441 442 /* catch any lost interrupts */ 443 xhci_do_poll(&sc->sc_bus); 444 445 if (sc->sc_port_route != NULL) { 446 /* Route all ports to the XHCI by default */ 447 sc->sc_port_route(sc->sc_bus.parent, 448 ~xhciroute, xhciroute); 449 } 450 return (0); 451 } 452 453 usb_error_t 454 xhci_halt_controller(struct xhci_softc *sc) 455 { 456 uint32_t temp; 457 uint16_t i; 458 459 DPRINTF("\n"); 460 461 sc->sc_capa_off = 0; 462 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 463 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 464 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 465 466 /* Halt controller */ 467 XWRITE4(sc, oper, XHCI_USBCMD, 0); 468 469 for (i = 0; i != 100; i++) { 470 usb_pause_mtx(NULL, hz / 100); 471 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 472 if (temp) 473 break; 474 } 475 476 if (!temp) { 477 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 478 return (USB_ERR_IOERROR); 479 } 480 return (0); 481 } 482 483 usb_error_t 484 xhci_reset_controller(struct xhci_softc *sc) 485 { 486 uint32_t temp = 0; 487 uint16_t i; 488 489 DPRINTF("\n"); 490 491 /* Reset controller */ 492 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 493 494 for (i = 0; i != 100; i++) { 495 usb_pause_mtx(NULL, hz / 100); 496 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 497 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 498 if (!temp) 499 break; 500 } 501 502 if (temp) { 503 device_printf(sc->sc_bus.parent, "Controller " 504 "reset timeout.\n"); 505 return (USB_ERR_IOERROR); 506 } 507 return (0); 508 } 509 510 usb_error_t 511 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32) 512 { 513 uint32_t temp; 514 515 DPRINTF("\n"); 516 517 /* initialize some bus fields */ 518 sc->sc_bus.parent = self; 519 520 /* set the bus revision */ 521 sc->sc_bus.usbrev = USB_REV_3_0; 522 523 /* set up the bus struct */ 524 sc->sc_bus.methods = &xhci_bus_methods; 525 526 /* set up devices array */ 527 sc->sc_bus.devices = sc->sc_devices; 528 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 529 530 /* set default cycle state in case of early interrupts */ 531 sc->sc_event_ccs = 1; 532 sc->sc_command_ccs = 1; 533 534 /* set up bus space offsets */ 535 sc->sc_capa_off = 0; 536 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 537 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 538 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 539 540 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 541 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 542 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 543 544 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 545 546 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 547 device_printf(sc->sc_bus.parent, "Controller does " 548 "not support 4K page size.\n"); 549 return (ENXIO); 550 } 551 552 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 553 554 DPRINTF("HCS0 = 0x%08x\n", temp); 555 556 /* set up context size */ 557 if (XHCI_HCS0_CSZ(temp)) { 558 sc->sc_ctx_is_64_byte = 1; 559 } else { 560 sc->sc_ctx_is_64_byte = 0; 561 } 562 563 /* get DMA bits */ 564 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && 565 xhcidma32 == 0 && dma32 == 0) ? 64 : 32; 566 567 device_printf(self, "%d bytes context size, %d-bit DMA\n", 568 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); 569 570 xhci_get_xecp(sc); 571 572 /* enable 64Kbyte control endpoint quirk */ 573 sc->sc_bus.control_ep_quirk = (xhcictlquirk ? 1 : 0); 574 575 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 576 577 /* get number of device slots */ 578 sc->sc_noport = XHCI_HCS1_N_PORTS(temp); 579 580 if (sc->sc_noport == 0) { 581 device_printf(sc->sc_bus.parent, "Invalid number " 582 "of ports: %u\n", sc->sc_noport); 583 return (ENXIO); 584 } 585 586 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 587 588 DPRINTF("Max slots: %u\n", sc->sc_noslot); 589 590 if (sc->sc_noslot > XHCI_MAX_DEVICES) 591 sc->sc_noslot = XHCI_MAX_DEVICES; 592 593 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 594 595 DPRINTF("HCS2=0x%08x\n", temp); 596 597 /* get isochronous scheduling threshold */ 598 sc->sc_ist = XHCI_HCS2_IST(temp); 599 600 /* get number of scratchpads */ 601 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 602 603 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 604 device_printf(sc->sc_bus.parent, "XHCI request " 605 "too many scratchpads\n"); 606 return (ENOMEM); 607 } 608 609 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 610 611 /* get event table size */ 612 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); 613 if (sc->sc_erst_max > XHCI_MAX_RSEG) 614 sc->sc_erst_max = XHCI_MAX_RSEG; 615 616 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 617 618 /* get maximum exit latency */ 619 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 620 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 621 622 /* Check if we should use the default IMOD value. */ 623 if (sc->sc_imod_default == 0) 624 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 625 626 /* get all DMA memory */ 627 if (usb_bus_mem_alloc_all(&sc->sc_bus, 628 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 629 return (ENOMEM); 630 } 631 632 /* set up command queue mutex and condition varible */ 633 cv_init(&sc->sc_cmd_cv, "CMDQ"); 634 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 635 636 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 637 sc->sc_config_msg[0].bus = &sc->sc_bus; 638 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 639 sc->sc_config_msg[1].bus = &sc->sc_bus; 640 641 return (0); 642 } 643 644 void 645 xhci_uninit(struct xhci_softc *sc) 646 { 647 /* 648 * NOTE: At this point the control transfer process is gone 649 * and "xhci_configure_msg" is no longer called. Consequently 650 * waiting for the configuration messages to complete is not 651 * needed. 652 */ 653 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 654 655 cv_destroy(&sc->sc_cmd_cv); 656 sx_destroy(&sc->sc_cmd_sx); 657 } 658 659 static void 660 xhci_get_xecp(struct xhci_softc *sc) 661 { 662 663 uint32_t hccp1; 664 uint32_t eec; 665 uint32_t eecp; 666 bool first = true; 667 668 hccp1 = XREAD4(sc, capa, XHCI_HCSPARAMS0); 669 670 if (XHCI_HCS0_XECP(hccp1) == 0) { 671 device_printf(sc->sc_bus.parent, 672 "xECP: no capabilities found\n"); 673 return; 674 } 675 676 /* 677 * Parse the xECP Capabilities table and print known caps. 678 * Implemented, vendor and reserved xECP Capabilities values are 679 * documented in Table 7.2 of eXtensible Host Controller Interface for 680 * Universal Serial Bus (xHCI) Rev 1.2b 2023. 681 */ 682 device_printf(sc->sc_bus.parent, "xECP capabilities <"); 683 684 eec = -1; 685 for (eecp = XHCI_HCS0_XECP(hccp1) << 2; 686 eecp != 0 && XHCI_XECP_NEXT(eec) != 0; 687 eecp += XHCI_XECP_NEXT(eec) << 2) { 688 eec = XREAD4(sc, capa, eecp); 689 690 uint8_t xecpid = XHCI_XECP_ID(eec); 691 692 if ((xecpid >= 11 && xecpid <= 16) || 693 (xecpid >= 19 && xecpid <= 191)) { 694 if (!first) 695 printf(","); 696 printf("RES(%x)", xecpid); 697 } else if (xecpid > 191) { 698 if (!first) 699 printf(","); 700 printf("VEND(%x)", xecpid); 701 } else { 702 if (!first) 703 printf(","); 704 switch (xecpid) 705 { 706 case XHCI_ID_USB_LEGACY: 707 printf("LEGACY"); 708 break; 709 case XHCI_ID_PROTOCOLS: 710 printf("PROTO"); 711 break; 712 case XHCI_ID_POWER_MGMT: 713 printf("POWER"); 714 break; 715 case XHCI_ID_VIRTUALIZATION: 716 printf("VIRT"); 717 break; 718 case XHCI_ID_MSG_IRQ: 719 printf("MSG IRQ"); 720 break; 721 case XHCI_ID_USB_LOCAL_MEM: 722 printf("LOCAL MEM"); 723 break; 724 case XHCI_ID_USB_DEBUG: 725 printf("DEBUG"); 726 break; 727 case XHCI_ID_EXT_MSI: 728 printf("EXT MSI"); 729 break; 730 case XHCI_ID_USB3_TUN: 731 printf("TUN"); 732 break; 733 734 } 735 } 736 first = false; 737 } 738 printf(">\n"); 739 } 740 741 static void 742 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 743 { 744 struct xhci_softc *sc = XHCI_BUS2SC(bus); 745 746 switch (state) { 747 case USB_HW_POWER_SUSPEND: 748 DPRINTF("Stopping the XHCI\n"); 749 xhci_halt_controller(sc); 750 xhci_reset_controller(sc); 751 break; 752 case USB_HW_POWER_SHUTDOWN: 753 DPRINTF("Stopping the XHCI\n"); 754 xhci_halt_controller(sc); 755 xhci_reset_controller(sc); 756 break; 757 case USB_HW_POWER_RESUME: 758 DPRINTF("Starting the XHCI\n"); 759 xhci_start_controller(sc); 760 break; 761 default: 762 break; 763 } 764 } 765 766 static usb_error_t 767 xhci_generic_done_sub(struct usb_xfer *xfer) 768 { 769 struct xhci_td *td; 770 struct xhci_td *td_alt_next; 771 uint32_t len; 772 uint8_t status; 773 774 td = xfer->td_transfer_cache; 775 td_alt_next = td->alt_next; 776 777 if (xfer->aframes != xfer->nframes) 778 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 779 780 while (1) { 781 usb_pc_cpu_invalidate(td->page_cache); 782 783 status = td->status; 784 len = td->remainder; 785 786 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 787 xfer, (unsigned)xfer->aframes, 788 (unsigned)xfer->nframes, 789 (unsigned)len, (unsigned)td->len, 790 (unsigned)status); 791 792 /* 793 * Verify the status length and 794 * add the length to "frlengths[]": 795 */ 796 if (len > td->len) { 797 /* should not happen */ 798 DPRINTF("Invalid status length, " 799 "0x%04x/0x%04x bytes\n", len, td->len); 800 status = XHCI_TRB_ERROR_LENGTH; 801 } else if (xfer->aframes != xfer->nframes) { 802 xfer->frlengths[xfer->aframes] += td->len - len; 803 } 804 /* Check for last transfer */ 805 if (((void *)td) == xfer->td_transfer_last) { 806 td = NULL; 807 break; 808 } 809 /* Check for transfer error */ 810 if (status != XHCI_TRB_ERROR_SHORT_PKT && 811 status != XHCI_TRB_ERROR_SUCCESS) { 812 /* the transfer is finished */ 813 td = NULL; 814 break; 815 } 816 /* Check for short transfer */ 817 if (len > 0) { 818 if (xfer->flags_int.short_frames_ok || 819 xfer->flags_int.isochronous_xfr || 820 xfer->flags_int.control_xfr) { 821 /* follow alt next */ 822 td = td->alt_next; 823 } else { 824 /* the transfer is finished */ 825 td = NULL; 826 } 827 break; 828 } 829 td = td->obj_next; 830 831 if (td->alt_next != td_alt_next) { 832 /* this USB frame is complete */ 833 break; 834 } 835 } 836 837 /* update transfer cache */ 838 839 xfer->td_transfer_cache = td; 840 841 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 842 (status != XHCI_TRB_ERROR_SHORT_PKT && 843 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 844 USB_ERR_NORMAL_COMPLETION); 845 } 846 847 static void 848 xhci_generic_done(struct usb_xfer *xfer) 849 { 850 usb_error_t err = 0; 851 852 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 853 xfer, xfer->endpoint); 854 855 /* reset scanner */ 856 857 xfer->td_transfer_cache = xfer->td_transfer_first; 858 859 if (xfer->flags_int.control_xfr) { 860 if (xfer->flags_int.control_hdr) 861 err = xhci_generic_done_sub(xfer); 862 863 xfer->aframes = 1; 864 865 if (xfer->td_transfer_cache == NULL) 866 goto done; 867 } 868 869 while (xfer->aframes != xfer->nframes) { 870 err = xhci_generic_done_sub(xfer); 871 xfer->aframes++; 872 873 if (xfer->td_transfer_cache == NULL) 874 goto done; 875 } 876 877 if (xfer->flags_int.control_xfr && 878 !xfer->flags_int.control_act) 879 err = xhci_generic_done_sub(xfer); 880 done: 881 /* transfer is complete */ 882 xhci_device_done(xfer, err); 883 } 884 885 static void 886 xhci_activate_transfer(struct usb_xfer *xfer) 887 { 888 struct xhci_td *td; 889 890 td = xfer->td_transfer_cache; 891 892 usb_pc_cpu_invalidate(td->page_cache); 893 894 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 895 /* activate the transfer */ 896 897 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 898 usb_pc_cpu_flush(td->page_cache); 899 900 xhci_endpoint_doorbell(xfer); 901 } 902 } 903 904 static void 905 xhci_skip_transfer(struct usb_xfer *xfer) 906 { 907 struct xhci_td *td; 908 struct xhci_td *td_last; 909 910 td = xfer->td_transfer_cache; 911 td_last = xfer->td_transfer_last; 912 913 td = td->alt_next; 914 915 usb_pc_cpu_invalidate(td->page_cache); 916 917 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 918 usb_pc_cpu_invalidate(td_last->page_cache); 919 920 /* copy LINK TRB to current waiting location */ 921 922 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 923 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 924 usb_pc_cpu_flush(td->page_cache); 925 926 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 927 usb_pc_cpu_flush(td->page_cache); 928 929 xhci_endpoint_doorbell(xfer); 930 } 931 } 932 933 /*------------------------------------------------------------------------* 934 * xhci_check_transfer 935 *------------------------------------------------------------------------*/ 936 static void 937 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 938 { 939 struct xhci_endpoint_ext *pepext; 940 int64_t offset; 941 uint64_t td_event; 942 uint32_t temp; 943 uint32_t remainder; 944 uint16_t stream_id = 0; 945 uint16_t i; 946 uint8_t status; 947 uint8_t halted; 948 uint8_t epno; 949 uint8_t index; 950 951 /* decode TRB */ 952 td_event = le64toh(trb->qwTrb0); 953 temp = le32toh(trb->dwTrb2); 954 955 remainder = XHCI_TRB_2_REM_GET(temp); 956 status = XHCI_TRB_2_ERROR_GET(temp); 957 958 temp = le32toh(trb->dwTrb3); 959 epno = XHCI_TRB_3_EP_GET(temp); 960 index = XHCI_TRB_3_SLOT_GET(temp); 961 962 /* check if error means halted */ 963 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 964 status != XHCI_TRB_ERROR_SUCCESS); 965 966 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 967 index, epno, remainder, status); 968 969 if (index > sc->sc_noslot) { 970 DPRINTF("Invalid slot.\n"); 971 return; 972 } 973 974 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 975 DPRINTF("Invalid endpoint.\n"); 976 return; 977 } 978 979 pepext = &sc->sc_hw.devs[index].endp[epno]; 980 981 /* try to find the USB transfer that generated the event */ 982 for (i = 0;; i++) { 983 struct usb_xfer *xfer; 984 struct xhci_td *td; 985 986 if (i == (XHCI_MAX_TRANSFERS - 1)) { 987 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS || 988 stream_id == (XHCI_MAX_STREAMS - 1)) 989 break; 990 stream_id++; 991 i = 0; 992 DPRINTFN(5, "stream_id=%u\n", stream_id); 993 } 994 995 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 996 if (xfer == NULL) 997 continue; 998 999 td = xfer->td_transfer_cache; 1000 1001 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 1002 (long long)td_event, 1003 (long long)td->td_self, 1004 (long long)td->td_self + sizeof(td->td_trb)); 1005 1006 /* 1007 * NOTE: Some XHCI implementations might not trigger 1008 * an event on the last LINK TRB so we need to 1009 * consider both the last and second last event 1010 * address as conditions for a successful transfer. 1011 * 1012 * NOTE: We assume that the XHCI will only trigger one 1013 * event per chain of TRBs. 1014 */ 1015 1016 offset = td_event - td->td_self; 1017 1018 if (offset >= 0 && 1019 offset < (int64_t)sizeof(td->td_trb)) { 1020 usb_pc_cpu_invalidate(td->page_cache); 1021 1022 /* compute rest of remainder, if any */ 1023 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 1024 temp = le32toh(td->td_trb[i].dwTrb2); 1025 remainder += XHCI_TRB_2_BYTES_GET(temp); 1026 } 1027 1028 DPRINTFN(5, "New remainder: %u\n", remainder); 1029 1030 /* clear isochronous transfer errors */ 1031 if (xfer->flags_int.isochronous_xfr) { 1032 if (halted) { 1033 halted = 0; 1034 status = XHCI_TRB_ERROR_SUCCESS; 1035 remainder = td->len; 1036 } 1037 } 1038 1039 /* "td->remainder" is verified later */ 1040 td->remainder = remainder; 1041 td->status = status; 1042 1043 usb_pc_cpu_flush(td->page_cache); 1044 1045 /* 1046 * 1) Last transfer descriptor makes the 1047 * transfer done 1048 */ 1049 if (((void *)td) == xfer->td_transfer_last) { 1050 DPRINTF("TD is last\n"); 1051 xhci_generic_done(xfer); 1052 break; 1053 } 1054 1055 /* 1056 * 2) Any kind of error makes the transfer 1057 * done 1058 */ 1059 if (halted) { 1060 DPRINTF("TD has I/O error\n"); 1061 xhci_generic_done(xfer); 1062 break; 1063 } 1064 1065 /* 1066 * 3) If there is no alternate next transfer, 1067 * a short packet also makes the transfer done 1068 */ 1069 if (td->remainder > 0) { 1070 if (td->alt_next == NULL) { 1071 DPRINTF( 1072 "short TD has no alternate next\n"); 1073 xhci_generic_done(xfer); 1074 break; 1075 } 1076 DPRINTF("TD has short pkt\n"); 1077 if (xfer->flags_int.short_frames_ok || 1078 xfer->flags_int.isochronous_xfr || 1079 xfer->flags_int.control_xfr) { 1080 /* follow the alt next */ 1081 xfer->td_transfer_cache = td->alt_next; 1082 xhci_activate_transfer(xfer); 1083 break; 1084 } 1085 xhci_skip_transfer(xfer); 1086 xhci_generic_done(xfer); 1087 break; 1088 } 1089 1090 /* 1091 * 4) Transfer complete - go to next TD 1092 */ 1093 DPRINTF("Following next TD\n"); 1094 xfer->td_transfer_cache = td->obj_next; 1095 xhci_activate_transfer(xfer); 1096 break; /* there should only be one match */ 1097 } 1098 } 1099 } 1100 1101 static int 1102 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1103 { 1104 if (sc->sc_cmd_addr == trb->qwTrb0) { 1105 DPRINTF("Received command event\n"); 1106 sc->sc_cmd_result[0] = trb->dwTrb2; 1107 sc->sc_cmd_result[1] = trb->dwTrb3; 1108 cv_signal(&sc->sc_cmd_cv); 1109 return (1); /* command match */ 1110 } 1111 return (0); 1112 } 1113 1114 static int 1115 xhci_interrupt_poll(struct xhci_softc *sc) 1116 { 1117 struct usb_page_search buf_res; 1118 struct xhci_hw_root *phwr; 1119 uint64_t addr; 1120 uint32_t temp; 1121 int retval = 0; 1122 uint16_t i; 1123 uint8_t event; 1124 uint8_t j; 1125 uint8_t k; 1126 uint8_t t; 1127 1128 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1129 1130 phwr = buf_res.buffer; 1131 1132 /* Receive any events */ 1133 1134 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1135 1136 i = sc->sc_event_idx; 1137 j = sc->sc_event_ccs; 1138 t = 2; 1139 1140 while (1) { 1141 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1142 1143 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1144 1145 if (j != k) 1146 break; 1147 1148 event = XHCI_TRB_3_TYPE_GET(temp); 1149 1150 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1151 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1152 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1153 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1154 1155 switch (event) { 1156 case XHCI_TRB_EVENT_TRANSFER: 1157 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1158 break; 1159 case XHCI_TRB_EVENT_CMD_COMPLETE: 1160 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1161 break; 1162 default: 1163 DPRINTF("Unhandled event = %u\n", event); 1164 break; 1165 } 1166 1167 i++; 1168 1169 if (i == XHCI_MAX_EVENTS) { 1170 i = 0; 1171 j ^= 1; 1172 1173 /* check for timeout */ 1174 if (!--t) 1175 break; 1176 } 1177 } 1178 1179 sc->sc_event_idx = i; 1180 sc->sc_event_ccs = j; 1181 1182 /* 1183 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1184 * latched. That means to activate the register we need to 1185 * write both the low and high double word of the 64-bit 1186 * register. 1187 */ 1188 1189 addr = buf_res.physaddr; 1190 addr += __offsetof(struct xhci_hw_root, hwr_events[i]); 1191 1192 /* try to clear busy bit */ 1193 addr |= XHCI_ERDP_LO_BUSY; 1194 1195 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1196 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1197 1198 return (retval); 1199 } 1200 1201 static usb_error_t 1202 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1203 uint16_t timeout_ms) 1204 { 1205 struct usb_page_search buf_res; 1206 struct xhci_hw_root *phwr; 1207 uint64_t addr; 1208 uint32_t temp; 1209 uint8_t i; 1210 uint8_t j; 1211 uint8_t timeout = 0; 1212 int err; 1213 1214 XHCI_CMD_ASSERT_LOCKED(sc); 1215 1216 /* get hardware root structure */ 1217 1218 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1219 1220 phwr = buf_res.buffer; 1221 1222 /* Queue command */ 1223 1224 USB_BUS_LOCK(&sc->sc_bus); 1225 retry: 1226 i = sc->sc_command_idx; 1227 j = sc->sc_command_ccs; 1228 1229 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1230 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1231 (long long)le64toh(trb->qwTrb0), 1232 (long)le32toh(trb->dwTrb2), 1233 (long)le32toh(trb->dwTrb3)); 1234 1235 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1236 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1237 1238 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1239 1240 temp = trb->dwTrb3; 1241 1242 if (j) 1243 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1244 else 1245 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1246 1247 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1248 1249 phwr->hwr_commands[i].dwTrb3 = temp; 1250 1251 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1252 1253 addr = buf_res.physaddr; 1254 addr += __offsetof(struct xhci_hw_root, hwr_commands[i]); 1255 1256 sc->sc_cmd_addr = htole64(addr); 1257 1258 i++; 1259 1260 if (i == (XHCI_MAX_COMMANDS - 1)) { 1261 if (j) { 1262 temp = htole32(XHCI_TRB_3_TC_BIT | 1263 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1264 XHCI_TRB_3_CYCLE_BIT); 1265 } else { 1266 temp = htole32(XHCI_TRB_3_TC_BIT | 1267 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1268 } 1269 1270 phwr->hwr_commands[i].dwTrb3 = temp; 1271 1272 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1273 1274 i = 0; 1275 j ^= 1; 1276 } 1277 1278 sc->sc_command_idx = i; 1279 sc->sc_command_ccs = j; 1280 1281 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1282 1283 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1284 USB_MS_TO_TICKS(timeout_ms)); 1285 1286 /* 1287 * In some error cases event interrupts are not generated. 1288 * Poll one time to see if the command has completed. 1289 */ 1290 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1291 DPRINTF("Command was completed when polling\n"); 1292 err = 0; 1293 } 1294 if (err != 0) { 1295 DPRINTF("Command timeout!\n"); 1296 /* 1297 * After some weeks of continuous operation, it has 1298 * been observed that the ASMedia Technology, ASM1042 1299 * SuperSpeed USB Host Controller can suddenly stop 1300 * accepting commands via the command queue. Try to 1301 * first reset the command queue. If that fails do a 1302 * host controller reset. 1303 */ 1304 if (timeout == 0 && 1305 xhci_reset_command_queue_locked(sc) == 0) { 1306 temp = le32toh(trb->dwTrb3); 1307 1308 /* 1309 * Avoid infinite XHCI reset loops if the set 1310 * address command fails to respond due to a 1311 * non-enumerating device: 1312 */ 1313 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1314 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1315 DPRINTF("Set address timeout\n"); 1316 } else { 1317 timeout = 1; 1318 goto retry; 1319 } 1320 } else { 1321 DPRINTF("Controller reset!\n"); 1322 usb_bus_reset_async_locked(&sc->sc_bus); 1323 } 1324 err = USB_ERR_TIMEOUT; 1325 trb->dwTrb2 = 0; 1326 trb->dwTrb3 = 0; 1327 } else { 1328 temp = le32toh(sc->sc_cmd_result[0]); 1329 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1330 err = USB_ERR_IOERROR; 1331 1332 trb->dwTrb2 = sc->sc_cmd_result[0]; 1333 trb->dwTrb3 = sc->sc_cmd_result[1]; 1334 } 1335 1336 USB_BUS_UNLOCK(&sc->sc_bus); 1337 1338 return (err); 1339 } 1340 1341 #if 0 1342 static usb_error_t 1343 xhci_cmd_nop(struct xhci_softc *sc) 1344 { 1345 struct xhci_trb trb; 1346 uint32_t temp; 1347 1348 DPRINTF("\n"); 1349 1350 trb.qwTrb0 = 0; 1351 trb.dwTrb2 = 0; 1352 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1353 1354 trb.dwTrb3 = htole32(temp); 1355 1356 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1357 } 1358 #endif 1359 1360 static usb_error_t 1361 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1362 { 1363 struct xhci_trb trb; 1364 uint32_t temp; 1365 usb_error_t err; 1366 1367 DPRINTF("\n"); 1368 1369 trb.qwTrb0 = 0; 1370 trb.dwTrb2 = 0; 1371 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1372 1373 err = xhci_do_command(sc, &trb, 100 /* ms */); 1374 if (err) 1375 goto done; 1376 1377 temp = le32toh(trb.dwTrb3); 1378 1379 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1380 1381 done: 1382 return (err); 1383 } 1384 1385 static usb_error_t 1386 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1387 { 1388 struct xhci_trb trb; 1389 uint32_t temp; 1390 1391 DPRINTF("\n"); 1392 1393 trb.qwTrb0 = 0; 1394 trb.dwTrb2 = 0; 1395 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1396 XHCI_TRB_3_SLOT_SET(slot_id); 1397 1398 trb.dwTrb3 = htole32(temp); 1399 1400 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1401 } 1402 1403 static usb_error_t 1404 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1405 uint8_t bsr, uint8_t slot_id) 1406 { 1407 struct xhci_trb trb; 1408 uint32_t temp; 1409 1410 DPRINTF("\n"); 1411 1412 trb.qwTrb0 = htole64(input_ctx); 1413 trb.dwTrb2 = 0; 1414 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1415 XHCI_TRB_3_SLOT_SET(slot_id); 1416 1417 if (bsr) 1418 temp |= XHCI_TRB_3_BSR_BIT; 1419 1420 trb.dwTrb3 = htole32(temp); 1421 1422 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1423 } 1424 1425 static usb_error_t 1426 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1427 { 1428 struct usb_page_search buf_inp; 1429 struct usb_page_search buf_dev; 1430 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1431 struct xhci_hw_dev *hdev; 1432 struct xhci_slot_ctx *slot; 1433 struct xhci_endpoint_ext *pepext; 1434 uint32_t temp; 1435 uint16_t mps; 1436 usb_error_t err; 1437 uint8_t index; 1438 1439 /* the root HUB case is not handled here */ 1440 if (udev->parent_hub == NULL) 1441 return (USB_ERR_INVAL); 1442 1443 index = udev->controller_slot_id; 1444 1445 hdev = &sc->sc_hw.devs[index]; 1446 1447 if (mtx != NULL) 1448 mtx_unlock(mtx); 1449 1450 XHCI_CMD_LOCK(sc); 1451 1452 switch (hdev->state) { 1453 case XHCI_ST_DEFAULT: 1454 case XHCI_ST_ENABLED: 1455 1456 hdev->state = XHCI_ST_ENABLED; 1457 1458 /* set configure mask to slot and EP0 */ 1459 xhci_configure_mask(udev, 3, 0); 1460 1461 /* configure input slot context structure */ 1462 err = xhci_configure_device(udev); 1463 1464 if (err != 0) { 1465 DPRINTF("Could not configure device\n"); 1466 break; 1467 } 1468 1469 /* configure input endpoint context structure */ 1470 switch (udev->speed) { 1471 case USB_SPEED_LOW: 1472 case USB_SPEED_FULL: 1473 mps = 8; 1474 break; 1475 case USB_SPEED_HIGH: 1476 mps = 64; 1477 break; 1478 default: 1479 mps = 512; 1480 break; 1481 } 1482 1483 pepext = xhci_get_endpoint_ext(udev, 1484 &udev->ctrl_ep_desc); 1485 1486 /* ensure the control endpoint is setup again */ 1487 USB_BUS_LOCK(udev->bus); 1488 pepext->trb_halted = 1; 1489 pepext->trb_running = 0; 1490 USB_BUS_UNLOCK(udev->bus); 1491 1492 err = xhci_configure_endpoint(udev, 1493 &udev->ctrl_ep_desc, pepext, 1494 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1495 1496 if (err != 0) { 1497 DPRINTF("Could not configure default endpoint\n"); 1498 break; 1499 } 1500 1501 /* execute set address command */ 1502 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1503 1504 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1505 (address == 0), index); 1506 1507 if (err != 0) { 1508 temp = le32toh(sc->sc_cmd_result[0]); 1509 if (address == 0 && sc->sc_port_route != NULL && 1510 XHCI_TRB_2_ERROR_GET(temp) == 1511 XHCI_TRB_ERROR_PARAMETER) { 1512 /* LynxPoint XHCI - ports are not switchable */ 1513 /* Un-route all ports from the XHCI */ 1514 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1515 } 1516 DPRINTF("Could not set address " 1517 "for slot %u.\n", index); 1518 if (address != 0) 1519 break; 1520 } 1521 1522 /* update device address to new value */ 1523 1524 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1525 slot = XHCI_GET_CTX(sc, xhci_dev_ctx, ctx_slot, 1526 buf_dev.buffer); 1527 usb_pc_cpu_invalidate(&hdev->device_pc); 1528 1529 temp = le32toh(slot->dwSctx3); 1530 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1531 1532 /* update device state to new value */ 1533 1534 if (address != 0) 1535 hdev->state = XHCI_ST_ADDRESSED; 1536 else 1537 hdev->state = XHCI_ST_DEFAULT; 1538 break; 1539 1540 default: 1541 DPRINTF("Wrong state for set address.\n"); 1542 err = USB_ERR_IOERROR; 1543 break; 1544 } 1545 XHCI_CMD_UNLOCK(sc); 1546 1547 if (mtx != NULL) 1548 mtx_lock(mtx); 1549 1550 return (err); 1551 } 1552 1553 static usb_error_t 1554 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1555 uint8_t deconfigure, uint8_t slot_id) 1556 { 1557 struct xhci_trb trb; 1558 uint32_t temp; 1559 1560 DPRINTF("\n"); 1561 1562 trb.qwTrb0 = htole64(input_ctx); 1563 trb.dwTrb2 = 0; 1564 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1565 XHCI_TRB_3_SLOT_SET(slot_id); 1566 1567 if (deconfigure) { 1568 if (sc->sc_no_deconfigure != 0 || xhcidcepquirk != 0) 1569 return (0); /* Success */ 1570 temp |= XHCI_TRB_3_DCEP_BIT; 1571 } 1572 1573 trb.dwTrb3 = htole32(temp); 1574 1575 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1576 } 1577 1578 static usb_error_t 1579 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1580 uint8_t slot_id) 1581 { 1582 struct xhci_trb trb; 1583 uint32_t temp; 1584 1585 DPRINTF("\n"); 1586 1587 trb.qwTrb0 = htole64(input_ctx); 1588 trb.dwTrb2 = 0; 1589 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1590 XHCI_TRB_3_SLOT_SET(slot_id); 1591 trb.dwTrb3 = htole32(temp); 1592 1593 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1594 } 1595 1596 static usb_error_t 1597 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1598 uint8_t ep_id, uint8_t slot_id) 1599 { 1600 struct xhci_trb trb; 1601 uint32_t temp; 1602 1603 DPRINTF("\n"); 1604 1605 trb.qwTrb0 = 0; 1606 trb.dwTrb2 = 0; 1607 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1608 XHCI_TRB_3_SLOT_SET(slot_id) | 1609 XHCI_TRB_3_EP_SET(ep_id); 1610 1611 if (preserve) 1612 temp |= XHCI_TRB_3_PRSV_BIT; 1613 1614 trb.dwTrb3 = htole32(temp); 1615 1616 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1617 } 1618 1619 static usb_error_t 1620 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1621 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1622 { 1623 struct xhci_trb trb; 1624 uint32_t temp; 1625 1626 DPRINTF("\n"); 1627 1628 trb.qwTrb0 = htole64(dequeue_ptr); 1629 1630 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1631 trb.dwTrb2 = htole32(temp); 1632 1633 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1634 XHCI_TRB_3_SLOT_SET(slot_id) | 1635 XHCI_TRB_3_EP_SET(ep_id); 1636 trb.dwTrb3 = htole32(temp); 1637 1638 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1639 } 1640 1641 static usb_error_t 1642 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1643 uint8_t ep_id, uint8_t slot_id) 1644 { 1645 struct xhci_trb trb; 1646 uint32_t temp; 1647 1648 DPRINTF("\n"); 1649 1650 trb.qwTrb0 = 0; 1651 trb.dwTrb2 = 0; 1652 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1653 XHCI_TRB_3_SLOT_SET(slot_id) | 1654 XHCI_TRB_3_EP_SET(ep_id); 1655 1656 if (suspend) 1657 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1658 1659 trb.dwTrb3 = htole32(temp); 1660 1661 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1662 } 1663 1664 static usb_error_t 1665 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1666 { 1667 struct xhci_trb trb; 1668 uint32_t temp; 1669 1670 DPRINTF("\n"); 1671 1672 trb.qwTrb0 = 0; 1673 trb.dwTrb2 = 0; 1674 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1675 XHCI_TRB_3_SLOT_SET(slot_id); 1676 1677 trb.dwTrb3 = htole32(temp); 1678 1679 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1680 } 1681 1682 /*------------------------------------------------------------------------* 1683 * xhci_interrupt - XHCI interrupt handler 1684 *------------------------------------------------------------------------*/ 1685 void 1686 xhci_interrupt(struct xhci_softc *sc) 1687 { 1688 uint32_t status; 1689 uint32_t temp; 1690 1691 USB_BUS_LOCK(&sc->sc_bus); 1692 1693 status = XREAD4(sc, oper, XHCI_USBSTS); 1694 1695 /* acknowledge interrupts, if any */ 1696 if (status != 0) { 1697 XWRITE4(sc, oper, XHCI_USBSTS, status); 1698 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1699 } 1700 1701 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1702 1703 /* force clearing of pending interrupts */ 1704 if (temp & XHCI_IMAN_INTR_PEND) 1705 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1706 1707 /* check for event(s) */ 1708 xhci_interrupt_poll(sc); 1709 1710 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1711 XHCI_STS_HSE | XHCI_STS_HCE)) { 1712 if (status & XHCI_STS_PCD) { 1713 xhci_root_intr(sc); 1714 } 1715 1716 if (status & XHCI_STS_HCH) { 1717 printf("%s: host controller halted\n", 1718 __FUNCTION__); 1719 } 1720 1721 if (status & XHCI_STS_HSE) { 1722 printf("%s: host system error\n", 1723 __FUNCTION__); 1724 } 1725 1726 if (status & XHCI_STS_HCE) { 1727 printf("%s: host controller error\n", 1728 __FUNCTION__); 1729 } 1730 } 1731 USB_BUS_UNLOCK(&sc->sc_bus); 1732 } 1733 1734 /*------------------------------------------------------------------------* 1735 * xhci_timeout - XHCI timeout handler 1736 *------------------------------------------------------------------------*/ 1737 static void 1738 xhci_timeout(void *arg) 1739 { 1740 struct usb_xfer *xfer = arg; 1741 1742 DPRINTF("xfer=%p\n", xfer); 1743 1744 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1745 1746 /* transfer is transferred */ 1747 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1748 } 1749 1750 static void 1751 xhci_do_poll(struct usb_bus *bus) 1752 { 1753 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1754 1755 USB_BUS_LOCK(&sc->sc_bus); 1756 xhci_interrupt_poll(sc); 1757 USB_BUS_UNLOCK(&sc->sc_bus); 1758 } 1759 1760 static void 1761 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1762 { 1763 struct usb_page_search buf_res; 1764 struct xhci_td *td; 1765 struct xhci_td *td_next; 1766 struct xhci_td *td_alt_next; 1767 struct xhci_td *td_first; 1768 uint32_t buf_offset; 1769 uint32_t average; 1770 uint32_t len_old; 1771 uint32_t npkt_off; 1772 uint32_t dword; 1773 uint8_t shortpkt_old; 1774 uint8_t precompute; 1775 uint8_t x; 1776 1777 td_alt_next = NULL; 1778 buf_offset = 0; 1779 shortpkt_old = temp->shortpkt; 1780 len_old = temp->len; 1781 npkt_off = 0; 1782 precompute = 1; 1783 1784 restart: 1785 1786 td = temp->td; 1787 td_next = td_first = temp->td_next; 1788 1789 while (1) { 1790 if (temp->len == 0) { 1791 if (temp->shortpkt) 1792 break; 1793 1794 /* send a Zero Length Packet, ZLP, last */ 1795 1796 temp->shortpkt = 1; 1797 average = 0; 1798 1799 } else { 1800 average = temp->average; 1801 1802 if (temp->len < average) { 1803 if (temp->len % temp->max_packet_size) { 1804 temp->shortpkt = 1; 1805 } 1806 average = temp->len; 1807 } 1808 } 1809 1810 if (td_next == NULL) 1811 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1812 1813 /* get next TD */ 1814 1815 td = td_next; 1816 td_next = td->obj_next; 1817 1818 /* check if we are pre-computing */ 1819 1820 if (precompute) { 1821 /* update remaining length */ 1822 1823 temp->len -= average; 1824 1825 continue; 1826 } 1827 /* fill out current TD */ 1828 1829 td->len = average; 1830 td->remainder = 0; 1831 td->status = 0; 1832 1833 /* update remaining length */ 1834 1835 temp->len -= average; 1836 1837 /* reset TRB index */ 1838 1839 x = 0; 1840 1841 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1842 /* immediate data */ 1843 1844 if (average > 8) 1845 average = 8; 1846 1847 td->td_trb[0].qwTrb0 = 0; 1848 1849 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1850 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1851 average); 1852 1853 dword = XHCI_TRB_2_BYTES_SET(8) | 1854 XHCI_TRB_2_TDSZ_SET(0) | 1855 XHCI_TRB_2_IRQ_SET(0); 1856 1857 td->td_trb[0].dwTrb2 = htole32(dword); 1858 1859 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1860 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1861 1862 /* check wLength */ 1863 if (td->td_trb[0].qwTrb0 & 1864 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1865 if (td->td_trb[0].qwTrb0 & 1866 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1867 dword |= XHCI_TRB_3_TRT_IN; 1868 else 1869 dword |= XHCI_TRB_3_TRT_OUT; 1870 } 1871 1872 td->td_trb[0].dwTrb3 = htole32(dword); 1873 #ifdef USB_DEBUG 1874 xhci_dump_trb(&td->td_trb[x]); 1875 #endif 1876 x++; 1877 1878 } else do { 1879 uint32_t npkt; 1880 1881 /* fill out buffer pointers */ 1882 1883 if (average == 0) { 1884 memset(&buf_res, 0, sizeof(buf_res)); 1885 } else { 1886 usbd_get_page(temp->pc, temp->offset + 1887 buf_offset, &buf_res); 1888 1889 /* get length to end of page */ 1890 if (buf_res.length > average) 1891 buf_res.length = average; 1892 1893 /* check for maximum length */ 1894 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1895 buf_res.length = XHCI_TD_PAGE_SIZE; 1896 1897 npkt_off += buf_res.length; 1898 } 1899 1900 /* set up npkt */ 1901 npkt = howmany(len_old - npkt_off, 1902 temp->max_packet_size); 1903 1904 if (npkt == 0) 1905 npkt = 1; 1906 else if (npkt > 31) 1907 npkt = 31; 1908 1909 /* fill out TRB's */ 1910 td->td_trb[x].qwTrb0 = 1911 htole64((uint64_t)buf_res.physaddr); 1912 1913 dword = 1914 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1915 XHCI_TRB_2_TDSZ_SET(npkt) | 1916 XHCI_TRB_2_IRQ_SET(0); 1917 1918 td->td_trb[x].dwTrb2 = htole32(dword); 1919 1920 switch (temp->trb_type) { 1921 case XHCI_TRB_TYPE_ISOCH: 1922 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1923 XHCI_TRB_3_TBC_SET(temp->tbc) | 1924 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1925 if (td != td_first) { 1926 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1927 } else if (temp->do_isoc_sync != 0) { 1928 temp->do_isoc_sync = 0; 1929 /* wait until "isoc_frame" */ 1930 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1931 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1932 } else { 1933 /* start data transfer at next interval */ 1934 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1935 XHCI_TRB_3_ISO_SIA_BIT; 1936 } 1937 if (temp->direction == UE_DIR_IN) 1938 dword |= XHCI_TRB_3_ISP_BIT; 1939 break; 1940 case XHCI_TRB_TYPE_DATA_STAGE: 1941 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1942 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1943 if (temp->direction == UE_DIR_IN) 1944 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1945 /* 1946 * Section 3.2.9 in the XHCI 1947 * specification about control 1948 * transfers says that we should use a 1949 * normal-TRB if there are more TRBs 1950 * extending the data-stage 1951 * TRB. Update the "trb_type". 1952 */ 1953 temp->trb_type = XHCI_TRB_TYPE_NORMAL; 1954 break; 1955 case XHCI_TRB_TYPE_STATUS_STAGE: 1956 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1957 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1958 if (temp->direction == UE_DIR_IN) 1959 dword |= XHCI_TRB_3_DIR_IN; 1960 break; 1961 default: /* XHCI_TRB_TYPE_NORMAL */ 1962 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1963 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1964 if (temp->direction == UE_DIR_IN) 1965 dword |= XHCI_TRB_3_ISP_BIT; 1966 break; 1967 } 1968 td->td_trb[x].dwTrb3 = htole32(dword); 1969 1970 average -= buf_res.length; 1971 buf_offset += buf_res.length; 1972 #ifdef USB_DEBUG 1973 xhci_dump_trb(&td->td_trb[x]); 1974 #endif 1975 x++; 1976 1977 } while (average != 0); 1978 1979 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1980 1981 /* store number of data TRB's */ 1982 1983 td->ntrb = x; 1984 1985 DPRINTF("NTRB=%u\n", x); 1986 1987 /* fill out link TRB */ 1988 1989 if (td_next != NULL) { 1990 /* link the current TD with the next one */ 1991 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1992 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1993 } else { 1994 /* this field will get updated later */ 1995 DPRINTF("NOLINK\n"); 1996 } 1997 1998 dword = XHCI_TRB_2_IRQ_SET(0); 1999 2000 td->td_trb[x].dwTrb2 = htole32(dword); 2001 2002 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2003 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 2004 /* 2005 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 2006 * frame only receives a single short packet event 2007 * by setting the CHAIN bit in the LINK field. In 2008 * addition some XHCI controllers have problems 2009 * sending a ZLP unless the CHAIN-BIT is set in 2010 * the LINK TRB. 2011 */ 2012 XHCI_TRB_3_CHAIN_BIT; 2013 2014 td->td_trb[x].dwTrb3 = htole32(dword); 2015 2016 td->alt_next = td_alt_next; 2017 #ifdef USB_DEBUG 2018 xhci_dump_trb(&td->td_trb[x]); 2019 #endif 2020 usb_pc_cpu_flush(td->page_cache); 2021 } 2022 2023 if (precompute) { 2024 precompute = 0; 2025 2026 /* set up alt next pointer, if any */ 2027 if (temp->last_frame) { 2028 td_alt_next = NULL; 2029 } else { 2030 /* we use this field internally */ 2031 td_alt_next = td_next; 2032 } 2033 2034 /* restore */ 2035 temp->shortpkt = shortpkt_old; 2036 temp->len = len_old; 2037 goto restart; 2038 } 2039 2040 /* 2041 * Remove cycle bit from the first TRB if we are 2042 * stepping them: 2043 */ 2044 if (temp->step_td != 0) { 2045 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2046 usb_pc_cpu_flush(td_first->page_cache); 2047 } 2048 2049 /* clear TD SIZE to zero, hence this is the last TRB */ 2050 /* remove chain bit because this is the last data TRB in the chain */ 2051 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31)); 2052 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 2053 /* remove CHAIN-BIT from last LINK TRB */ 2054 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 2055 2056 usb_pc_cpu_flush(td->page_cache); 2057 2058 temp->td = td; 2059 temp->td_next = td_next; 2060 } 2061 2062 static void 2063 xhci_setup_generic_chain(struct usb_xfer *xfer) 2064 { 2065 struct xhci_std_temp temp; 2066 struct xhci_td *td; 2067 uint32_t x; 2068 uint32_t y; 2069 uint8_t mult; 2070 2071 temp.do_isoc_sync = 0; 2072 temp.step_td = 0; 2073 temp.tbc = 0; 2074 temp.tlbpc = 0; 2075 temp.average = xfer->max_hc_frame_size; 2076 temp.max_packet_size = xfer->max_packet_size; 2077 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 2078 temp.pc = NULL; 2079 temp.last_frame = 0; 2080 temp.offset = 0; 2081 temp.multishort = xfer->flags_int.isochronous_xfr || 2082 xfer->flags_int.control_xfr || 2083 xfer->flags_int.short_frames_ok; 2084 2085 /* toggle the DMA set we are using */ 2086 xfer->flags_int.curr_dma_set ^= 1; 2087 2088 /* get next DMA set */ 2089 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2090 2091 temp.td = NULL; 2092 temp.td_next = td; 2093 2094 xfer->td_transfer_first = td; 2095 xfer->td_transfer_cache = td; 2096 2097 if (xfer->flags_int.isochronous_xfr) { 2098 uint8_t shift; 2099 2100 /* compute multiplier for ISOCHRONOUS transfers */ 2101 mult = xfer->endpoint->ecomp ? 2102 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2103 : 0; 2104 /* check for USB 2.0 multiplier */ 2105 if (mult == 0) { 2106 mult = (xfer->endpoint->edesc-> 2107 wMaxPacketSize[1] >> 3) & 3; 2108 } 2109 /* range check */ 2110 if (mult > 2) 2111 mult = 3; 2112 else 2113 mult++; 2114 2115 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2116 2117 DPRINTF("MFINDEX=0x%08x IST=0x%x\n", x, temp.sc->sc_ist); 2118 2119 switch (usbd_get_speed(xfer->xroot->udev)) { 2120 case USB_SPEED_FULL: 2121 shift = 3; 2122 temp.isoc_delta = 8; /* 1ms */ 2123 break; 2124 default: 2125 shift = usbd_xfer_get_fps_shift(xfer); 2126 temp.isoc_delta = 1U << shift; 2127 break; 2128 } 2129 2130 /* Compute isochronous scheduling threshold. */ 2131 if (temp.sc->sc_ist & 8) 2132 y = (temp.sc->sc_ist & 7) << 3; 2133 else 2134 y = (temp.sc->sc_ist & 7); 2135 2136 /* Range check the IST. */ 2137 if (y < 8) { 2138 y = 0; 2139 } else if (y > 15) { 2140 DPRINTFN(3, "IST(%d) is too big!\n", temp.sc->sc_ist); 2141 /* 2142 * The USB stack minimum isochronous transfer 2143 * size is typically 2x2 ms of payload. If the 2144 * IST makes is above 15 microframes, we have 2145 * an effective scheduling delay of more than 2146 * or equal to 2 milliseconds, which is too 2147 * much. 2148 */ 2149 y = 7; 2150 } else { 2151 /* 2152 * Subtract one millisecond, because the 2153 * generic code adds that to the latency. 2154 */ 2155 y -= 8; 2156 } 2157 2158 if (usbd_xfer_get_isochronous_start_frame( 2159 xfer, x, y, 8, XHCI_MFINDEX_GET(-1), &temp.isoc_frame)) { 2160 /* Start isochronous transfer at specified time. */ 2161 temp.do_isoc_sync = 1; 2162 2163 DPRINTFN(3, "start next=%d\n", temp.isoc_frame); 2164 } 2165 2166 x = 0; 2167 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2168 2169 } else if (xfer->flags_int.control_xfr) { 2170 /* check if we should prepend a setup message */ 2171 2172 if (xfer->flags_int.control_hdr) { 2173 temp.len = xfer->frlengths[0]; 2174 temp.pc = xfer->frbuffers + 0; 2175 temp.shortpkt = temp.len ? 1 : 0; 2176 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2177 temp.direction = 0; 2178 2179 /* check for last frame */ 2180 if (xfer->nframes == 1) { 2181 /* no STATUS stage yet, SETUP is last */ 2182 if (xfer->flags_int.control_act) 2183 temp.last_frame = 1; 2184 } 2185 2186 xhci_setup_generic_chain_sub(&temp); 2187 } 2188 x = 1; 2189 mult = 1; 2190 temp.isoc_delta = 0; 2191 temp.isoc_frame = 0; 2192 temp.trb_type = xfer->flags_int.control_did_data ? 2193 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE; 2194 } else { 2195 x = 0; 2196 mult = 1; 2197 temp.isoc_delta = 0; 2198 temp.isoc_frame = 0; 2199 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2200 } 2201 2202 if (x != xfer->nframes) { 2203 /* set up page_cache pointer */ 2204 temp.pc = xfer->frbuffers + x; 2205 /* set endpoint direction */ 2206 temp.direction = UE_GET_DIR(xfer->endpointno); 2207 } 2208 2209 while (x != xfer->nframes) { 2210 /* DATA0 / DATA1 message */ 2211 2212 temp.len = xfer->frlengths[x]; 2213 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2214 x != 0 && temp.multishort == 0); 2215 2216 x++; 2217 2218 if (x == xfer->nframes) { 2219 if (xfer->flags_int.control_xfr) { 2220 /* no STATUS stage yet, DATA is last */ 2221 if (xfer->flags_int.control_act) 2222 temp.last_frame = 1; 2223 } else { 2224 temp.last_frame = 1; 2225 } 2226 } 2227 if (temp.len == 0) { 2228 /* make sure that we send an USB packet */ 2229 2230 temp.shortpkt = 0; 2231 2232 temp.tbc = 0; 2233 temp.tlbpc = mult - 1; 2234 2235 } else if (xfer->flags_int.isochronous_xfr) { 2236 uint8_t tdpc; 2237 2238 /* 2239 * Isochronous transfers don't have short 2240 * packet termination: 2241 */ 2242 2243 temp.shortpkt = 1; 2244 2245 /* isochronous transfers have a transfer limit */ 2246 2247 if (temp.len > xfer->max_frame_size) 2248 temp.len = xfer->max_frame_size; 2249 2250 /* compute TD packet count */ 2251 tdpc = howmany(temp.len, xfer->max_packet_size); 2252 2253 temp.tbc = howmany(tdpc, mult) - 1; 2254 temp.tlbpc = (tdpc % mult); 2255 2256 if (temp.tlbpc == 0) 2257 temp.tlbpc = mult - 1; 2258 else 2259 temp.tlbpc--; 2260 } else { 2261 /* regular data transfer */ 2262 2263 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2264 } 2265 2266 xhci_setup_generic_chain_sub(&temp); 2267 2268 if (xfer->flags_int.isochronous_xfr) { 2269 temp.offset += xfer->frlengths[x - 1]; 2270 temp.isoc_frame += temp.isoc_delta; 2271 } else { 2272 /* get next Page Cache pointer */ 2273 temp.pc = xfer->frbuffers + x; 2274 } 2275 } 2276 2277 /* check if we should append a status stage */ 2278 2279 if (xfer->flags_int.control_xfr && 2280 !xfer->flags_int.control_act) { 2281 /* 2282 * Send a DATA1 message and invert the current 2283 * endpoint direction. 2284 */ 2285 if (xhcictlstep || temp.sc->sc_ctlstep) { 2286 /* 2287 * Some XHCI controllers will not delay the 2288 * status stage until the next SOF. Force this 2289 * behaviour to avoid failed control 2290 * transfers. 2291 */ 2292 temp.step_td = (xfer->nframes != 0); 2293 } else { 2294 temp.step_td = 0; 2295 } 2296 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2297 temp.len = 0; 2298 temp.pc = NULL; 2299 temp.shortpkt = 0; 2300 temp.last_frame = 1; 2301 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2302 2303 xhci_setup_generic_chain_sub(&temp); 2304 } 2305 2306 td = temp.td; 2307 2308 /* must have at least one frame! */ 2309 2310 xfer->td_transfer_last = td; 2311 2312 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2313 } 2314 2315 static void 2316 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2317 { 2318 struct usb_page_search buf_res; 2319 struct xhci_dev_ctx_addr *pdctxa; 2320 2321 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2322 2323 pdctxa = buf_res.buffer; 2324 2325 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2326 2327 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2328 2329 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2330 } 2331 2332 static usb_error_t 2333 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2334 { 2335 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2336 struct usb_page_search buf_inp; 2337 struct xhci_input_ctx *input; 2338 struct xhci_slot_ctx *slot; 2339 uint32_t temp; 2340 uint8_t index; 2341 uint8_t x; 2342 2343 index = udev->controller_slot_id; 2344 2345 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2346 2347 input = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_input, 2348 buf_inp.buffer); 2349 slot = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_slot, buf_inp.buffer); 2350 2351 if (drop) { 2352 mask &= XHCI_INCTX_NON_CTRL_MASK; 2353 input->dwInCtx0 = htole32(mask); 2354 input->dwInCtx1 = htole32(0); 2355 } else { 2356 /* 2357 * Some hardware requires that we drop the endpoint 2358 * context before adding it again: 2359 */ 2360 input->dwInCtx0 = htole32(mask & XHCI_INCTX_NON_CTRL_MASK); 2361 2362 /* Add new endpoint context */ 2363 input->dwInCtx1 = htole32(mask); 2364 2365 /* find most significant set bit */ 2366 for (x = 31; x != 1; x--) { 2367 if (mask & (1 << x)) 2368 break; 2369 } 2370 2371 /* adjust */ 2372 x--; 2373 2374 /* figure out the maximum number of contexts */ 2375 if (x > sc->sc_hw.devs[index].context_num) 2376 sc->sc_hw.devs[index].context_num = x; 2377 else 2378 x = sc->sc_hw.devs[index].context_num; 2379 2380 /* update number of contexts */ 2381 temp = le32toh(slot->dwSctx0); 2382 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2383 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2384 slot->dwSctx0 = htole32(temp); 2385 } 2386 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2387 return (0); 2388 } 2389 2390 static usb_error_t 2391 xhci_configure_endpoint(struct usb_device *udev, 2392 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2393 uint16_t interval, uint8_t max_packet_count, 2394 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2395 uint16_t max_frame_size, uint8_t ep_mode) 2396 { 2397 struct usb_page_search buf_inp; 2398 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2399 struct xhci_endp_ctx *endp; 2400 uint64_t ring_addr = pepext->physaddr; 2401 uint32_t temp; 2402 uint8_t index; 2403 uint8_t epno; 2404 uint8_t type; 2405 2406 index = udev->controller_slot_id; 2407 2408 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2409 2410 epno = edesc->bEndpointAddress; 2411 type = edesc->bmAttributes & UE_XFERTYPE; 2412 2413 if (type == UE_CONTROL) 2414 epno |= UE_DIR_IN; 2415 2416 epno = XHCI_EPNO2EPID(epno); 2417 2418 if (epno == 0) 2419 return (USB_ERR_NO_PIPE); /* invalid */ 2420 2421 if (max_packet_count == 0) 2422 return (USB_ERR_BAD_BUFSIZE); 2423 2424 max_packet_count--; 2425 2426 if (mult == 0) 2427 return (USB_ERR_BAD_BUFSIZE); 2428 2429 endp = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_ep[epno - 1], 2430 buf_inp.buffer); 2431 2432 /* store endpoint mode */ 2433 pepext->trb_ep_mode = ep_mode; 2434 /* store bMaxPacketSize for control endpoints */ 2435 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0]; 2436 usb_pc_cpu_flush(pepext->page_cache); 2437 2438 if (ep_mode == USB_EP_MODE_STREAMS) { 2439 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2440 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2441 XHCI_EPCTX_0_LSA_SET(1); 2442 2443 ring_addr += sizeof(struct xhci_trb) * 2444 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2445 } else { 2446 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2447 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2448 XHCI_EPCTX_0_LSA_SET(0); 2449 2450 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2451 } 2452 2453 switch (udev->speed) { 2454 case USB_SPEED_FULL: 2455 case USB_SPEED_LOW: 2456 /* 1ms -> 125us */ 2457 fps_shift += 3; 2458 break; 2459 default: 2460 break; 2461 } 2462 2463 switch (type) { 2464 case UE_INTERRUPT: 2465 if (fps_shift > 3) 2466 fps_shift--; 2467 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2468 break; 2469 case UE_ISOCHRONOUS: 2470 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2471 2472 switch (udev->speed) { 2473 case USB_SPEED_SUPER: 2474 if (mult > 3) 2475 mult = 3; 2476 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2477 max_packet_count /= mult; 2478 break; 2479 default: 2480 break; 2481 } 2482 break; 2483 default: 2484 break; 2485 } 2486 2487 endp->dwEpCtx0 = htole32(temp); 2488 2489 temp = 2490 XHCI_EPCTX_1_HID_SET(0) | 2491 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2492 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2493 2494 /* 2495 * Always enable the "three strikes and you are gone" feature 2496 * except for ISOCHRONOUS endpoints. This is suggested by 2497 * section 4.3.3 in the XHCI specification about device slot 2498 * initialisation. 2499 */ 2500 if (type != UE_ISOCHRONOUS) 2501 temp |= XHCI_EPCTX_1_CERR_SET(3); 2502 2503 switch (type) { 2504 case UE_CONTROL: 2505 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2506 break; 2507 case UE_ISOCHRONOUS: 2508 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2509 break; 2510 case UE_BULK: 2511 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2512 break; 2513 default: 2514 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2515 break; 2516 } 2517 2518 /* check for IN direction */ 2519 if (epno & 1) 2520 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2521 2522 endp->dwEpCtx1 = htole32(temp); 2523 endp->qwEpCtx2 = htole64(ring_addr); 2524 2525 switch (edesc->bmAttributes & UE_XFERTYPE) { 2526 case UE_INTERRUPT: 2527 case UE_ISOCHRONOUS: 2528 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2529 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2530 max_frame_size)); 2531 break; 2532 case UE_CONTROL: 2533 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2534 break; 2535 default: 2536 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2537 break; 2538 } 2539 2540 endp->dwEpCtx4 = htole32(temp); 2541 2542 #ifdef USB_DEBUG 2543 xhci_dump_endpoint(endp); 2544 #endif 2545 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2546 2547 return (0); /* success */ 2548 } 2549 2550 static usb_error_t 2551 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2552 { 2553 struct xhci_endpoint_ext *pepext; 2554 struct usb_endpoint_ss_comp_descriptor *ecomp; 2555 usb_stream_t x; 2556 2557 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2558 xfer->endpoint->edesc); 2559 2560 ecomp = xfer->endpoint->ecomp; 2561 2562 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2563 uint64_t temp; 2564 2565 /* halt any transfers */ 2566 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2567 2568 /* compute start of TRB ring for stream "x" */ 2569 temp = pepext->physaddr + 2570 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2571 XHCI_SCTX_0_SCT_SEC_TR_RING; 2572 2573 /* make tree structure */ 2574 pepext->trb[(XHCI_MAX_TRANSFERS * 2575 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2576 2577 /* reserved fields */ 2578 pepext->trb[(XHCI_MAX_TRANSFERS * 2579 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2580 pepext->trb[(XHCI_MAX_TRANSFERS * 2581 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2582 } 2583 usb_pc_cpu_flush(pepext->page_cache); 2584 2585 return (xhci_configure_endpoint(xfer->xroot->udev, 2586 xfer->endpoint->edesc, pepext, 2587 xfer->interval, xfer->max_packet_count, 2588 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2589 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2590 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2591 } 2592 2593 static usb_error_t 2594 xhci_configure_device(struct usb_device *udev) 2595 { 2596 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2597 struct usb_page_search buf_inp; 2598 struct usb_page_cache *pcinp; 2599 struct xhci_slot_ctx *slot; 2600 struct usb_device *hubdev; 2601 uint32_t temp; 2602 uint32_t route; 2603 uint32_t rh_port; 2604 uint8_t is_hub; 2605 uint8_t index; 2606 uint8_t depth; 2607 2608 index = udev->controller_slot_id; 2609 2610 DPRINTF("index=%u\n", index); 2611 2612 pcinp = &sc->sc_hw.devs[index].input_pc; 2613 2614 usbd_get_page(pcinp, 0, &buf_inp); 2615 2616 slot = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_slot, buf_inp.buffer); 2617 2618 rh_port = 0; 2619 route = 0; 2620 2621 /* figure out route string and root HUB port number */ 2622 2623 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2624 if (hubdev->parent_hub == NULL) 2625 break; 2626 2627 depth = hubdev->parent_hub->depth; 2628 2629 /* 2630 * NOTE: HS/FS/LS devices and the SS root HUB can have 2631 * more than 15 ports 2632 */ 2633 2634 rh_port = hubdev->port_no; 2635 2636 if (depth == 0) 2637 break; 2638 2639 if (rh_port > 15) 2640 rh_port = 15; 2641 2642 if (depth < 6) 2643 route |= rh_port << (4 * (depth - 1)); 2644 } 2645 2646 DPRINTF("Route=0x%08x\n", route); 2647 2648 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2649 XHCI_SCTX_0_CTX_NUM_SET( 2650 sc->sc_hw.devs[index].context_num + 1); 2651 2652 switch (udev->speed) { 2653 case USB_SPEED_LOW: 2654 temp |= XHCI_SCTX_0_SPEED_SET(2); 2655 if (udev->parent_hs_hub != NULL && 2656 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2657 UDPROTO_HSHUBMTT) { 2658 DPRINTF("Device inherits MTT\n"); 2659 temp |= XHCI_SCTX_0_MTT_SET(1); 2660 } 2661 break; 2662 case USB_SPEED_HIGH: 2663 temp |= XHCI_SCTX_0_SPEED_SET(3); 2664 if (sc->sc_hw.devs[index].nports != 0 && 2665 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2666 DPRINTF("HUB supports MTT\n"); 2667 temp |= XHCI_SCTX_0_MTT_SET(1); 2668 } 2669 break; 2670 case USB_SPEED_FULL: 2671 temp |= XHCI_SCTX_0_SPEED_SET(1); 2672 if (udev->parent_hs_hub != NULL && 2673 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2674 UDPROTO_HSHUBMTT) { 2675 DPRINTF("Device inherits MTT\n"); 2676 temp |= XHCI_SCTX_0_MTT_SET(1); 2677 } 2678 break; 2679 default: 2680 temp |= XHCI_SCTX_0_SPEED_SET(4); 2681 break; 2682 } 2683 2684 is_hub = sc->sc_hw.devs[index].nports != 0 && 2685 (udev->speed == USB_SPEED_SUPER || 2686 udev->speed == USB_SPEED_HIGH); 2687 2688 if (is_hub) 2689 temp |= XHCI_SCTX_0_HUB_SET(1); 2690 2691 slot->dwSctx0 = htole32(temp); 2692 2693 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2694 2695 if (is_hub) { 2696 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2697 sc->sc_hw.devs[index].nports); 2698 } 2699 2700 slot->dwSctx1 = htole32(temp); 2701 2702 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2703 2704 if (is_hub) { 2705 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2706 sc->sc_hw.devs[index].tt); 2707 } 2708 2709 hubdev = udev->parent_hs_hub; 2710 2711 /* check if we should activate the transaction translator */ 2712 switch (udev->speed) { 2713 case USB_SPEED_FULL: 2714 case USB_SPEED_LOW: 2715 if (hubdev != NULL) { 2716 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2717 hubdev->controller_slot_id); 2718 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2719 udev->hs_port_no); 2720 } 2721 break; 2722 default: 2723 break; 2724 } 2725 2726 slot->dwSctx2 = htole32(temp); 2727 2728 /* 2729 * These fields should be initialized to zero, according to 2730 * XHCI section 6.2.2 - slot context: 2731 */ 2732 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2733 XHCI_SCTX_3_SLOT_STATE_SET(0); 2734 2735 slot->dwSctx3 = htole32(temp); 2736 2737 #ifdef USB_DEBUG 2738 xhci_dump_device(slot); 2739 #endif 2740 usb_pc_cpu_flush(pcinp); 2741 2742 return (0); /* success */ 2743 } 2744 2745 static usb_error_t 2746 xhci_alloc_device_ext(struct usb_device *udev) 2747 { 2748 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2749 struct usb_page_search buf_dev; 2750 struct usb_page_search buf_ep; 2751 struct xhci_trb *trb; 2752 struct usb_page_cache *pc; 2753 struct usb_page *pg; 2754 uint64_t addr; 2755 uint8_t index; 2756 uint8_t i; 2757 2758 index = udev->controller_slot_id; 2759 2760 pc = &sc->sc_hw.devs[index].device_pc; 2761 pg = &sc->sc_hw.devs[index].device_pg; 2762 2763 /* need to initialize the page cache */ 2764 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2765 2766 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2767 sizeof(struct xhci_dev_ctx64) : 2768 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2769 goto error; 2770 2771 usbd_get_page(pc, 0, &buf_dev); 2772 2773 pc = &sc->sc_hw.devs[index].input_pc; 2774 pg = &sc->sc_hw.devs[index].input_pg; 2775 2776 /* need to initialize the page cache */ 2777 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2778 2779 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2780 sizeof(struct xhci_input_dev_ctx64) : 2781 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2782 goto error; 2783 } 2784 2785 /* initialize all endpoint LINK TRBs */ 2786 2787 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2788 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2789 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2790 2791 /* need to initialize the page cache */ 2792 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2793 2794 if (usb_pc_alloc_mem(pc, pg, 2795 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2796 goto error; 2797 } 2798 2799 /* lookup endpoint TRB ring */ 2800 usbd_get_page(pc, 0, &buf_ep); 2801 2802 /* get TRB pointer */ 2803 trb = buf_ep.buffer; 2804 trb += XHCI_MAX_TRANSFERS - 1; 2805 2806 /* get TRB start address */ 2807 addr = buf_ep.physaddr; 2808 2809 /* create LINK TRB */ 2810 trb->qwTrb0 = htole64(addr); 2811 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2812 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2813 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2814 2815 usb_pc_cpu_flush(pc); 2816 } 2817 2818 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2819 2820 return (0); 2821 2822 error: 2823 xhci_free_device_ext(udev); 2824 2825 return (USB_ERR_NOMEM); 2826 } 2827 2828 static void 2829 xhci_free_device_ext(struct usb_device *udev) 2830 { 2831 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2832 uint8_t index; 2833 uint8_t i; 2834 2835 index = udev->controller_slot_id; 2836 xhci_set_slot_pointer(sc, index, 0); 2837 2838 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2839 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2840 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2841 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2842 } 2843 2844 static struct xhci_endpoint_ext * 2845 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2846 { 2847 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2848 struct xhci_endpoint_ext *pepext; 2849 struct usb_page_cache *pc; 2850 struct usb_page_search buf_ep; 2851 uint8_t epno; 2852 uint8_t index; 2853 2854 epno = edesc->bEndpointAddress; 2855 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2856 epno |= UE_DIR_IN; 2857 2858 epno = XHCI_EPNO2EPID(epno); 2859 2860 index = udev->controller_slot_id; 2861 2862 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2863 2864 usbd_get_page(pc, 0, &buf_ep); 2865 2866 pepext = &sc->sc_hw.devs[index].endp[epno]; 2867 pepext->page_cache = pc; 2868 pepext->trb = buf_ep.buffer; 2869 pepext->physaddr = buf_ep.physaddr; 2870 2871 return (pepext); 2872 } 2873 2874 static void 2875 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2876 { 2877 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2878 uint8_t epno; 2879 uint8_t index; 2880 2881 epno = xfer->endpointno; 2882 if (xfer->flags_int.control_xfr) 2883 epno |= UE_DIR_IN; 2884 2885 epno = XHCI_EPNO2EPID(epno); 2886 index = xfer->xroot->udev->controller_slot_id; 2887 2888 if (xfer->xroot->udev->flags.self_suspended == 0) { 2889 XWRITE4(sc, door, XHCI_DOORBELL(index), 2890 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2891 } 2892 } 2893 2894 static void 2895 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2896 { 2897 struct xhci_endpoint_ext *pepext; 2898 2899 if (xfer->flags_int.bandwidth_reclaimed) { 2900 xfer->flags_int.bandwidth_reclaimed = 0; 2901 2902 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2903 xfer->endpoint->edesc); 2904 2905 pepext->trb_used[xfer->stream_id]--; 2906 2907 pepext->xfer[xfer->qh_pos] = NULL; 2908 2909 if (error && pepext->trb_running != 0) { 2910 pepext->trb_halted = 1; 2911 pepext->trb_running = 0; 2912 } 2913 } 2914 } 2915 2916 static usb_error_t 2917 xhci_transfer_insert(struct usb_xfer *xfer) 2918 { 2919 struct xhci_td *td_first; 2920 struct xhci_td *td_last; 2921 struct xhci_trb *trb_link; 2922 struct xhci_endpoint_ext *pepext; 2923 uint64_t addr; 2924 usb_stream_t id; 2925 uint8_t i; 2926 uint8_t inext; 2927 uint8_t trb_limit; 2928 2929 DPRINTFN(8, "\n"); 2930 2931 id = xfer->stream_id; 2932 2933 /* check if already inserted */ 2934 if (xfer->flags_int.bandwidth_reclaimed) { 2935 DPRINTFN(8, "Already in schedule\n"); 2936 return (0); 2937 } 2938 2939 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2940 xfer->endpoint->edesc); 2941 2942 td_first = xfer->td_transfer_first; 2943 td_last = xfer->td_transfer_last; 2944 addr = pepext->physaddr; 2945 2946 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2947 case UE_CONTROL: 2948 case UE_INTERRUPT: 2949 /* single buffered */ 2950 trb_limit = 1; 2951 break; 2952 default: 2953 /* multi buffered */ 2954 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2955 break; 2956 } 2957 2958 if (pepext->trb_used[id] >= trb_limit) { 2959 DPRINTFN(8, "Too many TDs queued.\n"); 2960 return (USB_ERR_NOMEM); 2961 } 2962 2963 /* check if bMaxPacketSize changed */ 2964 if (xfer->flags_int.control_xfr != 0 && 2965 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) { 2966 DPRINTFN(8, "Reconfigure control endpoint\n"); 2967 2968 /* force driver to reconfigure endpoint */ 2969 pepext->trb_halted = 1; 2970 pepext->trb_running = 0; 2971 } 2972 2973 /* check for stopped condition, after putting transfer on interrupt queue */ 2974 if (pepext->trb_running == 0) { 2975 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2976 2977 DPRINTFN(8, "Not running\n"); 2978 2979 /* start configuration */ 2980 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2981 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2982 return (0); 2983 } 2984 2985 pepext->trb_used[id]++; 2986 2987 /* get current TRB index */ 2988 i = pepext->trb_index[id]; 2989 2990 /* get next TRB index */ 2991 inext = (i + 1); 2992 2993 /* the last entry of the ring is a hardcoded link TRB */ 2994 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2995 inext = 0; 2996 2997 /* store next TRB index, before stream ID offset is added */ 2998 pepext->trb_index[id] = inext; 2999 3000 /* offset for stream */ 3001 i += id * XHCI_MAX_TRANSFERS; 3002 inext += id * XHCI_MAX_TRANSFERS; 3003 3004 /* compute terminating return address */ 3005 addr += (inext * sizeof(struct xhci_trb)); 3006 3007 /* compute link TRB pointer */ 3008 trb_link = td_last->td_trb + td_last->ntrb; 3009 3010 /* update next pointer of last link TRB */ 3011 trb_link->qwTrb0 = htole64(addr); 3012 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 3013 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 3014 XHCI_TRB_3_CYCLE_BIT | 3015 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 3016 3017 #ifdef USB_DEBUG 3018 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 3019 #endif 3020 usb_pc_cpu_flush(td_last->page_cache); 3021 3022 /* write ahead chain end marker */ 3023 3024 pepext->trb[inext].qwTrb0 = 0; 3025 pepext->trb[inext].dwTrb2 = 0; 3026 pepext->trb[inext].dwTrb3 = 0; 3027 3028 /* update next pointer of link TRB */ 3029 3030 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 3031 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 3032 3033 #ifdef USB_DEBUG 3034 xhci_dump_trb(&pepext->trb[i]); 3035 #endif 3036 usb_pc_cpu_flush(pepext->page_cache); 3037 3038 /* toggle cycle bit which activates the transfer chain */ 3039 3040 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 3041 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 3042 3043 usb_pc_cpu_flush(pepext->page_cache); 3044 3045 DPRINTF("qh_pos = %u\n", i); 3046 3047 pepext->xfer[i] = xfer; 3048 3049 xfer->qh_pos = i; 3050 3051 xfer->flags_int.bandwidth_reclaimed = 1; 3052 3053 xhci_endpoint_doorbell(xfer); 3054 3055 return (0); 3056 } 3057 3058 static void 3059 xhci_root_intr(struct xhci_softc *sc) 3060 { 3061 uint16_t i; 3062 3063 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3064 3065 /* clear any old interrupt data */ 3066 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 3067 3068 for (i = 1; i <= sc->sc_noport; i++) { 3069 /* pick out CHANGE bits from the status register */ 3070 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 3071 XHCI_PS_CSC | XHCI_PS_PEC | 3072 XHCI_PS_OCC | XHCI_PS_WRC | 3073 XHCI_PS_PRC | XHCI_PS_PLC | 3074 XHCI_PS_CEC)) { 3075 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 3076 DPRINTF("port %d changed\n", i); 3077 } 3078 } 3079 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3080 sizeof(sc->sc_hub_idata)); 3081 } 3082 3083 /*------------------------------------------------------------------------* 3084 * xhci_device_done - XHCI done handler 3085 * 3086 * NOTE: This function can be called two times in a row on 3087 * the same USB transfer. From close and from interrupt. 3088 *------------------------------------------------------------------------*/ 3089 static void 3090 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 3091 { 3092 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 3093 xfer, xfer->endpoint, error); 3094 3095 /* remove transfer from HW queue */ 3096 xhci_transfer_remove(xfer, error); 3097 3098 /* dequeue transfer and start next transfer */ 3099 usbd_transfer_done(xfer, error); 3100 } 3101 3102 /*------------------------------------------------------------------------* 3103 * XHCI data transfer support (generic type) 3104 *------------------------------------------------------------------------*/ 3105 static void 3106 xhci_device_generic_open(struct usb_xfer *xfer) 3107 { 3108 DPRINTF("\n"); 3109 } 3110 3111 static void 3112 xhci_device_generic_close(struct usb_xfer *xfer) 3113 { 3114 DPRINTF("\n"); 3115 3116 xhci_device_done(xfer, USB_ERR_CANCELLED); 3117 } 3118 3119 static void 3120 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3121 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3122 { 3123 struct usb_xfer *xfer; 3124 3125 /* check if there is a current transfer */ 3126 xfer = ep->endpoint_q[stream_id].curr; 3127 if (xfer == NULL) 3128 return; 3129 3130 /* 3131 * Check if the current transfer is started and then pickup 3132 * the next one, if any. Else wait for next start event due to 3133 * block on failure feature. 3134 */ 3135 if (!xfer->flags_int.bandwidth_reclaimed) 3136 return; 3137 3138 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3139 if (xfer == NULL) { 3140 /* 3141 * In case of enter we have to consider that the 3142 * transfer is queued by the USB core after the enter 3143 * method is called. 3144 */ 3145 xfer = enter_xfer; 3146 3147 if (xfer == NULL) 3148 return; 3149 } 3150 3151 /* try to multi buffer */ 3152 xhci_transfer_insert(xfer); 3153 } 3154 3155 static void 3156 xhci_device_generic_enter(struct usb_xfer *xfer) 3157 { 3158 DPRINTF("\n"); 3159 3160 /* set up TD's and QH */ 3161 xhci_setup_generic_chain(xfer); 3162 3163 xhci_device_generic_multi_enter(xfer->endpoint, 3164 xfer->stream_id, xfer); 3165 } 3166 3167 static void 3168 xhci_device_generic_start(struct usb_xfer *xfer) 3169 { 3170 DPRINTF("\n"); 3171 3172 /* try to insert xfer on HW queue */ 3173 xhci_transfer_insert(xfer); 3174 3175 /* try to multi buffer */ 3176 xhci_device_generic_multi_enter(xfer->endpoint, 3177 xfer->stream_id, NULL); 3178 3179 /* add transfer last on interrupt queue */ 3180 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3181 3182 /* start timeout, if any */ 3183 if (xfer->timeout != 0) 3184 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3185 } 3186 3187 static const struct usb_pipe_methods xhci_device_generic_methods = 3188 { 3189 .open = xhci_device_generic_open, 3190 .close = xhci_device_generic_close, 3191 .enter = xhci_device_generic_enter, 3192 .start = xhci_device_generic_start, 3193 }; 3194 3195 /*------------------------------------------------------------------------* 3196 * xhci root HUB support 3197 *------------------------------------------------------------------------* 3198 * Simulate a hardware HUB by handling all the necessary requests. 3199 *------------------------------------------------------------------------*/ 3200 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3201 3202 static const 3203 struct usb_device_descriptor xhci_devd = 3204 { 3205 .bLength = sizeof(xhci_devd), 3206 .bDescriptorType = UDESC_DEVICE, /* type */ 3207 HSETW(.bcdUSB, 0x0300), /* USB version */ 3208 .bDeviceClass = UDCLASS_HUB, /* class */ 3209 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3210 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3211 .bMaxPacketSize = 9, /* max packet size */ 3212 HSETW(.idVendor, 0x0000), /* vendor */ 3213 HSETW(.idProduct, 0x0000), /* product */ 3214 HSETW(.bcdDevice, 0x0100), /* device version */ 3215 .iManufacturer = 1, 3216 .iProduct = 2, 3217 .iSerialNumber = 0, 3218 .bNumConfigurations = 1, /* # of configurations */ 3219 }; 3220 3221 static const 3222 struct xhci_bos_desc xhci_bosd = { 3223 .bosd = { 3224 .bLength = sizeof(xhci_bosd.bosd), 3225 .bDescriptorType = UDESC_BOS, 3226 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3227 .bNumDeviceCaps = 3, 3228 }, 3229 .usb2extd = { 3230 .bLength = sizeof(xhci_bosd.usb2extd), 3231 .bDescriptorType = 1, 3232 .bDevCapabilityType = 2, 3233 .bmAttributes[0] = 2, 3234 }, 3235 .usbdcd = { 3236 .bLength = sizeof(xhci_bosd.usbdcd), 3237 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3238 .bDevCapabilityType = 3, 3239 .bmAttributes = 0, /* XXX */ 3240 HSETW(.wSpeedsSupported, 0x000C), 3241 .bFunctionalitySupport = 8, 3242 .bU1DevExitLat = 255, /* dummy - not used */ 3243 .wU2DevExitLat = { 0x00, 0x08 }, 3244 }, 3245 .cidd = { 3246 .bLength = sizeof(xhci_bosd.cidd), 3247 .bDescriptorType = 1, 3248 .bDevCapabilityType = 4, 3249 .bReserved = 0, 3250 .bContainerID = 0, /* XXX */ 3251 }, 3252 }; 3253 3254 static const 3255 struct xhci_config_desc xhci_confd = { 3256 .confd = { 3257 .bLength = sizeof(xhci_confd.confd), 3258 .bDescriptorType = UDESC_CONFIG, 3259 .wTotalLength[0] = sizeof(xhci_confd), 3260 .bNumInterface = 1, 3261 .bConfigurationValue = 1, 3262 .iConfiguration = 0, 3263 .bmAttributes = UC_SELF_POWERED, 3264 .bMaxPower = 0 /* max power */ 3265 }, 3266 .ifcd = { 3267 .bLength = sizeof(xhci_confd.ifcd), 3268 .bDescriptorType = UDESC_INTERFACE, 3269 .bNumEndpoints = 1, 3270 .bInterfaceClass = UICLASS_HUB, 3271 .bInterfaceSubClass = UISUBCLASS_HUB, 3272 .bInterfaceProtocol = 0, 3273 }, 3274 .endpd = { 3275 .bLength = sizeof(xhci_confd.endpd), 3276 .bDescriptorType = UDESC_ENDPOINT, 3277 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3278 .bmAttributes = UE_INTERRUPT, 3279 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3280 .bInterval = 255, 3281 }, 3282 .endpcd = { 3283 .bLength = sizeof(xhci_confd.endpcd), 3284 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3285 .bMaxBurst = 0, 3286 .bmAttributes = 0, 3287 }, 3288 }; 3289 3290 static const 3291 struct usb_hub_ss_descriptor xhci_hubd = { 3292 .bLength = sizeof(xhci_hubd), 3293 .bDescriptorType = UDESC_SS_HUB, 3294 }; 3295 3296 static usb_error_t 3297 xhci_roothub_exec(struct usb_device *udev, 3298 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3299 { 3300 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3301 const char *str_ptr; 3302 const void *ptr; 3303 uint32_t port; 3304 uint32_t v; 3305 uint16_t len; 3306 uint16_t i; 3307 uint16_t value; 3308 uint16_t index; 3309 uint8_t j; 3310 usb_error_t err; 3311 3312 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3313 3314 /* buffer reset */ 3315 ptr = (const void *)&sc->sc_hub_desc; 3316 len = 0; 3317 err = 0; 3318 3319 value = UGETW(req->wValue); 3320 index = UGETW(req->wIndex); 3321 3322 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3323 "wValue=0x%04x wIndex=0x%04x\n", 3324 req->bmRequestType, req->bRequest, 3325 UGETW(req->wLength), value, index); 3326 3327 #define C(x,y) ((x) | ((y) << 8)) 3328 switch (C(req->bRequest, req->bmRequestType)) { 3329 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3330 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3331 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3332 /* 3333 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3334 * for the integrated root hub. 3335 */ 3336 break; 3337 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3338 len = 1; 3339 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3340 break; 3341 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3342 switch (value >> 8) { 3343 case UDESC_DEVICE: 3344 if ((value & 0xff) != 0) { 3345 err = USB_ERR_IOERROR; 3346 goto done; 3347 } 3348 len = sizeof(xhci_devd); 3349 ptr = (const void *)&xhci_devd; 3350 break; 3351 3352 case UDESC_BOS: 3353 if ((value & 0xff) != 0) { 3354 err = USB_ERR_IOERROR; 3355 goto done; 3356 } 3357 len = sizeof(xhci_bosd); 3358 ptr = (const void *)&xhci_bosd; 3359 break; 3360 3361 case UDESC_CONFIG: 3362 if ((value & 0xff) != 0) { 3363 err = USB_ERR_IOERROR; 3364 goto done; 3365 } 3366 len = sizeof(xhci_confd); 3367 ptr = (const void *)&xhci_confd; 3368 break; 3369 3370 case UDESC_STRING: 3371 switch (value & 0xff) { 3372 case 0: /* Language table */ 3373 str_ptr = "\001"; 3374 break; 3375 3376 case 1: /* Vendor */ 3377 str_ptr = sc->sc_vendor; 3378 break; 3379 3380 case 2: /* Product */ 3381 str_ptr = "XHCI root HUB"; 3382 break; 3383 3384 default: 3385 str_ptr = ""; 3386 break; 3387 } 3388 3389 len = usb_make_str_desc( 3390 sc->sc_hub_desc.temp, 3391 sizeof(sc->sc_hub_desc.temp), 3392 str_ptr); 3393 break; 3394 3395 default: 3396 err = USB_ERR_IOERROR; 3397 goto done; 3398 } 3399 break; 3400 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3401 len = 1; 3402 sc->sc_hub_desc.temp[0] = 0; 3403 break; 3404 case C(UR_GET_STATUS, UT_READ_DEVICE): 3405 len = 2; 3406 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3407 break; 3408 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3409 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3410 len = 2; 3411 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3412 break; 3413 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3414 if (value >= XHCI_MAX_DEVICES) { 3415 err = USB_ERR_IOERROR; 3416 goto done; 3417 } 3418 break; 3419 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3420 if (value != 0 && value != 1) { 3421 err = USB_ERR_IOERROR; 3422 goto done; 3423 } 3424 sc->sc_conf = value; 3425 break; 3426 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3427 break; 3428 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3429 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3430 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3431 err = USB_ERR_IOERROR; 3432 goto done; 3433 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3434 break; 3435 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3436 break; 3437 /* Hub requests */ 3438 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3439 break; 3440 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3441 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3442 3443 if ((index < 1) || 3444 (index > sc->sc_noport)) { 3445 err = USB_ERR_IOERROR; 3446 goto done; 3447 } 3448 port = XHCI_PORTSC(index); 3449 3450 v = XREAD4(sc, oper, port); 3451 i = XHCI_PS_PLS_GET(v); 3452 v &= ~XHCI_PS_CLEAR; 3453 3454 switch (value) { 3455 case UHF_C_BH_PORT_RESET: 3456 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3457 break; 3458 case UHF_C_PORT_CONFIG_ERROR: 3459 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3460 break; 3461 case UHF_C_PORT_SUSPEND: 3462 case UHF_C_PORT_LINK_STATE: 3463 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3464 break; 3465 case UHF_C_PORT_CONNECTION: 3466 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3467 break; 3468 case UHF_C_PORT_ENABLE: 3469 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3470 break; 3471 case UHF_C_PORT_OVER_CURRENT: 3472 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3473 break; 3474 case UHF_C_PORT_RESET: 3475 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3476 break; 3477 case UHF_PORT_ENABLE: 3478 if ((sc->sc_quirks & XHCI_QUIRK_DISABLE_PORT_PED) == 0) 3479 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3480 break; 3481 case UHF_PORT_POWER: 3482 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3483 break; 3484 case UHF_PORT_INDICATOR: 3485 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3486 break; 3487 case UHF_PORT_SUSPEND: 3488 3489 /* U3 -> U15 */ 3490 if (i == 3) { 3491 XWRITE4(sc, oper, port, v | 3492 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3493 } 3494 3495 /* wait 20ms for resume sequence to complete */ 3496 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3497 3498 /* U0 */ 3499 XWRITE4(sc, oper, port, v | 3500 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3501 break; 3502 default: 3503 err = USB_ERR_IOERROR; 3504 goto done; 3505 } 3506 break; 3507 3508 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3509 if ((value & 0xff) != 0) { 3510 err = USB_ERR_IOERROR; 3511 goto done; 3512 } 3513 3514 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3515 3516 sc->sc_hub_desc.hubd = xhci_hubd; 3517 3518 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3519 3520 if (XHCI_HCS0_PPC(v)) 3521 i = UHD_PWR_INDIVIDUAL; 3522 else 3523 i = UHD_PWR_GANGED; 3524 3525 if (XHCI_HCS0_PIND(v)) 3526 i |= UHD_PORT_IND; 3527 3528 i |= UHD_OC_INDIVIDUAL; 3529 3530 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3531 3532 /* see XHCI section 5.4.9: */ 3533 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3534 3535 for (j = 1; j <= sc->sc_noport; j++) { 3536 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3537 if (v & XHCI_PS_DR) { 3538 sc->sc_hub_desc.hubd. 3539 DeviceRemovable[j / 8] |= 1U << (j % 8); 3540 } 3541 } 3542 len = sc->sc_hub_desc.hubd.bLength; 3543 break; 3544 3545 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3546 len = 16; 3547 memset(sc->sc_hub_desc.temp, 0, 16); 3548 break; 3549 3550 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3551 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3552 3553 if ((index < 1) || 3554 (index > sc->sc_noport)) { 3555 err = USB_ERR_IOERROR; 3556 goto done; 3557 } 3558 3559 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3560 3561 DPRINTFN(9, "port status=0x%08x\n", v); 3562 3563 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3564 3565 switch (XHCI_PS_SPEED_GET(v)) { 3566 case XHCI_PS_SPEED_HIGH: 3567 i |= UPS_HIGH_SPEED; 3568 break; 3569 case XHCI_PS_SPEED_LOW: 3570 i |= UPS_LOW_SPEED; 3571 break; 3572 case XHCI_PS_SPEED_FULL: 3573 /* FULL speed */ 3574 break; 3575 default: 3576 i |= UPS_OTHER_SPEED; 3577 break; 3578 } 3579 3580 if (v & XHCI_PS_CCS) 3581 i |= UPS_CURRENT_CONNECT_STATUS; 3582 if (v & XHCI_PS_PED) 3583 i |= UPS_PORT_ENABLED; 3584 if (v & XHCI_PS_OCA) 3585 i |= UPS_OVERCURRENT_INDICATOR; 3586 if (v & XHCI_PS_PR) 3587 i |= UPS_RESET; 3588 #if 0 3589 if (v & XHCI_PS_PP) 3590 /* XXX undefined */ 3591 #endif 3592 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3593 3594 i = 0; 3595 if (v & XHCI_PS_CSC) 3596 i |= UPS_C_CONNECT_STATUS; 3597 if (v & XHCI_PS_PEC) 3598 i |= UPS_C_PORT_ENABLED; 3599 if (v & XHCI_PS_OCC) 3600 i |= UPS_C_OVERCURRENT_INDICATOR; 3601 if (v & XHCI_PS_WRC) 3602 i |= UPS_C_BH_PORT_RESET; 3603 if (v & XHCI_PS_PRC) 3604 i |= UPS_C_PORT_RESET; 3605 if (v & XHCI_PS_PLC) 3606 i |= UPS_C_PORT_LINK_STATE; 3607 if (v & XHCI_PS_CEC) 3608 i |= UPS_C_PORT_CONFIG_ERROR; 3609 3610 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3611 len = sizeof(sc->sc_hub_desc.ps); 3612 break; 3613 3614 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3615 err = USB_ERR_IOERROR; 3616 goto done; 3617 3618 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3619 break; 3620 3621 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3622 3623 i = index >> 8; 3624 index &= 0x00FF; 3625 3626 if ((index < 1) || 3627 (index > sc->sc_noport)) { 3628 err = USB_ERR_IOERROR; 3629 goto done; 3630 } 3631 3632 port = XHCI_PORTSC(index); 3633 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3634 3635 switch (value) { 3636 case UHF_PORT_U1_TIMEOUT: 3637 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3638 err = USB_ERR_IOERROR; 3639 goto done; 3640 } 3641 port = XHCI_PORTPMSC(index); 3642 v = XREAD4(sc, oper, port); 3643 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3644 v |= XHCI_PM3_U1TO_SET(i); 3645 XWRITE4(sc, oper, port, v); 3646 break; 3647 case UHF_PORT_U2_TIMEOUT: 3648 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3649 err = USB_ERR_IOERROR; 3650 goto done; 3651 } 3652 port = XHCI_PORTPMSC(index); 3653 v = XREAD4(sc, oper, port); 3654 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3655 v |= XHCI_PM3_U2TO_SET(i); 3656 XWRITE4(sc, oper, port, v); 3657 break; 3658 case UHF_BH_PORT_RESET: 3659 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3660 break; 3661 case UHF_PORT_LINK_STATE: 3662 XWRITE4(sc, oper, port, v | 3663 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3664 /* 4ms settle time */ 3665 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3666 break; 3667 case UHF_PORT_ENABLE: 3668 DPRINTFN(3, "set port enable %d\n", index); 3669 break; 3670 case UHF_PORT_SUSPEND: 3671 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3672 j = XHCI_PS_SPEED_GET(v); 3673 if (j == 0 || j >= XHCI_PS_SPEED_SS) { 3674 /* non-supported speed */ 3675 err = USB_ERR_IOERROR; 3676 goto done; 3677 } 3678 XWRITE4(sc, oper, port, v | 3679 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3680 break; 3681 case UHF_PORT_RESET: 3682 DPRINTFN(6, "reset port %d\n", index); 3683 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3684 break; 3685 case UHF_PORT_POWER: 3686 DPRINTFN(3, "set port power %d\n", index); 3687 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3688 break; 3689 case UHF_PORT_TEST: 3690 DPRINTFN(3, "set port test %d\n", index); 3691 break; 3692 case UHF_PORT_INDICATOR: 3693 DPRINTFN(3, "set port indicator %d\n", index); 3694 3695 v &= ~XHCI_PS_PIC_SET(3); 3696 v |= XHCI_PS_PIC_SET(1); 3697 3698 XWRITE4(sc, oper, port, v); 3699 break; 3700 default: 3701 err = USB_ERR_IOERROR; 3702 goto done; 3703 } 3704 break; 3705 3706 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3707 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3708 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3709 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3710 break; 3711 default: 3712 err = USB_ERR_IOERROR; 3713 goto done; 3714 } 3715 done: 3716 *plength = len; 3717 *pptr = ptr; 3718 return (err); 3719 } 3720 3721 static void 3722 xhci_xfer_setup(struct usb_setup_params *parm) 3723 { 3724 struct usb_page_search page_info; 3725 struct usb_page_cache *pc; 3726 struct usb_xfer *xfer; 3727 void *last_obj; 3728 uint32_t ntd; 3729 uint32_t n; 3730 3731 xfer = parm->curr_xfer; 3732 3733 /* 3734 * The proof for the "ntd" formula is illustrated like this: 3735 * 3736 * +------------------------------------+ 3737 * | | 3738 * | |remainder -> | 3739 * | +-----+---+ | 3740 * | | xxx | x | frm 0 | 3741 * | +-----+---++ | 3742 * | | xxx | xx | frm 1 | 3743 * | +-----+----+ | 3744 * | ... | 3745 * +------------------------------------+ 3746 * 3747 * "xxx" means a completely full USB transfer descriptor 3748 * 3749 * "x" and "xx" means a short USB packet 3750 * 3751 * For the remainder of an USB transfer modulo 3752 * "max_data_length" we need two USB transfer descriptors. 3753 * One to transfer the remaining data and one to finalise with 3754 * a zero length packet in case the "force_short_xfer" flag is 3755 * set. We only need two USB transfer descriptors in the case 3756 * where the transfer length of the first one is a factor of 3757 * "max_frame_size". The rest of the needed USB transfer 3758 * descriptors is given by the buffer size divided by the 3759 * maximum data payload. 3760 */ 3761 parm->hc_max_packet_size = 0x400; 3762 parm->hc_max_packet_count = 16 * 3; 3763 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3764 3765 xfer->flags_int.bdma_enable = 1; 3766 3767 usbd_transfer_setup_sub(parm); 3768 3769 if (xfer->flags_int.isochronous_xfr) { 3770 ntd = ((1 * xfer->nframes) 3771 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3772 } else if (xfer->flags_int.control_xfr) { 3773 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3774 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3775 } else { 3776 ntd = ((2 * xfer->nframes) 3777 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3778 } 3779 3780 alloc_dma_set: 3781 3782 if (parm->err) 3783 return; 3784 3785 /* 3786 * Allocate queue heads and transfer descriptors 3787 */ 3788 last_obj = NULL; 3789 3790 if (usbd_transfer_setup_sub_malloc( 3791 parm, &pc, sizeof(struct xhci_td), 3792 XHCI_TD_ALIGN, ntd)) { 3793 parm->err = USB_ERR_NOMEM; 3794 return; 3795 } 3796 if (parm->buf) { 3797 for (n = 0; n != ntd; n++) { 3798 struct xhci_td *td; 3799 3800 usbd_get_page(pc + n, 0, &page_info); 3801 3802 td = page_info.buffer; 3803 3804 /* init TD */ 3805 td->td_self = page_info.physaddr; 3806 td->obj_next = last_obj; 3807 td->page_cache = pc + n; 3808 3809 last_obj = td; 3810 3811 usb_pc_cpu_flush(pc + n); 3812 } 3813 } 3814 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3815 3816 if (!xfer->flags_int.curr_dma_set) { 3817 xfer->flags_int.curr_dma_set = 1; 3818 goto alloc_dma_set; 3819 } 3820 } 3821 3822 static uint8_t 3823 xhci_get_endpoint_state(struct usb_device *udev, uint8_t epno) 3824 { 3825 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3826 struct usb_page_search buf_dev; 3827 struct xhci_hw_dev *hdev; 3828 struct xhci_endp_ctx *endp; 3829 uint32_t temp; 3830 3831 MPASS(epno != 0); 3832 3833 hdev = &sc->sc_hw.devs[udev->controller_slot_id]; 3834 3835 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 3836 endp = XHCI_GET_CTX(sc, xhci_dev_ctx, ctx_ep[epno - 1], 3837 buf_dev.buffer); 3838 usb_pc_cpu_invalidate(&hdev->device_pc); 3839 3840 temp = le32toh(endp->dwEpCtx0); 3841 3842 return (XHCI_EPCTX_0_EPSTATE_GET(temp)); 3843 } 3844 3845 static usb_error_t 3846 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3847 { 3848 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3849 struct usb_page_search buf_inp; 3850 struct usb_device *udev; 3851 struct xhci_endpoint_ext *pepext; 3852 struct usb_endpoint_descriptor *edesc; 3853 struct usb_page_cache *pcinp; 3854 usb_error_t err; 3855 usb_stream_t stream_id; 3856 uint32_t mask; 3857 uint8_t index; 3858 uint8_t epno; 3859 uint8_t drop; 3860 3861 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3862 xfer->endpoint->edesc); 3863 3864 udev = xfer->xroot->udev; 3865 index = udev->controller_slot_id; 3866 3867 pcinp = &sc->sc_hw.devs[index].input_pc; 3868 3869 usbd_get_page(pcinp, 0, &buf_inp); 3870 3871 edesc = xfer->endpoint->edesc; 3872 3873 epno = edesc->bEndpointAddress; 3874 stream_id = xfer->stream_id; 3875 3876 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3877 epno |= UE_DIR_IN; 3878 3879 epno = XHCI_EPNO2EPID(epno); 3880 3881 if (epno == 0) 3882 return (USB_ERR_NO_PIPE); /* invalid */ 3883 3884 XHCI_CMD_LOCK(sc); 3885 3886 /* configure endpoint */ 3887 3888 err = xhci_configure_endpoint_by_xfer(xfer); 3889 3890 if (err != 0) { 3891 XHCI_CMD_UNLOCK(sc); 3892 return (err); 3893 } 3894 3895 /* 3896 * Get the endpoint into the stopped state according to the 3897 * endpoint context state diagram in the XHCI specification: 3898 */ 3899 switch (xhci_get_endpoint_state(udev, epno)) { 3900 case XHCI_EPCTX_0_EPSTATE_DISABLED: 3901 drop = 0; 3902 break; 3903 case XHCI_EPCTX_0_EPSTATE_STOPPED: 3904 drop = 1; 3905 break; 3906 case XHCI_EPCTX_0_EPSTATE_HALTED: 3907 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3908 drop = (err != 0); 3909 if (drop) 3910 DPRINTF("Could not reset endpoint %u\n", epno); 3911 break; 3912 default: 3913 drop = 1; 3914 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3915 if (err != 0) 3916 DPRINTF("Could not stop endpoint %u\n", epno); 3917 break; 3918 } 3919 3920 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3921 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3922 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3923 stream_id, epno, index); 3924 3925 if (err != 0) 3926 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3927 3928 /* 3929 * Get the endpoint into the running state according to the 3930 * endpoint context state diagram in the XHCI specification: 3931 */ 3932 3933 mask = (1U << epno); 3934 3935 /* 3936 * So-called control and isochronous transfer types have 3937 * predefined data toggles (USB 2.0) or sequence numbers (USB 3938 * 3.0) and does not need to be dropped. 3939 */ 3940 if (drop != 0 && 3941 (edesc->bmAttributes & UE_XFERTYPE) != UE_CONTROL && 3942 (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) { 3943 /* drop endpoint context to reset data toggle value, if any. */ 3944 xhci_configure_mask(udev, mask, 1); 3945 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3946 if (err != 0) { 3947 DPRINTF("Could not drop " 3948 "endpoint %u at slot %u.\n", epno, index); 3949 } else { 3950 sc->sc_hw.devs[index].ep_configured &= ~mask; 3951 } 3952 } 3953 3954 /* 3955 * Always need to evaluate the slot context, because the maximum 3956 * number of endpoint contexts is stored there. 3957 */ 3958 xhci_configure_mask(udev, mask | 1U, 0); 3959 3960 if (!(sc->sc_hw.devs[index].ep_configured & mask)) { 3961 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3962 if (err == 0) 3963 sc->sc_hw.devs[index].ep_configured |= mask; 3964 } else { 3965 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3966 } 3967 3968 if (err != 0) { 3969 DPRINTF("Could not configure " 3970 "endpoint %u at slot %u.\n", epno, index); 3971 } 3972 XHCI_CMD_UNLOCK(sc); 3973 3974 return (0); 3975 } 3976 3977 static void 3978 xhci_xfer_unsetup(struct usb_xfer *xfer) 3979 { 3980 return; 3981 } 3982 3983 static void 3984 xhci_start_dma_delay(struct usb_xfer *xfer) 3985 { 3986 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3987 3988 /* put transfer on interrupt queue (again) */ 3989 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3990 3991 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3992 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3993 } 3994 3995 static void 3996 xhci_configure_msg(struct usb_proc_msg *pm) 3997 { 3998 struct xhci_softc *sc; 3999 struct xhci_endpoint_ext *pepext; 4000 struct usb_xfer *xfer; 4001 4002 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 4003 4004 restart: 4005 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4006 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 4007 xfer->endpoint->edesc); 4008 4009 if ((pepext->trb_halted != 0) || 4010 (pepext->trb_running == 0)) { 4011 uint16_t i; 4012 4013 /* clear halted and running */ 4014 pepext->trb_halted = 0; 4015 pepext->trb_running = 0; 4016 4017 /* nuke remaining buffered transfers */ 4018 4019 for (i = 0; i != (XHCI_MAX_TRANSFERS * 4020 XHCI_MAX_STREAMS); i++) { 4021 /* 4022 * NOTE: We need to use the timeout 4023 * error code here else existing 4024 * isochronous clients can get 4025 * confused: 4026 */ 4027 if (pepext->xfer[i] != NULL) { 4028 xhci_device_done(pepext->xfer[i], 4029 USB_ERR_TIMEOUT); 4030 } 4031 } 4032 4033 /* 4034 * NOTE: The USB transfer cannot vanish in 4035 * this state! 4036 */ 4037 4038 USB_BUS_UNLOCK(&sc->sc_bus); 4039 4040 xhci_configure_reset_endpoint(xfer); 4041 4042 USB_BUS_LOCK(&sc->sc_bus); 4043 4044 /* check if halted is still cleared */ 4045 if (pepext->trb_halted == 0) { 4046 pepext->trb_running = 1; 4047 memset(pepext->trb_index, 0, 4048 sizeof(pepext->trb_index)); 4049 } 4050 goto restart; 4051 } 4052 4053 if (xfer->flags_int.did_dma_delay) { 4054 /* remove transfer from interrupt queue (again) */ 4055 usbd_transfer_dequeue(xfer); 4056 4057 /* we are finally done */ 4058 usb_dma_delay_done_cb(xfer); 4059 4060 /* queue changed - restart */ 4061 goto restart; 4062 } 4063 } 4064 4065 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4066 /* try to insert xfer on HW queue */ 4067 xhci_transfer_insert(xfer); 4068 4069 /* try to multi buffer */ 4070 xhci_device_generic_multi_enter(xfer->endpoint, 4071 xfer->stream_id, NULL); 4072 } 4073 } 4074 4075 static void 4076 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4077 struct usb_endpoint *ep) 4078 { 4079 struct xhci_endpoint_ext *pepext; 4080 struct xhci_softc *sc; 4081 uint8_t index; 4082 uint8_t epno; 4083 4084 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 4085 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 4086 4087 if (udev->parent_hub == NULL) { 4088 /* root HUB has special endpoint handling */ 4089 return; 4090 } 4091 4092 ep->methods = &xhci_device_generic_methods; 4093 4094 pepext = xhci_get_endpoint_ext(udev, edesc); 4095 4096 USB_BUS_LOCK(udev->bus); 4097 pepext->trb_halted = 1; 4098 pepext->trb_running = 0; 4099 4100 /* 4101 * When doing an alternate setting, except for control 4102 * endpoints, we need to re-configure the XHCI endpoint 4103 * context: 4104 */ 4105 if ((edesc->bEndpointAddress & UE_ADDR) != 0) { 4106 sc = XHCI_BUS2SC(udev->bus); 4107 index = udev->controller_slot_id; 4108 epno = XHCI_EPNO2EPID(edesc->bEndpointAddress); 4109 sc->sc_hw.devs[index].ep_configured &= ~(1U << epno); 4110 } 4111 USB_BUS_UNLOCK(udev->bus); 4112 } 4113 4114 static void 4115 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 4116 { 4117 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4118 const struct usb_endpoint_descriptor *edesc = ep->edesc; 4119 struct usb_page_search buf_inp; 4120 struct usb_page_cache *pcinp; 4121 uint32_t mask; 4122 uint8_t index; 4123 uint8_t epno; 4124 usb_error_t err; 4125 4126 if (udev->parent_hub == NULL) { 4127 /* root HUB has special endpoint handling */ 4128 return; 4129 } 4130 4131 if ((edesc->bEndpointAddress & UE_ADDR) == 0) { 4132 /* control endpoint is never unconfigured */ 4133 return; 4134 } 4135 4136 XHCI_CMD_LOCK(sc); 4137 index = udev->controller_slot_id; 4138 epno = XHCI_EPNO2EPID(edesc->bEndpointAddress); 4139 mask = 1U << epno; 4140 4141 if (sc->sc_hw.devs[index].ep_configured & mask) { 4142 USB_BUS_LOCK(udev->bus); 4143 xhci_configure_mask(udev, mask, 1); 4144 USB_BUS_UNLOCK(udev->bus); 4145 4146 pcinp = &sc->sc_hw.devs[index].input_pc; 4147 usbd_get_page(pcinp, 0, &buf_inp); 4148 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 4149 if (err) { 4150 DPRINTF("Unconfiguring endpoint failed: %d\n", err); 4151 } else { 4152 USB_BUS_LOCK(udev->bus); 4153 sc->sc_hw.devs[index].ep_configured &= ~mask; 4154 USB_BUS_UNLOCK(udev->bus); 4155 } 4156 } 4157 XHCI_CMD_UNLOCK(sc); 4158 } 4159 4160 static void 4161 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 4162 { 4163 struct xhci_endpoint_ext *pepext; 4164 4165 DPRINTF("\n"); 4166 4167 if (udev->flags.usb_mode != USB_MODE_HOST) { 4168 /* not supported */ 4169 return; 4170 } 4171 if (udev->parent_hub == NULL) { 4172 /* root HUB has special endpoint handling */ 4173 return; 4174 } 4175 4176 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 4177 4178 USB_BUS_LOCK(udev->bus); 4179 pepext->trb_halted = 1; 4180 pepext->trb_running = 0; 4181 USB_BUS_UNLOCK(udev->bus); 4182 } 4183 4184 static usb_error_t 4185 xhci_device_init(struct usb_device *udev) 4186 { 4187 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4188 usb_error_t err; 4189 uint8_t temp; 4190 4191 /* no init for root HUB */ 4192 if (udev->parent_hub == NULL) 4193 return (0); 4194 4195 XHCI_CMD_LOCK(sc); 4196 4197 /* set invalid default */ 4198 4199 udev->controller_slot_id = sc->sc_noslot + 1; 4200 4201 /* try to get a new slot ID from the XHCI */ 4202 4203 err = xhci_cmd_enable_slot(sc, &temp); 4204 4205 if (err) { 4206 XHCI_CMD_UNLOCK(sc); 4207 return (err); 4208 } 4209 4210 if (temp > sc->sc_noslot) { 4211 XHCI_CMD_UNLOCK(sc); 4212 return (USB_ERR_BAD_ADDRESS); 4213 } 4214 4215 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4216 DPRINTF("slot %u already allocated.\n", temp); 4217 XHCI_CMD_UNLOCK(sc); 4218 return (USB_ERR_BAD_ADDRESS); 4219 } 4220 4221 /* store slot ID for later reference */ 4222 4223 udev->controller_slot_id = temp; 4224 4225 /* reset data structure */ 4226 4227 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4228 4229 /* set mark slot allocated */ 4230 4231 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4232 4233 err = xhci_alloc_device_ext(udev); 4234 4235 XHCI_CMD_UNLOCK(sc); 4236 4237 /* get device into default state */ 4238 4239 if (err == 0) 4240 err = xhci_set_address(udev, NULL, 0); 4241 4242 return (err); 4243 } 4244 4245 static void 4246 xhci_device_uninit(struct usb_device *udev) 4247 { 4248 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4249 uint8_t index; 4250 4251 /* no init for root HUB */ 4252 if (udev->parent_hub == NULL) 4253 return; 4254 4255 XHCI_CMD_LOCK(sc); 4256 4257 index = udev->controller_slot_id; 4258 4259 if (index <= sc->sc_noslot) { 4260 xhci_cmd_disable_slot(sc, index); 4261 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4262 4263 /* free device extension */ 4264 xhci_free_device_ext(udev); 4265 } 4266 4267 XHCI_CMD_UNLOCK(sc); 4268 } 4269 4270 static void 4271 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4272 { 4273 /* 4274 * Wait until the hardware has finished any possible use of 4275 * the transfer descriptor(s) 4276 */ 4277 *pus = 2048; /* microseconds */ 4278 } 4279 4280 static void 4281 xhci_device_resume(struct usb_device *udev) 4282 { 4283 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4284 uint8_t index; 4285 uint8_t n; 4286 uint8_t p; 4287 4288 DPRINTF("\n"); 4289 4290 /* check for root HUB */ 4291 if (udev->parent_hub == NULL) 4292 return; 4293 4294 index = udev->controller_slot_id; 4295 4296 XHCI_CMD_LOCK(sc); 4297 4298 /* blindly resume all endpoints */ 4299 4300 USB_BUS_LOCK(udev->bus); 4301 4302 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4303 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4304 XWRITE4(sc, door, XHCI_DOORBELL(index), 4305 n | XHCI_DB_SID_SET(p)); 4306 } 4307 } 4308 4309 USB_BUS_UNLOCK(udev->bus); 4310 4311 XHCI_CMD_UNLOCK(sc); 4312 } 4313 4314 static void 4315 xhci_device_suspend(struct usb_device *udev) 4316 { 4317 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4318 uint8_t index; 4319 uint8_t n; 4320 usb_error_t err; 4321 4322 DPRINTF("\n"); 4323 4324 /* check for root HUB */ 4325 if (udev->parent_hub == NULL) 4326 return; 4327 4328 index = udev->controller_slot_id; 4329 4330 XHCI_CMD_LOCK(sc); 4331 4332 /* blindly suspend all endpoints */ 4333 4334 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4335 err = xhci_cmd_stop_ep(sc, 1, n, index); 4336 if (err != 0) { 4337 DPRINTF("Failed to suspend endpoint " 4338 "%u on slot %u (ignored).\n", n, index); 4339 } 4340 } 4341 4342 XHCI_CMD_UNLOCK(sc); 4343 } 4344 4345 static void 4346 xhci_set_hw_power(struct usb_bus *bus) 4347 { 4348 DPRINTF("\n"); 4349 } 4350 4351 static void 4352 xhci_device_state_change(struct usb_device *udev) 4353 { 4354 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4355 struct usb_page_search buf_inp; 4356 usb_error_t err; 4357 uint8_t index; 4358 4359 /* check for root HUB */ 4360 if (udev->parent_hub == NULL) 4361 return; 4362 4363 index = udev->controller_slot_id; 4364 4365 DPRINTF("\n"); 4366 4367 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4368 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4369 &sc->sc_hw.devs[index].tt); 4370 if (err != 0) 4371 sc->sc_hw.devs[index].nports = 0; 4372 } 4373 4374 XHCI_CMD_LOCK(sc); 4375 4376 switch (usb_get_device_state(udev)) { 4377 case USB_STATE_POWERED: 4378 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4379 break; 4380 4381 /* set default state */ 4382 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4383 sc->sc_hw.devs[index].ep_configured = 3U; 4384 4385 /* reset number of contexts */ 4386 sc->sc_hw.devs[index].context_num = 0; 4387 4388 err = xhci_cmd_reset_dev(sc, index); 4389 4390 if (err != 0) { 4391 DPRINTF("Device reset failed " 4392 "for slot %u.\n", index); 4393 } 4394 break; 4395 4396 case USB_STATE_ADDRESSED: 4397 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4398 break; 4399 4400 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4401 sc->sc_hw.devs[index].ep_configured = 3U; 4402 4403 /* set configure mask to slot only */ 4404 xhci_configure_mask(udev, 1, 0); 4405 4406 /* deconfigure all endpoints, except EP0 */ 4407 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4408 4409 if (err) { 4410 DPRINTF("Failed to deconfigure " 4411 "slot %u.\n", index); 4412 } 4413 break; 4414 4415 case USB_STATE_CONFIGURED: 4416 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) { 4417 /* deconfigure all endpoints, except EP0 */ 4418 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4419 4420 if (err) { 4421 DPRINTF("Failed to deconfigure " 4422 "slot %u.\n", index); 4423 } 4424 } 4425 4426 /* set configured state */ 4427 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4428 sc->sc_hw.devs[index].ep_configured = 3U; 4429 4430 /* reset number of contexts */ 4431 sc->sc_hw.devs[index].context_num = 0; 4432 4433 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4434 4435 xhci_configure_mask(udev, 3, 0); 4436 4437 err = xhci_configure_device(udev); 4438 if (err != 0) { 4439 DPRINTF("Could not configure device " 4440 "at slot %u.\n", index); 4441 } 4442 4443 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4444 if (err != 0) { 4445 DPRINTF("Could not evaluate device " 4446 "context at slot %u.\n", index); 4447 } 4448 break; 4449 4450 default: 4451 break; 4452 } 4453 XHCI_CMD_UNLOCK(sc); 4454 } 4455 4456 static usb_error_t 4457 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4458 uint8_t ep_mode) 4459 { 4460 switch (ep_mode) { 4461 case USB_EP_MODE_DEFAULT: 4462 return (0); 4463 case USB_EP_MODE_STREAMS: 4464 if (xhcistreams == 0 || 4465 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4466 udev->speed != USB_SPEED_SUPER) 4467 return (USB_ERR_INVAL); 4468 return (0); 4469 default: 4470 return (USB_ERR_INVAL); 4471 } 4472 } 4473 4474 static const struct usb_bus_methods xhci_bus_methods = { 4475 .endpoint_init = xhci_ep_init, 4476 .endpoint_uninit = xhci_ep_uninit, 4477 .xfer_setup = xhci_xfer_setup, 4478 .xfer_unsetup = xhci_xfer_unsetup, 4479 .get_dma_delay = xhci_get_dma_delay, 4480 .device_init = xhci_device_init, 4481 .device_uninit = xhci_device_uninit, 4482 .device_resume = xhci_device_resume, 4483 .device_suspend = xhci_device_suspend, 4484 .set_hw_power = xhci_set_hw_power, 4485 .roothub_exec = xhci_roothub_exec, 4486 .xfer_poll = xhci_do_poll, 4487 .start_dma_delay = xhci_start_dma_delay, 4488 .set_address = xhci_set_address, 4489 .clear_stall = xhci_ep_clear_stall, 4490 .device_state_change = xhci_device_state_change, 4491 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4492 .set_endpoint_mode = xhci_set_endpoint_mode, 4493 }; 4494 4495 MODULE_VERSION(xhci, 1); 4496