1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36 /* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43 #ifdef USB_GLOBAL_INCLUDE_FILE 44 #include USB_GLOBAL_INCLUDE_FILE 45 #else 46 #include <sys/stdint.h> 47 #include <sys/stddef.h> 48 #include <sys/param.h> 49 #include <sys/queue.h> 50 #include <sys/types.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/bus.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/condvar.h> 58 #include <sys/sysctl.h> 59 #include <sys/sx.h> 60 #include <sys/unistd.h> 61 #include <sys/callout.h> 62 #include <sys/malloc.h> 63 #include <sys/priv.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 68 #define USB_DEBUG_VAR xhcidebug 69 70 #include <dev/usb/usb_core.h> 71 #include <dev/usb/usb_debug.h> 72 #include <dev/usb/usb_busdma.h> 73 #include <dev/usb/usb_process.h> 74 #include <dev/usb/usb_transfer.h> 75 #include <dev/usb/usb_device.h> 76 #include <dev/usb/usb_hub.h> 77 #include <dev/usb/usb_util.h> 78 79 #include <dev/usb/usb_controller.h> 80 #include <dev/usb/usb_bus.h> 81 #endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83 #include <dev/usb/controller/xhci.h> 84 #include <dev/usb/controller/xhcireg.h> 85 86 #define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90 #ifdef USB_DEBUG 91 static int xhcidebug; 92 static int xhciroute; 93 static int xhcipolling; 94 95 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 96 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 97 &xhcidebug, 0, "Debug level"); 98 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 99 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN, 100 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 101 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN, 103 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller"); 104 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling); 105 #endif 106 107 #define XHCI_INTR_ENDPT 1 108 109 struct xhci_std_temp { 110 struct xhci_softc *sc; 111 struct usb_page_cache *pc; 112 struct xhci_td *td; 113 struct xhci_td *td_next; 114 uint32_t len; 115 uint32_t offset; 116 uint32_t max_packet_size; 117 uint32_t average; 118 uint16_t isoc_delta; 119 uint16_t isoc_frame; 120 uint8_t shortpkt; 121 uint8_t multishort; 122 uint8_t last_frame; 123 uint8_t trb_type; 124 uint8_t direction; 125 uint8_t tbc; 126 uint8_t tlbpc; 127 uint8_t step_td; 128 uint8_t do_isoc_sync; 129 }; 130 131 static void xhci_do_poll(struct usb_bus *); 132 static void xhci_device_done(struct usb_xfer *, usb_error_t); 133 static void xhci_root_intr(struct xhci_softc *); 134 static void xhci_free_device_ext(struct usb_device *); 135 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 136 struct usb_endpoint_descriptor *); 137 static usb_proc_callback_t xhci_configure_msg; 138 static usb_error_t xhci_configure_device(struct usb_device *); 139 static usb_error_t xhci_configure_endpoint(struct usb_device *, 140 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 141 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 142 uint8_t); 143 static usb_error_t xhci_configure_mask(struct usb_device *, 144 uint32_t, uint8_t); 145 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 146 uint64_t, uint8_t); 147 static void xhci_endpoint_doorbell(struct usb_xfer *); 148 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 149 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 150 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 151 #ifdef USB_DEBUG 152 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 153 #endif 154 155 extern struct usb_bus_methods xhci_bus_methods; 156 157 #ifdef USB_DEBUG 158 static void 159 xhci_dump_trb(struct xhci_trb *trb) 160 { 161 DPRINTFN(5, "trb = %p\n", trb); 162 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 163 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 164 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 165 } 166 167 static void 168 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 169 { 170 DPRINTFN(5, "pep = %p\n", pep); 171 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 172 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 173 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 174 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 175 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 176 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 177 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 178 } 179 180 static void 181 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 182 { 183 DPRINTFN(5, "psl = %p\n", psl); 184 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 185 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 186 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 187 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 188 } 189 #endif 190 191 uint32_t 192 xhci_get_port_route(void) 193 { 194 #ifdef USB_DEBUG 195 return (0xFFFFFFFFU ^ ((uint32_t)xhciroute)); 196 #else 197 return (0xFFFFFFFFU); 198 #endif 199 } 200 201 uint8_t 202 xhci_use_polling(void) 203 { 204 #ifdef USB_DEBUG 205 return (xhcipolling != 0); 206 #else 207 return (0); 208 #endif 209 } 210 211 static void 212 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 213 { 214 struct xhci_softc *sc = XHCI_BUS2SC(bus); 215 uint8_t i; 216 217 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 218 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 219 220 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 221 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 222 223 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 224 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 225 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 226 } 227 } 228 229 static void 230 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 231 { 232 if (sc->sc_ctx_is_64_byte) { 233 uint32_t offset; 234 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 235 /* all contexts are initially 32-bytes */ 236 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 237 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 238 } 239 *ptr = htole32(val); 240 } 241 242 static uint32_t 243 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 244 { 245 if (sc->sc_ctx_is_64_byte) { 246 uint32_t offset; 247 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 248 /* all contexts are initially 32-bytes */ 249 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 250 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 251 } 252 return (le32toh(*ptr)); 253 } 254 255 static void 256 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 257 { 258 if (sc->sc_ctx_is_64_byte) { 259 uint32_t offset; 260 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 261 /* all contexts are initially 32-bytes */ 262 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 263 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 264 } 265 *ptr = htole64(val); 266 } 267 268 #ifdef USB_DEBUG 269 static uint64_t 270 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 271 { 272 if (sc->sc_ctx_is_64_byte) { 273 uint32_t offset; 274 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 275 /* all contexts are initially 32-bytes */ 276 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 277 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 278 } 279 return (le64toh(*ptr)); 280 } 281 #endif 282 283 usb_error_t 284 xhci_start_controller(struct xhci_softc *sc) 285 { 286 struct usb_page_search buf_res; 287 struct xhci_hw_root *phwr; 288 struct xhci_dev_ctx_addr *pdctxa; 289 uint64_t addr; 290 uint32_t temp; 291 uint16_t i; 292 293 DPRINTF("\n"); 294 295 sc->sc_capa_off = 0; 296 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 297 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 298 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 299 300 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 301 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 302 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 303 304 sc->sc_event_ccs = 1; 305 sc->sc_event_idx = 0; 306 sc->sc_command_ccs = 1; 307 sc->sc_command_idx = 0; 308 309 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 310 311 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 312 313 DPRINTF("HCS0 = 0x%08x\n", temp); 314 315 if (XHCI_HCS0_CSZ(temp)) { 316 sc->sc_ctx_is_64_byte = 1; 317 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 318 } else { 319 sc->sc_ctx_is_64_byte = 0; 320 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 321 } 322 323 /* Reset controller */ 324 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 325 326 for (i = 0; i != 100; i++) { 327 usb_pause_mtx(NULL, hz / 100); 328 temp = XREAD4(sc, oper, XHCI_USBCMD) & 329 (XHCI_CMD_HCRST | XHCI_STS_CNR); 330 if (!temp) 331 break; 332 } 333 334 if (temp) { 335 device_printf(sc->sc_bus.parent, "Controller " 336 "reset timeout.\n"); 337 return (USB_ERR_IOERROR); 338 } 339 340 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 341 device_printf(sc->sc_bus.parent, "Controller does " 342 "not support 4K page size.\n"); 343 return (USB_ERR_IOERROR); 344 } 345 346 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 347 348 i = XHCI_HCS1_N_PORTS(temp); 349 350 if (i == 0) { 351 device_printf(sc->sc_bus.parent, "Invalid number " 352 "of ports: %u\n", i); 353 return (USB_ERR_IOERROR); 354 } 355 356 sc->sc_noport = i; 357 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 358 359 if (sc->sc_noslot > XHCI_MAX_DEVICES) 360 sc->sc_noslot = XHCI_MAX_DEVICES; 361 362 /* setup number of device slots */ 363 364 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 365 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 366 367 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 368 369 DPRINTF("Max slots: %u\n", sc->sc_noslot); 370 371 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 372 373 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 374 375 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 376 device_printf(sc->sc_bus.parent, "XHCI request " 377 "too many scratchpads\n"); 378 return (USB_ERR_NOMEM); 379 } 380 381 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 382 383 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 384 385 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 386 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 387 388 temp = XREAD4(sc, oper, XHCI_USBSTS); 389 390 /* clear interrupts */ 391 XWRITE4(sc, oper, XHCI_USBSTS, temp); 392 /* disable all device notifications */ 393 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 394 395 /* setup device context base address */ 396 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 397 pdctxa = buf_res.buffer; 398 memset(pdctxa, 0, sizeof(*pdctxa)); 399 400 addr = buf_res.physaddr; 401 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 402 403 /* slot 0 points to the table of scratchpad pointers */ 404 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 405 406 for (i = 0; i != sc->sc_noscratch; i++) { 407 struct usb_page_search buf_scp; 408 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 409 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 410 } 411 412 addr = buf_res.physaddr; 413 414 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 415 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 416 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 417 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 418 419 /* Setup event table size */ 420 421 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 422 423 DPRINTF("HCS2=0x%08x\n", temp); 424 425 temp = XHCI_HCS2_ERST_MAX(temp); 426 temp = 1U << temp; 427 if (temp > XHCI_MAX_RSEG) 428 temp = XHCI_MAX_RSEG; 429 430 sc->sc_erst_max = temp; 431 432 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 433 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 434 435 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 436 437 /* Setup interrupt rate */ 438 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 439 440 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 441 442 phwr = buf_res.buffer; 443 addr = buf_res.physaddr; 444 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 445 446 /* reset hardware root structure */ 447 memset(phwr, 0, sizeof(*phwr)); 448 449 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 450 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 451 452 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 453 454 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 455 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 456 457 addr = (uint64_t)buf_res.physaddr; 458 459 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 460 461 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 462 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 463 464 /* Setup interrupter registers */ 465 466 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 467 temp |= XHCI_IMAN_INTR_ENA; 468 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 469 470 /* setup command ring control base address */ 471 addr = buf_res.physaddr; 472 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 473 474 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 475 476 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 477 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 478 479 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 480 481 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 482 483 /* Go! */ 484 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 485 XHCI_CMD_INTE | XHCI_CMD_HSEE); 486 487 for (i = 0; i != 100; i++) { 488 usb_pause_mtx(NULL, hz / 100); 489 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 490 if (!temp) 491 break; 492 } 493 if (temp) { 494 XWRITE4(sc, oper, XHCI_USBCMD, 0); 495 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 496 return (USB_ERR_IOERROR); 497 } 498 499 /* catch any lost interrupts */ 500 xhci_do_poll(&sc->sc_bus); 501 502 return (0); 503 } 504 505 usb_error_t 506 xhci_halt_controller(struct xhci_softc *sc) 507 { 508 uint32_t temp; 509 uint16_t i; 510 511 DPRINTF("\n"); 512 513 sc->sc_capa_off = 0; 514 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 515 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 516 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 517 518 /* Halt controller */ 519 XWRITE4(sc, oper, XHCI_USBCMD, 0); 520 521 for (i = 0; i != 100; i++) { 522 usb_pause_mtx(NULL, hz / 100); 523 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 524 if (temp) 525 break; 526 } 527 528 if (!temp) { 529 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 530 return (USB_ERR_IOERROR); 531 } 532 return (0); 533 } 534 535 usb_error_t 536 xhci_init(struct xhci_softc *sc, device_t self) 537 { 538 /* initialise some bus fields */ 539 sc->sc_bus.parent = self; 540 541 /* set the bus revision */ 542 sc->sc_bus.usbrev = USB_REV_3_0; 543 544 /* set up the bus struct */ 545 sc->sc_bus.methods = &xhci_bus_methods; 546 547 /* setup devices array */ 548 sc->sc_bus.devices = sc->sc_devices; 549 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 550 551 /* setup command queue mutex and condition varible */ 552 cv_init(&sc->sc_cmd_cv, "CMDQ"); 553 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 554 555 /* get all DMA memory */ 556 if (usb_bus_mem_alloc_all(&sc->sc_bus, 557 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 558 return (ENOMEM); 559 } 560 561 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 562 sc->sc_config_msg[0].bus = &sc->sc_bus; 563 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 564 sc->sc_config_msg[1].bus = &sc->sc_bus; 565 566 return (0); 567 } 568 569 void 570 xhci_uninit(struct xhci_softc *sc) 571 { 572 /* 573 * NOTE: At this point the control transfer process is gone 574 * and "xhci_configure_msg" is no longer called. Consequently 575 * waiting for the configuration messages to complete is not 576 * needed. 577 */ 578 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 579 580 cv_destroy(&sc->sc_cmd_cv); 581 sx_destroy(&sc->sc_cmd_sx); 582 } 583 584 static void 585 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 586 { 587 struct xhci_softc *sc = XHCI_BUS2SC(bus); 588 589 switch (state) { 590 case USB_HW_POWER_SUSPEND: 591 DPRINTF("Stopping the XHCI\n"); 592 xhci_halt_controller(sc); 593 break; 594 case USB_HW_POWER_SHUTDOWN: 595 DPRINTF("Stopping the XHCI\n"); 596 xhci_halt_controller(sc); 597 break; 598 case USB_HW_POWER_RESUME: 599 DPRINTF("Starting the XHCI\n"); 600 xhci_start_controller(sc); 601 break; 602 default: 603 break; 604 } 605 } 606 607 static usb_error_t 608 xhci_generic_done_sub(struct usb_xfer *xfer) 609 { 610 struct xhci_td *td; 611 struct xhci_td *td_alt_next; 612 uint32_t len; 613 uint8_t status; 614 615 td = xfer->td_transfer_cache; 616 td_alt_next = td->alt_next; 617 618 if (xfer->aframes != xfer->nframes) 619 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 620 621 while (1) { 622 623 usb_pc_cpu_invalidate(td->page_cache); 624 625 status = td->status; 626 len = td->remainder; 627 628 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 629 xfer, (unsigned int)xfer->aframes, 630 (unsigned int)xfer->nframes, 631 (unsigned int)len, (unsigned int)td->len, 632 (unsigned int)status); 633 634 /* 635 * Verify the status length and 636 * add the length to "frlengths[]": 637 */ 638 if (len > td->len) { 639 /* should not happen */ 640 DPRINTF("Invalid status length, " 641 "0x%04x/0x%04x bytes\n", len, td->len); 642 status = XHCI_TRB_ERROR_LENGTH; 643 } else if (xfer->aframes != xfer->nframes) { 644 xfer->frlengths[xfer->aframes] += td->len - len; 645 } 646 /* Check for last transfer */ 647 if (((void *)td) == xfer->td_transfer_last) { 648 td = NULL; 649 break; 650 } 651 /* Check for transfer error */ 652 if (status != XHCI_TRB_ERROR_SHORT_PKT && 653 status != XHCI_TRB_ERROR_SUCCESS) { 654 /* the transfer is finished */ 655 td = NULL; 656 break; 657 } 658 /* Check for short transfer */ 659 if (len > 0) { 660 if (xfer->flags_int.short_frames_ok || 661 xfer->flags_int.isochronous_xfr || 662 xfer->flags_int.control_xfr) { 663 /* follow alt next */ 664 td = td->alt_next; 665 } else { 666 /* the transfer is finished */ 667 td = NULL; 668 } 669 break; 670 } 671 td = td->obj_next; 672 673 if (td->alt_next != td_alt_next) { 674 /* this USB frame is complete */ 675 break; 676 } 677 } 678 679 /* update transfer cache */ 680 681 xfer->td_transfer_cache = td; 682 683 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 684 (status != XHCI_TRB_ERROR_SHORT_PKT && 685 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 686 USB_ERR_NORMAL_COMPLETION); 687 } 688 689 static void 690 xhci_generic_done(struct usb_xfer *xfer) 691 { 692 usb_error_t err = 0; 693 694 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 695 xfer, xfer->endpoint); 696 697 /* reset scanner */ 698 699 xfer->td_transfer_cache = xfer->td_transfer_first; 700 701 if (xfer->flags_int.control_xfr) { 702 703 if (xfer->flags_int.control_hdr) 704 err = xhci_generic_done_sub(xfer); 705 706 xfer->aframes = 1; 707 708 if (xfer->td_transfer_cache == NULL) 709 goto done; 710 } 711 712 while (xfer->aframes != xfer->nframes) { 713 714 err = xhci_generic_done_sub(xfer); 715 xfer->aframes++; 716 717 if (xfer->td_transfer_cache == NULL) 718 goto done; 719 } 720 721 if (xfer->flags_int.control_xfr && 722 !xfer->flags_int.control_act) 723 err = xhci_generic_done_sub(xfer); 724 done: 725 /* transfer is complete */ 726 xhci_device_done(xfer, err); 727 } 728 729 static void 730 xhci_activate_transfer(struct usb_xfer *xfer) 731 { 732 struct xhci_td *td; 733 734 td = xfer->td_transfer_cache; 735 736 usb_pc_cpu_invalidate(td->page_cache); 737 738 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 739 740 /* activate the transfer */ 741 742 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 743 usb_pc_cpu_flush(td->page_cache); 744 745 xhci_endpoint_doorbell(xfer); 746 } 747 } 748 749 static void 750 xhci_skip_transfer(struct usb_xfer *xfer) 751 { 752 struct xhci_td *td; 753 struct xhci_td *td_last; 754 755 td = xfer->td_transfer_cache; 756 td_last = xfer->td_transfer_last; 757 758 td = td->alt_next; 759 760 usb_pc_cpu_invalidate(td->page_cache); 761 762 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 763 764 usb_pc_cpu_invalidate(td_last->page_cache); 765 766 /* copy LINK TRB to current waiting location */ 767 768 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 769 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 770 usb_pc_cpu_flush(td->page_cache); 771 772 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 773 usb_pc_cpu_flush(td->page_cache); 774 775 xhci_endpoint_doorbell(xfer); 776 } 777 } 778 779 /*------------------------------------------------------------------------* 780 * xhci_check_transfer 781 *------------------------------------------------------------------------*/ 782 static void 783 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 784 { 785 struct xhci_endpoint_ext *pepext; 786 int64_t offset; 787 uint64_t td_event; 788 uint32_t temp; 789 uint32_t remainder; 790 uint16_t stream_id; 791 uint16_t i; 792 uint8_t status; 793 uint8_t halted; 794 uint8_t epno; 795 uint8_t index; 796 797 /* decode TRB */ 798 td_event = le64toh(trb->qwTrb0); 799 temp = le32toh(trb->dwTrb2); 800 801 remainder = XHCI_TRB_2_REM_GET(temp); 802 status = XHCI_TRB_2_ERROR_GET(temp); 803 stream_id = XHCI_TRB_2_STREAM_GET(temp); 804 805 temp = le32toh(trb->dwTrb3); 806 epno = XHCI_TRB_3_EP_GET(temp); 807 index = XHCI_TRB_3_SLOT_GET(temp); 808 809 /* check if error means halted */ 810 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 811 status != XHCI_TRB_ERROR_SUCCESS); 812 813 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 814 index, epno, stream_id, remainder, status); 815 816 if (index > sc->sc_noslot) { 817 DPRINTF("Invalid slot.\n"); 818 return; 819 } 820 821 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 822 DPRINTF("Invalid endpoint.\n"); 823 return; 824 } 825 826 pepext = &sc->sc_hw.devs[index].endp[epno]; 827 828 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 829 stream_id = 0; 830 DPRINTF("stream_id=0\n"); 831 } else if (stream_id >= XHCI_MAX_STREAMS) { 832 DPRINTF("Invalid stream ID.\n"); 833 return; 834 } 835 836 /* try to find the USB transfer that generated the event */ 837 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 838 struct usb_xfer *xfer; 839 struct xhci_td *td; 840 841 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 842 if (xfer == NULL) 843 continue; 844 845 td = xfer->td_transfer_cache; 846 847 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 848 (long long)td_event, 849 (long long)td->td_self, 850 (long long)td->td_self + sizeof(td->td_trb)); 851 852 /* 853 * NOTE: Some XHCI implementations might not trigger 854 * an event on the last LINK TRB so we need to 855 * consider both the last and second last event 856 * address as conditions for a successful transfer. 857 * 858 * NOTE: We assume that the XHCI will only trigger one 859 * event per chain of TRBs. 860 */ 861 862 offset = td_event - td->td_self; 863 864 if (offset >= 0 && 865 offset < (int64_t)sizeof(td->td_trb)) { 866 867 usb_pc_cpu_invalidate(td->page_cache); 868 869 /* compute rest of remainder, if any */ 870 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 871 temp = le32toh(td->td_trb[i].dwTrb2); 872 remainder += XHCI_TRB_2_BYTES_GET(temp); 873 } 874 875 DPRINTFN(5, "New remainder: %u\n", remainder); 876 877 /* clear isochronous transfer errors */ 878 if (xfer->flags_int.isochronous_xfr) { 879 if (halted) { 880 halted = 0; 881 status = XHCI_TRB_ERROR_SUCCESS; 882 remainder = td->len; 883 } 884 } 885 886 /* "td->remainder" is verified later */ 887 td->remainder = remainder; 888 td->status = status; 889 890 usb_pc_cpu_flush(td->page_cache); 891 892 /* 893 * 1) Last transfer descriptor makes the 894 * transfer done 895 */ 896 if (((void *)td) == xfer->td_transfer_last) { 897 DPRINTF("TD is last\n"); 898 xhci_generic_done(xfer); 899 break; 900 } 901 902 /* 903 * 2) Any kind of error makes the transfer 904 * done 905 */ 906 if (halted) { 907 DPRINTF("TD has I/O error\n"); 908 xhci_generic_done(xfer); 909 break; 910 } 911 912 /* 913 * 3) If there is no alternate next transfer, 914 * a short packet also makes the transfer done 915 */ 916 if (td->remainder > 0) { 917 if (td->alt_next == NULL) { 918 DPRINTF( 919 "short TD has no alternate next\n"); 920 xhci_generic_done(xfer); 921 break; 922 } 923 DPRINTF("TD has short pkt\n"); 924 if (xfer->flags_int.short_frames_ok || 925 xfer->flags_int.isochronous_xfr || 926 xfer->flags_int.control_xfr) { 927 /* follow the alt next */ 928 xfer->td_transfer_cache = td->alt_next; 929 xhci_activate_transfer(xfer); 930 break; 931 } 932 xhci_skip_transfer(xfer); 933 xhci_generic_done(xfer); 934 break; 935 } 936 937 /* 938 * 4) Transfer complete - go to next TD 939 */ 940 DPRINTF("Following next TD\n"); 941 xfer->td_transfer_cache = td->obj_next; 942 xhci_activate_transfer(xfer); 943 break; /* there should only be one match */ 944 } 945 } 946 } 947 948 static void 949 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 950 { 951 if (sc->sc_cmd_addr == trb->qwTrb0) { 952 DPRINTF("Received command event\n"); 953 sc->sc_cmd_result[0] = trb->dwTrb2; 954 sc->sc_cmd_result[1] = trb->dwTrb3; 955 cv_signal(&sc->sc_cmd_cv); 956 } 957 } 958 959 static void 960 xhci_interrupt_poll(struct xhci_softc *sc) 961 { 962 struct usb_page_search buf_res; 963 struct xhci_hw_root *phwr; 964 uint64_t addr; 965 uint32_t temp; 966 uint16_t i; 967 uint8_t event; 968 uint8_t j; 969 uint8_t k; 970 uint8_t t; 971 972 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 973 974 phwr = buf_res.buffer; 975 976 /* Receive any events */ 977 978 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 979 980 i = sc->sc_event_idx; 981 j = sc->sc_event_ccs; 982 t = 2; 983 984 while (1) { 985 986 temp = le32toh(phwr->hwr_events[i].dwTrb3); 987 988 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 989 990 if (j != k) 991 break; 992 993 event = XHCI_TRB_3_TYPE_GET(temp); 994 995 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 996 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 997 (long)le32toh(phwr->hwr_events[i].dwTrb2), 998 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 999 1000 switch (event) { 1001 case XHCI_TRB_EVENT_TRANSFER: 1002 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1003 break; 1004 case XHCI_TRB_EVENT_CMD_COMPLETE: 1005 xhci_check_command(sc, &phwr->hwr_events[i]); 1006 break; 1007 default: 1008 DPRINTF("Unhandled event = %u\n", event); 1009 break; 1010 } 1011 1012 i++; 1013 1014 if (i == XHCI_MAX_EVENTS) { 1015 i = 0; 1016 j ^= 1; 1017 1018 /* check for timeout */ 1019 if (!--t) 1020 break; 1021 } 1022 } 1023 1024 sc->sc_event_idx = i; 1025 sc->sc_event_ccs = j; 1026 1027 /* 1028 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1029 * latched. That means to activate the register we need to 1030 * write both the low and high double word of the 64-bit 1031 * register. 1032 */ 1033 1034 addr = (uint32_t)buf_res.physaddr; 1035 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1036 1037 /* try to clear busy bit */ 1038 addr |= XHCI_ERDP_LO_BUSY; 1039 1040 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1041 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1042 } 1043 1044 static usb_error_t 1045 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1046 uint16_t timeout_ms) 1047 { 1048 struct usb_page_search buf_res; 1049 struct xhci_hw_root *phwr; 1050 uint64_t addr; 1051 uint32_t temp; 1052 uint8_t i; 1053 uint8_t j; 1054 int err; 1055 1056 XHCI_CMD_ASSERT_LOCKED(sc); 1057 1058 /* get hardware root structure */ 1059 1060 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1061 1062 phwr = buf_res.buffer; 1063 1064 /* Queue command */ 1065 1066 USB_BUS_LOCK(&sc->sc_bus); 1067 1068 i = sc->sc_command_idx; 1069 j = sc->sc_command_ccs; 1070 1071 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1072 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1073 (long long)le64toh(trb->qwTrb0), 1074 (long)le32toh(trb->dwTrb2), 1075 (long)le32toh(trb->dwTrb3)); 1076 1077 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1078 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1079 1080 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1081 1082 temp = trb->dwTrb3; 1083 1084 if (j) 1085 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1086 else 1087 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1088 1089 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1090 1091 phwr->hwr_commands[i].dwTrb3 = temp; 1092 1093 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1094 1095 addr = buf_res.physaddr; 1096 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1097 1098 sc->sc_cmd_addr = htole64(addr); 1099 1100 i++; 1101 1102 if (i == (XHCI_MAX_COMMANDS - 1)) { 1103 1104 if (j) { 1105 temp = htole32(XHCI_TRB_3_TC_BIT | 1106 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1107 XHCI_TRB_3_CYCLE_BIT); 1108 } else { 1109 temp = htole32(XHCI_TRB_3_TC_BIT | 1110 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1111 } 1112 1113 phwr->hwr_commands[i].dwTrb3 = temp; 1114 1115 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1116 1117 i = 0; 1118 j ^= 1; 1119 } 1120 1121 sc->sc_command_idx = i; 1122 sc->sc_command_ccs = j; 1123 1124 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1125 1126 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1127 USB_MS_TO_TICKS(timeout_ms)); 1128 1129 if (err) { 1130 DPRINTFN(0, "Command timeout!\n"); 1131 err = USB_ERR_TIMEOUT; 1132 trb->dwTrb2 = 0; 1133 trb->dwTrb3 = 0; 1134 } else { 1135 temp = le32toh(sc->sc_cmd_result[0]); 1136 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1137 err = USB_ERR_IOERROR; 1138 1139 trb->dwTrb2 = sc->sc_cmd_result[0]; 1140 trb->dwTrb3 = sc->sc_cmd_result[1]; 1141 } 1142 1143 USB_BUS_UNLOCK(&sc->sc_bus); 1144 1145 return (err); 1146 } 1147 1148 #if 0 1149 static usb_error_t 1150 xhci_cmd_nop(struct xhci_softc *sc) 1151 { 1152 struct xhci_trb trb; 1153 uint32_t temp; 1154 1155 DPRINTF("\n"); 1156 1157 trb.qwTrb0 = 0; 1158 trb.dwTrb2 = 0; 1159 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1160 1161 trb.dwTrb3 = htole32(temp); 1162 1163 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1164 } 1165 #endif 1166 1167 static usb_error_t 1168 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1169 { 1170 struct xhci_trb trb; 1171 uint32_t temp; 1172 usb_error_t err; 1173 1174 DPRINTF("\n"); 1175 1176 trb.qwTrb0 = 0; 1177 trb.dwTrb2 = 0; 1178 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1179 1180 err = xhci_do_command(sc, &trb, 100 /* ms */); 1181 if (err) 1182 goto done; 1183 1184 temp = le32toh(trb.dwTrb3); 1185 1186 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1187 1188 done: 1189 return (err); 1190 } 1191 1192 static usb_error_t 1193 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1194 { 1195 struct xhci_trb trb; 1196 uint32_t temp; 1197 1198 DPRINTF("\n"); 1199 1200 trb.qwTrb0 = 0; 1201 trb.dwTrb2 = 0; 1202 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1203 XHCI_TRB_3_SLOT_SET(slot_id); 1204 1205 trb.dwTrb3 = htole32(temp); 1206 1207 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1208 } 1209 1210 static usb_error_t 1211 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1212 uint8_t bsr, uint8_t slot_id) 1213 { 1214 struct xhci_trb trb; 1215 uint32_t temp; 1216 1217 DPRINTF("\n"); 1218 1219 trb.qwTrb0 = htole64(input_ctx); 1220 trb.dwTrb2 = 0; 1221 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1222 XHCI_TRB_3_SLOT_SET(slot_id); 1223 1224 if (bsr) 1225 temp |= XHCI_TRB_3_BSR_BIT; 1226 1227 trb.dwTrb3 = htole32(temp); 1228 1229 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1230 } 1231 1232 static usb_error_t 1233 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1234 { 1235 struct usb_page_search buf_inp; 1236 struct usb_page_search buf_dev; 1237 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1238 struct xhci_hw_dev *hdev; 1239 struct xhci_dev_ctx *pdev; 1240 struct xhci_endpoint_ext *pepext; 1241 uint32_t temp; 1242 uint16_t mps; 1243 usb_error_t err; 1244 uint8_t index; 1245 1246 /* the root HUB case is not handled here */ 1247 if (udev->parent_hub == NULL) 1248 return (USB_ERR_INVAL); 1249 1250 index = udev->controller_slot_id; 1251 1252 hdev = &sc->sc_hw.devs[index]; 1253 1254 if (mtx != NULL) 1255 mtx_unlock(mtx); 1256 1257 XHCI_CMD_LOCK(sc); 1258 1259 switch (hdev->state) { 1260 case XHCI_ST_DEFAULT: 1261 case XHCI_ST_ENABLED: 1262 1263 hdev->state = XHCI_ST_ENABLED; 1264 1265 /* set configure mask to slot and EP0 */ 1266 xhci_configure_mask(udev, 3, 0); 1267 1268 /* configure input slot context structure */ 1269 err = xhci_configure_device(udev); 1270 1271 if (err != 0) { 1272 DPRINTF("Could not configure device\n"); 1273 break; 1274 } 1275 1276 /* configure input endpoint context structure */ 1277 switch (udev->speed) { 1278 case USB_SPEED_LOW: 1279 case USB_SPEED_FULL: 1280 mps = 8; 1281 break; 1282 case USB_SPEED_HIGH: 1283 mps = 64; 1284 break; 1285 default: 1286 mps = 512; 1287 break; 1288 } 1289 1290 pepext = xhci_get_endpoint_ext(udev, 1291 &udev->ctrl_ep_desc); 1292 err = xhci_configure_endpoint(udev, 1293 &udev->ctrl_ep_desc, pepext, 1294 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1295 1296 if (err != 0) { 1297 DPRINTF("Could not configure default endpoint\n"); 1298 break; 1299 } 1300 1301 /* execute set address command */ 1302 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1303 1304 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1305 (address == 0), index); 1306 1307 if (err != 0) { 1308 DPRINTF("Could not set address " 1309 "for slot %u.\n", index); 1310 if (address != 0) 1311 break; 1312 } 1313 1314 /* update device address to new value */ 1315 1316 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1317 pdev = buf_dev.buffer; 1318 usb_pc_cpu_invalidate(&hdev->device_pc); 1319 1320 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1321 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1322 1323 /* update device state to new value */ 1324 1325 if (address != 0) 1326 hdev->state = XHCI_ST_ADDRESSED; 1327 else 1328 hdev->state = XHCI_ST_DEFAULT; 1329 break; 1330 1331 default: 1332 DPRINTF("Wrong state for set address.\n"); 1333 err = USB_ERR_IOERROR; 1334 break; 1335 } 1336 XHCI_CMD_UNLOCK(sc); 1337 1338 if (mtx != NULL) 1339 mtx_lock(mtx); 1340 1341 return (err); 1342 } 1343 1344 static usb_error_t 1345 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1346 uint8_t deconfigure, uint8_t slot_id) 1347 { 1348 struct xhci_trb trb; 1349 uint32_t temp; 1350 1351 DPRINTF("\n"); 1352 1353 trb.qwTrb0 = htole64(input_ctx); 1354 trb.dwTrb2 = 0; 1355 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1356 XHCI_TRB_3_SLOT_SET(slot_id); 1357 1358 if (deconfigure) 1359 temp |= XHCI_TRB_3_DCEP_BIT; 1360 1361 trb.dwTrb3 = htole32(temp); 1362 1363 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1364 } 1365 1366 static usb_error_t 1367 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1368 uint8_t slot_id) 1369 { 1370 struct xhci_trb trb; 1371 uint32_t temp; 1372 1373 DPRINTF("\n"); 1374 1375 trb.qwTrb0 = htole64(input_ctx); 1376 trb.dwTrb2 = 0; 1377 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1378 XHCI_TRB_3_SLOT_SET(slot_id); 1379 trb.dwTrb3 = htole32(temp); 1380 1381 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1382 } 1383 1384 static usb_error_t 1385 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1386 uint8_t ep_id, uint8_t slot_id) 1387 { 1388 struct xhci_trb trb; 1389 uint32_t temp; 1390 1391 DPRINTF("\n"); 1392 1393 trb.qwTrb0 = 0; 1394 trb.dwTrb2 = 0; 1395 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1396 XHCI_TRB_3_SLOT_SET(slot_id) | 1397 XHCI_TRB_3_EP_SET(ep_id); 1398 1399 if (preserve) 1400 temp |= XHCI_TRB_3_PRSV_BIT; 1401 1402 trb.dwTrb3 = htole32(temp); 1403 1404 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1405 } 1406 1407 static usb_error_t 1408 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1409 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1410 { 1411 struct xhci_trb trb; 1412 uint32_t temp; 1413 1414 DPRINTF("\n"); 1415 1416 trb.qwTrb0 = htole64(dequeue_ptr); 1417 1418 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1419 trb.dwTrb2 = htole32(temp); 1420 1421 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1422 XHCI_TRB_3_SLOT_SET(slot_id) | 1423 XHCI_TRB_3_EP_SET(ep_id); 1424 trb.dwTrb3 = htole32(temp); 1425 1426 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1427 } 1428 1429 static usb_error_t 1430 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1431 uint8_t ep_id, uint8_t slot_id) 1432 { 1433 struct xhci_trb trb; 1434 uint32_t temp; 1435 1436 DPRINTF("\n"); 1437 1438 trb.qwTrb0 = 0; 1439 trb.dwTrb2 = 0; 1440 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1441 XHCI_TRB_3_SLOT_SET(slot_id) | 1442 XHCI_TRB_3_EP_SET(ep_id); 1443 1444 if (suspend) 1445 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1446 1447 trb.dwTrb3 = htole32(temp); 1448 1449 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1450 } 1451 1452 static usb_error_t 1453 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1454 { 1455 struct xhci_trb trb; 1456 uint32_t temp; 1457 1458 DPRINTF("\n"); 1459 1460 trb.qwTrb0 = 0; 1461 trb.dwTrb2 = 0; 1462 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1463 XHCI_TRB_3_SLOT_SET(slot_id); 1464 1465 trb.dwTrb3 = htole32(temp); 1466 1467 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1468 } 1469 1470 /*------------------------------------------------------------------------* 1471 * xhci_interrupt - XHCI interrupt handler 1472 *------------------------------------------------------------------------*/ 1473 void 1474 xhci_interrupt(struct xhci_softc *sc) 1475 { 1476 uint32_t status; 1477 uint32_t iman; 1478 1479 USB_BUS_LOCK(&sc->sc_bus); 1480 1481 status = XREAD4(sc, oper, XHCI_USBSTS); 1482 if (status == 0) 1483 goto done; 1484 1485 /* acknowledge interrupts */ 1486 1487 XWRITE4(sc, oper, XHCI_USBSTS, status); 1488 1489 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1490 1491 if (status & XHCI_STS_EINT) { 1492 1493 /* acknowledge pending event */ 1494 iman = XREAD4(sc, runt, XHCI_IMAN(0)); 1495 1496 /* reset interrupt */ 1497 XWRITE4(sc, runt, XHCI_IMAN(0), iman); 1498 1499 DPRINTFN(16, "real interrupt (iman=0x%08x)\n", iman); 1500 1501 /* check for event(s) */ 1502 xhci_interrupt_poll(sc); 1503 } 1504 1505 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1506 XHCI_STS_HSE | XHCI_STS_HCE)) { 1507 1508 if (status & XHCI_STS_PCD) { 1509 xhci_root_intr(sc); 1510 } 1511 1512 if (status & XHCI_STS_HCH) { 1513 printf("%s: host controller halted\n", 1514 __FUNCTION__); 1515 } 1516 1517 if (status & XHCI_STS_HSE) { 1518 printf("%s: host system error\n", 1519 __FUNCTION__); 1520 } 1521 1522 if (status & XHCI_STS_HCE) { 1523 printf("%s: host controller error\n", 1524 __FUNCTION__); 1525 } 1526 } 1527 done: 1528 USB_BUS_UNLOCK(&sc->sc_bus); 1529 } 1530 1531 /*------------------------------------------------------------------------* 1532 * xhci_timeout - XHCI timeout handler 1533 *------------------------------------------------------------------------*/ 1534 static void 1535 xhci_timeout(void *arg) 1536 { 1537 struct usb_xfer *xfer = arg; 1538 1539 DPRINTF("xfer=%p\n", xfer); 1540 1541 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1542 1543 /* transfer is transferred */ 1544 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1545 } 1546 1547 static void 1548 xhci_do_poll(struct usb_bus *bus) 1549 { 1550 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1551 1552 USB_BUS_LOCK(&sc->sc_bus); 1553 xhci_interrupt_poll(sc); 1554 USB_BUS_UNLOCK(&sc->sc_bus); 1555 } 1556 1557 static void 1558 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1559 { 1560 struct usb_page_search buf_res; 1561 struct xhci_td *td; 1562 struct xhci_td *td_next; 1563 struct xhci_td *td_alt_next; 1564 struct xhci_td *td_first; 1565 uint32_t buf_offset; 1566 uint32_t average; 1567 uint32_t len_old; 1568 uint32_t npkt_off; 1569 uint32_t dword; 1570 uint8_t shortpkt_old; 1571 uint8_t precompute; 1572 uint8_t x; 1573 1574 td_alt_next = NULL; 1575 buf_offset = 0; 1576 shortpkt_old = temp->shortpkt; 1577 len_old = temp->len; 1578 npkt_off = 0; 1579 precompute = 1; 1580 1581 restart: 1582 1583 td = temp->td; 1584 td_next = td_first = temp->td_next; 1585 1586 while (1) { 1587 1588 if (temp->len == 0) { 1589 1590 if (temp->shortpkt) 1591 break; 1592 1593 /* send a Zero Length Packet, ZLP, last */ 1594 1595 temp->shortpkt = 1; 1596 average = 0; 1597 1598 } else { 1599 1600 average = temp->average; 1601 1602 if (temp->len < average) { 1603 if (temp->len % temp->max_packet_size) { 1604 temp->shortpkt = 1; 1605 } 1606 average = temp->len; 1607 } 1608 } 1609 1610 if (td_next == NULL) 1611 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1612 1613 /* get next TD */ 1614 1615 td = td_next; 1616 td_next = td->obj_next; 1617 1618 /* check if we are pre-computing */ 1619 1620 if (precompute) { 1621 1622 /* update remaining length */ 1623 1624 temp->len -= average; 1625 1626 continue; 1627 } 1628 /* fill out current TD */ 1629 1630 td->len = average; 1631 td->remainder = 0; 1632 td->status = 0; 1633 1634 /* update remaining length */ 1635 1636 temp->len -= average; 1637 1638 /* reset TRB index */ 1639 1640 x = 0; 1641 1642 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1643 /* immediate data */ 1644 1645 if (average > 8) 1646 average = 8; 1647 1648 td->td_trb[0].qwTrb0 = 0; 1649 1650 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1651 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1652 average); 1653 1654 dword = XHCI_TRB_2_BYTES_SET(8) | 1655 XHCI_TRB_2_TDSZ_SET(0) | 1656 XHCI_TRB_2_IRQ_SET(0); 1657 1658 td->td_trb[0].dwTrb2 = htole32(dword); 1659 1660 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1661 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1662 1663 /* check wLength */ 1664 if (td->td_trb[0].qwTrb0 & 1665 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1666 if (td->td_trb[0].qwTrb0 & htole64(1)) 1667 dword |= XHCI_TRB_3_TRT_IN; 1668 else 1669 dword |= XHCI_TRB_3_TRT_OUT; 1670 } 1671 1672 td->td_trb[0].dwTrb3 = htole32(dword); 1673 #ifdef USB_DEBUG 1674 xhci_dump_trb(&td->td_trb[x]); 1675 #endif 1676 x++; 1677 1678 } else do { 1679 1680 uint32_t npkt; 1681 1682 /* fill out buffer pointers */ 1683 1684 if (average == 0) { 1685 memset(&buf_res, 0, sizeof(buf_res)); 1686 } else { 1687 usbd_get_page(temp->pc, temp->offset + 1688 buf_offset, &buf_res); 1689 1690 /* get length to end of page */ 1691 if (buf_res.length > average) 1692 buf_res.length = average; 1693 1694 /* check for maximum length */ 1695 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1696 buf_res.length = XHCI_TD_PAGE_SIZE; 1697 1698 npkt_off += buf_res.length; 1699 } 1700 1701 /* setup npkt */ 1702 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1703 temp->max_packet_size; 1704 1705 if (npkt == 0) 1706 npkt = 1; 1707 else if (npkt > 31) 1708 npkt = 31; 1709 1710 /* fill out TRB's */ 1711 td->td_trb[x].qwTrb0 = 1712 htole64((uint64_t)buf_res.physaddr); 1713 1714 dword = 1715 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1716 XHCI_TRB_2_TDSZ_SET(npkt) | 1717 XHCI_TRB_2_IRQ_SET(0); 1718 1719 td->td_trb[x].dwTrb2 = htole32(dword); 1720 1721 switch (temp->trb_type) { 1722 case XHCI_TRB_TYPE_ISOCH: 1723 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1724 XHCI_TRB_3_TBC_SET(temp->tbc) | 1725 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1726 if (td != td_first) { 1727 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1728 } else if (temp->do_isoc_sync != 0) { 1729 temp->do_isoc_sync = 0; 1730 /* wait until "isoc_frame" */ 1731 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1732 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1733 } else { 1734 /* start data transfer at next interval */ 1735 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1736 XHCI_TRB_3_ISO_SIA_BIT; 1737 } 1738 if (temp->direction == UE_DIR_IN) 1739 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1740 break; 1741 case XHCI_TRB_TYPE_DATA_STAGE: 1742 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1743 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 1744 XHCI_TRB_3_TBC_SET(temp->tbc) | 1745 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1746 if (temp->direction == UE_DIR_IN) 1747 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1748 break; 1749 case XHCI_TRB_TYPE_STATUS_STAGE: 1750 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1751 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 1752 XHCI_TRB_3_TBC_SET(temp->tbc) | 1753 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1754 if (temp->direction == UE_DIR_IN) 1755 dword |= XHCI_TRB_3_DIR_IN; 1756 break; 1757 default: /* XHCI_TRB_TYPE_NORMAL */ 1758 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1759 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 1760 XHCI_TRB_3_TBC_SET(temp->tbc) | 1761 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1762 if (temp->direction == UE_DIR_IN) 1763 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1764 break; 1765 } 1766 td->td_trb[x].dwTrb3 = htole32(dword); 1767 1768 average -= buf_res.length; 1769 buf_offset += buf_res.length; 1770 #ifdef USB_DEBUG 1771 xhci_dump_trb(&td->td_trb[x]); 1772 #endif 1773 x++; 1774 1775 } while (average != 0); 1776 1777 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1778 1779 /* store number of data TRB's */ 1780 1781 td->ntrb = x; 1782 1783 DPRINTF("NTRB=%u\n", x); 1784 1785 /* fill out link TRB */ 1786 1787 if (td_next != NULL) { 1788 /* link the current TD with the next one */ 1789 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1790 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1791 } else { 1792 /* this field will get updated later */ 1793 DPRINTF("NOLINK\n"); 1794 } 1795 1796 dword = XHCI_TRB_2_IRQ_SET(0); 1797 1798 td->td_trb[x].dwTrb2 = htole32(dword); 1799 1800 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1801 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT; 1802 1803 td->td_trb[x].dwTrb3 = htole32(dword); 1804 1805 td->alt_next = td_alt_next; 1806 #ifdef USB_DEBUG 1807 xhci_dump_trb(&td->td_trb[x]); 1808 #endif 1809 usb_pc_cpu_flush(td->page_cache); 1810 } 1811 1812 if (precompute) { 1813 precompute = 0; 1814 1815 /* setup alt next pointer, if any */ 1816 if (temp->last_frame) { 1817 td_alt_next = NULL; 1818 } else { 1819 /* we use this field internally */ 1820 td_alt_next = td_next; 1821 } 1822 1823 /* restore */ 1824 temp->shortpkt = shortpkt_old; 1825 temp->len = len_old; 1826 goto restart; 1827 } 1828 1829 /* 1830 * Remove cycle bit from the first TRB if we are 1831 * stepping them: 1832 */ 1833 if (temp->step_td != 0) { 1834 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1835 usb_pc_cpu_flush(td_first->page_cache); 1836 } 1837 1838 /* clear TD SIZE to zero, hence this is the last TRB */ 1839 /* remove chain bit because this is the last TRB in the chain */ 1840 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1841 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1842 1843 usb_pc_cpu_flush(td->page_cache); 1844 1845 temp->td = td; 1846 temp->td_next = td_next; 1847 } 1848 1849 static void 1850 xhci_setup_generic_chain(struct usb_xfer *xfer) 1851 { 1852 struct xhci_std_temp temp; 1853 struct xhci_td *td; 1854 uint32_t x; 1855 uint32_t y; 1856 uint8_t mult; 1857 1858 temp.do_isoc_sync = 0; 1859 temp.step_td = 0; 1860 temp.tbc = 0; 1861 temp.tlbpc = 0; 1862 temp.average = xfer->max_hc_frame_size; 1863 temp.max_packet_size = xfer->max_packet_size; 1864 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1865 temp.pc = NULL; 1866 temp.last_frame = 0; 1867 temp.offset = 0; 1868 temp.multishort = xfer->flags_int.isochronous_xfr || 1869 xfer->flags_int.control_xfr || 1870 xfer->flags_int.short_frames_ok; 1871 1872 /* toggle the DMA set we are using */ 1873 xfer->flags_int.curr_dma_set ^= 1; 1874 1875 /* get next DMA set */ 1876 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1877 1878 temp.td = NULL; 1879 temp.td_next = td; 1880 1881 xfer->td_transfer_first = td; 1882 xfer->td_transfer_cache = td; 1883 1884 if (xfer->flags_int.isochronous_xfr) { 1885 uint8_t shift; 1886 1887 /* compute multiplier for ISOCHRONOUS transfers */ 1888 mult = xfer->endpoint->ecomp ? 1889 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 1890 : 0; 1891 /* check for USB 2.0 multiplier */ 1892 if (mult == 0) { 1893 mult = (xfer->endpoint->edesc-> 1894 wMaxPacketSize[1] >> 3) & 3; 1895 } 1896 /* range check */ 1897 if (mult > 2) 1898 mult = 3; 1899 else 1900 mult++; 1901 1902 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 1903 1904 DPRINTF("MFINDEX=0x%08x\n", x); 1905 1906 switch (usbd_get_speed(xfer->xroot->udev)) { 1907 case USB_SPEED_FULL: 1908 shift = 3; 1909 temp.isoc_delta = 8; /* 1ms */ 1910 x += temp.isoc_delta - 1; 1911 x &= ~(temp.isoc_delta - 1); 1912 break; 1913 default: 1914 shift = usbd_xfer_get_fps_shift(xfer); 1915 temp.isoc_delta = 1U << shift; 1916 x += temp.isoc_delta - 1; 1917 x &= ~(temp.isoc_delta - 1); 1918 /* simple frame load balancing */ 1919 x += xfer->endpoint->usb_uframe; 1920 break; 1921 } 1922 1923 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 1924 1925 if ((xfer->endpoint->is_synced == 0) || 1926 (y < (xfer->nframes << shift)) || 1927 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 1928 /* 1929 * If there is data underflow or the pipe 1930 * queue is empty we schedule the transfer a 1931 * few frames ahead of the current frame 1932 * position. Else two isochronous transfers 1933 * might overlap. 1934 */ 1935 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 1936 xfer->endpoint->is_synced = 1; 1937 temp.do_isoc_sync = 1; 1938 1939 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1940 } 1941 1942 /* compute isochronous completion time */ 1943 1944 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 1945 1946 xfer->isoc_time_complete = 1947 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 1948 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 1949 1950 x = 0; 1951 temp.isoc_frame = xfer->endpoint->isoc_next; 1952 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 1953 1954 xfer->endpoint->isoc_next += xfer->nframes << shift; 1955 1956 } else if (xfer->flags_int.control_xfr) { 1957 1958 /* check if we should prepend a setup message */ 1959 1960 if (xfer->flags_int.control_hdr) { 1961 1962 temp.len = xfer->frlengths[0]; 1963 temp.pc = xfer->frbuffers + 0; 1964 temp.shortpkt = temp.len ? 1 : 0; 1965 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 1966 temp.direction = 0; 1967 1968 /* check for last frame */ 1969 if (xfer->nframes == 1) { 1970 /* no STATUS stage yet, SETUP is last */ 1971 if (xfer->flags_int.control_act) 1972 temp.last_frame = 1; 1973 } 1974 1975 xhci_setup_generic_chain_sub(&temp); 1976 } 1977 x = 1; 1978 mult = 1; 1979 temp.isoc_delta = 0; 1980 temp.isoc_frame = 0; 1981 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 1982 } else { 1983 x = 0; 1984 mult = 1; 1985 temp.isoc_delta = 0; 1986 temp.isoc_frame = 0; 1987 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 1988 } 1989 1990 if (x != xfer->nframes) { 1991 /* setup page_cache pointer */ 1992 temp.pc = xfer->frbuffers + x; 1993 /* set endpoint direction */ 1994 temp.direction = UE_GET_DIR(xfer->endpointno); 1995 } 1996 1997 while (x != xfer->nframes) { 1998 1999 /* DATA0 / DATA1 message */ 2000 2001 temp.len = xfer->frlengths[x]; 2002 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2003 x != 0 && temp.multishort == 0); 2004 2005 x++; 2006 2007 if (x == xfer->nframes) { 2008 if (xfer->flags_int.control_xfr) { 2009 /* no STATUS stage yet, DATA is last */ 2010 if (xfer->flags_int.control_act) 2011 temp.last_frame = 1; 2012 } else { 2013 temp.last_frame = 1; 2014 } 2015 } 2016 if (temp.len == 0) { 2017 2018 /* make sure that we send an USB packet */ 2019 2020 temp.shortpkt = 0; 2021 2022 temp.tbc = 0; 2023 temp.tlbpc = mult - 1; 2024 2025 } else if (xfer->flags_int.isochronous_xfr) { 2026 2027 uint8_t tdpc; 2028 2029 /* 2030 * Isochronous transfers don't have short 2031 * packet termination: 2032 */ 2033 2034 temp.shortpkt = 1; 2035 2036 /* isochronous transfers have a transfer limit */ 2037 2038 if (temp.len > xfer->max_frame_size) 2039 temp.len = xfer->max_frame_size; 2040 2041 /* compute TD packet count */ 2042 tdpc = (temp.len + xfer->max_packet_size - 1) / 2043 xfer->max_packet_size; 2044 2045 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2046 temp.tlbpc = (tdpc % mult); 2047 2048 if (temp.tlbpc == 0) 2049 temp.tlbpc = mult - 1; 2050 else 2051 temp.tlbpc--; 2052 } else { 2053 2054 /* regular data transfer */ 2055 2056 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2057 } 2058 2059 xhci_setup_generic_chain_sub(&temp); 2060 2061 if (xfer->flags_int.isochronous_xfr) { 2062 temp.offset += xfer->frlengths[x - 1]; 2063 temp.isoc_frame += temp.isoc_delta; 2064 } else { 2065 /* get next Page Cache pointer */ 2066 temp.pc = xfer->frbuffers + x; 2067 } 2068 } 2069 2070 /* check if we should append a status stage */ 2071 2072 if (xfer->flags_int.control_xfr && 2073 !xfer->flags_int.control_act) { 2074 2075 /* 2076 * Send a DATA1 message and invert the current 2077 * endpoint direction. 2078 */ 2079 temp.step_td = (xfer->nframes != 0); 2080 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2081 temp.len = 0; 2082 temp.pc = NULL; 2083 temp.shortpkt = 0; 2084 temp.last_frame = 1; 2085 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2086 2087 xhci_setup_generic_chain_sub(&temp); 2088 } 2089 2090 td = temp.td; 2091 2092 /* must have at least one frame! */ 2093 2094 xfer->td_transfer_last = td; 2095 2096 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2097 } 2098 2099 static void 2100 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2101 { 2102 struct usb_page_search buf_res; 2103 struct xhci_dev_ctx_addr *pdctxa; 2104 2105 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2106 2107 pdctxa = buf_res.buffer; 2108 2109 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2110 2111 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2112 2113 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2114 } 2115 2116 static usb_error_t 2117 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2118 { 2119 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2120 struct usb_page_search buf_inp; 2121 struct xhci_input_dev_ctx *pinp; 2122 uint32_t temp; 2123 uint8_t index; 2124 uint8_t x; 2125 2126 index = udev->controller_slot_id; 2127 2128 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2129 2130 pinp = buf_inp.buffer; 2131 2132 if (drop) { 2133 mask &= XHCI_INCTX_NON_CTRL_MASK; 2134 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2135 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2136 } else { 2137 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2138 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2139 2140 /* find most significant set bit */ 2141 for (x = 31; x != 1; x--) { 2142 if (mask & (1 << x)) 2143 break; 2144 } 2145 2146 /* adjust */ 2147 x--; 2148 2149 /* figure out maximum */ 2150 if (x > sc->sc_hw.devs[index].context_num) { 2151 sc->sc_hw.devs[index].context_num = x; 2152 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2153 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2154 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2155 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2156 } 2157 } 2158 return (0); 2159 } 2160 2161 static usb_error_t 2162 xhci_configure_endpoint(struct usb_device *udev, 2163 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2164 uint16_t interval, uint8_t max_packet_count, 2165 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2166 uint16_t max_frame_size, uint8_t ep_mode) 2167 { 2168 struct usb_page_search buf_inp; 2169 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2170 struct xhci_input_dev_ctx *pinp; 2171 uint64_t ring_addr = pepext->physaddr; 2172 uint32_t temp; 2173 uint8_t index; 2174 uint8_t epno; 2175 uint8_t type; 2176 2177 index = udev->controller_slot_id; 2178 2179 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2180 2181 pinp = buf_inp.buffer; 2182 2183 epno = edesc->bEndpointAddress; 2184 type = edesc->bmAttributes & UE_XFERTYPE; 2185 2186 if (type == UE_CONTROL) 2187 epno |= UE_DIR_IN; 2188 2189 epno = XHCI_EPNO2EPID(epno); 2190 2191 if (epno == 0) 2192 return (USB_ERR_NO_PIPE); /* invalid */ 2193 2194 if (max_packet_count == 0) 2195 return (USB_ERR_BAD_BUFSIZE); 2196 2197 max_packet_count--; 2198 2199 if (mult == 0) 2200 return (USB_ERR_BAD_BUFSIZE); 2201 2202 /* store endpoint mode */ 2203 pepext->trb_ep_mode = ep_mode; 2204 usb_pc_cpu_flush(pepext->page_cache); 2205 2206 if (ep_mode == USB_EP_MODE_STREAMS) { 2207 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2208 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2209 XHCI_EPCTX_0_LSA_SET(1); 2210 2211 ring_addr += sizeof(struct xhci_trb) * 2212 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2213 } else { 2214 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2215 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2216 XHCI_EPCTX_0_LSA_SET(0); 2217 2218 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2219 } 2220 2221 switch (udev->speed) { 2222 case USB_SPEED_FULL: 2223 case USB_SPEED_LOW: 2224 /* 1ms -> 125us */ 2225 fps_shift += 3; 2226 break; 2227 default: 2228 break; 2229 } 2230 2231 switch (type) { 2232 case UE_INTERRUPT: 2233 if (fps_shift > 3) 2234 fps_shift--; 2235 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2236 break; 2237 case UE_ISOCHRONOUS: 2238 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2239 2240 switch (udev->speed) { 2241 case USB_SPEED_SUPER: 2242 if (mult > 3) 2243 mult = 3; 2244 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2245 max_packet_count /= mult; 2246 break; 2247 default: 2248 break; 2249 } 2250 break; 2251 default: 2252 break; 2253 } 2254 2255 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2256 2257 temp = 2258 XHCI_EPCTX_1_HID_SET(0) | 2259 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2260 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2261 2262 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2263 if (type != UE_ISOCHRONOUS) 2264 temp |= XHCI_EPCTX_1_CERR_SET(3); 2265 } 2266 2267 switch (type) { 2268 case UE_CONTROL: 2269 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2270 break; 2271 case UE_ISOCHRONOUS: 2272 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2273 break; 2274 case UE_BULK: 2275 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2276 break; 2277 default: 2278 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2279 break; 2280 } 2281 2282 /* check for IN direction */ 2283 if (epno & 1) 2284 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2285 2286 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2287 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2288 2289 switch (edesc->bmAttributes & UE_XFERTYPE) { 2290 case UE_INTERRUPT: 2291 case UE_ISOCHRONOUS: 2292 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2293 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2294 max_frame_size)); 2295 break; 2296 case UE_CONTROL: 2297 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2298 break; 2299 default: 2300 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2301 break; 2302 } 2303 2304 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2305 2306 #ifdef USB_DEBUG 2307 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2308 #endif 2309 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2310 2311 return (0); /* success */ 2312 } 2313 2314 static usb_error_t 2315 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2316 { 2317 struct xhci_endpoint_ext *pepext; 2318 struct usb_endpoint_ss_comp_descriptor *ecomp; 2319 usb_stream_t x; 2320 2321 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2322 xfer->endpoint->edesc); 2323 2324 ecomp = xfer->endpoint->ecomp; 2325 2326 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2327 uint64_t temp; 2328 2329 /* halt any transfers */ 2330 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2331 2332 /* compute start of TRB ring for stream "x" */ 2333 temp = pepext->physaddr + 2334 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2335 XHCI_SCTX_0_SCT_SEC_TR_RING; 2336 2337 /* make tree structure */ 2338 pepext->trb[(XHCI_MAX_TRANSFERS * 2339 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2340 2341 /* reserved fields */ 2342 pepext->trb[(XHCI_MAX_TRANSFERS * 2343 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2344 pepext->trb[(XHCI_MAX_TRANSFERS * 2345 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2346 } 2347 usb_pc_cpu_flush(pepext->page_cache); 2348 2349 return (xhci_configure_endpoint(xfer->xroot->udev, 2350 xfer->endpoint->edesc, pepext, 2351 xfer->interval, xfer->max_packet_count, 2352 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2353 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2354 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2355 } 2356 2357 static usb_error_t 2358 xhci_configure_device(struct usb_device *udev) 2359 { 2360 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2361 struct usb_page_search buf_inp; 2362 struct usb_page_cache *pcinp; 2363 struct xhci_input_dev_ctx *pinp; 2364 struct usb_device *hubdev; 2365 uint32_t temp; 2366 uint32_t route; 2367 uint32_t rh_port; 2368 uint8_t is_hub; 2369 uint8_t index; 2370 uint8_t depth; 2371 2372 index = udev->controller_slot_id; 2373 2374 DPRINTF("index=%u\n", index); 2375 2376 pcinp = &sc->sc_hw.devs[index].input_pc; 2377 2378 usbd_get_page(pcinp, 0, &buf_inp); 2379 2380 pinp = buf_inp.buffer; 2381 2382 rh_port = 0; 2383 route = 0; 2384 2385 /* figure out route string and root HUB port number */ 2386 2387 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2388 2389 if (hubdev->parent_hub == NULL) 2390 break; 2391 2392 depth = hubdev->parent_hub->depth; 2393 2394 /* 2395 * NOTE: HS/FS/LS devices and the SS root HUB can have 2396 * more than 15 ports 2397 */ 2398 2399 rh_port = hubdev->port_no; 2400 2401 if (depth == 0) 2402 break; 2403 2404 if (rh_port > 15) 2405 rh_port = 15; 2406 2407 if (depth < 6) 2408 route |= rh_port << (4 * (depth - 1)); 2409 } 2410 2411 DPRINTF("Route=0x%08x\n", route); 2412 2413 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2414 XHCI_SCTX_0_CTX_NUM_SET( 2415 sc->sc_hw.devs[index].context_num + 1); 2416 2417 switch (udev->speed) { 2418 case USB_SPEED_LOW: 2419 temp |= XHCI_SCTX_0_SPEED_SET(2); 2420 if (udev->parent_hs_hub != NULL && 2421 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2422 UDPROTO_HSHUBMTT) { 2423 DPRINTF("Device inherits MTT\n"); 2424 temp |= XHCI_SCTX_0_MTT_SET(1); 2425 } 2426 break; 2427 case USB_SPEED_HIGH: 2428 temp |= XHCI_SCTX_0_SPEED_SET(3); 2429 if (sc->sc_hw.devs[index].nports != 0 && 2430 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2431 DPRINTF("HUB supports MTT\n"); 2432 temp |= XHCI_SCTX_0_MTT_SET(1); 2433 } 2434 break; 2435 case USB_SPEED_FULL: 2436 temp |= XHCI_SCTX_0_SPEED_SET(1); 2437 if (udev->parent_hs_hub != NULL && 2438 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2439 UDPROTO_HSHUBMTT) { 2440 DPRINTF("Device inherits MTT\n"); 2441 temp |= XHCI_SCTX_0_MTT_SET(1); 2442 } 2443 break; 2444 default: 2445 temp |= XHCI_SCTX_0_SPEED_SET(4); 2446 break; 2447 } 2448 2449 is_hub = sc->sc_hw.devs[index].nports != 0 && 2450 (udev->speed == USB_SPEED_SUPER || 2451 udev->speed == USB_SPEED_HIGH); 2452 2453 if (is_hub) 2454 temp |= XHCI_SCTX_0_HUB_SET(1); 2455 2456 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2457 2458 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2459 2460 if (is_hub) { 2461 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2462 sc->sc_hw.devs[index].nports); 2463 } 2464 2465 switch (udev->speed) { 2466 case USB_SPEED_SUPER: 2467 switch (sc->sc_hw.devs[index].state) { 2468 case XHCI_ST_ADDRESSED: 2469 case XHCI_ST_CONFIGURED: 2470 /* enable power save */ 2471 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2472 break; 2473 default: 2474 /* disable power save */ 2475 break; 2476 } 2477 break; 2478 default: 2479 break; 2480 } 2481 2482 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2483 2484 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2485 2486 if (is_hub) { 2487 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2488 sc->sc_hw.devs[index].tt); 2489 } 2490 2491 hubdev = udev->parent_hs_hub; 2492 2493 /* check if we should activate the transaction translator */ 2494 switch (udev->speed) { 2495 case USB_SPEED_FULL: 2496 case USB_SPEED_LOW: 2497 if (hubdev != NULL) { 2498 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2499 hubdev->controller_slot_id); 2500 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2501 udev->hs_port_no); 2502 } 2503 break; 2504 default: 2505 break; 2506 } 2507 2508 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2509 2510 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) | 2511 XHCI_SCTX_3_SLOT_STATE_SET(0); 2512 2513 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2514 2515 #ifdef USB_DEBUG 2516 xhci_dump_device(sc, &pinp->ctx_slot); 2517 #endif 2518 usb_pc_cpu_flush(pcinp); 2519 2520 return (0); /* success */ 2521 } 2522 2523 static usb_error_t 2524 xhci_alloc_device_ext(struct usb_device *udev) 2525 { 2526 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2527 struct usb_page_search buf_dev; 2528 struct usb_page_search buf_ep; 2529 struct xhci_trb *trb; 2530 struct usb_page_cache *pc; 2531 struct usb_page *pg; 2532 uint64_t addr; 2533 uint8_t index; 2534 uint8_t i; 2535 2536 index = udev->controller_slot_id; 2537 2538 pc = &sc->sc_hw.devs[index].device_pc; 2539 pg = &sc->sc_hw.devs[index].device_pg; 2540 2541 /* need to initialize the page cache */ 2542 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2543 2544 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2545 (2 * sizeof(struct xhci_dev_ctx)) : 2546 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2547 goto error; 2548 2549 usbd_get_page(pc, 0, &buf_dev); 2550 2551 pc = &sc->sc_hw.devs[index].input_pc; 2552 pg = &sc->sc_hw.devs[index].input_pg; 2553 2554 /* need to initialize the page cache */ 2555 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2556 2557 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2558 (2 * sizeof(struct xhci_input_dev_ctx)) : 2559 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2560 goto error; 2561 } 2562 2563 pc = &sc->sc_hw.devs[index].endpoint_pc; 2564 pg = &sc->sc_hw.devs[index].endpoint_pg; 2565 2566 /* need to initialize the page cache */ 2567 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2568 2569 if (usb_pc_alloc_mem(pc, pg, 2570 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) { 2571 goto error; 2572 } 2573 2574 /* initialise all endpoint LINK TRBs */ 2575 2576 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2577 2578 /* lookup endpoint TRB ring */ 2579 usbd_get_page(pc, (uintptr_t)& 2580 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2581 2582 /* get TRB pointer */ 2583 trb = buf_ep.buffer; 2584 trb += XHCI_MAX_TRANSFERS - 1; 2585 2586 /* get TRB start address */ 2587 addr = buf_ep.physaddr; 2588 2589 /* create LINK TRB */ 2590 trb->qwTrb0 = htole64(addr); 2591 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2592 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2593 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2594 } 2595 2596 usb_pc_cpu_flush(pc); 2597 2598 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2599 2600 return (0); 2601 2602 error: 2603 xhci_free_device_ext(udev); 2604 2605 return (USB_ERR_NOMEM); 2606 } 2607 2608 static void 2609 xhci_free_device_ext(struct usb_device *udev) 2610 { 2611 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2612 uint8_t index; 2613 2614 index = udev->controller_slot_id; 2615 xhci_set_slot_pointer(sc, index, 0); 2616 2617 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2618 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2619 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2620 } 2621 2622 static struct xhci_endpoint_ext * 2623 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2624 { 2625 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2626 struct xhci_endpoint_ext *pepext; 2627 struct usb_page_cache *pc; 2628 struct usb_page_search buf_ep; 2629 uint8_t epno; 2630 uint8_t index; 2631 2632 epno = edesc->bEndpointAddress; 2633 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2634 epno |= UE_DIR_IN; 2635 2636 epno = XHCI_EPNO2EPID(epno); 2637 2638 index = udev->controller_slot_id; 2639 2640 pc = &sc->sc_hw.devs[index].endpoint_pc; 2641 2642 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2643 trb[epno][0], &buf_ep); 2644 2645 pepext = &sc->sc_hw.devs[index].endp[epno]; 2646 pepext->page_cache = pc; 2647 pepext->trb = buf_ep.buffer; 2648 pepext->physaddr = buf_ep.physaddr; 2649 2650 return (pepext); 2651 } 2652 2653 static void 2654 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2655 { 2656 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2657 uint8_t epno; 2658 uint8_t index; 2659 2660 epno = xfer->endpointno; 2661 if (xfer->flags_int.control_xfr) 2662 epno |= UE_DIR_IN; 2663 2664 epno = XHCI_EPNO2EPID(epno); 2665 index = xfer->xroot->udev->controller_slot_id; 2666 2667 if (xfer->xroot->udev->flags.self_suspended == 0) { 2668 XWRITE4(sc, door, XHCI_DOORBELL(index), 2669 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2670 } 2671 } 2672 2673 static void 2674 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2675 { 2676 struct xhci_endpoint_ext *pepext; 2677 2678 if (xfer->flags_int.bandwidth_reclaimed) { 2679 xfer->flags_int.bandwidth_reclaimed = 0; 2680 2681 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2682 xfer->endpoint->edesc); 2683 2684 pepext->trb_used[xfer->stream_id]--; 2685 2686 pepext->xfer[xfer->qh_pos] = NULL; 2687 2688 if (error && pepext->trb_running != 0) { 2689 pepext->trb_halted = 1; 2690 pepext->trb_running = 0; 2691 } 2692 } 2693 } 2694 2695 static usb_error_t 2696 xhci_transfer_insert(struct usb_xfer *xfer) 2697 { 2698 struct xhci_td *td_first; 2699 struct xhci_td *td_last; 2700 struct xhci_trb *trb_link; 2701 struct xhci_endpoint_ext *pepext; 2702 uint64_t addr; 2703 usb_stream_t id; 2704 uint8_t i; 2705 uint8_t inext; 2706 uint8_t trb_limit; 2707 2708 DPRINTFN(8, "\n"); 2709 2710 id = xfer->stream_id; 2711 2712 /* check if already inserted */ 2713 if (xfer->flags_int.bandwidth_reclaimed) { 2714 DPRINTFN(8, "Already in schedule\n"); 2715 return (0); 2716 } 2717 2718 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2719 xfer->endpoint->edesc); 2720 2721 td_first = xfer->td_transfer_first; 2722 td_last = xfer->td_transfer_last; 2723 addr = pepext->physaddr; 2724 2725 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2726 case UE_CONTROL: 2727 case UE_INTERRUPT: 2728 /* single buffered */ 2729 trb_limit = 1; 2730 break; 2731 default: 2732 /* multi buffered */ 2733 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2734 break; 2735 } 2736 2737 if (pepext->trb_used[id] >= trb_limit) { 2738 DPRINTFN(8, "Too many TDs queued.\n"); 2739 return (USB_ERR_NOMEM); 2740 } 2741 2742 /* check for stopped condition, after putting transfer on interrupt queue */ 2743 if (pepext->trb_running == 0) { 2744 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2745 2746 DPRINTFN(8, "Not running\n"); 2747 2748 /* start configuration */ 2749 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2750 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2751 return (0); 2752 } 2753 2754 pepext->trb_used[id]++; 2755 2756 /* get current TRB index */ 2757 i = pepext->trb_index[id]; 2758 2759 /* get next TRB index */ 2760 inext = (i + 1); 2761 2762 /* the last entry of the ring is a hardcoded link TRB */ 2763 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2764 inext = 0; 2765 2766 /* store next TRB index, before stream ID offset is added */ 2767 pepext->trb_index[id] = inext; 2768 2769 /* offset for stream */ 2770 i += id * XHCI_MAX_TRANSFERS; 2771 inext += id * XHCI_MAX_TRANSFERS; 2772 2773 /* compute terminating return address */ 2774 addr += (inext * sizeof(struct xhci_trb)); 2775 2776 /* compute link TRB pointer */ 2777 trb_link = td_last->td_trb + td_last->ntrb; 2778 2779 /* update next pointer of last link TRB */ 2780 trb_link->qwTrb0 = htole64(addr); 2781 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2782 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2783 XHCI_TRB_3_CYCLE_BIT | 2784 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2785 2786 #ifdef USB_DEBUG 2787 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2788 #endif 2789 usb_pc_cpu_flush(td_last->page_cache); 2790 2791 /* write ahead chain end marker */ 2792 2793 pepext->trb[inext].qwTrb0 = 0; 2794 pepext->trb[inext].dwTrb2 = 0; 2795 pepext->trb[inext].dwTrb3 = 0; 2796 2797 /* update next pointer of link TRB */ 2798 2799 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2800 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2801 2802 #ifdef USB_DEBUG 2803 xhci_dump_trb(&pepext->trb[i]); 2804 #endif 2805 usb_pc_cpu_flush(pepext->page_cache); 2806 2807 /* toggle cycle bit which activates the transfer chain */ 2808 2809 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2810 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2811 2812 usb_pc_cpu_flush(pepext->page_cache); 2813 2814 DPRINTF("qh_pos = %u\n", i); 2815 2816 pepext->xfer[i] = xfer; 2817 2818 xfer->qh_pos = i; 2819 2820 xfer->flags_int.bandwidth_reclaimed = 1; 2821 2822 xhci_endpoint_doorbell(xfer); 2823 2824 return (0); 2825 } 2826 2827 static void 2828 xhci_root_intr(struct xhci_softc *sc) 2829 { 2830 uint16_t i; 2831 2832 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2833 2834 /* clear any old interrupt data */ 2835 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2836 2837 for (i = 1; i <= sc->sc_noport; i++) { 2838 /* pick out CHANGE bits from the status register */ 2839 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2840 XHCI_PS_CSC | XHCI_PS_PEC | 2841 XHCI_PS_OCC | XHCI_PS_WRC | 2842 XHCI_PS_PRC | XHCI_PS_PLC | 2843 XHCI_PS_CEC)) { 2844 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2845 DPRINTF("port %d changed\n", i); 2846 } 2847 } 2848 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2849 sizeof(sc->sc_hub_idata)); 2850 } 2851 2852 /*------------------------------------------------------------------------* 2853 * xhci_device_done - XHCI done handler 2854 * 2855 * NOTE: This function can be called two times in a row on 2856 * the same USB transfer. From close and from interrupt. 2857 *------------------------------------------------------------------------*/ 2858 static void 2859 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2860 { 2861 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2862 xfer, xfer->endpoint, error); 2863 2864 /* remove transfer from HW queue */ 2865 xhci_transfer_remove(xfer, error); 2866 2867 /* dequeue transfer and start next transfer */ 2868 usbd_transfer_done(xfer, error); 2869 } 2870 2871 /*------------------------------------------------------------------------* 2872 * XHCI data transfer support (generic type) 2873 *------------------------------------------------------------------------*/ 2874 static void 2875 xhci_device_generic_open(struct usb_xfer *xfer) 2876 { 2877 if (xfer->flags_int.isochronous_xfr) { 2878 switch (xfer->xroot->udev->speed) { 2879 case USB_SPEED_FULL: 2880 break; 2881 default: 2882 usb_hs_bandwidth_alloc(xfer); 2883 break; 2884 } 2885 } 2886 } 2887 2888 static void 2889 xhci_device_generic_close(struct usb_xfer *xfer) 2890 { 2891 DPRINTF("\n"); 2892 2893 xhci_device_done(xfer, USB_ERR_CANCELLED); 2894 2895 if (xfer->flags_int.isochronous_xfr) { 2896 switch (xfer->xroot->udev->speed) { 2897 case USB_SPEED_FULL: 2898 break; 2899 default: 2900 usb_hs_bandwidth_free(xfer); 2901 break; 2902 } 2903 } 2904 } 2905 2906 static void 2907 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 2908 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 2909 { 2910 struct usb_xfer *xfer; 2911 2912 /* check if there is a current transfer */ 2913 xfer = ep->endpoint_q[stream_id].curr; 2914 if (xfer == NULL) 2915 return; 2916 2917 /* 2918 * Check if the current transfer is started and then pickup 2919 * the next one, if any. Else wait for next start event due to 2920 * block on failure feature. 2921 */ 2922 if (!xfer->flags_int.bandwidth_reclaimed) 2923 return; 2924 2925 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 2926 if (xfer == NULL) { 2927 /* 2928 * In case of enter we have to consider that the 2929 * transfer is queued by the USB core after the enter 2930 * method is called. 2931 */ 2932 xfer = enter_xfer; 2933 2934 if (xfer == NULL) 2935 return; 2936 } 2937 2938 /* try to multi buffer */ 2939 xhci_transfer_insert(xfer); 2940 } 2941 2942 static void 2943 xhci_device_generic_enter(struct usb_xfer *xfer) 2944 { 2945 DPRINTF("\n"); 2946 2947 /* setup TD's and QH */ 2948 xhci_setup_generic_chain(xfer); 2949 2950 xhci_device_generic_multi_enter(xfer->endpoint, 2951 xfer->stream_id, xfer); 2952 } 2953 2954 static void 2955 xhci_device_generic_start(struct usb_xfer *xfer) 2956 { 2957 DPRINTF("\n"); 2958 2959 /* try to insert xfer on HW queue */ 2960 xhci_transfer_insert(xfer); 2961 2962 /* try to multi buffer */ 2963 xhci_device_generic_multi_enter(xfer->endpoint, 2964 xfer->stream_id, NULL); 2965 2966 /* add transfer last on interrupt queue */ 2967 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2968 2969 /* start timeout, if any */ 2970 if (xfer->timeout != 0) 2971 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 2972 } 2973 2974 struct usb_pipe_methods xhci_device_generic_methods = 2975 { 2976 .open = xhci_device_generic_open, 2977 .close = xhci_device_generic_close, 2978 .enter = xhci_device_generic_enter, 2979 .start = xhci_device_generic_start, 2980 }; 2981 2982 /*------------------------------------------------------------------------* 2983 * xhci root HUB support 2984 *------------------------------------------------------------------------* 2985 * Simulate a hardware HUB by handling all the necessary requests. 2986 *------------------------------------------------------------------------*/ 2987 2988 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 2989 2990 static const 2991 struct usb_device_descriptor xhci_devd = 2992 { 2993 .bLength = sizeof(xhci_devd), 2994 .bDescriptorType = UDESC_DEVICE, /* type */ 2995 HSETW(.bcdUSB, 0x0300), /* USB version */ 2996 .bDeviceClass = UDCLASS_HUB, /* class */ 2997 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 2998 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 2999 .bMaxPacketSize = 9, /* max packet size */ 3000 HSETW(.idVendor, 0x0000), /* vendor */ 3001 HSETW(.idProduct, 0x0000), /* product */ 3002 HSETW(.bcdDevice, 0x0100), /* device version */ 3003 .iManufacturer = 1, 3004 .iProduct = 2, 3005 .iSerialNumber = 0, 3006 .bNumConfigurations = 1, /* # of configurations */ 3007 }; 3008 3009 static const 3010 struct xhci_bos_desc xhci_bosd = { 3011 .bosd = { 3012 .bLength = sizeof(xhci_bosd.bosd), 3013 .bDescriptorType = UDESC_BOS, 3014 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3015 .bNumDeviceCaps = 3, 3016 }, 3017 .usb2extd = { 3018 .bLength = sizeof(xhci_bosd.usb2extd), 3019 .bDescriptorType = 1, 3020 .bDevCapabilityType = 2, 3021 .bmAttributes[0] = 2, 3022 }, 3023 .usbdcd = { 3024 .bLength = sizeof(xhci_bosd.usbdcd), 3025 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3026 .bDevCapabilityType = 3, 3027 .bmAttributes = 0, /* XXX */ 3028 HSETW(.wSpeedsSupported, 0x000C), 3029 .bFunctionalitySupport = 8, 3030 .bU1DevExitLat = 255, /* dummy - not used */ 3031 .wU2DevExitLat = { 0x00, 0x08 }, 3032 }, 3033 .cidd = { 3034 .bLength = sizeof(xhci_bosd.cidd), 3035 .bDescriptorType = 1, 3036 .bDevCapabilityType = 4, 3037 .bReserved = 0, 3038 .bContainerID = 0, /* XXX */ 3039 }, 3040 }; 3041 3042 static const 3043 struct xhci_config_desc xhci_confd = { 3044 .confd = { 3045 .bLength = sizeof(xhci_confd.confd), 3046 .bDescriptorType = UDESC_CONFIG, 3047 .wTotalLength[0] = sizeof(xhci_confd), 3048 .bNumInterface = 1, 3049 .bConfigurationValue = 1, 3050 .iConfiguration = 0, 3051 .bmAttributes = UC_SELF_POWERED, 3052 .bMaxPower = 0 /* max power */ 3053 }, 3054 .ifcd = { 3055 .bLength = sizeof(xhci_confd.ifcd), 3056 .bDescriptorType = UDESC_INTERFACE, 3057 .bNumEndpoints = 1, 3058 .bInterfaceClass = UICLASS_HUB, 3059 .bInterfaceSubClass = UISUBCLASS_HUB, 3060 .bInterfaceProtocol = 0, 3061 }, 3062 .endpd = { 3063 .bLength = sizeof(xhci_confd.endpd), 3064 .bDescriptorType = UDESC_ENDPOINT, 3065 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3066 .bmAttributes = UE_INTERRUPT, 3067 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3068 .bInterval = 255, 3069 }, 3070 .endpcd = { 3071 .bLength = sizeof(xhci_confd.endpcd), 3072 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3073 .bMaxBurst = 0, 3074 .bmAttributes = 0, 3075 }, 3076 }; 3077 3078 static const 3079 struct usb_hub_ss_descriptor xhci_hubd = { 3080 .bLength = sizeof(xhci_hubd), 3081 .bDescriptorType = UDESC_SS_HUB, 3082 }; 3083 3084 static usb_error_t 3085 xhci_roothub_exec(struct usb_device *udev, 3086 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3087 { 3088 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3089 const char *str_ptr; 3090 const void *ptr; 3091 uint32_t port; 3092 uint32_t v; 3093 uint16_t len; 3094 uint16_t i; 3095 uint16_t value; 3096 uint16_t index; 3097 uint8_t j; 3098 usb_error_t err; 3099 3100 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3101 3102 /* buffer reset */ 3103 ptr = (const void *)&sc->sc_hub_desc; 3104 len = 0; 3105 err = 0; 3106 3107 value = UGETW(req->wValue); 3108 index = UGETW(req->wIndex); 3109 3110 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3111 "wValue=0x%04x wIndex=0x%04x\n", 3112 req->bmRequestType, req->bRequest, 3113 UGETW(req->wLength), value, index); 3114 3115 #define C(x,y) ((x) | ((y) << 8)) 3116 switch (C(req->bRequest, req->bmRequestType)) { 3117 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3118 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3119 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3120 /* 3121 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3122 * for the integrated root hub. 3123 */ 3124 break; 3125 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3126 len = 1; 3127 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3128 break; 3129 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3130 switch (value >> 8) { 3131 case UDESC_DEVICE: 3132 if ((value & 0xff) != 0) { 3133 err = USB_ERR_IOERROR; 3134 goto done; 3135 } 3136 len = sizeof(xhci_devd); 3137 ptr = (const void *)&xhci_devd; 3138 break; 3139 3140 case UDESC_BOS: 3141 if ((value & 0xff) != 0) { 3142 err = USB_ERR_IOERROR; 3143 goto done; 3144 } 3145 len = sizeof(xhci_bosd); 3146 ptr = (const void *)&xhci_bosd; 3147 break; 3148 3149 case UDESC_CONFIG: 3150 if ((value & 0xff) != 0) { 3151 err = USB_ERR_IOERROR; 3152 goto done; 3153 } 3154 len = sizeof(xhci_confd); 3155 ptr = (const void *)&xhci_confd; 3156 break; 3157 3158 case UDESC_STRING: 3159 switch (value & 0xff) { 3160 case 0: /* Language table */ 3161 str_ptr = "\001"; 3162 break; 3163 3164 case 1: /* Vendor */ 3165 str_ptr = sc->sc_vendor; 3166 break; 3167 3168 case 2: /* Product */ 3169 str_ptr = "XHCI root HUB"; 3170 break; 3171 3172 default: 3173 str_ptr = ""; 3174 break; 3175 } 3176 3177 len = usb_make_str_desc( 3178 sc->sc_hub_desc.temp, 3179 sizeof(sc->sc_hub_desc.temp), 3180 str_ptr); 3181 break; 3182 3183 default: 3184 err = USB_ERR_IOERROR; 3185 goto done; 3186 } 3187 break; 3188 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3189 len = 1; 3190 sc->sc_hub_desc.temp[0] = 0; 3191 break; 3192 case C(UR_GET_STATUS, UT_READ_DEVICE): 3193 len = 2; 3194 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3195 break; 3196 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3197 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3198 len = 2; 3199 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3200 break; 3201 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3202 if (value >= XHCI_MAX_DEVICES) { 3203 err = USB_ERR_IOERROR; 3204 goto done; 3205 } 3206 break; 3207 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3208 if (value != 0 && value != 1) { 3209 err = USB_ERR_IOERROR; 3210 goto done; 3211 } 3212 sc->sc_conf = value; 3213 break; 3214 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3215 break; 3216 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3217 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3218 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3219 err = USB_ERR_IOERROR; 3220 goto done; 3221 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3222 break; 3223 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3224 break; 3225 /* Hub requests */ 3226 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3227 break; 3228 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3229 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3230 3231 if ((index < 1) || 3232 (index > sc->sc_noport)) { 3233 err = USB_ERR_IOERROR; 3234 goto done; 3235 } 3236 port = XHCI_PORTSC(index); 3237 3238 v = XREAD4(sc, oper, port); 3239 i = XHCI_PS_PLS_GET(v); 3240 v &= ~XHCI_PS_CLEAR; 3241 3242 switch (value) { 3243 case UHF_C_BH_PORT_RESET: 3244 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3245 break; 3246 case UHF_C_PORT_CONFIG_ERROR: 3247 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3248 break; 3249 case UHF_C_PORT_SUSPEND: 3250 case UHF_C_PORT_LINK_STATE: 3251 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3252 break; 3253 case UHF_C_PORT_CONNECTION: 3254 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3255 break; 3256 case UHF_C_PORT_ENABLE: 3257 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3258 break; 3259 case UHF_C_PORT_OVER_CURRENT: 3260 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3261 break; 3262 case UHF_C_PORT_RESET: 3263 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3264 break; 3265 case UHF_PORT_ENABLE: 3266 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3267 break; 3268 case UHF_PORT_POWER: 3269 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3270 break; 3271 case UHF_PORT_INDICATOR: 3272 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3273 break; 3274 case UHF_PORT_SUSPEND: 3275 3276 /* U3 -> U15 */ 3277 if (i == 3) { 3278 XWRITE4(sc, oper, port, v | 3279 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3280 } 3281 3282 /* wait 20ms for resume sequence to complete */ 3283 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3284 3285 /* U0 */ 3286 XWRITE4(sc, oper, port, v | 3287 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3288 break; 3289 default: 3290 err = USB_ERR_IOERROR; 3291 goto done; 3292 } 3293 break; 3294 3295 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3296 if ((value & 0xff) != 0) { 3297 err = USB_ERR_IOERROR; 3298 goto done; 3299 } 3300 3301 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3302 3303 sc->sc_hub_desc.hubd = xhci_hubd; 3304 3305 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3306 3307 if (XHCI_HCS0_PPC(v)) 3308 i = UHD_PWR_INDIVIDUAL; 3309 else 3310 i = UHD_PWR_GANGED; 3311 3312 if (XHCI_HCS0_PIND(v)) 3313 i |= UHD_PORT_IND; 3314 3315 i |= UHD_OC_INDIVIDUAL; 3316 3317 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3318 3319 /* see XHCI section 5.4.9: */ 3320 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3321 3322 for (j = 1; j <= sc->sc_noport; j++) { 3323 3324 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3325 if (v & XHCI_PS_DR) { 3326 sc->sc_hub_desc.hubd. 3327 DeviceRemovable[j / 8] |= 1U << (j % 8); 3328 } 3329 } 3330 len = sc->sc_hub_desc.hubd.bLength; 3331 break; 3332 3333 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3334 len = 16; 3335 memset(sc->sc_hub_desc.temp, 0, 16); 3336 break; 3337 3338 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3339 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3340 3341 if ((index < 1) || 3342 (index > sc->sc_noport)) { 3343 err = USB_ERR_IOERROR; 3344 goto done; 3345 } 3346 3347 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3348 3349 DPRINTFN(9, "port status=0x%08x\n", v); 3350 3351 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3352 3353 switch (XHCI_PS_SPEED_GET(v)) { 3354 case 3: 3355 i |= UPS_HIGH_SPEED; 3356 break; 3357 case 2: 3358 i |= UPS_LOW_SPEED; 3359 break; 3360 case 1: 3361 /* FULL speed */ 3362 break; 3363 default: 3364 i |= UPS_OTHER_SPEED; 3365 break; 3366 } 3367 3368 if (v & XHCI_PS_CCS) 3369 i |= UPS_CURRENT_CONNECT_STATUS; 3370 if (v & XHCI_PS_PED) 3371 i |= UPS_PORT_ENABLED; 3372 if (v & XHCI_PS_OCA) 3373 i |= UPS_OVERCURRENT_INDICATOR; 3374 if (v & XHCI_PS_PR) 3375 i |= UPS_RESET; 3376 if (v & XHCI_PS_PP) { 3377 /* 3378 * The USB 3.0 RH is using the 3379 * USB 2.0's power bit 3380 */ 3381 i |= UPS_PORT_POWER; 3382 } 3383 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3384 3385 i = 0; 3386 if (v & XHCI_PS_CSC) 3387 i |= UPS_C_CONNECT_STATUS; 3388 if (v & XHCI_PS_PEC) 3389 i |= UPS_C_PORT_ENABLED; 3390 if (v & XHCI_PS_OCC) 3391 i |= UPS_C_OVERCURRENT_INDICATOR; 3392 if (v & XHCI_PS_WRC) 3393 i |= UPS_C_BH_PORT_RESET; 3394 if (v & XHCI_PS_PRC) 3395 i |= UPS_C_PORT_RESET; 3396 if (v & XHCI_PS_PLC) 3397 i |= UPS_C_PORT_LINK_STATE; 3398 if (v & XHCI_PS_CEC) 3399 i |= UPS_C_PORT_CONFIG_ERROR; 3400 3401 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3402 len = sizeof(sc->sc_hub_desc.ps); 3403 break; 3404 3405 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3406 err = USB_ERR_IOERROR; 3407 goto done; 3408 3409 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3410 break; 3411 3412 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3413 3414 i = index >> 8; 3415 index &= 0x00FF; 3416 3417 if ((index < 1) || 3418 (index > sc->sc_noport)) { 3419 err = USB_ERR_IOERROR; 3420 goto done; 3421 } 3422 3423 port = XHCI_PORTSC(index); 3424 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3425 3426 switch (value) { 3427 case UHF_PORT_U1_TIMEOUT: 3428 if (XHCI_PS_SPEED_GET(v) != 4) { 3429 err = USB_ERR_IOERROR; 3430 goto done; 3431 } 3432 port = XHCI_PORTPMSC(index); 3433 v = XREAD4(sc, oper, port); 3434 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3435 v |= XHCI_PM3_U1TO_SET(i); 3436 XWRITE4(sc, oper, port, v); 3437 break; 3438 case UHF_PORT_U2_TIMEOUT: 3439 if (XHCI_PS_SPEED_GET(v) != 4) { 3440 err = USB_ERR_IOERROR; 3441 goto done; 3442 } 3443 port = XHCI_PORTPMSC(index); 3444 v = XREAD4(sc, oper, port); 3445 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3446 v |= XHCI_PM3_U2TO_SET(i); 3447 XWRITE4(sc, oper, port, v); 3448 break; 3449 case UHF_BH_PORT_RESET: 3450 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3451 break; 3452 case UHF_PORT_LINK_STATE: 3453 XWRITE4(sc, oper, port, v | 3454 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3455 /* 4ms settle time */ 3456 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3457 break; 3458 case UHF_PORT_ENABLE: 3459 DPRINTFN(3, "set port enable %d\n", index); 3460 break; 3461 case UHF_PORT_SUSPEND: 3462 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3463 j = XHCI_PS_SPEED_GET(v); 3464 if ((j < 1) || (j > 3)) { 3465 /* non-supported speed */ 3466 err = USB_ERR_IOERROR; 3467 goto done; 3468 } 3469 XWRITE4(sc, oper, port, v | 3470 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3471 break; 3472 case UHF_PORT_RESET: 3473 DPRINTFN(6, "reset port %d\n", index); 3474 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3475 break; 3476 case UHF_PORT_POWER: 3477 DPRINTFN(3, "set port power %d\n", index); 3478 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3479 break; 3480 case UHF_PORT_TEST: 3481 DPRINTFN(3, "set port test %d\n", index); 3482 break; 3483 case UHF_PORT_INDICATOR: 3484 DPRINTFN(3, "set port indicator %d\n", index); 3485 3486 v &= ~XHCI_PS_PIC_SET(3); 3487 v |= XHCI_PS_PIC_SET(1); 3488 3489 XWRITE4(sc, oper, port, v); 3490 break; 3491 default: 3492 err = USB_ERR_IOERROR; 3493 goto done; 3494 } 3495 break; 3496 3497 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3498 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3499 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3500 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3501 break; 3502 default: 3503 err = USB_ERR_IOERROR; 3504 goto done; 3505 } 3506 done: 3507 *plength = len; 3508 *pptr = ptr; 3509 return (err); 3510 } 3511 3512 static void 3513 xhci_xfer_setup(struct usb_setup_params *parm) 3514 { 3515 struct usb_page_search page_info; 3516 struct usb_page_cache *pc; 3517 struct xhci_softc *sc; 3518 struct usb_xfer *xfer; 3519 void *last_obj; 3520 uint32_t ntd; 3521 uint32_t n; 3522 3523 sc = XHCI_BUS2SC(parm->udev->bus); 3524 xfer = parm->curr_xfer; 3525 3526 /* 3527 * The proof for the "ntd" formula is illustrated like this: 3528 * 3529 * +------------------------------------+ 3530 * | | 3531 * | |remainder -> | 3532 * | +-----+---+ | 3533 * | | xxx | x | frm 0 | 3534 * | +-----+---++ | 3535 * | | xxx | xx | frm 1 | 3536 * | +-----+----+ | 3537 * | ... | 3538 * +------------------------------------+ 3539 * 3540 * "xxx" means a completely full USB transfer descriptor 3541 * 3542 * "x" and "xx" means a short USB packet 3543 * 3544 * For the remainder of an USB transfer modulo 3545 * "max_data_length" we need two USB transfer descriptors. 3546 * One to transfer the remaining data and one to finalise with 3547 * a zero length packet in case the "force_short_xfer" flag is 3548 * set. We only need two USB transfer descriptors in the case 3549 * where the transfer length of the first one is a factor of 3550 * "max_frame_size". The rest of the needed USB transfer 3551 * descriptors is given by the buffer size divided by the 3552 * maximum data payload. 3553 */ 3554 parm->hc_max_packet_size = 0x400; 3555 parm->hc_max_packet_count = 16 * 3; 3556 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3557 3558 xfer->flags_int.bdma_enable = 1; 3559 3560 usbd_transfer_setup_sub(parm); 3561 3562 if (xfer->flags_int.isochronous_xfr) { 3563 ntd = ((1 * xfer->nframes) 3564 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3565 } else if (xfer->flags_int.control_xfr) { 3566 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3567 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3568 } else { 3569 ntd = ((2 * xfer->nframes) 3570 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3571 } 3572 3573 alloc_dma_set: 3574 3575 if (parm->err) 3576 return; 3577 3578 /* 3579 * Allocate queue heads and transfer descriptors 3580 */ 3581 last_obj = NULL; 3582 3583 if (usbd_transfer_setup_sub_malloc( 3584 parm, &pc, sizeof(struct xhci_td), 3585 XHCI_TD_ALIGN, ntd)) { 3586 parm->err = USB_ERR_NOMEM; 3587 return; 3588 } 3589 if (parm->buf) { 3590 for (n = 0; n != ntd; n++) { 3591 struct xhci_td *td; 3592 3593 usbd_get_page(pc + n, 0, &page_info); 3594 3595 td = page_info.buffer; 3596 3597 /* init TD */ 3598 td->td_self = page_info.physaddr; 3599 td->obj_next = last_obj; 3600 td->page_cache = pc + n; 3601 3602 last_obj = td; 3603 3604 usb_pc_cpu_flush(pc + n); 3605 } 3606 } 3607 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3608 3609 if (!xfer->flags_int.curr_dma_set) { 3610 xfer->flags_int.curr_dma_set = 1; 3611 goto alloc_dma_set; 3612 } 3613 } 3614 3615 static usb_error_t 3616 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3617 { 3618 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3619 struct usb_page_search buf_inp; 3620 struct usb_device *udev; 3621 struct xhci_endpoint_ext *pepext; 3622 struct usb_endpoint_descriptor *edesc; 3623 struct usb_page_cache *pcinp; 3624 usb_error_t err; 3625 usb_stream_t stream_id; 3626 uint8_t index; 3627 uint8_t epno; 3628 3629 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3630 xfer->endpoint->edesc); 3631 3632 udev = xfer->xroot->udev; 3633 index = udev->controller_slot_id; 3634 3635 pcinp = &sc->sc_hw.devs[index].input_pc; 3636 3637 usbd_get_page(pcinp, 0, &buf_inp); 3638 3639 edesc = xfer->endpoint->edesc; 3640 3641 epno = edesc->bEndpointAddress; 3642 stream_id = xfer->stream_id; 3643 3644 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3645 epno |= UE_DIR_IN; 3646 3647 epno = XHCI_EPNO2EPID(epno); 3648 3649 if (epno == 0) 3650 return (USB_ERR_NO_PIPE); /* invalid */ 3651 3652 XHCI_CMD_LOCK(sc); 3653 3654 /* configure endpoint */ 3655 3656 err = xhci_configure_endpoint_by_xfer(xfer); 3657 3658 if (err != 0) { 3659 XHCI_CMD_UNLOCK(sc); 3660 return (err); 3661 } 3662 3663 /* 3664 * Get the endpoint into the stopped state according to the 3665 * endpoint context state diagram in the XHCI specification: 3666 */ 3667 3668 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3669 3670 if (err != 0) 3671 DPRINTF("Could not stop endpoint %u\n", epno); 3672 3673 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3674 3675 if (err != 0) 3676 DPRINTF("Could not reset endpoint %u\n", epno); 3677 3678 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3679 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3680 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3681 stream_id, epno, index); 3682 3683 if (err != 0) 3684 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3685 3686 /* 3687 * Get the endpoint into the running state according to the 3688 * endpoint context state diagram in the XHCI specification: 3689 */ 3690 3691 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3692 3693 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3694 3695 if (err != 0) 3696 DPRINTF("Could not configure endpoint %u\n", epno); 3697 3698 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3699 3700 if (err != 0) 3701 DPRINTF("Could not configure endpoint %u\n", epno); 3702 3703 XHCI_CMD_UNLOCK(sc); 3704 3705 return (0); 3706 } 3707 3708 static void 3709 xhci_xfer_unsetup(struct usb_xfer *xfer) 3710 { 3711 return; 3712 } 3713 3714 static void 3715 xhci_start_dma_delay(struct usb_xfer *xfer) 3716 { 3717 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3718 3719 /* put transfer on interrupt queue (again) */ 3720 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3721 3722 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3723 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3724 } 3725 3726 static void 3727 xhci_configure_msg(struct usb_proc_msg *pm) 3728 { 3729 struct xhci_softc *sc; 3730 struct xhci_endpoint_ext *pepext; 3731 struct usb_xfer *xfer; 3732 3733 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3734 3735 restart: 3736 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3737 3738 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3739 xfer->endpoint->edesc); 3740 3741 if ((pepext->trb_halted != 0) || 3742 (pepext->trb_running == 0)) { 3743 3744 uint16_t i; 3745 3746 /* clear halted and running */ 3747 pepext->trb_halted = 0; 3748 pepext->trb_running = 0; 3749 3750 /* nuke remaining buffered transfers */ 3751 3752 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3753 XHCI_MAX_STREAMS); i++) { 3754 /* 3755 * NOTE: We need to use the timeout 3756 * error code here else existing 3757 * isochronous clients can get 3758 * confused: 3759 */ 3760 if (pepext->xfer[i] != NULL) { 3761 xhci_device_done(pepext->xfer[i], 3762 USB_ERR_TIMEOUT); 3763 } 3764 } 3765 3766 /* 3767 * NOTE: The USB transfer cannot vanish in 3768 * this state! 3769 */ 3770 3771 USB_BUS_UNLOCK(&sc->sc_bus); 3772 3773 xhci_configure_reset_endpoint(xfer); 3774 3775 USB_BUS_LOCK(&sc->sc_bus); 3776 3777 /* check if halted is still cleared */ 3778 if (pepext->trb_halted == 0) { 3779 pepext->trb_running = 1; 3780 memset(pepext->trb_index, 0, 3781 sizeof(pepext->trb_index)); 3782 } 3783 goto restart; 3784 } 3785 3786 if (xfer->flags_int.did_dma_delay) { 3787 3788 /* remove transfer from interrupt queue (again) */ 3789 usbd_transfer_dequeue(xfer); 3790 3791 /* we are finally done */ 3792 usb_dma_delay_done_cb(xfer); 3793 3794 /* queue changed - restart */ 3795 goto restart; 3796 } 3797 } 3798 3799 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3800 3801 /* try to insert xfer on HW queue */ 3802 xhci_transfer_insert(xfer); 3803 3804 /* try to multi buffer */ 3805 xhci_device_generic_multi_enter(xfer->endpoint, 3806 xfer->stream_id, NULL); 3807 } 3808 } 3809 3810 static void 3811 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3812 struct usb_endpoint *ep) 3813 { 3814 struct xhci_endpoint_ext *pepext; 3815 3816 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3817 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3818 3819 if (udev->parent_hub == NULL) { 3820 /* root HUB has special endpoint handling */ 3821 return; 3822 } 3823 3824 ep->methods = &xhci_device_generic_methods; 3825 3826 pepext = xhci_get_endpoint_ext(udev, edesc); 3827 3828 USB_BUS_LOCK(udev->bus); 3829 pepext->trb_halted = 1; 3830 pepext->trb_running = 0; 3831 USB_BUS_UNLOCK(udev->bus); 3832 } 3833 3834 static void 3835 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3836 { 3837 3838 } 3839 3840 static void 3841 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3842 { 3843 struct xhci_endpoint_ext *pepext; 3844 3845 DPRINTF("\n"); 3846 3847 if (udev->flags.usb_mode != USB_MODE_HOST) { 3848 /* not supported */ 3849 return; 3850 } 3851 if (udev->parent_hub == NULL) { 3852 /* root HUB has special endpoint handling */ 3853 return; 3854 } 3855 3856 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3857 3858 USB_BUS_LOCK(udev->bus); 3859 pepext->trb_halted = 1; 3860 pepext->trb_running = 0; 3861 USB_BUS_UNLOCK(udev->bus); 3862 } 3863 3864 static usb_error_t 3865 xhci_device_init(struct usb_device *udev) 3866 { 3867 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3868 usb_error_t err; 3869 uint8_t temp; 3870 3871 /* no init for root HUB */ 3872 if (udev->parent_hub == NULL) 3873 return (0); 3874 3875 XHCI_CMD_LOCK(sc); 3876 3877 /* set invalid default */ 3878 3879 udev->controller_slot_id = sc->sc_noslot + 1; 3880 3881 /* try to get a new slot ID from the XHCI */ 3882 3883 err = xhci_cmd_enable_slot(sc, &temp); 3884 3885 if (err) { 3886 XHCI_CMD_UNLOCK(sc); 3887 return (err); 3888 } 3889 3890 if (temp > sc->sc_noslot) { 3891 XHCI_CMD_UNLOCK(sc); 3892 return (USB_ERR_BAD_ADDRESS); 3893 } 3894 3895 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 3896 DPRINTF("slot %u already allocated.\n", temp); 3897 XHCI_CMD_UNLOCK(sc); 3898 return (USB_ERR_BAD_ADDRESS); 3899 } 3900 3901 /* store slot ID for later reference */ 3902 3903 udev->controller_slot_id = temp; 3904 3905 /* reset data structure */ 3906 3907 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 3908 3909 /* set mark slot allocated */ 3910 3911 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 3912 3913 err = xhci_alloc_device_ext(udev); 3914 3915 XHCI_CMD_UNLOCK(sc); 3916 3917 /* get device into default state */ 3918 3919 if (err == 0) 3920 err = xhci_set_address(udev, NULL, 0); 3921 3922 return (err); 3923 } 3924 3925 static void 3926 xhci_device_uninit(struct usb_device *udev) 3927 { 3928 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3929 uint8_t index; 3930 3931 /* no init for root HUB */ 3932 if (udev->parent_hub == NULL) 3933 return; 3934 3935 XHCI_CMD_LOCK(sc); 3936 3937 index = udev->controller_slot_id; 3938 3939 if (index <= sc->sc_noslot) { 3940 xhci_cmd_disable_slot(sc, index); 3941 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 3942 3943 /* free device extension */ 3944 xhci_free_device_ext(udev); 3945 } 3946 3947 XHCI_CMD_UNLOCK(sc); 3948 } 3949 3950 static void 3951 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3952 { 3953 /* 3954 * Wait until the hardware has finished any possible use of 3955 * the transfer descriptor(s) 3956 */ 3957 *pus = 2048; /* microseconds */ 3958 } 3959 3960 static void 3961 xhci_device_resume(struct usb_device *udev) 3962 { 3963 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3964 uint8_t index; 3965 uint8_t n; 3966 uint8_t p; 3967 3968 DPRINTF("\n"); 3969 3970 /* check for root HUB */ 3971 if (udev->parent_hub == NULL) 3972 return; 3973 3974 index = udev->controller_slot_id; 3975 3976 XHCI_CMD_LOCK(sc); 3977 3978 /* blindly resume all endpoints */ 3979 3980 USB_BUS_LOCK(udev->bus); 3981 3982 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3983 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 3984 XWRITE4(sc, door, XHCI_DOORBELL(index), 3985 n | XHCI_DB_SID_SET(p)); 3986 } 3987 } 3988 3989 USB_BUS_UNLOCK(udev->bus); 3990 3991 XHCI_CMD_UNLOCK(sc); 3992 } 3993 3994 static void 3995 xhci_device_suspend(struct usb_device *udev) 3996 { 3997 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3998 uint8_t index; 3999 uint8_t n; 4000 usb_error_t err; 4001 4002 DPRINTF("\n"); 4003 4004 /* check for root HUB */ 4005 if (udev->parent_hub == NULL) 4006 return; 4007 4008 index = udev->controller_slot_id; 4009 4010 XHCI_CMD_LOCK(sc); 4011 4012 /* blindly suspend all endpoints */ 4013 4014 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4015 err = xhci_cmd_stop_ep(sc, 1, n, index); 4016 if (err != 0) { 4017 DPRINTF("Failed to suspend endpoint " 4018 "%u on slot %u (ignored).\n", n, index); 4019 } 4020 } 4021 4022 XHCI_CMD_UNLOCK(sc); 4023 } 4024 4025 static void 4026 xhci_set_hw_power(struct usb_bus *bus) 4027 { 4028 DPRINTF("\n"); 4029 } 4030 4031 static void 4032 xhci_device_state_change(struct usb_device *udev) 4033 { 4034 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4035 struct usb_page_search buf_inp; 4036 usb_error_t err; 4037 uint8_t index; 4038 4039 /* check for root HUB */ 4040 if (udev->parent_hub == NULL) 4041 return; 4042 4043 index = udev->controller_slot_id; 4044 4045 DPRINTF("\n"); 4046 4047 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4048 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4049 &sc->sc_hw.devs[index].tt); 4050 if (err != 0) 4051 sc->sc_hw.devs[index].nports = 0; 4052 } 4053 4054 XHCI_CMD_LOCK(sc); 4055 4056 switch (usb_get_device_state(udev)) { 4057 case USB_STATE_POWERED: 4058 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4059 break; 4060 4061 /* set default state */ 4062 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4063 4064 /* reset number of contexts */ 4065 sc->sc_hw.devs[index].context_num = 0; 4066 4067 err = xhci_cmd_reset_dev(sc, index); 4068 4069 if (err != 0) { 4070 DPRINTF("Device reset failed " 4071 "for slot %u.\n", index); 4072 } 4073 break; 4074 4075 case USB_STATE_ADDRESSED: 4076 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4077 break; 4078 4079 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4080 4081 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4082 4083 if (err) { 4084 DPRINTF("Failed to deconfigure " 4085 "slot %u.\n", index); 4086 } 4087 break; 4088 4089 case USB_STATE_CONFIGURED: 4090 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4091 break; 4092 4093 /* set configured state */ 4094 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4095 4096 /* reset number of contexts */ 4097 sc->sc_hw.devs[index].context_num = 0; 4098 4099 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4100 4101 xhci_configure_mask(udev, 3, 0); 4102 4103 err = xhci_configure_device(udev); 4104 if (err != 0) { 4105 DPRINTF("Could not configure device " 4106 "at slot %u.\n", index); 4107 } 4108 4109 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4110 if (err != 0) { 4111 DPRINTF("Could not evaluate device " 4112 "context at slot %u.\n", index); 4113 } 4114 break; 4115 4116 default: 4117 break; 4118 } 4119 XHCI_CMD_UNLOCK(sc); 4120 } 4121 4122 static usb_error_t 4123 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4124 uint8_t ep_mode) 4125 { 4126 switch (ep_mode) { 4127 case USB_EP_MODE_DEFAULT: 4128 return (0); 4129 case USB_EP_MODE_STREAMS: 4130 if ((ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4131 udev->speed != USB_SPEED_SUPER) 4132 return (USB_ERR_INVAL); 4133 return (0); 4134 default: 4135 return (USB_ERR_INVAL); 4136 } 4137 } 4138 4139 struct usb_bus_methods xhci_bus_methods = { 4140 .endpoint_init = xhci_ep_init, 4141 .endpoint_uninit = xhci_ep_uninit, 4142 .xfer_setup = xhci_xfer_setup, 4143 .xfer_unsetup = xhci_xfer_unsetup, 4144 .get_dma_delay = xhci_get_dma_delay, 4145 .device_init = xhci_device_init, 4146 .device_uninit = xhci_device_uninit, 4147 .device_resume = xhci_device_resume, 4148 .device_suspend = xhci_device_suspend, 4149 .set_hw_power = xhci_set_hw_power, 4150 .roothub_exec = xhci_roothub_exec, 4151 .xfer_poll = xhci_do_poll, 4152 .start_dma_delay = xhci_start_dma_delay, 4153 .set_address = xhci_set_address, 4154 .clear_stall = xhci_ep_clear_stall, 4155 .device_state_change = xhci_device_state_change, 4156 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4157 .set_endpoint_mode = xhci_set_endpoint_mode, 4158 }; 4159