1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36 /* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we avoid too much diveration among USB drivers. 40 */ 41 42 #ifdef USB_GLOBAL_INCLUDE_FILE 43 #include USB_GLOBAL_INCLUDE_FILE 44 #else 45 #include <sys/stdint.h> 46 #include <sys/stddef.h> 47 #include <sys/param.h> 48 #include <sys/queue.h> 49 #include <sys/types.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/bus.h> 53 #include <sys/module.h> 54 #include <sys/lock.h> 55 #include <sys/mutex.h> 56 #include <sys/condvar.h> 57 #include <sys/sysctl.h> 58 #include <sys/sx.h> 59 #include <sys/unistd.h> 60 #include <sys/callout.h> 61 #include <sys/malloc.h> 62 #include <sys/priv.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 67 #define USB_DEBUG_VAR xhcidebug 68 69 #include <dev/usb/usb_core.h> 70 #include <dev/usb/usb_debug.h> 71 #include <dev/usb/usb_busdma.h> 72 #include <dev/usb/usb_process.h> 73 #include <dev/usb/usb_transfer.h> 74 #include <dev/usb/usb_device.h> 75 #include <dev/usb/usb_hub.h> 76 #include <dev/usb/usb_util.h> 77 78 #include <dev/usb/usb_controller.h> 79 #include <dev/usb/usb_bus.h> 80 #endif /* USB_GLOBAL_INCLUDE_FILE */ 81 82 #include <dev/usb/controller/xhci.h> 83 #include <dev/usb/controller/xhcireg.h> 84 85 #define XHCI_BUS2SC(bus) \ 86 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 87 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 88 89 #ifdef USB_DEBUG 90 static int xhcidebug; 91 static int xhciroute; 92 93 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 95 &xhcidebug, 0, "Debug level"); 96 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 97 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN, 98 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 99 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 100 #endif 101 102 #define XHCI_INTR_ENDPT 1 103 104 struct xhci_std_temp { 105 struct xhci_softc *sc; 106 struct usb_page_cache *pc; 107 struct xhci_td *td; 108 struct xhci_td *td_next; 109 uint32_t len; 110 uint32_t offset; 111 uint32_t max_packet_size; 112 uint32_t average; 113 uint16_t isoc_delta; 114 uint16_t isoc_frame; 115 uint8_t shortpkt; 116 uint8_t multishort; 117 uint8_t last_frame; 118 uint8_t trb_type; 119 uint8_t direction; 120 uint8_t tbc; 121 uint8_t tlbpc; 122 uint8_t step_td; 123 uint8_t do_isoc_sync; 124 }; 125 126 static void xhci_do_poll(struct usb_bus *); 127 static void xhci_device_done(struct usb_xfer *, usb_error_t); 128 static void xhci_root_intr(struct xhci_softc *); 129 static void xhci_free_device_ext(struct usb_device *); 130 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 131 struct usb_endpoint_descriptor *); 132 static usb_proc_callback_t xhci_configure_msg; 133 static usb_error_t xhci_configure_device(struct usb_device *); 134 static usb_error_t xhci_configure_endpoint(struct usb_device *, 135 struct usb_endpoint_descriptor *, uint64_t, uint16_t, 136 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, uint8_t); 137 static usb_error_t xhci_configure_mask(struct usb_device *, 138 uint32_t, uint8_t); 139 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 140 uint64_t, uint8_t); 141 static void xhci_endpoint_doorbell(struct usb_xfer *); 142 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 143 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 144 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 145 #ifdef USB_DEBUG 146 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 147 #endif 148 149 extern struct usb_bus_methods xhci_bus_methods; 150 151 #ifdef USB_DEBUG 152 static void 153 xhci_dump_trb(struct xhci_trb *trb) 154 { 155 DPRINTFN(5, "trb = %p\n", trb); 156 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 157 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 158 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 159 } 160 161 static void 162 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 163 { 164 DPRINTFN(5, "pep = %p\n", pep); 165 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 166 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 167 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 168 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 169 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 170 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 171 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 172 } 173 174 static void 175 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 176 { 177 DPRINTFN(5, "psl = %p\n", psl); 178 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 179 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 180 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 181 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 182 } 183 #endif 184 185 uint32_t 186 xhci_get_port_route(void) 187 { 188 #ifdef USB_DEBUG 189 return (0xFFFFFFFFU ^ ((uint32_t)xhciroute)); 190 #else 191 return (0xFFFFFFFFU); 192 #endif 193 } 194 195 static void 196 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 197 { 198 struct xhci_softc *sc = XHCI_BUS2SC(bus); 199 uint8_t i; 200 201 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 202 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 203 204 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 205 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 206 207 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 208 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 209 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 210 } 211 } 212 213 static void 214 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 215 { 216 if (sc->sc_ctx_is_64_byte) { 217 uint32_t offset; 218 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 219 /* all contexts are initially 32-bytes */ 220 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 221 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 222 } 223 *ptr = htole32(val); 224 } 225 226 static uint32_t 227 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 228 { 229 if (sc->sc_ctx_is_64_byte) { 230 uint32_t offset; 231 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 232 /* all contexts are initially 32-bytes */ 233 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 234 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 235 } 236 return (le32toh(*ptr)); 237 } 238 239 static void 240 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 241 { 242 if (sc->sc_ctx_is_64_byte) { 243 uint32_t offset; 244 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 245 /* all contexts are initially 32-bytes */ 246 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 247 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 248 } 249 *ptr = htole64(val); 250 } 251 252 #ifdef USB_DEBUG 253 static uint64_t 254 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 255 { 256 if (sc->sc_ctx_is_64_byte) { 257 uint32_t offset; 258 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 259 /* all contexts are initially 32-bytes */ 260 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 261 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 262 } 263 return (le64toh(*ptr)); 264 } 265 #endif 266 267 usb_error_t 268 xhci_start_controller(struct xhci_softc *sc) 269 { 270 struct usb_page_search buf_res; 271 struct xhci_hw_root *phwr; 272 struct xhci_dev_ctx_addr *pdctxa; 273 uint64_t addr; 274 uint32_t temp; 275 uint16_t i; 276 277 DPRINTF("\n"); 278 279 sc->sc_capa_off = 0; 280 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 281 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 282 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 283 284 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 285 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 286 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 287 288 sc->sc_event_ccs = 1; 289 sc->sc_event_idx = 0; 290 sc->sc_command_ccs = 1; 291 sc->sc_command_idx = 0; 292 293 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 294 295 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 296 297 DPRINTF("HCS0 = 0x%08x\n", temp); 298 299 if (XHCI_HCS0_CSZ(temp)) { 300 sc->sc_ctx_is_64_byte = 1; 301 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 302 } else { 303 sc->sc_ctx_is_64_byte = 0; 304 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 305 } 306 307 /* Reset controller */ 308 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 309 310 for (i = 0; i != 100; i++) { 311 usb_pause_mtx(NULL, hz / 100); 312 temp = XREAD4(sc, oper, XHCI_USBCMD) & 313 (XHCI_CMD_HCRST | XHCI_STS_CNR); 314 if (!temp) 315 break; 316 } 317 318 if (temp) { 319 device_printf(sc->sc_bus.parent, "Controller " 320 "reset timeout.\n"); 321 return (USB_ERR_IOERROR); 322 } 323 324 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 325 device_printf(sc->sc_bus.parent, "Controller does " 326 "not support 4K page size.\n"); 327 return (USB_ERR_IOERROR); 328 } 329 330 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 331 332 i = XHCI_HCS1_N_PORTS(temp); 333 334 if (i == 0) { 335 device_printf(sc->sc_bus.parent, "Invalid number " 336 "of ports: %u\n", i); 337 return (USB_ERR_IOERROR); 338 } 339 340 sc->sc_noport = i; 341 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 342 343 if (sc->sc_noslot > XHCI_MAX_DEVICES) 344 sc->sc_noslot = XHCI_MAX_DEVICES; 345 346 /* setup number of device slots */ 347 348 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 349 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 350 351 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 352 353 DPRINTF("Max slots: %u\n", sc->sc_noslot); 354 355 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 356 357 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 358 359 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 360 device_printf(sc->sc_bus.parent, "XHCI request " 361 "too many scratchpads\n"); 362 return (USB_ERR_NOMEM); 363 } 364 365 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 366 367 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 368 369 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 370 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 371 372 temp = XREAD4(sc, oper, XHCI_USBSTS); 373 374 /* clear interrupts */ 375 XWRITE4(sc, oper, XHCI_USBSTS, temp); 376 /* disable all device notifications */ 377 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 378 379 /* setup device context base address */ 380 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 381 pdctxa = buf_res.buffer; 382 memset(pdctxa, 0, sizeof(*pdctxa)); 383 384 addr = buf_res.physaddr; 385 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 386 387 /* slot 0 points to the table of scratchpad pointers */ 388 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 389 390 for (i = 0; i != sc->sc_noscratch; i++) { 391 struct usb_page_search buf_scp; 392 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 393 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 394 } 395 396 addr = buf_res.physaddr; 397 398 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 399 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 400 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 401 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 402 403 /* Setup event table size */ 404 405 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 406 407 DPRINTF("HCS2=0x%08x\n", temp); 408 409 temp = XHCI_HCS2_ERST_MAX(temp); 410 temp = 1U << temp; 411 if (temp > XHCI_MAX_RSEG) 412 temp = XHCI_MAX_RSEG; 413 414 sc->sc_erst_max = temp; 415 416 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 417 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 418 419 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 420 421 /* Setup interrupt rate */ 422 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 423 424 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 425 426 phwr = buf_res.buffer; 427 addr = buf_res.physaddr; 428 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 429 430 /* reset hardware root structure */ 431 memset(phwr, 0, sizeof(*phwr)); 432 433 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 434 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 435 436 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 437 438 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 439 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 440 441 addr = (uint64_t)buf_res.physaddr; 442 443 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 444 445 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 446 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 447 448 /* Setup interrupter registers */ 449 450 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 451 temp |= XHCI_IMAN_INTR_ENA; 452 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 453 454 /* setup command ring control base address */ 455 addr = buf_res.physaddr; 456 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 457 458 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 459 460 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 461 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 462 463 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 464 465 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 466 467 /* Go! */ 468 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 469 XHCI_CMD_INTE | XHCI_CMD_HSEE); 470 471 for (i = 0; i != 100; i++) { 472 usb_pause_mtx(NULL, hz / 100); 473 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 474 if (!temp) 475 break; 476 } 477 if (temp) { 478 XWRITE4(sc, oper, XHCI_USBCMD, 0); 479 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 480 return (USB_ERR_IOERROR); 481 } 482 483 /* catch any lost interrupts */ 484 xhci_do_poll(&sc->sc_bus); 485 486 return (0); 487 } 488 489 usb_error_t 490 xhci_halt_controller(struct xhci_softc *sc) 491 { 492 uint32_t temp; 493 uint16_t i; 494 495 DPRINTF("\n"); 496 497 sc->sc_capa_off = 0; 498 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 499 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 500 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 501 502 /* Halt controller */ 503 XWRITE4(sc, oper, XHCI_USBCMD, 0); 504 505 for (i = 0; i != 100; i++) { 506 usb_pause_mtx(NULL, hz / 100); 507 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 508 if (temp) 509 break; 510 } 511 512 if (!temp) { 513 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 514 return (USB_ERR_IOERROR); 515 } 516 return (0); 517 } 518 519 usb_error_t 520 xhci_init(struct xhci_softc *sc, device_t self) 521 { 522 /* initialise some bus fields */ 523 sc->sc_bus.parent = self; 524 525 /* set the bus revision */ 526 sc->sc_bus.usbrev = USB_REV_3_0; 527 528 /* set up the bus struct */ 529 sc->sc_bus.methods = &xhci_bus_methods; 530 531 /* setup devices array */ 532 sc->sc_bus.devices = sc->sc_devices; 533 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 534 535 /* setup command queue mutex and condition varible */ 536 cv_init(&sc->sc_cmd_cv, "CMDQ"); 537 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 538 539 /* get all DMA memory */ 540 if (usb_bus_mem_alloc_all(&sc->sc_bus, 541 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 542 return (ENOMEM); 543 } 544 545 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 546 sc->sc_config_msg[0].bus = &sc->sc_bus; 547 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 548 sc->sc_config_msg[1].bus = &sc->sc_bus; 549 550 return (0); 551 } 552 553 void 554 xhci_uninit(struct xhci_softc *sc) 555 { 556 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 557 558 cv_destroy(&sc->sc_cmd_cv); 559 sx_destroy(&sc->sc_cmd_sx); 560 } 561 562 static void 563 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 564 { 565 struct xhci_softc *sc = XHCI_BUS2SC(bus); 566 567 switch (state) { 568 case USB_HW_POWER_SUSPEND: 569 DPRINTF("Stopping the XHCI\n"); 570 xhci_halt_controller(sc); 571 break; 572 case USB_HW_POWER_SHUTDOWN: 573 DPRINTF("Stopping the XHCI\n"); 574 xhci_halt_controller(sc); 575 break; 576 case USB_HW_POWER_RESUME: 577 DPRINTF("Starting the XHCI\n"); 578 xhci_start_controller(sc); 579 break; 580 default: 581 break; 582 } 583 } 584 585 static usb_error_t 586 xhci_generic_done_sub(struct usb_xfer *xfer) 587 { 588 struct xhci_td *td; 589 struct xhci_td *td_alt_next; 590 uint32_t len; 591 uint8_t status; 592 593 td = xfer->td_transfer_cache; 594 td_alt_next = td->alt_next; 595 596 if (xfer->aframes != xfer->nframes) 597 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 598 599 while (1) { 600 601 usb_pc_cpu_invalidate(td->page_cache); 602 603 status = td->status; 604 len = td->remainder; 605 606 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 607 xfer, (unsigned int)xfer->aframes, 608 (unsigned int)xfer->nframes, 609 (unsigned int)len, (unsigned int)td->len, 610 (unsigned int)status); 611 612 /* 613 * Verify the status length and 614 * add the length to "frlengths[]": 615 */ 616 if (len > td->len) { 617 /* should not happen */ 618 DPRINTF("Invalid status length, " 619 "0x%04x/0x%04x bytes\n", len, td->len); 620 status = XHCI_TRB_ERROR_LENGTH; 621 } else if (xfer->aframes != xfer->nframes) { 622 xfer->frlengths[xfer->aframes] += td->len - len; 623 } 624 /* Check for last transfer */ 625 if (((void *)td) == xfer->td_transfer_last) { 626 td = NULL; 627 break; 628 } 629 /* Check for transfer error */ 630 if (status != XHCI_TRB_ERROR_SHORT_PKT && 631 status != XHCI_TRB_ERROR_SUCCESS) { 632 /* the transfer is finished */ 633 td = NULL; 634 break; 635 } 636 /* Check for short transfer */ 637 if (len > 0) { 638 if (xfer->flags_int.short_frames_ok || 639 xfer->flags_int.isochronous_xfr || 640 xfer->flags_int.control_xfr) { 641 /* follow alt next */ 642 td = td->alt_next; 643 } else { 644 /* the transfer is finished */ 645 td = NULL; 646 } 647 break; 648 } 649 td = td->obj_next; 650 651 if (td->alt_next != td_alt_next) { 652 /* this USB frame is complete */ 653 break; 654 } 655 } 656 657 /* update transfer cache */ 658 659 xfer->td_transfer_cache = td; 660 661 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 662 (status != XHCI_TRB_ERROR_SHORT_PKT && 663 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 664 USB_ERR_NORMAL_COMPLETION); 665 } 666 667 static void 668 xhci_generic_done(struct usb_xfer *xfer) 669 { 670 usb_error_t err = 0; 671 672 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 673 xfer, xfer->endpoint); 674 675 /* reset scanner */ 676 677 xfer->td_transfer_cache = xfer->td_transfer_first; 678 679 if (xfer->flags_int.control_xfr) { 680 681 if (xfer->flags_int.control_hdr) 682 err = xhci_generic_done_sub(xfer); 683 684 xfer->aframes = 1; 685 686 if (xfer->td_transfer_cache == NULL) 687 goto done; 688 } 689 690 while (xfer->aframes != xfer->nframes) { 691 692 err = xhci_generic_done_sub(xfer); 693 xfer->aframes++; 694 695 if (xfer->td_transfer_cache == NULL) 696 goto done; 697 } 698 699 if (xfer->flags_int.control_xfr && 700 !xfer->flags_int.control_act) 701 err = xhci_generic_done_sub(xfer); 702 done: 703 /* transfer is complete */ 704 xhci_device_done(xfer, err); 705 } 706 707 static void 708 xhci_activate_transfer(struct usb_xfer *xfer) 709 { 710 struct xhci_td *td; 711 712 td = xfer->td_transfer_cache; 713 714 usb_pc_cpu_invalidate(td->page_cache); 715 716 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 717 718 /* activate the transfer */ 719 720 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 721 usb_pc_cpu_flush(td->page_cache); 722 723 xhci_endpoint_doorbell(xfer); 724 } 725 } 726 727 static void 728 xhci_skip_transfer(struct usb_xfer *xfer) 729 { 730 struct xhci_td *td; 731 struct xhci_td *td_last; 732 733 td = xfer->td_transfer_cache; 734 td_last = xfer->td_transfer_last; 735 736 td = td->alt_next; 737 738 usb_pc_cpu_invalidate(td->page_cache); 739 740 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 741 742 usb_pc_cpu_invalidate(td_last->page_cache); 743 744 /* copy LINK TRB to current waiting location */ 745 746 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 747 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 748 usb_pc_cpu_flush(td->page_cache); 749 750 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 751 usb_pc_cpu_flush(td->page_cache); 752 753 xhci_endpoint_doorbell(xfer); 754 } 755 } 756 757 /*------------------------------------------------------------------------* 758 * xhci_check_transfer 759 *------------------------------------------------------------------------*/ 760 static void 761 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 762 { 763 int64_t offset; 764 uint64_t td_event; 765 uint32_t temp; 766 uint32_t remainder; 767 uint8_t status; 768 uint8_t halted; 769 uint8_t epno; 770 uint8_t index; 771 uint8_t i; 772 773 /* decode TRB */ 774 td_event = le64toh(trb->qwTrb0); 775 temp = le32toh(trb->dwTrb2); 776 777 remainder = XHCI_TRB_2_REM_GET(temp); 778 status = XHCI_TRB_2_ERROR_GET(temp); 779 780 temp = le32toh(trb->dwTrb3); 781 epno = XHCI_TRB_3_EP_GET(temp); 782 index = XHCI_TRB_3_SLOT_GET(temp); 783 784 /* check if error means halted */ 785 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 786 status != XHCI_TRB_ERROR_SUCCESS); 787 788 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 789 index, epno, remainder, status); 790 791 if (index > sc->sc_noslot) { 792 DPRINTF("Invalid slot.\n"); 793 return; 794 } 795 796 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 797 DPRINTF("Invalid endpoint.\n"); 798 return; 799 } 800 801 /* try to find the USB transfer that generated the event */ 802 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 803 struct usb_xfer *xfer; 804 struct xhci_td *td; 805 struct xhci_endpoint_ext *pepext; 806 807 pepext = &sc->sc_hw.devs[index].endp[epno]; 808 809 xfer = pepext->xfer[i]; 810 if (xfer == NULL) 811 continue; 812 813 td = xfer->td_transfer_cache; 814 815 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 816 (long long)td_event, 817 (long long)td->td_self, 818 (long long)td->td_self + sizeof(td->td_trb)); 819 820 /* 821 * NOTE: Some XHCI implementations might not trigger 822 * an event on the last LINK TRB so we need to 823 * consider both the last and second last event 824 * address as conditions for a successful transfer. 825 * 826 * NOTE: We assume that the XHCI will only trigger one 827 * event per chain of TRBs. 828 */ 829 830 offset = td_event - td->td_self; 831 832 if (offset >= 0 && 833 offset < (int64_t)sizeof(td->td_trb)) { 834 835 usb_pc_cpu_invalidate(td->page_cache); 836 837 /* compute rest of remainder, if any */ 838 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 839 temp = le32toh(td->td_trb[i].dwTrb2); 840 remainder += XHCI_TRB_2_BYTES_GET(temp); 841 } 842 843 DPRINTFN(5, "New remainder: %u\n", remainder); 844 845 /* clear isochronous transfer errors */ 846 if (xfer->flags_int.isochronous_xfr) { 847 if (halted) { 848 halted = 0; 849 status = XHCI_TRB_ERROR_SUCCESS; 850 remainder = td->len; 851 } 852 } 853 854 /* "td->remainder" is verified later */ 855 td->remainder = remainder; 856 td->status = status; 857 858 usb_pc_cpu_flush(td->page_cache); 859 860 /* 861 * 1) Last transfer descriptor makes the 862 * transfer done 863 */ 864 if (((void *)td) == xfer->td_transfer_last) { 865 DPRINTF("TD is last\n"); 866 xhci_generic_done(xfer); 867 break; 868 } 869 870 /* 871 * 2) Any kind of error makes the transfer 872 * done 873 */ 874 if (halted) { 875 DPRINTF("TD has I/O error\n"); 876 xhci_generic_done(xfer); 877 break; 878 } 879 880 /* 881 * 3) If there is no alternate next transfer, 882 * a short packet also makes the transfer done 883 */ 884 if (td->remainder > 0) { 885 if (td->alt_next == NULL) { 886 DPRINTF( 887 "short TD has no alternate next\n"); 888 xhci_generic_done(xfer); 889 break; 890 } 891 DPRINTF("TD has short pkt\n"); 892 if (xfer->flags_int.short_frames_ok || 893 xfer->flags_int.isochronous_xfr || 894 xfer->flags_int.control_xfr) { 895 /* follow the alt next */ 896 xfer->td_transfer_cache = td->alt_next; 897 xhci_activate_transfer(xfer); 898 break; 899 } 900 xhci_skip_transfer(xfer); 901 xhci_generic_done(xfer); 902 break; 903 } 904 905 /* 906 * 4) Transfer complete - go to next TD 907 */ 908 DPRINTF("Following next TD\n"); 909 xfer->td_transfer_cache = td->obj_next; 910 xhci_activate_transfer(xfer); 911 break; /* there should only be one match */ 912 } 913 } 914 } 915 916 static void 917 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 918 { 919 if (sc->sc_cmd_addr == trb->qwTrb0) { 920 DPRINTF("Received command event\n"); 921 sc->sc_cmd_result[0] = trb->dwTrb2; 922 sc->sc_cmd_result[1] = trb->dwTrb3; 923 cv_signal(&sc->sc_cmd_cv); 924 } 925 } 926 927 static void 928 xhci_interrupt_poll(struct xhci_softc *sc) 929 { 930 struct usb_page_search buf_res; 931 struct xhci_hw_root *phwr; 932 uint64_t addr; 933 uint32_t temp; 934 uint16_t i; 935 uint8_t event; 936 uint8_t j; 937 uint8_t k; 938 uint8_t t; 939 940 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 941 942 phwr = buf_res.buffer; 943 944 /* Receive any events */ 945 946 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 947 948 i = sc->sc_event_idx; 949 j = sc->sc_event_ccs; 950 t = 2; 951 952 while (1) { 953 954 temp = le32toh(phwr->hwr_events[i].dwTrb3); 955 956 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 957 958 if (j != k) 959 break; 960 961 event = XHCI_TRB_3_TYPE_GET(temp); 962 963 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 964 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 965 (long)le32toh(phwr->hwr_events[i].dwTrb2), 966 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 967 968 switch (event) { 969 case XHCI_TRB_EVENT_TRANSFER: 970 xhci_check_transfer(sc, &phwr->hwr_events[i]); 971 break; 972 case XHCI_TRB_EVENT_CMD_COMPLETE: 973 xhci_check_command(sc, &phwr->hwr_events[i]); 974 break; 975 default: 976 DPRINTF("Unhandled event = %u\n", event); 977 break; 978 } 979 980 i++; 981 982 if (i == XHCI_MAX_EVENTS) { 983 i = 0; 984 j ^= 1; 985 986 /* check for timeout */ 987 if (!--t) 988 break; 989 } 990 } 991 992 sc->sc_event_idx = i; 993 sc->sc_event_ccs = j; 994 995 /* 996 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 997 * latched. That means to activate the register we need to 998 * write both the low and high double word of the 64-bit 999 * register. 1000 */ 1001 1002 addr = (uint32_t)buf_res.physaddr; 1003 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1004 1005 /* try to clear busy bit */ 1006 addr |= XHCI_ERDP_LO_BUSY; 1007 1008 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1009 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1010 } 1011 1012 static usb_error_t 1013 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1014 uint16_t timeout_ms) 1015 { 1016 struct usb_page_search buf_res; 1017 struct xhci_hw_root *phwr; 1018 uint64_t addr; 1019 uint32_t temp; 1020 uint8_t i; 1021 uint8_t j; 1022 int err; 1023 1024 XHCI_CMD_ASSERT_LOCKED(sc); 1025 1026 /* get hardware root structure */ 1027 1028 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1029 1030 phwr = buf_res.buffer; 1031 1032 /* Queue command */ 1033 1034 USB_BUS_LOCK(&sc->sc_bus); 1035 1036 i = sc->sc_command_idx; 1037 j = sc->sc_command_ccs; 1038 1039 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1040 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1041 (long long)le64toh(trb->qwTrb0), 1042 (long)le32toh(trb->dwTrb2), 1043 (long)le32toh(trb->dwTrb3)); 1044 1045 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1046 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1047 1048 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1049 1050 temp = trb->dwTrb3; 1051 1052 if (j) 1053 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1054 else 1055 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1056 1057 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1058 1059 phwr->hwr_commands[i].dwTrb3 = temp; 1060 1061 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1062 1063 addr = buf_res.physaddr; 1064 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1065 1066 sc->sc_cmd_addr = htole64(addr); 1067 1068 i++; 1069 1070 if (i == (XHCI_MAX_COMMANDS - 1)) { 1071 1072 if (j) { 1073 temp = htole32(XHCI_TRB_3_TC_BIT | 1074 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1075 XHCI_TRB_3_CYCLE_BIT); 1076 } else { 1077 temp = htole32(XHCI_TRB_3_TC_BIT | 1078 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1079 } 1080 1081 phwr->hwr_commands[i].dwTrb3 = temp; 1082 1083 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1084 1085 i = 0; 1086 j ^= 1; 1087 } 1088 1089 sc->sc_command_idx = i; 1090 sc->sc_command_ccs = j; 1091 1092 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1093 1094 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1095 USB_MS_TO_TICKS(timeout_ms)); 1096 1097 if (err) { 1098 DPRINTFN(0, "Command timeout!\n"); 1099 err = USB_ERR_TIMEOUT; 1100 trb->dwTrb2 = 0; 1101 trb->dwTrb3 = 0; 1102 } else { 1103 temp = le32toh(sc->sc_cmd_result[0]); 1104 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1105 err = USB_ERR_IOERROR; 1106 1107 trb->dwTrb2 = sc->sc_cmd_result[0]; 1108 trb->dwTrb3 = sc->sc_cmd_result[1]; 1109 } 1110 1111 USB_BUS_UNLOCK(&sc->sc_bus); 1112 1113 return (err); 1114 } 1115 1116 #if 0 1117 static usb_error_t 1118 xhci_cmd_nop(struct xhci_softc *sc) 1119 { 1120 struct xhci_trb trb; 1121 uint32_t temp; 1122 1123 DPRINTF("\n"); 1124 1125 trb.qwTrb0 = 0; 1126 trb.dwTrb2 = 0; 1127 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1128 1129 trb.dwTrb3 = htole32(temp); 1130 1131 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1132 } 1133 #endif 1134 1135 static usb_error_t 1136 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1137 { 1138 struct xhci_trb trb; 1139 uint32_t temp; 1140 usb_error_t err; 1141 1142 DPRINTF("\n"); 1143 1144 trb.qwTrb0 = 0; 1145 trb.dwTrb2 = 0; 1146 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1147 1148 err = xhci_do_command(sc, &trb, 100 /* ms */); 1149 if (err) 1150 goto done; 1151 1152 temp = le32toh(trb.dwTrb3); 1153 1154 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1155 1156 done: 1157 return (err); 1158 } 1159 1160 static usb_error_t 1161 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1162 { 1163 struct xhci_trb trb; 1164 uint32_t temp; 1165 1166 DPRINTF("\n"); 1167 1168 trb.qwTrb0 = 0; 1169 trb.dwTrb2 = 0; 1170 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1171 XHCI_TRB_3_SLOT_SET(slot_id); 1172 1173 trb.dwTrb3 = htole32(temp); 1174 1175 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1176 } 1177 1178 static usb_error_t 1179 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1180 uint8_t bsr, uint8_t slot_id) 1181 { 1182 struct xhci_trb trb; 1183 uint32_t temp; 1184 1185 DPRINTF("\n"); 1186 1187 trb.qwTrb0 = htole64(input_ctx); 1188 trb.dwTrb2 = 0; 1189 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1190 XHCI_TRB_3_SLOT_SET(slot_id); 1191 1192 if (bsr) 1193 temp |= XHCI_TRB_3_BSR_BIT; 1194 1195 trb.dwTrb3 = htole32(temp); 1196 1197 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1198 } 1199 1200 static usb_error_t 1201 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1202 { 1203 struct usb_page_search buf_inp; 1204 struct usb_page_search buf_dev; 1205 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1206 struct xhci_hw_dev *hdev; 1207 struct xhci_dev_ctx *pdev; 1208 struct xhci_endpoint_ext *pepext; 1209 uint32_t temp; 1210 uint16_t mps; 1211 usb_error_t err; 1212 uint8_t index; 1213 1214 /* the root HUB case is not handled here */ 1215 if (udev->parent_hub == NULL) 1216 return (USB_ERR_INVAL); 1217 1218 index = udev->controller_slot_id; 1219 1220 hdev = &sc->sc_hw.devs[index]; 1221 1222 if (mtx != NULL) 1223 mtx_unlock(mtx); 1224 1225 XHCI_CMD_LOCK(sc); 1226 1227 switch (hdev->state) { 1228 case XHCI_ST_DEFAULT: 1229 case XHCI_ST_ENABLED: 1230 1231 hdev->state = XHCI_ST_ENABLED; 1232 1233 /* set configure mask to slot and EP0 */ 1234 xhci_configure_mask(udev, 3, 0); 1235 1236 /* configure input slot context structure */ 1237 err = xhci_configure_device(udev); 1238 1239 if (err != 0) { 1240 DPRINTF("Could not configure device\n"); 1241 break; 1242 } 1243 1244 /* configure input endpoint context structure */ 1245 switch (udev->speed) { 1246 case USB_SPEED_LOW: 1247 case USB_SPEED_FULL: 1248 mps = 8; 1249 break; 1250 case USB_SPEED_HIGH: 1251 mps = 64; 1252 break; 1253 default: 1254 mps = 512; 1255 break; 1256 } 1257 1258 pepext = xhci_get_endpoint_ext(udev, 1259 &udev->ctrl_ep_desc); 1260 err = xhci_configure_endpoint(udev, 1261 &udev->ctrl_ep_desc, pepext->physaddr, 1262 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1263 1264 if (err != 0) { 1265 DPRINTF("Could not configure default endpoint\n"); 1266 break; 1267 } 1268 1269 /* execute set address command */ 1270 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1271 1272 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1273 (address == 0), index); 1274 1275 if (err != 0) { 1276 DPRINTF("Could not set address " 1277 "for slot %u.\n", index); 1278 if (address != 0) 1279 break; 1280 } 1281 1282 /* update device address to new value */ 1283 1284 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1285 pdev = buf_dev.buffer; 1286 usb_pc_cpu_invalidate(&hdev->device_pc); 1287 1288 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1289 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1290 1291 /* update device state to new value */ 1292 1293 if (address != 0) 1294 hdev->state = XHCI_ST_ADDRESSED; 1295 else 1296 hdev->state = XHCI_ST_DEFAULT; 1297 break; 1298 1299 default: 1300 DPRINTF("Wrong state for set address.\n"); 1301 err = USB_ERR_IOERROR; 1302 break; 1303 } 1304 XHCI_CMD_UNLOCK(sc); 1305 1306 if (mtx != NULL) 1307 mtx_lock(mtx); 1308 1309 return (err); 1310 } 1311 1312 static usb_error_t 1313 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1314 uint8_t deconfigure, uint8_t slot_id) 1315 { 1316 struct xhci_trb trb; 1317 uint32_t temp; 1318 1319 DPRINTF("\n"); 1320 1321 trb.qwTrb0 = htole64(input_ctx); 1322 trb.dwTrb2 = 0; 1323 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1324 XHCI_TRB_3_SLOT_SET(slot_id); 1325 1326 if (deconfigure) 1327 temp |= XHCI_TRB_3_DCEP_BIT; 1328 1329 trb.dwTrb3 = htole32(temp); 1330 1331 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1332 } 1333 1334 static usb_error_t 1335 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1336 uint8_t slot_id) 1337 { 1338 struct xhci_trb trb; 1339 uint32_t temp; 1340 1341 DPRINTF("\n"); 1342 1343 trb.qwTrb0 = htole64(input_ctx); 1344 trb.dwTrb2 = 0; 1345 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1346 XHCI_TRB_3_SLOT_SET(slot_id); 1347 trb.dwTrb3 = htole32(temp); 1348 1349 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1350 } 1351 1352 static usb_error_t 1353 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1354 uint8_t ep_id, uint8_t slot_id) 1355 { 1356 struct xhci_trb trb; 1357 uint32_t temp; 1358 1359 DPRINTF("\n"); 1360 1361 trb.qwTrb0 = 0; 1362 trb.dwTrb2 = 0; 1363 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1364 XHCI_TRB_3_SLOT_SET(slot_id) | 1365 XHCI_TRB_3_EP_SET(ep_id); 1366 1367 if (preserve) 1368 temp |= XHCI_TRB_3_PRSV_BIT; 1369 1370 trb.dwTrb3 = htole32(temp); 1371 1372 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1373 } 1374 1375 static usb_error_t 1376 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1377 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1378 { 1379 struct xhci_trb trb; 1380 uint32_t temp; 1381 1382 DPRINTF("\n"); 1383 1384 trb.qwTrb0 = htole64(dequeue_ptr); 1385 1386 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1387 trb.dwTrb2 = htole32(temp); 1388 1389 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1390 XHCI_TRB_3_SLOT_SET(slot_id) | 1391 XHCI_TRB_3_EP_SET(ep_id); 1392 trb.dwTrb3 = htole32(temp); 1393 1394 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1395 } 1396 1397 static usb_error_t 1398 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1399 uint8_t ep_id, uint8_t slot_id) 1400 { 1401 struct xhci_trb trb; 1402 uint32_t temp; 1403 1404 DPRINTF("\n"); 1405 1406 trb.qwTrb0 = 0; 1407 trb.dwTrb2 = 0; 1408 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1409 XHCI_TRB_3_SLOT_SET(slot_id) | 1410 XHCI_TRB_3_EP_SET(ep_id); 1411 1412 if (suspend) 1413 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1414 1415 trb.dwTrb3 = htole32(temp); 1416 1417 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1418 } 1419 1420 static usb_error_t 1421 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1422 { 1423 struct xhci_trb trb; 1424 uint32_t temp; 1425 1426 DPRINTF("\n"); 1427 1428 trb.qwTrb0 = 0; 1429 trb.dwTrb2 = 0; 1430 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1431 XHCI_TRB_3_SLOT_SET(slot_id); 1432 1433 trb.dwTrb3 = htole32(temp); 1434 1435 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1436 } 1437 1438 /*------------------------------------------------------------------------* 1439 * xhci_interrupt - XHCI interrupt handler 1440 *------------------------------------------------------------------------*/ 1441 void 1442 xhci_interrupt(struct xhci_softc *sc) 1443 { 1444 uint32_t status; 1445 uint32_t iman; 1446 1447 USB_BUS_LOCK(&sc->sc_bus); 1448 1449 status = XREAD4(sc, oper, XHCI_USBSTS); 1450 if (status == 0) 1451 goto done; 1452 1453 /* acknowledge interrupts */ 1454 1455 XWRITE4(sc, oper, XHCI_USBSTS, status); 1456 1457 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1458 1459 if (status & XHCI_STS_EINT) { 1460 1461 /* acknowledge pending event */ 1462 iman = XREAD4(sc, runt, XHCI_IMAN(0)); 1463 1464 /* reset interrupt */ 1465 XWRITE4(sc, runt, XHCI_IMAN(0), iman); 1466 1467 DPRINTFN(16, "real interrupt (iman=0x%08x)\n", iman); 1468 1469 /* check for event(s) */ 1470 xhci_interrupt_poll(sc); 1471 } 1472 1473 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1474 XHCI_STS_HSE | XHCI_STS_HCE)) { 1475 1476 if (status & XHCI_STS_PCD) { 1477 xhci_root_intr(sc); 1478 } 1479 1480 if (status & XHCI_STS_HCH) { 1481 printf("%s: host controller halted\n", 1482 __FUNCTION__); 1483 } 1484 1485 if (status & XHCI_STS_HSE) { 1486 printf("%s: host system error\n", 1487 __FUNCTION__); 1488 } 1489 1490 if (status & XHCI_STS_HCE) { 1491 printf("%s: host controller error\n", 1492 __FUNCTION__); 1493 } 1494 } 1495 done: 1496 USB_BUS_UNLOCK(&sc->sc_bus); 1497 } 1498 1499 /*------------------------------------------------------------------------* 1500 * xhci_timeout - XHCI timeout handler 1501 *------------------------------------------------------------------------*/ 1502 static void 1503 xhci_timeout(void *arg) 1504 { 1505 struct usb_xfer *xfer = arg; 1506 1507 DPRINTF("xfer=%p\n", xfer); 1508 1509 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1510 1511 /* transfer is transferred */ 1512 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1513 } 1514 1515 static void 1516 xhci_do_poll(struct usb_bus *bus) 1517 { 1518 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1519 1520 USB_BUS_LOCK(&sc->sc_bus); 1521 xhci_interrupt_poll(sc); 1522 USB_BUS_UNLOCK(&sc->sc_bus); 1523 } 1524 1525 static void 1526 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1527 { 1528 struct usb_page_search buf_res; 1529 struct xhci_td *td; 1530 struct xhci_td *td_next; 1531 struct xhci_td *td_alt_next; 1532 uint32_t buf_offset; 1533 uint32_t average; 1534 uint32_t len_old; 1535 uint32_t dword; 1536 uint8_t shortpkt_old; 1537 uint8_t precompute; 1538 uint8_t x; 1539 1540 td_alt_next = NULL; 1541 buf_offset = 0; 1542 shortpkt_old = temp->shortpkt; 1543 len_old = temp->len; 1544 precompute = 1; 1545 1546 restart: 1547 1548 td = temp->td; 1549 td_next = temp->td_next; 1550 1551 while (1) { 1552 1553 if (temp->len == 0) { 1554 1555 if (temp->shortpkt) 1556 break; 1557 1558 /* send a Zero Length Packet, ZLP, last */ 1559 1560 temp->shortpkt = 1; 1561 average = 0; 1562 1563 } else { 1564 1565 average = temp->average; 1566 1567 if (temp->len < average) { 1568 if (temp->len % temp->max_packet_size) { 1569 temp->shortpkt = 1; 1570 } 1571 average = temp->len; 1572 } 1573 } 1574 1575 if (td_next == NULL) 1576 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1577 1578 /* get next TD */ 1579 1580 td = td_next; 1581 td_next = td->obj_next; 1582 1583 /* check if we are pre-computing */ 1584 1585 if (precompute) { 1586 1587 /* update remaining length */ 1588 1589 temp->len -= average; 1590 1591 continue; 1592 } 1593 /* fill out current TD */ 1594 1595 td->len = average; 1596 td->remainder = 0; 1597 td->status = 0; 1598 1599 /* update remaining length */ 1600 1601 temp->len -= average; 1602 1603 /* reset TRB index */ 1604 1605 x = 0; 1606 1607 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1608 /* immediate data */ 1609 1610 if (average > 8) 1611 average = 8; 1612 1613 td->td_trb[0].qwTrb0 = 0; 1614 1615 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1616 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1617 average); 1618 1619 dword = XHCI_TRB_2_BYTES_SET(8) | 1620 XHCI_TRB_2_TDSZ_SET(0) | 1621 XHCI_TRB_2_IRQ_SET(0); 1622 1623 td->td_trb[0].dwTrb2 = htole32(dword); 1624 1625 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1626 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1627 1628 /* check wLength */ 1629 if (td->td_trb[0].qwTrb0 & 1630 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1631 if (td->td_trb[0].qwTrb0 & htole64(1)) 1632 dword |= XHCI_TRB_3_TRT_IN; 1633 else 1634 dword |= XHCI_TRB_3_TRT_OUT; 1635 } 1636 1637 td->td_trb[0].dwTrb3 = htole32(dword); 1638 #ifdef USB_DEBUG 1639 xhci_dump_trb(&td->td_trb[x]); 1640 #endif 1641 x++; 1642 1643 } else do { 1644 1645 uint32_t npkt; 1646 1647 /* fill out buffer pointers */ 1648 1649 if (average == 0) { 1650 npkt = 1; 1651 memset(&buf_res, 0, sizeof(buf_res)); 1652 } else { 1653 usbd_get_page(temp->pc, temp->offset + 1654 buf_offset, &buf_res); 1655 1656 /* get length to end of page */ 1657 if (buf_res.length > average) 1658 buf_res.length = average; 1659 1660 /* check for maximum length */ 1661 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1662 buf_res.length = XHCI_TD_PAGE_SIZE; 1663 1664 /* setup npkt */ 1665 npkt = (average + temp->max_packet_size - 1) / 1666 temp->max_packet_size; 1667 1668 if (npkt > 31) 1669 npkt = 31; 1670 } 1671 1672 /* fill out TRB's */ 1673 td->td_trb[x].qwTrb0 = 1674 htole64((uint64_t)buf_res.physaddr); 1675 1676 dword = 1677 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1678 XHCI_TRB_2_TDSZ_SET(npkt) | 1679 XHCI_TRB_2_IRQ_SET(0); 1680 1681 td->td_trb[x].dwTrb2 = htole32(dword); 1682 1683 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1684 XHCI_TRB_3_TYPE_SET(temp->trb_type) | 1685 (temp->do_isoc_sync ? 1686 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) : 1687 XHCI_TRB_3_ISO_SIA_BIT) | 1688 XHCI_TRB_3_TBC_SET(temp->tbc) | 1689 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1690 1691 temp->do_isoc_sync = 0; 1692 1693 if (temp->direction == UE_DIR_IN) { 1694 dword |= XHCI_TRB_3_DIR_IN; 1695 1696 /* 1697 * NOTE: Only the SETUP stage should 1698 * use the IDT bit. Else transactions 1699 * can be sent using the wrong data 1700 * toggle value. 1701 */ 1702 if (temp->trb_type != 1703 XHCI_TRB_TYPE_SETUP_STAGE && 1704 temp->trb_type != 1705 XHCI_TRB_TYPE_STATUS_STAGE) 1706 dword |= XHCI_TRB_3_ISP_BIT; 1707 } 1708 1709 td->td_trb[x].dwTrb3 = htole32(dword); 1710 1711 average -= buf_res.length; 1712 buf_offset += buf_res.length; 1713 #ifdef USB_DEBUG 1714 xhci_dump_trb(&td->td_trb[x]); 1715 #endif 1716 x++; 1717 1718 } while (average != 0); 1719 1720 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1721 1722 /* store number of data TRB's */ 1723 1724 td->ntrb = x; 1725 1726 DPRINTF("NTRB=%u\n", x); 1727 1728 /* fill out link TRB */ 1729 1730 if (td_next != NULL) { 1731 /* link the current TD with the next one */ 1732 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1733 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1734 } else { 1735 /* this field will get updated later */ 1736 DPRINTF("NOLINK\n"); 1737 } 1738 1739 dword = XHCI_TRB_2_IRQ_SET(0); 1740 1741 td->td_trb[x].dwTrb2 = htole32(dword); 1742 1743 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1744 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT; 1745 1746 td->td_trb[x].dwTrb3 = htole32(dword); 1747 1748 td->alt_next = td_alt_next; 1749 #ifdef USB_DEBUG 1750 xhci_dump_trb(&td->td_trb[x]); 1751 #endif 1752 usb_pc_cpu_flush(td->page_cache); 1753 } 1754 1755 if (precompute) { 1756 precompute = 0; 1757 1758 /* setup alt next pointer, if any */ 1759 if (temp->last_frame) { 1760 td_alt_next = NULL; 1761 } else { 1762 /* we use this field internally */ 1763 td_alt_next = td_next; 1764 } 1765 1766 /* restore */ 1767 temp->shortpkt = shortpkt_old; 1768 temp->len = len_old; 1769 goto restart; 1770 } 1771 1772 /* remove cycle bit from first if we are stepping the TRBs */ 1773 if (temp->step_td) 1774 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1775 1776 /* remove chain bit because this is the last TRB in the chain */ 1777 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1778 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1779 1780 usb_pc_cpu_flush(td->page_cache); 1781 1782 temp->td = td; 1783 temp->td_next = td_next; 1784 } 1785 1786 static void 1787 xhci_setup_generic_chain(struct usb_xfer *xfer) 1788 { 1789 struct xhci_std_temp temp; 1790 struct xhci_td *td; 1791 uint32_t x; 1792 uint32_t y; 1793 uint8_t mult; 1794 1795 temp.do_isoc_sync = 0; 1796 temp.step_td = 0; 1797 temp.tbc = 0; 1798 temp.tlbpc = 0; 1799 temp.average = xfer->max_hc_frame_size; 1800 temp.max_packet_size = xfer->max_packet_size; 1801 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1802 temp.pc = NULL; 1803 temp.last_frame = 0; 1804 temp.offset = 0; 1805 temp.multishort = xfer->flags_int.isochronous_xfr || 1806 xfer->flags_int.control_xfr || 1807 xfer->flags_int.short_frames_ok; 1808 1809 /* toggle the DMA set we are using */ 1810 xfer->flags_int.curr_dma_set ^= 1; 1811 1812 /* get next DMA set */ 1813 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1814 1815 temp.td = NULL; 1816 temp.td_next = td; 1817 1818 xfer->td_transfer_first = td; 1819 xfer->td_transfer_cache = td; 1820 1821 if (xfer->flags_int.isochronous_xfr) { 1822 uint8_t shift; 1823 1824 /* compute multiplier for ISOCHRONOUS transfers */ 1825 mult = xfer->endpoint->ecomp ? 1826 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 1827 : 0; 1828 /* check for USB 2.0 multiplier */ 1829 if (mult == 0) { 1830 mult = (xfer->endpoint->edesc-> 1831 wMaxPacketSize[1] >> 3) & 3; 1832 } 1833 /* range check */ 1834 if (mult > 2) 1835 mult = 3; 1836 else 1837 mult++; 1838 1839 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 1840 1841 DPRINTF("MFINDEX=0x%08x\n", x); 1842 1843 switch (usbd_get_speed(xfer->xroot->udev)) { 1844 case USB_SPEED_FULL: 1845 shift = 3; 1846 temp.isoc_delta = 8; /* 1ms */ 1847 x += temp.isoc_delta - 1; 1848 x &= ~(temp.isoc_delta - 1); 1849 break; 1850 default: 1851 shift = usbd_xfer_get_fps_shift(xfer); 1852 temp.isoc_delta = 1U << shift; 1853 x += temp.isoc_delta - 1; 1854 x &= ~(temp.isoc_delta - 1); 1855 /* simple frame load balancing */ 1856 x += xfer->endpoint->usb_uframe; 1857 break; 1858 } 1859 1860 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 1861 1862 if ((xfer->endpoint->is_synced == 0) || 1863 (y < (xfer->nframes << shift)) || 1864 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 1865 /* 1866 * If there is data underflow or the pipe 1867 * queue is empty we schedule the transfer a 1868 * few frames ahead of the current frame 1869 * position. Else two isochronous transfers 1870 * might overlap. 1871 */ 1872 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 1873 xfer->endpoint->is_synced = 1; 1874 temp.do_isoc_sync = 1; 1875 1876 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1877 } 1878 1879 /* compute isochronous completion time */ 1880 1881 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 1882 1883 xfer->isoc_time_complete = 1884 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 1885 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 1886 1887 x = 0; 1888 temp.isoc_frame = xfer->endpoint->isoc_next; 1889 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 1890 1891 xfer->endpoint->isoc_next += xfer->nframes << shift; 1892 1893 } else if (xfer->flags_int.control_xfr) { 1894 1895 /* check if we should prepend a setup message */ 1896 1897 if (xfer->flags_int.control_hdr) { 1898 1899 temp.len = xfer->frlengths[0]; 1900 temp.pc = xfer->frbuffers + 0; 1901 temp.shortpkt = temp.len ? 1 : 0; 1902 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 1903 temp.direction = 0; 1904 1905 /* check for last frame */ 1906 if (xfer->nframes == 1) { 1907 /* no STATUS stage yet, SETUP is last */ 1908 if (xfer->flags_int.control_act) 1909 temp.last_frame = 1; 1910 } 1911 1912 xhci_setup_generic_chain_sub(&temp); 1913 } 1914 x = 1; 1915 mult = 1; 1916 temp.isoc_delta = 0; 1917 temp.isoc_frame = 0; 1918 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 1919 } else { 1920 x = 0; 1921 mult = 1; 1922 temp.isoc_delta = 0; 1923 temp.isoc_frame = 0; 1924 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 1925 } 1926 1927 if (x != xfer->nframes) { 1928 /* setup page_cache pointer */ 1929 temp.pc = xfer->frbuffers + x; 1930 /* set endpoint direction */ 1931 temp.direction = UE_GET_DIR(xfer->endpointno); 1932 } 1933 1934 while (x != xfer->nframes) { 1935 1936 /* DATA0 / DATA1 message */ 1937 1938 temp.len = xfer->frlengths[x]; 1939 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 1940 x != 0 && temp.multishort == 0); 1941 1942 x++; 1943 1944 if (x == xfer->nframes) { 1945 if (xfer->flags_int.control_xfr) { 1946 /* no STATUS stage yet, DATA is last */ 1947 if (xfer->flags_int.control_act) 1948 temp.last_frame = 1; 1949 } else { 1950 temp.last_frame = 1; 1951 } 1952 } 1953 if (temp.len == 0) { 1954 1955 /* make sure that we send an USB packet */ 1956 1957 temp.shortpkt = 0; 1958 1959 temp.tbc = 0; 1960 temp.tlbpc = mult - 1; 1961 1962 } else if (xfer->flags_int.isochronous_xfr) { 1963 1964 uint8_t tdpc; 1965 1966 /* 1967 * Isochronous transfers don't have short 1968 * packet termination: 1969 */ 1970 1971 temp.shortpkt = 1; 1972 1973 /* isochronous transfers have a transfer limit */ 1974 1975 if (temp.len > xfer->max_frame_size) 1976 temp.len = xfer->max_frame_size; 1977 1978 /* compute TD packet count */ 1979 tdpc = (temp.len + xfer->max_packet_size - 1) / 1980 xfer->max_packet_size; 1981 1982 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 1983 temp.tlbpc = (tdpc % mult); 1984 1985 if (temp.tlbpc == 0) 1986 temp.tlbpc = mult - 1; 1987 else 1988 temp.tlbpc--; 1989 } else { 1990 1991 /* regular data transfer */ 1992 1993 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 1994 } 1995 1996 xhci_setup_generic_chain_sub(&temp); 1997 1998 if (xfer->flags_int.isochronous_xfr) { 1999 temp.offset += xfer->frlengths[x - 1]; 2000 temp.isoc_frame += temp.isoc_delta; 2001 } else { 2002 /* get next Page Cache pointer */ 2003 temp.pc = xfer->frbuffers + x; 2004 } 2005 } 2006 2007 /* check if we should append a status stage */ 2008 2009 if (xfer->flags_int.control_xfr && 2010 !xfer->flags_int.control_act) { 2011 2012 /* 2013 * Send a DATA1 message and invert the current 2014 * endpoint direction. 2015 */ 2016 temp.step_td = (xfer->nframes != 0); 2017 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2018 temp.len = 0; 2019 temp.pc = NULL; 2020 temp.shortpkt = 0; 2021 temp.last_frame = 1; 2022 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2023 2024 xhci_setup_generic_chain_sub(&temp); 2025 } 2026 2027 td = temp.td; 2028 2029 /* must have at least one frame! */ 2030 2031 xfer->td_transfer_last = td; 2032 2033 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2034 } 2035 2036 static void 2037 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2038 { 2039 struct usb_page_search buf_res; 2040 struct xhci_dev_ctx_addr *pdctxa; 2041 2042 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2043 2044 pdctxa = buf_res.buffer; 2045 2046 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2047 2048 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2049 2050 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2051 } 2052 2053 static usb_error_t 2054 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2055 { 2056 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2057 struct usb_page_search buf_inp; 2058 struct xhci_input_dev_ctx *pinp; 2059 uint32_t temp; 2060 uint8_t index; 2061 uint8_t x; 2062 2063 index = udev->controller_slot_id; 2064 2065 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2066 2067 pinp = buf_inp.buffer; 2068 2069 if (drop) { 2070 mask &= XHCI_INCTX_NON_CTRL_MASK; 2071 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2072 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2073 } else { 2074 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2075 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2076 2077 /* find most significant set bit */ 2078 for (x = 31; x != 1; x--) { 2079 if (mask & (1 << x)) 2080 break; 2081 } 2082 2083 /* adjust */ 2084 x--; 2085 2086 /* figure out maximum */ 2087 if (x > sc->sc_hw.devs[index].context_num) { 2088 sc->sc_hw.devs[index].context_num = x; 2089 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2090 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2091 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2092 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2093 } 2094 } 2095 return (0); 2096 } 2097 2098 static usb_error_t 2099 xhci_configure_endpoint(struct usb_device *udev, 2100 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr, 2101 uint16_t interval, uint8_t max_packet_count, uint8_t mult, 2102 uint8_t fps_shift, uint16_t max_packet_size, 2103 uint16_t max_frame_size, uint8_t ep_mode) 2104 { 2105 struct usb_page_search buf_inp; 2106 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2107 struct xhci_input_dev_ctx *pinp; 2108 uint32_t temp; 2109 uint8_t index; 2110 uint8_t epno; 2111 uint8_t type; 2112 2113 index = udev->controller_slot_id; 2114 2115 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2116 2117 pinp = buf_inp.buffer; 2118 2119 epno = edesc->bEndpointAddress; 2120 type = edesc->bmAttributes & UE_XFERTYPE; 2121 2122 if (type == UE_CONTROL) 2123 epno |= UE_DIR_IN; 2124 2125 epno = XHCI_EPNO2EPID(epno); 2126 2127 if (epno == 0) 2128 return (USB_ERR_NO_PIPE); /* invalid */ 2129 2130 if (max_packet_count == 0) 2131 return (USB_ERR_BAD_BUFSIZE); 2132 2133 max_packet_count--; 2134 2135 if (mult == 0) 2136 return (USB_ERR_BAD_BUFSIZE); 2137 2138 if (ep_mode == USB_EP_MODE_STREAMS) { 2139 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2140 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2141 XHCI_EPCTX_0_LSA_SET(1); 2142 2143 ring_addr += sizeof(struct xhci_trb) * 2144 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2145 } else { 2146 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2147 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2148 XHCI_EPCTX_0_LSA_SET(0); 2149 2150 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2151 } 2152 2153 switch (udev->speed) { 2154 case USB_SPEED_FULL: 2155 case USB_SPEED_LOW: 2156 /* 1ms -> 125us */ 2157 fps_shift += 3; 2158 break; 2159 default: 2160 break; 2161 } 2162 2163 switch (type) { 2164 case UE_INTERRUPT: 2165 if (fps_shift > 3) 2166 fps_shift--; 2167 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2168 break; 2169 case UE_ISOCHRONOUS: 2170 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2171 2172 switch (udev->speed) { 2173 case USB_SPEED_SUPER: 2174 if (mult > 3) 2175 mult = 3; 2176 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2177 max_packet_count /= mult; 2178 break; 2179 default: 2180 break; 2181 } 2182 break; 2183 default: 2184 break; 2185 } 2186 2187 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2188 2189 temp = 2190 XHCI_EPCTX_1_HID_SET(0) | 2191 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2192 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2193 2194 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2195 if (type != UE_ISOCHRONOUS) 2196 temp |= XHCI_EPCTX_1_CERR_SET(3); 2197 } 2198 2199 switch (type) { 2200 case UE_CONTROL: 2201 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2202 break; 2203 case UE_ISOCHRONOUS: 2204 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2205 break; 2206 case UE_BULK: 2207 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2208 break; 2209 default: 2210 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2211 break; 2212 } 2213 2214 /* check for IN direction */ 2215 if (epno & 1) 2216 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2217 2218 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2219 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2220 2221 switch (edesc->bmAttributes & UE_XFERTYPE) { 2222 case UE_INTERRUPT: 2223 case UE_ISOCHRONOUS: 2224 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2225 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2226 max_frame_size)); 2227 break; 2228 case UE_CONTROL: 2229 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2230 break; 2231 default: 2232 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2233 break; 2234 } 2235 2236 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2237 2238 #ifdef USB_DEBUG 2239 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2240 #endif 2241 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2242 2243 return (0); /* success */ 2244 } 2245 2246 static usb_error_t 2247 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2248 { 2249 struct xhci_endpoint_ext *pepext; 2250 struct usb_endpoint_ss_comp_descriptor *ecomp; 2251 usb_stream_t x; 2252 2253 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2254 xfer->endpoint->edesc); 2255 2256 ecomp = xfer->endpoint->ecomp; 2257 2258 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2259 uint64_t temp; 2260 2261 /* halt any transfers */ 2262 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2263 2264 /* compute start of TRB ring for stream "x" */ 2265 temp = pepext->physaddr + 2266 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2267 XHCI_SCTX_0_SCT_SEC_TR_RING; 2268 2269 /* make tree structure */ 2270 pepext->trb[(XHCI_MAX_TRANSFERS * 2271 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2272 2273 /* reserved fields */ 2274 pepext->trb[(XHCI_MAX_TRANSFERS * 2275 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2276 pepext->trb[(XHCI_MAX_TRANSFERS * 2277 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2278 } 2279 usb_pc_cpu_flush(pepext->page_cache); 2280 2281 return (xhci_configure_endpoint(xfer->xroot->udev, 2282 xfer->endpoint->edesc, pepext->physaddr, 2283 xfer->interval, xfer->max_packet_count, 2284 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2285 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2286 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2287 } 2288 2289 static usb_error_t 2290 xhci_configure_device(struct usb_device *udev) 2291 { 2292 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2293 struct usb_page_search buf_inp; 2294 struct usb_page_cache *pcinp; 2295 struct xhci_input_dev_ctx *pinp; 2296 struct usb_device *hubdev; 2297 uint32_t temp; 2298 uint32_t route; 2299 uint32_t rh_port; 2300 uint8_t is_hub; 2301 uint8_t index; 2302 uint8_t depth; 2303 2304 index = udev->controller_slot_id; 2305 2306 DPRINTF("index=%u\n", index); 2307 2308 pcinp = &sc->sc_hw.devs[index].input_pc; 2309 2310 usbd_get_page(pcinp, 0, &buf_inp); 2311 2312 pinp = buf_inp.buffer; 2313 2314 rh_port = 0; 2315 route = 0; 2316 2317 /* figure out route string and root HUB port number */ 2318 2319 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2320 2321 if (hubdev->parent_hub == NULL) 2322 break; 2323 2324 depth = hubdev->parent_hub->depth; 2325 2326 /* 2327 * NOTE: HS/FS/LS devices and the SS root HUB can have 2328 * more than 15 ports 2329 */ 2330 2331 rh_port = hubdev->port_no; 2332 2333 if (depth == 0) 2334 break; 2335 2336 if (rh_port > 15) 2337 rh_port = 15; 2338 2339 if (depth < 6) 2340 route |= rh_port << (4 * (depth - 1)); 2341 } 2342 2343 DPRINTF("Route=0x%08x\n", route); 2344 2345 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2346 XHCI_SCTX_0_CTX_NUM_SET( 2347 sc->sc_hw.devs[index].context_num + 1); 2348 2349 switch (udev->speed) { 2350 case USB_SPEED_LOW: 2351 temp |= XHCI_SCTX_0_SPEED_SET(2); 2352 if (udev->parent_hs_hub != NULL && 2353 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2354 UDPROTO_HSHUBMTT) { 2355 DPRINTF("Device inherits MTT\n"); 2356 temp |= XHCI_SCTX_0_MTT_SET(1); 2357 } 2358 break; 2359 case USB_SPEED_HIGH: 2360 temp |= XHCI_SCTX_0_SPEED_SET(3); 2361 if (sc->sc_hw.devs[index].nports != 0 && 2362 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2363 DPRINTF("HUB supports MTT\n"); 2364 temp |= XHCI_SCTX_0_MTT_SET(1); 2365 } 2366 break; 2367 case USB_SPEED_FULL: 2368 temp |= XHCI_SCTX_0_SPEED_SET(1); 2369 if (udev->parent_hs_hub != NULL && 2370 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2371 UDPROTO_HSHUBMTT) { 2372 DPRINTF("Device inherits MTT\n"); 2373 temp |= XHCI_SCTX_0_MTT_SET(1); 2374 } 2375 break; 2376 default: 2377 temp |= XHCI_SCTX_0_SPEED_SET(4); 2378 break; 2379 } 2380 2381 is_hub = sc->sc_hw.devs[index].nports != 0 && 2382 (udev->speed == USB_SPEED_SUPER || 2383 udev->speed == USB_SPEED_HIGH); 2384 2385 if (is_hub) 2386 temp |= XHCI_SCTX_0_HUB_SET(1); 2387 2388 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2389 2390 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2391 2392 if (is_hub) { 2393 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2394 sc->sc_hw.devs[index].nports); 2395 } 2396 2397 switch (udev->speed) { 2398 case USB_SPEED_SUPER: 2399 switch (sc->sc_hw.devs[index].state) { 2400 case XHCI_ST_ADDRESSED: 2401 case XHCI_ST_CONFIGURED: 2402 /* enable power save */ 2403 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2404 break; 2405 default: 2406 /* disable power save */ 2407 break; 2408 } 2409 break; 2410 default: 2411 break; 2412 } 2413 2414 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2415 2416 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2417 2418 if (is_hub) { 2419 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2420 sc->sc_hw.devs[index].tt); 2421 } 2422 2423 hubdev = udev->parent_hs_hub; 2424 2425 /* check if we should activate the transaction translator */ 2426 switch (udev->speed) { 2427 case USB_SPEED_FULL: 2428 case USB_SPEED_LOW: 2429 if (hubdev != NULL) { 2430 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2431 hubdev->controller_slot_id); 2432 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2433 udev->hs_port_no); 2434 } 2435 break; 2436 default: 2437 break; 2438 } 2439 2440 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2441 2442 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) | 2443 XHCI_SCTX_3_SLOT_STATE_SET(0); 2444 2445 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2446 2447 #ifdef USB_DEBUG 2448 xhci_dump_device(sc, &pinp->ctx_slot); 2449 #endif 2450 usb_pc_cpu_flush(pcinp); 2451 2452 return (0); /* success */ 2453 } 2454 2455 static usb_error_t 2456 xhci_alloc_device_ext(struct usb_device *udev) 2457 { 2458 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2459 struct usb_page_search buf_dev; 2460 struct usb_page_search buf_ep; 2461 struct xhci_trb *trb; 2462 struct usb_page_cache *pc; 2463 struct usb_page *pg; 2464 uint64_t addr; 2465 uint8_t index; 2466 uint8_t i; 2467 2468 index = udev->controller_slot_id; 2469 2470 pc = &sc->sc_hw.devs[index].device_pc; 2471 pg = &sc->sc_hw.devs[index].device_pg; 2472 2473 /* need to initialize the page cache */ 2474 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2475 2476 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2477 (2 * sizeof(struct xhci_dev_ctx)) : 2478 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2479 goto error; 2480 2481 usbd_get_page(pc, 0, &buf_dev); 2482 2483 pc = &sc->sc_hw.devs[index].input_pc; 2484 pg = &sc->sc_hw.devs[index].input_pg; 2485 2486 /* need to initialize the page cache */ 2487 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2488 2489 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2490 (2 * sizeof(struct xhci_input_dev_ctx)) : 2491 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2492 goto error; 2493 } 2494 2495 pc = &sc->sc_hw.devs[index].endpoint_pc; 2496 pg = &sc->sc_hw.devs[index].endpoint_pg; 2497 2498 /* need to initialize the page cache */ 2499 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2500 2501 if (usb_pc_alloc_mem(pc, pg, 2502 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) { 2503 goto error; 2504 } 2505 2506 /* initialise all endpoint LINK TRBs */ 2507 2508 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2509 2510 /* lookup endpoint TRB ring */ 2511 usbd_get_page(pc, (uintptr_t)& 2512 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2513 2514 /* get TRB pointer */ 2515 trb = buf_ep.buffer; 2516 trb += XHCI_MAX_TRANSFERS - 1; 2517 2518 /* get TRB start address */ 2519 addr = buf_ep.physaddr; 2520 2521 /* create LINK TRB */ 2522 trb->qwTrb0 = htole64(addr); 2523 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2524 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2525 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2526 } 2527 2528 usb_pc_cpu_flush(pc); 2529 2530 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2531 2532 return (0); 2533 2534 error: 2535 xhci_free_device_ext(udev); 2536 2537 return (USB_ERR_NOMEM); 2538 } 2539 2540 static void 2541 xhci_free_device_ext(struct usb_device *udev) 2542 { 2543 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2544 uint8_t index; 2545 2546 index = udev->controller_slot_id; 2547 xhci_set_slot_pointer(sc, index, 0); 2548 2549 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2550 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2551 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2552 } 2553 2554 static struct xhci_endpoint_ext * 2555 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2556 { 2557 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2558 struct xhci_endpoint_ext *pepext; 2559 struct usb_page_cache *pc; 2560 struct usb_page_search buf_ep; 2561 uint8_t epno; 2562 uint8_t index; 2563 2564 epno = edesc->bEndpointAddress; 2565 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2566 epno |= UE_DIR_IN; 2567 2568 epno = XHCI_EPNO2EPID(epno); 2569 2570 index = udev->controller_slot_id; 2571 2572 pc = &sc->sc_hw.devs[index].endpoint_pc; 2573 2574 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2575 trb[epno][0], &buf_ep); 2576 2577 pepext = &sc->sc_hw.devs[index].endp[epno]; 2578 pepext->page_cache = pc; 2579 pepext->trb = buf_ep.buffer; 2580 pepext->physaddr = buf_ep.physaddr; 2581 2582 return (pepext); 2583 } 2584 2585 static void 2586 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2587 { 2588 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2589 uint8_t epno; 2590 uint8_t index; 2591 2592 epno = xfer->endpointno; 2593 if (xfer->flags_int.control_xfr) 2594 epno |= UE_DIR_IN; 2595 2596 epno = XHCI_EPNO2EPID(epno); 2597 index = xfer->xroot->udev->controller_slot_id; 2598 2599 if (xfer->xroot->udev->flags.self_suspended == 0) { 2600 XWRITE4(sc, door, XHCI_DOORBELL(index), 2601 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2602 } 2603 } 2604 2605 static void 2606 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2607 { 2608 struct xhci_endpoint_ext *pepext; 2609 2610 if (xfer->flags_int.bandwidth_reclaimed) { 2611 xfer->flags_int.bandwidth_reclaimed = 0; 2612 2613 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2614 xfer->endpoint->edesc); 2615 2616 pepext->trb_used[xfer->stream_id]--; 2617 2618 pepext->xfer[xfer->qh_pos] = NULL; 2619 2620 if (error && pepext->trb_running != 0) { 2621 pepext->trb_halted = 1; 2622 pepext->trb_running = 0; 2623 } 2624 } 2625 } 2626 2627 static usb_error_t 2628 xhci_transfer_insert(struct usb_xfer *xfer) 2629 { 2630 struct xhci_td *td_first; 2631 struct xhci_td *td_last; 2632 struct xhci_endpoint_ext *pepext; 2633 uint64_t addr; 2634 usb_stream_t id; 2635 uint8_t i; 2636 uint8_t inext; 2637 uint8_t trb_limit; 2638 2639 DPRINTFN(8, "\n"); 2640 2641 id = xfer->stream_id; 2642 2643 /* check if already inserted */ 2644 if (xfer->flags_int.bandwidth_reclaimed) { 2645 DPRINTFN(8, "Already in schedule\n"); 2646 return (0); 2647 } 2648 2649 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2650 xfer->endpoint->edesc); 2651 2652 td_first = xfer->td_transfer_first; 2653 td_last = xfer->td_transfer_last; 2654 addr = pepext->physaddr; 2655 2656 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2657 case UE_CONTROL: 2658 case UE_INTERRUPT: 2659 /* single buffered */ 2660 trb_limit = 1; 2661 break; 2662 default: 2663 /* multi buffered */ 2664 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2665 break; 2666 } 2667 2668 if (pepext->trb_used[id] >= trb_limit) { 2669 DPRINTFN(8, "Too many TDs queued.\n"); 2670 return (USB_ERR_NOMEM); 2671 } 2672 2673 /* check for stopped condition, after putting transfer on interrupt queue */ 2674 if (pepext->trb_running == 0) { 2675 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2676 2677 DPRINTFN(8, "Not running\n"); 2678 2679 /* start configuration */ 2680 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2681 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2682 return (0); 2683 } 2684 2685 pepext->trb_used[id]++; 2686 2687 /* get current TRB index */ 2688 i = pepext->trb_index[id]; 2689 2690 /* get next TRB index */ 2691 inext = (i + 1); 2692 2693 /* the last entry of the ring is a hardcoded link TRB */ 2694 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2695 inext = 0; 2696 2697 /* offset for stream */ 2698 i += id * XHCI_MAX_TRANSFERS; 2699 inext += id * XHCI_MAX_TRANSFERS; 2700 2701 /* compute terminating return address */ 2702 addr += (inext * sizeof(struct xhci_trb)); 2703 2704 /* update next pointer of last link TRB */ 2705 td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr); 2706 td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2707 td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2708 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2709 2710 #ifdef USB_DEBUG 2711 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2712 #endif 2713 usb_pc_cpu_flush(td_last->page_cache); 2714 2715 /* write ahead chain end marker */ 2716 2717 pepext->trb[inext].qwTrb0 = 0; 2718 pepext->trb[inext].dwTrb2 = 0; 2719 pepext->trb[inext].dwTrb3 = 0; 2720 2721 /* update next pointer of link TRB */ 2722 2723 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2724 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2725 2726 #ifdef USB_DEBUG 2727 xhci_dump_trb(&pepext->trb[i]); 2728 #endif 2729 usb_pc_cpu_flush(pepext->page_cache); 2730 2731 /* toggle cycle bit which activates the transfer chain */ 2732 2733 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2734 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2735 2736 usb_pc_cpu_flush(pepext->page_cache); 2737 2738 DPRINTF("qh_pos = %u\n", i); 2739 2740 pepext->xfer[i] = xfer; 2741 2742 xfer->qh_pos = i; 2743 2744 xfer->flags_int.bandwidth_reclaimed = 1; 2745 2746 pepext->trb_index[id] = inext; 2747 2748 xhci_endpoint_doorbell(xfer); 2749 2750 return (0); 2751 } 2752 2753 static void 2754 xhci_root_intr(struct xhci_softc *sc) 2755 { 2756 uint16_t i; 2757 2758 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2759 2760 /* clear any old interrupt data */ 2761 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2762 2763 for (i = 1; i <= sc->sc_noport; i++) { 2764 /* pick out CHANGE bits from the status register */ 2765 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2766 XHCI_PS_CSC | XHCI_PS_PEC | 2767 XHCI_PS_OCC | XHCI_PS_WRC | 2768 XHCI_PS_PRC | XHCI_PS_PLC | 2769 XHCI_PS_CEC)) { 2770 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2771 DPRINTF("port %d changed\n", i); 2772 } 2773 } 2774 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2775 sizeof(sc->sc_hub_idata)); 2776 } 2777 2778 /*------------------------------------------------------------------------* 2779 * xhci_device_done - XHCI done handler 2780 * 2781 * NOTE: This function can be called two times in a row on 2782 * the same USB transfer. From close and from interrupt. 2783 *------------------------------------------------------------------------*/ 2784 static void 2785 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2786 { 2787 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2788 xfer, xfer->endpoint, error); 2789 2790 /* remove transfer from HW queue */ 2791 xhci_transfer_remove(xfer, error); 2792 2793 /* dequeue transfer and start next transfer */ 2794 usbd_transfer_done(xfer, error); 2795 } 2796 2797 /*------------------------------------------------------------------------* 2798 * XHCI data transfer support (generic type) 2799 *------------------------------------------------------------------------*/ 2800 static void 2801 xhci_device_generic_open(struct usb_xfer *xfer) 2802 { 2803 if (xfer->flags_int.isochronous_xfr) { 2804 switch (xfer->xroot->udev->speed) { 2805 case USB_SPEED_FULL: 2806 break; 2807 default: 2808 usb_hs_bandwidth_alloc(xfer); 2809 break; 2810 } 2811 } 2812 } 2813 2814 static void 2815 xhci_device_generic_close(struct usb_xfer *xfer) 2816 { 2817 DPRINTF("\n"); 2818 2819 xhci_device_done(xfer, USB_ERR_CANCELLED); 2820 2821 if (xfer->flags_int.isochronous_xfr) { 2822 switch (xfer->xroot->udev->speed) { 2823 case USB_SPEED_FULL: 2824 break; 2825 default: 2826 usb_hs_bandwidth_free(xfer); 2827 break; 2828 } 2829 } 2830 } 2831 2832 static void 2833 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 2834 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 2835 { 2836 struct usb_xfer *xfer; 2837 2838 /* check if there is a current transfer */ 2839 xfer = ep->endpoint_q[stream_id].curr; 2840 if (xfer == NULL) 2841 return; 2842 2843 /* 2844 * Check if the current transfer is started and then pickup 2845 * the next one, if any. Else wait for next start event due to 2846 * block on failure feature. 2847 */ 2848 if (!xfer->flags_int.bandwidth_reclaimed) 2849 return; 2850 2851 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 2852 if (xfer == NULL) { 2853 /* 2854 * In case of enter we have to consider that the 2855 * transfer is queued by the USB core after the enter 2856 * method is called. 2857 */ 2858 xfer = enter_xfer; 2859 2860 if (xfer == NULL) 2861 return; 2862 } 2863 2864 /* try to multi buffer */ 2865 xhci_transfer_insert(xfer); 2866 } 2867 2868 static void 2869 xhci_device_generic_enter(struct usb_xfer *xfer) 2870 { 2871 DPRINTF("\n"); 2872 2873 /* setup TD's and QH */ 2874 xhci_setup_generic_chain(xfer); 2875 2876 xhci_device_generic_multi_enter(xfer->endpoint, 2877 xfer->stream_id, xfer); 2878 } 2879 2880 static void 2881 xhci_device_generic_start(struct usb_xfer *xfer) 2882 { 2883 DPRINTF("\n"); 2884 2885 /* try to insert xfer on HW queue */ 2886 xhci_transfer_insert(xfer); 2887 2888 /* try to multi buffer */ 2889 xhci_device_generic_multi_enter(xfer->endpoint, 2890 xfer->stream_id, NULL); 2891 2892 /* add transfer last on interrupt queue */ 2893 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2894 2895 /* start timeout, if any */ 2896 if (xfer->timeout != 0) 2897 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 2898 } 2899 2900 struct usb_pipe_methods xhci_device_generic_methods = 2901 { 2902 .open = xhci_device_generic_open, 2903 .close = xhci_device_generic_close, 2904 .enter = xhci_device_generic_enter, 2905 .start = xhci_device_generic_start, 2906 }; 2907 2908 /*------------------------------------------------------------------------* 2909 * xhci root HUB support 2910 *------------------------------------------------------------------------* 2911 * Simulate a hardware HUB by handling all the necessary requests. 2912 *------------------------------------------------------------------------*/ 2913 2914 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 2915 2916 static const 2917 struct usb_device_descriptor xhci_devd = 2918 { 2919 .bLength = sizeof(xhci_devd), 2920 .bDescriptorType = UDESC_DEVICE, /* type */ 2921 HSETW(.bcdUSB, 0x0300), /* USB version */ 2922 .bDeviceClass = UDCLASS_HUB, /* class */ 2923 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 2924 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 2925 .bMaxPacketSize = 9, /* max packet size */ 2926 HSETW(.idVendor, 0x0000), /* vendor */ 2927 HSETW(.idProduct, 0x0000), /* product */ 2928 HSETW(.bcdDevice, 0x0100), /* device version */ 2929 .iManufacturer = 1, 2930 .iProduct = 2, 2931 .iSerialNumber = 0, 2932 .bNumConfigurations = 1, /* # of configurations */ 2933 }; 2934 2935 static const 2936 struct xhci_bos_desc xhci_bosd = { 2937 .bosd = { 2938 .bLength = sizeof(xhci_bosd.bosd), 2939 .bDescriptorType = UDESC_BOS, 2940 HSETW(.wTotalLength, sizeof(xhci_bosd)), 2941 .bNumDeviceCaps = 3, 2942 }, 2943 .usb2extd = { 2944 .bLength = sizeof(xhci_bosd.usb2extd), 2945 .bDescriptorType = 1, 2946 .bDevCapabilityType = 2, 2947 .bmAttributes[0] = 2, 2948 }, 2949 .usbdcd = { 2950 .bLength = sizeof(xhci_bosd.usbdcd), 2951 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 2952 .bDevCapabilityType = 3, 2953 .bmAttributes = 0, /* XXX */ 2954 HSETW(.wSpeedsSupported, 0x000C), 2955 .bFunctionalitySupport = 8, 2956 .bU1DevExitLat = 255, /* dummy - not used */ 2957 .wU2DevExitLat = { 0x00, 0x08 }, 2958 }, 2959 .cidd = { 2960 .bLength = sizeof(xhci_bosd.cidd), 2961 .bDescriptorType = 1, 2962 .bDevCapabilityType = 4, 2963 .bReserved = 0, 2964 .bContainerID = 0, /* XXX */ 2965 }, 2966 }; 2967 2968 static const 2969 struct xhci_config_desc xhci_confd = { 2970 .confd = { 2971 .bLength = sizeof(xhci_confd.confd), 2972 .bDescriptorType = UDESC_CONFIG, 2973 .wTotalLength[0] = sizeof(xhci_confd), 2974 .bNumInterface = 1, 2975 .bConfigurationValue = 1, 2976 .iConfiguration = 0, 2977 .bmAttributes = UC_SELF_POWERED, 2978 .bMaxPower = 0 /* max power */ 2979 }, 2980 .ifcd = { 2981 .bLength = sizeof(xhci_confd.ifcd), 2982 .bDescriptorType = UDESC_INTERFACE, 2983 .bNumEndpoints = 1, 2984 .bInterfaceClass = UICLASS_HUB, 2985 .bInterfaceSubClass = UISUBCLASS_HUB, 2986 .bInterfaceProtocol = 0, 2987 }, 2988 .endpd = { 2989 .bLength = sizeof(xhci_confd.endpd), 2990 .bDescriptorType = UDESC_ENDPOINT, 2991 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 2992 .bmAttributes = UE_INTERRUPT, 2993 .wMaxPacketSize[0] = 2, /* max 15 ports */ 2994 .bInterval = 255, 2995 }, 2996 .endpcd = { 2997 .bLength = sizeof(xhci_confd.endpcd), 2998 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 2999 .bMaxBurst = 0, 3000 .bmAttributes = 0, 3001 }, 3002 }; 3003 3004 static const 3005 struct usb_hub_ss_descriptor xhci_hubd = { 3006 .bLength = sizeof(xhci_hubd), 3007 .bDescriptorType = UDESC_SS_HUB, 3008 }; 3009 3010 static usb_error_t 3011 xhci_roothub_exec(struct usb_device *udev, 3012 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3013 { 3014 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3015 const char *str_ptr; 3016 const void *ptr; 3017 uint32_t port; 3018 uint32_t v; 3019 uint16_t len; 3020 uint16_t i; 3021 uint16_t value; 3022 uint16_t index; 3023 uint8_t j; 3024 usb_error_t err; 3025 3026 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3027 3028 /* buffer reset */ 3029 ptr = (const void *)&sc->sc_hub_desc; 3030 len = 0; 3031 err = 0; 3032 3033 value = UGETW(req->wValue); 3034 index = UGETW(req->wIndex); 3035 3036 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3037 "wValue=0x%04x wIndex=0x%04x\n", 3038 req->bmRequestType, req->bRequest, 3039 UGETW(req->wLength), value, index); 3040 3041 #define C(x,y) ((x) | ((y) << 8)) 3042 switch (C(req->bRequest, req->bmRequestType)) { 3043 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3044 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3045 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3046 /* 3047 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3048 * for the integrated root hub. 3049 */ 3050 break; 3051 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3052 len = 1; 3053 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3054 break; 3055 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3056 switch (value >> 8) { 3057 case UDESC_DEVICE: 3058 if ((value & 0xff) != 0) { 3059 err = USB_ERR_IOERROR; 3060 goto done; 3061 } 3062 len = sizeof(xhci_devd); 3063 ptr = (const void *)&xhci_devd; 3064 break; 3065 3066 case UDESC_BOS: 3067 if ((value & 0xff) != 0) { 3068 err = USB_ERR_IOERROR; 3069 goto done; 3070 } 3071 len = sizeof(xhci_bosd); 3072 ptr = (const void *)&xhci_bosd; 3073 break; 3074 3075 case UDESC_CONFIG: 3076 if ((value & 0xff) != 0) { 3077 err = USB_ERR_IOERROR; 3078 goto done; 3079 } 3080 len = sizeof(xhci_confd); 3081 ptr = (const void *)&xhci_confd; 3082 break; 3083 3084 case UDESC_STRING: 3085 switch (value & 0xff) { 3086 case 0: /* Language table */ 3087 str_ptr = "\001"; 3088 break; 3089 3090 case 1: /* Vendor */ 3091 str_ptr = sc->sc_vendor; 3092 break; 3093 3094 case 2: /* Product */ 3095 str_ptr = "XHCI root HUB"; 3096 break; 3097 3098 default: 3099 str_ptr = ""; 3100 break; 3101 } 3102 3103 len = usb_make_str_desc( 3104 sc->sc_hub_desc.temp, 3105 sizeof(sc->sc_hub_desc.temp), 3106 str_ptr); 3107 break; 3108 3109 default: 3110 err = USB_ERR_IOERROR; 3111 goto done; 3112 } 3113 break; 3114 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3115 len = 1; 3116 sc->sc_hub_desc.temp[0] = 0; 3117 break; 3118 case C(UR_GET_STATUS, UT_READ_DEVICE): 3119 len = 2; 3120 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3121 break; 3122 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3123 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3124 len = 2; 3125 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3126 break; 3127 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3128 if (value >= XHCI_MAX_DEVICES) { 3129 err = USB_ERR_IOERROR; 3130 goto done; 3131 } 3132 break; 3133 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3134 if (value != 0 && value != 1) { 3135 err = USB_ERR_IOERROR; 3136 goto done; 3137 } 3138 sc->sc_conf = value; 3139 break; 3140 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3141 break; 3142 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3143 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3144 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3145 err = USB_ERR_IOERROR; 3146 goto done; 3147 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3148 break; 3149 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3150 break; 3151 /* Hub requests */ 3152 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3153 break; 3154 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3155 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3156 3157 if ((index < 1) || 3158 (index > sc->sc_noport)) { 3159 err = USB_ERR_IOERROR; 3160 goto done; 3161 } 3162 port = XHCI_PORTSC(index); 3163 3164 v = XREAD4(sc, oper, port); 3165 i = XHCI_PS_PLS_GET(v); 3166 v &= ~XHCI_PS_CLEAR; 3167 3168 switch (value) { 3169 case UHF_C_BH_PORT_RESET: 3170 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3171 break; 3172 case UHF_C_PORT_CONFIG_ERROR: 3173 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3174 break; 3175 case UHF_C_PORT_SUSPEND: 3176 case UHF_C_PORT_LINK_STATE: 3177 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3178 break; 3179 case UHF_C_PORT_CONNECTION: 3180 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3181 break; 3182 case UHF_C_PORT_ENABLE: 3183 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3184 break; 3185 case UHF_C_PORT_OVER_CURRENT: 3186 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3187 break; 3188 case UHF_C_PORT_RESET: 3189 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3190 break; 3191 case UHF_PORT_ENABLE: 3192 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3193 break; 3194 case UHF_PORT_POWER: 3195 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3196 break; 3197 case UHF_PORT_INDICATOR: 3198 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3199 break; 3200 case UHF_PORT_SUSPEND: 3201 3202 /* U3 -> U15 */ 3203 if (i == 3) { 3204 XWRITE4(sc, oper, port, v | 3205 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3206 } 3207 3208 /* wait 20ms for resume sequence to complete */ 3209 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3210 3211 /* U0 */ 3212 XWRITE4(sc, oper, port, v | 3213 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3214 break; 3215 default: 3216 err = USB_ERR_IOERROR; 3217 goto done; 3218 } 3219 break; 3220 3221 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3222 if ((value & 0xff) != 0) { 3223 err = USB_ERR_IOERROR; 3224 goto done; 3225 } 3226 3227 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3228 3229 sc->sc_hub_desc.hubd = xhci_hubd; 3230 3231 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3232 3233 if (XHCI_HCS0_PPC(v)) 3234 i = UHD_PWR_INDIVIDUAL; 3235 else 3236 i = UHD_PWR_GANGED; 3237 3238 if (XHCI_HCS0_PIND(v)) 3239 i |= UHD_PORT_IND; 3240 3241 i |= UHD_OC_INDIVIDUAL; 3242 3243 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3244 3245 /* see XHCI section 5.4.9: */ 3246 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3247 3248 for (j = 1; j <= sc->sc_noport; j++) { 3249 3250 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3251 if (v & XHCI_PS_DR) { 3252 sc->sc_hub_desc.hubd. 3253 DeviceRemovable[j / 8] |= 1U << (j % 8); 3254 } 3255 } 3256 len = sc->sc_hub_desc.hubd.bLength; 3257 break; 3258 3259 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3260 len = 16; 3261 memset(sc->sc_hub_desc.temp, 0, 16); 3262 break; 3263 3264 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3265 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3266 3267 if ((index < 1) || 3268 (index > sc->sc_noport)) { 3269 err = USB_ERR_IOERROR; 3270 goto done; 3271 } 3272 3273 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3274 3275 DPRINTFN(9, "port status=0x%08x\n", v); 3276 3277 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3278 3279 switch (XHCI_PS_SPEED_GET(v)) { 3280 case 3: 3281 i |= UPS_HIGH_SPEED; 3282 break; 3283 case 2: 3284 i |= UPS_LOW_SPEED; 3285 break; 3286 case 1: 3287 /* FULL speed */ 3288 break; 3289 default: 3290 i |= UPS_OTHER_SPEED; 3291 break; 3292 } 3293 3294 if (v & XHCI_PS_CCS) 3295 i |= UPS_CURRENT_CONNECT_STATUS; 3296 if (v & XHCI_PS_PED) 3297 i |= UPS_PORT_ENABLED; 3298 if (v & XHCI_PS_OCA) 3299 i |= UPS_OVERCURRENT_INDICATOR; 3300 if (v & XHCI_PS_PR) 3301 i |= UPS_RESET; 3302 if (v & XHCI_PS_PP) { 3303 /* 3304 * The USB 3.0 RH is using the 3305 * USB 2.0's power bit 3306 */ 3307 i |= UPS_PORT_POWER; 3308 } 3309 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3310 3311 i = 0; 3312 if (v & XHCI_PS_CSC) 3313 i |= UPS_C_CONNECT_STATUS; 3314 if (v & XHCI_PS_PEC) 3315 i |= UPS_C_PORT_ENABLED; 3316 if (v & XHCI_PS_OCC) 3317 i |= UPS_C_OVERCURRENT_INDICATOR; 3318 if (v & XHCI_PS_WRC) 3319 i |= UPS_C_BH_PORT_RESET; 3320 if (v & XHCI_PS_PRC) 3321 i |= UPS_C_PORT_RESET; 3322 if (v & XHCI_PS_PLC) 3323 i |= UPS_C_PORT_LINK_STATE; 3324 if (v & XHCI_PS_CEC) 3325 i |= UPS_C_PORT_CONFIG_ERROR; 3326 3327 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3328 len = sizeof(sc->sc_hub_desc.ps); 3329 break; 3330 3331 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3332 err = USB_ERR_IOERROR; 3333 goto done; 3334 3335 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3336 break; 3337 3338 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3339 3340 i = index >> 8; 3341 index &= 0x00FF; 3342 3343 if ((index < 1) || 3344 (index > sc->sc_noport)) { 3345 err = USB_ERR_IOERROR; 3346 goto done; 3347 } 3348 3349 port = XHCI_PORTSC(index); 3350 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3351 3352 switch (value) { 3353 case UHF_PORT_U1_TIMEOUT: 3354 if (XHCI_PS_SPEED_GET(v) != 4) { 3355 err = USB_ERR_IOERROR; 3356 goto done; 3357 } 3358 port = XHCI_PORTPMSC(index); 3359 v = XREAD4(sc, oper, port); 3360 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3361 v |= XHCI_PM3_U1TO_SET(i); 3362 XWRITE4(sc, oper, port, v); 3363 break; 3364 case UHF_PORT_U2_TIMEOUT: 3365 if (XHCI_PS_SPEED_GET(v) != 4) { 3366 err = USB_ERR_IOERROR; 3367 goto done; 3368 } 3369 port = XHCI_PORTPMSC(index); 3370 v = XREAD4(sc, oper, port); 3371 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3372 v |= XHCI_PM3_U2TO_SET(i); 3373 XWRITE4(sc, oper, port, v); 3374 break; 3375 case UHF_BH_PORT_RESET: 3376 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3377 break; 3378 case UHF_PORT_LINK_STATE: 3379 XWRITE4(sc, oper, port, v | 3380 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3381 /* 4ms settle time */ 3382 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3383 break; 3384 case UHF_PORT_ENABLE: 3385 DPRINTFN(3, "set port enable %d\n", index); 3386 break; 3387 case UHF_PORT_SUSPEND: 3388 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3389 j = XHCI_PS_SPEED_GET(v); 3390 if ((j < 1) || (j > 3)) { 3391 /* non-supported speed */ 3392 err = USB_ERR_IOERROR; 3393 goto done; 3394 } 3395 XWRITE4(sc, oper, port, v | 3396 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3397 break; 3398 case UHF_PORT_RESET: 3399 DPRINTFN(6, "reset port %d\n", index); 3400 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3401 break; 3402 case UHF_PORT_POWER: 3403 DPRINTFN(3, "set port power %d\n", index); 3404 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3405 break; 3406 case UHF_PORT_TEST: 3407 DPRINTFN(3, "set port test %d\n", index); 3408 break; 3409 case UHF_PORT_INDICATOR: 3410 DPRINTFN(3, "set port indicator %d\n", index); 3411 3412 v &= ~XHCI_PS_PIC_SET(3); 3413 v |= XHCI_PS_PIC_SET(1); 3414 3415 XWRITE4(sc, oper, port, v); 3416 break; 3417 default: 3418 err = USB_ERR_IOERROR; 3419 goto done; 3420 } 3421 break; 3422 3423 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3424 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3425 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3426 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3427 break; 3428 default: 3429 err = USB_ERR_IOERROR; 3430 goto done; 3431 } 3432 done: 3433 *plength = len; 3434 *pptr = ptr; 3435 return (err); 3436 } 3437 3438 static void 3439 xhci_xfer_setup(struct usb_setup_params *parm) 3440 { 3441 struct usb_page_search page_info; 3442 struct usb_page_cache *pc; 3443 struct xhci_softc *sc; 3444 struct usb_xfer *xfer; 3445 void *last_obj; 3446 uint32_t ntd; 3447 uint32_t n; 3448 3449 sc = XHCI_BUS2SC(parm->udev->bus); 3450 xfer = parm->curr_xfer; 3451 3452 /* 3453 * The proof for the "ntd" formula is illustrated like this: 3454 * 3455 * +------------------------------------+ 3456 * | | 3457 * | |remainder -> | 3458 * | +-----+---+ | 3459 * | | xxx | x | frm 0 | 3460 * | +-----+---++ | 3461 * | | xxx | xx | frm 1 | 3462 * | +-----+----+ | 3463 * | ... | 3464 * +------------------------------------+ 3465 * 3466 * "xxx" means a completely full USB transfer descriptor 3467 * 3468 * "x" and "xx" means a short USB packet 3469 * 3470 * For the remainder of an USB transfer modulo 3471 * "max_data_length" we need two USB transfer descriptors. 3472 * One to transfer the remaining data and one to finalise with 3473 * a zero length packet in case the "force_short_xfer" flag is 3474 * set. We only need two USB transfer descriptors in the case 3475 * where the transfer length of the first one is a factor of 3476 * "max_frame_size". The rest of the needed USB transfer 3477 * descriptors is given by the buffer size divided by the 3478 * maximum data payload. 3479 */ 3480 parm->hc_max_packet_size = 0x400; 3481 parm->hc_max_packet_count = 16 * 3; 3482 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3483 3484 xfer->flags_int.bdma_enable = 1; 3485 3486 usbd_transfer_setup_sub(parm); 3487 3488 if (xfer->flags_int.isochronous_xfr) { 3489 ntd = ((1 * xfer->nframes) 3490 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3491 } else if (xfer->flags_int.control_xfr) { 3492 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3493 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3494 } else { 3495 ntd = ((2 * xfer->nframes) 3496 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3497 } 3498 3499 alloc_dma_set: 3500 3501 if (parm->err) 3502 return; 3503 3504 /* 3505 * Allocate queue heads and transfer descriptors 3506 */ 3507 last_obj = NULL; 3508 3509 if (usbd_transfer_setup_sub_malloc( 3510 parm, &pc, sizeof(struct xhci_td), 3511 XHCI_TD_ALIGN, ntd)) { 3512 parm->err = USB_ERR_NOMEM; 3513 return; 3514 } 3515 if (parm->buf) { 3516 for (n = 0; n != ntd; n++) { 3517 struct xhci_td *td; 3518 3519 usbd_get_page(pc + n, 0, &page_info); 3520 3521 td = page_info.buffer; 3522 3523 /* init TD */ 3524 td->td_self = page_info.physaddr; 3525 td->obj_next = last_obj; 3526 td->page_cache = pc + n; 3527 3528 last_obj = td; 3529 3530 usb_pc_cpu_flush(pc + n); 3531 } 3532 } 3533 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3534 3535 if (!xfer->flags_int.curr_dma_set) { 3536 xfer->flags_int.curr_dma_set = 1; 3537 goto alloc_dma_set; 3538 } 3539 } 3540 3541 static usb_error_t 3542 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3543 { 3544 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3545 struct usb_page_search buf_inp; 3546 struct usb_device *udev; 3547 struct xhci_endpoint_ext *pepext; 3548 struct usb_endpoint_descriptor *edesc; 3549 struct usb_page_cache *pcinp; 3550 usb_error_t err; 3551 usb_stream_t stream_id; 3552 uint8_t index; 3553 uint8_t epno; 3554 3555 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3556 xfer->endpoint->edesc); 3557 3558 udev = xfer->xroot->udev; 3559 index = udev->controller_slot_id; 3560 3561 pcinp = &sc->sc_hw.devs[index].input_pc; 3562 3563 usbd_get_page(pcinp, 0, &buf_inp); 3564 3565 edesc = xfer->endpoint->edesc; 3566 3567 epno = edesc->bEndpointAddress; 3568 stream_id = xfer->stream_id; 3569 3570 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3571 epno |= UE_DIR_IN; 3572 3573 epno = XHCI_EPNO2EPID(epno); 3574 3575 if (epno == 0) 3576 return (USB_ERR_NO_PIPE); /* invalid */ 3577 3578 XHCI_CMD_LOCK(sc); 3579 3580 /* configure endpoint */ 3581 3582 err = xhci_configure_endpoint_by_xfer(xfer); 3583 3584 if (err != 0) { 3585 XHCI_CMD_UNLOCK(sc); 3586 return (err); 3587 } 3588 3589 /* 3590 * Get the endpoint into the stopped state according to the 3591 * endpoint context state diagram in the XHCI specification: 3592 */ 3593 3594 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3595 3596 if (err != 0) 3597 DPRINTF("Could not stop endpoint %u\n", epno); 3598 3599 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3600 3601 if (err != 0) 3602 DPRINTF("Could not reset endpoint %u\n", epno); 3603 3604 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3605 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3606 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3607 stream_id, epno, index); 3608 3609 if (err != 0) 3610 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3611 3612 /* 3613 * Get the endpoint into the running state according to the 3614 * endpoint context state diagram in the XHCI specification: 3615 */ 3616 3617 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3618 3619 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3620 3621 if (err != 0) 3622 DPRINTF("Could not configure endpoint %u\n", epno); 3623 3624 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3625 3626 if (err != 0) 3627 DPRINTF("Could not configure endpoint %u\n", epno); 3628 3629 XHCI_CMD_UNLOCK(sc); 3630 3631 return (0); 3632 } 3633 3634 static void 3635 xhci_xfer_unsetup(struct usb_xfer *xfer) 3636 { 3637 return; 3638 } 3639 3640 static void 3641 xhci_start_dma_delay(struct usb_xfer *xfer) 3642 { 3643 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3644 3645 /* put transfer on interrupt queue (again) */ 3646 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3647 3648 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3649 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3650 } 3651 3652 static void 3653 xhci_configure_msg(struct usb_proc_msg *pm) 3654 { 3655 struct xhci_softc *sc; 3656 struct xhci_endpoint_ext *pepext; 3657 struct usb_xfer *xfer; 3658 3659 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3660 3661 restart: 3662 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3663 3664 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3665 xfer->endpoint->edesc); 3666 3667 if ((pepext->trb_halted != 0) || 3668 (pepext->trb_running == 0)) { 3669 3670 uint8_t i; 3671 3672 /* clear halted and running */ 3673 pepext->trb_halted = 0; 3674 pepext->trb_running = 0; 3675 3676 /* nuke remaining buffered transfers */ 3677 3678 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 3679 /* 3680 * NOTE: We need to use the timeout 3681 * error code here else existing 3682 * isochronous clients can get 3683 * confused: 3684 */ 3685 if (pepext->xfer[i] != NULL) { 3686 xhci_device_done(pepext->xfer[i], 3687 USB_ERR_TIMEOUT); 3688 } 3689 } 3690 3691 /* 3692 * NOTE: The USB transfer cannot vanish in 3693 * this state! 3694 */ 3695 3696 USB_BUS_UNLOCK(&sc->sc_bus); 3697 3698 xhci_configure_reset_endpoint(xfer); 3699 3700 USB_BUS_LOCK(&sc->sc_bus); 3701 3702 /* check if halted is still cleared */ 3703 if (pepext->trb_halted == 0) { 3704 pepext->trb_running = 1; 3705 memset(pepext->trb_index, 0, 3706 sizeof(pepext->trb_index)); 3707 } 3708 goto restart; 3709 } 3710 3711 if (xfer->flags_int.did_dma_delay) { 3712 3713 /* remove transfer from interrupt queue (again) */ 3714 usbd_transfer_dequeue(xfer); 3715 3716 /* we are finally done */ 3717 usb_dma_delay_done_cb(xfer); 3718 3719 /* queue changed - restart */ 3720 goto restart; 3721 } 3722 } 3723 3724 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3725 3726 /* try to insert xfer on HW queue */ 3727 xhci_transfer_insert(xfer); 3728 3729 /* try to multi buffer */ 3730 xhci_device_generic_multi_enter(xfer->endpoint, 3731 xfer->stream_id, NULL); 3732 } 3733 } 3734 3735 static void 3736 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3737 struct usb_endpoint *ep) 3738 { 3739 struct xhci_endpoint_ext *pepext; 3740 3741 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3742 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3743 3744 if (udev->parent_hub == NULL) { 3745 /* root HUB has special endpoint handling */ 3746 return; 3747 } 3748 3749 ep->methods = &xhci_device_generic_methods; 3750 3751 pepext = xhci_get_endpoint_ext(udev, edesc); 3752 3753 USB_BUS_LOCK(udev->bus); 3754 pepext->trb_halted = 1; 3755 pepext->trb_running = 0; 3756 USB_BUS_UNLOCK(udev->bus); 3757 } 3758 3759 static void 3760 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3761 { 3762 3763 } 3764 3765 static void 3766 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3767 { 3768 struct xhci_endpoint_ext *pepext; 3769 3770 DPRINTF("\n"); 3771 3772 if (udev->flags.usb_mode != USB_MODE_HOST) { 3773 /* not supported */ 3774 return; 3775 } 3776 if (udev->parent_hub == NULL) { 3777 /* root HUB has special endpoint handling */ 3778 return; 3779 } 3780 3781 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3782 3783 USB_BUS_LOCK(udev->bus); 3784 pepext->trb_halted = 1; 3785 pepext->trb_running = 0; 3786 USB_BUS_UNLOCK(udev->bus); 3787 } 3788 3789 static usb_error_t 3790 xhci_device_init(struct usb_device *udev) 3791 { 3792 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3793 usb_error_t err; 3794 uint8_t temp; 3795 3796 /* no init for root HUB */ 3797 if (udev->parent_hub == NULL) 3798 return (0); 3799 3800 XHCI_CMD_LOCK(sc); 3801 3802 /* set invalid default */ 3803 3804 udev->controller_slot_id = sc->sc_noslot + 1; 3805 3806 /* try to get a new slot ID from the XHCI */ 3807 3808 err = xhci_cmd_enable_slot(sc, &temp); 3809 3810 if (err) { 3811 XHCI_CMD_UNLOCK(sc); 3812 return (err); 3813 } 3814 3815 if (temp > sc->sc_noslot) { 3816 XHCI_CMD_UNLOCK(sc); 3817 return (USB_ERR_BAD_ADDRESS); 3818 } 3819 3820 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 3821 DPRINTF("slot %u already allocated.\n", temp); 3822 XHCI_CMD_UNLOCK(sc); 3823 return (USB_ERR_BAD_ADDRESS); 3824 } 3825 3826 /* store slot ID for later reference */ 3827 3828 udev->controller_slot_id = temp; 3829 3830 /* reset data structure */ 3831 3832 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 3833 3834 /* set mark slot allocated */ 3835 3836 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 3837 3838 err = xhci_alloc_device_ext(udev); 3839 3840 XHCI_CMD_UNLOCK(sc); 3841 3842 /* get device into default state */ 3843 3844 if (err == 0) 3845 err = xhci_set_address(udev, NULL, 0); 3846 3847 return (err); 3848 } 3849 3850 static void 3851 xhci_device_uninit(struct usb_device *udev) 3852 { 3853 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3854 uint8_t index; 3855 3856 /* no init for root HUB */ 3857 if (udev->parent_hub == NULL) 3858 return; 3859 3860 XHCI_CMD_LOCK(sc); 3861 3862 index = udev->controller_slot_id; 3863 3864 if (index <= sc->sc_noslot) { 3865 xhci_cmd_disable_slot(sc, index); 3866 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 3867 3868 /* free device extension */ 3869 xhci_free_device_ext(udev); 3870 } 3871 3872 XHCI_CMD_UNLOCK(sc); 3873 } 3874 3875 static void 3876 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3877 { 3878 /* 3879 * Wait until the hardware has finished any possible use of 3880 * the transfer descriptor(s) 3881 */ 3882 *pus = 2048; /* microseconds */ 3883 } 3884 3885 static void 3886 xhci_device_resume(struct usb_device *udev) 3887 { 3888 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3889 uint8_t index; 3890 uint8_t n; 3891 uint8_t p; 3892 3893 DPRINTF("\n"); 3894 3895 /* check for root HUB */ 3896 if (udev->parent_hub == NULL) 3897 return; 3898 3899 index = udev->controller_slot_id; 3900 3901 XHCI_CMD_LOCK(sc); 3902 3903 /* blindly resume all endpoints */ 3904 3905 USB_BUS_LOCK(udev->bus); 3906 3907 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3908 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 3909 XWRITE4(sc, door, XHCI_DOORBELL(index), 3910 n | XHCI_DB_SID_SET(p)); 3911 } 3912 } 3913 3914 USB_BUS_UNLOCK(udev->bus); 3915 3916 XHCI_CMD_UNLOCK(sc); 3917 } 3918 3919 static void 3920 xhci_device_suspend(struct usb_device *udev) 3921 { 3922 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3923 uint8_t index; 3924 uint8_t n; 3925 usb_error_t err; 3926 3927 DPRINTF("\n"); 3928 3929 /* check for root HUB */ 3930 if (udev->parent_hub == NULL) 3931 return; 3932 3933 index = udev->controller_slot_id; 3934 3935 XHCI_CMD_LOCK(sc); 3936 3937 /* blindly suspend all endpoints */ 3938 3939 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3940 err = xhci_cmd_stop_ep(sc, 1, n, index); 3941 if (err != 0) { 3942 DPRINTF("Failed to suspend endpoint " 3943 "%u on slot %u (ignored).\n", n, index); 3944 } 3945 } 3946 3947 XHCI_CMD_UNLOCK(sc); 3948 } 3949 3950 static void 3951 xhci_set_hw_power(struct usb_bus *bus) 3952 { 3953 DPRINTF("\n"); 3954 } 3955 3956 static void 3957 xhci_device_state_change(struct usb_device *udev) 3958 { 3959 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3960 struct usb_page_search buf_inp; 3961 usb_error_t err; 3962 uint8_t index; 3963 3964 /* check for root HUB */ 3965 if (udev->parent_hub == NULL) 3966 return; 3967 3968 index = udev->controller_slot_id; 3969 3970 DPRINTF("\n"); 3971 3972 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 3973 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 3974 &sc->sc_hw.devs[index].tt); 3975 if (err != 0) 3976 sc->sc_hw.devs[index].nports = 0; 3977 } 3978 3979 XHCI_CMD_LOCK(sc); 3980 3981 switch (usb_get_device_state(udev)) { 3982 case USB_STATE_POWERED: 3983 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 3984 break; 3985 3986 /* set default state */ 3987 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 3988 3989 /* reset number of contexts */ 3990 sc->sc_hw.devs[index].context_num = 0; 3991 3992 err = xhci_cmd_reset_dev(sc, index); 3993 3994 if (err != 0) { 3995 DPRINTF("Device reset failed " 3996 "for slot %u.\n", index); 3997 } 3998 break; 3999 4000 case USB_STATE_ADDRESSED: 4001 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4002 break; 4003 4004 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4005 4006 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4007 4008 if (err) { 4009 DPRINTF("Failed to deconfigure " 4010 "slot %u.\n", index); 4011 } 4012 break; 4013 4014 case USB_STATE_CONFIGURED: 4015 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4016 break; 4017 4018 /* set configured state */ 4019 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4020 4021 /* reset number of contexts */ 4022 sc->sc_hw.devs[index].context_num = 0; 4023 4024 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4025 4026 xhci_configure_mask(udev, 3, 0); 4027 4028 err = xhci_configure_device(udev); 4029 if (err != 0) { 4030 DPRINTF("Could not configure device " 4031 "at slot %u.\n", index); 4032 } 4033 4034 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4035 if (err != 0) { 4036 DPRINTF("Could not evaluate device " 4037 "context at slot %u.\n", index); 4038 } 4039 break; 4040 4041 default: 4042 break; 4043 } 4044 XHCI_CMD_UNLOCK(sc); 4045 } 4046 4047 static usb_error_t 4048 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4049 uint8_t ep_mode) 4050 { 4051 switch (ep_mode) { 4052 case USB_EP_MODE_DEFAULT: 4053 return (0); 4054 case USB_EP_MODE_STREAMS: 4055 if ((ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4056 udev->speed != USB_SPEED_SUPER) 4057 return (USB_ERR_INVAL); 4058 return (0); 4059 default: 4060 return (USB_ERR_INVAL); 4061 } 4062 } 4063 4064 struct usb_bus_methods xhci_bus_methods = { 4065 .endpoint_init = xhci_ep_init, 4066 .endpoint_uninit = xhci_ep_uninit, 4067 .xfer_setup = xhci_xfer_setup, 4068 .xfer_unsetup = xhci_xfer_unsetup, 4069 .get_dma_delay = xhci_get_dma_delay, 4070 .device_init = xhci_device_init, 4071 .device_uninit = xhci_device_uninit, 4072 .device_resume = xhci_device_resume, 4073 .device_suspend = xhci_device_suspend, 4074 .set_hw_power = xhci_set_hw_power, 4075 .roothub_exec = xhci_roothub_exec, 4076 .xfer_poll = xhci_do_poll, 4077 .start_dma_delay = xhci_start_dma_delay, 4078 .set_address = xhci_set_address, 4079 .clear_stall = xhci_ep_clear_stall, 4080 .device_state_change = xhci_device_state_change, 4081 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4082 .set_endpoint_mode = xhci_set_endpoint_mode, 4083 }; 4084