1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 28 * 29 * The XHCI 1.0 spec can be found at 30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 31 * and the USB 3.0 spec at 32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 33 */ 34 35 /* 36 * A few words about the design implementation: This driver emulates 37 * the concept about TDs which is found in EHCI specification. This 38 * way we avoid too much diveration among USB drivers. 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/stdint.h> 45 #include <sys/stddef.h> 46 #include <sys/param.h> 47 #include <sys/queue.h> 48 #include <sys/types.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/bus.h> 52 #include <sys/module.h> 53 #include <sys/lock.h> 54 #include <sys/mutex.h> 55 #include <sys/condvar.h> 56 #include <sys/sysctl.h> 57 #include <sys/sx.h> 58 #include <sys/unistd.h> 59 #include <sys/callout.h> 60 #include <sys/malloc.h> 61 #include <sys/priv.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 66 #define USB_DEBUG_VAR xhcidebug 67 68 #include <dev/usb/usb_core.h> 69 #include <dev/usb/usb_debug.h> 70 #include <dev/usb/usb_busdma.h> 71 #include <dev/usb/usb_process.h> 72 #include <dev/usb/usb_transfer.h> 73 #include <dev/usb/usb_device.h> 74 #include <dev/usb/usb_hub.h> 75 #include <dev/usb/usb_util.h> 76 77 #include <dev/usb/usb_controller.h> 78 #include <dev/usb/usb_bus.h> 79 #include <dev/usb/controller/xhci.h> 80 #include <dev/usb/controller/xhcireg.h> 81 82 #define XHCI_BUS2SC(bus) \ 83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 85 86 #ifdef USB_DEBUG 87 static int xhcidebug; 88 static int xhciroute; 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 92 &xhcidebug, 0, "Debug level"); 93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN, 95 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 97 #endif 98 99 #define XHCI_INTR_ENDPT 1 100 101 struct xhci_std_temp { 102 struct xhci_softc *sc; 103 struct usb_page_cache *pc; 104 struct xhci_td *td; 105 struct xhci_td *td_next; 106 uint32_t len; 107 uint32_t offset; 108 uint32_t max_packet_size; 109 uint32_t average; 110 uint16_t isoc_delta; 111 uint16_t isoc_frame; 112 uint8_t shortpkt; 113 uint8_t multishort; 114 uint8_t last_frame; 115 uint8_t trb_type; 116 uint8_t direction; 117 uint8_t tbc; 118 uint8_t tlbpc; 119 uint8_t step_td; 120 uint8_t do_isoc_sync; 121 }; 122 123 static void xhci_do_poll(struct usb_bus *); 124 static void xhci_device_done(struct usb_xfer *, usb_error_t); 125 static void xhci_root_intr(struct xhci_softc *); 126 static void xhci_free_device_ext(struct usb_device *); 127 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 128 struct usb_endpoint_descriptor *); 129 static usb_proc_callback_t xhci_configure_msg; 130 static usb_error_t xhci_configure_device(struct usb_device *); 131 static usb_error_t xhci_configure_endpoint(struct usb_device *, 132 struct usb_endpoint_descriptor *, uint64_t, uint16_t, 133 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, uint8_t); 134 static usb_error_t xhci_configure_mask(struct usb_device *, 135 uint32_t, uint8_t); 136 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 137 uint64_t, uint8_t); 138 static void xhci_endpoint_doorbell(struct usb_xfer *); 139 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 140 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 141 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 142 #ifdef USB_DEBUG 143 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 144 #endif 145 146 extern struct usb_bus_methods xhci_bus_methods; 147 148 #ifdef USB_DEBUG 149 static void 150 xhci_dump_trb(struct xhci_trb *trb) 151 { 152 DPRINTFN(5, "trb = %p\n", trb); 153 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 154 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 155 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 156 } 157 158 static void 159 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 160 { 161 DPRINTFN(5, "pep = %p\n", pep); 162 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 163 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 164 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 165 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 166 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 167 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 168 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 169 } 170 171 static void 172 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 173 { 174 DPRINTFN(5, "psl = %p\n", psl); 175 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 176 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 177 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 178 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 179 } 180 #endif 181 182 uint32_t 183 xhci_get_port_route(void) 184 { 185 #ifdef USB_DEBUG 186 return (0xFFFFFFFFU ^ ((uint32_t)xhciroute)); 187 #else 188 return (0xFFFFFFFFU); 189 #endif 190 } 191 192 static void 193 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 194 { 195 struct xhci_softc *sc = XHCI_BUS2SC(bus); 196 uint8_t i; 197 198 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 199 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 200 201 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 202 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 203 204 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 205 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 206 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 207 } 208 } 209 210 static void 211 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 212 { 213 if (sc->sc_ctx_is_64_byte) { 214 uint32_t offset; 215 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 216 /* all contexts are initially 32-bytes */ 217 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 218 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 219 } 220 *ptr = htole32(val); 221 } 222 223 static uint32_t 224 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 225 { 226 if (sc->sc_ctx_is_64_byte) { 227 uint32_t offset; 228 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 229 /* all contexts are initially 32-bytes */ 230 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 231 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 232 } 233 return (le32toh(*ptr)); 234 } 235 236 static void 237 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 238 { 239 if (sc->sc_ctx_is_64_byte) { 240 uint32_t offset; 241 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 242 /* all contexts are initially 32-bytes */ 243 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 244 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 245 } 246 *ptr = htole64(val); 247 } 248 249 #ifdef USB_DEBUG 250 static uint64_t 251 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 252 { 253 if (sc->sc_ctx_is_64_byte) { 254 uint32_t offset; 255 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 256 /* all contexts are initially 32-bytes */ 257 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 258 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 259 } 260 return (le64toh(*ptr)); 261 } 262 #endif 263 264 usb_error_t 265 xhci_start_controller(struct xhci_softc *sc) 266 { 267 struct usb_page_search buf_res; 268 struct xhci_hw_root *phwr; 269 struct xhci_dev_ctx_addr *pdctxa; 270 uint64_t addr; 271 uint32_t temp; 272 uint16_t i; 273 274 DPRINTF("\n"); 275 276 sc->sc_capa_off = 0; 277 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 278 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 279 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 280 281 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 282 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 283 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 284 285 sc->sc_event_ccs = 1; 286 sc->sc_event_idx = 0; 287 sc->sc_command_ccs = 1; 288 sc->sc_command_idx = 0; 289 290 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 291 292 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 293 294 DPRINTF("HCS0 = 0x%08x\n", temp); 295 296 if (XHCI_HCS0_CSZ(temp)) { 297 sc->sc_ctx_is_64_byte = 1; 298 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 299 } else { 300 sc->sc_ctx_is_64_byte = 0; 301 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 302 } 303 304 /* Reset controller */ 305 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 306 307 for (i = 0; i != 100; i++) { 308 usb_pause_mtx(NULL, hz / 100); 309 temp = XREAD4(sc, oper, XHCI_USBCMD) & 310 (XHCI_CMD_HCRST | XHCI_STS_CNR); 311 if (!temp) 312 break; 313 } 314 315 if (temp) { 316 device_printf(sc->sc_bus.parent, "Controller " 317 "reset timeout.\n"); 318 return (USB_ERR_IOERROR); 319 } 320 321 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 322 device_printf(sc->sc_bus.parent, "Controller does " 323 "not support 4K page size.\n"); 324 return (USB_ERR_IOERROR); 325 } 326 327 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 328 329 i = XHCI_HCS1_N_PORTS(temp); 330 331 if (i == 0) { 332 device_printf(sc->sc_bus.parent, "Invalid number " 333 "of ports: %u\n", i); 334 return (USB_ERR_IOERROR); 335 } 336 337 sc->sc_noport = i; 338 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 339 340 if (sc->sc_noslot > XHCI_MAX_DEVICES) 341 sc->sc_noslot = XHCI_MAX_DEVICES; 342 343 /* setup number of device slots */ 344 345 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 346 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 347 348 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 349 350 DPRINTF("Max slots: %u\n", sc->sc_noslot); 351 352 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 353 354 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 355 356 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 357 device_printf(sc->sc_bus.parent, "XHCI request " 358 "too many scratchpads\n"); 359 return (USB_ERR_NOMEM); 360 } 361 362 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 363 364 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 365 366 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 367 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 368 369 temp = XREAD4(sc, oper, XHCI_USBSTS); 370 371 /* clear interrupts */ 372 XWRITE4(sc, oper, XHCI_USBSTS, temp); 373 /* disable all device notifications */ 374 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 375 376 /* setup device context base address */ 377 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 378 pdctxa = buf_res.buffer; 379 memset(pdctxa, 0, sizeof(*pdctxa)); 380 381 addr = buf_res.physaddr; 382 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 383 384 /* slot 0 points to the table of scratchpad pointers */ 385 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 386 387 for (i = 0; i != sc->sc_noscratch; i++) { 388 struct usb_page_search buf_scp; 389 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 390 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 391 } 392 393 addr = buf_res.physaddr; 394 395 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 396 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 397 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 398 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 399 400 /* Setup event table size */ 401 402 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 403 404 DPRINTF("HCS2=0x%08x\n", temp); 405 406 temp = XHCI_HCS2_ERST_MAX(temp); 407 temp = 1U << temp; 408 if (temp > XHCI_MAX_RSEG) 409 temp = XHCI_MAX_RSEG; 410 411 sc->sc_erst_max = temp; 412 413 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 414 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 415 416 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 417 418 /* Setup interrupt rate */ 419 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 420 421 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 422 423 phwr = buf_res.buffer; 424 addr = buf_res.physaddr; 425 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 426 427 /* reset hardware root structure */ 428 memset(phwr, 0, sizeof(*phwr)); 429 430 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 431 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 432 433 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 434 435 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 436 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 437 438 addr = (uint64_t)buf_res.physaddr; 439 440 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 441 442 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 443 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 444 445 /* Setup interrupter registers */ 446 447 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 448 temp |= XHCI_IMAN_INTR_ENA; 449 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 450 451 /* setup command ring control base address */ 452 addr = buf_res.physaddr; 453 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 454 455 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 456 457 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 458 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 459 460 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 461 462 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 463 464 /* Go! */ 465 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 466 XHCI_CMD_INTE | XHCI_CMD_HSEE); 467 468 for (i = 0; i != 100; i++) { 469 usb_pause_mtx(NULL, hz / 100); 470 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 471 if (!temp) 472 break; 473 } 474 if (temp) { 475 XWRITE4(sc, oper, XHCI_USBCMD, 0); 476 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 477 return (USB_ERR_IOERROR); 478 } 479 480 /* catch any lost interrupts */ 481 xhci_do_poll(&sc->sc_bus); 482 483 return (0); 484 } 485 486 usb_error_t 487 xhci_halt_controller(struct xhci_softc *sc) 488 { 489 uint32_t temp; 490 uint16_t i; 491 492 DPRINTF("\n"); 493 494 sc->sc_capa_off = 0; 495 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 496 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 497 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 498 499 /* Halt controller */ 500 XWRITE4(sc, oper, XHCI_USBCMD, 0); 501 502 for (i = 0; i != 100; i++) { 503 usb_pause_mtx(NULL, hz / 100); 504 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 505 if (temp) 506 break; 507 } 508 509 if (!temp) { 510 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 511 return (USB_ERR_IOERROR); 512 } 513 return (0); 514 } 515 516 usb_error_t 517 xhci_init(struct xhci_softc *sc, device_t self) 518 { 519 /* initialise some bus fields */ 520 sc->sc_bus.parent = self; 521 522 /* set the bus revision */ 523 sc->sc_bus.usbrev = USB_REV_3_0; 524 525 /* set up the bus struct */ 526 sc->sc_bus.methods = &xhci_bus_methods; 527 528 /* setup devices array */ 529 sc->sc_bus.devices = sc->sc_devices; 530 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 531 532 /* setup command queue mutex and condition varible */ 533 cv_init(&sc->sc_cmd_cv, "CMDQ"); 534 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 535 536 /* get all DMA memory */ 537 if (usb_bus_mem_alloc_all(&sc->sc_bus, 538 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 539 return (ENOMEM); 540 } 541 542 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 543 sc->sc_config_msg[0].bus = &sc->sc_bus; 544 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 545 sc->sc_config_msg[1].bus = &sc->sc_bus; 546 547 if (usb_proc_create(&sc->sc_config_proc, 548 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) { 549 printf("WARNING: Creation of XHCI configure " 550 "callback process failed.\n"); 551 } 552 return (0); 553 } 554 555 void 556 xhci_uninit(struct xhci_softc *sc) 557 { 558 usb_proc_free(&sc->sc_config_proc); 559 560 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 561 562 cv_destroy(&sc->sc_cmd_cv); 563 sx_destroy(&sc->sc_cmd_sx); 564 } 565 566 static void 567 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 568 { 569 struct xhci_softc *sc = XHCI_BUS2SC(bus); 570 571 switch (state) { 572 case USB_HW_POWER_SUSPEND: 573 DPRINTF("Stopping the XHCI\n"); 574 xhci_halt_controller(sc); 575 break; 576 case USB_HW_POWER_SHUTDOWN: 577 DPRINTF("Stopping the XHCI\n"); 578 xhci_halt_controller(sc); 579 break; 580 case USB_HW_POWER_RESUME: 581 DPRINTF("Starting the XHCI\n"); 582 xhci_start_controller(sc); 583 break; 584 default: 585 break; 586 } 587 } 588 589 static usb_error_t 590 xhci_generic_done_sub(struct usb_xfer *xfer) 591 { 592 struct xhci_td *td; 593 struct xhci_td *td_alt_next; 594 uint32_t len; 595 uint8_t status; 596 597 td = xfer->td_transfer_cache; 598 td_alt_next = td->alt_next; 599 600 if (xfer->aframes != xfer->nframes) 601 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 602 603 while (1) { 604 605 usb_pc_cpu_invalidate(td->page_cache); 606 607 status = td->status; 608 len = td->remainder; 609 610 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 611 xfer, (unsigned int)xfer->aframes, 612 (unsigned int)xfer->nframes, 613 (unsigned int)len, (unsigned int)td->len, 614 (unsigned int)status); 615 616 /* 617 * Verify the status length and 618 * add the length to "frlengths[]": 619 */ 620 if (len > td->len) { 621 /* should not happen */ 622 DPRINTF("Invalid status length, " 623 "0x%04x/0x%04x bytes\n", len, td->len); 624 status = XHCI_TRB_ERROR_LENGTH; 625 } else if (xfer->aframes != xfer->nframes) { 626 xfer->frlengths[xfer->aframes] += td->len - len; 627 } 628 /* Check for last transfer */ 629 if (((void *)td) == xfer->td_transfer_last) { 630 td = NULL; 631 break; 632 } 633 /* Check for transfer error */ 634 if (status != XHCI_TRB_ERROR_SHORT_PKT && 635 status != XHCI_TRB_ERROR_SUCCESS) { 636 /* the transfer is finished */ 637 td = NULL; 638 break; 639 } 640 /* Check for short transfer */ 641 if (len > 0) { 642 if (xfer->flags_int.short_frames_ok || 643 xfer->flags_int.isochronous_xfr || 644 xfer->flags_int.control_xfr) { 645 /* follow alt next */ 646 td = td->alt_next; 647 } else { 648 /* the transfer is finished */ 649 td = NULL; 650 } 651 break; 652 } 653 td = td->obj_next; 654 655 if (td->alt_next != td_alt_next) { 656 /* this USB frame is complete */ 657 break; 658 } 659 } 660 661 /* update transfer cache */ 662 663 xfer->td_transfer_cache = td; 664 665 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 666 (status != XHCI_TRB_ERROR_SHORT_PKT && 667 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 668 USB_ERR_NORMAL_COMPLETION); 669 } 670 671 static void 672 xhci_generic_done(struct usb_xfer *xfer) 673 { 674 usb_error_t err = 0; 675 676 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 677 xfer, xfer->endpoint); 678 679 /* reset scanner */ 680 681 xfer->td_transfer_cache = xfer->td_transfer_first; 682 683 if (xfer->flags_int.control_xfr) { 684 685 if (xfer->flags_int.control_hdr) 686 err = xhci_generic_done_sub(xfer); 687 688 xfer->aframes = 1; 689 690 if (xfer->td_transfer_cache == NULL) 691 goto done; 692 } 693 694 while (xfer->aframes != xfer->nframes) { 695 696 err = xhci_generic_done_sub(xfer); 697 xfer->aframes++; 698 699 if (xfer->td_transfer_cache == NULL) 700 goto done; 701 } 702 703 if (xfer->flags_int.control_xfr && 704 !xfer->flags_int.control_act) 705 err = xhci_generic_done_sub(xfer); 706 done: 707 /* transfer is complete */ 708 xhci_device_done(xfer, err); 709 } 710 711 static void 712 xhci_activate_transfer(struct usb_xfer *xfer) 713 { 714 struct xhci_td *td; 715 716 td = xfer->td_transfer_cache; 717 718 usb_pc_cpu_invalidate(td->page_cache); 719 720 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 721 722 /* activate the transfer */ 723 724 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 725 usb_pc_cpu_flush(td->page_cache); 726 727 xhci_endpoint_doorbell(xfer); 728 } 729 } 730 731 static void 732 xhci_skip_transfer(struct usb_xfer *xfer) 733 { 734 struct xhci_td *td; 735 struct xhci_td *td_last; 736 737 td = xfer->td_transfer_cache; 738 td_last = xfer->td_transfer_last; 739 740 td = td->alt_next; 741 742 usb_pc_cpu_invalidate(td->page_cache); 743 744 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 745 746 usb_pc_cpu_invalidate(td_last->page_cache); 747 748 /* copy LINK TRB to current waiting location */ 749 750 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 751 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 752 usb_pc_cpu_flush(td->page_cache); 753 754 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 755 usb_pc_cpu_flush(td->page_cache); 756 757 xhci_endpoint_doorbell(xfer); 758 } 759 } 760 761 /*------------------------------------------------------------------------* 762 * xhci_check_transfer 763 *------------------------------------------------------------------------*/ 764 static void 765 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 766 { 767 int64_t offset; 768 uint64_t td_event; 769 uint32_t temp; 770 uint32_t remainder; 771 uint8_t status; 772 uint8_t halted; 773 uint8_t epno; 774 uint8_t index; 775 uint8_t i; 776 777 /* decode TRB */ 778 td_event = le64toh(trb->qwTrb0); 779 temp = le32toh(trb->dwTrb2); 780 781 remainder = XHCI_TRB_2_REM_GET(temp); 782 status = XHCI_TRB_2_ERROR_GET(temp); 783 784 temp = le32toh(trb->dwTrb3); 785 epno = XHCI_TRB_3_EP_GET(temp); 786 index = XHCI_TRB_3_SLOT_GET(temp); 787 788 /* check if error means halted */ 789 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 790 status != XHCI_TRB_ERROR_SUCCESS); 791 792 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 793 index, epno, remainder, status); 794 795 if (index > sc->sc_noslot) { 796 DPRINTF("Invalid slot.\n"); 797 return; 798 } 799 800 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 801 DPRINTF("Invalid endpoint.\n"); 802 return; 803 } 804 805 /* try to find the USB transfer that generated the event */ 806 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 807 struct usb_xfer *xfer; 808 struct xhci_td *td; 809 struct xhci_endpoint_ext *pepext; 810 811 pepext = &sc->sc_hw.devs[index].endp[epno]; 812 813 xfer = pepext->xfer[i]; 814 if (xfer == NULL) 815 continue; 816 817 td = xfer->td_transfer_cache; 818 819 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 820 (long long)td_event, 821 (long long)td->td_self, 822 (long long)td->td_self + sizeof(td->td_trb)); 823 824 /* 825 * NOTE: Some XHCI implementations might not trigger 826 * an event on the last LINK TRB so we need to 827 * consider both the last and second last event 828 * address as conditions for a successful transfer. 829 * 830 * NOTE: We assume that the XHCI will only trigger one 831 * event per chain of TRBs. 832 */ 833 834 offset = td_event - td->td_self; 835 836 if (offset >= 0 && 837 offset < (int64_t)sizeof(td->td_trb)) { 838 839 usb_pc_cpu_invalidate(td->page_cache); 840 841 /* compute rest of remainder, if any */ 842 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 843 temp = le32toh(td->td_trb[i].dwTrb2); 844 remainder += XHCI_TRB_2_BYTES_GET(temp); 845 } 846 847 DPRINTFN(5, "New remainder: %u\n", remainder); 848 849 /* clear isochronous transfer errors */ 850 if (xfer->flags_int.isochronous_xfr) { 851 if (halted) { 852 halted = 0; 853 status = XHCI_TRB_ERROR_SUCCESS; 854 remainder = td->len; 855 } 856 } 857 858 /* "td->remainder" is verified later */ 859 td->remainder = remainder; 860 td->status = status; 861 862 usb_pc_cpu_flush(td->page_cache); 863 864 /* 865 * 1) Last transfer descriptor makes the 866 * transfer done 867 */ 868 if (((void *)td) == xfer->td_transfer_last) { 869 DPRINTF("TD is last\n"); 870 xhci_generic_done(xfer); 871 break; 872 } 873 874 /* 875 * 2) Any kind of error makes the transfer 876 * done 877 */ 878 if (halted) { 879 DPRINTF("TD has I/O error\n"); 880 xhci_generic_done(xfer); 881 break; 882 } 883 884 /* 885 * 3) If there is no alternate next transfer, 886 * a short packet also makes the transfer done 887 */ 888 if (td->remainder > 0) { 889 DPRINTF("TD has short pkt\n"); 890 if (xfer->flags_int.short_frames_ok || 891 xfer->flags_int.isochronous_xfr || 892 xfer->flags_int.control_xfr) { 893 /* follow the alt next */ 894 xfer->td_transfer_cache = td->alt_next; 895 xhci_activate_transfer(xfer); 896 break; 897 } 898 xhci_skip_transfer(xfer); 899 xhci_generic_done(xfer); 900 break; 901 } 902 903 /* 904 * 4) Transfer complete - go to next TD 905 */ 906 DPRINTF("Following next TD\n"); 907 xfer->td_transfer_cache = td->obj_next; 908 xhci_activate_transfer(xfer); 909 break; /* there should only be one match */ 910 } 911 } 912 } 913 914 static void 915 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 916 { 917 if (sc->sc_cmd_addr == trb->qwTrb0) { 918 DPRINTF("Received command event\n"); 919 sc->sc_cmd_result[0] = trb->dwTrb2; 920 sc->sc_cmd_result[1] = trb->dwTrb3; 921 cv_signal(&sc->sc_cmd_cv); 922 } 923 } 924 925 static void 926 xhci_interrupt_poll(struct xhci_softc *sc) 927 { 928 struct usb_page_search buf_res; 929 struct xhci_hw_root *phwr; 930 uint64_t addr; 931 uint32_t temp; 932 uint16_t i; 933 uint8_t event; 934 uint8_t j; 935 uint8_t k; 936 uint8_t t; 937 938 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 939 940 phwr = buf_res.buffer; 941 942 /* Receive any events */ 943 944 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 945 946 i = sc->sc_event_idx; 947 j = sc->sc_event_ccs; 948 t = 2; 949 950 while (1) { 951 952 temp = le32toh(phwr->hwr_events[i].dwTrb3); 953 954 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 955 956 if (j != k) 957 break; 958 959 event = XHCI_TRB_3_TYPE_GET(temp); 960 961 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 962 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 963 (long)le32toh(phwr->hwr_events[i].dwTrb2), 964 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 965 966 switch (event) { 967 case XHCI_TRB_EVENT_TRANSFER: 968 xhci_check_transfer(sc, &phwr->hwr_events[i]); 969 break; 970 case XHCI_TRB_EVENT_CMD_COMPLETE: 971 xhci_check_command(sc, &phwr->hwr_events[i]); 972 break; 973 default: 974 DPRINTF("Unhandled event = %u\n", event); 975 break; 976 } 977 978 i++; 979 980 if (i == XHCI_MAX_EVENTS) { 981 i = 0; 982 j ^= 1; 983 984 /* check for timeout */ 985 if (!--t) 986 break; 987 } 988 } 989 990 sc->sc_event_idx = i; 991 sc->sc_event_ccs = j; 992 993 /* 994 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 995 * latched. That means to activate the register we need to 996 * write both the low and high double word of the 64-bit 997 * register. 998 */ 999 1000 addr = (uint32_t)buf_res.physaddr; 1001 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1002 1003 /* try to clear busy bit */ 1004 addr |= XHCI_ERDP_LO_BUSY; 1005 1006 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1007 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1008 } 1009 1010 static usb_error_t 1011 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1012 uint16_t timeout_ms) 1013 { 1014 struct usb_page_search buf_res; 1015 struct xhci_hw_root *phwr; 1016 uint64_t addr; 1017 uint32_t temp; 1018 uint8_t i; 1019 uint8_t j; 1020 int err; 1021 1022 XHCI_CMD_ASSERT_LOCKED(sc); 1023 1024 /* get hardware root structure */ 1025 1026 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1027 1028 phwr = buf_res.buffer; 1029 1030 /* Queue command */ 1031 1032 USB_BUS_LOCK(&sc->sc_bus); 1033 1034 i = sc->sc_command_idx; 1035 j = sc->sc_command_ccs; 1036 1037 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1038 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1039 (long long)le64toh(trb->qwTrb0), 1040 (long)le32toh(trb->dwTrb2), 1041 (long)le32toh(trb->dwTrb3)); 1042 1043 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1044 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1045 1046 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1047 1048 temp = trb->dwTrb3; 1049 1050 if (j) 1051 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1052 else 1053 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1054 1055 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1056 1057 phwr->hwr_commands[i].dwTrb3 = temp; 1058 1059 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1060 1061 addr = buf_res.physaddr; 1062 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1063 1064 sc->sc_cmd_addr = htole64(addr); 1065 1066 i++; 1067 1068 if (i == (XHCI_MAX_COMMANDS - 1)) { 1069 1070 if (j) { 1071 temp = htole32(XHCI_TRB_3_TC_BIT | 1072 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1073 XHCI_TRB_3_CYCLE_BIT); 1074 } else { 1075 temp = htole32(XHCI_TRB_3_TC_BIT | 1076 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1077 } 1078 1079 phwr->hwr_commands[i].dwTrb3 = temp; 1080 1081 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1082 1083 i = 0; 1084 j ^= 1; 1085 } 1086 1087 sc->sc_command_idx = i; 1088 sc->sc_command_ccs = j; 1089 1090 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1091 1092 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1093 USB_MS_TO_TICKS(timeout_ms)); 1094 1095 if (err) { 1096 DPRINTFN(0, "Command timeout!\n"); 1097 err = USB_ERR_TIMEOUT; 1098 trb->dwTrb2 = 0; 1099 trb->dwTrb3 = 0; 1100 } else { 1101 temp = le32toh(sc->sc_cmd_result[0]); 1102 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1103 err = USB_ERR_IOERROR; 1104 1105 trb->dwTrb2 = sc->sc_cmd_result[0]; 1106 trb->dwTrb3 = sc->sc_cmd_result[1]; 1107 } 1108 1109 USB_BUS_UNLOCK(&sc->sc_bus); 1110 1111 return (err); 1112 } 1113 1114 #if 0 1115 static usb_error_t 1116 xhci_cmd_nop(struct xhci_softc *sc) 1117 { 1118 struct xhci_trb trb; 1119 uint32_t temp; 1120 1121 DPRINTF("\n"); 1122 1123 trb.qwTrb0 = 0; 1124 trb.dwTrb2 = 0; 1125 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1126 1127 trb.dwTrb3 = htole32(temp); 1128 1129 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1130 } 1131 #endif 1132 1133 static usb_error_t 1134 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1135 { 1136 struct xhci_trb trb; 1137 uint32_t temp; 1138 usb_error_t err; 1139 1140 DPRINTF("\n"); 1141 1142 trb.qwTrb0 = 0; 1143 trb.dwTrb2 = 0; 1144 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1145 1146 err = xhci_do_command(sc, &trb, 100 /* ms */); 1147 if (err) 1148 goto done; 1149 1150 temp = le32toh(trb.dwTrb3); 1151 1152 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1153 1154 done: 1155 return (err); 1156 } 1157 1158 static usb_error_t 1159 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1160 { 1161 struct xhci_trb trb; 1162 uint32_t temp; 1163 1164 DPRINTF("\n"); 1165 1166 trb.qwTrb0 = 0; 1167 trb.dwTrb2 = 0; 1168 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1169 XHCI_TRB_3_SLOT_SET(slot_id); 1170 1171 trb.dwTrb3 = htole32(temp); 1172 1173 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1174 } 1175 1176 static usb_error_t 1177 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1178 uint8_t bsr, uint8_t slot_id) 1179 { 1180 struct xhci_trb trb; 1181 uint32_t temp; 1182 1183 DPRINTF("\n"); 1184 1185 trb.qwTrb0 = htole64(input_ctx); 1186 trb.dwTrb2 = 0; 1187 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1188 XHCI_TRB_3_SLOT_SET(slot_id); 1189 1190 if (bsr) 1191 temp |= XHCI_TRB_3_BSR_BIT; 1192 1193 trb.dwTrb3 = htole32(temp); 1194 1195 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1196 } 1197 1198 static usb_error_t 1199 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1200 { 1201 struct usb_page_search buf_inp; 1202 struct usb_page_search buf_dev; 1203 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1204 struct xhci_hw_dev *hdev; 1205 struct xhci_dev_ctx *pdev; 1206 struct xhci_endpoint_ext *pepext; 1207 uint32_t temp; 1208 uint16_t mps; 1209 usb_error_t err; 1210 uint8_t index; 1211 1212 /* the root HUB case is not handled here */ 1213 if (udev->parent_hub == NULL) 1214 return (USB_ERR_INVAL); 1215 1216 index = udev->controller_slot_id; 1217 1218 hdev = &sc->sc_hw.devs[index]; 1219 1220 if (mtx != NULL) 1221 mtx_unlock(mtx); 1222 1223 XHCI_CMD_LOCK(sc); 1224 1225 switch (hdev->state) { 1226 case XHCI_ST_DEFAULT: 1227 case XHCI_ST_ENABLED: 1228 1229 hdev->state = XHCI_ST_ENABLED; 1230 1231 /* set configure mask to slot and EP0 */ 1232 xhci_configure_mask(udev, 3, 0); 1233 1234 /* configure input slot context structure */ 1235 err = xhci_configure_device(udev); 1236 1237 if (err != 0) { 1238 DPRINTF("Could not configure device\n"); 1239 break; 1240 } 1241 1242 /* configure input endpoint context structure */ 1243 switch (udev->speed) { 1244 case USB_SPEED_LOW: 1245 case USB_SPEED_FULL: 1246 mps = 8; 1247 break; 1248 case USB_SPEED_HIGH: 1249 mps = 64; 1250 break; 1251 default: 1252 mps = 512; 1253 break; 1254 } 1255 1256 pepext = xhci_get_endpoint_ext(udev, 1257 &udev->ctrl_ep_desc); 1258 err = xhci_configure_endpoint(udev, 1259 &udev->ctrl_ep_desc, pepext->physaddr, 1260 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1261 1262 if (err != 0) { 1263 DPRINTF("Could not configure default endpoint\n"); 1264 break; 1265 } 1266 1267 /* execute set address command */ 1268 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1269 1270 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1271 (address == 0), index); 1272 1273 if (err != 0) { 1274 DPRINTF("Could not set address " 1275 "for slot %u.\n", index); 1276 if (address != 0) 1277 break; 1278 } 1279 1280 /* update device address to new value */ 1281 1282 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1283 pdev = buf_dev.buffer; 1284 usb_pc_cpu_invalidate(&hdev->device_pc); 1285 1286 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1287 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1288 1289 /* update device state to new value */ 1290 1291 if (address != 0) 1292 hdev->state = XHCI_ST_ADDRESSED; 1293 else 1294 hdev->state = XHCI_ST_DEFAULT; 1295 break; 1296 1297 default: 1298 DPRINTF("Wrong state for set address.\n"); 1299 err = USB_ERR_IOERROR; 1300 break; 1301 } 1302 XHCI_CMD_UNLOCK(sc); 1303 1304 if (mtx != NULL) 1305 mtx_lock(mtx); 1306 1307 return (err); 1308 } 1309 1310 static usb_error_t 1311 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1312 uint8_t deconfigure, uint8_t slot_id) 1313 { 1314 struct xhci_trb trb; 1315 uint32_t temp; 1316 1317 DPRINTF("\n"); 1318 1319 trb.qwTrb0 = htole64(input_ctx); 1320 trb.dwTrb2 = 0; 1321 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1322 XHCI_TRB_3_SLOT_SET(slot_id); 1323 1324 if (deconfigure) 1325 temp |= XHCI_TRB_3_DCEP_BIT; 1326 1327 trb.dwTrb3 = htole32(temp); 1328 1329 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1330 } 1331 1332 static usb_error_t 1333 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1334 uint8_t slot_id) 1335 { 1336 struct xhci_trb trb; 1337 uint32_t temp; 1338 1339 DPRINTF("\n"); 1340 1341 trb.qwTrb0 = htole64(input_ctx); 1342 trb.dwTrb2 = 0; 1343 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1344 XHCI_TRB_3_SLOT_SET(slot_id); 1345 trb.dwTrb3 = htole32(temp); 1346 1347 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1348 } 1349 1350 static usb_error_t 1351 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1352 uint8_t ep_id, uint8_t slot_id) 1353 { 1354 struct xhci_trb trb; 1355 uint32_t temp; 1356 1357 DPRINTF("\n"); 1358 1359 trb.qwTrb0 = 0; 1360 trb.dwTrb2 = 0; 1361 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1362 XHCI_TRB_3_SLOT_SET(slot_id) | 1363 XHCI_TRB_3_EP_SET(ep_id); 1364 1365 if (preserve) 1366 temp |= XHCI_TRB_3_PRSV_BIT; 1367 1368 trb.dwTrb3 = htole32(temp); 1369 1370 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1371 } 1372 1373 static usb_error_t 1374 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1375 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1376 { 1377 struct xhci_trb trb; 1378 uint32_t temp; 1379 1380 DPRINTF("\n"); 1381 1382 trb.qwTrb0 = htole64(dequeue_ptr); 1383 1384 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1385 trb.dwTrb2 = htole32(temp); 1386 1387 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1388 XHCI_TRB_3_SLOT_SET(slot_id) | 1389 XHCI_TRB_3_EP_SET(ep_id); 1390 trb.dwTrb3 = htole32(temp); 1391 1392 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1393 } 1394 1395 static usb_error_t 1396 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1397 uint8_t ep_id, uint8_t slot_id) 1398 { 1399 struct xhci_trb trb; 1400 uint32_t temp; 1401 1402 DPRINTF("\n"); 1403 1404 trb.qwTrb0 = 0; 1405 trb.dwTrb2 = 0; 1406 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1407 XHCI_TRB_3_SLOT_SET(slot_id) | 1408 XHCI_TRB_3_EP_SET(ep_id); 1409 1410 if (suspend) 1411 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1412 1413 trb.dwTrb3 = htole32(temp); 1414 1415 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1416 } 1417 1418 static usb_error_t 1419 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1420 { 1421 struct xhci_trb trb; 1422 uint32_t temp; 1423 1424 DPRINTF("\n"); 1425 1426 trb.qwTrb0 = 0; 1427 trb.dwTrb2 = 0; 1428 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1429 XHCI_TRB_3_SLOT_SET(slot_id); 1430 1431 trb.dwTrb3 = htole32(temp); 1432 1433 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1434 } 1435 1436 /*------------------------------------------------------------------------* 1437 * xhci_interrupt - XHCI interrupt handler 1438 *------------------------------------------------------------------------*/ 1439 void 1440 xhci_interrupt(struct xhci_softc *sc) 1441 { 1442 uint32_t status; 1443 uint32_t temp; 1444 1445 USB_BUS_LOCK(&sc->sc_bus); 1446 1447 status = XREAD4(sc, oper, XHCI_USBSTS); 1448 1449 /* acknowledge interrupts */ 1450 1451 XWRITE4(sc, oper, XHCI_USBSTS, status); 1452 1453 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1454 1455 /* acknowledge pending event */ 1456 1457 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1458 1459 DPRINTFN(16, "real interrupt (sts=0x%08x, " 1460 "iman=0x%08x)\n", status, temp); 1461 1462 if (status != 0) { 1463 if (status & XHCI_STS_PCD) { 1464 xhci_root_intr(sc); 1465 } 1466 1467 if (status & XHCI_STS_HCH) { 1468 printf("%s: host controller halted\n", 1469 __FUNCTION__); 1470 } 1471 1472 if (status & XHCI_STS_HSE) { 1473 printf("%s: host system error\n", 1474 __FUNCTION__); 1475 } 1476 1477 if (status & XHCI_STS_HCE) { 1478 printf("%s: host controller error\n", 1479 __FUNCTION__); 1480 } 1481 } 1482 1483 xhci_interrupt_poll(sc); 1484 1485 USB_BUS_UNLOCK(&sc->sc_bus); 1486 } 1487 1488 /*------------------------------------------------------------------------* 1489 * xhci_timeout - XHCI timeout handler 1490 *------------------------------------------------------------------------*/ 1491 static void 1492 xhci_timeout(void *arg) 1493 { 1494 struct usb_xfer *xfer = arg; 1495 1496 DPRINTF("xfer=%p\n", xfer); 1497 1498 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1499 1500 /* transfer is transferred */ 1501 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1502 } 1503 1504 static void 1505 xhci_do_poll(struct usb_bus *bus) 1506 { 1507 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1508 1509 USB_BUS_LOCK(&sc->sc_bus); 1510 xhci_interrupt_poll(sc); 1511 USB_BUS_UNLOCK(&sc->sc_bus); 1512 } 1513 1514 static void 1515 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1516 { 1517 struct usb_page_search buf_res; 1518 struct xhci_td *td; 1519 struct xhci_td *td_next; 1520 struct xhci_td *td_alt_next; 1521 uint32_t buf_offset; 1522 uint32_t average; 1523 uint32_t len_old; 1524 uint32_t dword; 1525 uint8_t shortpkt_old; 1526 uint8_t precompute; 1527 uint8_t x; 1528 1529 td_alt_next = NULL; 1530 buf_offset = 0; 1531 shortpkt_old = temp->shortpkt; 1532 len_old = temp->len; 1533 precompute = 1; 1534 1535 restart: 1536 1537 td = temp->td; 1538 td_next = temp->td_next; 1539 1540 while (1) { 1541 1542 if (temp->len == 0) { 1543 1544 if (temp->shortpkt) 1545 break; 1546 1547 /* send a Zero Length Packet, ZLP, last */ 1548 1549 temp->shortpkt = 1; 1550 average = 0; 1551 1552 } else { 1553 1554 average = temp->average; 1555 1556 if (temp->len < average) { 1557 if (temp->len % temp->max_packet_size) { 1558 temp->shortpkt = 1; 1559 } 1560 average = temp->len; 1561 } 1562 } 1563 1564 if (td_next == NULL) 1565 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1566 1567 /* get next TD */ 1568 1569 td = td_next; 1570 td_next = td->obj_next; 1571 1572 /* check if we are pre-computing */ 1573 1574 if (precompute) { 1575 1576 /* update remaining length */ 1577 1578 temp->len -= average; 1579 1580 continue; 1581 } 1582 /* fill out current TD */ 1583 1584 td->len = average; 1585 td->remainder = 0; 1586 td->status = 0; 1587 1588 /* update remaining length */ 1589 1590 temp->len -= average; 1591 1592 /* reset TRB index */ 1593 1594 x = 0; 1595 1596 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1597 /* immediate data */ 1598 1599 if (average > 8) 1600 average = 8; 1601 1602 td->td_trb[0].qwTrb0 = 0; 1603 1604 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1605 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1606 average); 1607 1608 dword = XHCI_TRB_2_BYTES_SET(8) | 1609 XHCI_TRB_2_TDSZ_SET(0) | 1610 XHCI_TRB_2_IRQ_SET(0); 1611 1612 td->td_trb[0].dwTrb2 = htole32(dword); 1613 1614 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1615 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1616 1617 /* check wLength */ 1618 if (td->td_trb[0].qwTrb0 & 1619 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1620 if (td->td_trb[0].qwTrb0 & htole64(1)) 1621 dword |= XHCI_TRB_3_TRT_IN; 1622 else 1623 dword |= XHCI_TRB_3_TRT_OUT; 1624 } 1625 1626 td->td_trb[0].dwTrb3 = htole32(dword); 1627 #ifdef USB_DEBUG 1628 xhci_dump_trb(&td->td_trb[x]); 1629 #endif 1630 x++; 1631 1632 } else do { 1633 1634 uint32_t npkt; 1635 1636 /* fill out buffer pointers */ 1637 1638 if (average == 0) { 1639 npkt = 1; 1640 memset(&buf_res, 0, sizeof(buf_res)); 1641 } else { 1642 usbd_get_page(temp->pc, temp->offset + 1643 buf_offset, &buf_res); 1644 1645 /* get length to end of page */ 1646 if (buf_res.length > average) 1647 buf_res.length = average; 1648 1649 /* check for maximum length */ 1650 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1651 buf_res.length = XHCI_TD_PAGE_SIZE; 1652 1653 /* setup npkt */ 1654 npkt = (average + temp->max_packet_size - 1) / 1655 temp->max_packet_size; 1656 1657 if (npkt > 31) 1658 npkt = 31; 1659 } 1660 1661 /* fill out TRB's */ 1662 td->td_trb[x].qwTrb0 = 1663 htole64((uint64_t)buf_res.physaddr); 1664 1665 dword = 1666 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1667 XHCI_TRB_2_TDSZ_SET(npkt) | 1668 XHCI_TRB_2_IRQ_SET(0); 1669 1670 td->td_trb[x].dwTrb2 = htole32(dword); 1671 1672 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1673 XHCI_TRB_3_TYPE_SET(temp->trb_type) | 1674 (temp->do_isoc_sync ? 1675 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) : 1676 XHCI_TRB_3_ISO_SIA_BIT) | 1677 XHCI_TRB_3_TBC_SET(temp->tbc) | 1678 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1679 1680 temp->do_isoc_sync = 0; 1681 1682 if (temp->direction == UE_DIR_IN) { 1683 dword |= XHCI_TRB_3_DIR_IN; 1684 1685 /* 1686 * NOTE: Only the SETUP stage should 1687 * use the IDT bit. Else transactions 1688 * can be sent using the wrong data 1689 * toggle value. 1690 */ 1691 if (temp->trb_type != 1692 XHCI_TRB_TYPE_SETUP_STAGE && 1693 temp->trb_type != 1694 XHCI_TRB_TYPE_STATUS_STAGE) 1695 dword |= XHCI_TRB_3_ISP_BIT; 1696 } 1697 1698 td->td_trb[x].dwTrb3 = htole32(dword); 1699 1700 average -= buf_res.length; 1701 buf_offset += buf_res.length; 1702 #ifdef USB_DEBUG 1703 xhci_dump_trb(&td->td_trb[x]); 1704 #endif 1705 x++; 1706 1707 } while (average != 0); 1708 1709 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1710 1711 /* store number of data TRB's */ 1712 1713 td->ntrb = x; 1714 1715 DPRINTF("NTRB=%u\n", x); 1716 1717 /* fill out link TRB */ 1718 1719 if (td_next != NULL) { 1720 /* link the current TD with the next one */ 1721 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1722 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1723 } else { 1724 /* this field will get updated later */ 1725 DPRINTF("NOLINK\n"); 1726 } 1727 1728 dword = XHCI_TRB_2_IRQ_SET(0); 1729 1730 td->td_trb[x].dwTrb2 = htole32(dword); 1731 1732 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1733 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT; 1734 1735 td->td_trb[x].dwTrb3 = htole32(dword); 1736 1737 td->alt_next = td_alt_next; 1738 #ifdef USB_DEBUG 1739 xhci_dump_trb(&td->td_trb[x]); 1740 #endif 1741 usb_pc_cpu_flush(td->page_cache); 1742 } 1743 1744 if (precompute) { 1745 precompute = 0; 1746 1747 /* setup alt next pointer, if any */ 1748 if (temp->last_frame) { 1749 td_alt_next = NULL; 1750 } else { 1751 /* we use this field internally */ 1752 td_alt_next = td_next; 1753 } 1754 1755 /* restore */ 1756 temp->shortpkt = shortpkt_old; 1757 temp->len = len_old; 1758 goto restart; 1759 } 1760 1761 /* remove cycle bit from first if we are stepping the TRBs */ 1762 if (temp->step_td) 1763 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1764 1765 /* remove chain bit because this is the last TRB in the chain */ 1766 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1767 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1768 1769 usb_pc_cpu_flush(td->page_cache); 1770 1771 temp->td = td; 1772 temp->td_next = td_next; 1773 } 1774 1775 static void 1776 xhci_setup_generic_chain(struct usb_xfer *xfer) 1777 { 1778 struct xhci_std_temp temp; 1779 struct xhci_td *td; 1780 uint32_t x; 1781 uint32_t y; 1782 uint8_t mult; 1783 1784 temp.do_isoc_sync = 0; 1785 temp.step_td = 0; 1786 temp.tbc = 0; 1787 temp.tlbpc = 0; 1788 temp.average = xfer->max_hc_frame_size; 1789 temp.max_packet_size = xfer->max_packet_size; 1790 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1791 temp.pc = NULL; 1792 temp.last_frame = 0; 1793 temp.offset = 0; 1794 temp.multishort = xfer->flags_int.isochronous_xfr || 1795 xfer->flags_int.control_xfr || 1796 xfer->flags_int.short_frames_ok; 1797 1798 /* toggle the DMA set we are using */ 1799 xfer->flags_int.curr_dma_set ^= 1; 1800 1801 /* get next DMA set */ 1802 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1803 1804 temp.td = NULL; 1805 temp.td_next = td; 1806 1807 xfer->td_transfer_first = td; 1808 xfer->td_transfer_cache = td; 1809 1810 if (xfer->flags_int.isochronous_xfr) { 1811 uint8_t shift; 1812 1813 /* compute multiplier for ISOCHRONOUS transfers */ 1814 mult = xfer->endpoint->ecomp ? 1815 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 1816 : 0; 1817 /* check for USB 2.0 multiplier */ 1818 if (mult == 0) { 1819 mult = (xfer->endpoint->edesc-> 1820 wMaxPacketSize[1] >> 3) & 3; 1821 } 1822 /* range check */ 1823 if (mult > 2) 1824 mult = 3; 1825 else 1826 mult++; 1827 1828 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 1829 1830 DPRINTF("MFINDEX=0x%08x\n", x); 1831 1832 switch (usbd_get_speed(xfer->xroot->udev)) { 1833 case USB_SPEED_FULL: 1834 shift = 3; 1835 temp.isoc_delta = 8; /* 1ms */ 1836 x += temp.isoc_delta - 1; 1837 x &= ~(temp.isoc_delta - 1); 1838 break; 1839 default: 1840 shift = usbd_xfer_get_fps_shift(xfer); 1841 temp.isoc_delta = 1U << shift; 1842 x += temp.isoc_delta - 1; 1843 x &= ~(temp.isoc_delta - 1); 1844 /* simple frame load balancing */ 1845 x += xfer->endpoint->usb_uframe; 1846 break; 1847 } 1848 1849 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 1850 1851 if ((xfer->endpoint->is_synced == 0) || 1852 (y < (xfer->nframes << shift)) || 1853 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 1854 /* 1855 * If there is data underflow or the pipe 1856 * queue is empty we schedule the transfer a 1857 * few frames ahead of the current frame 1858 * position. Else two isochronous transfers 1859 * might overlap. 1860 */ 1861 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 1862 xfer->endpoint->is_synced = 1; 1863 temp.do_isoc_sync = 1; 1864 1865 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1866 } 1867 1868 /* compute isochronous completion time */ 1869 1870 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 1871 1872 xfer->isoc_time_complete = 1873 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 1874 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 1875 1876 x = 0; 1877 temp.isoc_frame = xfer->endpoint->isoc_next; 1878 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 1879 1880 xfer->endpoint->isoc_next += xfer->nframes << shift; 1881 1882 } else if (xfer->flags_int.control_xfr) { 1883 1884 /* check if we should prepend a setup message */ 1885 1886 if (xfer->flags_int.control_hdr) { 1887 1888 temp.len = xfer->frlengths[0]; 1889 temp.pc = xfer->frbuffers + 0; 1890 temp.shortpkt = temp.len ? 1 : 0; 1891 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 1892 temp.direction = 0; 1893 1894 /* check for last frame */ 1895 if (xfer->nframes == 1) { 1896 /* no STATUS stage yet, SETUP is last */ 1897 if (xfer->flags_int.control_act) 1898 temp.last_frame = 1; 1899 } 1900 1901 xhci_setup_generic_chain_sub(&temp); 1902 } 1903 x = 1; 1904 mult = 1; 1905 temp.isoc_delta = 0; 1906 temp.isoc_frame = 0; 1907 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 1908 } else { 1909 x = 0; 1910 mult = 1; 1911 temp.isoc_delta = 0; 1912 temp.isoc_frame = 0; 1913 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 1914 } 1915 1916 if (x != xfer->nframes) { 1917 /* setup page_cache pointer */ 1918 temp.pc = xfer->frbuffers + x; 1919 /* set endpoint direction */ 1920 temp.direction = UE_GET_DIR(xfer->endpointno); 1921 } 1922 1923 while (x != xfer->nframes) { 1924 1925 /* DATA0 / DATA1 message */ 1926 1927 temp.len = xfer->frlengths[x]; 1928 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 1929 x != 0 && temp.multishort == 0); 1930 1931 x++; 1932 1933 if (x == xfer->nframes) { 1934 if (xfer->flags_int.control_xfr) { 1935 /* no STATUS stage yet, DATA is last */ 1936 if (xfer->flags_int.control_act) 1937 temp.last_frame = 1; 1938 } else { 1939 temp.last_frame = 1; 1940 } 1941 } 1942 if (temp.len == 0) { 1943 1944 /* make sure that we send an USB packet */ 1945 1946 temp.shortpkt = 0; 1947 1948 temp.tbc = 0; 1949 temp.tlbpc = mult - 1; 1950 1951 } else if (xfer->flags_int.isochronous_xfr) { 1952 1953 uint8_t tdpc; 1954 1955 /* 1956 * Isochronous transfers don't have short 1957 * packet termination: 1958 */ 1959 1960 temp.shortpkt = 1; 1961 1962 /* isochronous transfers have a transfer limit */ 1963 1964 if (temp.len > xfer->max_frame_size) 1965 temp.len = xfer->max_frame_size; 1966 1967 /* compute TD packet count */ 1968 tdpc = (temp.len + xfer->max_packet_size - 1) / 1969 xfer->max_packet_size; 1970 1971 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 1972 temp.tlbpc = (tdpc % mult); 1973 1974 if (temp.tlbpc == 0) 1975 temp.tlbpc = mult - 1; 1976 else 1977 temp.tlbpc--; 1978 } else { 1979 1980 /* regular data transfer */ 1981 1982 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 1983 } 1984 1985 xhci_setup_generic_chain_sub(&temp); 1986 1987 if (xfer->flags_int.isochronous_xfr) { 1988 temp.offset += xfer->frlengths[x - 1]; 1989 temp.isoc_frame += temp.isoc_delta; 1990 } else { 1991 /* get next Page Cache pointer */ 1992 temp.pc = xfer->frbuffers + x; 1993 } 1994 } 1995 1996 /* check if we should append a status stage */ 1997 1998 if (xfer->flags_int.control_xfr && 1999 !xfer->flags_int.control_act) { 2000 2001 /* 2002 * Send a DATA1 message and invert the current 2003 * endpoint direction. 2004 */ 2005 temp.step_td = (xfer->nframes != 0); 2006 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2007 temp.len = 0; 2008 temp.pc = NULL; 2009 temp.shortpkt = 0; 2010 temp.last_frame = 1; 2011 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2012 2013 xhci_setup_generic_chain_sub(&temp); 2014 } 2015 2016 td = temp.td; 2017 2018 /* must have at least one frame! */ 2019 2020 xfer->td_transfer_last = td; 2021 2022 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2023 } 2024 2025 static void 2026 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2027 { 2028 struct usb_page_search buf_res; 2029 struct xhci_dev_ctx_addr *pdctxa; 2030 2031 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2032 2033 pdctxa = buf_res.buffer; 2034 2035 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2036 2037 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2038 2039 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2040 } 2041 2042 static usb_error_t 2043 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2044 { 2045 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2046 struct usb_page_search buf_inp; 2047 struct xhci_input_dev_ctx *pinp; 2048 uint8_t index; 2049 2050 index = udev->controller_slot_id; 2051 2052 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2053 2054 pinp = buf_inp.buffer; 2055 2056 if (drop) { 2057 mask &= XHCI_INCTX_NON_CTRL_MASK; 2058 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2059 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2060 } else { 2061 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2062 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2063 } 2064 return (0); 2065 } 2066 2067 static usb_error_t 2068 xhci_configure_endpoint(struct usb_device *udev, 2069 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr, 2070 uint16_t interval, uint8_t max_packet_count, uint8_t mult, 2071 uint8_t fps_shift, uint16_t max_packet_size, 2072 uint16_t max_frame_size, uint8_t ep_mode) 2073 { 2074 struct usb_page_search buf_inp; 2075 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2076 struct xhci_input_dev_ctx *pinp; 2077 uint32_t temp; 2078 uint8_t index; 2079 uint8_t epno; 2080 uint8_t type; 2081 2082 index = udev->controller_slot_id; 2083 2084 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2085 2086 pinp = buf_inp.buffer; 2087 2088 epno = edesc->bEndpointAddress; 2089 type = edesc->bmAttributes & UE_XFERTYPE; 2090 2091 if (type == UE_CONTROL) 2092 epno |= UE_DIR_IN; 2093 2094 epno = XHCI_EPNO2EPID(epno); 2095 2096 if (epno == 0) 2097 return (USB_ERR_NO_PIPE); /* invalid */ 2098 2099 if (max_packet_count == 0) 2100 return (USB_ERR_BAD_BUFSIZE); 2101 2102 max_packet_count--; 2103 2104 if (mult == 0) 2105 return (USB_ERR_BAD_BUFSIZE); 2106 2107 if (ep_mode == USB_EP_MODE_STREAMS) { 2108 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2109 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2110 XHCI_EPCTX_0_LSA_SET(1); 2111 2112 ring_addr += sizeof(struct xhci_trb) * 2113 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2114 } else { 2115 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2116 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2117 XHCI_EPCTX_0_LSA_SET(0); 2118 2119 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2120 } 2121 2122 switch (udev->speed) { 2123 case USB_SPEED_FULL: 2124 case USB_SPEED_LOW: 2125 /* 1ms -> 125us */ 2126 fps_shift += 3; 2127 break; 2128 default: 2129 break; 2130 } 2131 2132 switch (type) { 2133 case UE_INTERRUPT: 2134 if (fps_shift > 3) 2135 fps_shift--; 2136 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2137 break; 2138 case UE_ISOCHRONOUS: 2139 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2140 2141 switch (udev->speed) { 2142 case USB_SPEED_SUPER: 2143 if (mult > 3) 2144 mult = 3; 2145 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2146 max_packet_count /= mult; 2147 break; 2148 default: 2149 break; 2150 } 2151 break; 2152 default: 2153 break; 2154 } 2155 2156 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2157 2158 temp = 2159 XHCI_EPCTX_1_HID_SET(0) | 2160 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2161 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2162 2163 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2164 if (type != UE_ISOCHRONOUS) 2165 temp |= XHCI_EPCTX_1_CERR_SET(3); 2166 } 2167 2168 switch (type) { 2169 case UE_CONTROL: 2170 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2171 break; 2172 case UE_ISOCHRONOUS: 2173 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2174 break; 2175 case UE_BULK: 2176 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2177 break; 2178 default: 2179 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2180 break; 2181 } 2182 2183 /* check for IN direction */ 2184 if (epno & 1) 2185 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2186 2187 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2188 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2189 2190 switch (edesc->bmAttributes & UE_XFERTYPE) { 2191 case UE_INTERRUPT: 2192 case UE_ISOCHRONOUS: 2193 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2194 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2195 max_frame_size)); 2196 break; 2197 case UE_CONTROL: 2198 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2199 break; 2200 default: 2201 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2202 break; 2203 } 2204 2205 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2206 2207 #ifdef USB_DEBUG 2208 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2209 #endif 2210 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2211 2212 return (0); /* success */ 2213 } 2214 2215 static usb_error_t 2216 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2217 { 2218 struct xhci_endpoint_ext *pepext; 2219 struct usb_endpoint_ss_comp_descriptor *ecomp; 2220 usb_stream_t x; 2221 2222 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2223 xfer->endpoint->edesc); 2224 2225 ecomp = xfer->endpoint->ecomp; 2226 2227 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2228 uint64_t temp; 2229 2230 /* halt any transfers */ 2231 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2232 2233 /* compute start of TRB ring for stream "x" */ 2234 temp = pepext->physaddr + 2235 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2236 XHCI_SCTX_0_SCT_SEC_TR_RING; 2237 2238 /* make tree structure */ 2239 pepext->trb[(XHCI_MAX_TRANSFERS * 2240 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2241 2242 /* reserved fields */ 2243 pepext->trb[(XHCI_MAX_TRANSFERS * 2244 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2245 pepext->trb[(XHCI_MAX_TRANSFERS * 2246 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2247 } 2248 usb_pc_cpu_flush(pepext->page_cache); 2249 2250 return (xhci_configure_endpoint(xfer->xroot->udev, 2251 xfer->endpoint->edesc, pepext->physaddr, 2252 xfer->interval, xfer->max_packet_count, 2253 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2254 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2255 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2256 } 2257 2258 static usb_error_t 2259 xhci_configure_device(struct usb_device *udev) 2260 { 2261 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2262 struct usb_page_search buf_inp; 2263 struct usb_page_cache *pcinp; 2264 struct xhci_input_dev_ctx *pinp; 2265 struct usb_device *hubdev; 2266 uint32_t temp; 2267 uint32_t route; 2268 uint32_t rh_port; 2269 uint8_t is_hub; 2270 uint8_t index; 2271 uint8_t depth; 2272 2273 index = udev->controller_slot_id; 2274 2275 DPRINTF("index=%u\n", index); 2276 2277 pcinp = &sc->sc_hw.devs[index].input_pc; 2278 2279 usbd_get_page(pcinp, 0, &buf_inp); 2280 2281 pinp = buf_inp.buffer; 2282 2283 rh_port = 0; 2284 route = 0; 2285 2286 /* figure out route string and root HUB port number */ 2287 2288 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2289 2290 if (hubdev->parent_hub == NULL) 2291 break; 2292 2293 depth = hubdev->parent_hub->depth; 2294 2295 /* 2296 * NOTE: HS/FS/LS devices and the SS root HUB can have 2297 * more than 15 ports 2298 */ 2299 2300 rh_port = hubdev->port_no; 2301 2302 if (depth == 0) 2303 break; 2304 2305 if (rh_port > 15) 2306 rh_port = 15; 2307 2308 if (depth < 6) 2309 route |= rh_port << (4 * (depth - 1)); 2310 } 2311 2312 DPRINTF("Route=0x%08x\n", route); 2313 2314 temp = XHCI_SCTX_0_ROUTE_SET(route); 2315 2316 switch (sc->sc_hw.devs[index].state) { 2317 case XHCI_ST_CONFIGURED: 2318 temp |= XHCI_SCTX_0_CTX_NUM_SET(XHCI_MAX_ENDPOINTS - 1); 2319 break; 2320 default: 2321 temp |= XHCI_SCTX_0_CTX_NUM_SET(1); 2322 break; 2323 } 2324 2325 switch (udev->speed) { 2326 case USB_SPEED_LOW: 2327 temp |= XHCI_SCTX_0_SPEED_SET(2); 2328 if (udev->parent_hs_hub != NULL && 2329 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2330 UDPROTO_HSHUBMTT) { 2331 DPRINTF("Device inherits MTT\n"); 2332 temp |= XHCI_SCTX_0_MTT_SET(1); 2333 } 2334 break; 2335 case USB_SPEED_HIGH: 2336 temp |= XHCI_SCTX_0_SPEED_SET(3); 2337 if (sc->sc_hw.devs[index].nports != 0 && 2338 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2339 DPRINTF("HUB supports MTT\n"); 2340 temp |= XHCI_SCTX_0_MTT_SET(1); 2341 } 2342 break; 2343 case USB_SPEED_FULL: 2344 temp |= XHCI_SCTX_0_SPEED_SET(1); 2345 if (udev->parent_hs_hub != NULL && 2346 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2347 UDPROTO_HSHUBMTT) { 2348 DPRINTF("Device inherits MTT\n"); 2349 temp |= XHCI_SCTX_0_MTT_SET(1); 2350 } 2351 break; 2352 default: 2353 temp |= XHCI_SCTX_0_SPEED_SET(4); 2354 break; 2355 } 2356 2357 is_hub = sc->sc_hw.devs[index].nports != 0 && 2358 (udev->speed == USB_SPEED_SUPER || 2359 udev->speed == USB_SPEED_HIGH); 2360 2361 if (is_hub) 2362 temp |= XHCI_SCTX_0_HUB_SET(1); 2363 2364 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2365 2366 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2367 2368 if (is_hub) { 2369 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2370 sc->sc_hw.devs[index].nports); 2371 } 2372 2373 switch (udev->speed) { 2374 case USB_SPEED_SUPER: 2375 switch (sc->sc_hw.devs[index].state) { 2376 case XHCI_ST_ADDRESSED: 2377 case XHCI_ST_CONFIGURED: 2378 /* enable power save */ 2379 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2380 break; 2381 default: 2382 /* disable power save */ 2383 break; 2384 } 2385 break; 2386 default: 2387 break; 2388 } 2389 2390 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2391 2392 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2393 2394 if (is_hub) { 2395 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2396 sc->sc_hw.devs[index].tt); 2397 } 2398 2399 hubdev = udev->parent_hs_hub; 2400 2401 /* check if we should activate the transaction translator */ 2402 switch (udev->speed) { 2403 case USB_SPEED_FULL: 2404 case USB_SPEED_LOW: 2405 if (hubdev != NULL) { 2406 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2407 hubdev->controller_slot_id); 2408 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2409 udev->hs_port_no); 2410 } 2411 break; 2412 default: 2413 break; 2414 } 2415 2416 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2417 2418 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) | 2419 XHCI_SCTX_3_SLOT_STATE_SET(0); 2420 2421 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2422 2423 #ifdef USB_DEBUG 2424 xhci_dump_device(sc, &pinp->ctx_slot); 2425 #endif 2426 usb_pc_cpu_flush(pcinp); 2427 2428 return (0); /* success */ 2429 } 2430 2431 static usb_error_t 2432 xhci_alloc_device_ext(struct usb_device *udev) 2433 { 2434 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2435 struct usb_page_search buf_dev; 2436 struct usb_page_search buf_ep; 2437 struct xhci_trb *trb; 2438 struct usb_page_cache *pc; 2439 struct usb_page *pg; 2440 uint64_t addr; 2441 uint8_t index; 2442 uint8_t i; 2443 2444 index = udev->controller_slot_id; 2445 2446 pc = &sc->sc_hw.devs[index].device_pc; 2447 pg = &sc->sc_hw.devs[index].device_pg; 2448 2449 /* need to initialize the page cache */ 2450 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2451 2452 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2453 (2 * sizeof(struct xhci_dev_ctx)) : 2454 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2455 goto error; 2456 2457 usbd_get_page(pc, 0, &buf_dev); 2458 2459 pc = &sc->sc_hw.devs[index].input_pc; 2460 pg = &sc->sc_hw.devs[index].input_pg; 2461 2462 /* need to initialize the page cache */ 2463 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2464 2465 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2466 (2 * sizeof(struct xhci_input_dev_ctx)) : 2467 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) 2468 goto error; 2469 2470 pc = &sc->sc_hw.devs[index].endpoint_pc; 2471 pg = &sc->sc_hw.devs[index].endpoint_pg; 2472 2473 /* need to initialize the page cache */ 2474 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2475 2476 if (usb_pc_alloc_mem(pc, pg, sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) 2477 goto error; 2478 2479 /* initialise all endpoint LINK TRBs */ 2480 2481 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2482 2483 /* lookup endpoint TRB ring */ 2484 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2485 2486 /* get TRB pointer */ 2487 trb = buf_ep.buffer; 2488 trb += XHCI_MAX_TRANSFERS - 1; 2489 2490 /* get TRB start address */ 2491 addr = buf_ep.physaddr; 2492 2493 /* create LINK TRB */ 2494 trb->qwTrb0 = htole64(addr); 2495 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2496 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2497 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2498 } 2499 2500 usb_pc_cpu_flush(pc); 2501 2502 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2503 2504 return (0); 2505 2506 error: 2507 xhci_free_device_ext(udev); 2508 2509 return (USB_ERR_NOMEM); 2510 } 2511 2512 static void 2513 xhci_free_device_ext(struct usb_device *udev) 2514 { 2515 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2516 uint8_t index; 2517 2518 index = udev->controller_slot_id; 2519 xhci_set_slot_pointer(sc, index, 0); 2520 2521 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2522 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2523 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2524 } 2525 2526 static struct xhci_endpoint_ext * 2527 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2528 { 2529 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2530 struct xhci_endpoint_ext *pepext; 2531 struct usb_page_cache *pc; 2532 struct usb_page_search buf_ep; 2533 uint8_t epno; 2534 uint8_t index; 2535 2536 epno = edesc->bEndpointAddress; 2537 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2538 epno |= UE_DIR_IN; 2539 2540 epno = XHCI_EPNO2EPID(epno); 2541 2542 index = udev->controller_slot_id; 2543 2544 pc = &sc->sc_hw.devs[index].endpoint_pc; 2545 2546 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2547 trb[epno][0], &buf_ep); 2548 2549 pepext = &sc->sc_hw.devs[index].endp[epno]; 2550 pepext->page_cache = pc; 2551 pepext->trb = buf_ep.buffer; 2552 pepext->physaddr = buf_ep.physaddr; 2553 2554 return (pepext); 2555 } 2556 2557 static void 2558 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2559 { 2560 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2561 uint8_t epno; 2562 uint8_t index; 2563 2564 epno = xfer->endpointno; 2565 if (xfer->flags_int.control_xfr) 2566 epno |= UE_DIR_IN; 2567 2568 epno = XHCI_EPNO2EPID(epno); 2569 index = xfer->xroot->udev->controller_slot_id; 2570 2571 if (xfer->xroot->udev->flags.self_suspended == 0) 2572 XWRITE4(sc, door, XHCI_DOORBELL(index), epno | XHCI_DB_SID_SET(0)); 2573 } 2574 2575 static void 2576 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2577 { 2578 struct xhci_endpoint_ext *pepext; 2579 2580 if (xfer->flags_int.bandwidth_reclaimed) { 2581 xfer->flags_int.bandwidth_reclaimed = 0; 2582 2583 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2584 xfer->endpoint->edesc); 2585 2586 pepext->trb_used[xfer->stream_id]--; 2587 2588 pepext->xfer[xfer->qh_pos] = NULL; 2589 2590 if (error && pepext->trb_running != 0) { 2591 pepext->trb_halted = 1; 2592 pepext->trb_running = 0; 2593 } 2594 } 2595 } 2596 2597 static usb_error_t 2598 xhci_transfer_insert(struct usb_xfer *xfer) 2599 { 2600 struct xhci_td *td_first; 2601 struct xhci_td *td_last; 2602 struct xhci_endpoint_ext *pepext; 2603 uint64_t addr; 2604 usb_stream_t id; 2605 uint8_t i; 2606 uint8_t inext; 2607 uint8_t trb_limit; 2608 2609 DPRINTFN(8, "\n"); 2610 2611 id = xfer->stream_id; 2612 2613 /* check if already inserted */ 2614 if (xfer->flags_int.bandwidth_reclaimed) { 2615 DPRINTFN(8, "Already in schedule\n"); 2616 return (0); 2617 } 2618 2619 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2620 xfer->endpoint->edesc); 2621 2622 td_first = xfer->td_transfer_first; 2623 td_last = xfer->td_transfer_last; 2624 addr = pepext->physaddr; 2625 2626 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2627 case UE_CONTROL: 2628 case UE_INTERRUPT: 2629 /* single buffered */ 2630 trb_limit = 1; 2631 break; 2632 default: 2633 /* multi buffered */ 2634 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2635 break; 2636 } 2637 2638 if (pepext->trb_used[id] >= trb_limit) { 2639 DPRINTFN(8, "Too many TDs queued.\n"); 2640 return (USB_ERR_NOMEM); 2641 } 2642 2643 /* check for stopped condition, after putting transfer on interrupt queue */ 2644 if (pepext->trb_running == 0) { 2645 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2646 2647 DPRINTFN(8, "Not running\n"); 2648 2649 /* start configuration */ 2650 (void)usb_proc_msignal(&sc->sc_config_proc, 2651 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2652 return (0); 2653 } 2654 2655 pepext->trb_used[id]++; 2656 2657 /* get current TRB index */ 2658 i = pepext->trb_index[id]; 2659 2660 /* get next TRB index */ 2661 inext = (i + 1); 2662 2663 /* the last entry of the ring is a hardcoded link TRB */ 2664 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2665 inext = 0; 2666 2667 /* offset for stream */ 2668 i += id * XHCI_MAX_TRANSFERS; 2669 inext += id * XHCI_MAX_TRANSFERS; 2670 2671 /* compute terminating return address */ 2672 addr += (inext * sizeof(struct xhci_trb)); 2673 2674 /* update next pointer of last link TRB */ 2675 td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr); 2676 td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2677 td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2678 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2679 2680 #ifdef USB_DEBUG 2681 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2682 #endif 2683 usb_pc_cpu_flush(td_last->page_cache); 2684 2685 /* write ahead chain end marker */ 2686 2687 pepext->trb[inext].qwTrb0 = 0; 2688 pepext->trb[inext].dwTrb2 = 0; 2689 pepext->trb[inext].dwTrb3 = 0; 2690 2691 /* update next pointer of link TRB */ 2692 2693 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2694 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2695 2696 #ifdef USB_DEBUG 2697 xhci_dump_trb(&pepext->trb[i]); 2698 #endif 2699 usb_pc_cpu_flush(pepext->page_cache); 2700 2701 /* toggle cycle bit which activates the transfer chain */ 2702 2703 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2704 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2705 2706 usb_pc_cpu_flush(pepext->page_cache); 2707 2708 DPRINTF("qh_pos = %u\n", i); 2709 2710 pepext->xfer[i] = xfer; 2711 2712 xfer->qh_pos = i; 2713 2714 xfer->flags_int.bandwidth_reclaimed = 1; 2715 2716 pepext->trb_index[id] = inext; 2717 2718 xhci_endpoint_doorbell(xfer); 2719 2720 return (0); 2721 } 2722 2723 static void 2724 xhci_root_intr(struct xhci_softc *sc) 2725 { 2726 uint16_t i; 2727 2728 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2729 2730 /* clear any old interrupt data */ 2731 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2732 2733 for (i = 1; i <= sc->sc_noport; i++) { 2734 /* pick out CHANGE bits from the status register */ 2735 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2736 XHCI_PS_CSC | XHCI_PS_PEC | 2737 XHCI_PS_OCC | XHCI_PS_WRC | 2738 XHCI_PS_PRC | XHCI_PS_PLC | 2739 XHCI_PS_CEC)) { 2740 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2741 DPRINTF("port %d changed\n", i); 2742 } 2743 } 2744 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2745 sizeof(sc->sc_hub_idata)); 2746 } 2747 2748 /*------------------------------------------------------------------------* 2749 * xhci_device_done - XHCI done handler 2750 * 2751 * NOTE: This function can be called two times in a row on 2752 * the same USB transfer. From close and from interrupt. 2753 *------------------------------------------------------------------------*/ 2754 static void 2755 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2756 { 2757 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2758 xfer, xfer->endpoint, error); 2759 2760 /* remove transfer from HW queue */ 2761 xhci_transfer_remove(xfer, error); 2762 2763 /* dequeue transfer and start next transfer */ 2764 usbd_transfer_done(xfer, error); 2765 } 2766 2767 /*------------------------------------------------------------------------* 2768 * XHCI data transfer support (generic type) 2769 *------------------------------------------------------------------------*/ 2770 static void 2771 xhci_device_generic_open(struct usb_xfer *xfer) 2772 { 2773 if (xfer->flags_int.isochronous_xfr) { 2774 switch (xfer->xroot->udev->speed) { 2775 case USB_SPEED_FULL: 2776 break; 2777 default: 2778 usb_hs_bandwidth_alloc(xfer); 2779 break; 2780 } 2781 } 2782 } 2783 2784 static void 2785 xhci_device_generic_close(struct usb_xfer *xfer) 2786 { 2787 DPRINTF("\n"); 2788 2789 xhci_device_done(xfer, USB_ERR_CANCELLED); 2790 2791 if (xfer->flags_int.isochronous_xfr) { 2792 switch (xfer->xroot->udev->speed) { 2793 case USB_SPEED_FULL: 2794 break; 2795 default: 2796 usb_hs_bandwidth_free(xfer); 2797 break; 2798 } 2799 } 2800 } 2801 2802 static void 2803 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 2804 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 2805 { 2806 struct usb_xfer *xfer; 2807 2808 /* check if there is a current transfer */ 2809 xfer = ep->endpoint_q[stream_id].curr; 2810 if (xfer == NULL) 2811 return; 2812 2813 /* 2814 * Check if the current transfer is started and then pickup 2815 * the next one, if any. Else wait for next start event due to 2816 * block on failure feature. 2817 */ 2818 if (!xfer->flags_int.bandwidth_reclaimed) 2819 return; 2820 2821 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 2822 if (xfer == NULL) { 2823 /* 2824 * In case of enter we have to consider that the 2825 * transfer is queued by the USB core after the enter 2826 * method is called. 2827 */ 2828 xfer = enter_xfer; 2829 2830 if (xfer == NULL) 2831 return; 2832 } 2833 2834 /* try to multi buffer */ 2835 xhci_transfer_insert(xfer); 2836 } 2837 2838 static void 2839 xhci_device_generic_enter(struct usb_xfer *xfer) 2840 { 2841 DPRINTF("\n"); 2842 2843 /* setup TD's and QH */ 2844 xhci_setup_generic_chain(xfer); 2845 2846 xhci_device_generic_multi_enter(xfer->endpoint, 2847 xfer->stream_id, xfer); 2848 } 2849 2850 static void 2851 xhci_device_generic_start(struct usb_xfer *xfer) 2852 { 2853 DPRINTF("\n"); 2854 2855 /* try to insert xfer on HW queue */ 2856 xhci_transfer_insert(xfer); 2857 2858 /* try to multi buffer */ 2859 xhci_device_generic_multi_enter(xfer->endpoint, 2860 xfer->stream_id, NULL); 2861 2862 /* add transfer last on interrupt queue */ 2863 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2864 2865 /* start timeout, if any */ 2866 if (xfer->timeout != 0) 2867 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 2868 } 2869 2870 struct usb_pipe_methods xhci_device_generic_methods = 2871 { 2872 .open = xhci_device_generic_open, 2873 .close = xhci_device_generic_close, 2874 .enter = xhci_device_generic_enter, 2875 .start = xhci_device_generic_start, 2876 }; 2877 2878 /*------------------------------------------------------------------------* 2879 * xhci root HUB support 2880 *------------------------------------------------------------------------* 2881 * Simulate a hardware HUB by handling all the necessary requests. 2882 *------------------------------------------------------------------------*/ 2883 2884 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 2885 2886 static const 2887 struct usb_device_descriptor xhci_devd = 2888 { 2889 .bLength = sizeof(xhci_devd), 2890 .bDescriptorType = UDESC_DEVICE, /* type */ 2891 HSETW(.bcdUSB, 0x0300), /* USB version */ 2892 .bDeviceClass = UDCLASS_HUB, /* class */ 2893 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 2894 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 2895 .bMaxPacketSize = 9, /* max packet size */ 2896 HSETW(.idVendor, 0x0000), /* vendor */ 2897 HSETW(.idProduct, 0x0000), /* product */ 2898 HSETW(.bcdDevice, 0x0100), /* device version */ 2899 .iManufacturer = 1, 2900 .iProduct = 2, 2901 .iSerialNumber = 0, 2902 .bNumConfigurations = 1, /* # of configurations */ 2903 }; 2904 2905 static const 2906 struct xhci_bos_desc xhci_bosd = { 2907 .bosd = { 2908 .bLength = sizeof(xhci_bosd.bosd), 2909 .bDescriptorType = UDESC_BOS, 2910 HSETW(.wTotalLength, sizeof(xhci_bosd)), 2911 .bNumDeviceCaps = 3, 2912 }, 2913 .usb2extd = { 2914 .bLength = sizeof(xhci_bosd.usb2extd), 2915 .bDescriptorType = 1, 2916 .bDevCapabilityType = 2, 2917 .bmAttributes[0] = 2, 2918 }, 2919 .usbdcd = { 2920 .bLength = sizeof(xhci_bosd.usbdcd), 2921 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 2922 .bDevCapabilityType = 3, 2923 .bmAttributes = 0, /* XXX */ 2924 HSETW(.wSpeedsSupported, 0x000C), 2925 .bFunctionalitySupport = 8, 2926 .bU1DevExitLat = 255, /* dummy - not used */ 2927 .wU2DevExitLat = { 0x00, 0x08 }, 2928 }, 2929 .cidd = { 2930 .bLength = sizeof(xhci_bosd.cidd), 2931 .bDescriptorType = 1, 2932 .bDevCapabilityType = 4, 2933 .bReserved = 0, 2934 .bContainerID = 0, /* XXX */ 2935 }, 2936 }; 2937 2938 static const 2939 struct xhci_config_desc xhci_confd = { 2940 .confd = { 2941 .bLength = sizeof(xhci_confd.confd), 2942 .bDescriptorType = UDESC_CONFIG, 2943 .wTotalLength[0] = sizeof(xhci_confd), 2944 .bNumInterface = 1, 2945 .bConfigurationValue = 1, 2946 .iConfiguration = 0, 2947 .bmAttributes = UC_SELF_POWERED, 2948 .bMaxPower = 0 /* max power */ 2949 }, 2950 .ifcd = { 2951 .bLength = sizeof(xhci_confd.ifcd), 2952 .bDescriptorType = UDESC_INTERFACE, 2953 .bNumEndpoints = 1, 2954 .bInterfaceClass = UICLASS_HUB, 2955 .bInterfaceSubClass = UISUBCLASS_HUB, 2956 .bInterfaceProtocol = 0, 2957 }, 2958 .endpd = { 2959 .bLength = sizeof(xhci_confd.endpd), 2960 .bDescriptorType = UDESC_ENDPOINT, 2961 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 2962 .bmAttributes = UE_INTERRUPT, 2963 .wMaxPacketSize[0] = 2, /* max 15 ports */ 2964 .bInterval = 255, 2965 }, 2966 .endpcd = { 2967 .bLength = sizeof(xhci_confd.endpcd), 2968 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 2969 .bMaxBurst = 0, 2970 .bmAttributes = 0, 2971 }, 2972 }; 2973 2974 static const 2975 struct usb_hub_ss_descriptor xhci_hubd = { 2976 .bLength = sizeof(xhci_hubd), 2977 .bDescriptorType = UDESC_SS_HUB, 2978 }; 2979 2980 static usb_error_t 2981 xhci_roothub_exec(struct usb_device *udev, 2982 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2983 { 2984 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2985 const char *str_ptr; 2986 const void *ptr; 2987 uint32_t port; 2988 uint32_t v; 2989 uint16_t len; 2990 uint16_t i; 2991 uint16_t value; 2992 uint16_t index; 2993 uint8_t j; 2994 usb_error_t err; 2995 2996 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2997 2998 /* buffer reset */ 2999 ptr = (const void *)&sc->sc_hub_desc; 3000 len = 0; 3001 err = 0; 3002 3003 value = UGETW(req->wValue); 3004 index = UGETW(req->wIndex); 3005 3006 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3007 "wValue=0x%04x wIndex=0x%04x\n", 3008 req->bmRequestType, req->bRequest, 3009 UGETW(req->wLength), value, index); 3010 3011 #define C(x,y) ((x) | ((y) << 8)) 3012 switch (C(req->bRequest, req->bmRequestType)) { 3013 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3014 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3015 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3016 /* 3017 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3018 * for the integrated root hub. 3019 */ 3020 break; 3021 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3022 len = 1; 3023 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3024 break; 3025 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3026 switch (value >> 8) { 3027 case UDESC_DEVICE: 3028 if ((value & 0xff) != 0) { 3029 err = USB_ERR_IOERROR; 3030 goto done; 3031 } 3032 len = sizeof(xhci_devd); 3033 ptr = (const void *)&xhci_devd; 3034 break; 3035 3036 case UDESC_BOS: 3037 if ((value & 0xff) != 0) { 3038 err = USB_ERR_IOERROR; 3039 goto done; 3040 } 3041 len = sizeof(xhci_bosd); 3042 ptr = (const void *)&xhci_bosd; 3043 break; 3044 3045 case UDESC_CONFIG: 3046 if ((value & 0xff) != 0) { 3047 err = USB_ERR_IOERROR; 3048 goto done; 3049 } 3050 len = sizeof(xhci_confd); 3051 ptr = (const void *)&xhci_confd; 3052 break; 3053 3054 case UDESC_STRING: 3055 switch (value & 0xff) { 3056 case 0: /* Language table */ 3057 str_ptr = "\001"; 3058 break; 3059 3060 case 1: /* Vendor */ 3061 str_ptr = sc->sc_vendor; 3062 break; 3063 3064 case 2: /* Product */ 3065 str_ptr = "XHCI root HUB"; 3066 break; 3067 3068 default: 3069 str_ptr = ""; 3070 break; 3071 } 3072 3073 len = usb_make_str_desc( 3074 sc->sc_hub_desc.temp, 3075 sizeof(sc->sc_hub_desc.temp), 3076 str_ptr); 3077 break; 3078 3079 default: 3080 err = USB_ERR_IOERROR; 3081 goto done; 3082 } 3083 break; 3084 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3085 len = 1; 3086 sc->sc_hub_desc.temp[0] = 0; 3087 break; 3088 case C(UR_GET_STATUS, UT_READ_DEVICE): 3089 len = 2; 3090 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3091 break; 3092 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3093 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3094 len = 2; 3095 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3096 break; 3097 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3098 if (value >= XHCI_MAX_DEVICES) { 3099 err = USB_ERR_IOERROR; 3100 goto done; 3101 } 3102 break; 3103 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3104 if (value != 0 && value != 1) { 3105 err = USB_ERR_IOERROR; 3106 goto done; 3107 } 3108 sc->sc_conf = value; 3109 break; 3110 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3111 break; 3112 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3113 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3114 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3115 err = USB_ERR_IOERROR; 3116 goto done; 3117 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3118 break; 3119 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3120 break; 3121 /* Hub requests */ 3122 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3123 break; 3124 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3125 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3126 3127 if ((index < 1) || 3128 (index > sc->sc_noport)) { 3129 err = USB_ERR_IOERROR; 3130 goto done; 3131 } 3132 port = XHCI_PORTSC(index); 3133 3134 v = XREAD4(sc, oper, port); 3135 i = XHCI_PS_PLS_GET(v); 3136 v &= ~XHCI_PS_CLEAR; 3137 3138 switch (value) { 3139 case UHF_C_BH_PORT_RESET: 3140 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3141 break; 3142 case UHF_C_PORT_CONFIG_ERROR: 3143 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3144 break; 3145 case UHF_C_PORT_SUSPEND: 3146 case UHF_C_PORT_LINK_STATE: 3147 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3148 break; 3149 case UHF_C_PORT_CONNECTION: 3150 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3151 break; 3152 case UHF_C_PORT_ENABLE: 3153 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3154 break; 3155 case UHF_C_PORT_OVER_CURRENT: 3156 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3157 break; 3158 case UHF_C_PORT_RESET: 3159 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3160 break; 3161 case UHF_PORT_ENABLE: 3162 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3163 break; 3164 case UHF_PORT_POWER: 3165 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3166 break; 3167 case UHF_PORT_INDICATOR: 3168 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3169 break; 3170 case UHF_PORT_SUSPEND: 3171 3172 /* U3 -> U15 */ 3173 if (i == 3) { 3174 XWRITE4(sc, oper, port, v | 3175 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3176 } 3177 3178 /* wait 20ms for resume sequence to complete */ 3179 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3180 3181 /* U0 */ 3182 XWRITE4(sc, oper, port, v | 3183 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3184 break; 3185 default: 3186 err = USB_ERR_IOERROR; 3187 goto done; 3188 } 3189 break; 3190 3191 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3192 if ((value & 0xff) != 0) { 3193 err = USB_ERR_IOERROR; 3194 goto done; 3195 } 3196 3197 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3198 3199 sc->sc_hub_desc.hubd = xhci_hubd; 3200 3201 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3202 3203 if (XHCI_HCS0_PPC(v)) 3204 i = UHD_PWR_INDIVIDUAL; 3205 else 3206 i = UHD_PWR_GANGED; 3207 3208 if (XHCI_HCS0_PIND(v)) 3209 i |= UHD_PORT_IND; 3210 3211 i |= UHD_OC_INDIVIDUAL; 3212 3213 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3214 3215 /* see XHCI section 5.4.9: */ 3216 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3217 3218 for (j = 1; j <= sc->sc_noport; j++) { 3219 3220 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3221 if (v & XHCI_PS_DR) { 3222 sc->sc_hub_desc.hubd. 3223 DeviceRemovable[j / 8] |= 1U << (j % 8); 3224 } 3225 } 3226 len = sc->sc_hub_desc.hubd.bLength; 3227 break; 3228 3229 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3230 len = 16; 3231 memset(sc->sc_hub_desc.temp, 0, 16); 3232 break; 3233 3234 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3235 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3236 3237 if ((index < 1) || 3238 (index > sc->sc_noport)) { 3239 err = USB_ERR_IOERROR; 3240 goto done; 3241 } 3242 3243 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3244 3245 DPRINTFN(9, "port status=0x%08x\n", v); 3246 3247 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3248 3249 switch (XHCI_PS_SPEED_GET(v)) { 3250 case 3: 3251 i |= UPS_HIGH_SPEED; 3252 break; 3253 case 2: 3254 i |= UPS_LOW_SPEED; 3255 break; 3256 case 1: 3257 /* FULL speed */ 3258 break; 3259 default: 3260 i |= UPS_OTHER_SPEED; 3261 break; 3262 } 3263 3264 if (v & XHCI_PS_CCS) 3265 i |= UPS_CURRENT_CONNECT_STATUS; 3266 if (v & XHCI_PS_PED) 3267 i |= UPS_PORT_ENABLED; 3268 if (v & XHCI_PS_OCA) 3269 i |= UPS_OVERCURRENT_INDICATOR; 3270 if (v & XHCI_PS_PR) 3271 i |= UPS_RESET; 3272 if (v & XHCI_PS_PP) { 3273 /* 3274 * The USB 3.0 RH is using the 3275 * USB 2.0's power bit 3276 */ 3277 i |= UPS_PORT_POWER; 3278 } 3279 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3280 3281 i = 0; 3282 if (v & XHCI_PS_CSC) 3283 i |= UPS_C_CONNECT_STATUS; 3284 if (v & XHCI_PS_PEC) 3285 i |= UPS_C_PORT_ENABLED; 3286 if (v & XHCI_PS_OCC) 3287 i |= UPS_C_OVERCURRENT_INDICATOR; 3288 if (v & XHCI_PS_WRC) 3289 i |= UPS_C_BH_PORT_RESET; 3290 if (v & XHCI_PS_PRC) 3291 i |= UPS_C_PORT_RESET; 3292 if (v & XHCI_PS_PLC) 3293 i |= UPS_C_PORT_LINK_STATE; 3294 if (v & XHCI_PS_CEC) 3295 i |= UPS_C_PORT_CONFIG_ERROR; 3296 3297 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3298 len = sizeof(sc->sc_hub_desc.ps); 3299 break; 3300 3301 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3302 err = USB_ERR_IOERROR; 3303 goto done; 3304 3305 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3306 break; 3307 3308 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3309 3310 i = index >> 8; 3311 index &= 0x00FF; 3312 3313 if ((index < 1) || 3314 (index > sc->sc_noport)) { 3315 err = USB_ERR_IOERROR; 3316 goto done; 3317 } 3318 3319 port = XHCI_PORTSC(index); 3320 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3321 3322 switch (value) { 3323 case UHF_PORT_U1_TIMEOUT: 3324 if (XHCI_PS_SPEED_GET(v) != 4) { 3325 err = USB_ERR_IOERROR; 3326 goto done; 3327 } 3328 port = XHCI_PORTPMSC(index); 3329 v = XREAD4(sc, oper, port); 3330 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3331 v |= XHCI_PM3_U1TO_SET(i); 3332 XWRITE4(sc, oper, port, v); 3333 break; 3334 case UHF_PORT_U2_TIMEOUT: 3335 if (XHCI_PS_SPEED_GET(v) != 4) { 3336 err = USB_ERR_IOERROR; 3337 goto done; 3338 } 3339 port = XHCI_PORTPMSC(index); 3340 v = XREAD4(sc, oper, port); 3341 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3342 v |= XHCI_PM3_U2TO_SET(i); 3343 XWRITE4(sc, oper, port, v); 3344 break; 3345 case UHF_BH_PORT_RESET: 3346 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3347 break; 3348 case UHF_PORT_LINK_STATE: 3349 XWRITE4(sc, oper, port, v | 3350 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3351 /* 4ms settle time */ 3352 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3353 break; 3354 case UHF_PORT_ENABLE: 3355 DPRINTFN(3, "set port enable %d\n", index); 3356 break; 3357 case UHF_PORT_SUSPEND: 3358 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3359 j = XHCI_PS_SPEED_GET(v); 3360 if ((j < 1) || (j > 3)) { 3361 /* non-supported speed */ 3362 err = USB_ERR_IOERROR; 3363 goto done; 3364 } 3365 XWRITE4(sc, oper, port, v | 3366 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3367 break; 3368 case UHF_PORT_RESET: 3369 DPRINTFN(6, "reset port %d\n", index); 3370 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3371 break; 3372 case UHF_PORT_POWER: 3373 DPRINTFN(3, "set port power %d\n", index); 3374 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3375 break; 3376 case UHF_PORT_TEST: 3377 DPRINTFN(3, "set port test %d\n", index); 3378 break; 3379 case UHF_PORT_INDICATOR: 3380 DPRINTFN(3, "set port indicator %d\n", index); 3381 3382 v &= ~XHCI_PS_PIC_SET(3); 3383 v |= XHCI_PS_PIC_SET(1); 3384 3385 XWRITE4(sc, oper, port, v); 3386 break; 3387 default: 3388 err = USB_ERR_IOERROR; 3389 goto done; 3390 } 3391 break; 3392 3393 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3394 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3395 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3396 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3397 break; 3398 default: 3399 err = USB_ERR_IOERROR; 3400 goto done; 3401 } 3402 done: 3403 *plength = len; 3404 *pptr = ptr; 3405 return (err); 3406 } 3407 3408 static void 3409 xhci_xfer_setup(struct usb_setup_params *parm) 3410 { 3411 struct usb_page_search page_info; 3412 struct usb_page_cache *pc; 3413 struct xhci_softc *sc; 3414 struct usb_xfer *xfer; 3415 void *last_obj; 3416 uint32_t ntd; 3417 uint32_t n; 3418 3419 sc = XHCI_BUS2SC(parm->udev->bus); 3420 xfer = parm->curr_xfer; 3421 3422 /* 3423 * The proof for the "ntd" formula is illustrated like this: 3424 * 3425 * +------------------------------------+ 3426 * | | 3427 * | |remainder -> | 3428 * | +-----+---+ | 3429 * | | xxx | x | frm 0 | 3430 * | +-----+---++ | 3431 * | | xxx | xx | frm 1 | 3432 * | +-----+----+ | 3433 * | ... | 3434 * +------------------------------------+ 3435 * 3436 * "xxx" means a completely full USB transfer descriptor 3437 * 3438 * "x" and "xx" means a short USB packet 3439 * 3440 * For the remainder of an USB transfer modulo 3441 * "max_data_length" we need two USB transfer descriptors. 3442 * One to transfer the remaining data and one to finalise with 3443 * a zero length packet in case the "force_short_xfer" flag is 3444 * set. We only need two USB transfer descriptors in the case 3445 * where the transfer length of the first one is a factor of 3446 * "max_frame_size". The rest of the needed USB transfer 3447 * descriptors is given by the buffer size divided by the 3448 * maximum data payload. 3449 */ 3450 parm->hc_max_packet_size = 0x400; 3451 parm->hc_max_packet_count = 16 * 3; 3452 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3453 3454 xfer->flags_int.bdma_enable = 1; 3455 3456 usbd_transfer_setup_sub(parm); 3457 3458 if (xfer->flags_int.isochronous_xfr) { 3459 ntd = ((1 * xfer->nframes) 3460 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3461 } else if (xfer->flags_int.control_xfr) { 3462 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3463 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3464 } else { 3465 ntd = ((2 * xfer->nframes) 3466 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3467 } 3468 3469 alloc_dma_set: 3470 3471 if (parm->err) 3472 return; 3473 3474 /* 3475 * Allocate queue heads and transfer descriptors 3476 */ 3477 last_obj = NULL; 3478 3479 if (usbd_transfer_setup_sub_malloc( 3480 parm, &pc, sizeof(struct xhci_td), 3481 XHCI_TD_ALIGN, ntd)) { 3482 parm->err = USB_ERR_NOMEM; 3483 return; 3484 } 3485 if (parm->buf) { 3486 for (n = 0; n != ntd; n++) { 3487 struct xhci_td *td; 3488 3489 usbd_get_page(pc + n, 0, &page_info); 3490 3491 td = page_info.buffer; 3492 3493 /* init TD */ 3494 td->td_self = page_info.physaddr; 3495 td->obj_next = last_obj; 3496 td->page_cache = pc + n; 3497 3498 last_obj = td; 3499 3500 usb_pc_cpu_flush(pc + n); 3501 } 3502 } 3503 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3504 3505 if (!xfer->flags_int.curr_dma_set) { 3506 xfer->flags_int.curr_dma_set = 1; 3507 goto alloc_dma_set; 3508 } 3509 } 3510 3511 static usb_error_t 3512 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3513 { 3514 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3515 struct usb_page_search buf_inp; 3516 struct usb_device *udev; 3517 struct xhci_endpoint_ext *pepext; 3518 struct usb_endpoint_descriptor *edesc; 3519 struct usb_page_cache *pcinp; 3520 usb_error_t err; 3521 usb_stream_t stream_id; 3522 uint8_t index; 3523 uint8_t epno; 3524 3525 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3526 xfer->endpoint->edesc); 3527 3528 udev = xfer->xroot->udev; 3529 index = udev->controller_slot_id; 3530 3531 pcinp = &sc->sc_hw.devs[index].input_pc; 3532 3533 usbd_get_page(pcinp, 0, &buf_inp); 3534 3535 edesc = xfer->endpoint->edesc; 3536 3537 epno = edesc->bEndpointAddress; 3538 stream_id = xfer->stream_id; 3539 3540 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3541 epno |= UE_DIR_IN; 3542 3543 epno = XHCI_EPNO2EPID(epno); 3544 3545 if (epno == 0) 3546 return (USB_ERR_NO_PIPE); /* invalid */ 3547 3548 XHCI_CMD_LOCK(sc); 3549 3550 /* configure endpoint */ 3551 3552 err = xhci_configure_endpoint_by_xfer(xfer); 3553 3554 if (err != 0) { 3555 XHCI_CMD_UNLOCK(sc); 3556 return (err); 3557 } 3558 3559 /* 3560 * Get the endpoint into the stopped state according to the 3561 * endpoint context state diagram in the XHCI specification: 3562 */ 3563 3564 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3565 3566 if (err != 0) 3567 DPRINTF("Could not stop endpoint %u\n", epno); 3568 3569 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3570 3571 if (err != 0) 3572 DPRINTF("Could not reset endpoint %u\n", epno); 3573 3574 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3575 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3576 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3577 stream_id, epno, index); 3578 3579 if (err != 0) 3580 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3581 3582 /* 3583 * Get the endpoint into the running state according to the 3584 * endpoint context state diagram in the XHCI specification: 3585 */ 3586 3587 xhci_configure_mask(udev, 1U << epno, 0); 3588 3589 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3590 3591 if (err != 0) 3592 DPRINTF("Could not configure endpoint %u\n", epno); 3593 3594 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3595 3596 if (err != 0) 3597 DPRINTF("Could not configure endpoint %u\n", epno); 3598 3599 XHCI_CMD_UNLOCK(sc); 3600 3601 return (0); 3602 } 3603 3604 static void 3605 xhci_xfer_unsetup(struct usb_xfer *xfer) 3606 { 3607 return; 3608 } 3609 3610 static void 3611 xhci_start_dma_delay(struct usb_xfer *xfer) 3612 { 3613 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3614 3615 /* put transfer on interrupt queue (again) */ 3616 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3617 3618 (void)usb_proc_msignal(&sc->sc_config_proc, 3619 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3620 } 3621 3622 static void 3623 xhci_configure_msg(struct usb_proc_msg *pm) 3624 { 3625 struct xhci_softc *sc; 3626 struct xhci_endpoint_ext *pepext; 3627 struct usb_xfer *xfer; 3628 3629 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3630 3631 restart: 3632 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3633 3634 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3635 xfer->endpoint->edesc); 3636 3637 if ((pepext->trb_halted != 0) || 3638 (pepext->trb_running == 0)) { 3639 3640 uint8_t i; 3641 3642 /* clear halted and running */ 3643 pepext->trb_halted = 0; 3644 pepext->trb_running = 0; 3645 3646 /* nuke remaining buffered transfers */ 3647 3648 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 3649 /* 3650 * NOTE: We need to use the timeout 3651 * error code here else existing 3652 * isochronous clients can get 3653 * confused: 3654 */ 3655 if (pepext->xfer[i] != NULL) { 3656 xhci_device_done(pepext->xfer[i], 3657 USB_ERR_TIMEOUT); 3658 } 3659 } 3660 3661 /* 3662 * NOTE: The USB transfer cannot vanish in 3663 * this state! 3664 */ 3665 3666 USB_BUS_UNLOCK(&sc->sc_bus); 3667 3668 xhci_configure_reset_endpoint(xfer); 3669 3670 USB_BUS_LOCK(&sc->sc_bus); 3671 3672 /* check if halted is still cleared */ 3673 if (pepext->trb_halted == 0) { 3674 pepext->trb_running = 1; 3675 memset(pepext->trb_index, 0, 3676 sizeof(pepext->trb_index)); 3677 } 3678 goto restart; 3679 } 3680 3681 if (xfer->flags_int.did_dma_delay) { 3682 3683 /* remove transfer from interrupt queue (again) */ 3684 usbd_transfer_dequeue(xfer); 3685 3686 /* we are finally done */ 3687 usb_dma_delay_done_cb(xfer); 3688 3689 /* queue changed - restart */ 3690 goto restart; 3691 } 3692 } 3693 3694 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3695 3696 /* try to insert xfer on HW queue */ 3697 xhci_transfer_insert(xfer); 3698 3699 /* try to multi buffer */ 3700 xhci_device_generic_multi_enter(xfer->endpoint, 3701 xfer->stream_id, NULL); 3702 } 3703 } 3704 3705 static void 3706 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3707 struct usb_endpoint *ep) 3708 { 3709 struct xhci_endpoint_ext *pepext; 3710 3711 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3712 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3713 3714 if (udev->parent_hub == NULL) { 3715 /* root HUB has special endpoint handling */ 3716 return; 3717 } 3718 3719 ep->methods = &xhci_device_generic_methods; 3720 3721 pepext = xhci_get_endpoint_ext(udev, edesc); 3722 3723 USB_BUS_LOCK(udev->bus); 3724 pepext->trb_halted = 1; 3725 pepext->trb_running = 0; 3726 USB_BUS_UNLOCK(udev->bus); 3727 } 3728 3729 static void 3730 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3731 { 3732 3733 } 3734 3735 static void 3736 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3737 { 3738 struct xhci_endpoint_ext *pepext; 3739 3740 DPRINTF("\n"); 3741 3742 if (udev->flags.usb_mode != USB_MODE_HOST) { 3743 /* not supported */ 3744 return; 3745 } 3746 if (udev->parent_hub == NULL) { 3747 /* root HUB has special endpoint handling */ 3748 return; 3749 } 3750 3751 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3752 3753 USB_BUS_LOCK(udev->bus); 3754 pepext->trb_halted = 1; 3755 pepext->trb_running = 0; 3756 USB_BUS_UNLOCK(udev->bus); 3757 } 3758 3759 static usb_error_t 3760 xhci_device_init(struct usb_device *udev) 3761 { 3762 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3763 usb_error_t err; 3764 uint8_t temp; 3765 3766 /* no init for root HUB */ 3767 if (udev->parent_hub == NULL) 3768 return (0); 3769 3770 XHCI_CMD_LOCK(sc); 3771 3772 /* set invalid default */ 3773 3774 udev->controller_slot_id = sc->sc_noslot + 1; 3775 3776 /* try to get a new slot ID from the XHCI */ 3777 3778 err = xhci_cmd_enable_slot(sc, &temp); 3779 3780 if (err) { 3781 XHCI_CMD_UNLOCK(sc); 3782 return (err); 3783 } 3784 3785 if (temp > sc->sc_noslot) { 3786 XHCI_CMD_UNLOCK(sc); 3787 return (USB_ERR_BAD_ADDRESS); 3788 } 3789 3790 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 3791 DPRINTF("slot %u already allocated.\n", temp); 3792 XHCI_CMD_UNLOCK(sc); 3793 return (USB_ERR_BAD_ADDRESS); 3794 } 3795 3796 /* store slot ID for later reference */ 3797 3798 udev->controller_slot_id = temp; 3799 3800 /* reset data structure */ 3801 3802 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 3803 3804 /* set mark slot allocated */ 3805 3806 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 3807 3808 err = xhci_alloc_device_ext(udev); 3809 3810 XHCI_CMD_UNLOCK(sc); 3811 3812 /* get device into default state */ 3813 3814 if (err == 0) 3815 err = xhci_set_address(udev, NULL, 0); 3816 3817 return (err); 3818 } 3819 3820 static void 3821 xhci_device_uninit(struct usb_device *udev) 3822 { 3823 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3824 uint8_t index; 3825 3826 /* no init for root HUB */ 3827 if (udev->parent_hub == NULL) 3828 return; 3829 3830 XHCI_CMD_LOCK(sc); 3831 3832 index = udev->controller_slot_id; 3833 3834 if (index <= sc->sc_noslot) { 3835 xhci_cmd_disable_slot(sc, index); 3836 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 3837 3838 /* free device extension */ 3839 xhci_free_device_ext(udev); 3840 } 3841 3842 XHCI_CMD_UNLOCK(sc); 3843 } 3844 3845 static void 3846 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3847 { 3848 /* 3849 * Wait until the hardware has finished any possible use of 3850 * the transfer descriptor(s) 3851 */ 3852 *pus = 2048; /* microseconds */ 3853 } 3854 3855 static void 3856 xhci_device_resume(struct usb_device *udev) 3857 { 3858 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3859 uint8_t index; 3860 uint8_t n; 3861 3862 DPRINTF("\n"); 3863 3864 /* check for root HUB */ 3865 if (udev->parent_hub == NULL) 3866 return; 3867 3868 index = udev->controller_slot_id; 3869 3870 XHCI_CMD_LOCK(sc); 3871 3872 /* blindly resume all endpoints */ 3873 3874 USB_BUS_LOCK(udev->bus); 3875 3876 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) 3877 XWRITE4(sc, door, XHCI_DOORBELL(index), n | XHCI_DB_SID_SET(0)); 3878 3879 USB_BUS_UNLOCK(udev->bus); 3880 3881 XHCI_CMD_UNLOCK(sc); 3882 } 3883 3884 static void 3885 xhci_device_suspend(struct usb_device *udev) 3886 { 3887 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3888 uint8_t index; 3889 uint8_t n; 3890 usb_error_t err; 3891 3892 DPRINTF("\n"); 3893 3894 /* check for root HUB */ 3895 if (udev->parent_hub == NULL) 3896 return; 3897 3898 index = udev->controller_slot_id; 3899 3900 XHCI_CMD_LOCK(sc); 3901 3902 /* blindly suspend all endpoints */ 3903 3904 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3905 err = xhci_cmd_stop_ep(sc, 1, n, index); 3906 if (err != 0) { 3907 DPRINTF("Failed to suspend endpoint " 3908 "%u on slot %u (ignored).\n", n, index); 3909 } 3910 } 3911 3912 XHCI_CMD_UNLOCK(sc); 3913 } 3914 3915 static void 3916 xhci_set_hw_power(struct usb_bus *bus) 3917 { 3918 DPRINTF("\n"); 3919 } 3920 3921 static void 3922 xhci_device_state_change(struct usb_device *udev) 3923 { 3924 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3925 struct usb_page_search buf_inp; 3926 usb_error_t err; 3927 uint8_t index; 3928 3929 /* check for root HUB */ 3930 if (udev->parent_hub == NULL) 3931 return; 3932 3933 index = udev->controller_slot_id; 3934 3935 DPRINTF("\n"); 3936 3937 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 3938 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 3939 &sc->sc_hw.devs[index].tt); 3940 if (err != 0) 3941 sc->sc_hw.devs[index].nports = 0; 3942 } 3943 3944 XHCI_CMD_LOCK(sc); 3945 3946 switch (usb_get_device_state(udev)) { 3947 case USB_STATE_POWERED: 3948 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 3949 break; 3950 3951 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 3952 3953 err = xhci_cmd_reset_dev(sc, index); 3954 3955 if (err != 0) { 3956 DPRINTF("Device reset failed " 3957 "for slot %u.\n", index); 3958 } 3959 break; 3960 3961 case USB_STATE_ADDRESSED: 3962 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 3963 break; 3964 3965 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 3966 3967 err = xhci_cmd_configure_ep(sc, 0, 1, index); 3968 3969 if (err) { 3970 DPRINTF("Failed to deconfigure " 3971 "slot %u.\n", index); 3972 } 3973 break; 3974 3975 case USB_STATE_CONFIGURED: 3976 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 3977 break; 3978 3979 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 3980 3981 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 3982 3983 xhci_configure_mask(udev, 1, 0); 3984 3985 err = xhci_configure_device(udev); 3986 if (err != 0) { 3987 DPRINTF("Could not configure device " 3988 "at slot %u.\n", index); 3989 } 3990 3991 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3992 if (err != 0) { 3993 DPRINTF("Could not evaluate device " 3994 "context at slot %u.\n", index); 3995 } 3996 break; 3997 3998 default: 3999 break; 4000 } 4001 XHCI_CMD_UNLOCK(sc); 4002 } 4003 4004 static usb_error_t 4005 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4006 uint8_t ep_mode) 4007 { 4008 switch (ep_mode) { 4009 case USB_EP_MODE_DEFAULT: 4010 return (0); 4011 case USB_EP_MODE_STREAMS: 4012 if ((ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4013 udev->speed != USB_SPEED_SUPER) 4014 return (USB_ERR_INVAL); 4015 return (0); 4016 default: 4017 return (USB_ERR_INVAL); 4018 } 4019 } 4020 4021 struct usb_bus_methods xhci_bus_methods = { 4022 .endpoint_init = xhci_ep_init, 4023 .endpoint_uninit = xhci_ep_uninit, 4024 .xfer_setup = xhci_xfer_setup, 4025 .xfer_unsetup = xhci_xfer_unsetup, 4026 .get_dma_delay = xhci_get_dma_delay, 4027 .device_init = xhci_device_init, 4028 .device_uninit = xhci_device_uninit, 4029 .device_resume = xhci_device_resume, 4030 .device_suspend = xhci_device_suspend, 4031 .set_hw_power = xhci_set_hw_power, 4032 .roothub_exec = xhci_roothub_exec, 4033 .xfer_poll = xhci_do_poll, 4034 .start_dma_delay = xhci_start_dma_delay, 4035 .set_address = xhci_set_address, 4036 .clear_stall = xhci_ep_clear_stall, 4037 .device_state_change = xhci_device_state_change, 4038 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4039 .set_endpoint_mode = xhci_set_endpoint_mode, 4040 }; 4041