1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36 /* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43 #ifdef USB_GLOBAL_INCLUDE_FILE 44 #include USB_GLOBAL_INCLUDE_FILE 45 #else 46 #include <sys/stdint.h> 47 #include <sys/stddef.h> 48 #include <sys/param.h> 49 #include <sys/queue.h> 50 #include <sys/types.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/bus.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/condvar.h> 58 #include <sys/sysctl.h> 59 #include <sys/sx.h> 60 #include <sys/unistd.h> 61 #include <sys/callout.h> 62 #include <sys/malloc.h> 63 #include <sys/priv.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 68 #define USB_DEBUG_VAR xhcidebug 69 70 #include <dev/usb/usb_core.h> 71 #include <dev/usb/usb_debug.h> 72 #include <dev/usb/usb_busdma.h> 73 #include <dev/usb/usb_process.h> 74 #include <dev/usb/usb_transfer.h> 75 #include <dev/usb/usb_device.h> 76 #include <dev/usb/usb_hub.h> 77 #include <dev/usb/usb_util.h> 78 79 #include <dev/usb/usb_controller.h> 80 #include <dev/usb/usb_bus.h> 81 #endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83 #include <dev/usb/controller/xhci.h> 84 #include <dev/usb/controller/xhcireg.h> 85 86 #define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 92 static int xhcistreams; 93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN, 94 &xhcistreams, 0, "Set to enable streams mode support"); 95 96 #ifdef USB_DEBUG 97 static int xhcidebug; 98 static int xhciroute; 99 static int xhcipolling; 100 101 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN, 102 &xhcidebug, 0, "Debug level"); 103 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN, 104 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN, 106 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller"); 107 #else 108 #define xhciroute 0 109 #endif 110 111 #define XHCI_INTR_ENDPT 1 112 113 struct xhci_std_temp { 114 struct xhci_softc *sc; 115 struct usb_page_cache *pc; 116 struct xhci_td *td; 117 struct xhci_td *td_next; 118 uint32_t len; 119 uint32_t offset; 120 uint32_t max_packet_size; 121 uint32_t average; 122 uint16_t isoc_delta; 123 uint16_t isoc_frame; 124 uint8_t shortpkt; 125 uint8_t multishort; 126 uint8_t last_frame; 127 uint8_t trb_type; 128 uint8_t direction; 129 uint8_t tbc; 130 uint8_t tlbpc; 131 uint8_t step_td; 132 uint8_t do_isoc_sync; 133 }; 134 135 static void xhci_do_poll(struct usb_bus *); 136 static void xhci_device_done(struct usb_xfer *, usb_error_t); 137 static void xhci_root_intr(struct xhci_softc *); 138 static void xhci_free_device_ext(struct usb_device *); 139 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 140 struct usb_endpoint_descriptor *); 141 static usb_proc_callback_t xhci_configure_msg; 142 static usb_error_t xhci_configure_device(struct usb_device *); 143 static usb_error_t xhci_configure_endpoint(struct usb_device *, 144 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 145 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 146 uint8_t); 147 static usb_error_t xhci_configure_mask(struct usb_device *, 148 uint32_t, uint8_t); 149 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 150 uint64_t, uint8_t); 151 static void xhci_endpoint_doorbell(struct usb_xfer *); 152 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 153 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 154 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 155 #ifdef USB_DEBUG 156 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 157 #endif 158 159 static const struct usb_bus_methods xhci_bus_methods; 160 161 #ifdef USB_DEBUG 162 static void 163 xhci_dump_trb(struct xhci_trb *trb) 164 { 165 DPRINTFN(5, "trb = %p\n", trb); 166 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 167 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 168 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 169 } 170 171 static void 172 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 173 { 174 DPRINTFN(5, "pep = %p\n", pep); 175 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 176 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 177 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 178 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 179 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 180 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 181 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 182 } 183 184 static void 185 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 186 { 187 DPRINTFN(5, "psl = %p\n", psl); 188 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 189 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 190 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 191 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 192 } 193 #endif 194 195 uint8_t 196 xhci_use_polling(void) 197 { 198 #ifdef USB_DEBUG 199 return (xhcipolling != 0); 200 #else 201 return (0); 202 #endif 203 } 204 205 static void 206 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 207 { 208 struct xhci_softc *sc = XHCI_BUS2SC(bus); 209 uint8_t i; 210 211 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 212 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 213 214 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 215 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 216 217 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 218 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 219 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 220 } 221 } 222 223 static void 224 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 225 { 226 if (sc->sc_ctx_is_64_byte) { 227 uint32_t offset; 228 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 229 /* all contexts are initially 32-bytes */ 230 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 231 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 232 } 233 *ptr = htole32(val); 234 } 235 236 static uint32_t 237 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 238 { 239 if (sc->sc_ctx_is_64_byte) { 240 uint32_t offset; 241 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 242 /* all contexts are initially 32-bytes */ 243 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 244 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 245 } 246 return (le32toh(*ptr)); 247 } 248 249 static void 250 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 251 { 252 if (sc->sc_ctx_is_64_byte) { 253 uint32_t offset; 254 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 255 /* all contexts are initially 32-bytes */ 256 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 257 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 258 } 259 *ptr = htole64(val); 260 } 261 262 #ifdef USB_DEBUG 263 static uint64_t 264 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 265 { 266 if (sc->sc_ctx_is_64_byte) { 267 uint32_t offset; 268 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 269 /* all contexts are initially 32-bytes */ 270 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 271 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 272 } 273 return (le64toh(*ptr)); 274 } 275 #endif 276 277 static int 278 xhci_reset_command_queue_locked(struct xhci_softc *sc) 279 { 280 struct usb_page_search buf_res; 281 struct xhci_hw_root *phwr; 282 uint64_t addr; 283 uint32_t temp; 284 285 DPRINTF("\n"); 286 287 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 288 if (temp & XHCI_CRCR_LO_CRR) { 289 DPRINTF("Command ring running\n"); 290 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 291 292 /* 293 * Try to abort the last command as per section 294 * 4.6.1.2 "Aborting a Command" of the XHCI 295 * specification: 296 */ 297 298 /* stop and cancel */ 299 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 300 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 301 302 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 303 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 304 305 /* wait 250ms */ 306 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 307 308 /* check if command ring is still running */ 309 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 310 if (temp & XHCI_CRCR_LO_CRR) { 311 DPRINTF("Comand ring still running\n"); 312 return (USB_ERR_IOERROR); 313 } 314 } 315 316 /* reset command ring */ 317 sc->sc_command_ccs = 1; 318 sc->sc_command_idx = 0; 319 320 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 321 322 /* setup command ring control base address */ 323 addr = buf_res.physaddr; 324 phwr = buf_res.buffer; 325 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 326 327 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 328 329 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 330 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 331 332 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 333 334 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 335 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 336 337 return (0); 338 } 339 340 usb_error_t 341 xhci_start_controller(struct xhci_softc *sc) 342 { 343 struct usb_page_search buf_res; 344 struct xhci_hw_root *phwr; 345 struct xhci_dev_ctx_addr *pdctxa; 346 uint64_t addr; 347 uint32_t temp; 348 uint16_t i; 349 350 DPRINTF("\n"); 351 352 sc->sc_capa_off = 0; 353 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 354 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 355 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 356 357 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 358 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 359 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 360 361 sc->sc_event_ccs = 1; 362 sc->sc_event_idx = 0; 363 sc->sc_command_ccs = 1; 364 sc->sc_command_idx = 0; 365 366 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 367 368 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 369 370 DPRINTF("HCS0 = 0x%08x\n", temp); 371 372 if (XHCI_HCS0_CSZ(temp)) { 373 sc->sc_ctx_is_64_byte = 1; 374 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 375 } else { 376 sc->sc_ctx_is_64_byte = 0; 377 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 378 } 379 380 /* Reset controller */ 381 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 382 383 for (i = 0; i != 100; i++) { 384 usb_pause_mtx(NULL, hz / 100); 385 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 386 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 387 if (!temp) 388 break; 389 } 390 391 if (temp) { 392 device_printf(sc->sc_bus.parent, "Controller " 393 "reset timeout.\n"); 394 return (USB_ERR_IOERROR); 395 } 396 397 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 398 device_printf(sc->sc_bus.parent, "Controller does " 399 "not support 4K page size.\n"); 400 return (USB_ERR_IOERROR); 401 } 402 403 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 404 405 i = XHCI_HCS1_N_PORTS(temp); 406 407 if (i == 0) { 408 device_printf(sc->sc_bus.parent, "Invalid number " 409 "of ports: %u\n", i); 410 return (USB_ERR_IOERROR); 411 } 412 413 sc->sc_noport = i; 414 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 415 416 if (sc->sc_noslot > XHCI_MAX_DEVICES) 417 sc->sc_noslot = XHCI_MAX_DEVICES; 418 419 /* setup number of device slots */ 420 421 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 422 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 423 424 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 425 426 DPRINTF("Max slots: %u\n", sc->sc_noslot); 427 428 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 429 430 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 431 432 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 433 device_printf(sc->sc_bus.parent, "XHCI request " 434 "too many scratchpads\n"); 435 return (USB_ERR_NOMEM); 436 } 437 438 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 439 440 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 441 442 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 443 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 444 445 temp = XREAD4(sc, oper, XHCI_USBSTS); 446 447 /* clear interrupts */ 448 XWRITE4(sc, oper, XHCI_USBSTS, temp); 449 /* disable all device notifications */ 450 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 451 452 /* setup device context base address */ 453 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 454 pdctxa = buf_res.buffer; 455 memset(pdctxa, 0, sizeof(*pdctxa)); 456 457 addr = buf_res.physaddr; 458 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 459 460 /* slot 0 points to the table of scratchpad pointers */ 461 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 462 463 for (i = 0; i != sc->sc_noscratch; i++) { 464 struct usb_page_search buf_scp; 465 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 466 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 467 } 468 469 addr = buf_res.physaddr; 470 471 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 472 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 473 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 474 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 475 476 /* Setup event table size */ 477 478 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 479 480 DPRINTF("HCS2=0x%08x\n", temp); 481 482 temp = XHCI_HCS2_ERST_MAX(temp); 483 temp = 1U << temp; 484 if (temp > XHCI_MAX_RSEG) 485 temp = XHCI_MAX_RSEG; 486 487 sc->sc_erst_max = temp; 488 489 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 490 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 491 492 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 493 494 /* Check if we should use the default IMOD value */ 495 if (sc->sc_imod_default == 0) 496 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 497 498 /* Setup interrupt rate */ 499 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 500 501 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 502 503 phwr = buf_res.buffer; 504 addr = buf_res.physaddr; 505 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 506 507 /* reset hardware root structure */ 508 memset(phwr, 0, sizeof(*phwr)); 509 510 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 511 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 512 513 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 514 515 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 516 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 517 518 addr = (uint64_t)buf_res.physaddr; 519 520 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 521 522 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 523 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 524 525 /* Setup interrupter registers */ 526 527 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 528 temp |= XHCI_IMAN_INTR_ENA; 529 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 530 531 /* setup command ring control base address */ 532 addr = buf_res.physaddr; 533 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 534 535 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 536 537 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 538 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 539 540 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 541 542 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 543 544 /* Go! */ 545 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 546 XHCI_CMD_INTE | XHCI_CMD_HSEE); 547 548 for (i = 0; i != 100; i++) { 549 usb_pause_mtx(NULL, hz / 100); 550 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 551 if (!temp) 552 break; 553 } 554 if (temp) { 555 XWRITE4(sc, oper, XHCI_USBCMD, 0); 556 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 557 return (USB_ERR_IOERROR); 558 } 559 560 /* catch any lost interrupts */ 561 xhci_do_poll(&sc->sc_bus); 562 563 if (sc->sc_port_route != NULL) { 564 /* Route all ports to the XHCI by default */ 565 sc->sc_port_route(sc->sc_bus.parent, 566 ~xhciroute, xhciroute); 567 } 568 return (0); 569 } 570 571 usb_error_t 572 xhci_halt_controller(struct xhci_softc *sc) 573 { 574 uint32_t temp; 575 uint16_t i; 576 577 DPRINTF("\n"); 578 579 sc->sc_capa_off = 0; 580 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 581 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 582 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 583 584 /* Halt controller */ 585 XWRITE4(sc, oper, XHCI_USBCMD, 0); 586 587 for (i = 0; i != 100; i++) { 588 usb_pause_mtx(NULL, hz / 100); 589 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 590 if (temp) 591 break; 592 } 593 594 if (!temp) { 595 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 596 return (USB_ERR_IOERROR); 597 } 598 return (0); 599 } 600 601 usb_error_t 602 xhci_init(struct xhci_softc *sc, device_t self) 603 { 604 /* initialise some bus fields */ 605 sc->sc_bus.parent = self; 606 607 /* set the bus revision */ 608 sc->sc_bus.usbrev = USB_REV_3_0; 609 610 /* set up the bus struct */ 611 sc->sc_bus.methods = &xhci_bus_methods; 612 613 /* setup devices array */ 614 sc->sc_bus.devices = sc->sc_devices; 615 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 616 617 /* set default cycle state in case of early interrupts */ 618 sc->sc_event_ccs = 1; 619 sc->sc_command_ccs = 1; 620 621 /* setup command queue mutex and condition varible */ 622 cv_init(&sc->sc_cmd_cv, "CMDQ"); 623 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 624 625 /* get all DMA memory */ 626 if (usb_bus_mem_alloc_all(&sc->sc_bus, 627 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 628 return (ENOMEM); 629 } 630 631 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 632 sc->sc_config_msg[0].bus = &sc->sc_bus; 633 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 634 sc->sc_config_msg[1].bus = &sc->sc_bus; 635 636 return (0); 637 } 638 639 void 640 xhci_uninit(struct xhci_softc *sc) 641 { 642 /* 643 * NOTE: At this point the control transfer process is gone 644 * and "xhci_configure_msg" is no longer called. Consequently 645 * waiting for the configuration messages to complete is not 646 * needed. 647 */ 648 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 649 650 cv_destroy(&sc->sc_cmd_cv); 651 sx_destroy(&sc->sc_cmd_sx); 652 } 653 654 static void 655 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 656 { 657 struct xhci_softc *sc = XHCI_BUS2SC(bus); 658 659 switch (state) { 660 case USB_HW_POWER_SUSPEND: 661 DPRINTF("Stopping the XHCI\n"); 662 xhci_halt_controller(sc); 663 break; 664 case USB_HW_POWER_SHUTDOWN: 665 DPRINTF("Stopping the XHCI\n"); 666 xhci_halt_controller(sc); 667 break; 668 case USB_HW_POWER_RESUME: 669 DPRINTF("Starting the XHCI\n"); 670 xhci_start_controller(sc); 671 break; 672 default: 673 break; 674 } 675 } 676 677 static usb_error_t 678 xhci_generic_done_sub(struct usb_xfer *xfer) 679 { 680 struct xhci_td *td; 681 struct xhci_td *td_alt_next; 682 uint32_t len; 683 uint8_t status; 684 685 td = xfer->td_transfer_cache; 686 td_alt_next = td->alt_next; 687 688 if (xfer->aframes != xfer->nframes) 689 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 690 691 while (1) { 692 693 usb_pc_cpu_invalidate(td->page_cache); 694 695 status = td->status; 696 len = td->remainder; 697 698 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 699 xfer, (unsigned int)xfer->aframes, 700 (unsigned int)xfer->nframes, 701 (unsigned int)len, (unsigned int)td->len, 702 (unsigned int)status); 703 704 /* 705 * Verify the status length and 706 * add the length to "frlengths[]": 707 */ 708 if (len > td->len) { 709 /* should not happen */ 710 DPRINTF("Invalid status length, " 711 "0x%04x/0x%04x bytes\n", len, td->len); 712 status = XHCI_TRB_ERROR_LENGTH; 713 } else if (xfer->aframes != xfer->nframes) { 714 xfer->frlengths[xfer->aframes] += td->len - len; 715 } 716 /* Check for last transfer */ 717 if (((void *)td) == xfer->td_transfer_last) { 718 td = NULL; 719 break; 720 } 721 /* Check for transfer error */ 722 if (status != XHCI_TRB_ERROR_SHORT_PKT && 723 status != XHCI_TRB_ERROR_SUCCESS) { 724 /* the transfer is finished */ 725 td = NULL; 726 break; 727 } 728 /* Check for short transfer */ 729 if (len > 0) { 730 if (xfer->flags_int.short_frames_ok || 731 xfer->flags_int.isochronous_xfr || 732 xfer->flags_int.control_xfr) { 733 /* follow alt next */ 734 td = td->alt_next; 735 } else { 736 /* the transfer is finished */ 737 td = NULL; 738 } 739 break; 740 } 741 td = td->obj_next; 742 743 if (td->alt_next != td_alt_next) { 744 /* this USB frame is complete */ 745 break; 746 } 747 } 748 749 /* update transfer cache */ 750 751 xfer->td_transfer_cache = td; 752 753 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 754 (status != XHCI_TRB_ERROR_SHORT_PKT && 755 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 756 USB_ERR_NORMAL_COMPLETION); 757 } 758 759 static void 760 xhci_generic_done(struct usb_xfer *xfer) 761 { 762 usb_error_t err = 0; 763 764 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 765 xfer, xfer->endpoint); 766 767 /* reset scanner */ 768 769 xfer->td_transfer_cache = xfer->td_transfer_first; 770 771 if (xfer->flags_int.control_xfr) { 772 773 if (xfer->flags_int.control_hdr) 774 err = xhci_generic_done_sub(xfer); 775 776 xfer->aframes = 1; 777 778 if (xfer->td_transfer_cache == NULL) 779 goto done; 780 } 781 782 while (xfer->aframes != xfer->nframes) { 783 784 err = xhci_generic_done_sub(xfer); 785 xfer->aframes++; 786 787 if (xfer->td_transfer_cache == NULL) 788 goto done; 789 } 790 791 if (xfer->flags_int.control_xfr && 792 !xfer->flags_int.control_act) 793 err = xhci_generic_done_sub(xfer); 794 done: 795 /* transfer is complete */ 796 xhci_device_done(xfer, err); 797 } 798 799 static void 800 xhci_activate_transfer(struct usb_xfer *xfer) 801 { 802 struct xhci_td *td; 803 804 td = xfer->td_transfer_cache; 805 806 usb_pc_cpu_invalidate(td->page_cache); 807 808 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 809 810 /* activate the transfer */ 811 812 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 813 usb_pc_cpu_flush(td->page_cache); 814 815 xhci_endpoint_doorbell(xfer); 816 } 817 } 818 819 static void 820 xhci_skip_transfer(struct usb_xfer *xfer) 821 { 822 struct xhci_td *td; 823 struct xhci_td *td_last; 824 825 td = xfer->td_transfer_cache; 826 td_last = xfer->td_transfer_last; 827 828 td = td->alt_next; 829 830 usb_pc_cpu_invalidate(td->page_cache); 831 832 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 833 834 usb_pc_cpu_invalidate(td_last->page_cache); 835 836 /* copy LINK TRB to current waiting location */ 837 838 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 839 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 840 usb_pc_cpu_flush(td->page_cache); 841 842 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 843 usb_pc_cpu_flush(td->page_cache); 844 845 xhci_endpoint_doorbell(xfer); 846 } 847 } 848 849 /*------------------------------------------------------------------------* 850 * xhci_check_transfer 851 *------------------------------------------------------------------------*/ 852 static void 853 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 854 { 855 struct xhci_endpoint_ext *pepext; 856 int64_t offset; 857 uint64_t td_event; 858 uint32_t temp; 859 uint32_t remainder; 860 uint16_t stream_id; 861 uint16_t i; 862 uint8_t status; 863 uint8_t halted; 864 uint8_t epno; 865 uint8_t index; 866 867 /* decode TRB */ 868 td_event = le64toh(trb->qwTrb0); 869 temp = le32toh(trb->dwTrb2); 870 871 remainder = XHCI_TRB_2_REM_GET(temp); 872 status = XHCI_TRB_2_ERROR_GET(temp); 873 stream_id = XHCI_TRB_2_STREAM_GET(temp); 874 875 temp = le32toh(trb->dwTrb3); 876 epno = XHCI_TRB_3_EP_GET(temp); 877 index = XHCI_TRB_3_SLOT_GET(temp); 878 879 /* check if error means halted */ 880 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 881 status != XHCI_TRB_ERROR_SUCCESS); 882 883 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 884 index, epno, stream_id, remainder, status); 885 886 if (index > sc->sc_noslot) { 887 DPRINTF("Invalid slot.\n"); 888 return; 889 } 890 891 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 892 DPRINTF("Invalid endpoint.\n"); 893 return; 894 } 895 896 pepext = &sc->sc_hw.devs[index].endp[epno]; 897 898 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 899 stream_id = 0; 900 DPRINTF("stream_id=0\n"); 901 } else if (stream_id >= XHCI_MAX_STREAMS) { 902 DPRINTF("Invalid stream ID.\n"); 903 return; 904 } 905 906 /* try to find the USB transfer that generated the event */ 907 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 908 struct usb_xfer *xfer; 909 struct xhci_td *td; 910 911 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 912 if (xfer == NULL) 913 continue; 914 915 td = xfer->td_transfer_cache; 916 917 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 918 (long long)td_event, 919 (long long)td->td_self, 920 (long long)td->td_self + sizeof(td->td_trb)); 921 922 /* 923 * NOTE: Some XHCI implementations might not trigger 924 * an event on the last LINK TRB so we need to 925 * consider both the last and second last event 926 * address as conditions for a successful transfer. 927 * 928 * NOTE: We assume that the XHCI will only trigger one 929 * event per chain of TRBs. 930 */ 931 932 offset = td_event - td->td_self; 933 934 if (offset >= 0 && 935 offset < (int64_t)sizeof(td->td_trb)) { 936 937 usb_pc_cpu_invalidate(td->page_cache); 938 939 /* compute rest of remainder, if any */ 940 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 941 temp = le32toh(td->td_trb[i].dwTrb2); 942 remainder += XHCI_TRB_2_BYTES_GET(temp); 943 } 944 945 DPRINTFN(5, "New remainder: %u\n", remainder); 946 947 /* clear isochronous transfer errors */ 948 if (xfer->flags_int.isochronous_xfr) { 949 if (halted) { 950 halted = 0; 951 status = XHCI_TRB_ERROR_SUCCESS; 952 remainder = td->len; 953 } 954 } 955 956 /* "td->remainder" is verified later */ 957 td->remainder = remainder; 958 td->status = status; 959 960 usb_pc_cpu_flush(td->page_cache); 961 962 /* 963 * 1) Last transfer descriptor makes the 964 * transfer done 965 */ 966 if (((void *)td) == xfer->td_transfer_last) { 967 DPRINTF("TD is last\n"); 968 xhci_generic_done(xfer); 969 break; 970 } 971 972 /* 973 * 2) Any kind of error makes the transfer 974 * done 975 */ 976 if (halted) { 977 DPRINTF("TD has I/O error\n"); 978 xhci_generic_done(xfer); 979 break; 980 } 981 982 /* 983 * 3) If there is no alternate next transfer, 984 * a short packet also makes the transfer done 985 */ 986 if (td->remainder > 0) { 987 if (td->alt_next == NULL) { 988 DPRINTF( 989 "short TD has no alternate next\n"); 990 xhci_generic_done(xfer); 991 break; 992 } 993 DPRINTF("TD has short pkt\n"); 994 if (xfer->flags_int.short_frames_ok || 995 xfer->flags_int.isochronous_xfr || 996 xfer->flags_int.control_xfr) { 997 /* follow the alt next */ 998 xfer->td_transfer_cache = td->alt_next; 999 xhci_activate_transfer(xfer); 1000 break; 1001 } 1002 xhci_skip_transfer(xfer); 1003 xhci_generic_done(xfer); 1004 break; 1005 } 1006 1007 /* 1008 * 4) Transfer complete - go to next TD 1009 */ 1010 DPRINTF("Following next TD\n"); 1011 xfer->td_transfer_cache = td->obj_next; 1012 xhci_activate_transfer(xfer); 1013 break; /* there should only be one match */ 1014 } 1015 } 1016 } 1017 1018 static int 1019 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1020 { 1021 if (sc->sc_cmd_addr == trb->qwTrb0) { 1022 DPRINTF("Received command event\n"); 1023 sc->sc_cmd_result[0] = trb->dwTrb2; 1024 sc->sc_cmd_result[1] = trb->dwTrb3; 1025 cv_signal(&sc->sc_cmd_cv); 1026 return (1); /* command match */ 1027 } 1028 return (0); 1029 } 1030 1031 static int 1032 xhci_interrupt_poll(struct xhci_softc *sc) 1033 { 1034 struct usb_page_search buf_res; 1035 struct xhci_hw_root *phwr; 1036 uint64_t addr; 1037 uint32_t temp; 1038 int retval = 0; 1039 uint16_t i; 1040 uint8_t event; 1041 uint8_t j; 1042 uint8_t k; 1043 uint8_t t; 1044 1045 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1046 1047 phwr = buf_res.buffer; 1048 1049 /* Receive any events */ 1050 1051 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1052 1053 i = sc->sc_event_idx; 1054 j = sc->sc_event_ccs; 1055 t = 2; 1056 1057 while (1) { 1058 1059 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1060 1061 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1062 1063 if (j != k) 1064 break; 1065 1066 event = XHCI_TRB_3_TYPE_GET(temp); 1067 1068 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1069 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1070 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1071 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1072 1073 switch (event) { 1074 case XHCI_TRB_EVENT_TRANSFER: 1075 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1076 break; 1077 case XHCI_TRB_EVENT_CMD_COMPLETE: 1078 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1079 break; 1080 default: 1081 DPRINTF("Unhandled event = %u\n", event); 1082 break; 1083 } 1084 1085 i++; 1086 1087 if (i == XHCI_MAX_EVENTS) { 1088 i = 0; 1089 j ^= 1; 1090 1091 /* check for timeout */ 1092 if (!--t) 1093 break; 1094 } 1095 } 1096 1097 sc->sc_event_idx = i; 1098 sc->sc_event_ccs = j; 1099 1100 /* 1101 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1102 * latched. That means to activate the register we need to 1103 * write both the low and high double word of the 64-bit 1104 * register. 1105 */ 1106 1107 addr = (uint32_t)buf_res.physaddr; 1108 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1109 1110 /* try to clear busy bit */ 1111 addr |= XHCI_ERDP_LO_BUSY; 1112 1113 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1114 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1115 1116 return (retval); 1117 } 1118 1119 static usb_error_t 1120 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1121 uint16_t timeout_ms) 1122 { 1123 struct usb_page_search buf_res; 1124 struct xhci_hw_root *phwr; 1125 uint64_t addr; 1126 uint32_t temp; 1127 uint8_t i; 1128 uint8_t j; 1129 uint8_t timeout = 0; 1130 int err; 1131 1132 XHCI_CMD_ASSERT_LOCKED(sc); 1133 1134 /* get hardware root structure */ 1135 1136 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1137 1138 phwr = buf_res.buffer; 1139 1140 /* Queue command */ 1141 1142 USB_BUS_LOCK(&sc->sc_bus); 1143 retry: 1144 i = sc->sc_command_idx; 1145 j = sc->sc_command_ccs; 1146 1147 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1148 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1149 (long long)le64toh(trb->qwTrb0), 1150 (long)le32toh(trb->dwTrb2), 1151 (long)le32toh(trb->dwTrb3)); 1152 1153 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1154 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1155 1156 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1157 1158 temp = trb->dwTrb3; 1159 1160 if (j) 1161 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1162 else 1163 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1164 1165 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1166 1167 phwr->hwr_commands[i].dwTrb3 = temp; 1168 1169 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1170 1171 addr = buf_res.physaddr; 1172 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1173 1174 sc->sc_cmd_addr = htole64(addr); 1175 1176 i++; 1177 1178 if (i == (XHCI_MAX_COMMANDS - 1)) { 1179 1180 if (j) { 1181 temp = htole32(XHCI_TRB_3_TC_BIT | 1182 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1183 XHCI_TRB_3_CYCLE_BIT); 1184 } else { 1185 temp = htole32(XHCI_TRB_3_TC_BIT | 1186 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1187 } 1188 1189 phwr->hwr_commands[i].dwTrb3 = temp; 1190 1191 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1192 1193 i = 0; 1194 j ^= 1; 1195 } 1196 1197 sc->sc_command_idx = i; 1198 sc->sc_command_ccs = j; 1199 1200 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1201 1202 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1203 USB_MS_TO_TICKS(timeout_ms)); 1204 1205 /* 1206 * In some error cases event interrupts are not generated. 1207 * Poll one time to see if the command has completed. 1208 */ 1209 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1210 DPRINTF("Command was completed when polling\n"); 1211 err = 0; 1212 } 1213 if (err != 0) { 1214 DPRINTF("Command timeout!\n"); 1215 /* 1216 * After some weeks of continuous operation, it has 1217 * been observed that the ASMedia Technology, ASM1042 1218 * SuperSpeed USB Host Controller can suddenly stop 1219 * accepting commands via the command queue. Try to 1220 * first reset the command queue. If that fails do a 1221 * host controller reset. 1222 */ 1223 if (timeout == 0 && 1224 xhci_reset_command_queue_locked(sc) == 0) { 1225 temp = le32toh(trb->dwTrb3); 1226 1227 /* 1228 * Avoid infinite XHCI reset loops if the set 1229 * address command fails to respond due to a 1230 * non-enumerating device: 1231 */ 1232 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1233 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1234 DPRINTF("Set address timeout\n"); 1235 } else { 1236 timeout = 1; 1237 goto retry; 1238 } 1239 } else { 1240 DPRINTF("Controller reset!\n"); 1241 usb_bus_reset_async_locked(&sc->sc_bus); 1242 } 1243 err = USB_ERR_TIMEOUT; 1244 trb->dwTrb2 = 0; 1245 trb->dwTrb3 = 0; 1246 } else { 1247 temp = le32toh(sc->sc_cmd_result[0]); 1248 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1249 err = USB_ERR_IOERROR; 1250 1251 trb->dwTrb2 = sc->sc_cmd_result[0]; 1252 trb->dwTrb3 = sc->sc_cmd_result[1]; 1253 } 1254 1255 USB_BUS_UNLOCK(&sc->sc_bus); 1256 1257 return (err); 1258 } 1259 1260 #if 0 1261 static usb_error_t 1262 xhci_cmd_nop(struct xhci_softc *sc) 1263 { 1264 struct xhci_trb trb; 1265 uint32_t temp; 1266 1267 DPRINTF("\n"); 1268 1269 trb.qwTrb0 = 0; 1270 trb.dwTrb2 = 0; 1271 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1272 1273 trb.dwTrb3 = htole32(temp); 1274 1275 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1276 } 1277 #endif 1278 1279 static usb_error_t 1280 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1281 { 1282 struct xhci_trb trb; 1283 uint32_t temp; 1284 usb_error_t err; 1285 1286 DPRINTF("\n"); 1287 1288 trb.qwTrb0 = 0; 1289 trb.dwTrb2 = 0; 1290 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1291 1292 err = xhci_do_command(sc, &trb, 100 /* ms */); 1293 if (err) 1294 goto done; 1295 1296 temp = le32toh(trb.dwTrb3); 1297 1298 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1299 1300 done: 1301 return (err); 1302 } 1303 1304 static usb_error_t 1305 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1306 { 1307 struct xhci_trb trb; 1308 uint32_t temp; 1309 1310 DPRINTF("\n"); 1311 1312 trb.qwTrb0 = 0; 1313 trb.dwTrb2 = 0; 1314 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1315 XHCI_TRB_3_SLOT_SET(slot_id); 1316 1317 trb.dwTrb3 = htole32(temp); 1318 1319 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1320 } 1321 1322 static usb_error_t 1323 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1324 uint8_t bsr, uint8_t slot_id) 1325 { 1326 struct xhci_trb trb; 1327 uint32_t temp; 1328 1329 DPRINTF("\n"); 1330 1331 trb.qwTrb0 = htole64(input_ctx); 1332 trb.dwTrb2 = 0; 1333 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1334 XHCI_TRB_3_SLOT_SET(slot_id); 1335 1336 if (bsr) 1337 temp |= XHCI_TRB_3_BSR_BIT; 1338 1339 trb.dwTrb3 = htole32(temp); 1340 1341 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1342 } 1343 1344 static usb_error_t 1345 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1346 { 1347 struct usb_page_search buf_inp; 1348 struct usb_page_search buf_dev; 1349 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1350 struct xhci_hw_dev *hdev; 1351 struct xhci_dev_ctx *pdev; 1352 struct xhci_endpoint_ext *pepext; 1353 uint32_t temp; 1354 uint16_t mps; 1355 usb_error_t err; 1356 uint8_t index; 1357 1358 /* the root HUB case is not handled here */ 1359 if (udev->parent_hub == NULL) 1360 return (USB_ERR_INVAL); 1361 1362 index = udev->controller_slot_id; 1363 1364 hdev = &sc->sc_hw.devs[index]; 1365 1366 if (mtx != NULL) 1367 mtx_unlock(mtx); 1368 1369 XHCI_CMD_LOCK(sc); 1370 1371 switch (hdev->state) { 1372 case XHCI_ST_DEFAULT: 1373 case XHCI_ST_ENABLED: 1374 1375 hdev->state = XHCI_ST_ENABLED; 1376 1377 /* set configure mask to slot and EP0 */ 1378 xhci_configure_mask(udev, 3, 0); 1379 1380 /* configure input slot context structure */ 1381 err = xhci_configure_device(udev); 1382 1383 if (err != 0) { 1384 DPRINTF("Could not configure device\n"); 1385 break; 1386 } 1387 1388 /* configure input endpoint context structure */ 1389 switch (udev->speed) { 1390 case USB_SPEED_LOW: 1391 case USB_SPEED_FULL: 1392 mps = 8; 1393 break; 1394 case USB_SPEED_HIGH: 1395 mps = 64; 1396 break; 1397 default: 1398 mps = 512; 1399 break; 1400 } 1401 1402 pepext = xhci_get_endpoint_ext(udev, 1403 &udev->ctrl_ep_desc); 1404 err = xhci_configure_endpoint(udev, 1405 &udev->ctrl_ep_desc, pepext, 1406 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1407 1408 if (err != 0) { 1409 DPRINTF("Could not configure default endpoint\n"); 1410 break; 1411 } 1412 1413 /* execute set address command */ 1414 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1415 1416 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1417 (address == 0), index); 1418 1419 if (err != 0) { 1420 temp = le32toh(sc->sc_cmd_result[0]); 1421 if (address == 0 && sc->sc_port_route != NULL && 1422 XHCI_TRB_2_ERROR_GET(temp) == 1423 XHCI_TRB_ERROR_PARAMETER) { 1424 /* LynxPoint XHCI - ports are not switchable */ 1425 /* Un-route all ports from the XHCI */ 1426 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1427 } 1428 DPRINTF("Could not set address " 1429 "for slot %u.\n", index); 1430 if (address != 0) 1431 break; 1432 } 1433 1434 /* update device address to new value */ 1435 1436 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1437 pdev = buf_dev.buffer; 1438 usb_pc_cpu_invalidate(&hdev->device_pc); 1439 1440 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1441 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1442 1443 /* update device state to new value */ 1444 1445 if (address != 0) 1446 hdev->state = XHCI_ST_ADDRESSED; 1447 else 1448 hdev->state = XHCI_ST_DEFAULT; 1449 break; 1450 1451 default: 1452 DPRINTF("Wrong state for set address.\n"); 1453 err = USB_ERR_IOERROR; 1454 break; 1455 } 1456 XHCI_CMD_UNLOCK(sc); 1457 1458 if (mtx != NULL) 1459 mtx_lock(mtx); 1460 1461 return (err); 1462 } 1463 1464 static usb_error_t 1465 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1466 uint8_t deconfigure, uint8_t slot_id) 1467 { 1468 struct xhci_trb trb; 1469 uint32_t temp; 1470 1471 DPRINTF("\n"); 1472 1473 trb.qwTrb0 = htole64(input_ctx); 1474 trb.dwTrb2 = 0; 1475 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1476 XHCI_TRB_3_SLOT_SET(slot_id); 1477 1478 if (deconfigure) 1479 temp |= XHCI_TRB_3_DCEP_BIT; 1480 1481 trb.dwTrb3 = htole32(temp); 1482 1483 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1484 } 1485 1486 static usb_error_t 1487 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1488 uint8_t slot_id) 1489 { 1490 struct xhci_trb trb; 1491 uint32_t temp; 1492 1493 DPRINTF("\n"); 1494 1495 trb.qwTrb0 = htole64(input_ctx); 1496 trb.dwTrb2 = 0; 1497 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1498 XHCI_TRB_3_SLOT_SET(slot_id); 1499 trb.dwTrb3 = htole32(temp); 1500 1501 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1502 } 1503 1504 static usb_error_t 1505 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1506 uint8_t ep_id, uint8_t slot_id) 1507 { 1508 struct xhci_trb trb; 1509 uint32_t temp; 1510 1511 DPRINTF("\n"); 1512 1513 trb.qwTrb0 = 0; 1514 trb.dwTrb2 = 0; 1515 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1516 XHCI_TRB_3_SLOT_SET(slot_id) | 1517 XHCI_TRB_3_EP_SET(ep_id); 1518 1519 if (preserve) 1520 temp |= XHCI_TRB_3_PRSV_BIT; 1521 1522 trb.dwTrb3 = htole32(temp); 1523 1524 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1525 } 1526 1527 static usb_error_t 1528 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1529 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1530 { 1531 struct xhci_trb trb; 1532 uint32_t temp; 1533 1534 DPRINTF("\n"); 1535 1536 trb.qwTrb0 = htole64(dequeue_ptr); 1537 1538 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1539 trb.dwTrb2 = htole32(temp); 1540 1541 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1542 XHCI_TRB_3_SLOT_SET(slot_id) | 1543 XHCI_TRB_3_EP_SET(ep_id); 1544 trb.dwTrb3 = htole32(temp); 1545 1546 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1547 } 1548 1549 static usb_error_t 1550 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1551 uint8_t ep_id, uint8_t slot_id) 1552 { 1553 struct xhci_trb trb; 1554 uint32_t temp; 1555 1556 DPRINTF("\n"); 1557 1558 trb.qwTrb0 = 0; 1559 trb.dwTrb2 = 0; 1560 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1561 XHCI_TRB_3_SLOT_SET(slot_id) | 1562 XHCI_TRB_3_EP_SET(ep_id); 1563 1564 if (suspend) 1565 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1566 1567 trb.dwTrb3 = htole32(temp); 1568 1569 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1570 } 1571 1572 static usb_error_t 1573 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1574 { 1575 struct xhci_trb trb; 1576 uint32_t temp; 1577 1578 DPRINTF("\n"); 1579 1580 trb.qwTrb0 = 0; 1581 trb.dwTrb2 = 0; 1582 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1583 XHCI_TRB_3_SLOT_SET(slot_id); 1584 1585 trb.dwTrb3 = htole32(temp); 1586 1587 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1588 } 1589 1590 /*------------------------------------------------------------------------* 1591 * xhci_interrupt - XHCI interrupt handler 1592 *------------------------------------------------------------------------*/ 1593 void 1594 xhci_interrupt(struct xhci_softc *sc) 1595 { 1596 uint32_t status; 1597 uint32_t temp; 1598 1599 USB_BUS_LOCK(&sc->sc_bus); 1600 1601 status = XREAD4(sc, oper, XHCI_USBSTS); 1602 1603 /* acknowledge interrupts, if any */ 1604 if (status != 0) { 1605 XWRITE4(sc, oper, XHCI_USBSTS, status); 1606 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1607 } 1608 1609 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1610 1611 /* force clearing of pending interrupts */ 1612 if (temp & XHCI_IMAN_INTR_PEND) 1613 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1614 1615 /* check for event(s) */ 1616 xhci_interrupt_poll(sc); 1617 1618 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1619 XHCI_STS_HSE | XHCI_STS_HCE)) { 1620 1621 if (status & XHCI_STS_PCD) { 1622 xhci_root_intr(sc); 1623 } 1624 1625 if (status & XHCI_STS_HCH) { 1626 printf("%s: host controller halted\n", 1627 __FUNCTION__); 1628 } 1629 1630 if (status & XHCI_STS_HSE) { 1631 printf("%s: host system error\n", 1632 __FUNCTION__); 1633 } 1634 1635 if (status & XHCI_STS_HCE) { 1636 printf("%s: host controller error\n", 1637 __FUNCTION__); 1638 } 1639 } 1640 USB_BUS_UNLOCK(&sc->sc_bus); 1641 } 1642 1643 /*------------------------------------------------------------------------* 1644 * xhci_timeout - XHCI timeout handler 1645 *------------------------------------------------------------------------*/ 1646 static void 1647 xhci_timeout(void *arg) 1648 { 1649 struct usb_xfer *xfer = arg; 1650 1651 DPRINTF("xfer=%p\n", xfer); 1652 1653 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1654 1655 /* transfer is transferred */ 1656 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1657 } 1658 1659 static void 1660 xhci_do_poll(struct usb_bus *bus) 1661 { 1662 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1663 1664 USB_BUS_LOCK(&sc->sc_bus); 1665 xhci_interrupt_poll(sc); 1666 USB_BUS_UNLOCK(&sc->sc_bus); 1667 } 1668 1669 static void 1670 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1671 { 1672 struct usb_page_search buf_res; 1673 struct xhci_td *td; 1674 struct xhci_td *td_next; 1675 struct xhci_td *td_alt_next; 1676 struct xhci_td *td_first; 1677 uint32_t buf_offset; 1678 uint32_t average; 1679 uint32_t len_old; 1680 uint32_t npkt_off; 1681 uint32_t dword; 1682 uint8_t shortpkt_old; 1683 uint8_t precompute; 1684 uint8_t x; 1685 1686 td_alt_next = NULL; 1687 buf_offset = 0; 1688 shortpkt_old = temp->shortpkt; 1689 len_old = temp->len; 1690 npkt_off = 0; 1691 precompute = 1; 1692 1693 restart: 1694 1695 td = temp->td; 1696 td_next = td_first = temp->td_next; 1697 1698 while (1) { 1699 1700 if (temp->len == 0) { 1701 1702 if (temp->shortpkt) 1703 break; 1704 1705 /* send a Zero Length Packet, ZLP, last */ 1706 1707 temp->shortpkt = 1; 1708 average = 0; 1709 1710 } else { 1711 1712 average = temp->average; 1713 1714 if (temp->len < average) { 1715 if (temp->len % temp->max_packet_size) { 1716 temp->shortpkt = 1; 1717 } 1718 average = temp->len; 1719 } 1720 } 1721 1722 if (td_next == NULL) 1723 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1724 1725 /* get next TD */ 1726 1727 td = td_next; 1728 td_next = td->obj_next; 1729 1730 /* check if we are pre-computing */ 1731 1732 if (precompute) { 1733 1734 /* update remaining length */ 1735 1736 temp->len -= average; 1737 1738 continue; 1739 } 1740 /* fill out current TD */ 1741 1742 td->len = average; 1743 td->remainder = 0; 1744 td->status = 0; 1745 1746 /* update remaining length */ 1747 1748 temp->len -= average; 1749 1750 /* reset TRB index */ 1751 1752 x = 0; 1753 1754 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1755 /* immediate data */ 1756 1757 if (average > 8) 1758 average = 8; 1759 1760 td->td_trb[0].qwTrb0 = 0; 1761 1762 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1763 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1764 average); 1765 1766 dword = XHCI_TRB_2_BYTES_SET(8) | 1767 XHCI_TRB_2_TDSZ_SET(0) | 1768 XHCI_TRB_2_IRQ_SET(0); 1769 1770 td->td_trb[0].dwTrb2 = htole32(dword); 1771 1772 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1773 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1774 1775 /* check wLength */ 1776 if (td->td_trb[0].qwTrb0 & 1777 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1778 if (td->td_trb[0].qwTrb0 & 1779 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1780 dword |= XHCI_TRB_3_TRT_IN; 1781 else 1782 dword |= XHCI_TRB_3_TRT_OUT; 1783 } 1784 1785 td->td_trb[0].dwTrb3 = htole32(dword); 1786 #ifdef USB_DEBUG 1787 xhci_dump_trb(&td->td_trb[x]); 1788 #endif 1789 x++; 1790 1791 } else do { 1792 1793 uint32_t npkt; 1794 1795 /* fill out buffer pointers */ 1796 1797 if (average == 0) { 1798 memset(&buf_res, 0, sizeof(buf_res)); 1799 } else { 1800 usbd_get_page(temp->pc, temp->offset + 1801 buf_offset, &buf_res); 1802 1803 /* get length to end of page */ 1804 if (buf_res.length > average) 1805 buf_res.length = average; 1806 1807 /* check for maximum length */ 1808 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1809 buf_res.length = XHCI_TD_PAGE_SIZE; 1810 1811 npkt_off += buf_res.length; 1812 } 1813 1814 /* setup npkt */ 1815 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1816 temp->max_packet_size; 1817 1818 if (npkt == 0) 1819 npkt = 1; 1820 else if (npkt > 31) 1821 npkt = 31; 1822 1823 /* fill out TRB's */ 1824 td->td_trb[x].qwTrb0 = 1825 htole64((uint64_t)buf_res.physaddr); 1826 1827 dword = 1828 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1829 XHCI_TRB_2_TDSZ_SET(npkt) | 1830 XHCI_TRB_2_IRQ_SET(0); 1831 1832 td->td_trb[x].dwTrb2 = htole32(dword); 1833 1834 switch (temp->trb_type) { 1835 case XHCI_TRB_TYPE_ISOCH: 1836 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1837 XHCI_TRB_3_TBC_SET(temp->tbc) | 1838 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1839 if (td != td_first) { 1840 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1841 } else if (temp->do_isoc_sync != 0) { 1842 temp->do_isoc_sync = 0; 1843 /* wait until "isoc_frame" */ 1844 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1845 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1846 } else { 1847 /* start data transfer at next interval */ 1848 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1849 XHCI_TRB_3_ISO_SIA_BIT; 1850 } 1851 if (temp->direction == UE_DIR_IN) 1852 dword |= XHCI_TRB_3_ISP_BIT; 1853 break; 1854 case XHCI_TRB_TYPE_DATA_STAGE: 1855 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1856 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1857 if (temp->direction == UE_DIR_IN) 1858 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1859 break; 1860 case XHCI_TRB_TYPE_STATUS_STAGE: 1861 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1862 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1863 if (temp->direction == UE_DIR_IN) 1864 dword |= XHCI_TRB_3_DIR_IN; 1865 break; 1866 default: /* XHCI_TRB_TYPE_NORMAL */ 1867 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1868 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1869 if (temp->direction == UE_DIR_IN) 1870 dword |= XHCI_TRB_3_ISP_BIT; 1871 break; 1872 } 1873 td->td_trb[x].dwTrb3 = htole32(dword); 1874 1875 average -= buf_res.length; 1876 buf_offset += buf_res.length; 1877 #ifdef USB_DEBUG 1878 xhci_dump_trb(&td->td_trb[x]); 1879 #endif 1880 x++; 1881 1882 } while (average != 0); 1883 1884 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1885 1886 /* store number of data TRB's */ 1887 1888 td->ntrb = x; 1889 1890 DPRINTF("NTRB=%u\n", x); 1891 1892 /* fill out link TRB */ 1893 1894 if (td_next != NULL) { 1895 /* link the current TD with the next one */ 1896 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1897 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1898 } else { 1899 /* this field will get updated later */ 1900 DPRINTF("NOLINK\n"); 1901 } 1902 1903 dword = XHCI_TRB_2_IRQ_SET(0); 1904 1905 td->td_trb[x].dwTrb2 = htole32(dword); 1906 1907 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1908 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1909 /* 1910 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1911 * frame only receives a single short packet event 1912 * by setting the CHAIN bit in the LINK field. In 1913 * addition some XHCI controllers have problems 1914 * sending a ZLP unless the CHAIN-BIT is set in 1915 * the LINK TRB. 1916 */ 1917 XHCI_TRB_3_CHAIN_BIT; 1918 1919 td->td_trb[x].dwTrb3 = htole32(dword); 1920 1921 td->alt_next = td_alt_next; 1922 #ifdef USB_DEBUG 1923 xhci_dump_trb(&td->td_trb[x]); 1924 #endif 1925 usb_pc_cpu_flush(td->page_cache); 1926 } 1927 1928 if (precompute) { 1929 precompute = 0; 1930 1931 /* setup alt next pointer, if any */ 1932 if (temp->last_frame) { 1933 td_alt_next = NULL; 1934 } else { 1935 /* we use this field internally */ 1936 td_alt_next = td_next; 1937 } 1938 1939 /* restore */ 1940 temp->shortpkt = shortpkt_old; 1941 temp->len = len_old; 1942 goto restart; 1943 } 1944 1945 /* 1946 * Remove cycle bit from the first TRB if we are 1947 * stepping them: 1948 */ 1949 if (temp->step_td != 0) { 1950 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1951 usb_pc_cpu_flush(td_first->page_cache); 1952 } 1953 1954 /* clear TD SIZE to zero, hence this is the last TRB */ 1955 /* remove chain bit because this is the last data TRB in the chain */ 1956 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1957 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1958 /* remove CHAIN-BIT from last LINK TRB */ 1959 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1960 1961 usb_pc_cpu_flush(td->page_cache); 1962 1963 temp->td = td; 1964 temp->td_next = td_next; 1965 } 1966 1967 static void 1968 xhci_setup_generic_chain(struct usb_xfer *xfer) 1969 { 1970 struct xhci_std_temp temp; 1971 struct xhci_td *td; 1972 uint32_t x; 1973 uint32_t y; 1974 uint8_t mult; 1975 1976 temp.do_isoc_sync = 0; 1977 temp.step_td = 0; 1978 temp.tbc = 0; 1979 temp.tlbpc = 0; 1980 temp.average = xfer->max_hc_frame_size; 1981 temp.max_packet_size = xfer->max_packet_size; 1982 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1983 temp.pc = NULL; 1984 temp.last_frame = 0; 1985 temp.offset = 0; 1986 temp.multishort = xfer->flags_int.isochronous_xfr || 1987 xfer->flags_int.control_xfr || 1988 xfer->flags_int.short_frames_ok; 1989 1990 /* toggle the DMA set we are using */ 1991 xfer->flags_int.curr_dma_set ^= 1; 1992 1993 /* get next DMA set */ 1994 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1995 1996 temp.td = NULL; 1997 temp.td_next = td; 1998 1999 xfer->td_transfer_first = td; 2000 xfer->td_transfer_cache = td; 2001 2002 if (xfer->flags_int.isochronous_xfr) { 2003 uint8_t shift; 2004 2005 /* compute multiplier for ISOCHRONOUS transfers */ 2006 mult = xfer->endpoint->ecomp ? 2007 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2008 : 0; 2009 /* check for USB 2.0 multiplier */ 2010 if (mult == 0) { 2011 mult = (xfer->endpoint->edesc-> 2012 wMaxPacketSize[1] >> 3) & 3; 2013 } 2014 /* range check */ 2015 if (mult > 2) 2016 mult = 3; 2017 else 2018 mult++; 2019 2020 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2021 2022 DPRINTF("MFINDEX=0x%08x\n", x); 2023 2024 switch (usbd_get_speed(xfer->xroot->udev)) { 2025 case USB_SPEED_FULL: 2026 shift = 3; 2027 temp.isoc_delta = 8; /* 1ms */ 2028 x += temp.isoc_delta - 1; 2029 x &= ~(temp.isoc_delta - 1); 2030 break; 2031 default: 2032 shift = usbd_xfer_get_fps_shift(xfer); 2033 temp.isoc_delta = 1U << shift; 2034 x += temp.isoc_delta - 1; 2035 x &= ~(temp.isoc_delta - 1); 2036 /* simple frame load balancing */ 2037 x += xfer->endpoint->usb_uframe; 2038 break; 2039 } 2040 2041 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2042 2043 if ((xfer->endpoint->is_synced == 0) || 2044 (y < (xfer->nframes << shift)) || 2045 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2046 /* 2047 * If there is data underflow or the pipe 2048 * queue is empty we schedule the transfer a 2049 * few frames ahead of the current frame 2050 * position. Else two isochronous transfers 2051 * might overlap. 2052 */ 2053 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2054 xfer->endpoint->is_synced = 1; 2055 temp.do_isoc_sync = 1; 2056 2057 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2058 } 2059 2060 /* compute isochronous completion time */ 2061 2062 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2063 2064 xfer->isoc_time_complete = 2065 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2066 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2067 2068 x = 0; 2069 temp.isoc_frame = xfer->endpoint->isoc_next; 2070 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2071 2072 xfer->endpoint->isoc_next += xfer->nframes << shift; 2073 2074 } else if (xfer->flags_int.control_xfr) { 2075 2076 /* check if we should prepend a setup message */ 2077 2078 if (xfer->flags_int.control_hdr) { 2079 2080 temp.len = xfer->frlengths[0]; 2081 temp.pc = xfer->frbuffers + 0; 2082 temp.shortpkt = temp.len ? 1 : 0; 2083 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2084 temp.direction = 0; 2085 2086 /* check for last frame */ 2087 if (xfer->nframes == 1) { 2088 /* no STATUS stage yet, SETUP is last */ 2089 if (xfer->flags_int.control_act) 2090 temp.last_frame = 1; 2091 } 2092 2093 xhci_setup_generic_chain_sub(&temp); 2094 } 2095 x = 1; 2096 mult = 1; 2097 temp.isoc_delta = 0; 2098 temp.isoc_frame = 0; 2099 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 2100 } else { 2101 x = 0; 2102 mult = 1; 2103 temp.isoc_delta = 0; 2104 temp.isoc_frame = 0; 2105 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2106 } 2107 2108 if (x != xfer->nframes) { 2109 /* setup page_cache pointer */ 2110 temp.pc = xfer->frbuffers + x; 2111 /* set endpoint direction */ 2112 temp.direction = UE_GET_DIR(xfer->endpointno); 2113 } 2114 2115 while (x != xfer->nframes) { 2116 2117 /* DATA0 / DATA1 message */ 2118 2119 temp.len = xfer->frlengths[x]; 2120 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2121 x != 0 && temp.multishort == 0); 2122 2123 x++; 2124 2125 if (x == xfer->nframes) { 2126 if (xfer->flags_int.control_xfr) { 2127 /* no STATUS stage yet, DATA is last */ 2128 if (xfer->flags_int.control_act) 2129 temp.last_frame = 1; 2130 } else { 2131 temp.last_frame = 1; 2132 } 2133 } 2134 if (temp.len == 0) { 2135 2136 /* make sure that we send an USB packet */ 2137 2138 temp.shortpkt = 0; 2139 2140 temp.tbc = 0; 2141 temp.tlbpc = mult - 1; 2142 2143 } else if (xfer->flags_int.isochronous_xfr) { 2144 2145 uint8_t tdpc; 2146 2147 /* 2148 * Isochronous transfers don't have short 2149 * packet termination: 2150 */ 2151 2152 temp.shortpkt = 1; 2153 2154 /* isochronous transfers have a transfer limit */ 2155 2156 if (temp.len > xfer->max_frame_size) 2157 temp.len = xfer->max_frame_size; 2158 2159 /* compute TD packet count */ 2160 tdpc = (temp.len + xfer->max_packet_size - 1) / 2161 xfer->max_packet_size; 2162 2163 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2164 temp.tlbpc = (tdpc % mult); 2165 2166 if (temp.tlbpc == 0) 2167 temp.tlbpc = mult - 1; 2168 else 2169 temp.tlbpc--; 2170 } else { 2171 2172 /* regular data transfer */ 2173 2174 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2175 } 2176 2177 xhci_setup_generic_chain_sub(&temp); 2178 2179 if (xfer->flags_int.isochronous_xfr) { 2180 temp.offset += xfer->frlengths[x - 1]; 2181 temp.isoc_frame += temp.isoc_delta; 2182 } else { 2183 /* get next Page Cache pointer */ 2184 temp.pc = xfer->frbuffers + x; 2185 } 2186 } 2187 2188 /* check if we should append a status stage */ 2189 2190 if (xfer->flags_int.control_xfr && 2191 !xfer->flags_int.control_act) { 2192 2193 /* 2194 * Send a DATA1 message and invert the current 2195 * endpoint direction. 2196 */ 2197 temp.step_td = (xfer->nframes != 0); 2198 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2199 temp.len = 0; 2200 temp.pc = NULL; 2201 temp.shortpkt = 0; 2202 temp.last_frame = 1; 2203 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2204 2205 xhci_setup_generic_chain_sub(&temp); 2206 } 2207 2208 td = temp.td; 2209 2210 /* must have at least one frame! */ 2211 2212 xfer->td_transfer_last = td; 2213 2214 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2215 } 2216 2217 static void 2218 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2219 { 2220 struct usb_page_search buf_res; 2221 struct xhci_dev_ctx_addr *pdctxa; 2222 2223 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2224 2225 pdctxa = buf_res.buffer; 2226 2227 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2228 2229 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2230 2231 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2232 } 2233 2234 static usb_error_t 2235 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2236 { 2237 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2238 struct usb_page_search buf_inp; 2239 struct xhci_input_dev_ctx *pinp; 2240 uint32_t temp; 2241 uint8_t index; 2242 uint8_t x; 2243 2244 index = udev->controller_slot_id; 2245 2246 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2247 2248 pinp = buf_inp.buffer; 2249 2250 if (drop) { 2251 mask &= XHCI_INCTX_NON_CTRL_MASK; 2252 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2253 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2254 } else { 2255 /* 2256 * Some hardware requires that we drop the endpoint 2257 * context before adding it again: 2258 */ 2259 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 2260 mask & XHCI_INCTX_NON_CTRL_MASK); 2261 2262 /* Add new endpoint context */ 2263 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2264 2265 /* find most significant set bit */ 2266 for (x = 31; x != 1; x--) { 2267 if (mask & (1 << x)) 2268 break; 2269 } 2270 2271 /* adjust */ 2272 x--; 2273 2274 /* figure out the maximum number of contexts */ 2275 if (x > sc->sc_hw.devs[index].context_num) 2276 sc->sc_hw.devs[index].context_num = x; 2277 else 2278 x = sc->sc_hw.devs[index].context_num; 2279 2280 /* update number of contexts */ 2281 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2282 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2283 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2284 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2285 } 2286 return (0); 2287 } 2288 2289 static usb_error_t 2290 xhci_configure_endpoint(struct usb_device *udev, 2291 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2292 uint16_t interval, uint8_t max_packet_count, 2293 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2294 uint16_t max_frame_size, uint8_t ep_mode) 2295 { 2296 struct usb_page_search buf_inp; 2297 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2298 struct xhci_input_dev_ctx *pinp; 2299 uint64_t ring_addr = pepext->physaddr; 2300 uint32_t temp; 2301 uint8_t index; 2302 uint8_t epno; 2303 uint8_t type; 2304 2305 index = udev->controller_slot_id; 2306 2307 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2308 2309 pinp = buf_inp.buffer; 2310 2311 epno = edesc->bEndpointAddress; 2312 type = edesc->bmAttributes & UE_XFERTYPE; 2313 2314 if (type == UE_CONTROL) 2315 epno |= UE_DIR_IN; 2316 2317 epno = XHCI_EPNO2EPID(epno); 2318 2319 if (epno == 0) 2320 return (USB_ERR_NO_PIPE); /* invalid */ 2321 2322 if (max_packet_count == 0) 2323 return (USB_ERR_BAD_BUFSIZE); 2324 2325 max_packet_count--; 2326 2327 if (mult == 0) 2328 return (USB_ERR_BAD_BUFSIZE); 2329 2330 /* store endpoint mode */ 2331 pepext->trb_ep_mode = ep_mode; 2332 usb_pc_cpu_flush(pepext->page_cache); 2333 2334 if (ep_mode == USB_EP_MODE_STREAMS) { 2335 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2336 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2337 XHCI_EPCTX_0_LSA_SET(1); 2338 2339 ring_addr += sizeof(struct xhci_trb) * 2340 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2341 } else { 2342 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2343 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2344 XHCI_EPCTX_0_LSA_SET(0); 2345 2346 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2347 } 2348 2349 switch (udev->speed) { 2350 case USB_SPEED_FULL: 2351 case USB_SPEED_LOW: 2352 /* 1ms -> 125us */ 2353 fps_shift += 3; 2354 break; 2355 default: 2356 break; 2357 } 2358 2359 switch (type) { 2360 case UE_INTERRUPT: 2361 if (fps_shift > 3) 2362 fps_shift--; 2363 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2364 break; 2365 case UE_ISOCHRONOUS: 2366 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2367 2368 switch (udev->speed) { 2369 case USB_SPEED_SUPER: 2370 if (mult > 3) 2371 mult = 3; 2372 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2373 max_packet_count /= mult; 2374 break; 2375 default: 2376 break; 2377 } 2378 break; 2379 default: 2380 break; 2381 } 2382 2383 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2384 2385 temp = 2386 XHCI_EPCTX_1_HID_SET(0) | 2387 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2388 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2389 2390 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2391 if (type != UE_ISOCHRONOUS) 2392 temp |= XHCI_EPCTX_1_CERR_SET(3); 2393 } 2394 2395 switch (type) { 2396 case UE_CONTROL: 2397 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2398 break; 2399 case UE_ISOCHRONOUS: 2400 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2401 break; 2402 case UE_BULK: 2403 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2404 break; 2405 default: 2406 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2407 break; 2408 } 2409 2410 /* check for IN direction */ 2411 if (epno & 1) 2412 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2413 2414 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2415 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2416 2417 switch (edesc->bmAttributes & UE_XFERTYPE) { 2418 case UE_INTERRUPT: 2419 case UE_ISOCHRONOUS: 2420 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2421 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2422 max_frame_size)); 2423 break; 2424 case UE_CONTROL: 2425 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2426 break; 2427 default: 2428 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2429 break; 2430 } 2431 2432 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2433 2434 #ifdef USB_DEBUG 2435 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2436 #endif 2437 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2438 2439 return (0); /* success */ 2440 } 2441 2442 static usb_error_t 2443 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2444 { 2445 struct xhci_endpoint_ext *pepext; 2446 struct usb_endpoint_ss_comp_descriptor *ecomp; 2447 usb_stream_t x; 2448 2449 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2450 xfer->endpoint->edesc); 2451 2452 ecomp = xfer->endpoint->ecomp; 2453 2454 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2455 uint64_t temp; 2456 2457 /* halt any transfers */ 2458 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2459 2460 /* compute start of TRB ring for stream "x" */ 2461 temp = pepext->physaddr + 2462 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2463 XHCI_SCTX_0_SCT_SEC_TR_RING; 2464 2465 /* make tree structure */ 2466 pepext->trb[(XHCI_MAX_TRANSFERS * 2467 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2468 2469 /* reserved fields */ 2470 pepext->trb[(XHCI_MAX_TRANSFERS * 2471 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2472 pepext->trb[(XHCI_MAX_TRANSFERS * 2473 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2474 } 2475 usb_pc_cpu_flush(pepext->page_cache); 2476 2477 return (xhci_configure_endpoint(xfer->xroot->udev, 2478 xfer->endpoint->edesc, pepext, 2479 xfer->interval, xfer->max_packet_count, 2480 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2481 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2482 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2483 } 2484 2485 static usb_error_t 2486 xhci_configure_device(struct usb_device *udev) 2487 { 2488 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2489 struct usb_page_search buf_inp; 2490 struct usb_page_cache *pcinp; 2491 struct xhci_input_dev_ctx *pinp; 2492 struct usb_device *hubdev; 2493 uint32_t temp; 2494 uint32_t route; 2495 uint32_t rh_port; 2496 uint8_t is_hub; 2497 uint8_t index; 2498 uint8_t depth; 2499 2500 index = udev->controller_slot_id; 2501 2502 DPRINTF("index=%u\n", index); 2503 2504 pcinp = &sc->sc_hw.devs[index].input_pc; 2505 2506 usbd_get_page(pcinp, 0, &buf_inp); 2507 2508 pinp = buf_inp.buffer; 2509 2510 rh_port = 0; 2511 route = 0; 2512 2513 /* figure out route string and root HUB port number */ 2514 2515 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2516 2517 if (hubdev->parent_hub == NULL) 2518 break; 2519 2520 depth = hubdev->parent_hub->depth; 2521 2522 /* 2523 * NOTE: HS/FS/LS devices and the SS root HUB can have 2524 * more than 15 ports 2525 */ 2526 2527 rh_port = hubdev->port_no; 2528 2529 if (depth == 0) 2530 break; 2531 2532 if (rh_port > 15) 2533 rh_port = 15; 2534 2535 if (depth < 6) 2536 route |= rh_port << (4 * (depth - 1)); 2537 } 2538 2539 DPRINTF("Route=0x%08x\n", route); 2540 2541 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2542 XHCI_SCTX_0_CTX_NUM_SET( 2543 sc->sc_hw.devs[index].context_num + 1); 2544 2545 switch (udev->speed) { 2546 case USB_SPEED_LOW: 2547 temp |= XHCI_SCTX_0_SPEED_SET(2); 2548 if (udev->parent_hs_hub != NULL && 2549 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2550 UDPROTO_HSHUBMTT) { 2551 DPRINTF("Device inherits MTT\n"); 2552 temp |= XHCI_SCTX_0_MTT_SET(1); 2553 } 2554 break; 2555 case USB_SPEED_HIGH: 2556 temp |= XHCI_SCTX_0_SPEED_SET(3); 2557 if (sc->sc_hw.devs[index].nports != 0 && 2558 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2559 DPRINTF("HUB supports MTT\n"); 2560 temp |= XHCI_SCTX_0_MTT_SET(1); 2561 } 2562 break; 2563 case USB_SPEED_FULL: 2564 temp |= XHCI_SCTX_0_SPEED_SET(1); 2565 if (udev->parent_hs_hub != NULL && 2566 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2567 UDPROTO_HSHUBMTT) { 2568 DPRINTF("Device inherits MTT\n"); 2569 temp |= XHCI_SCTX_0_MTT_SET(1); 2570 } 2571 break; 2572 default: 2573 temp |= XHCI_SCTX_0_SPEED_SET(4); 2574 break; 2575 } 2576 2577 is_hub = sc->sc_hw.devs[index].nports != 0 && 2578 (udev->speed == USB_SPEED_SUPER || 2579 udev->speed == USB_SPEED_HIGH); 2580 2581 if (is_hub) 2582 temp |= XHCI_SCTX_0_HUB_SET(1); 2583 2584 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2585 2586 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2587 2588 if (is_hub) { 2589 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2590 sc->sc_hw.devs[index].nports); 2591 } 2592 2593 switch (udev->speed) { 2594 case USB_SPEED_SUPER: 2595 switch (sc->sc_hw.devs[index].state) { 2596 case XHCI_ST_ADDRESSED: 2597 case XHCI_ST_CONFIGURED: 2598 /* enable power save */ 2599 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2600 break; 2601 default: 2602 /* disable power save */ 2603 break; 2604 } 2605 break; 2606 default: 2607 break; 2608 } 2609 2610 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2611 2612 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2613 2614 if (is_hub) { 2615 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2616 sc->sc_hw.devs[index].tt); 2617 } 2618 2619 hubdev = udev->parent_hs_hub; 2620 2621 /* check if we should activate the transaction translator */ 2622 switch (udev->speed) { 2623 case USB_SPEED_FULL: 2624 case USB_SPEED_LOW: 2625 if (hubdev != NULL) { 2626 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2627 hubdev->controller_slot_id); 2628 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2629 udev->hs_port_no); 2630 } 2631 break; 2632 default: 2633 break; 2634 } 2635 2636 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2637 2638 /* 2639 * These fields should be initialized to zero, according to 2640 * XHCI section 6.2.2 - slot context: 2641 */ 2642 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2643 XHCI_SCTX_3_SLOT_STATE_SET(0); 2644 2645 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2646 2647 #ifdef USB_DEBUG 2648 xhci_dump_device(sc, &pinp->ctx_slot); 2649 #endif 2650 usb_pc_cpu_flush(pcinp); 2651 2652 return (0); /* success */ 2653 } 2654 2655 static usb_error_t 2656 xhci_alloc_device_ext(struct usb_device *udev) 2657 { 2658 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2659 struct usb_page_search buf_dev; 2660 struct usb_page_search buf_ep; 2661 struct xhci_trb *trb; 2662 struct usb_page_cache *pc; 2663 struct usb_page *pg; 2664 uint64_t addr; 2665 uint8_t index; 2666 uint8_t i; 2667 2668 index = udev->controller_slot_id; 2669 2670 pc = &sc->sc_hw.devs[index].device_pc; 2671 pg = &sc->sc_hw.devs[index].device_pg; 2672 2673 /* need to initialize the page cache */ 2674 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2675 2676 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2677 (2 * sizeof(struct xhci_dev_ctx)) : 2678 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2679 goto error; 2680 2681 usbd_get_page(pc, 0, &buf_dev); 2682 2683 pc = &sc->sc_hw.devs[index].input_pc; 2684 pg = &sc->sc_hw.devs[index].input_pg; 2685 2686 /* need to initialize the page cache */ 2687 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2688 2689 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2690 (2 * sizeof(struct xhci_input_dev_ctx)) : 2691 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2692 goto error; 2693 } 2694 2695 /* initialise all endpoint LINK TRBs */ 2696 2697 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2698 2699 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2700 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2701 2702 /* need to initialize the page cache */ 2703 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2704 2705 if (usb_pc_alloc_mem(pc, pg, 2706 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2707 goto error; 2708 } 2709 2710 /* lookup endpoint TRB ring */ 2711 usbd_get_page(pc, 0, &buf_ep); 2712 2713 /* get TRB pointer */ 2714 trb = buf_ep.buffer; 2715 trb += XHCI_MAX_TRANSFERS - 1; 2716 2717 /* get TRB start address */ 2718 addr = buf_ep.physaddr; 2719 2720 /* create LINK TRB */ 2721 trb->qwTrb0 = htole64(addr); 2722 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2723 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2724 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2725 2726 usb_pc_cpu_flush(pc); 2727 } 2728 2729 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2730 2731 return (0); 2732 2733 error: 2734 xhci_free_device_ext(udev); 2735 2736 return (USB_ERR_NOMEM); 2737 } 2738 2739 static void 2740 xhci_free_device_ext(struct usb_device *udev) 2741 { 2742 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2743 uint8_t index; 2744 uint8_t i; 2745 2746 index = udev->controller_slot_id; 2747 xhci_set_slot_pointer(sc, index, 0); 2748 2749 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2750 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2751 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2752 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2753 } 2754 2755 static struct xhci_endpoint_ext * 2756 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2757 { 2758 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2759 struct xhci_endpoint_ext *pepext; 2760 struct usb_page_cache *pc; 2761 struct usb_page_search buf_ep; 2762 uint8_t epno; 2763 uint8_t index; 2764 2765 epno = edesc->bEndpointAddress; 2766 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2767 epno |= UE_DIR_IN; 2768 2769 epno = XHCI_EPNO2EPID(epno); 2770 2771 index = udev->controller_slot_id; 2772 2773 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2774 2775 usbd_get_page(pc, 0, &buf_ep); 2776 2777 pepext = &sc->sc_hw.devs[index].endp[epno]; 2778 pepext->page_cache = pc; 2779 pepext->trb = buf_ep.buffer; 2780 pepext->physaddr = buf_ep.physaddr; 2781 2782 return (pepext); 2783 } 2784 2785 static void 2786 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2787 { 2788 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2789 uint8_t epno; 2790 uint8_t index; 2791 2792 epno = xfer->endpointno; 2793 if (xfer->flags_int.control_xfr) 2794 epno |= UE_DIR_IN; 2795 2796 epno = XHCI_EPNO2EPID(epno); 2797 index = xfer->xroot->udev->controller_slot_id; 2798 2799 if (xfer->xroot->udev->flags.self_suspended == 0) { 2800 XWRITE4(sc, door, XHCI_DOORBELL(index), 2801 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2802 } 2803 } 2804 2805 static void 2806 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2807 { 2808 struct xhci_endpoint_ext *pepext; 2809 2810 if (xfer->flags_int.bandwidth_reclaimed) { 2811 xfer->flags_int.bandwidth_reclaimed = 0; 2812 2813 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2814 xfer->endpoint->edesc); 2815 2816 pepext->trb_used[xfer->stream_id]--; 2817 2818 pepext->xfer[xfer->qh_pos] = NULL; 2819 2820 if (error && pepext->trb_running != 0) { 2821 pepext->trb_halted = 1; 2822 pepext->trb_running = 0; 2823 } 2824 } 2825 } 2826 2827 static usb_error_t 2828 xhci_transfer_insert(struct usb_xfer *xfer) 2829 { 2830 struct xhci_td *td_first; 2831 struct xhci_td *td_last; 2832 struct xhci_trb *trb_link; 2833 struct xhci_endpoint_ext *pepext; 2834 uint64_t addr; 2835 usb_stream_t id; 2836 uint8_t i; 2837 uint8_t inext; 2838 uint8_t trb_limit; 2839 2840 DPRINTFN(8, "\n"); 2841 2842 id = xfer->stream_id; 2843 2844 /* check if already inserted */ 2845 if (xfer->flags_int.bandwidth_reclaimed) { 2846 DPRINTFN(8, "Already in schedule\n"); 2847 return (0); 2848 } 2849 2850 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2851 xfer->endpoint->edesc); 2852 2853 td_first = xfer->td_transfer_first; 2854 td_last = xfer->td_transfer_last; 2855 addr = pepext->physaddr; 2856 2857 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2858 case UE_CONTROL: 2859 case UE_INTERRUPT: 2860 /* single buffered */ 2861 trb_limit = 1; 2862 break; 2863 default: 2864 /* multi buffered */ 2865 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2866 break; 2867 } 2868 2869 if (pepext->trb_used[id] >= trb_limit) { 2870 DPRINTFN(8, "Too many TDs queued.\n"); 2871 return (USB_ERR_NOMEM); 2872 } 2873 2874 /* check for stopped condition, after putting transfer on interrupt queue */ 2875 if (pepext->trb_running == 0) { 2876 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2877 2878 DPRINTFN(8, "Not running\n"); 2879 2880 /* start configuration */ 2881 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2882 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2883 return (0); 2884 } 2885 2886 pepext->trb_used[id]++; 2887 2888 /* get current TRB index */ 2889 i = pepext->trb_index[id]; 2890 2891 /* get next TRB index */ 2892 inext = (i + 1); 2893 2894 /* the last entry of the ring is a hardcoded link TRB */ 2895 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2896 inext = 0; 2897 2898 /* store next TRB index, before stream ID offset is added */ 2899 pepext->trb_index[id] = inext; 2900 2901 /* offset for stream */ 2902 i += id * XHCI_MAX_TRANSFERS; 2903 inext += id * XHCI_MAX_TRANSFERS; 2904 2905 /* compute terminating return address */ 2906 addr += (inext * sizeof(struct xhci_trb)); 2907 2908 /* compute link TRB pointer */ 2909 trb_link = td_last->td_trb + td_last->ntrb; 2910 2911 /* update next pointer of last link TRB */ 2912 trb_link->qwTrb0 = htole64(addr); 2913 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2914 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2915 XHCI_TRB_3_CYCLE_BIT | 2916 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2917 2918 #ifdef USB_DEBUG 2919 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2920 #endif 2921 usb_pc_cpu_flush(td_last->page_cache); 2922 2923 /* write ahead chain end marker */ 2924 2925 pepext->trb[inext].qwTrb0 = 0; 2926 pepext->trb[inext].dwTrb2 = 0; 2927 pepext->trb[inext].dwTrb3 = 0; 2928 2929 /* update next pointer of link TRB */ 2930 2931 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2932 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2933 2934 #ifdef USB_DEBUG 2935 xhci_dump_trb(&pepext->trb[i]); 2936 #endif 2937 usb_pc_cpu_flush(pepext->page_cache); 2938 2939 /* toggle cycle bit which activates the transfer chain */ 2940 2941 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2942 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2943 2944 usb_pc_cpu_flush(pepext->page_cache); 2945 2946 DPRINTF("qh_pos = %u\n", i); 2947 2948 pepext->xfer[i] = xfer; 2949 2950 xfer->qh_pos = i; 2951 2952 xfer->flags_int.bandwidth_reclaimed = 1; 2953 2954 xhci_endpoint_doorbell(xfer); 2955 2956 return (0); 2957 } 2958 2959 static void 2960 xhci_root_intr(struct xhci_softc *sc) 2961 { 2962 uint16_t i; 2963 2964 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2965 2966 /* clear any old interrupt data */ 2967 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2968 2969 for (i = 1; i <= sc->sc_noport; i++) { 2970 /* pick out CHANGE bits from the status register */ 2971 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2972 XHCI_PS_CSC | XHCI_PS_PEC | 2973 XHCI_PS_OCC | XHCI_PS_WRC | 2974 XHCI_PS_PRC | XHCI_PS_PLC | 2975 XHCI_PS_CEC)) { 2976 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2977 DPRINTF("port %d changed\n", i); 2978 } 2979 } 2980 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2981 sizeof(sc->sc_hub_idata)); 2982 } 2983 2984 /*------------------------------------------------------------------------* 2985 * xhci_device_done - XHCI done handler 2986 * 2987 * NOTE: This function can be called two times in a row on 2988 * the same USB transfer. From close and from interrupt. 2989 *------------------------------------------------------------------------*/ 2990 static void 2991 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2992 { 2993 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2994 xfer, xfer->endpoint, error); 2995 2996 /* remove transfer from HW queue */ 2997 xhci_transfer_remove(xfer, error); 2998 2999 /* dequeue transfer and start next transfer */ 3000 usbd_transfer_done(xfer, error); 3001 } 3002 3003 /*------------------------------------------------------------------------* 3004 * XHCI data transfer support (generic type) 3005 *------------------------------------------------------------------------*/ 3006 static void 3007 xhci_device_generic_open(struct usb_xfer *xfer) 3008 { 3009 if (xfer->flags_int.isochronous_xfr) { 3010 switch (xfer->xroot->udev->speed) { 3011 case USB_SPEED_FULL: 3012 break; 3013 default: 3014 usb_hs_bandwidth_alloc(xfer); 3015 break; 3016 } 3017 } 3018 } 3019 3020 static void 3021 xhci_device_generic_close(struct usb_xfer *xfer) 3022 { 3023 DPRINTF("\n"); 3024 3025 xhci_device_done(xfer, USB_ERR_CANCELLED); 3026 3027 if (xfer->flags_int.isochronous_xfr) { 3028 switch (xfer->xroot->udev->speed) { 3029 case USB_SPEED_FULL: 3030 break; 3031 default: 3032 usb_hs_bandwidth_free(xfer); 3033 break; 3034 } 3035 } 3036 } 3037 3038 static void 3039 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3040 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3041 { 3042 struct usb_xfer *xfer; 3043 3044 /* check if there is a current transfer */ 3045 xfer = ep->endpoint_q[stream_id].curr; 3046 if (xfer == NULL) 3047 return; 3048 3049 /* 3050 * Check if the current transfer is started and then pickup 3051 * the next one, if any. Else wait for next start event due to 3052 * block on failure feature. 3053 */ 3054 if (!xfer->flags_int.bandwidth_reclaimed) 3055 return; 3056 3057 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3058 if (xfer == NULL) { 3059 /* 3060 * In case of enter we have to consider that the 3061 * transfer is queued by the USB core after the enter 3062 * method is called. 3063 */ 3064 xfer = enter_xfer; 3065 3066 if (xfer == NULL) 3067 return; 3068 } 3069 3070 /* try to multi buffer */ 3071 xhci_transfer_insert(xfer); 3072 } 3073 3074 static void 3075 xhci_device_generic_enter(struct usb_xfer *xfer) 3076 { 3077 DPRINTF("\n"); 3078 3079 /* setup TD's and QH */ 3080 xhci_setup_generic_chain(xfer); 3081 3082 xhci_device_generic_multi_enter(xfer->endpoint, 3083 xfer->stream_id, xfer); 3084 } 3085 3086 static void 3087 xhci_device_generic_start(struct usb_xfer *xfer) 3088 { 3089 DPRINTF("\n"); 3090 3091 /* try to insert xfer on HW queue */ 3092 xhci_transfer_insert(xfer); 3093 3094 /* try to multi buffer */ 3095 xhci_device_generic_multi_enter(xfer->endpoint, 3096 xfer->stream_id, NULL); 3097 3098 /* add transfer last on interrupt queue */ 3099 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3100 3101 /* start timeout, if any */ 3102 if (xfer->timeout != 0) 3103 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3104 } 3105 3106 static const struct usb_pipe_methods xhci_device_generic_methods = 3107 { 3108 .open = xhci_device_generic_open, 3109 .close = xhci_device_generic_close, 3110 .enter = xhci_device_generic_enter, 3111 .start = xhci_device_generic_start, 3112 }; 3113 3114 /*------------------------------------------------------------------------* 3115 * xhci root HUB support 3116 *------------------------------------------------------------------------* 3117 * Simulate a hardware HUB by handling all the necessary requests. 3118 *------------------------------------------------------------------------*/ 3119 3120 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3121 3122 static const 3123 struct usb_device_descriptor xhci_devd = 3124 { 3125 .bLength = sizeof(xhci_devd), 3126 .bDescriptorType = UDESC_DEVICE, /* type */ 3127 HSETW(.bcdUSB, 0x0300), /* USB version */ 3128 .bDeviceClass = UDCLASS_HUB, /* class */ 3129 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3130 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3131 .bMaxPacketSize = 9, /* max packet size */ 3132 HSETW(.idVendor, 0x0000), /* vendor */ 3133 HSETW(.idProduct, 0x0000), /* product */ 3134 HSETW(.bcdDevice, 0x0100), /* device version */ 3135 .iManufacturer = 1, 3136 .iProduct = 2, 3137 .iSerialNumber = 0, 3138 .bNumConfigurations = 1, /* # of configurations */ 3139 }; 3140 3141 static const 3142 struct xhci_bos_desc xhci_bosd = { 3143 .bosd = { 3144 .bLength = sizeof(xhci_bosd.bosd), 3145 .bDescriptorType = UDESC_BOS, 3146 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3147 .bNumDeviceCaps = 3, 3148 }, 3149 .usb2extd = { 3150 .bLength = sizeof(xhci_bosd.usb2extd), 3151 .bDescriptorType = 1, 3152 .bDevCapabilityType = 2, 3153 .bmAttributes[0] = 2, 3154 }, 3155 .usbdcd = { 3156 .bLength = sizeof(xhci_bosd.usbdcd), 3157 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3158 .bDevCapabilityType = 3, 3159 .bmAttributes = 0, /* XXX */ 3160 HSETW(.wSpeedsSupported, 0x000C), 3161 .bFunctionalitySupport = 8, 3162 .bU1DevExitLat = 255, /* dummy - not used */ 3163 .wU2DevExitLat = { 0x00, 0x08 }, 3164 }, 3165 .cidd = { 3166 .bLength = sizeof(xhci_bosd.cidd), 3167 .bDescriptorType = 1, 3168 .bDevCapabilityType = 4, 3169 .bReserved = 0, 3170 .bContainerID = 0, /* XXX */ 3171 }, 3172 }; 3173 3174 static const 3175 struct xhci_config_desc xhci_confd = { 3176 .confd = { 3177 .bLength = sizeof(xhci_confd.confd), 3178 .bDescriptorType = UDESC_CONFIG, 3179 .wTotalLength[0] = sizeof(xhci_confd), 3180 .bNumInterface = 1, 3181 .bConfigurationValue = 1, 3182 .iConfiguration = 0, 3183 .bmAttributes = UC_SELF_POWERED, 3184 .bMaxPower = 0 /* max power */ 3185 }, 3186 .ifcd = { 3187 .bLength = sizeof(xhci_confd.ifcd), 3188 .bDescriptorType = UDESC_INTERFACE, 3189 .bNumEndpoints = 1, 3190 .bInterfaceClass = UICLASS_HUB, 3191 .bInterfaceSubClass = UISUBCLASS_HUB, 3192 .bInterfaceProtocol = 0, 3193 }, 3194 .endpd = { 3195 .bLength = sizeof(xhci_confd.endpd), 3196 .bDescriptorType = UDESC_ENDPOINT, 3197 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3198 .bmAttributes = UE_INTERRUPT, 3199 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3200 .bInterval = 255, 3201 }, 3202 .endpcd = { 3203 .bLength = sizeof(xhci_confd.endpcd), 3204 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3205 .bMaxBurst = 0, 3206 .bmAttributes = 0, 3207 }, 3208 }; 3209 3210 static const 3211 struct usb_hub_ss_descriptor xhci_hubd = { 3212 .bLength = sizeof(xhci_hubd), 3213 .bDescriptorType = UDESC_SS_HUB, 3214 }; 3215 3216 static usb_error_t 3217 xhci_roothub_exec(struct usb_device *udev, 3218 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3219 { 3220 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3221 const char *str_ptr; 3222 const void *ptr; 3223 uint32_t port; 3224 uint32_t v; 3225 uint16_t len; 3226 uint16_t i; 3227 uint16_t value; 3228 uint16_t index; 3229 uint8_t j; 3230 usb_error_t err; 3231 3232 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3233 3234 /* buffer reset */ 3235 ptr = (const void *)&sc->sc_hub_desc; 3236 len = 0; 3237 err = 0; 3238 3239 value = UGETW(req->wValue); 3240 index = UGETW(req->wIndex); 3241 3242 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3243 "wValue=0x%04x wIndex=0x%04x\n", 3244 req->bmRequestType, req->bRequest, 3245 UGETW(req->wLength), value, index); 3246 3247 #define C(x,y) ((x) | ((y) << 8)) 3248 switch (C(req->bRequest, req->bmRequestType)) { 3249 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3250 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3251 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3252 /* 3253 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3254 * for the integrated root hub. 3255 */ 3256 break; 3257 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3258 len = 1; 3259 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3260 break; 3261 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3262 switch (value >> 8) { 3263 case UDESC_DEVICE: 3264 if ((value & 0xff) != 0) { 3265 err = USB_ERR_IOERROR; 3266 goto done; 3267 } 3268 len = sizeof(xhci_devd); 3269 ptr = (const void *)&xhci_devd; 3270 break; 3271 3272 case UDESC_BOS: 3273 if ((value & 0xff) != 0) { 3274 err = USB_ERR_IOERROR; 3275 goto done; 3276 } 3277 len = sizeof(xhci_bosd); 3278 ptr = (const void *)&xhci_bosd; 3279 break; 3280 3281 case UDESC_CONFIG: 3282 if ((value & 0xff) != 0) { 3283 err = USB_ERR_IOERROR; 3284 goto done; 3285 } 3286 len = sizeof(xhci_confd); 3287 ptr = (const void *)&xhci_confd; 3288 break; 3289 3290 case UDESC_STRING: 3291 switch (value & 0xff) { 3292 case 0: /* Language table */ 3293 str_ptr = "\001"; 3294 break; 3295 3296 case 1: /* Vendor */ 3297 str_ptr = sc->sc_vendor; 3298 break; 3299 3300 case 2: /* Product */ 3301 str_ptr = "XHCI root HUB"; 3302 break; 3303 3304 default: 3305 str_ptr = ""; 3306 break; 3307 } 3308 3309 len = usb_make_str_desc( 3310 sc->sc_hub_desc.temp, 3311 sizeof(sc->sc_hub_desc.temp), 3312 str_ptr); 3313 break; 3314 3315 default: 3316 err = USB_ERR_IOERROR; 3317 goto done; 3318 } 3319 break; 3320 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3321 len = 1; 3322 sc->sc_hub_desc.temp[0] = 0; 3323 break; 3324 case C(UR_GET_STATUS, UT_READ_DEVICE): 3325 len = 2; 3326 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3327 break; 3328 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3329 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3330 len = 2; 3331 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3332 break; 3333 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3334 if (value >= XHCI_MAX_DEVICES) { 3335 err = USB_ERR_IOERROR; 3336 goto done; 3337 } 3338 break; 3339 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3340 if (value != 0 && value != 1) { 3341 err = USB_ERR_IOERROR; 3342 goto done; 3343 } 3344 sc->sc_conf = value; 3345 break; 3346 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3347 break; 3348 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3349 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3350 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3351 err = USB_ERR_IOERROR; 3352 goto done; 3353 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3354 break; 3355 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3356 break; 3357 /* Hub requests */ 3358 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3359 break; 3360 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3361 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3362 3363 if ((index < 1) || 3364 (index > sc->sc_noport)) { 3365 err = USB_ERR_IOERROR; 3366 goto done; 3367 } 3368 port = XHCI_PORTSC(index); 3369 3370 v = XREAD4(sc, oper, port); 3371 i = XHCI_PS_PLS_GET(v); 3372 v &= ~XHCI_PS_CLEAR; 3373 3374 switch (value) { 3375 case UHF_C_BH_PORT_RESET: 3376 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3377 break; 3378 case UHF_C_PORT_CONFIG_ERROR: 3379 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3380 break; 3381 case UHF_C_PORT_SUSPEND: 3382 case UHF_C_PORT_LINK_STATE: 3383 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3384 break; 3385 case UHF_C_PORT_CONNECTION: 3386 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3387 break; 3388 case UHF_C_PORT_ENABLE: 3389 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3390 break; 3391 case UHF_C_PORT_OVER_CURRENT: 3392 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3393 break; 3394 case UHF_C_PORT_RESET: 3395 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3396 break; 3397 case UHF_PORT_ENABLE: 3398 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3399 break; 3400 case UHF_PORT_POWER: 3401 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3402 break; 3403 case UHF_PORT_INDICATOR: 3404 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3405 break; 3406 case UHF_PORT_SUSPEND: 3407 3408 /* U3 -> U15 */ 3409 if (i == 3) { 3410 XWRITE4(sc, oper, port, v | 3411 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3412 } 3413 3414 /* wait 20ms for resume sequence to complete */ 3415 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3416 3417 /* U0 */ 3418 XWRITE4(sc, oper, port, v | 3419 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3420 break; 3421 default: 3422 err = USB_ERR_IOERROR; 3423 goto done; 3424 } 3425 break; 3426 3427 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3428 if ((value & 0xff) != 0) { 3429 err = USB_ERR_IOERROR; 3430 goto done; 3431 } 3432 3433 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3434 3435 sc->sc_hub_desc.hubd = xhci_hubd; 3436 3437 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3438 3439 if (XHCI_HCS0_PPC(v)) 3440 i = UHD_PWR_INDIVIDUAL; 3441 else 3442 i = UHD_PWR_GANGED; 3443 3444 if (XHCI_HCS0_PIND(v)) 3445 i |= UHD_PORT_IND; 3446 3447 i |= UHD_OC_INDIVIDUAL; 3448 3449 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3450 3451 /* see XHCI section 5.4.9: */ 3452 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3453 3454 for (j = 1; j <= sc->sc_noport; j++) { 3455 3456 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3457 if (v & XHCI_PS_DR) { 3458 sc->sc_hub_desc.hubd. 3459 DeviceRemovable[j / 8] |= 1U << (j % 8); 3460 } 3461 } 3462 len = sc->sc_hub_desc.hubd.bLength; 3463 break; 3464 3465 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3466 len = 16; 3467 memset(sc->sc_hub_desc.temp, 0, 16); 3468 break; 3469 3470 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3471 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3472 3473 if ((index < 1) || 3474 (index > sc->sc_noport)) { 3475 err = USB_ERR_IOERROR; 3476 goto done; 3477 } 3478 3479 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3480 3481 DPRINTFN(9, "port status=0x%08x\n", v); 3482 3483 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3484 3485 switch (XHCI_PS_SPEED_GET(v)) { 3486 case 3: 3487 i |= UPS_HIGH_SPEED; 3488 break; 3489 case 2: 3490 i |= UPS_LOW_SPEED; 3491 break; 3492 case 1: 3493 /* FULL speed */ 3494 break; 3495 default: 3496 i |= UPS_OTHER_SPEED; 3497 break; 3498 } 3499 3500 if (v & XHCI_PS_CCS) 3501 i |= UPS_CURRENT_CONNECT_STATUS; 3502 if (v & XHCI_PS_PED) 3503 i |= UPS_PORT_ENABLED; 3504 if (v & XHCI_PS_OCA) 3505 i |= UPS_OVERCURRENT_INDICATOR; 3506 if (v & XHCI_PS_PR) 3507 i |= UPS_RESET; 3508 if (v & XHCI_PS_PP) { 3509 /* 3510 * The USB 3.0 RH is using the 3511 * USB 2.0's power bit 3512 */ 3513 i |= UPS_PORT_POWER; 3514 } 3515 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3516 3517 i = 0; 3518 if (v & XHCI_PS_CSC) 3519 i |= UPS_C_CONNECT_STATUS; 3520 if (v & XHCI_PS_PEC) 3521 i |= UPS_C_PORT_ENABLED; 3522 if (v & XHCI_PS_OCC) 3523 i |= UPS_C_OVERCURRENT_INDICATOR; 3524 if (v & XHCI_PS_WRC) 3525 i |= UPS_C_BH_PORT_RESET; 3526 if (v & XHCI_PS_PRC) 3527 i |= UPS_C_PORT_RESET; 3528 if (v & XHCI_PS_PLC) 3529 i |= UPS_C_PORT_LINK_STATE; 3530 if (v & XHCI_PS_CEC) 3531 i |= UPS_C_PORT_CONFIG_ERROR; 3532 3533 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3534 len = sizeof(sc->sc_hub_desc.ps); 3535 break; 3536 3537 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3538 err = USB_ERR_IOERROR; 3539 goto done; 3540 3541 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3542 break; 3543 3544 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3545 3546 i = index >> 8; 3547 index &= 0x00FF; 3548 3549 if ((index < 1) || 3550 (index > sc->sc_noport)) { 3551 err = USB_ERR_IOERROR; 3552 goto done; 3553 } 3554 3555 port = XHCI_PORTSC(index); 3556 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3557 3558 switch (value) { 3559 case UHF_PORT_U1_TIMEOUT: 3560 if (XHCI_PS_SPEED_GET(v) != 4) { 3561 err = USB_ERR_IOERROR; 3562 goto done; 3563 } 3564 port = XHCI_PORTPMSC(index); 3565 v = XREAD4(sc, oper, port); 3566 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3567 v |= XHCI_PM3_U1TO_SET(i); 3568 XWRITE4(sc, oper, port, v); 3569 break; 3570 case UHF_PORT_U2_TIMEOUT: 3571 if (XHCI_PS_SPEED_GET(v) != 4) { 3572 err = USB_ERR_IOERROR; 3573 goto done; 3574 } 3575 port = XHCI_PORTPMSC(index); 3576 v = XREAD4(sc, oper, port); 3577 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3578 v |= XHCI_PM3_U2TO_SET(i); 3579 XWRITE4(sc, oper, port, v); 3580 break; 3581 case UHF_BH_PORT_RESET: 3582 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3583 break; 3584 case UHF_PORT_LINK_STATE: 3585 XWRITE4(sc, oper, port, v | 3586 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3587 /* 4ms settle time */ 3588 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3589 break; 3590 case UHF_PORT_ENABLE: 3591 DPRINTFN(3, "set port enable %d\n", index); 3592 break; 3593 case UHF_PORT_SUSPEND: 3594 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3595 j = XHCI_PS_SPEED_GET(v); 3596 if ((j < 1) || (j > 3)) { 3597 /* non-supported speed */ 3598 err = USB_ERR_IOERROR; 3599 goto done; 3600 } 3601 XWRITE4(sc, oper, port, v | 3602 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3603 break; 3604 case UHF_PORT_RESET: 3605 DPRINTFN(6, "reset port %d\n", index); 3606 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3607 break; 3608 case UHF_PORT_POWER: 3609 DPRINTFN(3, "set port power %d\n", index); 3610 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3611 break; 3612 case UHF_PORT_TEST: 3613 DPRINTFN(3, "set port test %d\n", index); 3614 break; 3615 case UHF_PORT_INDICATOR: 3616 DPRINTFN(3, "set port indicator %d\n", index); 3617 3618 v &= ~XHCI_PS_PIC_SET(3); 3619 v |= XHCI_PS_PIC_SET(1); 3620 3621 XWRITE4(sc, oper, port, v); 3622 break; 3623 default: 3624 err = USB_ERR_IOERROR; 3625 goto done; 3626 } 3627 break; 3628 3629 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3630 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3631 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3632 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3633 break; 3634 default: 3635 err = USB_ERR_IOERROR; 3636 goto done; 3637 } 3638 done: 3639 *plength = len; 3640 *pptr = ptr; 3641 return (err); 3642 } 3643 3644 static void 3645 xhci_xfer_setup(struct usb_setup_params *parm) 3646 { 3647 struct usb_page_search page_info; 3648 struct usb_page_cache *pc; 3649 struct xhci_softc *sc; 3650 struct usb_xfer *xfer; 3651 void *last_obj; 3652 uint32_t ntd; 3653 uint32_t n; 3654 3655 sc = XHCI_BUS2SC(parm->udev->bus); 3656 xfer = parm->curr_xfer; 3657 3658 /* 3659 * The proof for the "ntd" formula is illustrated like this: 3660 * 3661 * +------------------------------------+ 3662 * | | 3663 * | |remainder -> | 3664 * | +-----+---+ | 3665 * | | xxx | x | frm 0 | 3666 * | +-----+---++ | 3667 * | | xxx | xx | frm 1 | 3668 * | +-----+----+ | 3669 * | ... | 3670 * +------------------------------------+ 3671 * 3672 * "xxx" means a completely full USB transfer descriptor 3673 * 3674 * "x" and "xx" means a short USB packet 3675 * 3676 * For the remainder of an USB transfer modulo 3677 * "max_data_length" we need two USB transfer descriptors. 3678 * One to transfer the remaining data and one to finalise with 3679 * a zero length packet in case the "force_short_xfer" flag is 3680 * set. We only need two USB transfer descriptors in the case 3681 * where the transfer length of the first one is a factor of 3682 * "max_frame_size". The rest of the needed USB transfer 3683 * descriptors is given by the buffer size divided by the 3684 * maximum data payload. 3685 */ 3686 parm->hc_max_packet_size = 0x400; 3687 parm->hc_max_packet_count = 16 * 3; 3688 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3689 3690 xfer->flags_int.bdma_enable = 1; 3691 3692 usbd_transfer_setup_sub(parm); 3693 3694 if (xfer->flags_int.isochronous_xfr) { 3695 ntd = ((1 * xfer->nframes) 3696 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3697 } else if (xfer->flags_int.control_xfr) { 3698 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3699 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3700 } else { 3701 ntd = ((2 * xfer->nframes) 3702 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3703 } 3704 3705 alloc_dma_set: 3706 3707 if (parm->err) 3708 return; 3709 3710 /* 3711 * Allocate queue heads and transfer descriptors 3712 */ 3713 last_obj = NULL; 3714 3715 if (usbd_transfer_setup_sub_malloc( 3716 parm, &pc, sizeof(struct xhci_td), 3717 XHCI_TD_ALIGN, ntd)) { 3718 parm->err = USB_ERR_NOMEM; 3719 return; 3720 } 3721 if (parm->buf) { 3722 for (n = 0; n != ntd; n++) { 3723 struct xhci_td *td; 3724 3725 usbd_get_page(pc + n, 0, &page_info); 3726 3727 td = page_info.buffer; 3728 3729 /* init TD */ 3730 td->td_self = page_info.physaddr; 3731 td->obj_next = last_obj; 3732 td->page_cache = pc + n; 3733 3734 last_obj = td; 3735 3736 usb_pc_cpu_flush(pc + n); 3737 } 3738 } 3739 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3740 3741 if (!xfer->flags_int.curr_dma_set) { 3742 xfer->flags_int.curr_dma_set = 1; 3743 goto alloc_dma_set; 3744 } 3745 } 3746 3747 static usb_error_t 3748 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3749 { 3750 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3751 struct usb_page_search buf_inp; 3752 struct usb_device *udev; 3753 struct xhci_endpoint_ext *pepext; 3754 struct usb_endpoint_descriptor *edesc; 3755 struct usb_page_cache *pcinp; 3756 usb_error_t err; 3757 usb_stream_t stream_id; 3758 uint8_t index; 3759 uint8_t epno; 3760 3761 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3762 xfer->endpoint->edesc); 3763 3764 udev = xfer->xroot->udev; 3765 index = udev->controller_slot_id; 3766 3767 pcinp = &sc->sc_hw.devs[index].input_pc; 3768 3769 usbd_get_page(pcinp, 0, &buf_inp); 3770 3771 edesc = xfer->endpoint->edesc; 3772 3773 epno = edesc->bEndpointAddress; 3774 stream_id = xfer->stream_id; 3775 3776 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3777 epno |= UE_DIR_IN; 3778 3779 epno = XHCI_EPNO2EPID(epno); 3780 3781 if (epno == 0) 3782 return (USB_ERR_NO_PIPE); /* invalid */ 3783 3784 XHCI_CMD_LOCK(sc); 3785 3786 /* configure endpoint */ 3787 3788 err = xhci_configure_endpoint_by_xfer(xfer); 3789 3790 if (err != 0) { 3791 XHCI_CMD_UNLOCK(sc); 3792 return (err); 3793 } 3794 3795 /* 3796 * Get the endpoint into the stopped state according to the 3797 * endpoint context state diagram in the XHCI specification: 3798 */ 3799 3800 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3801 3802 if (err != 0) 3803 DPRINTF("Could not stop endpoint %u\n", epno); 3804 3805 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3806 3807 if (err != 0) 3808 DPRINTF("Could not reset endpoint %u\n", epno); 3809 3810 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3811 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3812 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3813 stream_id, epno, index); 3814 3815 if (err != 0) 3816 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3817 3818 /* 3819 * Get the endpoint into the running state according to the 3820 * endpoint context state diagram in the XHCI specification: 3821 */ 3822 3823 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3824 3825 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3826 3827 if (err != 0) 3828 DPRINTF("Could not configure endpoint %u\n", epno); 3829 3830 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3831 3832 if (err != 0) 3833 DPRINTF("Could not configure endpoint %u\n", epno); 3834 3835 XHCI_CMD_UNLOCK(sc); 3836 3837 return (0); 3838 } 3839 3840 static void 3841 xhci_xfer_unsetup(struct usb_xfer *xfer) 3842 { 3843 return; 3844 } 3845 3846 static void 3847 xhci_start_dma_delay(struct usb_xfer *xfer) 3848 { 3849 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3850 3851 /* put transfer on interrupt queue (again) */ 3852 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3853 3854 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3855 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3856 } 3857 3858 static void 3859 xhci_configure_msg(struct usb_proc_msg *pm) 3860 { 3861 struct xhci_softc *sc; 3862 struct xhci_endpoint_ext *pepext; 3863 struct usb_xfer *xfer; 3864 3865 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3866 3867 restart: 3868 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3869 3870 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3871 xfer->endpoint->edesc); 3872 3873 if ((pepext->trb_halted != 0) || 3874 (pepext->trb_running == 0)) { 3875 3876 uint16_t i; 3877 3878 /* clear halted and running */ 3879 pepext->trb_halted = 0; 3880 pepext->trb_running = 0; 3881 3882 /* nuke remaining buffered transfers */ 3883 3884 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3885 XHCI_MAX_STREAMS); i++) { 3886 /* 3887 * NOTE: We need to use the timeout 3888 * error code here else existing 3889 * isochronous clients can get 3890 * confused: 3891 */ 3892 if (pepext->xfer[i] != NULL) { 3893 xhci_device_done(pepext->xfer[i], 3894 USB_ERR_TIMEOUT); 3895 } 3896 } 3897 3898 /* 3899 * NOTE: The USB transfer cannot vanish in 3900 * this state! 3901 */ 3902 3903 USB_BUS_UNLOCK(&sc->sc_bus); 3904 3905 xhci_configure_reset_endpoint(xfer); 3906 3907 USB_BUS_LOCK(&sc->sc_bus); 3908 3909 /* check if halted is still cleared */ 3910 if (pepext->trb_halted == 0) { 3911 pepext->trb_running = 1; 3912 memset(pepext->trb_index, 0, 3913 sizeof(pepext->trb_index)); 3914 } 3915 goto restart; 3916 } 3917 3918 if (xfer->flags_int.did_dma_delay) { 3919 3920 /* remove transfer from interrupt queue (again) */ 3921 usbd_transfer_dequeue(xfer); 3922 3923 /* we are finally done */ 3924 usb_dma_delay_done_cb(xfer); 3925 3926 /* queue changed - restart */ 3927 goto restart; 3928 } 3929 } 3930 3931 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3932 3933 /* try to insert xfer on HW queue */ 3934 xhci_transfer_insert(xfer); 3935 3936 /* try to multi buffer */ 3937 xhci_device_generic_multi_enter(xfer->endpoint, 3938 xfer->stream_id, NULL); 3939 } 3940 } 3941 3942 static void 3943 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3944 struct usb_endpoint *ep) 3945 { 3946 struct xhci_endpoint_ext *pepext; 3947 3948 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3949 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3950 3951 if (udev->parent_hub == NULL) { 3952 /* root HUB has special endpoint handling */ 3953 return; 3954 } 3955 3956 ep->methods = &xhci_device_generic_methods; 3957 3958 pepext = xhci_get_endpoint_ext(udev, edesc); 3959 3960 USB_BUS_LOCK(udev->bus); 3961 pepext->trb_halted = 1; 3962 pepext->trb_running = 0; 3963 USB_BUS_UNLOCK(udev->bus); 3964 } 3965 3966 static void 3967 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3968 { 3969 3970 } 3971 3972 static void 3973 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3974 { 3975 struct xhci_endpoint_ext *pepext; 3976 3977 DPRINTF("\n"); 3978 3979 if (udev->flags.usb_mode != USB_MODE_HOST) { 3980 /* not supported */ 3981 return; 3982 } 3983 if (udev->parent_hub == NULL) { 3984 /* root HUB has special endpoint handling */ 3985 return; 3986 } 3987 3988 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3989 3990 USB_BUS_LOCK(udev->bus); 3991 pepext->trb_halted = 1; 3992 pepext->trb_running = 0; 3993 USB_BUS_UNLOCK(udev->bus); 3994 } 3995 3996 static usb_error_t 3997 xhci_device_init(struct usb_device *udev) 3998 { 3999 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4000 usb_error_t err; 4001 uint8_t temp; 4002 4003 /* no init for root HUB */ 4004 if (udev->parent_hub == NULL) 4005 return (0); 4006 4007 XHCI_CMD_LOCK(sc); 4008 4009 /* set invalid default */ 4010 4011 udev->controller_slot_id = sc->sc_noslot + 1; 4012 4013 /* try to get a new slot ID from the XHCI */ 4014 4015 err = xhci_cmd_enable_slot(sc, &temp); 4016 4017 if (err) { 4018 XHCI_CMD_UNLOCK(sc); 4019 return (err); 4020 } 4021 4022 if (temp > sc->sc_noslot) { 4023 XHCI_CMD_UNLOCK(sc); 4024 return (USB_ERR_BAD_ADDRESS); 4025 } 4026 4027 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4028 DPRINTF("slot %u already allocated.\n", temp); 4029 XHCI_CMD_UNLOCK(sc); 4030 return (USB_ERR_BAD_ADDRESS); 4031 } 4032 4033 /* store slot ID for later reference */ 4034 4035 udev->controller_slot_id = temp; 4036 4037 /* reset data structure */ 4038 4039 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4040 4041 /* set mark slot allocated */ 4042 4043 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4044 4045 err = xhci_alloc_device_ext(udev); 4046 4047 XHCI_CMD_UNLOCK(sc); 4048 4049 /* get device into default state */ 4050 4051 if (err == 0) 4052 err = xhci_set_address(udev, NULL, 0); 4053 4054 return (err); 4055 } 4056 4057 static void 4058 xhci_device_uninit(struct usb_device *udev) 4059 { 4060 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4061 uint8_t index; 4062 4063 /* no init for root HUB */ 4064 if (udev->parent_hub == NULL) 4065 return; 4066 4067 XHCI_CMD_LOCK(sc); 4068 4069 index = udev->controller_slot_id; 4070 4071 if (index <= sc->sc_noslot) { 4072 xhci_cmd_disable_slot(sc, index); 4073 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4074 4075 /* free device extension */ 4076 xhci_free_device_ext(udev); 4077 } 4078 4079 XHCI_CMD_UNLOCK(sc); 4080 } 4081 4082 static void 4083 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4084 { 4085 /* 4086 * Wait until the hardware has finished any possible use of 4087 * the transfer descriptor(s) 4088 */ 4089 *pus = 2048; /* microseconds */ 4090 } 4091 4092 static void 4093 xhci_device_resume(struct usb_device *udev) 4094 { 4095 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4096 uint8_t index; 4097 uint8_t n; 4098 uint8_t p; 4099 4100 DPRINTF("\n"); 4101 4102 /* check for root HUB */ 4103 if (udev->parent_hub == NULL) 4104 return; 4105 4106 index = udev->controller_slot_id; 4107 4108 XHCI_CMD_LOCK(sc); 4109 4110 /* blindly resume all endpoints */ 4111 4112 USB_BUS_LOCK(udev->bus); 4113 4114 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4115 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4116 XWRITE4(sc, door, XHCI_DOORBELL(index), 4117 n | XHCI_DB_SID_SET(p)); 4118 } 4119 } 4120 4121 USB_BUS_UNLOCK(udev->bus); 4122 4123 XHCI_CMD_UNLOCK(sc); 4124 } 4125 4126 static void 4127 xhci_device_suspend(struct usb_device *udev) 4128 { 4129 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4130 uint8_t index; 4131 uint8_t n; 4132 usb_error_t err; 4133 4134 DPRINTF("\n"); 4135 4136 /* check for root HUB */ 4137 if (udev->parent_hub == NULL) 4138 return; 4139 4140 index = udev->controller_slot_id; 4141 4142 XHCI_CMD_LOCK(sc); 4143 4144 /* blindly suspend all endpoints */ 4145 4146 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4147 err = xhci_cmd_stop_ep(sc, 1, n, index); 4148 if (err != 0) { 4149 DPRINTF("Failed to suspend endpoint " 4150 "%u on slot %u (ignored).\n", n, index); 4151 } 4152 } 4153 4154 XHCI_CMD_UNLOCK(sc); 4155 } 4156 4157 static void 4158 xhci_set_hw_power(struct usb_bus *bus) 4159 { 4160 DPRINTF("\n"); 4161 } 4162 4163 static void 4164 xhci_device_state_change(struct usb_device *udev) 4165 { 4166 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4167 struct usb_page_search buf_inp; 4168 usb_error_t err; 4169 uint8_t index; 4170 4171 /* check for root HUB */ 4172 if (udev->parent_hub == NULL) 4173 return; 4174 4175 index = udev->controller_slot_id; 4176 4177 DPRINTF("\n"); 4178 4179 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4180 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4181 &sc->sc_hw.devs[index].tt); 4182 if (err != 0) 4183 sc->sc_hw.devs[index].nports = 0; 4184 } 4185 4186 XHCI_CMD_LOCK(sc); 4187 4188 switch (usb_get_device_state(udev)) { 4189 case USB_STATE_POWERED: 4190 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4191 break; 4192 4193 /* set default state */ 4194 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4195 4196 /* reset number of contexts */ 4197 sc->sc_hw.devs[index].context_num = 0; 4198 4199 err = xhci_cmd_reset_dev(sc, index); 4200 4201 if (err != 0) { 4202 DPRINTF("Device reset failed " 4203 "for slot %u.\n", index); 4204 } 4205 break; 4206 4207 case USB_STATE_ADDRESSED: 4208 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4209 break; 4210 4211 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4212 4213 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4214 4215 if (err) { 4216 DPRINTF("Failed to deconfigure " 4217 "slot %u.\n", index); 4218 } 4219 break; 4220 4221 case USB_STATE_CONFIGURED: 4222 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4223 break; 4224 4225 /* set configured state */ 4226 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4227 4228 /* reset number of contexts */ 4229 sc->sc_hw.devs[index].context_num = 0; 4230 4231 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4232 4233 xhci_configure_mask(udev, 3, 0); 4234 4235 err = xhci_configure_device(udev); 4236 if (err != 0) { 4237 DPRINTF("Could not configure device " 4238 "at slot %u.\n", index); 4239 } 4240 4241 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4242 if (err != 0) { 4243 DPRINTF("Could not evaluate device " 4244 "context at slot %u.\n", index); 4245 } 4246 break; 4247 4248 default: 4249 break; 4250 } 4251 XHCI_CMD_UNLOCK(sc); 4252 } 4253 4254 static usb_error_t 4255 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4256 uint8_t ep_mode) 4257 { 4258 switch (ep_mode) { 4259 case USB_EP_MODE_DEFAULT: 4260 return (0); 4261 case USB_EP_MODE_STREAMS: 4262 if (xhcistreams == 0 || 4263 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4264 udev->speed != USB_SPEED_SUPER) 4265 return (USB_ERR_INVAL); 4266 return (0); 4267 default: 4268 return (USB_ERR_INVAL); 4269 } 4270 } 4271 4272 static const struct usb_bus_methods xhci_bus_methods = { 4273 .endpoint_init = xhci_ep_init, 4274 .endpoint_uninit = xhci_ep_uninit, 4275 .xfer_setup = xhci_xfer_setup, 4276 .xfer_unsetup = xhci_xfer_unsetup, 4277 .get_dma_delay = xhci_get_dma_delay, 4278 .device_init = xhci_device_init, 4279 .device_uninit = xhci_device_uninit, 4280 .device_resume = xhci_device_resume, 4281 .device_suspend = xhci_device_suspend, 4282 .set_hw_power = xhci_set_hw_power, 4283 .roothub_exec = xhci_roothub_exec, 4284 .xfer_poll = xhci_do_poll, 4285 .start_dma_delay = xhci_start_dma_delay, 4286 .set_address = xhci_set_address, 4287 .clear_stall = xhci_ep_clear_stall, 4288 .device_state_change = xhci_device_state_change, 4289 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4290 .set_endpoint_mode = xhci_set_endpoint_mode, 4291 }; 4292