1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 28 * 29 * The XHCI 1.0 spec can be found at 30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 31 * and the USB 3.0 spec at 32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 33 */ 34 35 /* 36 * A few words about the design implementation: This driver emulates 37 * the concept about TDs which is found in EHCI specification. This 38 * way we avoid too much diveration among USB drivers. 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/stdint.h> 45 #include <sys/stddef.h> 46 #include <sys/param.h> 47 #include <sys/queue.h> 48 #include <sys/types.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/bus.h> 52 #include <sys/module.h> 53 #include <sys/lock.h> 54 #include <sys/mutex.h> 55 #include <sys/condvar.h> 56 #include <sys/sysctl.h> 57 #include <sys/sx.h> 58 #include <sys/unistd.h> 59 #include <sys/callout.h> 60 #include <sys/malloc.h> 61 #include <sys/priv.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 66 #define USB_DEBUG_VAR xhcidebug 67 68 #include <dev/usb/usb_core.h> 69 #include <dev/usb/usb_debug.h> 70 #include <dev/usb/usb_busdma.h> 71 #include <dev/usb/usb_process.h> 72 #include <dev/usb/usb_transfer.h> 73 #include <dev/usb/usb_device.h> 74 #include <dev/usb/usb_hub.h> 75 #include <dev/usb/usb_util.h> 76 77 #include <dev/usb/usb_controller.h> 78 #include <dev/usb/usb_bus.h> 79 #include <dev/usb/controller/xhci.h> 80 #include <dev/usb/controller/xhcireg.h> 81 82 #define XHCI_BUS2SC(bus) \ 83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 85 86 #ifdef USB_DEBUG 87 static int xhcidebug = 0; 88 89 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 90 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW, 91 &xhcidebug, 0, "Debug level"); 92 93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 94 95 #endif 96 97 #define XHCI_INTR_ENDPT 1 98 99 struct xhci_std_temp { 100 struct xhci_softc *sc; 101 struct usb_page_cache *pc; 102 struct xhci_td *td; 103 struct xhci_td *td_next; 104 uint32_t len; 105 uint32_t offset; 106 uint32_t max_packet_size; 107 uint32_t average; 108 uint16_t isoc_delta; 109 uint16_t isoc_frame; 110 uint8_t shortpkt; 111 uint8_t multishort; 112 uint8_t last_frame; 113 uint8_t trb_type; 114 uint8_t direction; 115 uint8_t tbc; 116 uint8_t tlbpc; 117 uint8_t step_td; 118 }; 119 120 static void xhci_do_poll(struct usb_bus *); 121 static void xhci_device_done(struct usb_xfer *, usb_error_t); 122 static void xhci_root_intr(struct xhci_softc *); 123 static void xhci_free_device_ext(struct usb_device *); 124 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 125 struct usb_endpoint_descriptor *); 126 static usb_proc_callback_t xhci_configure_msg; 127 static usb_error_t xhci_configure_device(struct usb_device *); 128 static usb_error_t xhci_configure_endpoint(struct usb_device *, 129 struct usb_endpoint_descriptor *, uint64_t, uint16_t, 130 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t); 131 static usb_error_t xhci_configure_mask(struct usb_device *, 132 uint32_t, uint8_t); 133 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 134 uint64_t, uint8_t); 135 static void xhci_endpoint_doorbell(struct usb_xfer *); 136 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 137 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 138 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 139 #ifdef USB_DEBUG 140 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 141 #endif 142 143 extern struct usb_bus_methods xhci_bus_methods; 144 145 #ifdef USB_DEBUG 146 static void 147 xhci_dump_trb(struct xhci_trb *trb) 148 { 149 DPRINTFN(5, "trb = %p\n", trb); 150 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 151 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 152 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 153 } 154 155 static void 156 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 157 { 158 DPRINTFN(5, "pep = %p\n", pep); 159 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 160 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 161 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 162 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 163 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 164 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 165 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 166 } 167 168 static void 169 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 170 { 171 DPRINTFN(5, "psl = %p\n", psl); 172 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 173 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 174 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 175 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 176 } 177 #endif 178 179 static void 180 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 181 { 182 struct xhci_softc *sc = XHCI_BUS2SC(bus); 183 uint8_t i; 184 185 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 186 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 187 188 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 189 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 190 191 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 192 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 193 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 194 } 195 } 196 197 static void 198 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 199 { 200 if (sc->sc_ctx_is_64_byte) { 201 uint32_t offset; 202 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 203 /* all contexts are initially 32-bytes */ 204 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 205 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 206 } 207 *ptr = htole32(val); 208 } 209 210 static uint32_t 211 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 212 { 213 if (sc->sc_ctx_is_64_byte) { 214 uint32_t offset; 215 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 216 /* all contexts are initially 32-bytes */ 217 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 218 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 219 } 220 return (le32toh(*ptr)); 221 } 222 223 static void 224 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 225 { 226 if (sc->sc_ctx_is_64_byte) { 227 uint32_t offset; 228 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 229 /* all contexts are initially 32-bytes */ 230 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 231 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 232 } 233 *ptr = htole64(val); 234 } 235 236 #ifdef USB_DEBUG 237 static uint64_t 238 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 239 { 240 if (sc->sc_ctx_is_64_byte) { 241 uint32_t offset; 242 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 243 /* all contexts are initially 32-bytes */ 244 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 245 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 246 } 247 return (le64toh(*ptr)); 248 } 249 #endif 250 251 usb_error_t 252 xhci_start_controller(struct xhci_softc *sc) 253 { 254 struct usb_page_search buf_res; 255 struct xhci_hw_root *phwr; 256 struct xhci_dev_ctx_addr *pdctxa; 257 uint64_t addr; 258 uint32_t temp; 259 uint16_t i; 260 261 DPRINTF("\n"); 262 263 sc->sc_capa_off = 0; 264 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 265 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 266 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 267 268 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 269 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 270 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 271 272 sc->sc_event_ccs = 1; 273 sc->sc_event_idx = 0; 274 sc->sc_command_ccs = 1; 275 sc->sc_command_idx = 0; 276 277 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 278 279 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 280 281 DPRINTF("HCS0 = 0x%08x\n", temp); 282 283 if (XHCI_HCS0_CSZ(temp)) { 284 sc->sc_ctx_is_64_byte = 1; 285 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 286 } else { 287 sc->sc_ctx_is_64_byte = 0; 288 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 289 } 290 291 /* Reset controller */ 292 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 293 294 for (i = 0; i != 100; i++) { 295 usb_pause_mtx(NULL, hz / 100); 296 temp = XREAD4(sc, oper, XHCI_USBCMD) & 297 (XHCI_CMD_HCRST | XHCI_STS_CNR); 298 if (!temp) 299 break; 300 } 301 302 if (temp) { 303 device_printf(sc->sc_bus.parent, "Controller " 304 "reset timeout.\n"); 305 return (USB_ERR_IOERROR); 306 } 307 308 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 309 device_printf(sc->sc_bus.parent, "Controller does " 310 "not support 4K page size.\n"); 311 return (USB_ERR_IOERROR); 312 } 313 314 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 315 316 i = XHCI_HCS1_N_PORTS(temp); 317 318 if (i == 0) { 319 device_printf(sc->sc_bus.parent, "Invalid number " 320 "of ports: %u\n", i); 321 return (USB_ERR_IOERROR); 322 } 323 324 sc->sc_noport = i; 325 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 326 327 if (sc->sc_noslot > XHCI_MAX_DEVICES) 328 sc->sc_noslot = XHCI_MAX_DEVICES; 329 330 /* setup number of device slots */ 331 332 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 333 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 334 335 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 336 337 DPRINTF("Max slots: %u\n", sc->sc_noslot); 338 339 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 340 341 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 342 343 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 344 device_printf(sc->sc_bus.parent, "XHCI request " 345 "too many scratchpads\n"); 346 return (USB_ERR_NOMEM); 347 } 348 349 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 350 351 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 352 353 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 354 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 355 356 temp = XREAD4(sc, oper, XHCI_USBSTS); 357 358 /* clear interrupts */ 359 XWRITE4(sc, oper, XHCI_USBSTS, temp); 360 /* disable all device notifications */ 361 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 362 363 /* setup device context base address */ 364 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 365 pdctxa = buf_res.buffer; 366 memset(pdctxa, 0, sizeof(*pdctxa)); 367 368 addr = buf_res.physaddr; 369 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 370 371 /* slot 0 points to the table of scratchpad pointers */ 372 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 373 374 for (i = 0; i != sc->sc_noscratch; i++) { 375 struct usb_page_search buf_scp; 376 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 377 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 378 } 379 380 addr = buf_res.physaddr; 381 382 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 383 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 384 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 385 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 386 387 /* Setup event table size */ 388 389 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 390 391 DPRINTF("HCS2=0x%08x\n", temp); 392 393 temp = XHCI_HCS2_ERST_MAX(temp); 394 temp = 1U << temp; 395 if (temp > XHCI_MAX_RSEG) 396 temp = XHCI_MAX_RSEG; 397 398 sc->sc_erst_max = temp; 399 400 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 401 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 402 403 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 404 405 /* Setup interrupt rate */ 406 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 407 408 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 409 410 phwr = buf_res.buffer; 411 addr = buf_res.physaddr; 412 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 413 414 /* reset hardware root structure */ 415 memset(phwr, 0, sizeof(*phwr)); 416 417 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 418 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 419 420 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 421 422 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 423 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 424 425 addr = (uint64_t)buf_res.physaddr; 426 427 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 428 429 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 430 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 431 432 /* Setup interrupter registers */ 433 434 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 435 temp |= XHCI_IMAN_INTR_ENA; 436 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 437 438 /* setup command ring control base address */ 439 addr = buf_res.physaddr; 440 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 441 442 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 443 444 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 445 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 446 447 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 448 449 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 450 451 /* Go! */ 452 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 453 XHCI_CMD_INTE | XHCI_CMD_HSEE); 454 455 for (i = 0; i != 100; i++) { 456 usb_pause_mtx(NULL, hz / 100); 457 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 458 if (!temp) 459 break; 460 } 461 if (temp) { 462 XWRITE4(sc, oper, XHCI_USBCMD, 0); 463 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 464 return (USB_ERR_IOERROR); 465 } 466 467 /* catch any lost interrupts */ 468 xhci_do_poll(&sc->sc_bus); 469 470 return (0); 471 } 472 473 usb_error_t 474 xhci_halt_controller(struct xhci_softc *sc) 475 { 476 uint32_t temp; 477 uint16_t i; 478 479 DPRINTF("\n"); 480 481 sc->sc_capa_off = 0; 482 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 483 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 484 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 485 486 /* Halt controller */ 487 XWRITE4(sc, oper, XHCI_USBCMD, 0); 488 489 for (i = 0; i != 100; i++) { 490 usb_pause_mtx(NULL, hz / 100); 491 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 492 if (temp) 493 break; 494 } 495 496 if (!temp) { 497 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 498 return (USB_ERR_IOERROR); 499 } 500 return (0); 501 } 502 503 usb_error_t 504 xhci_init(struct xhci_softc *sc, device_t self) 505 { 506 /* initialise some bus fields */ 507 sc->sc_bus.parent = self; 508 509 /* set the bus revision */ 510 sc->sc_bus.usbrev = USB_REV_3_0; 511 512 /* set up the bus struct */ 513 sc->sc_bus.methods = &xhci_bus_methods; 514 515 /* setup devices array */ 516 sc->sc_bus.devices = sc->sc_devices; 517 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 518 519 /* setup command queue mutex and condition varible */ 520 cv_init(&sc->sc_cmd_cv, "CMDQ"); 521 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 522 523 /* get all DMA memory */ 524 if (usb_bus_mem_alloc_all(&sc->sc_bus, 525 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 526 return (ENOMEM); 527 } 528 529 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 530 sc->sc_config_msg[0].bus = &sc->sc_bus; 531 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 532 sc->sc_config_msg[1].bus = &sc->sc_bus; 533 534 if (usb_proc_create(&sc->sc_config_proc, 535 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) { 536 printf("WARNING: Creation of XHCI configure " 537 "callback process failed.\n"); 538 } 539 return (0); 540 } 541 542 void 543 xhci_uninit(struct xhci_softc *sc) 544 { 545 usb_proc_free(&sc->sc_config_proc); 546 547 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 548 549 cv_destroy(&sc->sc_cmd_cv); 550 sx_destroy(&sc->sc_cmd_sx); 551 } 552 553 static void 554 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 555 { 556 struct xhci_softc *sc = XHCI_BUS2SC(bus); 557 558 switch (state) { 559 case USB_HW_POWER_SUSPEND: 560 DPRINTF("Stopping the XHCI\n"); 561 xhci_halt_controller(sc); 562 break; 563 case USB_HW_POWER_SHUTDOWN: 564 DPRINTF("Stopping the XHCI\n"); 565 xhci_halt_controller(sc); 566 break; 567 case USB_HW_POWER_RESUME: 568 DPRINTF("Starting the XHCI\n"); 569 xhci_start_controller(sc); 570 break; 571 default: 572 break; 573 } 574 } 575 576 static usb_error_t 577 xhci_generic_done_sub(struct usb_xfer *xfer) 578 { 579 struct xhci_td *td; 580 struct xhci_td *td_alt_next; 581 uint32_t len; 582 uint8_t status; 583 584 td = xfer->td_transfer_cache; 585 td_alt_next = td->alt_next; 586 587 if (xfer->aframes != xfer->nframes) 588 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 589 590 while (1) { 591 592 usb_pc_cpu_invalidate(td->page_cache); 593 594 status = td->status; 595 len = td->remainder; 596 597 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 598 xfer, (unsigned int)xfer->aframes, 599 (unsigned int)xfer->nframes, 600 (unsigned int)len, (unsigned int)td->len, 601 (unsigned int)status); 602 603 /* 604 * Verify the status length and 605 * add the length to "frlengths[]": 606 */ 607 if (len > td->len) { 608 /* should not happen */ 609 DPRINTF("Invalid status length, " 610 "0x%04x/0x%04x bytes\n", len, td->len); 611 status = XHCI_TRB_ERROR_LENGTH; 612 } else if (xfer->aframes != xfer->nframes) { 613 xfer->frlengths[xfer->aframes] += td->len - len; 614 } 615 /* Check for last transfer */ 616 if (((void *)td) == xfer->td_transfer_last) { 617 td = NULL; 618 break; 619 } 620 /* Check for transfer error */ 621 if (status != XHCI_TRB_ERROR_SHORT_PKT && 622 status != XHCI_TRB_ERROR_SUCCESS) { 623 /* the transfer is finished */ 624 td = NULL; 625 break; 626 } 627 /* Check for short transfer */ 628 if (len > 0) { 629 if (xfer->flags_int.short_frames_ok || 630 xfer->flags_int.isochronous_xfr || 631 xfer->flags_int.control_xfr) { 632 /* follow alt next */ 633 td = td->alt_next; 634 } else { 635 /* the transfer is finished */ 636 td = NULL; 637 } 638 break; 639 } 640 td = td->obj_next; 641 642 if (td->alt_next != td_alt_next) { 643 /* this USB frame is complete */ 644 break; 645 } 646 } 647 648 /* update transfer cache */ 649 650 xfer->td_transfer_cache = td; 651 652 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 653 (status != XHCI_TRB_ERROR_SHORT_PKT && 654 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 655 USB_ERR_NORMAL_COMPLETION); 656 } 657 658 static void 659 xhci_generic_done(struct usb_xfer *xfer) 660 { 661 usb_error_t err = 0; 662 663 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 664 xfer, xfer->endpoint); 665 666 /* reset scanner */ 667 668 xfer->td_transfer_cache = xfer->td_transfer_first; 669 670 if (xfer->flags_int.control_xfr) { 671 672 if (xfer->flags_int.control_hdr) 673 err = xhci_generic_done_sub(xfer); 674 675 xfer->aframes = 1; 676 677 if (xfer->td_transfer_cache == NULL) 678 goto done; 679 } 680 681 while (xfer->aframes != xfer->nframes) { 682 683 err = xhci_generic_done_sub(xfer); 684 xfer->aframes++; 685 686 if (xfer->td_transfer_cache == NULL) 687 goto done; 688 } 689 690 if (xfer->flags_int.control_xfr && 691 !xfer->flags_int.control_act) 692 err = xhci_generic_done_sub(xfer); 693 done: 694 /* transfer is complete */ 695 xhci_device_done(xfer, err); 696 } 697 698 static void 699 xhci_activate_transfer(struct usb_xfer *xfer) 700 { 701 struct xhci_td *td; 702 703 td = xfer->td_transfer_cache; 704 705 usb_pc_cpu_invalidate(td->page_cache); 706 707 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 708 709 /* activate the transfer */ 710 711 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 712 usb_pc_cpu_flush(td->page_cache); 713 714 xhci_endpoint_doorbell(xfer); 715 } 716 } 717 718 static void 719 xhci_skip_transfer(struct usb_xfer *xfer) 720 { 721 struct xhci_td *td; 722 struct xhci_td *td_last; 723 724 td = xfer->td_transfer_cache; 725 td_last = xfer->td_transfer_last; 726 727 td = td->alt_next; 728 729 usb_pc_cpu_invalidate(td->page_cache); 730 731 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 732 733 usb_pc_cpu_invalidate(td_last->page_cache); 734 735 /* copy LINK TRB to current waiting location */ 736 737 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 738 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 739 usb_pc_cpu_flush(td->page_cache); 740 741 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 742 usb_pc_cpu_flush(td->page_cache); 743 744 xhci_endpoint_doorbell(xfer); 745 } 746 } 747 748 /*------------------------------------------------------------------------* 749 * xhci_check_transfer 750 *------------------------------------------------------------------------*/ 751 static void 752 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 753 { 754 int64_t offset; 755 uint64_t td_event; 756 uint32_t temp; 757 uint32_t remainder; 758 uint8_t status; 759 uint8_t halted; 760 uint8_t epno; 761 uint8_t index; 762 uint8_t i; 763 764 /* decode TRB */ 765 td_event = le64toh(trb->qwTrb0); 766 temp = le32toh(trb->dwTrb2); 767 768 remainder = XHCI_TRB_2_REM_GET(temp); 769 status = XHCI_TRB_2_ERROR_GET(temp); 770 771 temp = le32toh(trb->dwTrb3); 772 epno = XHCI_TRB_3_EP_GET(temp); 773 index = XHCI_TRB_3_SLOT_GET(temp); 774 775 /* check if error means halted */ 776 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 777 status != XHCI_TRB_ERROR_SUCCESS); 778 779 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 780 index, epno, remainder, status); 781 782 if (index > sc->sc_noslot) { 783 DPRINTF("Invalid slot.\n"); 784 return; 785 } 786 787 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 788 DPRINTF("Invalid endpoint.\n"); 789 return; 790 } 791 792 /* try to find the USB transfer that generated the event */ 793 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 794 struct usb_xfer *xfer; 795 struct xhci_td *td; 796 struct xhci_endpoint_ext *pepext; 797 798 pepext = &sc->sc_hw.devs[index].endp[epno]; 799 800 xfer = pepext->xfer[i]; 801 if (xfer == NULL) 802 continue; 803 804 td = xfer->td_transfer_cache; 805 806 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 807 (long long)td_event, 808 (long long)td->td_self, 809 (long long)td->td_self + sizeof(td->td_trb)); 810 811 /* 812 * NOTE: Some XHCI implementations might not trigger 813 * an event on the last LINK TRB so we need to 814 * consider both the last and second last event 815 * address as conditions for a successful transfer. 816 * 817 * NOTE: We assume that the XHCI will only trigger one 818 * event per chain of TRBs. 819 */ 820 821 offset = td_event - td->td_self; 822 823 if (offset >= 0 && 824 offset < sizeof(td->td_trb)) { 825 826 usb_pc_cpu_invalidate(td->page_cache); 827 828 /* compute rest of remainder, if any */ 829 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 830 temp = le32toh(td->td_trb[i].dwTrb2); 831 remainder += XHCI_TRB_2_BYTES_GET(temp); 832 } 833 834 DPRINTFN(5, "New remainder: %u\n", remainder); 835 836 /* clear isochronous transfer errors */ 837 if (xfer->flags_int.isochronous_xfr) { 838 if (halted) { 839 halted = 0; 840 status = XHCI_TRB_ERROR_SUCCESS; 841 remainder = td->len; 842 } 843 } 844 845 /* "td->remainder" is verified later */ 846 td->remainder = remainder; 847 td->status = status; 848 849 usb_pc_cpu_flush(td->page_cache); 850 851 /* 852 * 1) Last transfer descriptor makes the 853 * transfer done 854 */ 855 if (((void *)td) == xfer->td_transfer_last) { 856 DPRINTF("TD is last\n"); 857 xhci_generic_done(xfer); 858 break; 859 } 860 861 /* 862 * 2) Any kind of error makes the transfer 863 * done 864 */ 865 if (halted) { 866 DPRINTF("TD has I/O error\n"); 867 xhci_generic_done(xfer); 868 break; 869 } 870 871 /* 872 * 3) If there is no alternate next transfer, 873 * a short packet also makes the transfer done 874 */ 875 if (td->remainder > 0) { 876 DPRINTF("TD has short pkt\n"); 877 if (xfer->flags_int.short_frames_ok || 878 xfer->flags_int.isochronous_xfr || 879 xfer->flags_int.control_xfr) { 880 /* follow the alt next */ 881 xfer->td_transfer_cache = td->alt_next; 882 xhci_activate_transfer(xfer); 883 break; 884 } 885 xhci_skip_transfer(xfer); 886 xhci_generic_done(xfer); 887 break; 888 } 889 890 /* 891 * 4) Transfer complete - go to next TD 892 */ 893 DPRINTF("Following next TD\n"); 894 xfer->td_transfer_cache = td->obj_next; 895 xhci_activate_transfer(xfer); 896 break; /* there should only be one match */ 897 } 898 } 899 } 900 901 static void 902 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 903 { 904 if (sc->sc_cmd_addr == trb->qwTrb0) { 905 DPRINTF("Received command event\n"); 906 sc->sc_cmd_result[0] = trb->dwTrb2; 907 sc->sc_cmd_result[1] = trb->dwTrb3; 908 cv_signal(&sc->sc_cmd_cv); 909 } 910 } 911 912 static void 913 xhci_interrupt_poll(struct xhci_softc *sc) 914 { 915 struct usb_page_search buf_res; 916 struct xhci_hw_root *phwr; 917 uint64_t addr; 918 uint32_t temp; 919 uint16_t i; 920 uint8_t event; 921 uint8_t j; 922 uint8_t k; 923 uint8_t t; 924 925 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 926 927 phwr = buf_res.buffer; 928 929 /* Receive any events */ 930 931 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 932 933 i = sc->sc_event_idx; 934 j = sc->sc_event_ccs; 935 t = 2; 936 937 while (1) { 938 939 temp = le32toh(phwr->hwr_events[i].dwTrb3); 940 941 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 942 943 if (j != k) 944 break; 945 946 event = XHCI_TRB_3_TYPE_GET(temp); 947 948 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 949 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 950 (long)le32toh(phwr->hwr_events[i].dwTrb2), 951 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 952 953 switch (event) { 954 case XHCI_TRB_EVENT_TRANSFER: 955 xhci_check_transfer(sc, &phwr->hwr_events[i]); 956 break; 957 case XHCI_TRB_EVENT_CMD_COMPLETE: 958 xhci_check_command(sc, &phwr->hwr_events[i]); 959 break; 960 default: 961 DPRINTF("Unhandled event = %u\n", event); 962 break; 963 } 964 965 i++; 966 967 if (i == XHCI_MAX_EVENTS) { 968 i = 0; 969 j ^= 1; 970 971 /* check for timeout */ 972 if (!--t) 973 break; 974 } 975 } 976 977 sc->sc_event_idx = i; 978 sc->sc_event_ccs = j; 979 980 /* 981 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 982 * latched. That means to activate the register we need to 983 * write both the low and high double word of the 64-bit 984 * register. 985 */ 986 987 addr = (uint32_t)buf_res.physaddr; 988 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 989 990 /* try to clear busy bit */ 991 addr |= XHCI_ERDP_LO_BUSY; 992 993 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 994 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 995 } 996 997 static usb_error_t 998 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 999 uint16_t timeout_ms) 1000 { 1001 struct usb_page_search buf_res; 1002 struct xhci_hw_root *phwr; 1003 uint64_t addr; 1004 uint32_t temp; 1005 uint8_t i; 1006 uint8_t j; 1007 int err; 1008 1009 XHCI_CMD_ASSERT_LOCKED(sc); 1010 1011 /* get hardware root structure */ 1012 1013 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1014 1015 phwr = buf_res.buffer; 1016 1017 /* Queue command */ 1018 1019 USB_BUS_LOCK(&sc->sc_bus); 1020 1021 i = sc->sc_command_idx; 1022 j = sc->sc_command_ccs; 1023 1024 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1025 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1026 (long long)le64toh(trb->qwTrb0), 1027 (long)le32toh(trb->dwTrb2), 1028 (long)le32toh(trb->dwTrb3)); 1029 1030 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1031 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1032 1033 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1034 1035 temp = trb->dwTrb3; 1036 1037 if (j) 1038 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1039 else 1040 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1041 1042 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1043 1044 phwr->hwr_commands[i].dwTrb3 = temp; 1045 1046 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1047 1048 addr = buf_res.physaddr; 1049 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1050 1051 sc->sc_cmd_addr = htole64(addr); 1052 1053 i++; 1054 1055 if (i == (XHCI_MAX_COMMANDS - 1)) { 1056 1057 if (j) { 1058 temp = htole32(XHCI_TRB_3_TC_BIT | 1059 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1060 XHCI_TRB_3_CYCLE_BIT); 1061 } else { 1062 temp = htole32(XHCI_TRB_3_TC_BIT | 1063 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1064 } 1065 1066 phwr->hwr_commands[i].dwTrb3 = temp; 1067 1068 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1069 1070 i = 0; 1071 j ^= 1; 1072 } 1073 1074 sc->sc_command_idx = i; 1075 sc->sc_command_ccs = j; 1076 1077 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1078 1079 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1080 USB_MS_TO_TICKS(timeout_ms)); 1081 1082 if (err) { 1083 DPRINTFN(0, "Command timeout!\n"); 1084 err = USB_ERR_TIMEOUT; 1085 trb->dwTrb2 = 0; 1086 trb->dwTrb3 = 0; 1087 } else { 1088 temp = le32toh(sc->sc_cmd_result[0]); 1089 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1090 err = USB_ERR_IOERROR; 1091 1092 trb->dwTrb2 = sc->sc_cmd_result[0]; 1093 trb->dwTrb3 = sc->sc_cmd_result[1]; 1094 } 1095 1096 USB_BUS_UNLOCK(&sc->sc_bus); 1097 1098 return (err); 1099 } 1100 1101 #if 0 1102 static usb_error_t 1103 xhci_cmd_nop(struct xhci_softc *sc) 1104 { 1105 struct xhci_trb trb; 1106 uint32_t temp; 1107 1108 DPRINTF("\n"); 1109 1110 trb.qwTrb0 = 0; 1111 trb.dwTrb2 = 0; 1112 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1113 1114 trb.dwTrb3 = htole32(temp); 1115 1116 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1117 } 1118 #endif 1119 1120 static usb_error_t 1121 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1122 { 1123 struct xhci_trb trb; 1124 uint32_t temp; 1125 usb_error_t err; 1126 1127 DPRINTF("\n"); 1128 1129 trb.qwTrb0 = 0; 1130 trb.dwTrb2 = 0; 1131 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1132 1133 err = xhci_do_command(sc, &trb, 100 /* ms */); 1134 if (err) 1135 goto done; 1136 1137 temp = le32toh(trb.dwTrb3); 1138 1139 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1140 1141 done: 1142 return (err); 1143 } 1144 1145 static usb_error_t 1146 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1147 { 1148 struct xhci_trb trb; 1149 uint32_t temp; 1150 1151 DPRINTF("\n"); 1152 1153 trb.qwTrb0 = 0; 1154 trb.dwTrb2 = 0; 1155 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1156 XHCI_TRB_3_SLOT_SET(slot_id); 1157 1158 trb.dwTrb3 = htole32(temp); 1159 1160 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1161 } 1162 1163 static usb_error_t 1164 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1165 uint8_t bsr, uint8_t slot_id) 1166 { 1167 struct xhci_trb trb; 1168 uint32_t temp; 1169 1170 DPRINTF("\n"); 1171 1172 trb.qwTrb0 = htole64(input_ctx); 1173 trb.dwTrb2 = 0; 1174 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1175 XHCI_TRB_3_SLOT_SET(slot_id); 1176 1177 if (bsr) 1178 temp |= XHCI_TRB_3_BSR_BIT; 1179 1180 trb.dwTrb3 = htole32(temp); 1181 1182 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1183 } 1184 1185 static usb_error_t 1186 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1187 { 1188 struct usb_page_search buf_inp; 1189 struct usb_page_search buf_dev; 1190 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1191 struct xhci_hw_dev *hdev; 1192 struct xhci_dev_ctx *pdev; 1193 struct xhci_endpoint_ext *pepext; 1194 uint32_t temp; 1195 uint16_t mps; 1196 usb_error_t err; 1197 uint8_t index; 1198 1199 /* the root HUB case is not handled here */ 1200 if (udev->parent_hub == NULL) 1201 return (USB_ERR_INVAL); 1202 1203 index = udev->controller_slot_id; 1204 1205 hdev = &sc->sc_hw.devs[index]; 1206 1207 if (mtx != NULL) 1208 mtx_unlock(mtx); 1209 1210 XHCI_CMD_LOCK(sc); 1211 1212 switch (hdev->state) { 1213 case XHCI_ST_DEFAULT: 1214 case XHCI_ST_ENABLED: 1215 1216 hdev->state = XHCI_ST_ENABLED; 1217 1218 /* set configure mask to slot and EP0 */ 1219 xhci_configure_mask(udev, 3, 0); 1220 1221 /* configure input slot context structure */ 1222 err = xhci_configure_device(udev); 1223 1224 if (err != 0) { 1225 DPRINTF("Could not configure device\n"); 1226 break; 1227 } 1228 1229 /* configure input endpoint context structure */ 1230 switch (udev->speed) { 1231 case USB_SPEED_LOW: 1232 case USB_SPEED_FULL: 1233 mps = 8; 1234 break; 1235 case USB_SPEED_HIGH: 1236 mps = 64; 1237 break; 1238 default: 1239 mps = 512; 1240 break; 1241 } 1242 1243 pepext = xhci_get_endpoint_ext(udev, 1244 &udev->ctrl_ep_desc); 1245 err = xhci_configure_endpoint(udev, 1246 &udev->ctrl_ep_desc, pepext->physaddr, 1247 0, 1, 1, 0, mps, mps); 1248 1249 if (err != 0) { 1250 DPRINTF("Could not configure default endpoint\n"); 1251 break; 1252 } 1253 1254 /* execute set address command */ 1255 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1256 1257 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1258 (address == 0), index); 1259 1260 if (err != 0) { 1261 DPRINTF("Could not set address " 1262 "for slot %u.\n", index); 1263 if (address != 0) 1264 break; 1265 } 1266 1267 /* update device address to new value */ 1268 1269 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1270 pdev = buf_dev.buffer; 1271 usb_pc_cpu_invalidate(&hdev->device_pc); 1272 1273 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1274 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1275 1276 /* update device state to new value */ 1277 1278 if (address != 0) 1279 hdev->state = XHCI_ST_ADDRESSED; 1280 else 1281 hdev->state = XHCI_ST_DEFAULT; 1282 break; 1283 1284 default: 1285 DPRINTF("Wrong state for set address.\n"); 1286 err = USB_ERR_IOERROR; 1287 break; 1288 } 1289 XHCI_CMD_UNLOCK(sc); 1290 1291 if (mtx != NULL) 1292 mtx_lock(mtx); 1293 1294 return (err); 1295 } 1296 1297 static usb_error_t 1298 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1299 uint8_t deconfigure, uint8_t slot_id) 1300 { 1301 struct xhci_trb trb; 1302 uint32_t temp; 1303 1304 DPRINTF("\n"); 1305 1306 trb.qwTrb0 = htole64(input_ctx); 1307 trb.dwTrb2 = 0; 1308 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1309 XHCI_TRB_3_SLOT_SET(slot_id); 1310 1311 if (deconfigure) 1312 temp |= XHCI_TRB_3_DCEP_BIT; 1313 1314 trb.dwTrb3 = htole32(temp); 1315 1316 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1317 } 1318 1319 static usb_error_t 1320 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1321 uint8_t slot_id) 1322 { 1323 struct xhci_trb trb; 1324 uint32_t temp; 1325 1326 DPRINTF("\n"); 1327 1328 trb.qwTrb0 = htole64(input_ctx); 1329 trb.dwTrb2 = 0; 1330 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1331 XHCI_TRB_3_SLOT_SET(slot_id); 1332 trb.dwTrb3 = htole32(temp); 1333 1334 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1335 } 1336 1337 static usb_error_t 1338 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1339 uint8_t ep_id, uint8_t slot_id) 1340 { 1341 struct xhci_trb trb; 1342 uint32_t temp; 1343 1344 DPRINTF("\n"); 1345 1346 trb.qwTrb0 = 0; 1347 trb.dwTrb2 = 0; 1348 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1349 XHCI_TRB_3_SLOT_SET(slot_id) | 1350 XHCI_TRB_3_EP_SET(ep_id); 1351 1352 if (preserve) 1353 temp |= XHCI_TRB_3_PRSV_BIT; 1354 1355 trb.dwTrb3 = htole32(temp); 1356 1357 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1358 } 1359 1360 static usb_error_t 1361 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1362 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1363 { 1364 struct xhci_trb trb; 1365 uint32_t temp; 1366 1367 DPRINTF("\n"); 1368 1369 trb.qwTrb0 = htole64(dequeue_ptr); 1370 1371 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1372 trb.dwTrb2 = htole32(temp); 1373 1374 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1375 XHCI_TRB_3_SLOT_SET(slot_id) | 1376 XHCI_TRB_3_EP_SET(ep_id); 1377 trb.dwTrb3 = htole32(temp); 1378 1379 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1380 } 1381 1382 static usb_error_t 1383 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1384 uint8_t ep_id, uint8_t slot_id) 1385 { 1386 struct xhci_trb trb; 1387 uint32_t temp; 1388 1389 DPRINTF("\n"); 1390 1391 trb.qwTrb0 = 0; 1392 trb.dwTrb2 = 0; 1393 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1394 XHCI_TRB_3_SLOT_SET(slot_id) | 1395 XHCI_TRB_3_EP_SET(ep_id); 1396 1397 if (suspend) 1398 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1399 1400 trb.dwTrb3 = htole32(temp); 1401 1402 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1403 } 1404 1405 static usb_error_t 1406 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1407 { 1408 struct xhci_trb trb; 1409 uint32_t temp; 1410 1411 DPRINTF("\n"); 1412 1413 trb.qwTrb0 = 0; 1414 trb.dwTrb2 = 0; 1415 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1416 XHCI_TRB_3_SLOT_SET(slot_id); 1417 1418 trb.dwTrb3 = htole32(temp); 1419 1420 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1421 } 1422 1423 /*------------------------------------------------------------------------* 1424 * xhci_interrupt - XHCI interrupt handler 1425 *------------------------------------------------------------------------*/ 1426 void 1427 xhci_interrupt(struct xhci_softc *sc) 1428 { 1429 uint32_t status; 1430 uint32_t temp; 1431 1432 USB_BUS_LOCK(&sc->sc_bus); 1433 1434 status = XREAD4(sc, oper, XHCI_USBSTS); 1435 1436 /* acknowledge interrupts */ 1437 1438 XWRITE4(sc, oper, XHCI_USBSTS, status); 1439 1440 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1441 1442 /* acknowledge pending event */ 1443 1444 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1445 1446 DPRINTFN(16, "real interrupt (sts=0x%08x, " 1447 "iman=0x%08x)\n", status, temp); 1448 1449 if (status != 0) { 1450 if (status & XHCI_STS_PCD) { 1451 xhci_root_intr(sc); 1452 } 1453 1454 if (status & XHCI_STS_HCH) { 1455 printf("%s: host controller halted\n", 1456 __FUNCTION__); 1457 } 1458 1459 if (status & XHCI_STS_HSE) { 1460 printf("%s: host system error\n", 1461 __FUNCTION__); 1462 } 1463 1464 if (status & XHCI_STS_HCE) { 1465 printf("%s: host controller error\n", 1466 __FUNCTION__); 1467 } 1468 } 1469 1470 xhci_interrupt_poll(sc); 1471 1472 USB_BUS_UNLOCK(&sc->sc_bus); 1473 } 1474 1475 /*------------------------------------------------------------------------* 1476 * xhci_timeout - XHCI timeout handler 1477 *------------------------------------------------------------------------*/ 1478 static void 1479 xhci_timeout(void *arg) 1480 { 1481 struct usb_xfer *xfer = arg; 1482 1483 DPRINTF("xfer=%p\n", xfer); 1484 1485 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1486 1487 /* transfer is transferred */ 1488 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1489 } 1490 1491 static void 1492 xhci_do_poll(struct usb_bus *bus) 1493 { 1494 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1495 1496 USB_BUS_LOCK(&sc->sc_bus); 1497 xhci_interrupt_poll(sc); 1498 USB_BUS_UNLOCK(&sc->sc_bus); 1499 } 1500 1501 static void 1502 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1503 { 1504 struct usb_page_search buf_res; 1505 struct xhci_td *td; 1506 struct xhci_td *td_next; 1507 struct xhci_td *td_alt_next; 1508 uint32_t buf_offset; 1509 uint32_t average; 1510 uint32_t len_old; 1511 uint32_t dword; 1512 uint8_t shortpkt_old; 1513 uint8_t precompute; 1514 uint8_t x; 1515 1516 td_alt_next = NULL; 1517 buf_offset = 0; 1518 shortpkt_old = temp->shortpkt; 1519 len_old = temp->len; 1520 precompute = 1; 1521 1522 restart: 1523 1524 td = temp->td; 1525 td_next = temp->td_next; 1526 1527 while (1) { 1528 1529 if (temp->len == 0) { 1530 1531 if (temp->shortpkt) 1532 break; 1533 1534 /* send a Zero Length Packet, ZLP, last */ 1535 1536 temp->shortpkt = 1; 1537 average = 0; 1538 1539 } else { 1540 1541 average = temp->average; 1542 1543 if (temp->len < average) { 1544 if (temp->len % temp->max_packet_size) { 1545 temp->shortpkt = 1; 1546 } 1547 average = temp->len; 1548 } 1549 } 1550 1551 if (td_next == NULL) 1552 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1553 1554 /* get next TD */ 1555 1556 td = td_next; 1557 td_next = td->obj_next; 1558 1559 /* check if we are pre-computing */ 1560 1561 if (precompute) { 1562 1563 /* update remaining length */ 1564 1565 temp->len -= average; 1566 1567 continue; 1568 } 1569 /* fill out current TD */ 1570 1571 td->len = average; 1572 td->remainder = 0; 1573 td->status = 0; 1574 1575 /* update remaining length */ 1576 1577 temp->len -= average; 1578 1579 /* reset TRB index */ 1580 1581 x = 0; 1582 1583 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1584 /* immediate data */ 1585 1586 if (average > 8) 1587 average = 8; 1588 1589 td->td_trb[0].qwTrb0 = 0; 1590 1591 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1592 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1593 average); 1594 1595 dword = XHCI_TRB_2_BYTES_SET(8) | 1596 XHCI_TRB_2_TDSZ_SET(0) | 1597 XHCI_TRB_2_IRQ_SET(0); 1598 1599 td->td_trb[0].dwTrb2 = htole32(dword); 1600 1601 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1602 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1603 1604 /* check wLength */ 1605 if (td->td_trb[0].qwTrb0 & 1606 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1607 if (td->td_trb[0].qwTrb0 & htole64(1)) 1608 dword |= XHCI_TRB_3_TRT_IN; 1609 else 1610 dword |= XHCI_TRB_3_TRT_OUT; 1611 } 1612 1613 td->td_trb[0].dwTrb3 = htole32(dword); 1614 #ifdef USB_DEBUG 1615 xhci_dump_trb(&td->td_trb[x]); 1616 #endif 1617 x++; 1618 1619 } else do { 1620 1621 uint32_t npkt; 1622 1623 /* fill out buffer pointers */ 1624 1625 if (average == 0) { 1626 npkt = 1; 1627 memset(&buf_res, 0, sizeof(buf_res)); 1628 } else { 1629 usbd_get_page(temp->pc, temp->offset + 1630 buf_offset, &buf_res); 1631 1632 /* get length to end of page */ 1633 if (buf_res.length > average) 1634 buf_res.length = average; 1635 1636 /* check for maximum length */ 1637 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1638 buf_res.length = XHCI_TD_PAGE_SIZE; 1639 1640 /* setup npkt */ 1641 npkt = (average + temp->max_packet_size - 1) / 1642 temp->max_packet_size; 1643 1644 if (npkt > 31) 1645 npkt = 31; 1646 } 1647 1648 /* fill out TRB's */ 1649 td->td_trb[x].qwTrb0 = 1650 htole64((uint64_t)buf_res.physaddr); 1651 1652 dword = 1653 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1654 XHCI_TRB_2_TDSZ_SET(npkt) | 1655 XHCI_TRB_2_IRQ_SET(0); 1656 1657 td->td_trb[x].dwTrb2 = htole32(dword); 1658 1659 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1660 XHCI_TRB_3_TYPE_SET(temp->trb_type) | 1661 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) | 1662 XHCI_TRB_3_TBC_SET(temp->tbc) | 1663 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1664 1665 if (temp->direction == UE_DIR_IN) { 1666 dword |= XHCI_TRB_3_DIR_IN; 1667 1668 /* 1669 * NOTE: Only the SETUP stage should 1670 * use the IDT bit. Else transactions 1671 * can be sent using the wrong data 1672 * toggle value. 1673 */ 1674 if (temp->trb_type != 1675 XHCI_TRB_TYPE_SETUP_STAGE && 1676 temp->trb_type != 1677 XHCI_TRB_TYPE_STATUS_STAGE) 1678 dword |= XHCI_TRB_3_ISP_BIT; 1679 } 1680 1681 td->td_trb[x].dwTrb3 = htole32(dword); 1682 1683 average -= buf_res.length; 1684 buf_offset += buf_res.length; 1685 #ifdef USB_DEBUG 1686 xhci_dump_trb(&td->td_trb[x]); 1687 #endif 1688 x++; 1689 1690 } while (average != 0); 1691 1692 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1693 1694 /* store number of data TRB's */ 1695 1696 td->ntrb = x; 1697 1698 DPRINTF("NTRB=%u\n", x); 1699 1700 /* fill out link TRB */ 1701 1702 if (td_next != NULL) { 1703 /* link the current TD with the next one */ 1704 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1705 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1706 } else { 1707 /* this field will get updated later */ 1708 DPRINTF("NOLINK\n"); 1709 } 1710 1711 dword = XHCI_TRB_2_IRQ_SET(0); 1712 1713 td->td_trb[x].dwTrb2 = htole32(dword); 1714 1715 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1716 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT; 1717 1718 td->td_trb[x].dwTrb3 = htole32(dword); 1719 1720 td->alt_next = td_alt_next; 1721 #ifdef USB_DEBUG 1722 xhci_dump_trb(&td->td_trb[x]); 1723 #endif 1724 usb_pc_cpu_flush(td->page_cache); 1725 } 1726 1727 if (precompute) { 1728 precompute = 0; 1729 1730 /* setup alt next pointer, if any */ 1731 if (temp->last_frame) { 1732 td_alt_next = NULL; 1733 } else { 1734 /* we use this field internally */ 1735 td_alt_next = td_next; 1736 } 1737 1738 /* restore */ 1739 temp->shortpkt = shortpkt_old; 1740 temp->len = len_old; 1741 goto restart; 1742 } 1743 1744 /* remove cycle bit from first if we are stepping the TRBs */ 1745 if (temp->step_td) 1746 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1747 1748 /* remove chain bit because this is the last TRB in the chain */ 1749 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1750 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1751 1752 usb_pc_cpu_flush(td->page_cache); 1753 1754 temp->td = td; 1755 temp->td_next = td_next; 1756 } 1757 1758 static void 1759 xhci_setup_generic_chain(struct usb_xfer *xfer) 1760 { 1761 struct xhci_std_temp temp; 1762 struct xhci_td *td; 1763 uint32_t x; 1764 uint32_t y; 1765 uint8_t mult; 1766 1767 temp.step_td = 0; 1768 temp.tbc = 0; 1769 temp.tlbpc = 0; 1770 temp.average = xfer->max_hc_frame_size; 1771 temp.max_packet_size = xfer->max_packet_size; 1772 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1773 temp.pc = NULL; 1774 temp.last_frame = 0; 1775 temp.offset = 0; 1776 temp.multishort = xfer->flags_int.isochronous_xfr || 1777 xfer->flags_int.control_xfr || 1778 xfer->flags_int.short_frames_ok; 1779 1780 /* toggle the DMA set we are using */ 1781 xfer->flags_int.curr_dma_set ^= 1; 1782 1783 /* get next DMA set */ 1784 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1785 1786 temp.td = NULL; 1787 temp.td_next = td; 1788 1789 xfer->td_transfer_first = td; 1790 xfer->td_transfer_cache = td; 1791 1792 if (xfer->flags_int.isochronous_xfr) { 1793 uint8_t shift; 1794 1795 /* compute multiplier for ISOCHRONOUS transfers */ 1796 mult = xfer->endpoint->ecomp ? 1797 (xfer->endpoint->ecomp->bmAttributes & 3) : 0; 1798 /* check for USB 2.0 multiplier */ 1799 if (mult == 0) { 1800 mult = (xfer->endpoint->edesc-> 1801 wMaxPacketSize[1] >> 3) & 3; 1802 } 1803 /* range check */ 1804 if (mult > 2) 1805 mult = 3; 1806 else 1807 mult++; 1808 1809 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 1810 1811 DPRINTF("MFINDEX=0x%08x\n", x); 1812 1813 switch (usbd_get_speed(xfer->xroot->udev)) { 1814 case USB_SPEED_FULL: 1815 shift = 3; 1816 temp.isoc_delta = 8; /* 1ms */ 1817 x += temp.isoc_delta - 1; 1818 x &= ~(temp.isoc_delta - 1); 1819 break; 1820 default: 1821 shift = usbd_xfer_get_fps_shift(xfer); 1822 temp.isoc_delta = 1U << shift; 1823 x += temp.isoc_delta - 1; 1824 x &= ~(temp.isoc_delta - 1); 1825 /* simple frame load balancing */ 1826 x += xfer->endpoint->usb_uframe; 1827 break; 1828 } 1829 1830 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 1831 1832 if ((xfer->endpoint->is_synced == 0) || 1833 (y < (xfer->nframes << shift)) || 1834 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 1835 /* 1836 * If there is data underflow or the pipe 1837 * queue is empty we schedule the transfer a 1838 * few frames ahead of the current frame 1839 * position. Else two isochronous transfers 1840 * might overlap. 1841 */ 1842 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 1843 xfer->endpoint->is_synced = 1; 1844 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1845 } 1846 1847 /* compute isochronous completion time */ 1848 1849 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 1850 1851 xfer->isoc_time_complete = 1852 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 1853 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 1854 1855 x = 0; 1856 temp.isoc_frame = xfer->endpoint->isoc_next; 1857 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 1858 1859 xfer->endpoint->isoc_next += xfer->nframes << shift; 1860 1861 } else if (xfer->flags_int.control_xfr) { 1862 1863 /* check if we should prepend a setup message */ 1864 1865 if (xfer->flags_int.control_hdr) { 1866 1867 temp.len = xfer->frlengths[0]; 1868 temp.pc = xfer->frbuffers + 0; 1869 temp.shortpkt = temp.len ? 1 : 0; 1870 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 1871 temp.direction = 0; 1872 1873 /* check for last frame */ 1874 if (xfer->nframes == 1) { 1875 /* no STATUS stage yet, SETUP is last */ 1876 if (xfer->flags_int.control_act) 1877 temp.last_frame = 1; 1878 } 1879 1880 xhci_setup_generic_chain_sub(&temp); 1881 } 1882 x = 1; 1883 mult = 1; 1884 temp.isoc_delta = 0; 1885 temp.isoc_frame = 0; 1886 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 1887 } else { 1888 x = 0; 1889 mult = 1; 1890 temp.isoc_delta = 0; 1891 temp.isoc_frame = 0; 1892 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 1893 } 1894 1895 if (x != xfer->nframes) { 1896 /* setup page_cache pointer */ 1897 temp.pc = xfer->frbuffers + x; 1898 /* set endpoint direction */ 1899 temp.direction = UE_GET_DIR(xfer->endpointno); 1900 } 1901 1902 while (x != xfer->nframes) { 1903 1904 /* DATA0 / DATA1 message */ 1905 1906 temp.len = xfer->frlengths[x]; 1907 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 1908 x != 0 && temp.multishort == 0); 1909 1910 x++; 1911 1912 if (x == xfer->nframes) { 1913 if (xfer->flags_int.control_xfr) { 1914 /* no STATUS stage yet, DATA is last */ 1915 if (xfer->flags_int.control_act) 1916 temp.last_frame = 1; 1917 } else { 1918 temp.last_frame = 1; 1919 } 1920 } 1921 if (temp.len == 0) { 1922 1923 /* make sure that we send an USB packet */ 1924 1925 temp.shortpkt = 0; 1926 1927 temp.tbc = 0; 1928 temp.tlbpc = mult - 1; 1929 1930 } else if (xfer->flags_int.isochronous_xfr) { 1931 1932 uint8_t tdpc; 1933 1934 /* isochronous transfers don't have short packet termination */ 1935 1936 temp.shortpkt = 1; 1937 1938 /* isochronous transfers have a transfer limit */ 1939 1940 if (temp.len > xfer->max_frame_size) 1941 temp.len = xfer->max_frame_size; 1942 1943 /* compute TD packet count */ 1944 tdpc = (temp.len + xfer->max_packet_size - 1) / 1945 xfer->max_packet_size; 1946 1947 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 1948 temp.tlbpc = (tdpc % mult); 1949 1950 if (temp.tlbpc == 0) 1951 temp.tlbpc = mult - 1; 1952 else 1953 temp.tlbpc--; 1954 } else { 1955 1956 /* regular data transfer */ 1957 1958 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 1959 } 1960 1961 xhci_setup_generic_chain_sub(&temp); 1962 1963 if (xfer->flags_int.isochronous_xfr) { 1964 temp.offset += xfer->frlengths[x - 1]; 1965 temp.isoc_frame += temp.isoc_delta; 1966 } else { 1967 /* get next Page Cache pointer */ 1968 temp.pc = xfer->frbuffers + x; 1969 } 1970 } 1971 1972 /* check if we should append a status stage */ 1973 1974 if (xfer->flags_int.control_xfr && 1975 !xfer->flags_int.control_act) { 1976 1977 /* 1978 * Send a DATA1 message and invert the current 1979 * endpoint direction. 1980 */ 1981 temp.step_td = (xfer->nframes != 0); 1982 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 1983 temp.len = 0; 1984 temp.pc = NULL; 1985 temp.shortpkt = 0; 1986 temp.last_frame = 1; 1987 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 1988 1989 xhci_setup_generic_chain_sub(&temp); 1990 } 1991 1992 td = temp.td; 1993 1994 /* must have at least one frame! */ 1995 1996 xfer->td_transfer_last = td; 1997 1998 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 1999 } 2000 2001 static void 2002 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2003 { 2004 struct usb_page_search buf_res; 2005 struct xhci_dev_ctx_addr *pdctxa; 2006 2007 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2008 2009 pdctxa = buf_res.buffer; 2010 2011 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2012 2013 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2014 2015 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2016 } 2017 2018 static usb_error_t 2019 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2020 { 2021 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2022 struct usb_page_search buf_inp; 2023 struct xhci_input_dev_ctx *pinp; 2024 uint8_t index; 2025 2026 index = udev->controller_slot_id; 2027 2028 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2029 2030 pinp = buf_inp.buffer; 2031 2032 if (drop) { 2033 mask &= XHCI_INCTX_NON_CTRL_MASK; 2034 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2035 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2036 } else { 2037 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2038 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2039 } 2040 return (0); 2041 } 2042 2043 static usb_error_t 2044 xhci_configure_endpoint(struct usb_device *udev, 2045 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr, 2046 uint16_t interval, uint8_t max_packet_count, uint8_t mult, 2047 uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size) 2048 { 2049 struct usb_page_search buf_inp; 2050 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2051 struct xhci_input_dev_ctx *pinp; 2052 uint32_t temp; 2053 uint8_t index; 2054 uint8_t epno; 2055 uint8_t type; 2056 2057 index = udev->controller_slot_id; 2058 2059 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2060 2061 pinp = buf_inp.buffer; 2062 2063 epno = edesc->bEndpointAddress; 2064 type = edesc->bmAttributes & UE_XFERTYPE; 2065 2066 if (type == UE_CONTROL) 2067 epno |= UE_DIR_IN; 2068 2069 epno = XHCI_EPNO2EPID(epno); 2070 2071 if (epno == 0) 2072 return (USB_ERR_NO_PIPE); /* invalid */ 2073 2074 if (max_packet_count == 0) 2075 return (USB_ERR_BAD_BUFSIZE); 2076 2077 max_packet_count--; 2078 2079 if (mult == 0) 2080 return (USB_ERR_BAD_BUFSIZE); 2081 2082 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2083 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2084 XHCI_EPCTX_0_LSA_SET(0); 2085 2086 switch (udev->speed) { 2087 case USB_SPEED_FULL: 2088 case USB_SPEED_LOW: 2089 /* 1ms -> 125us */ 2090 fps_shift += 3; 2091 break; 2092 default: 2093 break; 2094 } 2095 2096 switch (type) { 2097 case UE_INTERRUPT: 2098 if (fps_shift > 3) 2099 fps_shift--; 2100 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2101 break; 2102 case UE_ISOCHRONOUS: 2103 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2104 2105 switch (udev->speed) { 2106 case USB_SPEED_SUPER: 2107 if (mult > 3) 2108 mult = 3; 2109 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2110 max_packet_count /= mult; 2111 break; 2112 default: 2113 break; 2114 } 2115 break; 2116 default: 2117 break; 2118 } 2119 2120 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2121 2122 temp = 2123 XHCI_EPCTX_1_HID_SET(0) | 2124 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2125 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2126 2127 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2128 if (type != UE_ISOCHRONOUS) 2129 temp |= XHCI_EPCTX_1_CERR_SET(3); 2130 } 2131 2132 switch (type) { 2133 case UE_CONTROL: 2134 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2135 break; 2136 case UE_ISOCHRONOUS: 2137 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2138 break; 2139 case UE_BULK: 2140 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2141 break; 2142 default: 2143 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2144 break; 2145 } 2146 2147 /* check for IN direction */ 2148 if (epno & 1) 2149 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2150 2151 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2152 2153 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2154 2155 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2156 2157 switch (edesc->bmAttributes & UE_XFERTYPE) { 2158 case UE_INTERRUPT: 2159 case UE_ISOCHRONOUS: 2160 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2161 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2162 max_frame_size)); 2163 break; 2164 case UE_CONTROL: 2165 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2166 break; 2167 default: 2168 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2169 break; 2170 } 2171 2172 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2173 2174 #ifdef USB_DEBUG 2175 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2176 #endif 2177 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2178 2179 return (0); /* success */ 2180 } 2181 2182 static usb_error_t 2183 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2184 { 2185 struct xhci_endpoint_ext *pepext; 2186 struct usb_endpoint_ss_comp_descriptor *ecomp; 2187 2188 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2189 xfer->endpoint->edesc); 2190 2191 ecomp = xfer->endpoint->ecomp; 2192 2193 pepext->trb[0].dwTrb3 = 0; /* halt any transfers */ 2194 usb_pc_cpu_flush(pepext->page_cache); 2195 2196 return (xhci_configure_endpoint(xfer->xroot->udev, 2197 xfer->endpoint->edesc, pepext->physaddr, 2198 xfer->interval, xfer->max_packet_count, 2199 (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1, 2200 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2201 xfer->max_frame_size)); 2202 } 2203 2204 static usb_error_t 2205 xhci_configure_device(struct usb_device *udev) 2206 { 2207 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2208 struct usb_page_search buf_inp; 2209 struct usb_page_cache *pcinp; 2210 struct xhci_input_dev_ctx *pinp; 2211 struct usb_device *hubdev; 2212 uint32_t temp; 2213 uint32_t route; 2214 uint8_t is_hub; 2215 uint8_t index; 2216 uint8_t rh_port; 2217 2218 index = udev->controller_slot_id; 2219 2220 DPRINTF("index=%u\n", index); 2221 2222 pcinp = &sc->sc_hw.devs[index].input_pc; 2223 2224 usbd_get_page(pcinp, 0, &buf_inp); 2225 2226 pinp = buf_inp.buffer; 2227 2228 rh_port = 0; 2229 route = 0; 2230 2231 /* figure out route string and root HUB port number */ 2232 2233 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2234 2235 if (hubdev->parent_hub == NULL) 2236 break; 2237 2238 /* 2239 * NOTE: HS/FS/LS devices and the SS root HUB can have 2240 * more than 15 ports 2241 */ 2242 2243 rh_port = hubdev->port_no; 2244 2245 if (hubdev->parent_hub->parent_hub == NULL) 2246 break; 2247 2248 route *= 16; 2249 2250 if (rh_port > 15) 2251 route |= 15; 2252 else 2253 route |= rh_port; 2254 } 2255 2256 temp = XHCI_SCTX_0_ROUTE_SET(route); 2257 2258 switch (sc->sc_hw.devs[index].state) { 2259 case XHCI_ST_CONFIGURED: 2260 temp |= XHCI_SCTX_0_CTX_NUM_SET(XHCI_MAX_ENDPOINTS - 1); 2261 break; 2262 default: 2263 temp = XHCI_SCTX_0_CTX_NUM_SET(1); 2264 break; 2265 } 2266 2267 switch (udev->speed) { 2268 case USB_SPEED_LOW: 2269 temp |= XHCI_SCTX_0_SPEED_SET(2); 2270 break; 2271 case USB_SPEED_HIGH: 2272 temp |= XHCI_SCTX_0_SPEED_SET(3); 2273 break; 2274 case USB_SPEED_FULL: 2275 temp |= XHCI_SCTX_0_SPEED_SET(1); 2276 break; 2277 default: 2278 temp |= XHCI_SCTX_0_SPEED_SET(4); 2279 break; 2280 } 2281 2282 is_hub = sc->sc_hw.devs[index].nports != 0 && 2283 (udev->speed == USB_SPEED_SUPER || 2284 udev->speed == USB_SPEED_HIGH); 2285 2286 if (is_hub) { 2287 temp |= XHCI_SCTX_0_HUB_SET(1); 2288 #if 0 2289 if (udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2290 DPRINTF("HUB supports MTT\n"); 2291 temp |= XHCI_SCTX_0_MTT_SET(1); 2292 } 2293 #endif 2294 } 2295 2296 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2297 2298 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2299 2300 if (is_hub) { 2301 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2302 sc->sc_hw.devs[index].nports); 2303 } 2304 2305 switch (udev->speed) { 2306 case USB_SPEED_SUPER: 2307 switch (sc->sc_hw.devs[index].state) { 2308 case XHCI_ST_ADDRESSED: 2309 case XHCI_ST_CONFIGURED: 2310 /* enable power save */ 2311 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2312 break; 2313 default: 2314 /* disable power save */ 2315 break; 2316 } 2317 break; 2318 default: 2319 break; 2320 } 2321 2322 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2323 2324 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2325 2326 if (is_hub) 2327 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(sc->sc_hw.devs[index].tt); 2328 2329 hubdev = udev->parent_hs_hub; 2330 2331 /* check if we should activate the transaction translator */ 2332 switch (udev->speed) { 2333 case USB_SPEED_FULL: 2334 case USB_SPEED_LOW: 2335 if (hubdev != NULL) { 2336 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2337 hubdev->controller_slot_id); 2338 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2339 udev->hs_port_no); 2340 } 2341 break; 2342 default: 2343 break; 2344 } 2345 2346 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2347 2348 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) | 2349 XHCI_SCTX_3_SLOT_STATE_SET(0); 2350 2351 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2352 2353 #ifdef USB_DEBUG 2354 xhci_dump_device(sc, &pinp->ctx_slot); 2355 #endif 2356 usb_pc_cpu_flush(pcinp); 2357 2358 return (0); /* success */ 2359 } 2360 2361 static usb_error_t 2362 xhci_alloc_device_ext(struct usb_device *udev) 2363 { 2364 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2365 struct usb_page_search buf_dev; 2366 struct usb_page_search buf_ep; 2367 struct xhci_trb *trb; 2368 struct usb_page_cache *pc; 2369 struct usb_page *pg; 2370 uint64_t addr; 2371 uint8_t index; 2372 uint8_t i; 2373 2374 index = udev->controller_slot_id; 2375 2376 pc = &sc->sc_hw.devs[index].device_pc; 2377 pg = &sc->sc_hw.devs[index].device_pg; 2378 2379 /* need to initialize the page cache */ 2380 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2381 2382 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2383 (2 * sizeof(struct xhci_dev_ctx)) : 2384 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2385 goto error; 2386 2387 usbd_get_page(pc, 0, &buf_dev); 2388 2389 pc = &sc->sc_hw.devs[index].input_pc; 2390 pg = &sc->sc_hw.devs[index].input_pg; 2391 2392 /* need to initialize the page cache */ 2393 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2394 2395 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2396 (2 * sizeof(struct xhci_input_dev_ctx)) : 2397 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) 2398 goto error; 2399 2400 pc = &sc->sc_hw.devs[index].endpoint_pc; 2401 pg = &sc->sc_hw.devs[index].endpoint_pg; 2402 2403 /* need to initialize the page cache */ 2404 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2405 2406 if (usb_pc_alloc_mem(pc, pg, sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) 2407 goto error; 2408 2409 /* initialise all endpoint LINK TRBs */ 2410 2411 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2412 2413 /* lookup endpoint TRB ring */ 2414 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2415 2416 /* get TRB pointer */ 2417 trb = buf_ep.buffer; 2418 trb += XHCI_MAX_TRANSFERS - 1; 2419 2420 /* get TRB start address */ 2421 addr = buf_ep.physaddr; 2422 2423 /* create LINK TRB */ 2424 trb->qwTrb0 = htole64(addr); 2425 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2426 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2427 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2428 } 2429 2430 usb_pc_cpu_flush(pc); 2431 2432 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2433 2434 return (0); 2435 2436 error: 2437 xhci_free_device_ext(udev); 2438 2439 return (USB_ERR_NOMEM); 2440 } 2441 2442 static void 2443 xhci_free_device_ext(struct usb_device *udev) 2444 { 2445 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2446 uint8_t index; 2447 2448 index = udev->controller_slot_id; 2449 xhci_set_slot_pointer(sc, index, 0); 2450 2451 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2452 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2453 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2454 } 2455 2456 static struct xhci_endpoint_ext * 2457 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2458 { 2459 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2460 struct xhci_endpoint_ext *pepext; 2461 struct usb_page_cache *pc; 2462 struct usb_page_search buf_ep; 2463 uint8_t epno; 2464 uint8_t index; 2465 2466 epno = edesc->bEndpointAddress; 2467 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2468 epno |= UE_DIR_IN; 2469 2470 epno = XHCI_EPNO2EPID(epno); 2471 2472 index = udev->controller_slot_id; 2473 2474 pc = &sc->sc_hw.devs[index].endpoint_pc; 2475 2476 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep); 2477 2478 pepext = &sc->sc_hw.devs[index].endp[epno]; 2479 pepext->page_cache = pc; 2480 pepext->trb = buf_ep.buffer; 2481 pepext->physaddr = buf_ep.physaddr; 2482 2483 return (pepext); 2484 } 2485 2486 static void 2487 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2488 { 2489 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2490 uint8_t epno; 2491 uint8_t index; 2492 2493 epno = xfer->endpointno; 2494 if (xfer->flags_int.control_xfr) 2495 epno |= UE_DIR_IN; 2496 2497 epno = XHCI_EPNO2EPID(epno); 2498 index = xfer->xroot->udev->controller_slot_id; 2499 2500 if (xfer->xroot->udev->flags.self_suspended == 0) 2501 XWRITE4(sc, door, XHCI_DOORBELL(index), epno | XHCI_DB_SID_SET(0)); 2502 } 2503 2504 static void 2505 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2506 { 2507 struct xhci_endpoint_ext *pepext; 2508 2509 if (xfer->flags_int.bandwidth_reclaimed) { 2510 xfer->flags_int.bandwidth_reclaimed = 0; 2511 2512 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2513 xfer->endpoint->edesc); 2514 2515 pepext->trb_used--; 2516 2517 pepext->xfer[xfer->qh_pos] = NULL; 2518 2519 if (error && pepext->trb_running != 0) { 2520 pepext->trb_halted = 1; 2521 pepext->trb_running = 0; 2522 } 2523 } 2524 } 2525 2526 static usb_error_t 2527 xhci_transfer_insert(struct usb_xfer *xfer) 2528 { 2529 struct xhci_td *td_first; 2530 struct xhci_td *td_last; 2531 struct xhci_endpoint_ext *pepext; 2532 uint64_t addr; 2533 uint8_t i; 2534 uint8_t inext; 2535 uint8_t trb_limit; 2536 2537 DPRINTFN(8, "\n"); 2538 2539 /* check if already inserted */ 2540 if (xfer->flags_int.bandwidth_reclaimed) { 2541 DPRINTFN(8, "Already in schedule\n"); 2542 return (0); 2543 } 2544 2545 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2546 xfer->endpoint->edesc); 2547 2548 td_first = xfer->td_transfer_first; 2549 td_last = xfer->td_transfer_last; 2550 addr = pepext->physaddr; 2551 2552 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2553 case UE_CONTROL: 2554 case UE_INTERRUPT: 2555 /* single buffered */ 2556 trb_limit = 1; 2557 break; 2558 default: 2559 /* multi buffered */ 2560 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2561 break; 2562 } 2563 2564 if (pepext->trb_used >= trb_limit) { 2565 DPRINTFN(8, "Too many TDs queued.\n"); 2566 return (USB_ERR_NOMEM); 2567 } 2568 2569 /* check for stopped condition, after putting transfer on interrupt queue */ 2570 if (pepext->trb_running == 0) { 2571 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2572 2573 DPRINTFN(8, "Not running\n"); 2574 2575 /* start configuration */ 2576 (void)usb_proc_msignal(&sc->sc_config_proc, 2577 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2578 return (0); 2579 } 2580 2581 pepext->trb_used++; 2582 2583 /* get current TRB index */ 2584 i = pepext->trb_index; 2585 2586 /* get next TRB index */ 2587 inext = (i + 1); 2588 2589 /* the last entry of the ring is a hardcoded link TRB */ 2590 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2591 inext = 0; 2592 2593 /* compute terminating return address */ 2594 addr += inext * sizeof(struct xhci_trb); 2595 2596 /* update next pointer of last link TRB */ 2597 td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr); 2598 td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2599 td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2600 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2601 2602 #ifdef USB_DEBUG 2603 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2604 #endif 2605 usb_pc_cpu_flush(td_last->page_cache); 2606 2607 /* write ahead chain end marker */ 2608 2609 pepext->trb[inext].qwTrb0 = 0; 2610 pepext->trb[inext].dwTrb2 = 0; 2611 pepext->trb[inext].dwTrb3 = 0; 2612 2613 /* update next pointer of link TRB */ 2614 2615 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2616 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2617 2618 #ifdef USB_DEBUG 2619 xhci_dump_trb(&pepext->trb[i]); 2620 #endif 2621 usb_pc_cpu_flush(pepext->page_cache); 2622 2623 /* toggle cycle bit which activates the transfer chain */ 2624 2625 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2626 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2627 2628 usb_pc_cpu_flush(pepext->page_cache); 2629 2630 DPRINTF("qh_pos = %u\n", i); 2631 2632 pepext->xfer[i] = xfer; 2633 2634 xfer->qh_pos = i; 2635 2636 xfer->flags_int.bandwidth_reclaimed = 1; 2637 2638 pepext->trb_index = inext; 2639 2640 xhci_endpoint_doorbell(xfer); 2641 2642 return (0); 2643 } 2644 2645 static void 2646 xhci_root_intr(struct xhci_softc *sc) 2647 { 2648 uint16_t i; 2649 2650 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2651 2652 /* clear any old interrupt data */ 2653 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2654 2655 for (i = 1; i <= sc->sc_noport; i++) { 2656 /* pick out CHANGE bits from the status register */ 2657 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2658 XHCI_PS_CSC | XHCI_PS_PEC | 2659 XHCI_PS_OCC | XHCI_PS_WRC | 2660 XHCI_PS_PRC | XHCI_PS_PLC | 2661 XHCI_PS_CEC)) { 2662 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2663 DPRINTF("port %d changed\n", i); 2664 } 2665 } 2666 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2667 sizeof(sc->sc_hub_idata)); 2668 } 2669 2670 /*------------------------------------------------------------------------* 2671 * xhci_device_done - XHCI done handler 2672 * 2673 * NOTE: This function can be called two times in a row on 2674 * the same USB transfer. From close and from interrupt. 2675 *------------------------------------------------------------------------*/ 2676 static void 2677 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2678 { 2679 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2680 xfer, xfer->endpoint, error); 2681 2682 /* remove transfer from HW queue */ 2683 xhci_transfer_remove(xfer, error); 2684 2685 /* dequeue transfer and start next transfer */ 2686 usbd_transfer_done(xfer, error); 2687 } 2688 2689 /*------------------------------------------------------------------------* 2690 * XHCI data transfer support (generic type) 2691 *------------------------------------------------------------------------*/ 2692 static void 2693 xhci_device_generic_open(struct usb_xfer *xfer) 2694 { 2695 if (xfer->flags_int.isochronous_xfr) { 2696 switch (xfer->xroot->udev->speed) { 2697 case USB_SPEED_FULL: 2698 break; 2699 default: 2700 usb_hs_bandwidth_alloc(xfer); 2701 break; 2702 } 2703 } 2704 } 2705 2706 static void 2707 xhci_device_generic_close(struct usb_xfer *xfer) 2708 { 2709 DPRINTF("\n"); 2710 2711 xhci_device_done(xfer, USB_ERR_CANCELLED); 2712 2713 if (xfer->flags_int.isochronous_xfr) { 2714 switch (xfer->xroot->udev->speed) { 2715 case USB_SPEED_FULL: 2716 break; 2717 default: 2718 usb_hs_bandwidth_free(xfer); 2719 break; 2720 } 2721 } 2722 } 2723 2724 static void 2725 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 2726 struct usb_xfer *enter_xfer) 2727 { 2728 struct usb_xfer *xfer; 2729 2730 /* check if there is a current transfer */ 2731 xfer = ep->endpoint_q.curr; 2732 if (xfer == NULL) 2733 return; 2734 2735 /* 2736 * Check if the current transfer is started and then pickup 2737 * the next one, if any. Else wait for next start event due to 2738 * block on failure feature. 2739 */ 2740 if (!xfer->flags_int.bandwidth_reclaimed) 2741 return; 2742 2743 xfer = TAILQ_FIRST(&ep->endpoint_q.head); 2744 if (xfer == NULL) { 2745 /* 2746 * In case of enter we have to consider that the 2747 * transfer is queued by the USB core after the enter 2748 * method is called. 2749 */ 2750 xfer = enter_xfer; 2751 2752 if (xfer == NULL) 2753 return; 2754 } 2755 2756 /* try to multi buffer */ 2757 xhci_transfer_insert(xfer); 2758 } 2759 2760 static void 2761 xhci_device_generic_enter(struct usb_xfer *xfer) 2762 { 2763 DPRINTF("\n"); 2764 2765 /* setup TD's and QH */ 2766 xhci_setup_generic_chain(xfer); 2767 2768 xhci_device_generic_multi_enter(xfer->endpoint, xfer); 2769 } 2770 2771 static void 2772 xhci_device_generic_start(struct usb_xfer *xfer) 2773 { 2774 DPRINTF("\n"); 2775 2776 /* try to insert xfer on HW queue */ 2777 xhci_transfer_insert(xfer); 2778 2779 /* try to multi buffer */ 2780 xhci_device_generic_multi_enter(xfer->endpoint, NULL); 2781 2782 /* add transfer last on interrupt queue */ 2783 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2784 2785 /* start timeout, if any */ 2786 if (xfer->timeout != 0) 2787 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 2788 } 2789 2790 struct usb_pipe_methods xhci_device_generic_methods = 2791 { 2792 .open = xhci_device_generic_open, 2793 .close = xhci_device_generic_close, 2794 .enter = xhci_device_generic_enter, 2795 .start = xhci_device_generic_start, 2796 }; 2797 2798 /*------------------------------------------------------------------------* 2799 * xhci root HUB support 2800 *------------------------------------------------------------------------* 2801 * Simulate a hardware HUB by handling all the necessary requests. 2802 *------------------------------------------------------------------------*/ 2803 2804 #define HSETW(ptr, val) ptr[0] = (uint8_t)(val), ptr[1] = (uint8_t)((val) >> 8) 2805 2806 static const 2807 struct usb_device_descriptor xhci_devd = 2808 { 2809 .bLength = sizeof(xhci_devd), 2810 .bDescriptorType = UDESC_DEVICE, /* type */ 2811 HSETW(.bcdUSB, 0x0300), /* USB version */ 2812 .bDeviceClass = UDCLASS_HUB, /* class */ 2813 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 2814 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 2815 .bMaxPacketSize = 9, /* max packet size */ 2816 HSETW(.idVendor, 0x0000), /* vendor */ 2817 HSETW(.idProduct, 0x0000), /* product */ 2818 HSETW(.bcdDevice, 0x0100), /* device version */ 2819 .iManufacturer = 1, 2820 .iProduct = 2, 2821 .iSerialNumber = 0, 2822 .bNumConfigurations = 1, /* # of configurations */ 2823 }; 2824 2825 static const 2826 struct xhci_bos_desc xhci_bosd = { 2827 .bosd = { 2828 .bLength = sizeof(xhci_bosd.bosd), 2829 .bDescriptorType = UDESC_BOS, 2830 HSETW(.wTotalLength, sizeof(xhci_bosd)), 2831 .bNumDeviceCaps = 3, 2832 }, 2833 .usb2extd = { 2834 .bLength = sizeof(xhci_bosd.usb2extd), 2835 .bDescriptorType = 1, 2836 .bDevCapabilityType = 2, 2837 .bmAttributes[0] = 2, 2838 }, 2839 .usbdcd = { 2840 .bLength = sizeof(xhci_bosd.usbdcd), 2841 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 2842 .bDevCapabilityType = 3, 2843 .bmAttributes = 0, /* XXX */ 2844 HSETW(.wSpeedsSupported, 0x000C), 2845 .bFunctionalitySupport = 8, 2846 .bU1DevExitLat = 255, /* dummy - not used */ 2847 .wU2DevExitLat[0] = 0x00, 2848 .wU2DevExitLat[1] = 0x08, 2849 }, 2850 .cidd = { 2851 .bLength = sizeof(xhci_bosd.cidd), 2852 .bDescriptorType = 1, 2853 .bDevCapabilityType = 4, 2854 .bReserved = 0, 2855 .bContainerID = 0, /* XXX */ 2856 }, 2857 }; 2858 2859 static const 2860 struct xhci_config_desc xhci_confd = { 2861 .confd = { 2862 .bLength = sizeof(xhci_confd.confd), 2863 .bDescriptorType = UDESC_CONFIG, 2864 .wTotalLength[0] = sizeof(xhci_confd), 2865 .bNumInterface = 1, 2866 .bConfigurationValue = 1, 2867 .iConfiguration = 0, 2868 .bmAttributes = UC_SELF_POWERED, 2869 .bMaxPower = 0 /* max power */ 2870 }, 2871 .ifcd = { 2872 .bLength = sizeof(xhci_confd.ifcd), 2873 .bDescriptorType = UDESC_INTERFACE, 2874 .bNumEndpoints = 1, 2875 .bInterfaceClass = UICLASS_HUB, 2876 .bInterfaceSubClass = UISUBCLASS_HUB, 2877 .bInterfaceProtocol = 0, 2878 }, 2879 .endpd = { 2880 .bLength = sizeof(xhci_confd.endpd), 2881 .bDescriptorType = UDESC_ENDPOINT, 2882 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 2883 .bmAttributes = UE_INTERRUPT, 2884 .wMaxPacketSize[0] = 2, /* max 15 ports */ 2885 .bInterval = 255, 2886 }, 2887 .endpcd = { 2888 .bLength = sizeof(xhci_confd.endpcd), 2889 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 2890 .bMaxBurst = 0, 2891 .bmAttributes = 0, 2892 }, 2893 }; 2894 2895 static const 2896 struct usb_hub_ss_descriptor xhci_hubd = { 2897 .bLength = sizeof(xhci_hubd), 2898 .bDescriptorType = UDESC_SS_HUB, 2899 }; 2900 2901 static usb_error_t 2902 xhci_roothub_exec(struct usb_device *udev, 2903 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2904 { 2905 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2906 const char *str_ptr; 2907 const void *ptr; 2908 uint32_t port; 2909 uint32_t v; 2910 uint16_t len; 2911 uint16_t i; 2912 uint16_t value; 2913 uint16_t index; 2914 uint8_t j; 2915 usb_error_t err; 2916 2917 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2918 2919 /* buffer reset */ 2920 ptr = (const void *)&sc->sc_hub_desc; 2921 len = 0; 2922 err = 0; 2923 2924 value = UGETW(req->wValue); 2925 index = UGETW(req->wIndex); 2926 2927 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2928 "wValue=0x%04x wIndex=0x%04x\n", 2929 req->bmRequestType, req->bRequest, 2930 UGETW(req->wLength), value, index); 2931 2932 #define C(x,y) ((x) | ((y) << 8)) 2933 switch (C(req->bRequest, req->bmRequestType)) { 2934 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2935 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2936 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2937 /* 2938 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2939 * for the integrated root hub. 2940 */ 2941 break; 2942 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2943 len = 1; 2944 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2945 break; 2946 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2947 switch (value >> 8) { 2948 case UDESC_DEVICE: 2949 if ((value & 0xff) != 0) { 2950 err = USB_ERR_IOERROR; 2951 goto done; 2952 } 2953 len = sizeof(xhci_devd); 2954 ptr = (const void *)&xhci_devd; 2955 break; 2956 2957 case UDESC_BOS: 2958 if ((value & 0xff) != 0) { 2959 err = USB_ERR_IOERROR; 2960 goto done; 2961 } 2962 len = sizeof(xhci_bosd); 2963 ptr = (const void *)&xhci_bosd; 2964 break; 2965 2966 case UDESC_CONFIG: 2967 if ((value & 0xff) != 0) { 2968 err = USB_ERR_IOERROR; 2969 goto done; 2970 } 2971 len = sizeof(xhci_confd); 2972 ptr = (const void *)&xhci_confd; 2973 break; 2974 2975 case UDESC_STRING: 2976 switch (value & 0xff) { 2977 case 0: /* Language table */ 2978 str_ptr = "\001"; 2979 break; 2980 2981 case 1: /* Vendor */ 2982 str_ptr = sc->sc_vendor; 2983 break; 2984 2985 case 2: /* Product */ 2986 str_ptr = "XHCI root HUB"; 2987 break; 2988 2989 default: 2990 str_ptr = ""; 2991 break; 2992 } 2993 2994 len = usb_make_str_desc( 2995 sc->sc_hub_desc.temp, 2996 sizeof(sc->sc_hub_desc.temp), 2997 str_ptr); 2998 break; 2999 3000 default: 3001 err = USB_ERR_IOERROR; 3002 goto done; 3003 } 3004 break; 3005 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3006 len = 1; 3007 sc->sc_hub_desc.temp[0] = 0; 3008 break; 3009 case C(UR_GET_STATUS, UT_READ_DEVICE): 3010 len = 2; 3011 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3012 break; 3013 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3014 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3015 len = 2; 3016 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3017 break; 3018 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3019 if (value >= XHCI_MAX_DEVICES) { 3020 err = USB_ERR_IOERROR; 3021 goto done; 3022 } 3023 break; 3024 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3025 if (value != 0 && value != 1) { 3026 err = USB_ERR_IOERROR; 3027 goto done; 3028 } 3029 sc->sc_conf = value; 3030 break; 3031 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3032 break; 3033 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3034 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3035 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3036 err = USB_ERR_IOERROR; 3037 goto done; 3038 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3039 break; 3040 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3041 break; 3042 /* Hub requests */ 3043 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3044 break; 3045 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3046 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3047 3048 if ((index < 1) || 3049 (index > sc->sc_noport)) { 3050 err = USB_ERR_IOERROR; 3051 goto done; 3052 } 3053 port = XHCI_PORTSC(index); 3054 3055 v = XREAD4(sc, oper, port); 3056 i = XHCI_PS_PLS_GET(v); 3057 v &= ~XHCI_PS_CLEAR; 3058 3059 switch (value) { 3060 case UHF_C_BH_PORT_RESET: 3061 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3062 break; 3063 case UHF_C_PORT_CONFIG_ERROR: 3064 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3065 break; 3066 case UHF_C_PORT_LINK_STATE: 3067 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3068 break; 3069 case UHF_C_PORT_CONNECTION: 3070 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3071 break; 3072 case UHF_C_PORT_ENABLE: 3073 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3074 break; 3075 case UHF_C_PORT_OVER_CURRENT: 3076 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3077 break; 3078 case UHF_C_PORT_RESET: 3079 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3080 break; 3081 case UHF_PORT_ENABLE: 3082 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3083 break; 3084 case UHF_PORT_POWER: 3085 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3086 break; 3087 case UHF_PORT_INDICATOR: 3088 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3089 break; 3090 case UHF_PORT_SUSPEND: 3091 3092 /* U3 -> U15 */ 3093 if (i == 3) { 3094 XWRITE4(sc, oper, port, v | 3095 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3096 } 3097 3098 /* wait 20ms for resume sequence to complete */ 3099 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3100 3101 /* U0 */ 3102 XWRITE4(sc, oper, port, v | 3103 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3104 break; 3105 default: 3106 err = USB_ERR_IOERROR; 3107 goto done; 3108 } 3109 break; 3110 3111 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3112 if ((value & 0xff) != 0) { 3113 err = USB_ERR_IOERROR; 3114 goto done; 3115 } 3116 3117 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3118 3119 sc->sc_hub_desc.hubd = xhci_hubd; 3120 3121 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3122 3123 if (XHCI_HCS0_PPC(v)) 3124 i = UHD_PWR_INDIVIDUAL; 3125 else 3126 i = UHD_PWR_GANGED; 3127 3128 if (XHCI_HCS0_PIND(v)) 3129 i |= UHD_PORT_IND; 3130 3131 i |= UHD_OC_INDIVIDUAL; 3132 3133 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3134 3135 /* see XHCI section 5.4.9: */ 3136 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3137 3138 for (j = 1; j <= sc->sc_noport; j++) { 3139 3140 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3141 if (v & XHCI_PS_DR) { 3142 sc->sc_hub_desc.hubd. 3143 DeviceRemovable[j / 8] |= 1U << (j % 8); 3144 } 3145 } 3146 len = sc->sc_hub_desc.hubd.bLength; 3147 break; 3148 3149 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3150 len = 16; 3151 memset(sc->sc_hub_desc.temp, 0, 16); 3152 break; 3153 3154 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3155 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3156 3157 if ((index < 1) || 3158 (index > sc->sc_noport)) { 3159 err = USB_ERR_IOERROR; 3160 goto done; 3161 } 3162 3163 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3164 3165 DPRINTFN(9, "port status=0x%08x\n", v); 3166 3167 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3168 3169 switch (XHCI_PS_SPEED_GET(v)) { 3170 case 3: 3171 i |= UPS_HIGH_SPEED; 3172 break; 3173 case 2: 3174 i |= UPS_LOW_SPEED; 3175 break; 3176 case 1: 3177 /* FULL speed */ 3178 break; 3179 default: 3180 i |= UPS_OTHER_SPEED; 3181 break; 3182 } 3183 3184 if (v & XHCI_PS_CCS) 3185 i |= UPS_CURRENT_CONNECT_STATUS; 3186 if (v & XHCI_PS_PED) 3187 i |= UPS_PORT_ENABLED; 3188 if (v & XHCI_PS_OCA) 3189 i |= UPS_OVERCURRENT_INDICATOR; 3190 if (v & XHCI_PS_PR) 3191 i |= UPS_RESET; 3192 if (v & XHCI_PS_PP) 3193 i |= UPS_PORT_POWER; 3194 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3195 3196 i = 0; 3197 if (v & XHCI_PS_CSC) 3198 i |= UPS_C_CONNECT_STATUS; 3199 if (v & XHCI_PS_PEC) 3200 i |= UPS_C_PORT_ENABLED; 3201 if (v & XHCI_PS_OCC) 3202 i |= UPS_C_OVERCURRENT_INDICATOR; 3203 if (v & XHCI_PS_WRC) 3204 i |= UPS_C_BH_PORT_RESET; 3205 if (v & XHCI_PS_PRC) 3206 i |= UPS_C_PORT_RESET; 3207 if (v & XHCI_PS_PLC) 3208 i |= UPS_C_PORT_LINK_STATE; 3209 if (v & XHCI_PS_CEC) 3210 i |= UPS_C_PORT_CONFIG_ERROR; 3211 3212 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3213 len = sizeof(sc->sc_hub_desc.ps); 3214 break; 3215 3216 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3217 err = USB_ERR_IOERROR; 3218 goto done; 3219 3220 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3221 break; 3222 3223 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3224 3225 i = index >> 8; 3226 index &= 0x00FF; 3227 3228 if ((index < 1) || 3229 (index > sc->sc_noport)) { 3230 err = USB_ERR_IOERROR; 3231 goto done; 3232 } 3233 3234 port = XHCI_PORTSC(index); 3235 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3236 3237 switch (value) { 3238 case UHF_PORT_U1_TIMEOUT: 3239 if (XHCI_PS_SPEED_GET(v) != 4) { 3240 err = USB_ERR_IOERROR; 3241 goto done; 3242 } 3243 port = XHCI_PORTPMSC(index); 3244 v = XREAD4(sc, oper, port); 3245 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3246 v |= XHCI_PM3_U1TO_SET(i); 3247 XWRITE4(sc, oper, port, v); 3248 break; 3249 case UHF_PORT_U2_TIMEOUT: 3250 if (XHCI_PS_SPEED_GET(v) != 4) { 3251 err = USB_ERR_IOERROR; 3252 goto done; 3253 } 3254 port = XHCI_PORTPMSC(index); 3255 v = XREAD4(sc, oper, port); 3256 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3257 v |= XHCI_PM3_U2TO_SET(i); 3258 XWRITE4(sc, oper, port, v); 3259 break; 3260 case UHF_BH_PORT_RESET: 3261 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3262 break; 3263 case UHF_PORT_LINK_STATE: 3264 XWRITE4(sc, oper, port, v | 3265 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3266 /* 4ms settle time */ 3267 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3268 break; 3269 case UHF_PORT_ENABLE: 3270 DPRINTFN(3, "set port enable %d\n", index); 3271 break; 3272 case UHF_PORT_SUSPEND: 3273 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3274 j = XHCI_PS_SPEED_GET(v); 3275 if ((j < 1) || (j > 3)) { 3276 /* non-supported speed */ 3277 err = USB_ERR_IOERROR; 3278 goto done; 3279 } 3280 XWRITE4(sc, oper, port, v | 3281 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3282 break; 3283 case UHF_PORT_RESET: 3284 DPRINTFN(6, "reset port %d\n", index); 3285 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3286 break; 3287 case UHF_PORT_POWER: 3288 DPRINTFN(3, "set port power %d\n", index); 3289 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3290 break; 3291 case UHF_PORT_TEST: 3292 DPRINTFN(3, "set port test %d\n", index); 3293 break; 3294 case UHF_PORT_INDICATOR: 3295 DPRINTFN(3, "set port indicator %d\n", index); 3296 3297 v &= ~XHCI_PS_PIC_SET(3); 3298 v |= XHCI_PS_PIC_SET(1); 3299 3300 XWRITE4(sc, oper, port, v); 3301 break; 3302 default: 3303 err = USB_ERR_IOERROR; 3304 goto done; 3305 } 3306 break; 3307 3308 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3309 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3310 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3311 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3312 break; 3313 default: 3314 err = USB_ERR_IOERROR; 3315 goto done; 3316 } 3317 done: 3318 *plength = len; 3319 *pptr = ptr; 3320 return (err); 3321 } 3322 3323 static void 3324 xhci_xfer_setup(struct usb_setup_params *parm) 3325 { 3326 struct usb_page_search page_info; 3327 struct usb_page_cache *pc; 3328 struct xhci_softc *sc; 3329 struct usb_xfer *xfer; 3330 void *last_obj; 3331 uint32_t ntd; 3332 uint32_t n; 3333 3334 sc = XHCI_BUS2SC(parm->udev->bus); 3335 xfer = parm->curr_xfer; 3336 3337 /* 3338 * The proof for the "ntd" formula is illustrated like this: 3339 * 3340 * +------------------------------------+ 3341 * | | 3342 * | |remainder -> | 3343 * | +-----+---+ | 3344 * | | xxx | x | frm 0 | 3345 * | +-----+---++ | 3346 * | | xxx | xx | frm 1 | 3347 * | +-----+----+ | 3348 * | ... | 3349 * +------------------------------------+ 3350 * 3351 * "xxx" means a completely full USB transfer descriptor 3352 * 3353 * "x" and "xx" means a short USB packet 3354 * 3355 * For the remainder of an USB transfer modulo 3356 * "max_data_length" we need two USB transfer descriptors. 3357 * One to transfer the remaining data and one to finalise with 3358 * a zero length packet in case the "force_short_xfer" flag is 3359 * set. We only need two USB transfer descriptors in the case 3360 * where the transfer length of the first one is a factor of 3361 * "max_frame_size". The rest of the needed USB transfer 3362 * descriptors is given by the buffer size divided by the 3363 * maximum data payload. 3364 */ 3365 parm->hc_max_packet_size = 0x400; 3366 parm->hc_max_packet_count = 16 * 3; 3367 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3368 3369 xfer->flags_int.bdma_enable = 1; 3370 3371 usbd_transfer_setup_sub(parm); 3372 3373 if (xfer->flags_int.isochronous_xfr) { 3374 ntd = ((1 * xfer->nframes) 3375 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3376 } else if (xfer->flags_int.control_xfr) { 3377 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3378 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3379 } else { 3380 ntd = ((2 * xfer->nframes) 3381 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3382 } 3383 3384 alloc_dma_set: 3385 3386 if (parm->err) 3387 return; 3388 3389 /* 3390 * Allocate queue heads and transfer descriptors 3391 */ 3392 last_obj = NULL; 3393 3394 if (usbd_transfer_setup_sub_malloc( 3395 parm, &pc, sizeof(struct xhci_td), 3396 XHCI_TD_ALIGN, ntd)) { 3397 parm->err = USB_ERR_NOMEM; 3398 return; 3399 } 3400 if (parm->buf) { 3401 for (n = 0; n != ntd; n++) { 3402 struct xhci_td *td; 3403 3404 usbd_get_page(pc + n, 0, &page_info); 3405 3406 td = page_info.buffer; 3407 3408 /* init TD */ 3409 td->td_self = page_info.physaddr; 3410 td->obj_next = last_obj; 3411 td->page_cache = pc + n; 3412 3413 last_obj = td; 3414 3415 usb_pc_cpu_flush(pc + n); 3416 } 3417 } 3418 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3419 3420 if (!xfer->flags_int.curr_dma_set) { 3421 xfer->flags_int.curr_dma_set = 1; 3422 goto alloc_dma_set; 3423 } 3424 } 3425 3426 static usb_error_t 3427 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3428 { 3429 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3430 struct usb_page_search buf_inp; 3431 struct usb_device *udev; 3432 struct xhci_endpoint_ext *pepext; 3433 struct usb_endpoint_descriptor *edesc; 3434 struct usb_page_cache *pcinp; 3435 usb_error_t err; 3436 uint8_t index; 3437 uint8_t epno; 3438 3439 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3440 xfer->endpoint->edesc); 3441 3442 udev = xfer->xroot->udev; 3443 index = udev->controller_slot_id; 3444 3445 pcinp = &sc->sc_hw.devs[index].input_pc; 3446 3447 usbd_get_page(pcinp, 0, &buf_inp); 3448 3449 edesc = xfer->endpoint->edesc; 3450 3451 epno = edesc->bEndpointAddress; 3452 3453 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3454 epno |= UE_DIR_IN; 3455 3456 epno = XHCI_EPNO2EPID(epno); 3457 3458 if (epno == 0) 3459 return (USB_ERR_NO_PIPE); /* invalid */ 3460 3461 XHCI_CMD_LOCK(sc); 3462 3463 /* configure endpoint */ 3464 3465 err = xhci_configure_endpoint_by_xfer(xfer); 3466 3467 if (err != 0) { 3468 XHCI_CMD_UNLOCK(sc); 3469 return (err); 3470 } 3471 3472 /* 3473 * Get the endpoint into the stopped state according to the 3474 * endpoint context state diagram in the XHCI specification: 3475 */ 3476 3477 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3478 3479 if (err != 0) 3480 DPRINTF("Could not stop endpoint %u\n", epno); 3481 3482 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3483 3484 if (err != 0) 3485 DPRINTF("Could not reset endpoint %u\n", epno); 3486 3487 err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr | 3488 XHCI_EPCTX_2_DCS_SET(1), 0, epno, index); 3489 3490 if (err != 0) 3491 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3492 3493 /* 3494 * Get the endpoint into the running state according to the 3495 * endpoint context state diagram in the XHCI specification: 3496 */ 3497 3498 xhci_configure_mask(udev, 1U << epno, 0); 3499 3500 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3501 3502 if (err != 0) 3503 DPRINTF("Could not configure endpoint %u\n", epno); 3504 3505 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3506 3507 if (err != 0) 3508 DPRINTF("Could not configure endpoint %u\n", epno); 3509 3510 XHCI_CMD_UNLOCK(sc); 3511 3512 return (0); 3513 } 3514 3515 static void 3516 xhci_xfer_unsetup(struct usb_xfer *xfer) 3517 { 3518 return; 3519 } 3520 3521 static void 3522 xhci_start_dma_delay(struct usb_xfer *xfer) 3523 { 3524 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3525 3526 /* put transfer on interrupt queue (again) */ 3527 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3528 3529 (void)usb_proc_msignal(&sc->sc_config_proc, 3530 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3531 } 3532 3533 static void 3534 xhci_configure_msg(struct usb_proc_msg *pm) 3535 { 3536 struct xhci_softc *sc; 3537 struct xhci_endpoint_ext *pepext; 3538 struct usb_xfer *xfer; 3539 3540 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3541 3542 restart: 3543 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3544 3545 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3546 xfer->endpoint->edesc); 3547 3548 if ((pepext->trb_halted != 0) || 3549 (pepext->trb_running == 0)) { 3550 3551 uint8_t i; 3552 3553 /* clear halted and running */ 3554 pepext->trb_halted = 0; 3555 pepext->trb_running = 0; 3556 3557 /* nuke remaining buffered transfers */ 3558 3559 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 3560 /* 3561 * NOTE: We need to use the timeout 3562 * error code here else existing 3563 * isochronous clients can get 3564 * confused: 3565 */ 3566 if (pepext->xfer[i] != NULL) { 3567 xhci_device_done(pepext->xfer[i], 3568 USB_ERR_TIMEOUT); 3569 } 3570 } 3571 3572 /* 3573 * NOTE: The USB transfer cannot vanish in 3574 * this state! 3575 */ 3576 3577 USB_BUS_UNLOCK(&sc->sc_bus); 3578 3579 xhci_configure_reset_endpoint(xfer); 3580 3581 USB_BUS_LOCK(&sc->sc_bus); 3582 3583 /* check if halted is still cleared */ 3584 if (pepext->trb_halted == 0) { 3585 pepext->trb_running = 1; 3586 pepext->trb_index = 0; 3587 } 3588 goto restart; 3589 } 3590 3591 if (xfer->flags_int.did_dma_delay) { 3592 3593 /* remove transfer from interrupt queue (again) */ 3594 usbd_transfer_dequeue(xfer); 3595 3596 /* we are finally done */ 3597 usb_dma_delay_done_cb(xfer); 3598 3599 /* queue changed - restart */ 3600 goto restart; 3601 } 3602 } 3603 3604 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3605 3606 /* try to insert xfer on HW queue */ 3607 xhci_transfer_insert(xfer); 3608 3609 /* try to multi buffer */ 3610 xhci_device_generic_multi_enter(xfer->endpoint, NULL); 3611 } 3612 } 3613 3614 static void 3615 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3616 struct usb_endpoint *ep) 3617 { 3618 struct xhci_endpoint_ext *pepext; 3619 3620 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3621 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3622 3623 if (udev->flags.usb_mode != USB_MODE_HOST) { 3624 /* not supported */ 3625 return; 3626 } 3627 if (udev->parent_hub == NULL) { 3628 /* root HUB has special endpoint handling */ 3629 return; 3630 } 3631 3632 ep->methods = &xhci_device_generic_methods; 3633 3634 pepext = xhci_get_endpoint_ext(udev, edesc); 3635 3636 USB_BUS_LOCK(udev->bus); 3637 pepext->trb_halted = 1; 3638 pepext->trb_running = 0; 3639 USB_BUS_UNLOCK(udev->bus); 3640 } 3641 3642 static void 3643 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3644 { 3645 3646 } 3647 3648 static void 3649 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3650 { 3651 struct xhci_endpoint_ext *pepext; 3652 3653 DPRINTF("\n"); 3654 3655 if (udev->flags.usb_mode != USB_MODE_HOST) { 3656 /* not supported */ 3657 return; 3658 } 3659 if (udev->parent_hub == NULL) { 3660 /* root HUB has special endpoint handling */ 3661 return; 3662 } 3663 3664 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3665 3666 USB_BUS_LOCK(udev->bus); 3667 pepext->trb_halted = 1; 3668 pepext->trb_running = 0; 3669 USB_BUS_UNLOCK(udev->bus); 3670 } 3671 3672 static usb_error_t 3673 xhci_device_init(struct usb_device *udev) 3674 { 3675 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3676 usb_error_t err; 3677 uint8_t temp; 3678 3679 /* no init for root HUB */ 3680 if (udev->parent_hub == NULL) 3681 return (0); 3682 3683 XHCI_CMD_LOCK(sc); 3684 3685 /* set invalid default */ 3686 3687 udev->controller_slot_id = sc->sc_noslot + 1; 3688 3689 /* try to get a new slot ID from the XHCI */ 3690 3691 err = xhci_cmd_enable_slot(sc, &temp); 3692 3693 if (err) { 3694 XHCI_CMD_UNLOCK(sc); 3695 return (err); 3696 } 3697 3698 if (temp > sc->sc_noslot) { 3699 XHCI_CMD_UNLOCK(sc); 3700 return (USB_ERR_BAD_ADDRESS); 3701 } 3702 3703 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 3704 DPRINTF("slot %u already allocated.\n", temp); 3705 XHCI_CMD_UNLOCK(sc); 3706 return (USB_ERR_BAD_ADDRESS); 3707 } 3708 3709 /* store slot ID for later reference */ 3710 3711 udev->controller_slot_id = temp; 3712 3713 /* reset data structure */ 3714 3715 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 3716 3717 /* set mark slot allocated */ 3718 3719 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 3720 3721 err = xhci_alloc_device_ext(udev); 3722 3723 XHCI_CMD_UNLOCK(sc); 3724 3725 /* get device into default state */ 3726 3727 if (err == 0) 3728 err = xhci_set_address(udev, NULL, 0); 3729 3730 return (err); 3731 } 3732 3733 static void 3734 xhci_device_uninit(struct usb_device *udev) 3735 { 3736 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3737 uint8_t index; 3738 3739 /* no init for root HUB */ 3740 if (udev->parent_hub == NULL) 3741 return; 3742 3743 XHCI_CMD_LOCK(sc); 3744 3745 index = udev->controller_slot_id; 3746 3747 if (index <= sc->sc_noslot) { 3748 xhci_cmd_disable_slot(sc, index); 3749 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 3750 3751 /* free device extension */ 3752 xhci_free_device_ext(udev); 3753 } 3754 3755 XHCI_CMD_UNLOCK(sc); 3756 } 3757 3758 static void 3759 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3760 { 3761 /* 3762 * Wait until the hardware has finished any possible use of 3763 * the transfer descriptor(s) 3764 */ 3765 *pus = 2048; /* microseconds */ 3766 } 3767 3768 static void 3769 xhci_device_resume(struct usb_device *udev) 3770 { 3771 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3772 uint8_t index; 3773 uint8_t n; 3774 3775 DPRINTF("\n"); 3776 3777 /* check for root HUB */ 3778 if (udev->parent_hub == NULL) 3779 return; 3780 3781 index = udev->controller_slot_id; 3782 3783 XHCI_CMD_LOCK(sc); 3784 3785 /* blindly resume all endpoints */ 3786 3787 USB_BUS_LOCK(udev->bus); 3788 3789 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) 3790 XWRITE4(sc, door, XHCI_DOORBELL(index), n | XHCI_DB_SID_SET(0)); 3791 3792 USB_BUS_UNLOCK(udev->bus); 3793 3794 XHCI_CMD_UNLOCK(sc); 3795 } 3796 3797 static void 3798 xhci_device_suspend(struct usb_device *udev) 3799 { 3800 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3801 uint8_t index; 3802 uint8_t n; 3803 usb_error_t err; 3804 3805 DPRINTF("\n"); 3806 3807 /* check for root HUB */ 3808 if (udev->parent_hub == NULL) 3809 return; 3810 3811 index = udev->controller_slot_id; 3812 3813 XHCI_CMD_LOCK(sc); 3814 3815 /* blindly suspend all endpoints */ 3816 3817 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3818 err = xhci_cmd_stop_ep(sc, 1, n, index); 3819 if (err != 0) { 3820 DPRINTF("Failed to suspend endpoint " 3821 "%u on slot %u (ignored).\n", n, index); 3822 } 3823 } 3824 3825 XHCI_CMD_UNLOCK(sc); 3826 } 3827 3828 static void 3829 xhci_set_hw_power(struct usb_bus *bus) 3830 { 3831 DPRINTF("\n"); 3832 } 3833 3834 static void 3835 xhci_device_state_change(struct usb_device *udev) 3836 { 3837 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3838 struct usb_page_search buf_inp; 3839 usb_error_t err; 3840 uint8_t index; 3841 3842 /* check for root HUB */ 3843 if (udev->parent_hub == NULL) 3844 return; 3845 3846 index = udev->controller_slot_id; 3847 3848 DPRINTF("\n"); 3849 3850 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 3851 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 3852 &sc->sc_hw.devs[index].tt); 3853 if (err != 0) 3854 sc->sc_hw.devs[index].nports = 0; 3855 } 3856 3857 XHCI_CMD_LOCK(sc); 3858 3859 switch (usb_get_device_state(udev)) { 3860 case USB_STATE_POWERED: 3861 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 3862 break; 3863 3864 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 3865 3866 err = xhci_cmd_reset_dev(sc, index); 3867 3868 if (err != 0) { 3869 DPRINTF("Device reset failed " 3870 "for slot %u.\n", index); 3871 } 3872 break; 3873 3874 case USB_STATE_ADDRESSED: 3875 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 3876 break; 3877 3878 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 3879 3880 err = xhci_cmd_configure_ep(sc, 0, 1, index); 3881 3882 if (err) { 3883 DPRINTF("Failed to deconfigure " 3884 "slot %u.\n", index); 3885 } 3886 break; 3887 3888 case USB_STATE_CONFIGURED: 3889 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 3890 break; 3891 3892 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 3893 3894 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 3895 3896 xhci_configure_mask(udev, 1, 0); 3897 3898 err = xhci_configure_device(udev); 3899 if (err != 0) { 3900 DPRINTF("Could not configure device " 3901 "at slot %u.\n", index); 3902 } 3903 3904 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3905 if (err != 0) { 3906 DPRINTF("Could not evaluate device " 3907 "context at slot %u.\n", index); 3908 } 3909 break; 3910 3911 default: 3912 break; 3913 } 3914 XHCI_CMD_UNLOCK(sc); 3915 } 3916 3917 struct usb_bus_methods xhci_bus_methods = { 3918 .endpoint_init = xhci_ep_init, 3919 .endpoint_uninit = xhci_ep_uninit, 3920 .xfer_setup = xhci_xfer_setup, 3921 .xfer_unsetup = xhci_xfer_unsetup, 3922 .get_dma_delay = xhci_get_dma_delay, 3923 .device_init = xhci_device_init, 3924 .device_uninit = xhci_device_uninit, 3925 .device_resume = xhci_device_resume, 3926 .device_suspend = xhci_device_suspend, 3927 .set_hw_power = xhci_set_hw_power, 3928 .roothub_exec = xhci_roothub_exec, 3929 .xfer_poll = xhci_do_poll, 3930 .start_dma_delay = xhci_start_dma_delay, 3931 .set_address = xhci_set_address, 3932 .clear_stall = xhci_ep_clear_stall, 3933 .device_state_change = xhci_device_state_change, 3934 .set_hw_power_sleep = xhci_set_hw_power_sleep, 3935 }; 3936