1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36 /* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43 #ifdef USB_GLOBAL_INCLUDE_FILE 44 #include USB_GLOBAL_INCLUDE_FILE 45 #else 46 #include <sys/stdint.h> 47 #include <sys/stddef.h> 48 #include <sys/param.h> 49 #include <sys/queue.h> 50 #include <sys/types.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/bus.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/condvar.h> 58 #include <sys/sysctl.h> 59 #include <sys/sx.h> 60 #include <sys/unistd.h> 61 #include <sys/callout.h> 62 #include <sys/malloc.h> 63 #include <sys/priv.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 68 #define USB_DEBUG_VAR xhcidebug 69 70 #include <dev/usb/usb_core.h> 71 #include <dev/usb/usb_debug.h> 72 #include <dev/usb/usb_busdma.h> 73 #include <dev/usb/usb_process.h> 74 #include <dev/usb/usb_transfer.h> 75 #include <dev/usb/usb_device.h> 76 #include <dev/usb/usb_hub.h> 77 #include <dev/usb/usb_util.h> 78 79 #include <dev/usb/usb_controller.h> 80 #include <dev/usb/usb_bus.h> 81 #endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83 #include <dev/usb/controller/xhci.h> 84 #include <dev/usb/controller/xhcireg.h> 85 86 #define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90 #ifdef USB_DEBUG 91 static int xhcidebug; 92 static int xhciroute; 93 94 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 95 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 96 &xhcidebug, 0, "Debug level"); 97 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 98 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN, 99 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 100 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 101 #endif 102 103 #define XHCI_INTR_ENDPT 1 104 105 struct xhci_std_temp { 106 struct xhci_softc *sc; 107 struct usb_page_cache *pc; 108 struct xhci_td *td; 109 struct xhci_td *td_next; 110 uint32_t len; 111 uint32_t offset; 112 uint32_t max_packet_size; 113 uint32_t average; 114 uint16_t isoc_delta; 115 uint16_t isoc_frame; 116 uint8_t shortpkt; 117 uint8_t multishort; 118 uint8_t last_frame; 119 uint8_t trb_type; 120 uint8_t direction; 121 uint8_t tbc; 122 uint8_t tlbpc; 123 uint8_t step_td; 124 uint8_t do_isoc_sync; 125 }; 126 127 static void xhci_do_poll(struct usb_bus *); 128 static void xhci_device_done(struct usb_xfer *, usb_error_t); 129 static void xhci_root_intr(struct xhci_softc *); 130 static void xhci_free_device_ext(struct usb_device *); 131 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 132 struct usb_endpoint_descriptor *); 133 static usb_proc_callback_t xhci_configure_msg; 134 static usb_error_t xhci_configure_device(struct usb_device *); 135 static usb_error_t xhci_configure_endpoint(struct usb_device *, 136 struct usb_endpoint_descriptor *, uint64_t, uint16_t, 137 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, uint8_t); 138 static usb_error_t xhci_configure_mask(struct usb_device *, 139 uint32_t, uint8_t); 140 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 141 uint64_t, uint8_t); 142 static void xhci_endpoint_doorbell(struct usb_xfer *); 143 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 144 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 145 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 146 #ifdef USB_DEBUG 147 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 148 #endif 149 150 extern struct usb_bus_methods xhci_bus_methods; 151 152 #ifdef USB_DEBUG 153 static void 154 xhci_dump_trb(struct xhci_trb *trb) 155 { 156 DPRINTFN(5, "trb = %p\n", trb); 157 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 158 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 159 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 160 } 161 162 static void 163 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 164 { 165 DPRINTFN(5, "pep = %p\n", pep); 166 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 167 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 168 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 169 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 170 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 171 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 172 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 173 } 174 175 static void 176 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 177 { 178 DPRINTFN(5, "psl = %p\n", psl); 179 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 180 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 181 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 182 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 183 } 184 #endif 185 186 uint32_t 187 xhci_get_port_route(void) 188 { 189 #ifdef USB_DEBUG 190 return (0xFFFFFFFFU ^ ((uint32_t)xhciroute)); 191 #else 192 return (0xFFFFFFFFU); 193 #endif 194 } 195 196 static void 197 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 198 { 199 struct xhci_softc *sc = XHCI_BUS2SC(bus); 200 uint8_t i; 201 202 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 203 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 204 205 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 206 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 207 208 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 209 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 210 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 211 } 212 } 213 214 static void 215 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 216 { 217 if (sc->sc_ctx_is_64_byte) { 218 uint32_t offset; 219 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 220 /* all contexts are initially 32-bytes */ 221 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 222 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 223 } 224 *ptr = htole32(val); 225 } 226 227 static uint32_t 228 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 229 { 230 if (sc->sc_ctx_is_64_byte) { 231 uint32_t offset; 232 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 233 /* all contexts are initially 32-bytes */ 234 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 235 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 236 } 237 return (le32toh(*ptr)); 238 } 239 240 static void 241 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 242 { 243 if (sc->sc_ctx_is_64_byte) { 244 uint32_t offset; 245 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 246 /* all contexts are initially 32-bytes */ 247 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 248 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 249 } 250 *ptr = htole64(val); 251 } 252 253 #ifdef USB_DEBUG 254 static uint64_t 255 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 256 { 257 if (sc->sc_ctx_is_64_byte) { 258 uint32_t offset; 259 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 260 /* all contexts are initially 32-bytes */ 261 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 262 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 263 } 264 return (le64toh(*ptr)); 265 } 266 #endif 267 268 usb_error_t 269 xhci_start_controller(struct xhci_softc *sc) 270 { 271 struct usb_page_search buf_res; 272 struct xhci_hw_root *phwr; 273 struct xhci_dev_ctx_addr *pdctxa; 274 uint64_t addr; 275 uint32_t temp; 276 uint16_t i; 277 278 DPRINTF("\n"); 279 280 sc->sc_capa_off = 0; 281 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 282 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 283 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 284 285 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 286 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 287 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 288 289 sc->sc_event_ccs = 1; 290 sc->sc_event_idx = 0; 291 sc->sc_command_ccs = 1; 292 sc->sc_command_idx = 0; 293 294 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 295 296 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 297 298 DPRINTF("HCS0 = 0x%08x\n", temp); 299 300 if (XHCI_HCS0_CSZ(temp)) { 301 sc->sc_ctx_is_64_byte = 1; 302 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 303 } else { 304 sc->sc_ctx_is_64_byte = 0; 305 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 306 } 307 308 /* Reset controller */ 309 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 310 311 for (i = 0; i != 100; i++) { 312 usb_pause_mtx(NULL, hz / 100); 313 temp = XREAD4(sc, oper, XHCI_USBCMD) & 314 (XHCI_CMD_HCRST | XHCI_STS_CNR); 315 if (!temp) 316 break; 317 } 318 319 if (temp) { 320 device_printf(sc->sc_bus.parent, "Controller " 321 "reset timeout.\n"); 322 return (USB_ERR_IOERROR); 323 } 324 325 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 326 device_printf(sc->sc_bus.parent, "Controller does " 327 "not support 4K page size.\n"); 328 return (USB_ERR_IOERROR); 329 } 330 331 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 332 333 i = XHCI_HCS1_N_PORTS(temp); 334 335 if (i == 0) { 336 device_printf(sc->sc_bus.parent, "Invalid number " 337 "of ports: %u\n", i); 338 return (USB_ERR_IOERROR); 339 } 340 341 sc->sc_noport = i; 342 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 343 344 if (sc->sc_noslot > XHCI_MAX_DEVICES) 345 sc->sc_noslot = XHCI_MAX_DEVICES; 346 347 /* setup number of device slots */ 348 349 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 350 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 351 352 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 353 354 DPRINTF("Max slots: %u\n", sc->sc_noslot); 355 356 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 357 358 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 359 360 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 361 device_printf(sc->sc_bus.parent, "XHCI request " 362 "too many scratchpads\n"); 363 return (USB_ERR_NOMEM); 364 } 365 366 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 367 368 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 369 370 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 371 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 372 373 temp = XREAD4(sc, oper, XHCI_USBSTS); 374 375 /* clear interrupts */ 376 XWRITE4(sc, oper, XHCI_USBSTS, temp); 377 /* disable all device notifications */ 378 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 379 380 /* setup device context base address */ 381 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 382 pdctxa = buf_res.buffer; 383 memset(pdctxa, 0, sizeof(*pdctxa)); 384 385 addr = buf_res.physaddr; 386 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 387 388 /* slot 0 points to the table of scratchpad pointers */ 389 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 390 391 for (i = 0; i != sc->sc_noscratch; i++) { 392 struct usb_page_search buf_scp; 393 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 394 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 395 } 396 397 addr = buf_res.physaddr; 398 399 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 400 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 401 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 402 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 403 404 /* Setup event table size */ 405 406 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 407 408 DPRINTF("HCS2=0x%08x\n", temp); 409 410 temp = XHCI_HCS2_ERST_MAX(temp); 411 temp = 1U << temp; 412 if (temp > XHCI_MAX_RSEG) 413 temp = XHCI_MAX_RSEG; 414 415 sc->sc_erst_max = temp; 416 417 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 418 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 419 420 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 421 422 /* Setup interrupt rate */ 423 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 424 425 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 426 427 phwr = buf_res.buffer; 428 addr = buf_res.physaddr; 429 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 430 431 /* reset hardware root structure */ 432 memset(phwr, 0, sizeof(*phwr)); 433 434 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 435 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 436 437 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 438 439 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 440 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 441 442 addr = (uint64_t)buf_res.physaddr; 443 444 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 445 446 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 447 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 448 449 /* Setup interrupter registers */ 450 451 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 452 temp |= XHCI_IMAN_INTR_ENA; 453 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 454 455 /* setup command ring control base address */ 456 addr = buf_res.physaddr; 457 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 458 459 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 460 461 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 462 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 463 464 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 465 466 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 467 468 /* Go! */ 469 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 470 XHCI_CMD_INTE | XHCI_CMD_HSEE); 471 472 for (i = 0; i != 100; i++) { 473 usb_pause_mtx(NULL, hz / 100); 474 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 475 if (!temp) 476 break; 477 } 478 if (temp) { 479 XWRITE4(sc, oper, XHCI_USBCMD, 0); 480 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 481 return (USB_ERR_IOERROR); 482 } 483 484 /* catch any lost interrupts */ 485 xhci_do_poll(&sc->sc_bus); 486 487 return (0); 488 } 489 490 usb_error_t 491 xhci_halt_controller(struct xhci_softc *sc) 492 { 493 uint32_t temp; 494 uint16_t i; 495 496 DPRINTF("\n"); 497 498 sc->sc_capa_off = 0; 499 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 500 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 501 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 502 503 /* Halt controller */ 504 XWRITE4(sc, oper, XHCI_USBCMD, 0); 505 506 for (i = 0; i != 100; i++) { 507 usb_pause_mtx(NULL, hz / 100); 508 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 509 if (temp) 510 break; 511 } 512 513 if (!temp) { 514 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 515 return (USB_ERR_IOERROR); 516 } 517 return (0); 518 } 519 520 usb_error_t 521 xhci_init(struct xhci_softc *sc, device_t self) 522 { 523 /* initialise some bus fields */ 524 sc->sc_bus.parent = self; 525 526 /* set the bus revision */ 527 sc->sc_bus.usbrev = USB_REV_3_0; 528 529 /* set up the bus struct */ 530 sc->sc_bus.methods = &xhci_bus_methods; 531 532 /* setup devices array */ 533 sc->sc_bus.devices = sc->sc_devices; 534 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 535 536 /* setup command queue mutex and condition varible */ 537 cv_init(&sc->sc_cmd_cv, "CMDQ"); 538 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 539 540 /* get all DMA memory */ 541 if (usb_bus_mem_alloc_all(&sc->sc_bus, 542 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 543 return (ENOMEM); 544 } 545 546 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 547 sc->sc_config_msg[0].bus = &sc->sc_bus; 548 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 549 sc->sc_config_msg[1].bus = &sc->sc_bus; 550 551 return (0); 552 } 553 554 void 555 xhci_uninit(struct xhci_softc *sc) 556 { 557 /* 558 * NOTE: At this point the control transfer process is gone 559 * and "xhci_configure_msg" is no longer called. Consequently 560 * waiting for the configuration messages to complete is not 561 * needed. 562 */ 563 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 564 565 cv_destroy(&sc->sc_cmd_cv); 566 sx_destroy(&sc->sc_cmd_sx); 567 } 568 569 static void 570 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 571 { 572 struct xhci_softc *sc = XHCI_BUS2SC(bus); 573 574 switch (state) { 575 case USB_HW_POWER_SUSPEND: 576 DPRINTF("Stopping the XHCI\n"); 577 xhci_halt_controller(sc); 578 break; 579 case USB_HW_POWER_SHUTDOWN: 580 DPRINTF("Stopping the XHCI\n"); 581 xhci_halt_controller(sc); 582 break; 583 case USB_HW_POWER_RESUME: 584 DPRINTF("Starting the XHCI\n"); 585 xhci_start_controller(sc); 586 break; 587 default: 588 break; 589 } 590 } 591 592 static usb_error_t 593 xhci_generic_done_sub(struct usb_xfer *xfer) 594 { 595 struct xhci_td *td; 596 struct xhci_td *td_alt_next; 597 uint32_t len; 598 uint8_t status; 599 600 td = xfer->td_transfer_cache; 601 td_alt_next = td->alt_next; 602 603 if (xfer->aframes != xfer->nframes) 604 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 605 606 while (1) { 607 608 usb_pc_cpu_invalidate(td->page_cache); 609 610 status = td->status; 611 len = td->remainder; 612 613 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 614 xfer, (unsigned int)xfer->aframes, 615 (unsigned int)xfer->nframes, 616 (unsigned int)len, (unsigned int)td->len, 617 (unsigned int)status); 618 619 /* 620 * Verify the status length and 621 * add the length to "frlengths[]": 622 */ 623 if (len > td->len) { 624 /* should not happen */ 625 DPRINTF("Invalid status length, " 626 "0x%04x/0x%04x bytes\n", len, td->len); 627 status = XHCI_TRB_ERROR_LENGTH; 628 } else if (xfer->aframes != xfer->nframes) { 629 xfer->frlengths[xfer->aframes] += td->len - len; 630 } 631 /* Check for last transfer */ 632 if (((void *)td) == xfer->td_transfer_last) { 633 td = NULL; 634 break; 635 } 636 /* Check for transfer error */ 637 if (status != XHCI_TRB_ERROR_SHORT_PKT && 638 status != XHCI_TRB_ERROR_SUCCESS) { 639 /* the transfer is finished */ 640 td = NULL; 641 break; 642 } 643 /* Check for short transfer */ 644 if (len > 0) { 645 if (xfer->flags_int.short_frames_ok || 646 xfer->flags_int.isochronous_xfr || 647 xfer->flags_int.control_xfr) { 648 /* follow alt next */ 649 td = td->alt_next; 650 } else { 651 /* the transfer is finished */ 652 td = NULL; 653 } 654 break; 655 } 656 td = td->obj_next; 657 658 if (td->alt_next != td_alt_next) { 659 /* this USB frame is complete */ 660 break; 661 } 662 } 663 664 /* update transfer cache */ 665 666 xfer->td_transfer_cache = td; 667 668 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 669 (status != XHCI_TRB_ERROR_SHORT_PKT && 670 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 671 USB_ERR_NORMAL_COMPLETION); 672 } 673 674 static void 675 xhci_generic_done(struct usb_xfer *xfer) 676 { 677 usb_error_t err = 0; 678 679 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 680 xfer, xfer->endpoint); 681 682 /* reset scanner */ 683 684 xfer->td_transfer_cache = xfer->td_transfer_first; 685 686 if (xfer->flags_int.control_xfr) { 687 688 if (xfer->flags_int.control_hdr) 689 err = xhci_generic_done_sub(xfer); 690 691 xfer->aframes = 1; 692 693 if (xfer->td_transfer_cache == NULL) 694 goto done; 695 } 696 697 while (xfer->aframes != xfer->nframes) { 698 699 err = xhci_generic_done_sub(xfer); 700 xfer->aframes++; 701 702 if (xfer->td_transfer_cache == NULL) 703 goto done; 704 } 705 706 if (xfer->flags_int.control_xfr && 707 !xfer->flags_int.control_act) 708 err = xhci_generic_done_sub(xfer); 709 done: 710 /* transfer is complete */ 711 xhci_device_done(xfer, err); 712 } 713 714 static void 715 xhci_activate_transfer(struct usb_xfer *xfer) 716 { 717 struct xhci_td *td; 718 719 td = xfer->td_transfer_cache; 720 721 usb_pc_cpu_invalidate(td->page_cache); 722 723 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 724 725 /* activate the transfer */ 726 727 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 728 usb_pc_cpu_flush(td->page_cache); 729 730 xhci_endpoint_doorbell(xfer); 731 } 732 } 733 734 static void 735 xhci_skip_transfer(struct usb_xfer *xfer) 736 { 737 struct xhci_td *td; 738 struct xhci_td *td_last; 739 740 td = xfer->td_transfer_cache; 741 td_last = xfer->td_transfer_last; 742 743 td = td->alt_next; 744 745 usb_pc_cpu_invalidate(td->page_cache); 746 747 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 748 749 usb_pc_cpu_invalidate(td_last->page_cache); 750 751 /* copy LINK TRB to current waiting location */ 752 753 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 754 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 755 usb_pc_cpu_flush(td->page_cache); 756 757 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 758 usb_pc_cpu_flush(td->page_cache); 759 760 xhci_endpoint_doorbell(xfer); 761 } 762 } 763 764 /*------------------------------------------------------------------------* 765 * xhci_check_transfer 766 *------------------------------------------------------------------------*/ 767 static void 768 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 769 { 770 int64_t offset; 771 uint64_t td_event; 772 uint32_t temp; 773 uint32_t remainder; 774 uint8_t status; 775 uint8_t halted; 776 uint8_t epno; 777 uint8_t index; 778 uint8_t i; 779 780 /* decode TRB */ 781 td_event = le64toh(trb->qwTrb0); 782 temp = le32toh(trb->dwTrb2); 783 784 remainder = XHCI_TRB_2_REM_GET(temp); 785 status = XHCI_TRB_2_ERROR_GET(temp); 786 787 temp = le32toh(trb->dwTrb3); 788 epno = XHCI_TRB_3_EP_GET(temp); 789 index = XHCI_TRB_3_SLOT_GET(temp); 790 791 /* check if error means halted */ 792 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 793 status != XHCI_TRB_ERROR_SUCCESS); 794 795 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 796 index, epno, remainder, status); 797 798 if (index > sc->sc_noslot) { 799 DPRINTF("Invalid slot.\n"); 800 return; 801 } 802 803 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 804 DPRINTF("Invalid endpoint.\n"); 805 return; 806 } 807 808 /* try to find the USB transfer that generated the event */ 809 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 810 struct usb_xfer *xfer; 811 struct xhci_td *td; 812 struct xhci_endpoint_ext *pepext; 813 814 pepext = &sc->sc_hw.devs[index].endp[epno]; 815 816 xfer = pepext->xfer[i]; 817 if (xfer == NULL) 818 continue; 819 820 td = xfer->td_transfer_cache; 821 822 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 823 (long long)td_event, 824 (long long)td->td_self, 825 (long long)td->td_self + sizeof(td->td_trb)); 826 827 /* 828 * NOTE: Some XHCI implementations might not trigger 829 * an event on the last LINK TRB so we need to 830 * consider both the last and second last event 831 * address as conditions for a successful transfer. 832 * 833 * NOTE: We assume that the XHCI will only trigger one 834 * event per chain of TRBs. 835 */ 836 837 offset = td_event - td->td_self; 838 839 if (offset >= 0 && 840 offset < (int64_t)sizeof(td->td_trb)) { 841 842 usb_pc_cpu_invalidate(td->page_cache); 843 844 /* compute rest of remainder, if any */ 845 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 846 temp = le32toh(td->td_trb[i].dwTrb2); 847 remainder += XHCI_TRB_2_BYTES_GET(temp); 848 } 849 850 DPRINTFN(5, "New remainder: %u\n", remainder); 851 852 /* clear isochronous transfer errors */ 853 if (xfer->flags_int.isochronous_xfr) { 854 if (halted) { 855 halted = 0; 856 status = XHCI_TRB_ERROR_SUCCESS; 857 remainder = td->len; 858 } 859 } 860 861 /* "td->remainder" is verified later */ 862 td->remainder = remainder; 863 td->status = status; 864 865 usb_pc_cpu_flush(td->page_cache); 866 867 /* 868 * 1) Last transfer descriptor makes the 869 * transfer done 870 */ 871 if (((void *)td) == xfer->td_transfer_last) { 872 DPRINTF("TD is last\n"); 873 xhci_generic_done(xfer); 874 break; 875 } 876 877 /* 878 * 2) Any kind of error makes the transfer 879 * done 880 */ 881 if (halted) { 882 DPRINTF("TD has I/O error\n"); 883 xhci_generic_done(xfer); 884 break; 885 } 886 887 /* 888 * 3) If there is no alternate next transfer, 889 * a short packet also makes the transfer done 890 */ 891 if (td->remainder > 0) { 892 if (td->alt_next == NULL) { 893 DPRINTF( 894 "short TD has no alternate next\n"); 895 xhci_generic_done(xfer); 896 break; 897 } 898 DPRINTF("TD has short pkt\n"); 899 if (xfer->flags_int.short_frames_ok || 900 xfer->flags_int.isochronous_xfr || 901 xfer->flags_int.control_xfr) { 902 /* follow the alt next */ 903 xfer->td_transfer_cache = td->alt_next; 904 xhci_activate_transfer(xfer); 905 break; 906 } 907 xhci_skip_transfer(xfer); 908 xhci_generic_done(xfer); 909 break; 910 } 911 912 /* 913 * 4) Transfer complete - go to next TD 914 */ 915 DPRINTF("Following next TD\n"); 916 xfer->td_transfer_cache = td->obj_next; 917 xhci_activate_transfer(xfer); 918 break; /* there should only be one match */ 919 } 920 } 921 } 922 923 static void 924 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 925 { 926 if (sc->sc_cmd_addr == trb->qwTrb0) { 927 DPRINTF("Received command event\n"); 928 sc->sc_cmd_result[0] = trb->dwTrb2; 929 sc->sc_cmd_result[1] = trb->dwTrb3; 930 cv_signal(&sc->sc_cmd_cv); 931 } 932 } 933 934 static void 935 xhci_interrupt_poll(struct xhci_softc *sc) 936 { 937 struct usb_page_search buf_res; 938 struct xhci_hw_root *phwr; 939 uint64_t addr; 940 uint32_t temp; 941 uint16_t i; 942 uint8_t event; 943 uint8_t j; 944 uint8_t k; 945 uint8_t t; 946 947 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 948 949 phwr = buf_res.buffer; 950 951 /* Receive any events */ 952 953 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 954 955 i = sc->sc_event_idx; 956 j = sc->sc_event_ccs; 957 t = 2; 958 959 while (1) { 960 961 temp = le32toh(phwr->hwr_events[i].dwTrb3); 962 963 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 964 965 if (j != k) 966 break; 967 968 event = XHCI_TRB_3_TYPE_GET(temp); 969 970 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 971 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 972 (long)le32toh(phwr->hwr_events[i].dwTrb2), 973 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 974 975 switch (event) { 976 case XHCI_TRB_EVENT_TRANSFER: 977 xhci_check_transfer(sc, &phwr->hwr_events[i]); 978 break; 979 case XHCI_TRB_EVENT_CMD_COMPLETE: 980 xhci_check_command(sc, &phwr->hwr_events[i]); 981 break; 982 default: 983 DPRINTF("Unhandled event = %u\n", event); 984 break; 985 } 986 987 i++; 988 989 if (i == XHCI_MAX_EVENTS) { 990 i = 0; 991 j ^= 1; 992 993 /* check for timeout */ 994 if (!--t) 995 break; 996 } 997 } 998 999 sc->sc_event_idx = i; 1000 sc->sc_event_ccs = j; 1001 1002 /* 1003 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1004 * latched. That means to activate the register we need to 1005 * write both the low and high double word of the 64-bit 1006 * register. 1007 */ 1008 1009 addr = (uint32_t)buf_res.physaddr; 1010 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1011 1012 /* try to clear busy bit */ 1013 addr |= XHCI_ERDP_LO_BUSY; 1014 1015 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1016 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1017 } 1018 1019 static usb_error_t 1020 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1021 uint16_t timeout_ms) 1022 { 1023 struct usb_page_search buf_res; 1024 struct xhci_hw_root *phwr; 1025 uint64_t addr; 1026 uint32_t temp; 1027 uint8_t i; 1028 uint8_t j; 1029 int err; 1030 1031 XHCI_CMD_ASSERT_LOCKED(sc); 1032 1033 /* get hardware root structure */ 1034 1035 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1036 1037 phwr = buf_res.buffer; 1038 1039 /* Queue command */ 1040 1041 USB_BUS_LOCK(&sc->sc_bus); 1042 1043 i = sc->sc_command_idx; 1044 j = sc->sc_command_ccs; 1045 1046 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1047 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1048 (long long)le64toh(trb->qwTrb0), 1049 (long)le32toh(trb->dwTrb2), 1050 (long)le32toh(trb->dwTrb3)); 1051 1052 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1053 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1054 1055 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1056 1057 temp = trb->dwTrb3; 1058 1059 if (j) 1060 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1061 else 1062 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1063 1064 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1065 1066 phwr->hwr_commands[i].dwTrb3 = temp; 1067 1068 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1069 1070 addr = buf_res.physaddr; 1071 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1072 1073 sc->sc_cmd_addr = htole64(addr); 1074 1075 i++; 1076 1077 if (i == (XHCI_MAX_COMMANDS - 1)) { 1078 1079 if (j) { 1080 temp = htole32(XHCI_TRB_3_TC_BIT | 1081 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1082 XHCI_TRB_3_CYCLE_BIT); 1083 } else { 1084 temp = htole32(XHCI_TRB_3_TC_BIT | 1085 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1086 } 1087 1088 phwr->hwr_commands[i].dwTrb3 = temp; 1089 1090 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1091 1092 i = 0; 1093 j ^= 1; 1094 } 1095 1096 sc->sc_command_idx = i; 1097 sc->sc_command_ccs = j; 1098 1099 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1100 1101 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1102 USB_MS_TO_TICKS(timeout_ms)); 1103 1104 if (err) { 1105 DPRINTFN(0, "Command timeout!\n"); 1106 err = USB_ERR_TIMEOUT; 1107 trb->dwTrb2 = 0; 1108 trb->dwTrb3 = 0; 1109 } else { 1110 temp = le32toh(sc->sc_cmd_result[0]); 1111 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1112 err = USB_ERR_IOERROR; 1113 1114 trb->dwTrb2 = sc->sc_cmd_result[0]; 1115 trb->dwTrb3 = sc->sc_cmd_result[1]; 1116 } 1117 1118 USB_BUS_UNLOCK(&sc->sc_bus); 1119 1120 return (err); 1121 } 1122 1123 #if 0 1124 static usb_error_t 1125 xhci_cmd_nop(struct xhci_softc *sc) 1126 { 1127 struct xhci_trb trb; 1128 uint32_t temp; 1129 1130 DPRINTF("\n"); 1131 1132 trb.qwTrb0 = 0; 1133 trb.dwTrb2 = 0; 1134 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1135 1136 trb.dwTrb3 = htole32(temp); 1137 1138 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1139 } 1140 #endif 1141 1142 static usb_error_t 1143 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1144 { 1145 struct xhci_trb trb; 1146 uint32_t temp; 1147 usb_error_t err; 1148 1149 DPRINTF("\n"); 1150 1151 trb.qwTrb0 = 0; 1152 trb.dwTrb2 = 0; 1153 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1154 1155 err = xhci_do_command(sc, &trb, 100 /* ms */); 1156 if (err) 1157 goto done; 1158 1159 temp = le32toh(trb.dwTrb3); 1160 1161 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1162 1163 done: 1164 return (err); 1165 } 1166 1167 static usb_error_t 1168 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1169 { 1170 struct xhci_trb trb; 1171 uint32_t temp; 1172 1173 DPRINTF("\n"); 1174 1175 trb.qwTrb0 = 0; 1176 trb.dwTrb2 = 0; 1177 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1178 XHCI_TRB_3_SLOT_SET(slot_id); 1179 1180 trb.dwTrb3 = htole32(temp); 1181 1182 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1183 } 1184 1185 static usb_error_t 1186 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1187 uint8_t bsr, uint8_t slot_id) 1188 { 1189 struct xhci_trb trb; 1190 uint32_t temp; 1191 1192 DPRINTF("\n"); 1193 1194 trb.qwTrb0 = htole64(input_ctx); 1195 trb.dwTrb2 = 0; 1196 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1197 XHCI_TRB_3_SLOT_SET(slot_id); 1198 1199 if (bsr) 1200 temp |= XHCI_TRB_3_BSR_BIT; 1201 1202 trb.dwTrb3 = htole32(temp); 1203 1204 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1205 } 1206 1207 static usb_error_t 1208 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1209 { 1210 struct usb_page_search buf_inp; 1211 struct usb_page_search buf_dev; 1212 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1213 struct xhci_hw_dev *hdev; 1214 struct xhci_dev_ctx *pdev; 1215 struct xhci_endpoint_ext *pepext; 1216 uint32_t temp; 1217 uint16_t mps; 1218 usb_error_t err; 1219 uint8_t index; 1220 1221 /* the root HUB case is not handled here */ 1222 if (udev->parent_hub == NULL) 1223 return (USB_ERR_INVAL); 1224 1225 index = udev->controller_slot_id; 1226 1227 hdev = &sc->sc_hw.devs[index]; 1228 1229 if (mtx != NULL) 1230 mtx_unlock(mtx); 1231 1232 XHCI_CMD_LOCK(sc); 1233 1234 switch (hdev->state) { 1235 case XHCI_ST_DEFAULT: 1236 case XHCI_ST_ENABLED: 1237 1238 hdev->state = XHCI_ST_ENABLED; 1239 1240 /* set configure mask to slot and EP0 */ 1241 xhci_configure_mask(udev, 3, 0); 1242 1243 /* configure input slot context structure */ 1244 err = xhci_configure_device(udev); 1245 1246 if (err != 0) { 1247 DPRINTF("Could not configure device\n"); 1248 break; 1249 } 1250 1251 /* configure input endpoint context structure */ 1252 switch (udev->speed) { 1253 case USB_SPEED_LOW: 1254 case USB_SPEED_FULL: 1255 mps = 8; 1256 break; 1257 case USB_SPEED_HIGH: 1258 mps = 64; 1259 break; 1260 default: 1261 mps = 512; 1262 break; 1263 } 1264 1265 pepext = xhci_get_endpoint_ext(udev, 1266 &udev->ctrl_ep_desc); 1267 err = xhci_configure_endpoint(udev, 1268 &udev->ctrl_ep_desc, pepext->physaddr, 1269 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1270 1271 if (err != 0) { 1272 DPRINTF("Could not configure default endpoint\n"); 1273 break; 1274 } 1275 1276 /* execute set address command */ 1277 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1278 1279 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1280 (address == 0), index); 1281 1282 if (err != 0) { 1283 DPRINTF("Could not set address " 1284 "for slot %u.\n", index); 1285 if (address != 0) 1286 break; 1287 } 1288 1289 /* update device address to new value */ 1290 1291 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1292 pdev = buf_dev.buffer; 1293 usb_pc_cpu_invalidate(&hdev->device_pc); 1294 1295 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1296 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1297 1298 /* update device state to new value */ 1299 1300 if (address != 0) 1301 hdev->state = XHCI_ST_ADDRESSED; 1302 else 1303 hdev->state = XHCI_ST_DEFAULT; 1304 break; 1305 1306 default: 1307 DPRINTF("Wrong state for set address.\n"); 1308 err = USB_ERR_IOERROR; 1309 break; 1310 } 1311 XHCI_CMD_UNLOCK(sc); 1312 1313 if (mtx != NULL) 1314 mtx_lock(mtx); 1315 1316 return (err); 1317 } 1318 1319 static usb_error_t 1320 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1321 uint8_t deconfigure, uint8_t slot_id) 1322 { 1323 struct xhci_trb trb; 1324 uint32_t temp; 1325 1326 DPRINTF("\n"); 1327 1328 trb.qwTrb0 = htole64(input_ctx); 1329 trb.dwTrb2 = 0; 1330 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1331 XHCI_TRB_3_SLOT_SET(slot_id); 1332 1333 if (deconfigure) 1334 temp |= XHCI_TRB_3_DCEP_BIT; 1335 1336 trb.dwTrb3 = htole32(temp); 1337 1338 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1339 } 1340 1341 static usb_error_t 1342 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1343 uint8_t slot_id) 1344 { 1345 struct xhci_trb trb; 1346 uint32_t temp; 1347 1348 DPRINTF("\n"); 1349 1350 trb.qwTrb0 = htole64(input_ctx); 1351 trb.dwTrb2 = 0; 1352 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1353 XHCI_TRB_3_SLOT_SET(slot_id); 1354 trb.dwTrb3 = htole32(temp); 1355 1356 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1357 } 1358 1359 static usb_error_t 1360 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1361 uint8_t ep_id, uint8_t slot_id) 1362 { 1363 struct xhci_trb trb; 1364 uint32_t temp; 1365 1366 DPRINTF("\n"); 1367 1368 trb.qwTrb0 = 0; 1369 trb.dwTrb2 = 0; 1370 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1371 XHCI_TRB_3_SLOT_SET(slot_id) | 1372 XHCI_TRB_3_EP_SET(ep_id); 1373 1374 if (preserve) 1375 temp |= XHCI_TRB_3_PRSV_BIT; 1376 1377 trb.dwTrb3 = htole32(temp); 1378 1379 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1380 } 1381 1382 static usb_error_t 1383 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1384 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1385 { 1386 struct xhci_trb trb; 1387 uint32_t temp; 1388 1389 DPRINTF("\n"); 1390 1391 trb.qwTrb0 = htole64(dequeue_ptr); 1392 1393 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1394 trb.dwTrb2 = htole32(temp); 1395 1396 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1397 XHCI_TRB_3_SLOT_SET(slot_id) | 1398 XHCI_TRB_3_EP_SET(ep_id); 1399 trb.dwTrb3 = htole32(temp); 1400 1401 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1402 } 1403 1404 static usb_error_t 1405 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1406 uint8_t ep_id, uint8_t slot_id) 1407 { 1408 struct xhci_trb trb; 1409 uint32_t temp; 1410 1411 DPRINTF("\n"); 1412 1413 trb.qwTrb0 = 0; 1414 trb.dwTrb2 = 0; 1415 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1416 XHCI_TRB_3_SLOT_SET(slot_id) | 1417 XHCI_TRB_3_EP_SET(ep_id); 1418 1419 if (suspend) 1420 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1421 1422 trb.dwTrb3 = htole32(temp); 1423 1424 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1425 } 1426 1427 static usb_error_t 1428 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1429 { 1430 struct xhci_trb trb; 1431 uint32_t temp; 1432 1433 DPRINTF("\n"); 1434 1435 trb.qwTrb0 = 0; 1436 trb.dwTrb2 = 0; 1437 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1438 XHCI_TRB_3_SLOT_SET(slot_id); 1439 1440 trb.dwTrb3 = htole32(temp); 1441 1442 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1443 } 1444 1445 /*------------------------------------------------------------------------* 1446 * xhci_interrupt - XHCI interrupt handler 1447 *------------------------------------------------------------------------*/ 1448 void 1449 xhci_interrupt(struct xhci_softc *sc) 1450 { 1451 uint32_t status; 1452 uint32_t iman; 1453 1454 USB_BUS_LOCK(&sc->sc_bus); 1455 1456 status = XREAD4(sc, oper, XHCI_USBSTS); 1457 if (status == 0) 1458 goto done; 1459 1460 /* acknowledge interrupts */ 1461 1462 XWRITE4(sc, oper, XHCI_USBSTS, status); 1463 1464 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1465 1466 if (status & XHCI_STS_EINT) { 1467 1468 /* acknowledge pending event */ 1469 iman = XREAD4(sc, runt, XHCI_IMAN(0)); 1470 1471 /* reset interrupt */ 1472 XWRITE4(sc, runt, XHCI_IMAN(0), iman); 1473 1474 DPRINTFN(16, "real interrupt (iman=0x%08x)\n", iman); 1475 1476 /* check for event(s) */ 1477 xhci_interrupt_poll(sc); 1478 } 1479 1480 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1481 XHCI_STS_HSE | XHCI_STS_HCE)) { 1482 1483 if (status & XHCI_STS_PCD) { 1484 xhci_root_intr(sc); 1485 } 1486 1487 if (status & XHCI_STS_HCH) { 1488 printf("%s: host controller halted\n", 1489 __FUNCTION__); 1490 } 1491 1492 if (status & XHCI_STS_HSE) { 1493 printf("%s: host system error\n", 1494 __FUNCTION__); 1495 } 1496 1497 if (status & XHCI_STS_HCE) { 1498 printf("%s: host controller error\n", 1499 __FUNCTION__); 1500 } 1501 } 1502 done: 1503 USB_BUS_UNLOCK(&sc->sc_bus); 1504 } 1505 1506 /*------------------------------------------------------------------------* 1507 * xhci_timeout - XHCI timeout handler 1508 *------------------------------------------------------------------------*/ 1509 static void 1510 xhci_timeout(void *arg) 1511 { 1512 struct usb_xfer *xfer = arg; 1513 1514 DPRINTF("xfer=%p\n", xfer); 1515 1516 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1517 1518 /* transfer is transferred */ 1519 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1520 } 1521 1522 static void 1523 xhci_do_poll(struct usb_bus *bus) 1524 { 1525 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1526 1527 USB_BUS_LOCK(&sc->sc_bus); 1528 xhci_interrupt_poll(sc); 1529 USB_BUS_UNLOCK(&sc->sc_bus); 1530 } 1531 1532 static void 1533 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1534 { 1535 struct usb_page_search buf_res; 1536 struct xhci_td *td; 1537 struct xhci_td *td_next; 1538 struct xhci_td *td_alt_next; 1539 uint32_t buf_offset; 1540 uint32_t average; 1541 uint32_t len_old; 1542 uint32_t dword; 1543 uint8_t shortpkt_old; 1544 uint8_t precompute; 1545 uint8_t x; 1546 1547 td_alt_next = NULL; 1548 buf_offset = 0; 1549 shortpkt_old = temp->shortpkt; 1550 len_old = temp->len; 1551 precompute = 1; 1552 1553 restart: 1554 1555 td = temp->td; 1556 td_next = temp->td_next; 1557 1558 while (1) { 1559 1560 if (temp->len == 0) { 1561 1562 if (temp->shortpkt) 1563 break; 1564 1565 /* send a Zero Length Packet, ZLP, last */ 1566 1567 temp->shortpkt = 1; 1568 average = 0; 1569 1570 } else { 1571 1572 average = temp->average; 1573 1574 if (temp->len < average) { 1575 if (temp->len % temp->max_packet_size) { 1576 temp->shortpkt = 1; 1577 } 1578 average = temp->len; 1579 } 1580 } 1581 1582 if (td_next == NULL) 1583 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1584 1585 /* get next TD */ 1586 1587 td = td_next; 1588 td_next = td->obj_next; 1589 1590 /* check if we are pre-computing */ 1591 1592 if (precompute) { 1593 1594 /* update remaining length */ 1595 1596 temp->len -= average; 1597 1598 continue; 1599 } 1600 /* fill out current TD */ 1601 1602 td->len = average; 1603 td->remainder = 0; 1604 td->status = 0; 1605 1606 /* update remaining length */ 1607 1608 temp->len -= average; 1609 1610 /* reset TRB index */ 1611 1612 x = 0; 1613 1614 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1615 /* immediate data */ 1616 1617 if (average > 8) 1618 average = 8; 1619 1620 td->td_trb[0].qwTrb0 = 0; 1621 1622 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1623 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1624 average); 1625 1626 dword = XHCI_TRB_2_BYTES_SET(8) | 1627 XHCI_TRB_2_TDSZ_SET(0) | 1628 XHCI_TRB_2_IRQ_SET(0); 1629 1630 td->td_trb[0].dwTrb2 = htole32(dword); 1631 1632 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1633 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1634 1635 /* check wLength */ 1636 if (td->td_trb[0].qwTrb0 & 1637 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1638 if (td->td_trb[0].qwTrb0 & htole64(1)) 1639 dword |= XHCI_TRB_3_TRT_IN; 1640 else 1641 dword |= XHCI_TRB_3_TRT_OUT; 1642 } 1643 1644 td->td_trb[0].dwTrb3 = htole32(dword); 1645 #ifdef USB_DEBUG 1646 xhci_dump_trb(&td->td_trb[x]); 1647 #endif 1648 x++; 1649 1650 } else do { 1651 1652 uint32_t npkt; 1653 1654 /* fill out buffer pointers */ 1655 1656 if (average == 0) { 1657 npkt = 1; 1658 memset(&buf_res, 0, sizeof(buf_res)); 1659 } else { 1660 usbd_get_page(temp->pc, temp->offset + 1661 buf_offset, &buf_res); 1662 1663 /* get length to end of page */ 1664 if (buf_res.length > average) 1665 buf_res.length = average; 1666 1667 /* check for maximum length */ 1668 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1669 buf_res.length = XHCI_TD_PAGE_SIZE; 1670 1671 /* setup npkt */ 1672 npkt = (average + temp->max_packet_size - 1) / 1673 temp->max_packet_size; 1674 1675 if (npkt > 31) 1676 npkt = 31; 1677 } 1678 1679 /* fill out TRB's */ 1680 td->td_trb[x].qwTrb0 = 1681 htole64((uint64_t)buf_res.physaddr); 1682 1683 dword = 1684 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1685 XHCI_TRB_2_TDSZ_SET(npkt) | 1686 XHCI_TRB_2_IRQ_SET(0); 1687 1688 td->td_trb[x].dwTrb2 = htole32(dword); 1689 1690 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1691 XHCI_TRB_3_TYPE_SET(temp->trb_type) | 1692 (temp->do_isoc_sync ? 1693 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) : 1694 XHCI_TRB_3_ISO_SIA_BIT) | 1695 XHCI_TRB_3_TBC_SET(temp->tbc) | 1696 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1697 1698 temp->do_isoc_sync = 0; 1699 1700 if (temp->direction == UE_DIR_IN) { 1701 dword |= XHCI_TRB_3_DIR_IN; 1702 1703 /* 1704 * NOTE: Only the SETUP stage should 1705 * use the IDT bit. Else transactions 1706 * can be sent using the wrong data 1707 * toggle value. 1708 */ 1709 if (temp->trb_type != 1710 XHCI_TRB_TYPE_SETUP_STAGE && 1711 temp->trb_type != 1712 XHCI_TRB_TYPE_STATUS_STAGE) 1713 dword |= XHCI_TRB_3_ISP_BIT; 1714 } 1715 1716 td->td_trb[x].dwTrb3 = htole32(dword); 1717 1718 average -= buf_res.length; 1719 buf_offset += buf_res.length; 1720 #ifdef USB_DEBUG 1721 xhci_dump_trb(&td->td_trb[x]); 1722 #endif 1723 x++; 1724 1725 } while (average != 0); 1726 1727 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1728 1729 /* store number of data TRB's */ 1730 1731 td->ntrb = x; 1732 1733 DPRINTF("NTRB=%u\n", x); 1734 1735 /* fill out link TRB */ 1736 1737 if (td_next != NULL) { 1738 /* link the current TD with the next one */ 1739 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1740 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1741 } else { 1742 /* this field will get updated later */ 1743 DPRINTF("NOLINK\n"); 1744 } 1745 1746 dword = XHCI_TRB_2_IRQ_SET(0); 1747 1748 td->td_trb[x].dwTrb2 = htole32(dword); 1749 1750 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1751 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT; 1752 1753 td->td_trb[x].dwTrb3 = htole32(dword); 1754 1755 td->alt_next = td_alt_next; 1756 #ifdef USB_DEBUG 1757 xhci_dump_trb(&td->td_trb[x]); 1758 #endif 1759 usb_pc_cpu_flush(td->page_cache); 1760 } 1761 1762 if (precompute) { 1763 precompute = 0; 1764 1765 /* setup alt next pointer, if any */ 1766 if (temp->last_frame) { 1767 td_alt_next = NULL; 1768 } else { 1769 /* we use this field internally */ 1770 td_alt_next = td_next; 1771 } 1772 1773 /* restore */ 1774 temp->shortpkt = shortpkt_old; 1775 temp->len = len_old; 1776 goto restart; 1777 } 1778 1779 /* remove cycle bit from first if we are stepping the TRBs */ 1780 if (temp->step_td) 1781 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1782 1783 /* remove chain bit because this is the last TRB in the chain */ 1784 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1785 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1786 1787 usb_pc_cpu_flush(td->page_cache); 1788 1789 temp->td = td; 1790 temp->td_next = td_next; 1791 } 1792 1793 static void 1794 xhci_setup_generic_chain(struct usb_xfer *xfer) 1795 { 1796 struct xhci_std_temp temp; 1797 struct xhci_td *td; 1798 uint32_t x; 1799 uint32_t y; 1800 uint8_t mult; 1801 1802 temp.do_isoc_sync = 0; 1803 temp.step_td = 0; 1804 temp.tbc = 0; 1805 temp.tlbpc = 0; 1806 temp.average = xfer->max_hc_frame_size; 1807 temp.max_packet_size = xfer->max_packet_size; 1808 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1809 temp.pc = NULL; 1810 temp.last_frame = 0; 1811 temp.offset = 0; 1812 temp.multishort = xfer->flags_int.isochronous_xfr || 1813 xfer->flags_int.control_xfr || 1814 xfer->flags_int.short_frames_ok; 1815 1816 /* toggle the DMA set we are using */ 1817 xfer->flags_int.curr_dma_set ^= 1; 1818 1819 /* get next DMA set */ 1820 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1821 1822 temp.td = NULL; 1823 temp.td_next = td; 1824 1825 xfer->td_transfer_first = td; 1826 xfer->td_transfer_cache = td; 1827 1828 if (xfer->flags_int.isochronous_xfr) { 1829 uint8_t shift; 1830 1831 /* compute multiplier for ISOCHRONOUS transfers */ 1832 mult = xfer->endpoint->ecomp ? 1833 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 1834 : 0; 1835 /* check for USB 2.0 multiplier */ 1836 if (mult == 0) { 1837 mult = (xfer->endpoint->edesc-> 1838 wMaxPacketSize[1] >> 3) & 3; 1839 } 1840 /* range check */ 1841 if (mult > 2) 1842 mult = 3; 1843 else 1844 mult++; 1845 1846 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 1847 1848 DPRINTF("MFINDEX=0x%08x\n", x); 1849 1850 switch (usbd_get_speed(xfer->xroot->udev)) { 1851 case USB_SPEED_FULL: 1852 shift = 3; 1853 temp.isoc_delta = 8; /* 1ms */ 1854 x += temp.isoc_delta - 1; 1855 x &= ~(temp.isoc_delta - 1); 1856 break; 1857 default: 1858 shift = usbd_xfer_get_fps_shift(xfer); 1859 temp.isoc_delta = 1U << shift; 1860 x += temp.isoc_delta - 1; 1861 x &= ~(temp.isoc_delta - 1); 1862 /* simple frame load balancing */ 1863 x += xfer->endpoint->usb_uframe; 1864 break; 1865 } 1866 1867 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 1868 1869 if ((xfer->endpoint->is_synced == 0) || 1870 (y < (xfer->nframes << shift)) || 1871 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 1872 /* 1873 * If there is data underflow or the pipe 1874 * queue is empty we schedule the transfer a 1875 * few frames ahead of the current frame 1876 * position. Else two isochronous transfers 1877 * might overlap. 1878 */ 1879 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 1880 xfer->endpoint->is_synced = 1; 1881 temp.do_isoc_sync = 1; 1882 1883 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1884 } 1885 1886 /* compute isochronous completion time */ 1887 1888 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 1889 1890 xfer->isoc_time_complete = 1891 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 1892 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 1893 1894 x = 0; 1895 temp.isoc_frame = xfer->endpoint->isoc_next; 1896 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 1897 1898 xfer->endpoint->isoc_next += xfer->nframes << shift; 1899 1900 } else if (xfer->flags_int.control_xfr) { 1901 1902 /* check if we should prepend a setup message */ 1903 1904 if (xfer->flags_int.control_hdr) { 1905 1906 temp.len = xfer->frlengths[0]; 1907 temp.pc = xfer->frbuffers + 0; 1908 temp.shortpkt = temp.len ? 1 : 0; 1909 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 1910 temp.direction = 0; 1911 1912 /* check for last frame */ 1913 if (xfer->nframes == 1) { 1914 /* no STATUS stage yet, SETUP is last */ 1915 if (xfer->flags_int.control_act) 1916 temp.last_frame = 1; 1917 } 1918 1919 xhci_setup_generic_chain_sub(&temp); 1920 } 1921 x = 1; 1922 mult = 1; 1923 temp.isoc_delta = 0; 1924 temp.isoc_frame = 0; 1925 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 1926 } else { 1927 x = 0; 1928 mult = 1; 1929 temp.isoc_delta = 0; 1930 temp.isoc_frame = 0; 1931 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 1932 } 1933 1934 if (x != xfer->nframes) { 1935 /* setup page_cache pointer */ 1936 temp.pc = xfer->frbuffers + x; 1937 /* set endpoint direction */ 1938 temp.direction = UE_GET_DIR(xfer->endpointno); 1939 } 1940 1941 while (x != xfer->nframes) { 1942 1943 /* DATA0 / DATA1 message */ 1944 1945 temp.len = xfer->frlengths[x]; 1946 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 1947 x != 0 && temp.multishort == 0); 1948 1949 x++; 1950 1951 if (x == xfer->nframes) { 1952 if (xfer->flags_int.control_xfr) { 1953 /* no STATUS stage yet, DATA is last */ 1954 if (xfer->flags_int.control_act) 1955 temp.last_frame = 1; 1956 } else { 1957 temp.last_frame = 1; 1958 } 1959 } 1960 if (temp.len == 0) { 1961 1962 /* make sure that we send an USB packet */ 1963 1964 temp.shortpkt = 0; 1965 1966 temp.tbc = 0; 1967 temp.tlbpc = mult - 1; 1968 1969 } else if (xfer->flags_int.isochronous_xfr) { 1970 1971 uint8_t tdpc; 1972 1973 /* 1974 * Isochronous transfers don't have short 1975 * packet termination: 1976 */ 1977 1978 temp.shortpkt = 1; 1979 1980 /* isochronous transfers have a transfer limit */ 1981 1982 if (temp.len > xfer->max_frame_size) 1983 temp.len = xfer->max_frame_size; 1984 1985 /* compute TD packet count */ 1986 tdpc = (temp.len + xfer->max_packet_size - 1) / 1987 xfer->max_packet_size; 1988 1989 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 1990 temp.tlbpc = (tdpc % mult); 1991 1992 if (temp.tlbpc == 0) 1993 temp.tlbpc = mult - 1; 1994 else 1995 temp.tlbpc--; 1996 } else { 1997 1998 /* regular data transfer */ 1999 2000 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2001 } 2002 2003 xhci_setup_generic_chain_sub(&temp); 2004 2005 if (xfer->flags_int.isochronous_xfr) { 2006 temp.offset += xfer->frlengths[x - 1]; 2007 temp.isoc_frame += temp.isoc_delta; 2008 } else { 2009 /* get next Page Cache pointer */ 2010 temp.pc = xfer->frbuffers + x; 2011 } 2012 } 2013 2014 /* check if we should append a status stage */ 2015 2016 if (xfer->flags_int.control_xfr && 2017 !xfer->flags_int.control_act) { 2018 2019 /* 2020 * Send a DATA1 message and invert the current 2021 * endpoint direction. 2022 */ 2023 temp.step_td = (xfer->nframes != 0); 2024 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2025 temp.len = 0; 2026 temp.pc = NULL; 2027 temp.shortpkt = 0; 2028 temp.last_frame = 1; 2029 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2030 2031 xhci_setup_generic_chain_sub(&temp); 2032 } 2033 2034 td = temp.td; 2035 2036 /* must have at least one frame! */ 2037 2038 xfer->td_transfer_last = td; 2039 2040 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2041 } 2042 2043 static void 2044 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2045 { 2046 struct usb_page_search buf_res; 2047 struct xhci_dev_ctx_addr *pdctxa; 2048 2049 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2050 2051 pdctxa = buf_res.buffer; 2052 2053 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2054 2055 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2056 2057 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2058 } 2059 2060 static usb_error_t 2061 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2062 { 2063 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2064 struct usb_page_search buf_inp; 2065 struct xhci_input_dev_ctx *pinp; 2066 uint32_t temp; 2067 uint8_t index; 2068 uint8_t x; 2069 2070 index = udev->controller_slot_id; 2071 2072 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2073 2074 pinp = buf_inp.buffer; 2075 2076 if (drop) { 2077 mask &= XHCI_INCTX_NON_CTRL_MASK; 2078 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2079 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2080 } else { 2081 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2082 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2083 2084 /* find most significant set bit */ 2085 for (x = 31; x != 1; x--) { 2086 if (mask & (1 << x)) 2087 break; 2088 } 2089 2090 /* adjust */ 2091 x--; 2092 2093 /* figure out maximum */ 2094 if (x > sc->sc_hw.devs[index].context_num) { 2095 sc->sc_hw.devs[index].context_num = x; 2096 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2097 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2098 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2099 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2100 } 2101 } 2102 return (0); 2103 } 2104 2105 static usb_error_t 2106 xhci_configure_endpoint(struct usb_device *udev, 2107 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr, 2108 uint16_t interval, uint8_t max_packet_count, uint8_t mult, 2109 uint8_t fps_shift, uint16_t max_packet_size, 2110 uint16_t max_frame_size, uint8_t ep_mode) 2111 { 2112 struct usb_page_search buf_inp; 2113 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2114 struct xhci_input_dev_ctx *pinp; 2115 uint32_t temp; 2116 uint8_t index; 2117 uint8_t epno; 2118 uint8_t type; 2119 2120 index = udev->controller_slot_id; 2121 2122 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2123 2124 pinp = buf_inp.buffer; 2125 2126 epno = edesc->bEndpointAddress; 2127 type = edesc->bmAttributes & UE_XFERTYPE; 2128 2129 if (type == UE_CONTROL) 2130 epno |= UE_DIR_IN; 2131 2132 epno = XHCI_EPNO2EPID(epno); 2133 2134 if (epno == 0) 2135 return (USB_ERR_NO_PIPE); /* invalid */ 2136 2137 if (max_packet_count == 0) 2138 return (USB_ERR_BAD_BUFSIZE); 2139 2140 max_packet_count--; 2141 2142 if (mult == 0) 2143 return (USB_ERR_BAD_BUFSIZE); 2144 2145 if (ep_mode == USB_EP_MODE_STREAMS) { 2146 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2147 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2148 XHCI_EPCTX_0_LSA_SET(1); 2149 2150 ring_addr += sizeof(struct xhci_trb) * 2151 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2152 } else { 2153 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2154 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2155 XHCI_EPCTX_0_LSA_SET(0); 2156 2157 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2158 } 2159 2160 switch (udev->speed) { 2161 case USB_SPEED_FULL: 2162 case USB_SPEED_LOW: 2163 /* 1ms -> 125us */ 2164 fps_shift += 3; 2165 break; 2166 default: 2167 break; 2168 } 2169 2170 switch (type) { 2171 case UE_INTERRUPT: 2172 if (fps_shift > 3) 2173 fps_shift--; 2174 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2175 break; 2176 case UE_ISOCHRONOUS: 2177 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2178 2179 switch (udev->speed) { 2180 case USB_SPEED_SUPER: 2181 if (mult > 3) 2182 mult = 3; 2183 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2184 max_packet_count /= mult; 2185 break; 2186 default: 2187 break; 2188 } 2189 break; 2190 default: 2191 break; 2192 } 2193 2194 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2195 2196 temp = 2197 XHCI_EPCTX_1_HID_SET(0) | 2198 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2199 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2200 2201 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2202 if (type != UE_ISOCHRONOUS) 2203 temp |= XHCI_EPCTX_1_CERR_SET(3); 2204 } 2205 2206 switch (type) { 2207 case UE_CONTROL: 2208 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2209 break; 2210 case UE_ISOCHRONOUS: 2211 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2212 break; 2213 case UE_BULK: 2214 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2215 break; 2216 default: 2217 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2218 break; 2219 } 2220 2221 /* check for IN direction */ 2222 if (epno & 1) 2223 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2224 2225 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2226 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2227 2228 switch (edesc->bmAttributes & UE_XFERTYPE) { 2229 case UE_INTERRUPT: 2230 case UE_ISOCHRONOUS: 2231 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2232 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2233 max_frame_size)); 2234 break; 2235 case UE_CONTROL: 2236 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2237 break; 2238 default: 2239 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2240 break; 2241 } 2242 2243 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2244 2245 #ifdef USB_DEBUG 2246 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2247 #endif 2248 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2249 2250 return (0); /* success */ 2251 } 2252 2253 static usb_error_t 2254 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2255 { 2256 struct xhci_endpoint_ext *pepext; 2257 struct usb_endpoint_ss_comp_descriptor *ecomp; 2258 usb_stream_t x; 2259 2260 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2261 xfer->endpoint->edesc); 2262 2263 ecomp = xfer->endpoint->ecomp; 2264 2265 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2266 uint64_t temp; 2267 2268 /* halt any transfers */ 2269 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2270 2271 /* compute start of TRB ring for stream "x" */ 2272 temp = pepext->physaddr + 2273 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2274 XHCI_SCTX_0_SCT_SEC_TR_RING; 2275 2276 /* make tree structure */ 2277 pepext->trb[(XHCI_MAX_TRANSFERS * 2278 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2279 2280 /* reserved fields */ 2281 pepext->trb[(XHCI_MAX_TRANSFERS * 2282 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2283 pepext->trb[(XHCI_MAX_TRANSFERS * 2284 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2285 } 2286 usb_pc_cpu_flush(pepext->page_cache); 2287 2288 return (xhci_configure_endpoint(xfer->xroot->udev, 2289 xfer->endpoint->edesc, pepext->physaddr, 2290 xfer->interval, xfer->max_packet_count, 2291 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2292 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2293 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2294 } 2295 2296 static usb_error_t 2297 xhci_configure_device(struct usb_device *udev) 2298 { 2299 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2300 struct usb_page_search buf_inp; 2301 struct usb_page_cache *pcinp; 2302 struct xhci_input_dev_ctx *pinp; 2303 struct usb_device *hubdev; 2304 uint32_t temp; 2305 uint32_t route; 2306 uint32_t rh_port; 2307 uint8_t is_hub; 2308 uint8_t index; 2309 uint8_t depth; 2310 2311 index = udev->controller_slot_id; 2312 2313 DPRINTF("index=%u\n", index); 2314 2315 pcinp = &sc->sc_hw.devs[index].input_pc; 2316 2317 usbd_get_page(pcinp, 0, &buf_inp); 2318 2319 pinp = buf_inp.buffer; 2320 2321 rh_port = 0; 2322 route = 0; 2323 2324 /* figure out route string and root HUB port number */ 2325 2326 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2327 2328 if (hubdev->parent_hub == NULL) 2329 break; 2330 2331 depth = hubdev->parent_hub->depth; 2332 2333 /* 2334 * NOTE: HS/FS/LS devices and the SS root HUB can have 2335 * more than 15 ports 2336 */ 2337 2338 rh_port = hubdev->port_no; 2339 2340 if (depth == 0) 2341 break; 2342 2343 if (rh_port > 15) 2344 rh_port = 15; 2345 2346 if (depth < 6) 2347 route |= rh_port << (4 * (depth - 1)); 2348 } 2349 2350 DPRINTF("Route=0x%08x\n", route); 2351 2352 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2353 XHCI_SCTX_0_CTX_NUM_SET( 2354 sc->sc_hw.devs[index].context_num + 1); 2355 2356 switch (udev->speed) { 2357 case USB_SPEED_LOW: 2358 temp |= XHCI_SCTX_0_SPEED_SET(2); 2359 if (udev->parent_hs_hub != NULL && 2360 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2361 UDPROTO_HSHUBMTT) { 2362 DPRINTF("Device inherits MTT\n"); 2363 temp |= XHCI_SCTX_0_MTT_SET(1); 2364 } 2365 break; 2366 case USB_SPEED_HIGH: 2367 temp |= XHCI_SCTX_0_SPEED_SET(3); 2368 if (sc->sc_hw.devs[index].nports != 0 && 2369 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2370 DPRINTF("HUB supports MTT\n"); 2371 temp |= XHCI_SCTX_0_MTT_SET(1); 2372 } 2373 break; 2374 case USB_SPEED_FULL: 2375 temp |= XHCI_SCTX_0_SPEED_SET(1); 2376 if (udev->parent_hs_hub != NULL && 2377 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2378 UDPROTO_HSHUBMTT) { 2379 DPRINTF("Device inherits MTT\n"); 2380 temp |= XHCI_SCTX_0_MTT_SET(1); 2381 } 2382 break; 2383 default: 2384 temp |= XHCI_SCTX_0_SPEED_SET(4); 2385 break; 2386 } 2387 2388 is_hub = sc->sc_hw.devs[index].nports != 0 && 2389 (udev->speed == USB_SPEED_SUPER || 2390 udev->speed == USB_SPEED_HIGH); 2391 2392 if (is_hub) 2393 temp |= XHCI_SCTX_0_HUB_SET(1); 2394 2395 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2396 2397 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2398 2399 if (is_hub) { 2400 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2401 sc->sc_hw.devs[index].nports); 2402 } 2403 2404 switch (udev->speed) { 2405 case USB_SPEED_SUPER: 2406 switch (sc->sc_hw.devs[index].state) { 2407 case XHCI_ST_ADDRESSED: 2408 case XHCI_ST_CONFIGURED: 2409 /* enable power save */ 2410 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2411 break; 2412 default: 2413 /* disable power save */ 2414 break; 2415 } 2416 break; 2417 default: 2418 break; 2419 } 2420 2421 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2422 2423 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2424 2425 if (is_hub) { 2426 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2427 sc->sc_hw.devs[index].tt); 2428 } 2429 2430 hubdev = udev->parent_hs_hub; 2431 2432 /* check if we should activate the transaction translator */ 2433 switch (udev->speed) { 2434 case USB_SPEED_FULL: 2435 case USB_SPEED_LOW: 2436 if (hubdev != NULL) { 2437 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2438 hubdev->controller_slot_id); 2439 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2440 udev->hs_port_no); 2441 } 2442 break; 2443 default: 2444 break; 2445 } 2446 2447 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2448 2449 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) | 2450 XHCI_SCTX_3_SLOT_STATE_SET(0); 2451 2452 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2453 2454 #ifdef USB_DEBUG 2455 xhci_dump_device(sc, &pinp->ctx_slot); 2456 #endif 2457 usb_pc_cpu_flush(pcinp); 2458 2459 return (0); /* success */ 2460 } 2461 2462 static usb_error_t 2463 xhci_alloc_device_ext(struct usb_device *udev) 2464 { 2465 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2466 struct usb_page_search buf_dev; 2467 struct usb_page_search buf_ep; 2468 struct xhci_trb *trb; 2469 struct usb_page_cache *pc; 2470 struct usb_page *pg; 2471 uint64_t addr; 2472 uint8_t index; 2473 uint8_t i; 2474 2475 index = udev->controller_slot_id; 2476 2477 pc = &sc->sc_hw.devs[index].device_pc; 2478 pg = &sc->sc_hw.devs[index].device_pg; 2479 2480 /* need to initialize the page cache */ 2481 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2482 2483 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2484 (2 * sizeof(struct xhci_dev_ctx)) : 2485 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2486 goto error; 2487 2488 usbd_get_page(pc, 0, &buf_dev); 2489 2490 pc = &sc->sc_hw.devs[index].input_pc; 2491 pg = &sc->sc_hw.devs[index].input_pg; 2492 2493 /* need to initialize the page cache */ 2494 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2495 2496 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2497 (2 * sizeof(struct xhci_input_dev_ctx)) : 2498 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2499 goto error; 2500 } 2501 2502 pc = &sc->sc_hw.devs[index].endpoint_pc; 2503 pg = &sc->sc_hw.devs[index].endpoint_pg; 2504 2505 /* need to initialize the page cache */ 2506 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2507 2508 if (usb_pc_alloc_mem(pc, pg, 2509 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) { 2510 goto error; 2511 } 2512 2513 /* initialise all endpoint LINK TRBs */ 2514 2515 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2516 2517 /* lookup endpoint TRB ring */ 2518 usbd_get_page(pc, (uintptr_t)& 2519 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2520 2521 /* get TRB pointer */ 2522 trb = buf_ep.buffer; 2523 trb += XHCI_MAX_TRANSFERS - 1; 2524 2525 /* get TRB start address */ 2526 addr = buf_ep.physaddr; 2527 2528 /* create LINK TRB */ 2529 trb->qwTrb0 = htole64(addr); 2530 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2531 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2532 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2533 } 2534 2535 usb_pc_cpu_flush(pc); 2536 2537 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2538 2539 return (0); 2540 2541 error: 2542 xhci_free_device_ext(udev); 2543 2544 return (USB_ERR_NOMEM); 2545 } 2546 2547 static void 2548 xhci_free_device_ext(struct usb_device *udev) 2549 { 2550 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2551 uint8_t index; 2552 2553 index = udev->controller_slot_id; 2554 xhci_set_slot_pointer(sc, index, 0); 2555 2556 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2557 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2558 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2559 } 2560 2561 static struct xhci_endpoint_ext * 2562 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2563 { 2564 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2565 struct xhci_endpoint_ext *pepext; 2566 struct usb_page_cache *pc; 2567 struct usb_page_search buf_ep; 2568 uint8_t epno; 2569 uint8_t index; 2570 2571 epno = edesc->bEndpointAddress; 2572 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2573 epno |= UE_DIR_IN; 2574 2575 epno = XHCI_EPNO2EPID(epno); 2576 2577 index = udev->controller_slot_id; 2578 2579 pc = &sc->sc_hw.devs[index].endpoint_pc; 2580 2581 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2582 trb[epno][0], &buf_ep); 2583 2584 pepext = &sc->sc_hw.devs[index].endp[epno]; 2585 pepext->page_cache = pc; 2586 pepext->trb = buf_ep.buffer; 2587 pepext->physaddr = buf_ep.physaddr; 2588 2589 return (pepext); 2590 } 2591 2592 static void 2593 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2594 { 2595 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2596 uint8_t epno; 2597 uint8_t index; 2598 2599 epno = xfer->endpointno; 2600 if (xfer->flags_int.control_xfr) 2601 epno |= UE_DIR_IN; 2602 2603 epno = XHCI_EPNO2EPID(epno); 2604 index = xfer->xroot->udev->controller_slot_id; 2605 2606 if (xfer->xroot->udev->flags.self_suspended == 0) { 2607 XWRITE4(sc, door, XHCI_DOORBELL(index), 2608 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2609 } 2610 } 2611 2612 static void 2613 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2614 { 2615 struct xhci_endpoint_ext *pepext; 2616 2617 if (xfer->flags_int.bandwidth_reclaimed) { 2618 xfer->flags_int.bandwidth_reclaimed = 0; 2619 2620 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2621 xfer->endpoint->edesc); 2622 2623 pepext->trb_used[xfer->stream_id]--; 2624 2625 pepext->xfer[xfer->qh_pos] = NULL; 2626 2627 if (error && pepext->trb_running != 0) { 2628 pepext->trb_halted = 1; 2629 pepext->trb_running = 0; 2630 } 2631 } 2632 } 2633 2634 static usb_error_t 2635 xhci_transfer_insert(struct usb_xfer *xfer) 2636 { 2637 struct xhci_td *td_first; 2638 struct xhci_td *td_last; 2639 struct xhci_endpoint_ext *pepext; 2640 uint64_t addr; 2641 usb_stream_t id; 2642 uint8_t i; 2643 uint8_t inext; 2644 uint8_t trb_limit; 2645 2646 DPRINTFN(8, "\n"); 2647 2648 id = xfer->stream_id; 2649 2650 /* check if already inserted */ 2651 if (xfer->flags_int.bandwidth_reclaimed) { 2652 DPRINTFN(8, "Already in schedule\n"); 2653 return (0); 2654 } 2655 2656 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2657 xfer->endpoint->edesc); 2658 2659 td_first = xfer->td_transfer_first; 2660 td_last = xfer->td_transfer_last; 2661 addr = pepext->physaddr; 2662 2663 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2664 case UE_CONTROL: 2665 case UE_INTERRUPT: 2666 /* single buffered */ 2667 trb_limit = 1; 2668 break; 2669 default: 2670 /* multi buffered */ 2671 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2672 break; 2673 } 2674 2675 if (pepext->trb_used[id] >= trb_limit) { 2676 DPRINTFN(8, "Too many TDs queued.\n"); 2677 return (USB_ERR_NOMEM); 2678 } 2679 2680 /* check for stopped condition, after putting transfer on interrupt queue */ 2681 if (pepext->trb_running == 0) { 2682 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2683 2684 DPRINTFN(8, "Not running\n"); 2685 2686 /* start configuration */ 2687 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2688 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2689 return (0); 2690 } 2691 2692 pepext->trb_used[id]++; 2693 2694 /* get current TRB index */ 2695 i = pepext->trb_index[id]; 2696 2697 /* get next TRB index */ 2698 inext = (i + 1); 2699 2700 /* the last entry of the ring is a hardcoded link TRB */ 2701 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2702 inext = 0; 2703 2704 /* offset for stream */ 2705 i += id * XHCI_MAX_TRANSFERS; 2706 inext += id * XHCI_MAX_TRANSFERS; 2707 2708 /* compute terminating return address */ 2709 addr += (inext * sizeof(struct xhci_trb)); 2710 2711 /* update next pointer of last link TRB */ 2712 td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr); 2713 td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2714 td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2715 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2716 2717 #ifdef USB_DEBUG 2718 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2719 #endif 2720 usb_pc_cpu_flush(td_last->page_cache); 2721 2722 /* write ahead chain end marker */ 2723 2724 pepext->trb[inext].qwTrb0 = 0; 2725 pepext->trb[inext].dwTrb2 = 0; 2726 pepext->trb[inext].dwTrb3 = 0; 2727 2728 /* update next pointer of link TRB */ 2729 2730 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2731 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2732 2733 #ifdef USB_DEBUG 2734 xhci_dump_trb(&pepext->trb[i]); 2735 #endif 2736 usb_pc_cpu_flush(pepext->page_cache); 2737 2738 /* toggle cycle bit which activates the transfer chain */ 2739 2740 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2741 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2742 2743 usb_pc_cpu_flush(pepext->page_cache); 2744 2745 DPRINTF("qh_pos = %u\n", i); 2746 2747 pepext->xfer[i] = xfer; 2748 2749 xfer->qh_pos = i; 2750 2751 xfer->flags_int.bandwidth_reclaimed = 1; 2752 2753 pepext->trb_index[id] = inext; 2754 2755 xhci_endpoint_doorbell(xfer); 2756 2757 return (0); 2758 } 2759 2760 static void 2761 xhci_root_intr(struct xhci_softc *sc) 2762 { 2763 uint16_t i; 2764 2765 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2766 2767 /* clear any old interrupt data */ 2768 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2769 2770 for (i = 1; i <= sc->sc_noport; i++) { 2771 /* pick out CHANGE bits from the status register */ 2772 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2773 XHCI_PS_CSC | XHCI_PS_PEC | 2774 XHCI_PS_OCC | XHCI_PS_WRC | 2775 XHCI_PS_PRC | XHCI_PS_PLC | 2776 XHCI_PS_CEC)) { 2777 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2778 DPRINTF("port %d changed\n", i); 2779 } 2780 } 2781 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2782 sizeof(sc->sc_hub_idata)); 2783 } 2784 2785 /*------------------------------------------------------------------------* 2786 * xhci_device_done - XHCI done handler 2787 * 2788 * NOTE: This function can be called two times in a row on 2789 * the same USB transfer. From close and from interrupt. 2790 *------------------------------------------------------------------------*/ 2791 static void 2792 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2793 { 2794 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2795 xfer, xfer->endpoint, error); 2796 2797 /* remove transfer from HW queue */ 2798 xhci_transfer_remove(xfer, error); 2799 2800 /* dequeue transfer and start next transfer */ 2801 usbd_transfer_done(xfer, error); 2802 } 2803 2804 /*------------------------------------------------------------------------* 2805 * XHCI data transfer support (generic type) 2806 *------------------------------------------------------------------------*/ 2807 static void 2808 xhci_device_generic_open(struct usb_xfer *xfer) 2809 { 2810 if (xfer->flags_int.isochronous_xfr) { 2811 switch (xfer->xroot->udev->speed) { 2812 case USB_SPEED_FULL: 2813 break; 2814 default: 2815 usb_hs_bandwidth_alloc(xfer); 2816 break; 2817 } 2818 } 2819 } 2820 2821 static void 2822 xhci_device_generic_close(struct usb_xfer *xfer) 2823 { 2824 DPRINTF("\n"); 2825 2826 xhci_device_done(xfer, USB_ERR_CANCELLED); 2827 2828 if (xfer->flags_int.isochronous_xfr) { 2829 switch (xfer->xroot->udev->speed) { 2830 case USB_SPEED_FULL: 2831 break; 2832 default: 2833 usb_hs_bandwidth_free(xfer); 2834 break; 2835 } 2836 } 2837 } 2838 2839 static void 2840 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 2841 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 2842 { 2843 struct usb_xfer *xfer; 2844 2845 /* check if there is a current transfer */ 2846 xfer = ep->endpoint_q[stream_id].curr; 2847 if (xfer == NULL) 2848 return; 2849 2850 /* 2851 * Check if the current transfer is started and then pickup 2852 * the next one, if any. Else wait for next start event due to 2853 * block on failure feature. 2854 */ 2855 if (!xfer->flags_int.bandwidth_reclaimed) 2856 return; 2857 2858 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 2859 if (xfer == NULL) { 2860 /* 2861 * In case of enter we have to consider that the 2862 * transfer is queued by the USB core after the enter 2863 * method is called. 2864 */ 2865 xfer = enter_xfer; 2866 2867 if (xfer == NULL) 2868 return; 2869 } 2870 2871 /* try to multi buffer */ 2872 xhci_transfer_insert(xfer); 2873 } 2874 2875 static void 2876 xhci_device_generic_enter(struct usb_xfer *xfer) 2877 { 2878 DPRINTF("\n"); 2879 2880 /* setup TD's and QH */ 2881 xhci_setup_generic_chain(xfer); 2882 2883 xhci_device_generic_multi_enter(xfer->endpoint, 2884 xfer->stream_id, xfer); 2885 } 2886 2887 static void 2888 xhci_device_generic_start(struct usb_xfer *xfer) 2889 { 2890 DPRINTF("\n"); 2891 2892 /* try to insert xfer on HW queue */ 2893 xhci_transfer_insert(xfer); 2894 2895 /* try to multi buffer */ 2896 xhci_device_generic_multi_enter(xfer->endpoint, 2897 xfer->stream_id, NULL); 2898 2899 /* add transfer last on interrupt queue */ 2900 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2901 2902 /* start timeout, if any */ 2903 if (xfer->timeout != 0) 2904 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 2905 } 2906 2907 struct usb_pipe_methods xhci_device_generic_methods = 2908 { 2909 .open = xhci_device_generic_open, 2910 .close = xhci_device_generic_close, 2911 .enter = xhci_device_generic_enter, 2912 .start = xhci_device_generic_start, 2913 }; 2914 2915 /*------------------------------------------------------------------------* 2916 * xhci root HUB support 2917 *------------------------------------------------------------------------* 2918 * Simulate a hardware HUB by handling all the necessary requests. 2919 *------------------------------------------------------------------------*/ 2920 2921 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 2922 2923 static const 2924 struct usb_device_descriptor xhci_devd = 2925 { 2926 .bLength = sizeof(xhci_devd), 2927 .bDescriptorType = UDESC_DEVICE, /* type */ 2928 HSETW(.bcdUSB, 0x0300), /* USB version */ 2929 .bDeviceClass = UDCLASS_HUB, /* class */ 2930 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 2931 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 2932 .bMaxPacketSize = 9, /* max packet size */ 2933 HSETW(.idVendor, 0x0000), /* vendor */ 2934 HSETW(.idProduct, 0x0000), /* product */ 2935 HSETW(.bcdDevice, 0x0100), /* device version */ 2936 .iManufacturer = 1, 2937 .iProduct = 2, 2938 .iSerialNumber = 0, 2939 .bNumConfigurations = 1, /* # of configurations */ 2940 }; 2941 2942 static const 2943 struct xhci_bos_desc xhci_bosd = { 2944 .bosd = { 2945 .bLength = sizeof(xhci_bosd.bosd), 2946 .bDescriptorType = UDESC_BOS, 2947 HSETW(.wTotalLength, sizeof(xhci_bosd)), 2948 .bNumDeviceCaps = 3, 2949 }, 2950 .usb2extd = { 2951 .bLength = sizeof(xhci_bosd.usb2extd), 2952 .bDescriptorType = 1, 2953 .bDevCapabilityType = 2, 2954 .bmAttributes[0] = 2, 2955 }, 2956 .usbdcd = { 2957 .bLength = sizeof(xhci_bosd.usbdcd), 2958 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 2959 .bDevCapabilityType = 3, 2960 .bmAttributes = 0, /* XXX */ 2961 HSETW(.wSpeedsSupported, 0x000C), 2962 .bFunctionalitySupport = 8, 2963 .bU1DevExitLat = 255, /* dummy - not used */ 2964 .wU2DevExitLat = { 0x00, 0x08 }, 2965 }, 2966 .cidd = { 2967 .bLength = sizeof(xhci_bosd.cidd), 2968 .bDescriptorType = 1, 2969 .bDevCapabilityType = 4, 2970 .bReserved = 0, 2971 .bContainerID = 0, /* XXX */ 2972 }, 2973 }; 2974 2975 static const 2976 struct xhci_config_desc xhci_confd = { 2977 .confd = { 2978 .bLength = sizeof(xhci_confd.confd), 2979 .bDescriptorType = UDESC_CONFIG, 2980 .wTotalLength[0] = sizeof(xhci_confd), 2981 .bNumInterface = 1, 2982 .bConfigurationValue = 1, 2983 .iConfiguration = 0, 2984 .bmAttributes = UC_SELF_POWERED, 2985 .bMaxPower = 0 /* max power */ 2986 }, 2987 .ifcd = { 2988 .bLength = sizeof(xhci_confd.ifcd), 2989 .bDescriptorType = UDESC_INTERFACE, 2990 .bNumEndpoints = 1, 2991 .bInterfaceClass = UICLASS_HUB, 2992 .bInterfaceSubClass = UISUBCLASS_HUB, 2993 .bInterfaceProtocol = 0, 2994 }, 2995 .endpd = { 2996 .bLength = sizeof(xhci_confd.endpd), 2997 .bDescriptorType = UDESC_ENDPOINT, 2998 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 2999 .bmAttributes = UE_INTERRUPT, 3000 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3001 .bInterval = 255, 3002 }, 3003 .endpcd = { 3004 .bLength = sizeof(xhci_confd.endpcd), 3005 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3006 .bMaxBurst = 0, 3007 .bmAttributes = 0, 3008 }, 3009 }; 3010 3011 static const 3012 struct usb_hub_ss_descriptor xhci_hubd = { 3013 .bLength = sizeof(xhci_hubd), 3014 .bDescriptorType = UDESC_SS_HUB, 3015 }; 3016 3017 static usb_error_t 3018 xhci_roothub_exec(struct usb_device *udev, 3019 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3020 { 3021 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3022 const char *str_ptr; 3023 const void *ptr; 3024 uint32_t port; 3025 uint32_t v; 3026 uint16_t len; 3027 uint16_t i; 3028 uint16_t value; 3029 uint16_t index; 3030 uint8_t j; 3031 usb_error_t err; 3032 3033 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3034 3035 /* buffer reset */ 3036 ptr = (const void *)&sc->sc_hub_desc; 3037 len = 0; 3038 err = 0; 3039 3040 value = UGETW(req->wValue); 3041 index = UGETW(req->wIndex); 3042 3043 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3044 "wValue=0x%04x wIndex=0x%04x\n", 3045 req->bmRequestType, req->bRequest, 3046 UGETW(req->wLength), value, index); 3047 3048 #define C(x,y) ((x) | ((y) << 8)) 3049 switch (C(req->bRequest, req->bmRequestType)) { 3050 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3051 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3052 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3053 /* 3054 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3055 * for the integrated root hub. 3056 */ 3057 break; 3058 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3059 len = 1; 3060 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3061 break; 3062 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3063 switch (value >> 8) { 3064 case UDESC_DEVICE: 3065 if ((value & 0xff) != 0) { 3066 err = USB_ERR_IOERROR; 3067 goto done; 3068 } 3069 len = sizeof(xhci_devd); 3070 ptr = (const void *)&xhci_devd; 3071 break; 3072 3073 case UDESC_BOS: 3074 if ((value & 0xff) != 0) { 3075 err = USB_ERR_IOERROR; 3076 goto done; 3077 } 3078 len = sizeof(xhci_bosd); 3079 ptr = (const void *)&xhci_bosd; 3080 break; 3081 3082 case UDESC_CONFIG: 3083 if ((value & 0xff) != 0) { 3084 err = USB_ERR_IOERROR; 3085 goto done; 3086 } 3087 len = sizeof(xhci_confd); 3088 ptr = (const void *)&xhci_confd; 3089 break; 3090 3091 case UDESC_STRING: 3092 switch (value & 0xff) { 3093 case 0: /* Language table */ 3094 str_ptr = "\001"; 3095 break; 3096 3097 case 1: /* Vendor */ 3098 str_ptr = sc->sc_vendor; 3099 break; 3100 3101 case 2: /* Product */ 3102 str_ptr = "XHCI root HUB"; 3103 break; 3104 3105 default: 3106 str_ptr = ""; 3107 break; 3108 } 3109 3110 len = usb_make_str_desc( 3111 sc->sc_hub_desc.temp, 3112 sizeof(sc->sc_hub_desc.temp), 3113 str_ptr); 3114 break; 3115 3116 default: 3117 err = USB_ERR_IOERROR; 3118 goto done; 3119 } 3120 break; 3121 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3122 len = 1; 3123 sc->sc_hub_desc.temp[0] = 0; 3124 break; 3125 case C(UR_GET_STATUS, UT_READ_DEVICE): 3126 len = 2; 3127 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3128 break; 3129 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3130 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3131 len = 2; 3132 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3133 break; 3134 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3135 if (value >= XHCI_MAX_DEVICES) { 3136 err = USB_ERR_IOERROR; 3137 goto done; 3138 } 3139 break; 3140 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3141 if (value != 0 && value != 1) { 3142 err = USB_ERR_IOERROR; 3143 goto done; 3144 } 3145 sc->sc_conf = value; 3146 break; 3147 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3148 break; 3149 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3150 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3151 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3152 err = USB_ERR_IOERROR; 3153 goto done; 3154 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3155 break; 3156 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3157 break; 3158 /* Hub requests */ 3159 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3160 break; 3161 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3162 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3163 3164 if ((index < 1) || 3165 (index > sc->sc_noport)) { 3166 err = USB_ERR_IOERROR; 3167 goto done; 3168 } 3169 port = XHCI_PORTSC(index); 3170 3171 v = XREAD4(sc, oper, port); 3172 i = XHCI_PS_PLS_GET(v); 3173 v &= ~XHCI_PS_CLEAR; 3174 3175 switch (value) { 3176 case UHF_C_BH_PORT_RESET: 3177 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3178 break; 3179 case UHF_C_PORT_CONFIG_ERROR: 3180 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3181 break; 3182 case UHF_C_PORT_SUSPEND: 3183 case UHF_C_PORT_LINK_STATE: 3184 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3185 break; 3186 case UHF_C_PORT_CONNECTION: 3187 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3188 break; 3189 case UHF_C_PORT_ENABLE: 3190 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3191 break; 3192 case UHF_C_PORT_OVER_CURRENT: 3193 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3194 break; 3195 case UHF_C_PORT_RESET: 3196 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3197 break; 3198 case UHF_PORT_ENABLE: 3199 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3200 break; 3201 case UHF_PORT_POWER: 3202 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3203 break; 3204 case UHF_PORT_INDICATOR: 3205 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3206 break; 3207 case UHF_PORT_SUSPEND: 3208 3209 /* U3 -> U15 */ 3210 if (i == 3) { 3211 XWRITE4(sc, oper, port, v | 3212 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3213 } 3214 3215 /* wait 20ms for resume sequence to complete */ 3216 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3217 3218 /* U0 */ 3219 XWRITE4(sc, oper, port, v | 3220 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3221 break; 3222 default: 3223 err = USB_ERR_IOERROR; 3224 goto done; 3225 } 3226 break; 3227 3228 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3229 if ((value & 0xff) != 0) { 3230 err = USB_ERR_IOERROR; 3231 goto done; 3232 } 3233 3234 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3235 3236 sc->sc_hub_desc.hubd = xhci_hubd; 3237 3238 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3239 3240 if (XHCI_HCS0_PPC(v)) 3241 i = UHD_PWR_INDIVIDUAL; 3242 else 3243 i = UHD_PWR_GANGED; 3244 3245 if (XHCI_HCS0_PIND(v)) 3246 i |= UHD_PORT_IND; 3247 3248 i |= UHD_OC_INDIVIDUAL; 3249 3250 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3251 3252 /* see XHCI section 5.4.9: */ 3253 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3254 3255 for (j = 1; j <= sc->sc_noport; j++) { 3256 3257 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3258 if (v & XHCI_PS_DR) { 3259 sc->sc_hub_desc.hubd. 3260 DeviceRemovable[j / 8] |= 1U << (j % 8); 3261 } 3262 } 3263 len = sc->sc_hub_desc.hubd.bLength; 3264 break; 3265 3266 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3267 len = 16; 3268 memset(sc->sc_hub_desc.temp, 0, 16); 3269 break; 3270 3271 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3272 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3273 3274 if ((index < 1) || 3275 (index > sc->sc_noport)) { 3276 err = USB_ERR_IOERROR; 3277 goto done; 3278 } 3279 3280 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3281 3282 DPRINTFN(9, "port status=0x%08x\n", v); 3283 3284 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3285 3286 switch (XHCI_PS_SPEED_GET(v)) { 3287 case 3: 3288 i |= UPS_HIGH_SPEED; 3289 break; 3290 case 2: 3291 i |= UPS_LOW_SPEED; 3292 break; 3293 case 1: 3294 /* FULL speed */ 3295 break; 3296 default: 3297 i |= UPS_OTHER_SPEED; 3298 break; 3299 } 3300 3301 if (v & XHCI_PS_CCS) 3302 i |= UPS_CURRENT_CONNECT_STATUS; 3303 if (v & XHCI_PS_PED) 3304 i |= UPS_PORT_ENABLED; 3305 if (v & XHCI_PS_OCA) 3306 i |= UPS_OVERCURRENT_INDICATOR; 3307 if (v & XHCI_PS_PR) 3308 i |= UPS_RESET; 3309 if (v & XHCI_PS_PP) { 3310 /* 3311 * The USB 3.0 RH is using the 3312 * USB 2.0's power bit 3313 */ 3314 i |= UPS_PORT_POWER; 3315 } 3316 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3317 3318 i = 0; 3319 if (v & XHCI_PS_CSC) 3320 i |= UPS_C_CONNECT_STATUS; 3321 if (v & XHCI_PS_PEC) 3322 i |= UPS_C_PORT_ENABLED; 3323 if (v & XHCI_PS_OCC) 3324 i |= UPS_C_OVERCURRENT_INDICATOR; 3325 if (v & XHCI_PS_WRC) 3326 i |= UPS_C_BH_PORT_RESET; 3327 if (v & XHCI_PS_PRC) 3328 i |= UPS_C_PORT_RESET; 3329 if (v & XHCI_PS_PLC) 3330 i |= UPS_C_PORT_LINK_STATE; 3331 if (v & XHCI_PS_CEC) 3332 i |= UPS_C_PORT_CONFIG_ERROR; 3333 3334 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3335 len = sizeof(sc->sc_hub_desc.ps); 3336 break; 3337 3338 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3339 err = USB_ERR_IOERROR; 3340 goto done; 3341 3342 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3343 break; 3344 3345 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3346 3347 i = index >> 8; 3348 index &= 0x00FF; 3349 3350 if ((index < 1) || 3351 (index > sc->sc_noport)) { 3352 err = USB_ERR_IOERROR; 3353 goto done; 3354 } 3355 3356 port = XHCI_PORTSC(index); 3357 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3358 3359 switch (value) { 3360 case UHF_PORT_U1_TIMEOUT: 3361 if (XHCI_PS_SPEED_GET(v) != 4) { 3362 err = USB_ERR_IOERROR; 3363 goto done; 3364 } 3365 port = XHCI_PORTPMSC(index); 3366 v = XREAD4(sc, oper, port); 3367 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3368 v |= XHCI_PM3_U1TO_SET(i); 3369 XWRITE4(sc, oper, port, v); 3370 break; 3371 case UHF_PORT_U2_TIMEOUT: 3372 if (XHCI_PS_SPEED_GET(v) != 4) { 3373 err = USB_ERR_IOERROR; 3374 goto done; 3375 } 3376 port = XHCI_PORTPMSC(index); 3377 v = XREAD4(sc, oper, port); 3378 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3379 v |= XHCI_PM3_U2TO_SET(i); 3380 XWRITE4(sc, oper, port, v); 3381 break; 3382 case UHF_BH_PORT_RESET: 3383 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3384 break; 3385 case UHF_PORT_LINK_STATE: 3386 XWRITE4(sc, oper, port, v | 3387 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3388 /* 4ms settle time */ 3389 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3390 break; 3391 case UHF_PORT_ENABLE: 3392 DPRINTFN(3, "set port enable %d\n", index); 3393 break; 3394 case UHF_PORT_SUSPEND: 3395 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3396 j = XHCI_PS_SPEED_GET(v); 3397 if ((j < 1) || (j > 3)) { 3398 /* non-supported speed */ 3399 err = USB_ERR_IOERROR; 3400 goto done; 3401 } 3402 XWRITE4(sc, oper, port, v | 3403 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3404 break; 3405 case UHF_PORT_RESET: 3406 DPRINTFN(6, "reset port %d\n", index); 3407 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3408 break; 3409 case UHF_PORT_POWER: 3410 DPRINTFN(3, "set port power %d\n", index); 3411 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3412 break; 3413 case UHF_PORT_TEST: 3414 DPRINTFN(3, "set port test %d\n", index); 3415 break; 3416 case UHF_PORT_INDICATOR: 3417 DPRINTFN(3, "set port indicator %d\n", index); 3418 3419 v &= ~XHCI_PS_PIC_SET(3); 3420 v |= XHCI_PS_PIC_SET(1); 3421 3422 XWRITE4(sc, oper, port, v); 3423 break; 3424 default: 3425 err = USB_ERR_IOERROR; 3426 goto done; 3427 } 3428 break; 3429 3430 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3431 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3432 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3433 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3434 break; 3435 default: 3436 err = USB_ERR_IOERROR; 3437 goto done; 3438 } 3439 done: 3440 *plength = len; 3441 *pptr = ptr; 3442 return (err); 3443 } 3444 3445 static void 3446 xhci_xfer_setup(struct usb_setup_params *parm) 3447 { 3448 struct usb_page_search page_info; 3449 struct usb_page_cache *pc; 3450 struct xhci_softc *sc; 3451 struct usb_xfer *xfer; 3452 void *last_obj; 3453 uint32_t ntd; 3454 uint32_t n; 3455 3456 sc = XHCI_BUS2SC(parm->udev->bus); 3457 xfer = parm->curr_xfer; 3458 3459 /* 3460 * The proof for the "ntd" formula is illustrated like this: 3461 * 3462 * +------------------------------------+ 3463 * | | 3464 * | |remainder -> | 3465 * | +-----+---+ | 3466 * | | xxx | x | frm 0 | 3467 * | +-----+---++ | 3468 * | | xxx | xx | frm 1 | 3469 * | +-----+----+ | 3470 * | ... | 3471 * +------------------------------------+ 3472 * 3473 * "xxx" means a completely full USB transfer descriptor 3474 * 3475 * "x" and "xx" means a short USB packet 3476 * 3477 * For the remainder of an USB transfer modulo 3478 * "max_data_length" we need two USB transfer descriptors. 3479 * One to transfer the remaining data and one to finalise with 3480 * a zero length packet in case the "force_short_xfer" flag is 3481 * set. We only need two USB transfer descriptors in the case 3482 * where the transfer length of the first one is a factor of 3483 * "max_frame_size". The rest of the needed USB transfer 3484 * descriptors is given by the buffer size divided by the 3485 * maximum data payload. 3486 */ 3487 parm->hc_max_packet_size = 0x400; 3488 parm->hc_max_packet_count = 16 * 3; 3489 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3490 3491 xfer->flags_int.bdma_enable = 1; 3492 3493 usbd_transfer_setup_sub(parm); 3494 3495 if (xfer->flags_int.isochronous_xfr) { 3496 ntd = ((1 * xfer->nframes) 3497 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3498 } else if (xfer->flags_int.control_xfr) { 3499 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3500 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3501 } else { 3502 ntd = ((2 * xfer->nframes) 3503 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3504 } 3505 3506 alloc_dma_set: 3507 3508 if (parm->err) 3509 return; 3510 3511 /* 3512 * Allocate queue heads and transfer descriptors 3513 */ 3514 last_obj = NULL; 3515 3516 if (usbd_transfer_setup_sub_malloc( 3517 parm, &pc, sizeof(struct xhci_td), 3518 XHCI_TD_ALIGN, ntd)) { 3519 parm->err = USB_ERR_NOMEM; 3520 return; 3521 } 3522 if (parm->buf) { 3523 for (n = 0; n != ntd; n++) { 3524 struct xhci_td *td; 3525 3526 usbd_get_page(pc + n, 0, &page_info); 3527 3528 td = page_info.buffer; 3529 3530 /* init TD */ 3531 td->td_self = page_info.physaddr; 3532 td->obj_next = last_obj; 3533 td->page_cache = pc + n; 3534 3535 last_obj = td; 3536 3537 usb_pc_cpu_flush(pc + n); 3538 } 3539 } 3540 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3541 3542 if (!xfer->flags_int.curr_dma_set) { 3543 xfer->flags_int.curr_dma_set = 1; 3544 goto alloc_dma_set; 3545 } 3546 } 3547 3548 static usb_error_t 3549 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3550 { 3551 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3552 struct usb_page_search buf_inp; 3553 struct usb_device *udev; 3554 struct xhci_endpoint_ext *pepext; 3555 struct usb_endpoint_descriptor *edesc; 3556 struct usb_page_cache *pcinp; 3557 usb_error_t err; 3558 usb_stream_t stream_id; 3559 uint8_t index; 3560 uint8_t epno; 3561 3562 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3563 xfer->endpoint->edesc); 3564 3565 udev = xfer->xroot->udev; 3566 index = udev->controller_slot_id; 3567 3568 pcinp = &sc->sc_hw.devs[index].input_pc; 3569 3570 usbd_get_page(pcinp, 0, &buf_inp); 3571 3572 edesc = xfer->endpoint->edesc; 3573 3574 epno = edesc->bEndpointAddress; 3575 stream_id = xfer->stream_id; 3576 3577 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3578 epno |= UE_DIR_IN; 3579 3580 epno = XHCI_EPNO2EPID(epno); 3581 3582 if (epno == 0) 3583 return (USB_ERR_NO_PIPE); /* invalid */ 3584 3585 XHCI_CMD_LOCK(sc); 3586 3587 /* configure endpoint */ 3588 3589 err = xhci_configure_endpoint_by_xfer(xfer); 3590 3591 if (err != 0) { 3592 XHCI_CMD_UNLOCK(sc); 3593 return (err); 3594 } 3595 3596 /* 3597 * Get the endpoint into the stopped state according to the 3598 * endpoint context state diagram in the XHCI specification: 3599 */ 3600 3601 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3602 3603 if (err != 0) 3604 DPRINTF("Could not stop endpoint %u\n", epno); 3605 3606 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3607 3608 if (err != 0) 3609 DPRINTF("Could not reset endpoint %u\n", epno); 3610 3611 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3612 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3613 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3614 stream_id, epno, index); 3615 3616 if (err != 0) 3617 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3618 3619 /* 3620 * Get the endpoint into the running state according to the 3621 * endpoint context state diagram in the XHCI specification: 3622 */ 3623 3624 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3625 3626 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3627 3628 if (err != 0) 3629 DPRINTF("Could not configure endpoint %u\n", epno); 3630 3631 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3632 3633 if (err != 0) 3634 DPRINTF("Could not configure endpoint %u\n", epno); 3635 3636 XHCI_CMD_UNLOCK(sc); 3637 3638 return (0); 3639 } 3640 3641 static void 3642 xhci_xfer_unsetup(struct usb_xfer *xfer) 3643 { 3644 return; 3645 } 3646 3647 static void 3648 xhci_start_dma_delay(struct usb_xfer *xfer) 3649 { 3650 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3651 3652 /* put transfer on interrupt queue (again) */ 3653 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3654 3655 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3656 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3657 } 3658 3659 static void 3660 xhci_configure_msg(struct usb_proc_msg *pm) 3661 { 3662 struct xhci_softc *sc; 3663 struct xhci_endpoint_ext *pepext; 3664 struct usb_xfer *xfer; 3665 3666 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3667 3668 restart: 3669 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3670 3671 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3672 xfer->endpoint->edesc); 3673 3674 if ((pepext->trb_halted != 0) || 3675 (pepext->trb_running == 0)) { 3676 3677 uint8_t i; 3678 3679 /* clear halted and running */ 3680 pepext->trb_halted = 0; 3681 pepext->trb_running = 0; 3682 3683 /* nuke remaining buffered transfers */ 3684 3685 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 3686 /* 3687 * NOTE: We need to use the timeout 3688 * error code here else existing 3689 * isochronous clients can get 3690 * confused: 3691 */ 3692 if (pepext->xfer[i] != NULL) { 3693 xhci_device_done(pepext->xfer[i], 3694 USB_ERR_TIMEOUT); 3695 } 3696 } 3697 3698 /* 3699 * NOTE: The USB transfer cannot vanish in 3700 * this state! 3701 */ 3702 3703 USB_BUS_UNLOCK(&sc->sc_bus); 3704 3705 xhci_configure_reset_endpoint(xfer); 3706 3707 USB_BUS_LOCK(&sc->sc_bus); 3708 3709 /* check if halted is still cleared */ 3710 if (pepext->trb_halted == 0) { 3711 pepext->trb_running = 1; 3712 memset(pepext->trb_index, 0, 3713 sizeof(pepext->trb_index)); 3714 } 3715 goto restart; 3716 } 3717 3718 if (xfer->flags_int.did_dma_delay) { 3719 3720 /* remove transfer from interrupt queue (again) */ 3721 usbd_transfer_dequeue(xfer); 3722 3723 /* we are finally done */ 3724 usb_dma_delay_done_cb(xfer); 3725 3726 /* queue changed - restart */ 3727 goto restart; 3728 } 3729 } 3730 3731 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3732 3733 /* try to insert xfer on HW queue */ 3734 xhci_transfer_insert(xfer); 3735 3736 /* try to multi buffer */ 3737 xhci_device_generic_multi_enter(xfer->endpoint, 3738 xfer->stream_id, NULL); 3739 } 3740 } 3741 3742 static void 3743 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3744 struct usb_endpoint *ep) 3745 { 3746 struct xhci_endpoint_ext *pepext; 3747 3748 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3749 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3750 3751 if (udev->parent_hub == NULL) { 3752 /* root HUB has special endpoint handling */ 3753 return; 3754 } 3755 3756 ep->methods = &xhci_device_generic_methods; 3757 3758 pepext = xhci_get_endpoint_ext(udev, edesc); 3759 3760 USB_BUS_LOCK(udev->bus); 3761 pepext->trb_halted = 1; 3762 pepext->trb_running = 0; 3763 USB_BUS_UNLOCK(udev->bus); 3764 } 3765 3766 static void 3767 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3768 { 3769 3770 } 3771 3772 static void 3773 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3774 { 3775 struct xhci_endpoint_ext *pepext; 3776 3777 DPRINTF("\n"); 3778 3779 if (udev->flags.usb_mode != USB_MODE_HOST) { 3780 /* not supported */ 3781 return; 3782 } 3783 if (udev->parent_hub == NULL) { 3784 /* root HUB has special endpoint handling */ 3785 return; 3786 } 3787 3788 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3789 3790 USB_BUS_LOCK(udev->bus); 3791 pepext->trb_halted = 1; 3792 pepext->trb_running = 0; 3793 USB_BUS_UNLOCK(udev->bus); 3794 } 3795 3796 static usb_error_t 3797 xhci_device_init(struct usb_device *udev) 3798 { 3799 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3800 usb_error_t err; 3801 uint8_t temp; 3802 3803 /* no init for root HUB */ 3804 if (udev->parent_hub == NULL) 3805 return (0); 3806 3807 XHCI_CMD_LOCK(sc); 3808 3809 /* set invalid default */ 3810 3811 udev->controller_slot_id = sc->sc_noslot + 1; 3812 3813 /* try to get a new slot ID from the XHCI */ 3814 3815 err = xhci_cmd_enable_slot(sc, &temp); 3816 3817 if (err) { 3818 XHCI_CMD_UNLOCK(sc); 3819 return (err); 3820 } 3821 3822 if (temp > sc->sc_noslot) { 3823 XHCI_CMD_UNLOCK(sc); 3824 return (USB_ERR_BAD_ADDRESS); 3825 } 3826 3827 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 3828 DPRINTF("slot %u already allocated.\n", temp); 3829 XHCI_CMD_UNLOCK(sc); 3830 return (USB_ERR_BAD_ADDRESS); 3831 } 3832 3833 /* store slot ID for later reference */ 3834 3835 udev->controller_slot_id = temp; 3836 3837 /* reset data structure */ 3838 3839 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 3840 3841 /* set mark slot allocated */ 3842 3843 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 3844 3845 err = xhci_alloc_device_ext(udev); 3846 3847 XHCI_CMD_UNLOCK(sc); 3848 3849 /* get device into default state */ 3850 3851 if (err == 0) 3852 err = xhci_set_address(udev, NULL, 0); 3853 3854 return (err); 3855 } 3856 3857 static void 3858 xhci_device_uninit(struct usb_device *udev) 3859 { 3860 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3861 uint8_t index; 3862 3863 /* no init for root HUB */ 3864 if (udev->parent_hub == NULL) 3865 return; 3866 3867 XHCI_CMD_LOCK(sc); 3868 3869 index = udev->controller_slot_id; 3870 3871 if (index <= sc->sc_noslot) { 3872 xhci_cmd_disable_slot(sc, index); 3873 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 3874 3875 /* free device extension */ 3876 xhci_free_device_ext(udev); 3877 } 3878 3879 XHCI_CMD_UNLOCK(sc); 3880 } 3881 3882 static void 3883 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3884 { 3885 /* 3886 * Wait until the hardware has finished any possible use of 3887 * the transfer descriptor(s) 3888 */ 3889 *pus = 2048; /* microseconds */ 3890 } 3891 3892 static void 3893 xhci_device_resume(struct usb_device *udev) 3894 { 3895 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3896 uint8_t index; 3897 uint8_t n; 3898 uint8_t p; 3899 3900 DPRINTF("\n"); 3901 3902 /* check for root HUB */ 3903 if (udev->parent_hub == NULL) 3904 return; 3905 3906 index = udev->controller_slot_id; 3907 3908 XHCI_CMD_LOCK(sc); 3909 3910 /* blindly resume all endpoints */ 3911 3912 USB_BUS_LOCK(udev->bus); 3913 3914 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3915 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 3916 XWRITE4(sc, door, XHCI_DOORBELL(index), 3917 n | XHCI_DB_SID_SET(p)); 3918 } 3919 } 3920 3921 USB_BUS_UNLOCK(udev->bus); 3922 3923 XHCI_CMD_UNLOCK(sc); 3924 } 3925 3926 static void 3927 xhci_device_suspend(struct usb_device *udev) 3928 { 3929 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3930 uint8_t index; 3931 uint8_t n; 3932 usb_error_t err; 3933 3934 DPRINTF("\n"); 3935 3936 /* check for root HUB */ 3937 if (udev->parent_hub == NULL) 3938 return; 3939 3940 index = udev->controller_slot_id; 3941 3942 XHCI_CMD_LOCK(sc); 3943 3944 /* blindly suspend all endpoints */ 3945 3946 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3947 err = xhci_cmd_stop_ep(sc, 1, n, index); 3948 if (err != 0) { 3949 DPRINTF("Failed to suspend endpoint " 3950 "%u on slot %u (ignored).\n", n, index); 3951 } 3952 } 3953 3954 XHCI_CMD_UNLOCK(sc); 3955 } 3956 3957 static void 3958 xhci_set_hw_power(struct usb_bus *bus) 3959 { 3960 DPRINTF("\n"); 3961 } 3962 3963 static void 3964 xhci_device_state_change(struct usb_device *udev) 3965 { 3966 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3967 struct usb_page_search buf_inp; 3968 usb_error_t err; 3969 uint8_t index; 3970 3971 /* check for root HUB */ 3972 if (udev->parent_hub == NULL) 3973 return; 3974 3975 index = udev->controller_slot_id; 3976 3977 DPRINTF("\n"); 3978 3979 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 3980 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 3981 &sc->sc_hw.devs[index].tt); 3982 if (err != 0) 3983 sc->sc_hw.devs[index].nports = 0; 3984 } 3985 3986 XHCI_CMD_LOCK(sc); 3987 3988 switch (usb_get_device_state(udev)) { 3989 case USB_STATE_POWERED: 3990 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 3991 break; 3992 3993 /* set default state */ 3994 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 3995 3996 /* reset number of contexts */ 3997 sc->sc_hw.devs[index].context_num = 0; 3998 3999 err = xhci_cmd_reset_dev(sc, index); 4000 4001 if (err != 0) { 4002 DPRINTF("Device reset failed " 4003 "for slot %u.\n", index); 4004 } 4005 break; 4006 4007 case USB_STATE_ADDRESSED: 4008 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4009 break; 4010 4011 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4012 4013 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4014 4015 if (err) { 4016 DPRINTF("Failed to deconfigure " 4017 "slot %u.\n", index); 4018 } 4019 break; 4020 4021 case USB_STATE_CONFIGURED: 4022 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4023 break; 4024 4025 /* set configured state */ 4026 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4027 4028 /* reset number of contexts */ 4029 sc->sc_hw.devs[index].context_num = 0; 4030 4031 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4032 4033 xhci_configure_mask(udev, 3, 0); 4034 4035 err = xhci_configure_device(udev); 4036 if (err != 0) { 4037 DPRINTF("Could not configure device " 4038 "at slot %u.\n", index); 4039 } 4040 4041 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4042 if (err != 0) { 4043 DPRINTF("Could not evaluate device " 4044 "context at slot %u.\n", index); 4045 } 4046 break; 4047 4048 default: 4049 break; 4050 } 4051 XHCI_CMD_UNLOCK(sc); 4052 } 4053 4054 static usb_error_t 4055 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4056 uint8_t ep_mode) 4057 { 4058 switch (ep_mode) { 4059 case USB_EP_MODE_DEFAULT: 4060 return (0); 4061 case USB_EP_MODE_STREAMS: 4062 if ((ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4063 udev->speed != USB_SPEED_SUPER) 4064 return (USB_ERR_INVAL); 4065 return (0); 4066 default: 4067 return (USB_ERR_INVAL); 4068 } 4069 } 4070 4071 struct usb_bus_methods xhci_bus_methods = { 4072 .endpoint_init = xhci_ep_init, 4073 .endpoint_uninit = xhci_ep_uninit, 4074 .xfer_setup = xhci_xfer_setup, 4075 .xfer_unsetup = xhci_xfer_unsetup, 4076 .get_dma_delay = xhci_get_dma_delay, 4077 .device_init = xhci_device_init, 4078 .device_uninit = xhci_device_uninit, 4079 .device_resume = xhci_device_resume, 4080 .device_suspend = xhci_device_suspend, 4081 .set_hw_power = xhci_set_hw_power, 4082 .roothub_exec = xhci_roothub_exec, 4083 .xfer_poll = xhci_do_poll, 4084 .start_dma_delay = xhci_start_dma_delay, 4085 .set_address = xhci_set_address, 4086 .clear_stall = xhci_ep_clear_stall, 4087 .device_state_change = xhci_device_state_change, 4088 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4089 .set_endpoint_mode = xhci_set_endpoint_mode, 4090 }; 4091