xref: /freebsd/sys/dev/usb/controller/xhci.c (revision 4ec234c813eed05c166859bba82c882e40826eb9)
1 /* $FreeBSD$ */
2 /*-
3  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 /*
28  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
29  *
30  * The XHCI 1.0 spec can be found at
31  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
32  * and the USB 3.0 spec at
33  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
34  */
35 
36 /*
37  * A few words about the design implementation: This driver emulates
38  * the concept about TDs which is found in EHCI specification. This
39  * way we achieve that the USB controller drivers look similar to
40  * eachother which makes it easier to understand the code.
41  */
42 
43 #ifdef USB_GLOBAL_INCLUDE_FILE
44 #include USB_GLOBAL_INCLUDE_FILE
45 #else
46 #include <sys/stdint.h>
47 #include <sys/stddef.h>
48 #include <sys/param.h>
49 #include <sys/queue.h>
50 #include <sys/types.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
53 #include <sys/bus.h>
54 #include <sys/module.h>
55 #include <sys/lock.h>
56 #include <sys/mutex.h>
57 #include <sys/condvar.h>
58 #include <sys/sysctl.h>
59 #include <sys/sx.h>
60 #include <sys/unistd.h>
61 #include <sys/callout.h>
62 #include <sys/malloc.h>
63 #include <sys/priv.h>
64 
65 #include <dev/usb/usb.h>
66 #include <dev/usb/usbdi.h>
67 
68 #define	USB_DEBUG_VAR xhcidebug
69 
70 #include <dev/usb/usb_core.h>
71 #include <dev/usb/usb_debug.h>
72 #include <dev/usb/usb_busdma.h>
73 #include <dev/usb/usb_process.h>
74 #include <dev/usb/usb_transfer.h>
75 #include <dev/usb/usb_device.h>
76 #include <dev/usb/usb_hub.h>
77 #include <dev/usb/usb_util.h>
78 
79 #include <dev/usb/usb_controller.h>
80 #include <dev/usb/usb_bus.h>
81 #endif			/* USB_GLOBAL_INCLUDE_FILE */
82 
83 #include <dev/usb/controller/xhci.h>
84 #include <dev/usb/controller/xhcireg.h>
85 
86 #define	XHCI_BUS2SC(bus) \
87    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
88     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
89 
90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
91 
92 static int xhcistreams;
93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN,
94     &xhcistreams, 0, "Set to enable streams mode support");
95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams);
96 
97 #ifdef USB_DEBUG
98 static int xhcidebug;
99 static int xhciroute;
100 static int xhcipolling;
101 
102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
103     &xhcidebug, 0, "Debug level");
104 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
106     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
107 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
109     &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller");
110 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
111 #else
112 #define	xhciroute 0
113 #endif
114 
115 #define	XHCI_INTR_ENDPT 1
116 
117 struct xhci_std_temp {
118 	struct xhci_softc	*sc;
119 	struct usb_page_cache	*pc;
120 	struct xhci_td		*td;
121 	struct xhci_td		*td_next;
122 	uint32_t		len;
123 	uint32_t		offset;
124 	uint32_t		max_packet_size;
125 	uint32_t		average;
126 	uint16_t		isoc_delta;
127 	uint16_t		isoc_frame;
128 	uint8_t			shortpkt;
129 	uint8_t			multishort;
130 	uint8_t			last_frame;
131 	uint8_t			trb_type;
132 	uint8_t			direction;
133 	uint8_t			tbc;
134 	uint8_t			tlbpc;
135 	uint8_t			step_td;
136 	uint8_t			do_isoc_sync;
137 };
138 
139 static void	xhci_do_poll(struct usb_bus *);
140 static void	xhci_device_done(struct usb_xfer *, usb_error_t);
141 static void	xhci_root_intr(struct xhci_softc *);
142 static void	xhci_free_device_ext(struct usb_device *);
143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
144 		    struct usb_endpoint_descriptor *);
145 static usb_proc_callback_t xhci_configure_msg;
146 static usb_error_t xhci_configure_device(struct usb_device *);
147 static usb_error_t xhci_configure_endpoint(struct usb_device *,
148 		   struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
149 		   uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
150 		   uint8_t);
151 static usb_error_t xhci_configure_mask(struct usb_device *,
152 		    uint32_t, uint8_t);
153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
154 		    uint64_t, uint8_t);
155 static void xhci_endpoint_doorbell(struct usb_xfer *);
156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
159 #ifdef USB_DEBUG
160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
161 #endif
162 
163 static const struct usb_bus_methods xhci_bus_methods;
164 
165 #ifdef USB_DEBUG
166 static void
167 xhci_dump_trb(struct xhci_trb *trb)
168 {
169 	DPRINTFN(5, "trb = %p\n", trb);
170 	DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
171 	DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
172 	DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
173 }
174 
175 static void
176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
177 {
178 	DPRINTFN(5, "pep = %p\n", pep);
179 	DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
180 	DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
181 	DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
182 	DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
183 	DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
184 	DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
185 	DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
186 }
187 
188 static void
189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
190 {
191 	DPRINTFN(5, "psl = %p\n", psl);
192 	DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
193 	DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
194 	DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
195 	DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
196 }
197 #endif
198 
199 uint8_t
200 xhci_use_polling(void)
201 {
202 #ifdef USB_DEBUG
203 	return (xhcipolling != 0);
204 #else
205 	return (0);
206 #endif
207 }
208 
209 static void
210 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
211 {
212 	struct xhci_softc *sc = XHCI_BUS2SC(bus);
213 	uint8_t i;
214 
215 	cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
216 	   sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
217 
218 	cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
219 	   sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
220 
221 	for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
222 		cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
223 		    XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
224 	}
225 }
226 
227 static void
228 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
229 {
230 	if (sc->sc_ctx_is_64_byte) {
231 		uint32_t offset;
232 		/* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
233 		/* all contexts are initially 32-bytes */
234 		offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
235 		ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
236 	}
237 	*ptr = htole32(val);
238 }
239 
240 static uint32_t
241 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
242 {
243 	if (sc->sc_ctx_is_64_byte) {
244 		uint32_t offset;
245 		/* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
246 		/* all contexts are initially 32-bytes */
247 		offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
248 		ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
249 	}
250 	return (le32toh(*ptr));
251 }
252 
253 static void
254 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
255 {
256 	if (sc->sc_ctx_is_64_byte) {
257 		uint32_t offset;
258 		/* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
259 		/* all contexts are initially 32-bytes */
260 		offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
261 		ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
262 	}
263 	*ptr = htole64(val);
264 }
265 
266 #ifdef USB_DEBUG
267 static uint64_t
268 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
269 {
270 	if (sc->sc_ctx_is_64_byte) {
271 		uint32_t offset;
272 		/* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
273 		/* all contexts are initially 32-bytes */
274 		offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
275 		ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
276 	}
277 	return (le64toh(*ptr));
278 }
279 #endif
280 
281 static int
282 xhci_reset_command_queue_locked(struct xhci_softc *sc)
283 {
284 	struct usb_page_search buf_res;
285 	struct xhci_hw_root *phwr;
286 	uint64_t addr;
287 	uint32_t temp;
288 
289 	DPRINTF("\n");
290 
291 	temp = XREAD4(sc, oper, XHCI_CRCR_LO);
292 	if (temp & XHCI_CRCR_LO_CRR) {
293 		DPRINTF("Command ring running\n");
294 		temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
295 
296 		/*
297 		 * Try to abort the last command as per section
298 		 * 4.6.1.2 "Aborting a Command" of the XHCI
299 		 * specification:
300 		 */
301 
302 		/* stop and cancel */
303 		XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
304 		XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
305 
306 		XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
307 		XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
308 
309  		/* wait 250ms */
310  		usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
311 
312 		/* check if command ring is still running */
313 		temp = XREAD4(sc, oper, XHCI_CRCR_LO);
314 		if (temp & XHCI_CRCR_LO_CRR) {
315 			DPRINTF("Comand ring still running\n");
316 			return (USB_ERR_IOERROR);
317 		}
318 	}
319 
320 	/* reset command ring */
321 	sc->sc_command_ccs = 1;
322 	sc->sc_command_idx = 0;
323 
324 	usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
325 
326 	/* setup command ring control base address */
327 	addr = buf_res.physaddr;
328 	phwr = buf_res.buffer;
329 	addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
330 
331 	DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
332 
333 	memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
334 	phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
335 
336 	usb_pc_cpu_flush(&sc->sc_hw.root_pc);
337 
338 	XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
339 	XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
340 
341 	return (0);
342 }
343 
344 usb_error_t
345 xhci_start_controller(struct xhci_softc *sc)
346 {
347 	struct usb_page_search buf_res;
348 	struct xhci_hw_root *phwr;
349 	struct xhci_dev_ctx_addr *pdctxa;
350 	uint64_t addr;
351 	uint32_t temp;
352 	uint16_t i;
353 
354 	DPRINTF("\n");
355 
356 	sc->sc_capa_off = 0;
357 	sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
358 	sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
359 	sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
360 
361 	DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
362 	DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
363 	DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
364 
365 	sc->sc_event_ccs = 1;
366 	sc->sc_event_idx = 0;
367 	sc->sc_command_ccs = 1;
368 	sc->sc_command_idx = 0;
369 
370 	DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
371 
372 	temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
373 
374 	DPRINTF("HCS0 = 0x%08x\n", temp);
375 
376 	if (XHCI_HCS0_CSZ(temp)) {
377 		sc->sc_ctx_is_64_byte = 1;
378 		device_printf(sc->sc_bus.parent, "64 byte context size.\n");
379 	} else {
380 		sc->sc_ctx_is_64_byte = 0;
381 		device_printf(sc->sc_bus.parent, "32 byte context size.\n");
382 	}
383 
384 	/* Reset controller */
385 	XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
386 
387 	for (i = 0; i != 100; i++) {
388 		usb_pause_mtx(NULL, hz / 100);
389 		temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
390 		    (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
391 		if (!temp)
392 			break;
393 	}
394 
395 	if (temp) {
396 		device_printf(sc->sc_bus.parent, "Controller "
397 		    "reset timeout.\n");
398 		return (USB_ERR_IOERROR);
399 	}
400 
401 	if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
402 		device_printf(sc->sc_bus.parent, "Controller does "
403 		    "not support 4K page size.\n");
404 		return (USB_ERR_IOERROR);
405 	}
406 
407 	temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
408 
409 	i = XHCI_HCS1_N_PORTS(temp);
410 
411 	if (i == 0) {
412 		device_printf(sc->sc_bus.parent, "Invalid number "
413 		    "of ports: %u\n", i);
414 		return (USB_ERR_IOERROR);
415 	}
416 
417 	sc->sc_noport = i;
418 	sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
419 
420 	if (sc->sc_noslot > XHCI_MAX_DEVICES)
421 		sc->sc_noslot = XHCI_MAX_DEVICES;
422 
423 	/* setup number of device slots */
424 
425 	DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
426 	    XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
427 
428 	XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
429 
430 	DPRINTF("Max slots: %u\n", sc->sc_noslot);
431 
432 	temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
433 
434 	sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
435 
436 	if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
437 		device_printf(sc->sc_bus.parent, "XHCI request "
438 		    "too many scratchpads\n");
439 		return (USB_ERR_NOMEM);
440 	}
441 
442 	DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
443 
444 	temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
445 
446 	sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
447 	    XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
448 
449 	temp = XREAD4(sc, oper, XHCI_USBSTS);
450 
451 	/* clear interrupts */
452 	XWRITE4(sc, oper, XHCI_USBSTS, temp);
453 	/* disable all device notifications */
454 	XWRITE4(sc, oper, XHCI_DNCTRL, 0);
455 
456 	/* setup device context base address */
457 	usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
458 	pdctxa = buf_res.buffer;
459 	memset(pdctxa, 0, sizeof(*pdctxa));
460 
461 	addr = buf_res.physaddr;
462 	addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
463 
464 	/* slot 0 points to the table of scratchpad pointers */
465 	pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
466 
467 	for (i = 0; i != sc->sc_noscratch; i++) {
468 		struct usb_page_search buf_scp;
469 		usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
470 		pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
471 	}
472 
473 	addr = buf_res.physaddr;
474 
475 	XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
476 	XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
477 	XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
478 	XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
479 
480 	/* Setup event table size */
481 
482 	temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
483 
484 	DPRINTF("HCS2=0x%08x\n", temp);
485 
486 	temp = XHCI_HCS2_ERST_MAX(temp);
487 	temp = 1U << temp;
488 	if (temp > XHCI_MAX_RSEG)
489 		temp = XHCI_MAX_RSEG;
490 
491 	sc->sc_erst_max = temp;
492 
493 	DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
494 	    XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
495 
496 	XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
497 
498 	/* Setup interrupt rate */
499 	XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT);
500 
501 	usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
502 
503 	phwr = buf_res.buffer;
504 	addr = buf_res.physaddr;
505 	addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
506 
507 	/* reset hardware root structure */
508 	memset(phwr, 0, sizeof(*phwr));
509 
510 	phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
511 	phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
512 
513 	DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
514 
515 	XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
516 	XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
517 
518 	addr = (uint64_t)buf_res.physaddr;
519 
520 	DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
521 
522 	XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
523 	XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
524 
525 	/* Setup interrupter registers */
526 
527 	temp = XREAD4(sc, runt, XHCI_IMAN(0));
528 	temp |= XHCI_IMAN_INTR_ENA;
529 	XWRITE4(sc, runt, XHCI_IMAN(0), temp);
530 
531 	/* setup command ring control base address */
532 	addr = buf_res.physaddr;
533 	addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
534 
535 	DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
536 
537 	XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
538 	XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
539 
540 	phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
541 
542 	usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
543 
544 	/* Go! */
545 	XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
546 	    XHCI_CMD_INTE | XHCI_CMD_HSEE);
547 
548 	for (i = 0; i != 100; i++) {
549 		usb_pause_mtx(NULL, hz / 100);
550 		temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
551 		if (!temp)
552 			break;
553 	}
554 	if (temp) {
555 		XWRITE4(sc, oper, XHCI_USBCMD, 0);
556 		device_printf(sc->sc_bus.parent, "Run timeout.\n");
557 		return (USB_ERR_IOERROR);
558 	}
559 
560 	/* catch any lost interrupts */
561 	xhci_do_poll(&sc->sc_bus);
562 
563 	if (sc->sc_port_route != NULL) {
564 		/* Route all ports to the XHCI by default */
565 		sc->sc_port_route(sc->sc_bus.parent,
566 		    ~xhciroute, xhciroute);
567 	}
568 	return (0);
569 }
570 
571 usb_error_t
572 xhci_halt_controller(struct xhci_softc *sc)
573 {
574 	uint32_t temp;
575 	uint16_t i;
576 
577 	DPRINTF("\n");
578 
579 	sc->sc_capa_off = 0;
580 	sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
581 	sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
582 	sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
583 
584 	/* Halt controller */
585 	XWRITE4(sc, oper, XHCI_USBCMD, 0);
586 
587 	for (i = 0; i != 100; i++) {
588 		usb_pause_mtx(NULL, hz / 100);
589 		temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
590 		if (temp)
591 			break;
592 	}
593 
594 	if (!temp) {
595 		device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
596 		return (USB_ERR_IOERROR);
597 	}
598 	return (0);
599 }
600 
601 usb_error_t
602 xhci_init(struct xhci_softc *sc, device_t self)
603 {
604 	/* initialise some bus fields */
605 	sc->sc_bus.parent = self;
606 
607 	/* set the bus revision */
608 	sc->sc_bus.usbrev = USB_REV_3_0;
609 
610 	/* set up the bus struct */
611 	sc->sc_bus.methods = &xhci_bus_methods;
612 
613 	/* setup devices array */
614 	sc->sc_bus.devices = sc->sc_devices;
615 	sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
616 
617 	/* setup command queue mutex and condition varible */
618 	cv_init(&sc->sc_cmd_cv, "CMDQ");
619 	sx_init(&sc->sc_cmd_sx, "CMDQ lock");
620 
621 	/* get all DMA memory */
622 	if (usb_bus_mem_alloc_all(&sc->sc_bus,
623 	    USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
624 		return (ENOMEM);
625 	}
626 
627         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
628         sc->sc_config_msg[0].bus = &sc->sc_bus;
629         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
630         sc->sc_config_msg[1].bus = &sc->sc_bus;
631 
632 	return (0);
633 }
634 
635 void
636 xhci_uninit(struct xhci_softc *sc)
637 {
638 	/*
639 	 * NOTE: At this point the control transfer process is gone
640 	 * and "xhci_configure_msg" is no longer called. Consequently
641 	 * waiting for the configuration messages to complete is not
642 	 * needed.
643 	 */
644 	usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
645 
646 	cv_destroy(&sc->sc_cmd_cv);
647 	sx_destroy(&sc->sc_cmd_sx);
648 }
649 
650 static void
651 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
652 {
653 	struct xhci_softc *sc = XHCI_BUS2SC(bus);
654 
655 	switch (state) {
656 	case USB_HW_POWER_SUSPEND:
657 		DPRINTF("Stopping the XHCI\n");
658 		xhci_halt_controller(sc);
659 		break;
660 	case USB_HW_POWER_SHUTDOWN:
661 		DPRINTF("Stopping the XHCI\n");
662 		xhci_halt_controller(sc);
663 		break;
664 	case USB_HW_POWER_RESUME:
665 		DPRINTF("Starting the XHCI\n");
666 		xhci_start_controller(sc);
667 		break;
668 	default:
669 		break;
670 	}
671 }
672 
673 static usb_error_t
674 xhci_generic_done_sub(struct usb_xfer *xfer)
675 {
676 	struct xhci_td *td;
677 	struct xhci_td *td_alt_next;
678 	uint32_t len;
679 	uint8_t status;
680 
681 	td = xfer->td_transfer_cache;
682 	td_alt_next = td->alt_next;
683 
684 	if (xfer->aframes != xfer->nframes)
685 		usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
686 
687 	while (1) {
688 
689 		usb_pc_cpu_invalidate(td->page_cache);
690 
691 		status = td->status;
692 		len = td->remainder;
693 
694 		DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
695 		    xfer, (unsigned int)xfer->aframes,
696 		    (unsigned int)xfer->nframes,
697 		    (unsigned int)len, (unsigned int)td->len,
698 		    (unsigned int)status);
699 
700 		/*
701 	         * Verify the status length and
702 		 * add the length to "frlengths[]":
703 	         */
704 		if (len > td->len) {
705 			/* should not happen */
706 			DPRINTF("Invalid status length, "
707 			    "0x%04x/0x%04x bytes\n", len, td->len);
708 			status = XHCI_TRB_ERROR_LENGTH;
709 		} else if (xfer->aframes != xfer->nframes) {
710 			xfer->frlengths[xfer->aframes] += td->len - len;
711 		}
712 		/* Check for last transfer */
713 		if (((void *)td) == xfer->td_transfer_last) {
714 			td = NULL;
715 			break;
716 		}
717 		/* Check for transfer error */
718 		if (status != XHCI_TRB_ERROR_SHORT_PKT &&
719 		    status != XHCI_TRB_ERROR_SUCCESS) {
720 			/* the transfer is finished */
721 			td = NULL;
722 			break;
723 		}
724 		/* Check for short transfer */
725 		if (len > 0) {
726 			if (xfer->flags_int.short_frames_ok ||
727 			    xfer->flags_int.isochronous_xfr ||
728 			    xfer->flags_int.control_xfr) {
729 				/* follow alt next */
730 				td = td->alt_next;
731 			} else {
732 				/* the transfer is finished */
733 				td = NULL;
734 			}
735 			break;
736 		}
737 		td = td->obj_next;
738 
739 		if (td->alt_next != td_alt_next) {
740 			/* this USB frame is complete */
741 			break;
742 		}
743 	}
744 
745 	/* update transfer cache */
746 
747 	xfer->td_transfer_cache = td;
748 
749 	return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
750 	    (status != XHCI_TRB_ERROR_SHORT_PKT &&
751 	    status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
752 	    USB_ERR_NORMAL_COMPLETION);
753 }
754 
755 static void
756 xhci_generic_done(struct usb_xfer *xfer)
757 {
758 	usb_error_t err = 0;
759 
760 	DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
761 	    xfer, xfer->endpoint);
762 
763 	/* reset scanner */
764 
765 	xfer->td_transfer_cache = xfer->td_transfer_first;
766 
767 	if (xfer->flags_int.control_xfr) {
768 
769 		if (xfer->flags_int.control_hdr)
770 			err = xhci_generic_done_sub(xfer);
771 
772 		xfer->aframes = 1;
773 
774 		if (xfer->td_transfer_cache == NULL)
775 			goto done;
776 	}
777 
778 	while (xfer->aframes != xfer->nframes) {
779 
780 		err = xhci_generic_done_sub(xfer);
781 		xfer->aframes++;
782 
783 		if (xfer->td_transfer_cache == NULL)
784 			goto done;
785 	}
786 
787 	if (xfer->flags_int.control_xfr &&
788 	    !xfer->flags_int.control_act)
789 		err = xhci_generic_done_sub(xfer);
790 done:
791 	/* transfer is complete */
792 	xhci_device_done(xfer, err);
793 }
794 
795 static void
796 xhci_activate_transfer(struct usb_xfer *xfer)
797 {
798 	struct xhci_td *td;
799 
800 	td = xfer->td_transfer_cache;
801 
802 	usb_pc_cpu_invalidate(td->page_cache);
803 
804 	if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
805 
806 		/* activate the transfer */
807 
808 		td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
809 		usb_pc_cpu_flush(td->page_cache);
810 
811 		xhci_endpoint_doorbell(xfer);
812 	}
813 }
814 
815 static void
816 xhci_skip_transfer(struct usb_xfer *xfer)
817 {
818 	struct xhci_td *td;
819 	struct xhci_td *td_last;
820 
821 	td = xfer->td_transfer_cache;
822 	td_last = xfer->td_transfer_last;
823 
824 	td = td->alt_next;
825 
826 	usb_pc_cpu_invalidate(td->page_cache);
827 
828 	if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
829 
830 		usb_pc_cpu_invalidate(td_last->page_cache);
831 
832 		/* copy LINK TRB to current waiting location */
833 
834 		td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
835 		td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
836 		usb_pc_cpu_flush(td->page_cache);
837 
838 		td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
839 		usb_pc_cpu_flush(td->page_cache);
840 
841 		xhci_endpoint_doorbell(xfer);
842 	}
843 }
844 
845 /*------------------------------------------------------------------------*
846  *	xhci_check_transfer
847  *------------------------------------------------------------------------*/
848 static void
849 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
850 {
851 	struct xhci_endpoint_ext *pepext;
852 	int64_t offset;
853 	uint64_t td_event;
854 	uint32_t temp;
855 	uint32_t remainder;
856 	uint16_t stream_id;
857 	uint16_t i;
858 	uint8_t status;
859 	uint8_t halted;
860 	uint8_t epno;
861 	uint8_t index;
862 
863 	/* decode TRB */
864 	td_event = le64toh(trb->qwTrb0);
865 	temp = le32toh(trb->dwTrb2);
866 
867 	remainder = XHCI_TRB_2_REM_GET(temp);
868 	status = XHCI_TRB_2_ERROR_GET(temp);
869 	stream_id = XHCI_TRB_2_STREAM_GET(temp);
870 
871 	temp = le32toh(trb->dwTrb3);
872 	epno = XHCI_TRB_3_EP_GET(temp);
873 	index = XHCI_TRB_3_SLOT_GET(temp);
874 
875 	/* check if error means halted */
876 	halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
877 	    status != XHCI_TRB_ERROR_SUCCESS);
878 
879 	DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n",
880 	    index, epno, stream_id, remainder, status);
881 
882 	if (index > sc->sc_noslot) {
883 		DPRINTF("Invalid slot.\n");
884 		return;
885 	}
886 
887 	if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
888 		DPRINTF("Invalid endpoint.\n");
889 		return;
890 	}
891 
892 	pepext = &sc->sc_hw.devs[index].endp[epno];
893 
894 	if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) {
895 		stream_id = 0;
896 		DPRINTF("stream_id=0\n");
897 	} else if (stream_id >= XHCI_MAX_STREAMS) {
898 		DPRINTF("Invalid stream ID.\n");
899 		return;
900 	}
901 
902 	/* try to find the USB transfer that generated the event */
903 	for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
904 		struct usb_xfer *xfer;
905 		struct xhci_td *td;
906 
907 		xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
908 		if (xfer == NULL)
909 			continue;
910 
911 		td = xfer->td_transfer_cache;
912 
913 		DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
914 			(long long)td_event,
915 			(long long)td->td_self,
916 			(long long)td->td_self + sizeof(td->td_trb));
917 
918 		/*
919 		 * NOTE: Some XHCI implementations might not trigger
920 		 * an event on the last LINK TRB so we need to
921 		 * consider both the last and second last event
922 		 * address as conditions for a successful transfer.
923 		 *
924 		 * NOTE: We assume that the XHCI will only trigger one
925 		 * event per chain of TRBs.
926 		 */
927 
928 		offset = td_event - td->td_self;
929 
930 		if (offset >= 0 &&
931 		    offset < (int64_t)sizeof(td->td_trb)) {
932 
933 			usb_pc_cpu_invalidate(td->page_cache);
934 
935 			/* compute rest of remainder, if any */
936 			for (i = (offset / 16) + 1; i < td->ntrb; i++) {
937 				temp = le32toh(td->td_trb[i].dwTrb2);
938 				remainder += XHCI_TRB_2_BYTES_GET(temp);
939 			}
940 
941 			DPRINTFN(5, "New remainder: %u\n", remainder);
942 
943 			/* clear isochronous transfer errors */
944 			if (xfer->flags_int.isochronous_xfr) {
945 				if (halted) {
946 					halted = 0;
947 					status = XHCI_TRB_ERROR_SUCCESS;
948 					remainder = td->len;
949 				}
950 			}
951 
952 			/* "td->remainder" is verified later */
953 			td->remainder = remainder;
954 			td->status = status;
955 
956 			usb_pc_cpu_flush(td->page_cache);
957 
958 			/*
959 			 * 1) Last transfer descriptor makes the
960 			 * transfer done
961 			 */
962 			if (((void *)td) == xfer->td_transfer_last) {
963 				DPRINTF("TD is last\n");
964 				xhci_generic_done(xfer);
965 				break;
966 			}
967 
968 			/*
969 			 * 2) Any kind of error makes the transfer
970 			 * done
971 			 */
972 			if (halted) {
973 				DPRINTF("TD has I/O error\n");
974 				xhci_generic_done(xfer);
975 				break;
976 			}
977 
978 			/*
979 			 * 3) If there is no alternate next transfer,
980 			 * a short packet also makes the transfer done
981 			 */
982 			if (td->remainder > 0) {
983 				if (td->alt_next == NULL) {
984 					DPRINTF(
985 					    "short TD has no alternate next\n");
986 					xhci_generic_done(xfer);
987 					break;
988 				}
989 				DPRINTF("TD has short pkt\n");
990 				if (xfer->flags_int.short_frames_ok ||
991 				    xfer->flags_int.isochronous_xfr ||
992 				    xfer->flags_int.control_xfr) {
993 					/* follow the alt next */
994 					xfer->td_transfer_cache = td->alt_next;
995 					xhci_activate_transfer(xfer);
996 					break;
997 				}
998 				xhci_skip_transfer(xfer);
999 				xhci_generic_done(xfer);
1000 				break;
1001 			}
1002 
1003 			/*
1004 			 * 4) Transfer complete - go to next TD
1005 			 */
1006 			DPRINTF("Following next TD\n");
1007 			xfer->td_transfer_cache = td->obj_next;
1008 			xhci_activate_transfer(xfer);
1009 			break;		/* there should only be one match */
1010 		}
1011 	}
1012 }
1013 
1014 static int
1015 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1016 {
1017 	if (sc->sc_cmd_addr == trb->qwTrb0) {
1018 		DPRINTF("Received command event\n");
1019 		sc->sc_cmd_result[0] = trb->dwTrb2;
1020 		sc->sc_cmd_result[1] = trb->dwTrb3;
1021 		cv_signal(&sc->sc_cmd_cv);
1022 		return (1);	/* command match */
1023 	}
1024 	return (0);
1025 }
1026 
1027 static int
1028 xhci_interrupt_poll(struct xhci_softc *sc)
1029 {
1030 	struct usb_page_search buf_res;
1031 	struct xhci_hw_root *phwr;
1032 	uint64_t addr;
1033 	uint32_t temp;
1034 	int retval = 0;
1035 	uint16_t i;
1036 	uint8_t event;
1037 	uint8_t j;
1038 	uint8_t k;
1039 	uint8_t t;
1040 
1041 	usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1042 
1043 	phwr = buf_res.buffer;
1044 
1045 	/* Receive any events */
1046 
1047 	usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1048 
1049 	i = sc->sc_event_idx;
1050 	j = sc->sc_event_ccs;
1051 	t = 2;
1052 
1053 	while (1) {
1054 
1055 		temp = le32toh(phwr->hwr_events[i].dwTrb3);
1056 
1057 		k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1058 
1059 		if (j != k)
1060 			break;
1061 
1062 		event = XHCI_TRB_3_TYPE_GET(temp);
1063 
1064 		DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1065 		    i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1066 		    (long)le32toh(phwr->hwr_events[i].dwTrb2),
1067 		    (long)le32toh(phwr->hwr_events[i].dwTrb3));
1068 
1069 		switch (event) {
1070 		case XHCI_TRB_EVENT_TRANSFER:
1071 			xhci_check_transfer(sc, &phwr->hwr_events[i]);
1072 			break;
1073 		case XHCI_TRB_EVENT_CMD_COMPLETE:
1074 			retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1075 			break;
1076 		default:
1077 			DPRINTF("Unhandled event = %u\n", event);
1078 			break;
1079 		}
1080 
1081 		i++;
1082 
1083 		if (i == XHCI_MAX_EVENTS) {
1084 			i = 0;
1085 			j ^= 1;
1086 
1087 			/* check for timeout */
1088 			if (!--t)
1089 				break;
1090 		}
1091 	}
1092 
1093 	sc->sc_event_idx = i;
1094 	sc->sc_event_ccs = j;
1095 
1096 	/*
1097 	 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1098 	 * latched. That means to activate the register we need to
1099 	 * write both the low and high double word of the 64-bit
1100 	 * register.
1101 	 */
1102 
1103 	addr = (uint32_t)buf_res.physaddr;
1104 	addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1105 
1106 	/* try to clear busy bit */
1107 	addr |= XHCI_ERDP_LO_BUSY;
1108 
1109 	XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1110 	XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1111 
1112 	return (retval);
1113 }
1114 
1115 static usb_error_t
1116 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1117     uint16_t timeout_ms)
1118 {
1119 	struct usb_page_search buf_res;
1120 	struct xhci_hw_root *phwr;
1121 	uint64_t addr;
1122 	uint32_t temp;
1123 	uint8_t i;
1124 	uint8_t j;
1125 	uint8_t timeout = 0;
1126 	int err;
1127 
1128 	XHCI_CMD_ASSERT_LOCKED(sc);
1129 
1130 	/* get hardware root structure */
1131 
1132 	usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1133 
1134 	phwr = buf_res.buffer;
1135 
1136 	/* Queue command */
1137 
1138 	USB_BUS_LOCK(&sc->sc_bus);
1139 retry:
1140 	i = sc->sc_command_idx;
1141 	j = sc->sc_command_ccs;
1142 
1143 	DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1144 	    i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1145 	    (long long)le64toh(trb->qwTrb0),
1146 	    (long)le32toh(trb->dwTrb2),
1147 	    (long)le32toh(trb->dwTrb3));
1148 
1149 	phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1150 	phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1151 
1152 	usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1153 
1154 	temp = trb->dwTrb3;
1155 
1156 	if (j)
1157 		temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1158 	else
1159 		temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1160 
1161 	temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1162 
1163 	phwr->hwr_commands[i].dwTrb3 = temp;
1164 
1165 	usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1166 
1167 	addr = buf_res.physaddr;
1168 	addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1169 
1170 	sc->sc_cmd_addr = htole64(addr);
1171 
1172 	i++;
1173 
1174 	if (i == (XHCI_MAX_COMMANDS - 1)) {
1175 
1176 		if (j) {
1177 			temp = htole32(XHCI_TRB_3_TC_BIT |
1178 			    XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1179 			    XHCI_TRB_3_CYCLE_BIT);
1180 		} else {
1181 			temp = htole32(XHCI_TRB_3_TC_BIT |
1182 			    XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1183 		}
1184 
1185 		phwr->hwr_commands[i].dwTrb3 = temp;
1186 
1187 		usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1188 
1189 		i = 0;
1190 		j ^= 1;
1191 	}
1192 
1193 	sc->sc_command_idx = i;
1194 	sc->sc_command_ccs = j;
1195 
1196 	XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1197 
1198 	err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1199 	    USB_MS_TO_TICKS(timeout_ms));
1200 
1201 	/*
1202 	 * In some error cases event interrupts are not generated.
1203 	 * Poll one time to see if the command has completed.
1204 	 */
1205 	if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1206 		DPRINTF("Command was completed when polling\n");
1207 		err = 0;
1208 	}
1209 	if (err != 0) {
1210 		DPRINTF("Command timeout!\n");
1211 		/*
1212 		 * After some weeks of continuous operation, it has
1213 		 * been observed that the ASMedia Technology, ASM1042
1214 		 * SuperSpeed USB Host Controller can suddenly stop
1215 		 * accepting commands via the command queue. Try to
1216 		 * first reset the command queue. If that fails do a
1217 		 * host controller reset.
1218 		 */
1219 		if (timeout == 0 &&
1220 		    xhci_reset_command_queue_locked(sc) == 0) {
1221 			timeout = 1;
1222 			goto retry;
1223 		} else {
1224 			DPRINTF("Controller reset!\n");
1225 			usb_bus_reset_async_locked(&sc->sc_bus);
1226 		}
1227 		err = USB_ERR_TIMEOUT;
1228 		trb->dwTrb2 = 0;
1229 		trb->dwTrb3 = 0;
1230 	} else {
1231 		temp = le32toh(sc->sc_cmd_result[0]);
1232 		if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1233 			err = USB_ERR_IOERROR;
1234 
1235 		trb->dwTrb2 = sc->sc_cmd_result[0];
1236 		trb->dwTrb3 = sc->sc_cmd_result[1];
1237 	}
1238 
1239 	USB_BUS_UNLOCK(&sc->sc_bus);
1240 
1241 	return (err);
1242 }
1243 
1244 #if 0
1245 static usb_error_t
1246 xhci_cmd_nop(struct xhci_softc *sc)
1247 {
1248 	struct xhci_trb trb;
1249 	uint32_t temp;
1250 
1251 	DPRINTF("\n");
1252 
1253 	trb.qwTrb0 = 0;
1254 	trb.dwTrb2 = 0;
1255 	temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1256 
1257 	trb.dwTrb3 = htole32(temp);
1258 
1259 	return (xhci_do_command(sc, &trb, 100 /* ms */));
1260 }
1261 #endif
1262 
1263 static usb_error_t
1264 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1265 {
1266 	struct xhci_trb trb;
1267 	uint32_t temp;
1268 	usb_error_t err;
1269 
1270 	DPRINTF("\n");
1271 
1272 	trb.qwTrb0 = 0;
1273 	trb.dwTrb2 = 0;
1274 	trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1275 
1276 	err = xhci_do_command(sc, &trb, 100 /* ms */);
1277 	if (err)
1278 		goto done;
1279 
1280 	temp = le32toh(trb.dwTrb3);
1281 
1282 	*pslot = XHCI_TRB_3_SLOT_GET(temp);
1283 
1284 done:
1285 	return (err);
1286 }
1287 
1288 static usb_error_t
1289 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1290 {
1291 	struct xhci_trb trb;
1292 	uint32_t temp;
1293 
1294 	DPRINTF("\n");
1295 
1296 	trb.qwTrb0 = 0;
1297 	trb.dwTrb2 = 0;
1298 	temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1299 	    XHCI_TRB_3_SLOT_SET(slot_id);
1300 
1301 	trb.dwTrb3 = htole32(temp);
1302 
1303 	return (xhci_do_command(sc, &trb, 100 /* ms */));
1304 }
1305 
1306 static usb_error_t
1307 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1308     uint8_t bsr, uint8_t slot_id)
1309 {
1310 	struct xhci_trb trb;
1311 	uint32_t temp;
1312 
1313 	DPRINTF("\n");
1314 
1315 	trb.qwTrb0 = htole64(input_ctx);
1316 	trb.dwTrb2 = 0;
1317 	temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1318 	    XHCI_TRB_3_SLOT_SET(slot_id);
1319 
1320 	if (bsr)
1321 		temp |= XHCI_TRB_3_BSR_BIT;
1322 
1323 	trb.dwTrb3 = htole32(temp);
1324 
1325 	return (xhci_do_command(sc, &trb, 500 /* ms */));
1326 }
1327 
1328 static usb_error_t
1329 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1330 {
1331 	struct usb_page_search buf_inp;
1332 	struct usb_page_search buf_dev;
1333 	struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1334 	struct xhci_hw_dev *hdev;
1335 	struct xhci_dev_ctx *pdev;
1336 	struct xhci_endpoint_ext *pepext;
1337 	uint32_t temp;
1338 	uint16_t mps;
1339 	usb_error_t err;
1340 	uint8_t index;
1341 
1342 	/* the root HUB case is not handled here */
1343 	if (udev->parent_hub == NULL)
1344 		return (USB_ERR_INVAL);
1345 
1346 	index = udev->controller_slot_id;
1347 
1348 	hdev = 	&sc->sc_hw.devs[index];
1349 
1350 	if (mtx != NULL)
1351 		mtx_unlock(mtx);
1352 
1353 	XHCI_CMD_LOCK(sc);
1354 
1355 	switch (hdev->state) {
1356 	case XHCI_ST_DEFAULT:
1357 	case XHCI_ST_ENABLED:
1358 
1359 		hdev->state = XHCI_ST_ENABLED;
1360 
1361 		/* set configure mask to slot and EP0 */
1362 		xhci_configure_mask(udev, 3, 0);
1363 
1364 		/* configure input slot context structure */
1365 		err = xhci_configure_device(udev);
1366 
1367 		if (err != 0) {
1368 			DPRINTF("Could not configure device\n");
1369 			break;
1370 		}
1371 
1372 		/* configure input endpoint context structure */
1373 		switch (udev->speed) {
1374 		case USB_SPEED_LOW:
1375 		case USB_SPEED_FULL:
1376 			mps = 8;
1377 			break;
1378 		case USB_SPEED_HIGH:
1379 			mps = 64;
1380 			break;
1381 		default:
1382 			mps = 512;
1383 			break;
1384 		}
1385 
1386 		pepext = xhci_get_endpoint_ext(udev,
1387 		    &udev->ctrl_ep_desc);
1388 		err = xhci_configure_endpoint(udev,
1389 		    &udev->ctrl_ep_desc, pepext,
1390 		    0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1391 
1392 		if (err != 0) {
1393 			DPRINTF("Could not configure default endpoint\n");
1394 			break;
1395 		}
1396 
1397 		/* execute set address command */
1398 		usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1399 
1400 		err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1401 		    (address == 0), index);
1402 
1403 		if (err != 0) {
1404 			temp = le32toh(sc->sc_cmd_result[0]);
1405 			if (address == 0 && sc->sc_port_route != NULL &&
1406 			    XHCI_TRB_2_ERROR_GET(temp) ==
1407 			    XHCI_TRB_ERROR_PARAMETER) {
1408 				/* LynxPoint XHCI - ports are not switchable */
1409 				/* Un-route all ports from the XHCI */
1410 				sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1411 			}
1412 			DPRINTF("Could not set address "
1413 			    "for slot %u.\n", index);
1414 			if (address != 0)
1415 				break;
1416 		}
1417 
1418 		/* update device address to new value */
1419 
1420 		usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1421 		pdev = buf_dev.buffer;
1422 		usb_pc_cpu_invalidate(&hdev->device_pc);
1423 
1424 		temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1425 		udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1426 
1427 		/* update device state to new value */
1428 
1429 		if (address != 0)
1430 			hdev->state = XHCI_ST_ADDRESSED;
1431 		else
1432 			hdev->state = XHCI_ST_DEFAULT;
1433 		break;
1434 
1435 	default:
1436 		DPRINTF("Wrong state for set address.\n");
1437 		err = USB_ERR_IOERROR;
1438 		break;
1439 	}
1440 	XHCI_CMD_UNLOCK(sc);
1441 
1442 	if (mtx != NULL)
1443 		mtx_lock(mtx);
1444 
1445 	return (err);
1446 }
1447 
1448 static usb_error_t
1449 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1450     uint8_t deconfigure, uint8_t slot_id)
1451 {
1452 	struct xhci_trb trb;
1453 	uint32_t temp;
1454 
1455 	DPRINTF("\n");
1456 
1457 	trb.qwTrb0 = htole64(input_ctx);
1458 	trb.dwTrb2 = 0;
1459 	temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1460 	    XHCI_TRB_3_SLOT_SET(slot_id);
1461 
1462 	if (deconfigure)
1463 		temp |= XHCI_TRB_3_DCEP_BIT;
1464 
1465 	trb.dwTrb3 = htole32(temp);
1466 
1467 	return (xhci_do_command(sc, &trb, 100 /* ms */));
1468 }
1469 
1470 static usb_error_t
1471 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1472     uint8_t slot_id)
1473 {
1474 	struct xhci_trb trb;
1475 	uint32_t temp;
1476 
1477 	DPRINTF("\n");
1478 
1479 	trb.qwTrb0 = htole64(input_ctx);
1480 	trb.dwTrb2 = 0;
1481 	temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1482 	    XHCI_TRB_3_SLOT_SET(slot_id);
1483 	trb.dwTrb3 = htole32(temp);
1484 
1485 	return (xhci_do_command(sc, &trb, 100 /* ms */));
1486 }
1487 
1488 static usb_error_t
1489 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1490     uint8_t ep_id, uint8_t slot_id)
1491 {
1492 	struct xhci_trb trb;
1493 	uint32_t temp;
1494 
1495 	DPRINTF("\n");
1496 
1497 	trb.qwTrb0 = 0;
1498 	trb.dwTrb2 = 0;
1499 	temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1500 	    XHCI_TRB_3_SLOT_SET(slot_id) |
1501 	    XHCI_TRB_3_EP_SET(ep_id);
1502 
1503 	if (preserve)
1504 		temp |= XHCI_TRB_3_PRSV_BIT;
1505 
1506 	trb.dwTrb3 = htole32(temp);
1507 
1508 	return (xhci_do_command(sc, &trb, 100 /* ms */));
1509 }
1510 
1511 static usb_error_t
1512 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1513     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1514 {
1515 	struct xhci_trb trb;
1516 	uint32_t temp;
1517 
1518 	DPRINTF("\n");
1519 
1520 	trb.qwTrb0 = htole64(dequeue_ptr);
1521 
1522 	temp = XHCI_TRB_2_STREAM_SET(stream_id);
1523 	trb.dwTrb2 = htole32(temp);
1524 
1525 	temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1526 	    XHCI_TRB_3_SLOT_SET(slot_id) |
1527 	    XHCI_TRB_3_EP_SET(ep_id);
1528 	trb.dwTrb3 = htole32(temp);
1529 
1530 	return (xhci_do_command(sc, &trb, 100 /* ms */));
1531 }
1532 
1533 static usb_error_t
1534 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1535     uint8_t ep_id, uint8_t slot_id)
1536 {
1537 	struct xhci_trb trb;
1538 	uint32_t temp;
1539 
1540 	DPRINTF("\n");
1541 
1542 	trb.qwTrb0 = 0;
1543 	trb.dwTrb2 = 0;
1544 	temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1545 	    XHCI_TRB_3_SLOT_SET(slot_id) |
1546 	    XHCI_TRB_3_EP_SET(ep_id);
1547 
1548 	if (suspend)
1549 		temp |= XHCI_TRB_3_SUSP_EP_BIT;
1550 
1551 	trb.dwTrb3 = htole32(temp);
1552 
1553 	return (xhci_do_command(sc, &trb, 100 /* ms */));
1554 }
1555 
1556 static usb_error_t
1557 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1558 {
1559 	struct xhci_trb trb;
1560 	uint32_t temp;
1561 
1562 	DPRINTF("\n");
1563 
1564 	trb.qwTrb0 = 0;
1565 	trb.dwTrb2 = 0;
1566 	temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1567 	    XHCI_TRB_3_SLOT_SET(slot_id);
1568 
1569 	trb.dwTrb3 = htole32(temp);
1570 
1571 	return (xhci_do_command(sc, &trb, 100 /* ms */));
1572 }
1573 
1574 /*------------------------------------------------------------------------*
1575  *	xhci_interrupt - XHCI interrupt handler
1576  *------------------------------------------------------------------------*/
1577 void
1578 xhci_interrupt(struct xhci_softc *sc)
1579 {
1580 	uint32_t status;
1581 	uint32_t temp;
1582 
1583 	USB_BUS_LOCK(&sc->sc_bus);
1584 
1585 	status = XREAD4(sc, oper, XHCI_USBSTS);
1586 
1587 	/* acknowledge interrupts, if any */
1588 	if (status != 0) {
1589 		XWRITE4(sc, oper, XHCI_USBSTS, status);
1590 		DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1591 	}
1592 
1593 	temp = XREAD4(sc, runt, XHCI_IMAN(0));
1594 
1595 	/* force clearing of pending interrupts */
1596 	if (temp & XHCI_IMAN_INTR_PEND)
1597 		XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1598 
1599 	/* check for event(s) */
1600 	xhci_interrupt_poll(sc);
1601 
1602 	if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1603 	    XHCI_STS_HSE | XHCI_STS_HCE)) {
1604 
1605 		if (status & XHCI_STS_PCD) {
1606 			xhci_root_intr(sc);
1607 		}
1608 
1609 		if (status & XHCI_STS_HCH) {
1610 			printf("%s: host controller halted\n",
1611 			    __FUNCTION__);
1612 		}
1613 
1614 		if (status & XHCI_STS_HSE) {
1615 			printf("%s: host system error\n",
1616 			    __FUNCTION__);
1617 		}
1618 
1619 		if (status & XHCI_STS_HCE) {
1620 			printf("%s: host controller error\n",
1621 			   __FUNCTION__);
1622 		}
1623 	}
1624 	USB_BUS_UNLOCK(&sc->sc_bus);
1625 }
1626 
1627 /*------------------------------------------------------------------------*
1628  *	xhci_timeout - XHCI timeout handler
1629  *------------------------------------------------------------------------*/
1630 static void
1631 xhci_timeout(void *arg)
1632 {
1633 	struct usb_xfer *xfer = arg;
1634 
1635 	DPRINTF("xfer=%p\n", xfer);
1636 
1637 	USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1638 
1639 	/* transfer is transferred */
1640 	xhci_device_done(xfer, USB_ERR_TIMEOUT);
1641 }
1642 
1643 static void
1644 xhci_do_poll(struct usb_bus *bus)
1645 {
1646 	struct xhci_softc *sc = XHCI_BUS2SC(bus);
1647 
1648 	USB_BUS_LOCK(&sc->sc_bus);
1649 	xhci_interrupt_poll(sc);
1650 	USB_BUS_UNLOCK(&sc->sc_bus);
1651 }
1652 
1653 static void
1654 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1655 {
1656 	struct usb_page_search buf_res;
1657 	struct xhci_td *td;
1658 	struct xhci_td *td_next;
1659 	struct xhci_td *td_alt_next;
1660 	struct xhci_td *td_first;
1661 	uint32_t buf_offset;
1662 	uint32_t average;
1663 	uint32_t len_old;
1664 	uint32_t npkt_off;
1665 	uint32_t dword;
1666 	uint8_t shortpkt_old;
1667 	uint8_t precompute;
1668 	uint8_t x;
1669 
1670 	td_alt_next = NULL;
1671 	buf_offset = 0;
1672 	shortpkt_old = temp->shortpkt;
1673 	len_old = temp->len;
1674 	npkt_off = 0;
1675 	precompute = 1;
1676 
1677 restart:
1678 
1679 	td = temp->td;
1680 	td_next = td_first = temp->td_next;
1681 
1682 	while (1) {
1683 
1684 		if (temp->len == 0) {
1685 
1686 			if (temp->shortpkt)
1687 				break;
1688 
1689 			/* send a Zero Length Packet, ZLP, last */
1690 
1691 			temp->shortpkt = 1;
1692 			average = 0;
1693 
1694 		} else {
1695 
1696 			average = temp->average;
1697 
1698 			if (temp->len < average) {
1699 				if (temp->len % temp->max_packet_size) {
1700 					temp->shortpkt = 1;
1701 				}
1702 				average = temp->len;
1703 			}
1704 		}
1705 
1706 		if (td_next == NULL)
1707 			panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1708 
1709 		/* get next TD */
1710 
1711 		td = td_next;
1712 		td_next = td->obj_next;
1713 
1714 		/* check if we are pre-computing */
1715 
1716 		if (precompute) {
1717 
1718 			/* update remaining length */
1719 
1720 			temp->len -= average;
1721 
1722 			continue;
1723 		}
1724 		/* fill out current TD */
1725 
1726 		td->len = average;
1727 		td->remainder = 0;
1728 		td->status = 0;
1729 
1730 		/* update remaining length */
1731 
1732 		temp->len -= average;
1733 
1734 		/* reset TRB index */
1735 
1736 		x = 0;
1737 
1738 		if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1739 			/* immediate data */
1740 
1741 			if (average > 8)
1742 				average = 8;
1743 
1744 			td->td_trb[0].qwTrb0 = 0;
1745 
1746 			usbd_copy_out(temp->pc, temp->offset + buf_offset,
1747 			   (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1748 			   average);
1749 
1750 			dword = XHCI_TRB_2_BYTES_SET(8) |
1751 			    XHCI_TRB_2_TDSZ_SET(0) |
1752 			    XHCI_TRB_2_IRQ_SET(0);
1753 
1754 			td->td_trb[0].dwTrb2 = htole32(dword);
1755 
1756 			dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1757 			  XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1758 
1759 			/* check wLength */
1760 			if (td->td_trb[0].qwTrb0 &
1761 			   htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1762 				if (td->td_trb[0].qwTrb0 & htole64(1))
1763 					dword |= XHCI_TRB_3_TRT_IN;
1764 				else
1765 					dword |= XHCI_TRB_3_TRT_OUT;
1766 			}
1767 
1768 			td->td_trb[0].dwTrb3 = htole32(dword);
1769 #ifdef USB_DEBUG
1770 			xhci_dump_trb(&td->td_trb[x]);
1771 #endif
1772 			x++;
1773 
1774 		} else do {
1775 
1776 			uint32_t npkt;
1777 
1778 			/* fill out buffer pointers */
1779 
1780 			if (average == 0) {
1781 				memset(&buf_res, 0, sizeof(buf_res));
1782 			} else {
1783 				usbd_get_page(temp->pc, temp->offset +
1784 				    buf_offset, &buf_res);
1785 
1786 				/* get length to end of page */
1787 				if (buf_res.length > average)
1788 					buf_res.length = average;
1789 
1790 				/* check for maximum length */
1791 				if (buf_res.length > XHCI_TD_PAGE_SIZE)
1792 					buf_res.length = XHCI_TD_PAGE_SIZE;
1793 
1794 				npkt_off += buf_res.length;
1795 			}
1796 
1797 			/* setup npkt */
1798 			npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1799 			    temp->max_packet_size;
1800 
1801 			if (npkt == 0)
1802 				npkt = 1;
1803 			else if (npkt > 31)
1804 				npkt = 31;
1805 
1806 			/* fill out TRB's */
1807 			td->td_trb[x].qwTrb0 =
1808 			    htole64((uint64_t)buf_res.physaddr);
1809 
1810 			dword =
1811 			  XHCI_TRB_2_BYTES_SET(buf_res.length) |
1812 			  XHCI_TRB_2_TDSZ_SET(npkt) |
1813 			  XHCI_TRB_2_IRQ_SET(0);
1814 
1815 			td->td_trb[x].dwTrb2 = htole32(dword);
1816 
1817 			switch (temp->trb_type) {
1818 			case XHCI_TRB_TYPE_ISOCH:
1819 				dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1820 				    XHCI_TRB_3_TBC_SET(temp->tbc) |
1821 				    XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1822 				if (td != td_first) {
1823 					dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1824 				} else if (temp->do_isoc_sync != 0) {
1825 					temp->do_isoc_sync = 0;
1826 					/* wait until "isoc_frame" */
1827 					dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1828 					    XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1829 				} else {
1830 					/* start data transfer at next interval */
1831 					dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1832 					    XHCI_TRB_3_ISO_SIA_BIT;
1833 				}
1834 				if (temp->direction == UE_DIR_IN)
1835 					dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1836 				break;
1837 			case XHCI_TRB_TYPE_DATA_STAGE:
1838 				dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1839 				    XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) |
1840 				    XHCI_TRB_3_TBC_SET(temp->tbc) |
1841 				    XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1842 				if (temp->direction == UE_DIR_IN)
1843 					dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1844 				break;
1845 			case XHCI_TRB_TYPE_STATUS_STAGE:
1846 				dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1847 				    XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) |
1848 				    XHCI_TRB_3_TBC_SET(temp->tbc) |
1849 				    XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1850 				if (temp->direction == UE_DIR_IN)
1851 					dword |= XHCI_TRB_3_DIR_IN;
1852 				break;
1853 			default:	/* XHCI_TRB_TYPE_NORMAL */
1854 				dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1855 				    XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
1856 				    XHCI_TRB_3_TBC_SET(temp->tbc) |
1857 				    XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1858 				if (temp->direction == UE_DIR_IN)
1859 					dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1860 				break;
1861 			}
1862 			td->td_trb[x].dwTrb3 = htole32(dword);
1863 
1864 			average -= buf_res.length;
1865 			buf_offset += buf_res.length;
1866 #ifdef USB_DEBUG
1867 			xhci_dump_trb(&td->td_trb[x]);
1868 #endif
1869 			x++;
1870 
1871 		} while (average != 0);
1872 
1873 		td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1874 
1875 		/* store number of data TRB's */
1876 
1877 		td->ntrb = x;
1878 
1879 		DPRINTF("NTRB=%u\n", x);
1880 
1881 		/* fill out link TRB */
1882 
1883 		if (td_next != NULL) {
1884 			/* link the current TD with the next one */
1885 			td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1886 			DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1887 		} else {
1888 			/* this field will get updated later */
1889 			DPRINTF("NOLINK\n");
1890 		}
1891 
1892 		dword = XHCI_TRB_2_IRQ_SET(0);
1893 
1894 		td->td_trb[x].dwTrb2 = htole32(dword);
1895 
1896 		dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1897 		    XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1898 		    /*
1899 		     * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1900 		     * frame only receives a single short packet event
1901 		     * by setting the CHAIN bit in the LINK field. In
1902 		     * addition some XHCI controllers have problems
1903 		     * sending a ZLP unless the CHAIN-BIT is set in
1904 		     * the LINK TRB.
1905 		     */
1906 		    XHCI_TRB_3_CHAIN_BIT;
1907 
1908 		td->td_trb[x].dwTrb3 = htole32(dword);
1909 
1910 		td->alt_next = td_alt_next;
1911 #ifdef USB_DEBUG
1912 		xhci_dump_trb(&td->td_trb[x]);
1913 #endif
1914 		usb_pc_cpu_flush(td->page_cache);
1915 	}
1916 
1917 	if (precompute) {
1918 		precompute = 0;
1919 
1920 		/* setup alt next pointer, if any */
1921 		if (temp->last_frame) {
1922 			td_alt_next = NULL;
1923 		} else {
1924 			/* we use this field internally */
1925 			td_alt_next = td_next;
1926 		}
1927 
1928 		/* restore */
1929 		temp->shortpkt = shortpkt_old;
1930 		temp->len = len_old;
1931 		goto restart;
1932 	}
1933 
1934 	/*
1935 	 * Remove cycle bit from the first TRB if we are
1936 	 * stepping them:
1937 	 */
1938 	if (temp->step_td != 0) {
1939 		td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1940 		usb_pc_cpu_flush(td_first->page_cache);
1941 	}
1942 
1943 	/* clear TD SIZE to zero, hence this is the last TRB */
1944 	/* remove chain bit because this is the last data TRB in the chain */
1945 	td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1946 	td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1947 	/* remove CHAIN-BIT from last LINK TRB */
1948 	td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1949 
1950 	usb_pc_cpu_flush(td->page_cache);
1951 
1952 	temp->td = td;
1953 	temp->td_next = td_next;
1954 }
1955 
1956 static void
1957 xhci_setup_generic_chain(struct usb_xfer *xfer)
1958 {
1959 	struct xhci_std_temp temp;
1960 	struct xhci_td *td;
1961 	uint32_t x;
1962 	uint32_t y;
1963 	uint8_t mult;
1964 
1965 	temp.do_isoc_sync = 0;
1966 	temp.step_td = 0;
1967 	temp.tbc = 0;
1968 	temp.tlbpc = 0;
1969 	temp.average = xfer->max_hc_frame_size;
1970 	temp.max_packet_size = xfer->max_packet_size;
1971 	temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1972 	temp.pc = NULL;
1973 	temp.last_frame = 0;
1974 	temp.offset = 0;
1975 	temp.multishort = xfer->flags_int.isochronous_xfr ||
1976 	    xfer->flags_int.control_xfr ||
1977 	    xfer->flags_int.short_frames_ok;
1978 
1979 	/* toggle the DMA set we are using */
1980 	xfer->flags_int.curr_dma_set ^= 1;
1981 
1982 	/* get next DMA set */
1983 	td = xfer->td_start[xfer->flags_int.curr_dma_set];
1984 
1985 	temp.td = NULL;
1986 	temp.td_next = td;
1987 
1988 	xfer->td_transfer_first = td;
1989 	xfer->td_transfer_cache = td;
1990 
1991 	if (xfer->flags_int.isochronous_xfr) {
1992 		uint8_t shift;
1993 
1994 		/* compute multiplier for ISOCHRONOUS transfers */
1995 		mult = xfer->endpoint->ecomp ?
1996 		    UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
1997 		    : 0;
1998 		/* check for USB 2.0 multiplier */
1999 		if (mult == 0) {
2000 			mult = (xfer->endpoint->edesc->
2001 			    wMaxPacketSize[1] >> 3) & 3;
2002 		}
2003 		/* range check */
2004 		if (mult > 2)
2005 			mult = 3;
2006 		else
2007 			mult++;
2008 
2009 		x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2010 
2011 		DPRINTF("MFINDEX=0x%08x\n", x);
2012 
2013 		switch (usbd_get_speed(xfer->xroot->udev)) {
2014 		case USB_SPEED_FULL:
2015 			shift = 3;
2016 			temp.isoc_delta = 8;	/* 1ms */
2017 			x += temp.isoc_delta - 1;
2018 			x &= ~(temp.isoc_delta - 1);
2019 			break;
2020 		default:
2021 			shift = usbd_xfer_get_fps_shift(xfer);
2022 			temp.isoc_delta = 1U << shift;
2023 			x += temp.isoc_delta - 1;
2024 			x &= ~(temp.isoc_delta - 1);
2025 			/* simple frame load balancing */
2026 			x += xfer->endpoint->usb_uframe;
2027 			break;
2028 		}
2029 
2030 		y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2031 
2032 		if ((xfer->endpoint->is_synced == 0) ||
2033 		    (y < (xfer->nframes << shift)) ||
2034 		    (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2035 			/*
2036 			 * If there is data underflow or the pipe
2037 			 * queue is empty we schedule the transfer a
2038 			 * few frames ahead of the current frame
2039 			 * position. Else two isochronous transfers
2040 			 * might overlap.
2041 			 */
2042 			xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2043 			xfer->endpoint->is_synced = 1;
2044 			temp.do_isoc_sync = 1;
2045 
2046 			DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2047 		}
2048 
2049 		/* compute isochronous completion time */
2050 
2051 		y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2052 
2053 		xfer->isoc_time_complete =
2054 		    usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2055 		    (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2056 
2057 		x = 0;
2058 		temp.isoc_frame = xfer->endpoint->isoc_next;
2059 		temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2060 
2061 		xfer->endpoint->isoc_next += xfer->nframes << shift;
2062 
2063 	} else if (xfer->flags_int.control_xfr) {
2064 
2065 		/* check if we should prepend a setup message */
2066 
2067 		if (xfer->flags_int.control_hdr) {
2068 
2069 			temp.len = xfer->frlengths[0];
2070 			temp.pc = xfer->frbuffers + 0;
2071 			temp.shortpkt = temp.len ? 1 : 0;
2072 			temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2073 			temp.direction = 0;
2074 
2075 			/* check for last frame */
2076 			if (xfer->nframes == 1) {
2077 				/* no STATUS stage yet, SETUP is last */
2078 				if (xfer->flags_int.control_act)
2079 					temp.last_frame = 1;
2080 			}
2081 
2082 			xhci_setup_generic_chain_sub(&temp);
2083 		}
2084 		x = 1;
2085 		mult = 1;
2086 		temp.isoc_delta = 0;
2087 		temp.isoc_frame = 0;
2088 		temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
2089 	} else {
2090 		x = 0;
2091 		mult = 1;
2092 		temp.isoc_delta = 0;
2093 		temp.isoc_frame = 0;
2094 		temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2095 	}
2096 
2097 	if (x != xfer->nframes) {
2098                 /* setup page_cache pointer */
2099                 temp.pc = xfer->frbuffers + x;
2100 		/* set endpoint direction */
2101 		temp.direction = UE_GET_DIR(xfer->endpointno);
2102 	}
2103 
2104 	while (x != xfer->nframes) {
2105 
2106 		/* DATA0 / DATA1 message */
2107 
2108 		temp.len = xfer->frlengths[x];
2109 		temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2110 		    x != 0 && temp.multishort == 0);
2111 
2112 		x++;
2113 
2114 		if (x == xfer->nframes) {
2115 			if (xfer->flags_int.control_xfr) {
2116 				/* no STATUS stage yet, DATA is last */
2117 				if (xfer->flags_int.control_act)
2118 					temp.last_frame = 1;
2119 			} else {
2120 				temp.last_frame = 1;
2121 			}
2122 		}
2123 		if (temp.len == 0) {
2124 
2125 			/* make sure that we send an USB packet */
2126 
2127 			temp.shortpkt = 0;
2128 
2129 			temp.tbc = 0;
2130 			temp.tlbpc = mult - 1;
2131 
2132 		} else if (xfer->flags_int.isochronous_xfr) {
2133 
2134 			uint8_t tdpc;
2135 
2136 			/*
2137 			 * Isochronous transfers don't have short
2138 			 * packet termination:
2139 			 */
2140 
2141 			temp.shortpkt = 1;
2142 
2143 			/* isochronous transfers have a transfer limit */
2144 
2145 			if (temp.len > xfer->max_frame_size)
2146 				temp.len = xfer->max_frame_size;
2147 
2148 			/* compute TD packet count */
2149 			tdpc = (temp.len + xfer->max_packet_size - 1) /
2150 			    xfer->max_packet_size;
2151 
2152 			temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2153 			temp.tlbpc = (tdpc % mult);
2154 
2155 			if (temp.tlbpc == 0)
2156 				temp.tlbpc = mult - 1;
2157 			else
2158 				temp.tlbpc--;
2159 		} else {
2160 
2161 			/* regular data transfer */
2162 
2163 			temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2164 		}
2165 
2166 		xhci_setup_generic_chain_sub(&temp);
2167 
2168 		if (xfer->flags_int.isochronous_xfr) {
2169 			temp.offset += xfer->frlengths[x - 1];
2170 			temp.isoc_frame += temp.isoc_delta;
2171 		} else {
2172 			/* get next Page Cache pointer */
2173 			temp.pc = xfer->frbuffers + x;
2174 		}
2175 	}
2176 
2177 	/* check if we should append a status stage */
2178 
2179 	if (xfer->flags_int.control_xfr &&
2180 	    !xfer->flags_int.control_act) {
2181 
2182 		/*
2183 		 * Send a DATA1 message and invert the current
2184 		 * endpoint direction.
2185 		 */
2186 		temp.step_td = (xfer->nframes != 0);
2187 		temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2188 		temp.len = 0;
2189 		temp.pc = NULL;
2190 		temp.shortpkt = 0;
2191 		temp.last_frame = 1;
2192 		temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2193 
2194 		xhci_setup_generic_chain_sub(&temp);
2195 	}
2196 
2197 	td = temp.td;
2198 
2199 	/* must have at least one frame! */
2200 
2201 	xfer->td_transfer_last = td;
2202 
2203 	DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2204 }
2205 
2206 static void
2207 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2208 {
2209 	struct usb_page_search buf_res;
2210 	struct xhci_dev_ctx_addr *pdctxa;
2211 
2212 	usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2213 
2214 	pdctxa = buf_res.buffer;
2215 
2216 	DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2217 
2218 	pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2219 
2220 	usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2221 }
2222 
2223 static usb_error_t
2224 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2225 {
2226 	struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2227 	struct usb_page_search buf_inp;
2228 	struct xhci_input_dev_ctx *pinp;
2229 	uint32_t temp;
2230 	uint8_t index;
2231 	uint8_t x;
2232 
2233 	index = udev->controller_slot_id;
2234 
2235 	usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2236 
2237 	pinp = buf_inp.buffer;
2238 
2239 	if (drop) {
2240 		mask &= XHCI_INCTX_NON_CTRL_MASK;
2241 		xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2242 		xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2243 	} else {
2244 		xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2245 		xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2246 
2247 		/* find most significant set bit */
2248 		for (x = 31; x != 1; x--) {
2249 			if (mask & (1 << x))
2250 				break;
2251 		}
2252 
2253 		/* adjust */
2254 		x--;
2255 
2256 		/* figure out maximum */
2257 		if (x > sc->sc_hw.devs[index].context_num) {
2258 			sc->sc_hw.devs[index].context_num = x;
2259 			temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2260 			temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2261 			temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2262 			xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2263 		}
2264 	}
2265 	return (0);
2266 }
2267 
2268 static usb_error_t
2269 xhci_configure_endpoint(struct usb_device *udev,
2270     struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2271     uint16_t interval, uint8_t max_packet_count,
2272     uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2273     uint16_t max_frame_size, uint8_t ep_mode)
2274 {
2275 	struct usb_page_search buf_inp;
2276 	struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2277 	struct xhci_input_dev_ctx *pinp;
2278 	uint64_t ring_addr = pepext->physaddr;
2279 	uint32_t temp;
2280 	uint8_t index;
2281 	uint8_t epno;
2282 	uint8_t type;
2283 
2284 	index = udev->controller_slot_id;
2285 
2286 	usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2287 
2288 	pinp = buf_inp.buffer;
2289 
2290 	epno = edesc->bEndpointAddress;
2291 	type = edesc->bmAttributes & UE_XFERTYPE;
2292 
2293 	if (type == UE_CONTROL)
2294 		epno |= UE_DIR_IN;
2295 
2296 	epno = XHCI_EPNO2EPID(epno);
2297 
2298  	if (epno == 0)
2299 		return (USB_ERR_NO_PIPE);		/* invalid */
2300 
2301 	if (max_packet_count == 0)
2302 		return (USB_ERR_BAD_BUFSIZE);
2303 
2304 	max_packet_count--;
2305 
2306 	if (mult == 0)
2307 		return (USB_ERR_BAD_BUFSIZE);
2308 
2309 	/* store endpoint mode */
2310 	pepext->trb_ep_mode = ep_mode;
2311 	usb_pc_cpu_flush(pepext->page_cache);
2312 
2313 	if (ep_mode == USB_EP_MODE_STREAMS) {
2314 		temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2315 		    XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2316 		    XHCI_EPCTX_0_LSA_SET(1);
2317 
2318 		ring_addr += sizeof(struct xhci_trb) *
2319 		    XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2320 	} else {
2321 		temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2322 		    XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2323 		    XHCI_EPCTX_0_LSA_SET(0);
2324 
2325 		ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2326 	}
2327 
2328 	switch (udev->speed) {
2329 	case USB_SPEED_FULL:
2330 	case USB_SPEED_LOW:
2331 		/* 1ms -> 125us */
2332 		fps_shift += 3;
2333 		break;
2334 	default:
2335 		break;
2336 	}
2337 
2338 	switch (type) {
2339 	case UE_INTERRUPT:
2340 		if (fps_shift > 3)
2341 			fps_shift--;
2342 		temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2343 		break;
2344 	case UE_ISOCHRONOUS:
2345 		temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2346 
2347 		switch (udev->speed) {
2348 		case USB_SPEED_SUPER:
2349 			if (mult > 3)
2350 				mult = 3;
2351 			temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2352 			max_packet_count /= mult;
2353 			break;
2354 		default:
2355 			break;
2356 		}
2357 		break;
2358 	default:
2359 		break;
2360 	}
2361 
2362 	xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2363 
2364 	temp =
2365 	    XHCI_EPCTX_1_HID_SET(0) |
2366 	    XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2367 	    XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2368 
2369 	if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2370 		if (type != UE_ISOCHRONOUS)
2371 			temp |= XHCI_EPCTX_1_CERR_SET(3);
2372 	}
2373 
2374 	switch (type) {
2375 	case UE_CONTROL:
2376 		temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2377 		break;
2378 	case UE_ISOCHRONOUS:
2379 		temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2380 		break;
2381 	case UE_BULK:
2382 		temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2383 		break;
2384 	default:
2385 		temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2386 		break;
2387 	}
2388 
2389 	/* check for IN direction */
2390 	if (epno & 1)
2391 		temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2392 
2393 	xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2394 	xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2395 
2396 	switch (edesc->bmAttributes & UE_XFERTYPE) {
2397 	case UE_INTERRUPT:
2398 	case UE_ISOCHRONOUS:
2399 		temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2400 		    XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2401 		    max_frame_size));
2402 		break;
2403 	case UE_CONTROL:
2404 		temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2405 		break;
2406 	default:
2407 		temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2408 		break;
2409 	}
2410 
2411 	xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2412 
2413 #ifdef USB_DEBUG
2414 	xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2415 #endif
2416 	usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2417 
2418 	return (0);		/* success */
2419 }
2420 
2421 static usb_error_t
2422 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2423 {
2424 	struct xhci_endpoint_ext *pepext;
2425 	struct usb_endpoint_ss_comp_descriptor *ecomp;
2426 	usb_stream_t x;
2427 
2428 	pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2429 	    xfer->endpoint->edesc);
2430 
2431 	ecomp = xfer->endpoint->ecomp;
2432 
2433 	for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2434 		uint64_t temp;
2435 
2436 		/* halt any transfers */
2437 		pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2438 
2439 		/* compute start of TRB ring for stream "x" */
2440 		temp = pepext->physaddr +
2441 		    (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2442 		    XHCI_SCTX_0_SCT_SEC_TR_RING;
2443 
2444 		/* make tree structure */
2445 		pepext->trb[(XHCI_MAX_TRANSFERS *
2446 		    XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2447 
2448 		/* reserved fields */
2449 		pepext->trb[(XHCI_MAX_TRANSFERS *
2450                     XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2451 		pepext->trb[(XHCI_MAX_TRANSFERS *
2452 		    XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2453 	}
2454 	usb_pc_cpu_flush(pepext->page_cache);
2455 
2456 	return (xhci_configure_endpoint(xfer->xroot->udev,
2457 	    xfer->endpoint->edesc, pepext,
2458 	    xfer->interval, xfer->max_packet_count,
2459 	    (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2460 	    usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2461 	    xfer->max_frame_size, xfer->endpoint->ep_mode));
2462 }
2463 
2464 static usb_error_t
2465 xhci_configure_device(struct usb_device *udev)
2466 {
2467 	struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2468 	struct usb_page_search buf_inp;
2469 	struct usb_page_cache *pcinp;
2470 	struct xhci_input_dev_ctx *pinp;
2471 	struct usb_device *hubdev;
2472 	uint32_t temp;
2473 	uint32_t route;
2474 	uint32_t rh_port;
2475 	uint8_t is_hub;
2476 	uint8_t index;
2477 	uint8_t depth;
2478 
2479 	index = udev->controller_slot_id;
2480 
2481 	DPRINTF("index=%u\n", index);
2482 
2483 	pcinp = &sc->sc_hw.devs[index].input_pc;
2484 
2485 	usbd_get_page(pcinp, 0, &buf_inp);
2486 
2487 	pinp = buf_inp.buffer;
2488 
2489 	rh_port = 0;
2490 	route = 0;
2491 
2492 	/* figure out route string and root HUB port number */
2493 
2494 	for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2495 
2496 		if (hubdev->parent_hub == NULL)
2497 			break;
2498 
2499 		depth = hubdev->parent_hub->depth;
2500 
2501 		/*
2502 		 * NOTE: HS/FS/LS devices and the SS root HUB can have
2503 		 * more than 15 ports
2504 		 */
2505 
2506 		rh_port = hubdev->port_no;
2507 
2508 		if (depth == 0)
2509 			break;
2510 
2511 		if (rh_port > 15)
2512 			rh_port = 15;
2513 
2514 		if (depth < 6)
2515 			route |= rh_port << (4 * (depth - 1));
2516 	}
2517 
2518 	DPRINTF("Route=0x%08x\n", route);
2519 
2520 	temp = XHCI_SCTX_0_ROUTE_SET(route) |
2521 	    XHCI_SCTX_0_CTX_NUM_SET(
2522 	    sc->sc_hw.devs[index].context_num + 1);
2523 
2524 	switch (udev->speed) {
2525 	case USB_SPEED_LOW:
2526 		temp |= XHCI_SCTX_0_SPEED_SET(2);
2527 		if (udev->parent_hs_hub != NULL &&
2528 		    udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2529 		    UDPROTO_HSHUBMTT) {
2530 			DPRINTF("Device inherits MTT\n");
2531 			temp |= XHCI_SCTX_0_MTT_SET(1);
2532 		}
2533 		break;
2534 	case USB_SPEED_HIGH:
2535 		temp |= XHCI_SCTX_0_SPEED_SET(3);
2536 		if (sc->sc_hw.devs[index].nports != 0 &&
2537 		    udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2538 			DPRINTF("HUB supports MTT\n");
2539 			temp |= XHCI_SCTX_0_MTT_SET(1);
2540 		}
2541 		break;
2542 	case USB_SPEED_FULL:
2543 		temp |= XHCI_SCTX_0_SPEED_SET(1);
2544 		if (udev->parent_hs_hub != NULL &&
2545 		    udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2546 		    UDPROTO_HSHUBMTT) {
2547 			DPRINTF("Device inherits MTT\n");
2548 			temp |= XHCI_SCTX_0_MTT_SET(1);
2549 		}
2550 		break;
2551 	default:
2552 		temp |= XHCI_SCTX_0_SPEED_SET(4);
2553 		break;
2554 	}
2555 
2556 	is_hub = sc->sc_hw.devs[index].nports != 0 &&
2557 	    (udev->speed == USB_SPEED_SUPER ||
2558 	    udev->speed == USB_SPEED_HIGH);
2559 
2560 	if (is_hub)
2561 		temp |= XHCI_SCTX_0_HUB_SET(1);
2562 
2563 	xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2564 
2565 	temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2566 
2567 	if (is_hub) {
2568 		temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2569 		    sc->sc_hw.devs[index].nports);
2570 	}
2571 
2572 	switch (udev->speed) {
2573 	case USB_SPEED_SUPER:
2574 		switch (sc->sc_hw.devs[index].state) {
2575 		case XHCI_ST_ADDRESSED:
2576 		case XHCI_ST_CONFIGURED:
2577 			/* enable power save */
2578 			temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2579 			break;
2580 		default:
2581 			/* disable power save */
2582 			break;
2583 		}
2584 		break;
2585 	default:
2586 		break;
2587 	}
2588 
2589 	xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2590 
2591 	temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2592 
2593 	if (is_hub) {
2594 		temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2595 		    sc->sc_hw.devs[index].tt);
2596 	}
2597 
2598 	hubdev = udev->parent_hs_hub;
2599 
2600 	/* check if we should activate the transaction translator */
2601 	switch (udev->speed) {
2602 	case USB_SPEED_FULL:
2603 	case USB_SPEED_LOW:
2604 		if (hubdev != NULL) {
2605 			temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2606 			    hubdev->controller_slot_id);
2607 			temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2608 			    udev->hs_port_no);
2609 		}
2610 		break;
2611 	default:
2612 		break;
2613 	}
2614 
2615 	xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2616 
2617 	/*
2618 	 * These fields should be initialized to zero, according to
2619 	 * XHCI section 6.2.2 - slot context:
2620 	 */
2621 	temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2622 	    XHCI_SCTX_3_SLOT_STATE_SET(0);
2623 
2624 	xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2625 
2626 #ifdef USB_DEBUG
2627 	xhci_dump_device(sc, &pinp->ctx_slot);
2628 #endif
2629 	usb_pc_cpu_flush(pcinp);
2630 
2631 	return (0);		/* success */
2632 }
2633 
2634 static usb_error_t
2635 xhci_alloc_device_ext(struct usb_device *udev)
2636 {
2637 	struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2638 	struct usb_page_search buf_dev;
2639 	struct usb_page_search buf_ep;
2640 	struct xhci_trb *trb;
2641 	struct usb_page_cache *pc;
2642 	struct usb_page *pg;
2643 	uint64_t addr;
2644 	uint8_t index;
2645 	uint8_t i;
2646 
2647 	index = udev->controller_slot_id;
2648 
2649 	pc = &sc->sc_hw.devs[index].device_pc;
2650 	pg = &sc->sc_hw.devs[index].device_pg;
2651 
2652 	/* need to initialize the page cache */
2653 	pc->tag_parent = sc->sc_bus.dma_parent_tag;
2654 
2655 	if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2656 	    (2 * sizeof(struct xhci_dev_ctx)) :
2657 	    sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2658 		goto error;
2659 
2660 	usbd_get_page(pc, 0, &buf_dev);
2661 
2662 	pc = &sc->sc_hw.devs[index].input_pc;
2663 	pg = &sc->sc_hw.devs[index].input_pg;
2664 
2665 	/* need to initialize the page cache */
2666 	pc->tag_parent = sc->sc_bus.dma_parent_tag;
2667 
2668 	if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2669 	    (2 * sizeof(struct xhci_input_dev_ctx)) :
2670 	    sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2671 		goto error;
2672 	}
2673 
2674 	pc = &sc->sc_hw.devs[index].endpoint_pc;
2675 	pg = &sc->sc_hw.devs[index].endpoint_pg;
2676 
2677 	/* need to initialize the page cache */
2678 	pc->tag_parent = sc->sc_bus.dma_parent_tag;
2679 
2680 	if (usb_pc_alloc_mem(pc, pg,
2681 	    sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2682 		goto error;
2683 	}
2684 
2685 	/* initialise all endpoint LINK TRBs */
2686 
2687 	for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2688 
2689 		/* lookup endpoint TRB ring */
2690 		usbd_get_page(pc, (uintptr_t)&
2691 		    ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2692 
2693 		/* get TRB pointer */
2694 		trb = buf_ep.buffer;
2695 		trb += XHCI_MAX_TRANSFERS - 1;
2696 
2697 		/* get TRB start address */
2698 		addr = buf_ep.physaddr;
2699 
2700 		/* create LINK TRB */
2701 		trb->qwTrb0 = htole64(addr);
2702 		trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2703 		trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2704 		    XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2705 	}
2706 
2707 	usb_pc_cpu_flush(pc);
2708 
2709 	xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2710 
2711 	return (0);
2712 
2713 error:
2714 	xhci_free_device_ext(udev);
2715 
2716 	return (USB_ERR_NOMEM);
2717 }
2718 
2719 static void
2720 xhci_free_device_ext(struct usb_device *udev)
2721 {
2722 	struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2723 	uint8_t index;
2724 
2725 	index = udev->controller_slot_id;
2726 	xhci_set_slot_pointer(sc, index, 0);
2727 
2728 	usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2729 	usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2730 	usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2731 }
2732 
2733 static struct xhci_endpoint_ext *
2734 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2735 {
2736 	struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2737 	struct xhci_endpoint_ext *pepext;
2738 	struct usb_page_cache *pc;
2739 	struct usb_page_search buf_ep;
2740 	uint8_t epno;
2741 	uint8_t index;
2742 
2743 	epno = edesc->bEndpointAddress;
2744 	if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2745 		epno |= UE_DIR_IN;
2746 
2747 	epno = XHCI_EPNO2EPID(epno);
2748 
2749 	index = udev->controller_slot_id;
2750 
2751 	pc = &sc->sc_hw.devs[index].endpoint_pc;
2752 
2753 	usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->
2754 	    trb[epno][0], &buf_ep);
2755 
2756 	pepext = &sc->sc_hw.devs[index].endp[epno];
2757 	pepext->page_cache = pc;
2758 	pepext->trb = buf_ep.buffer;
2759 	pepext->physaddr = buf_ep.physaddr;
2760 
2761 	return (pepext);
2762 }
2763 
2764 static void
2765 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2766 {
2767 	struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2768 	uint8_t epno;
2769 	uint8_t index;
2770 
2771 	epno = xfer->endpointno;
2772 	if (xfer->flags_int.control_xfr)
2773 		epno |= UE_DIR_IN;
2774 
2775 	epno = XHCI_EPNO2EPID(epno);
2776 	index = xfer->xroot->udev->controller_slot_id;
2777 
2778 	if (xfer->xroot->udev->flags.self_suspended == 0) {
2779 		XWRITE4(sc, door, XHCI_DOORBELL(index),
2780 		    epno | XHCI_DB_SID_SET(xfer->stream_id));
2781 	}
2782 }
2783 
2784 static void
2785 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2786 {
2787 	struct xhci_endpoint_ext *pepext;
2788 
2789 	if (xfer->flags_int.bandwidth_reclaimed) {
2790 		xfer->flags_int.bandwidth_reclaimed = 0;
2791 
2792 		pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2793 		    xfer->endpoint->edesc);
2794 
2795 		pepext->trb_used[xfer->stream_id]--;
2796 
2797 		pepext->xfer[xfer->qh_pos] = NULL;
2798 
2799 		if (error && pepext->trb_running != 0) {
2800 			pepext->trb_halted = 1;
2801 			pepext->trb_running = 0;
2802 		}
2803 	}
2804 }
2805 
2806 static usb_error_t
2807 xhci_transfer_insert(struct usb_xfer *xfer)
2808 {
2809 	struct xhci_td *td_first;
2810 	struct xhci_td *td_last;
2811 	struct xhci_trb *trb_link;
2812 	struct xhci_endpoint_ext *pepext;
2813 	uint64_t addr;
2814 	usb_stream_t id;
2815 	uint8_t i;
2816 	uint8_t inext;
2817 	uint8_t trb_limit;
2818 
2819 	DPRINTFN(8, "\n");
2820 
2821 	id = xfer->stream_id;
2822 
2823 	/* check if already inserted */
2824 	if (xfer->flags_int.bandwidth_reclaimed) {
2825 		DPRINTFN(8, "Already in schedule\n");
2826 		return (0);
2827 	}
2828 
2829 	pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2830 	    xfer->endpoint->edesc);
2831 
2832 	td_first = xfer->td_transfer_first;
2833 	td_last = xfer->td_transfer_last;
2834 	addr = pepext->physaddr;
2835 
2836 	switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2837 	case UE_CONTROL:
2838 	case UE_INTERRUPT:
2839 		/* single buffered */
2840 		trb_limit = 1;
2841 		break;
2842 	default:
2843 		/* multi buffered */
2844 		trb_limit = (XHCI_MAX_TRANSFERS - 2);
2845 		break;
2846 	}
2847 
2848 	if (pepext->trb_used[id] >= trb_limit) {
2849 		DPRINTFN(8, "Too many TDs queued.\n");
2850 		return (USB_ERR_NOMEM);
2851 	}
2852 
2853 	/* check for stopped condition, after putting transfer on interrupt queue */
2854 	if (pepext->trb_running == 0) {
2855 		struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2856 
2857 		DPRINTFN(8, "Not running\n");
2858 
2859 		/* start configuration */
2860 		(void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2861 		    &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2862 		return (0);
2863 	}
2864 
2865 	pepext->trb_used[id]++;
2866 
2867 	/* get current TRB index */
2868 	i = pepext->trb_index[id];
2869 
2870 	/* get next TRB index */
2871 	inext = (i + 1);
2872 
2873 	/* the last entry of the ring is a hardcoded link TRB */
2874 	if (inext >= (XHCI_MAX_TRANSFERS - 1))
2875 		inext = 0;
2876 
2877 	/* store next TRB index, before stream ID offset is added */
2878 	pepext->trb_index[id] = inext;
2879 
2880 	/* offset for stream */
2881 	i += id * XHCI_MAX_TRANSFERS;
2882 	inext += id * XHCI_MAX_TRANSFERS;
2883 
2884 	/* compute terminating return address */
2885 	addr += (inext * sizeof(struct xhci_trb));
2886 
2887 	/* compute link TRB pointer */
2888 	trb_link = td_last->td_trb + td_last->ntrb;
2889 
2890 	/* update next pointer of last link TRB */
2891 	trb_link->qwTrb0 = htole64(addr);
2892 	trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2893 	trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2894 	    XHCI_TRB_3_CYCLE_BIT |
2895 	    XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2896 
2897 #ifdef USB_DEBUG
2898 	xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2899 #endif
2900 	usb_pc_cpu_flush(td_last->page_cache);
2901 
2902 	/* write ahead chain end marker */
2903 
2904 	pepext->trb[inext].qwTrb0 = 0;
2905 	pepext->trb[inext].dwTrb2 = 0;
2906 	pepext->trb[inext].dwTrb3 = 0;
2907 
2908 	/* update next pointer of link TRB */
2909 
2910 	pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2911 	pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2912 
2913 #ifdef USB_DEBUG
2914 	xhci_dump_trb(&pepext->trb[i]);
2915 #endif
2916 	usb_pc_cpu_flush(pepext->page_cache);
2917 
2918 	/* toggle cycle bit which activates the transfer chain */
2919 
2920 	pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2921 	    XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2922 
2923 	usb_pc_cpu_flush(pepext->page_cache);
2924 
2925 	DPRINTF("qh_pos = %u\n", i);
2926 
2927 	pepext->xfer[i] = xfer;
2928 
2929 	xfer->qh_pos = i;
2930 
2931 	xfer->flags_int.bandwidth_reclaimed = 1;
2932 
2933 	xhci_endpoint_doorbell(xfer);
2934 
2935 	return (0);
2936 }
2937 
2938 static void
2939 xhci_root_intr(struct xhci_softc *sc)
2940 {
2941 	uint16_t i;
2942 
2943 	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2944 
2945 	/* clear any old interrupt data */
2946 	memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2947 
2948 	for (i = 1; i <= sc->sc_noport; i++) {
2949 		/* pick out CHANGE bits from the status register */
2950 		if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2951 		    XHCI_PS_CSC | XHCI_PS_PEC |
2952 		    XHCI_PS_OCC | XHCI_PS_WRC |
2953 		    XHCI_PS_PRC | XHCI_PS_PLC |
2954 		    XHCI_PS_CEC)) {
2955 			sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2956 			DPRINTF("port %d changed\n", i);
2957 		}
2958 	}
2959 	uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2960 	    sizeof(sc->sc_hub_idata));
2961 }
2962 
2963 /*------------------------------------------------------------------------*
2964  *	xhci_device_done - XHCI done handler
2965  *
2966  * NOTE: This function can be called two times in a row on
2967  * the same USB transfer. From close and from interrupt.
2968  *------------------------------------------------------------------------*/
2969 static void
2970 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2971 {
2972 	DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2973 	    xfer, xfer->endpoint, error);
2974 
2975 	/* remove transfer from HW queue */
2976 	xhci_transfer_remove(xfer, error);
2977 
2978 	/* dequeue transfer and start next transfer */
2979 	usbd_transfer_done(xfer, error);
2980 }
2981 
2982 /*------------------------------------------------------------------------*
2983  * XHCI data transfer support (generic type)
2984  *------------------------------------------------------------------------*/
2985 static void
2986 xhci_device_generic_open(struct usb_xfer *xfer)
2987 {
2988 	if (xfer->flags_int.isochronous_xfr) {
2989 		switch (xfer->xroot->udev->speed) {
2990 		case USB_SPEED_FULL:
2991 			break;
2992 		default:
2993 			usb_hs_bandwidth_alloc(xfer);
2994 			break;
2995 		}
2996 	}
2997 }
2998 
2999 static void
3000 xhci_device_generic_close(struct usb_xfer *xfer)
3001 {
3002 	DPRINTF("\n");
3003 
3004 	xhci_device_done(xfer, USB_ERR_CANCELLED);
3005 
3006 	if (xfer->flags_int.isochronous_xfr) {
3007 		switch (xfer->xroot->udev->speed) {
3008 		case USB_SPEED_FULL:
3009 			break;
3010 		default:
3011 			usb_hs_bandwidth_free(xfer);
3012 			break;
3013 		}
3014 	}
3015 }
3016 
3017 static void
3018 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3019     usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3020 {
3021 	struct usb_xfer *xfer;
3022 
3023 	/* check if there is a current transfer */
3024 	xfer = ep->endpoint_q[stream_id].curr;
3025 	if (xfer == NULL)
3026 		return;
3027 
3028 	/*
3029 	 * Check if the current transfer is started and then pickup
3030 	 * the next one, if any. Else wait for next start event due to
3031 	 * block on failure feature.
3032 	 */
3033 	if (!xfer->flags_int.bandwidth_reclaimed)
3034 		return;
3035 
3036 	xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3037 	if (xfer == NULL) {
3038 		/*
3039 		 * In case of enter we have to consider that the
3040 		 * transfer is queued by the USB core after the enter
3041 		 * method is called.
3042 		 */
3043 		xfer = enter_xfer;
3044 
3045 		if (xfer == NULL)
3046 			return;
3047 	}
3048 
3049 	/* try to multi buffer */
3050 	xhci_transfer_insert(xfer);
3051 }
3052 
3053 static void
3054 xhci_device_generic_enter(struct usb_xfer *xfer)
3055 {
3056 	DPRINTF("\n");
3057 
3058 	/* setup TD's and QH */
3059 	xhci_setup_generic_chain(xfer);
3060 
3061 	xhci_device_generic_multi_enter(xfer->endpoint,
3062 	    xfer->stream_id, xfer);
3063 }
3064 
3065 static void
3066 xhci_device_generic_start(struct usb_xfer *xfer)
3067 {
3068 	DPRINTF("\n");
3069 
3070 	/* try to insert xfer on HW queue */
3071 	xhci_transfer_insert(xfer);
3072 
3073 	/* try to multi buffer */
3074 	xhci_device_generic_multi_enter(xfer->endpoint,
3075 	    xfer->stream_id, NULL);
3076 
3077 	/* add transfer last on interrupt queue */
3078 	usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3079 
3080 	/* start timeout, if any */
3081 	if (xfer->timeout != 0)
3082 		usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3083 }
3084 
3085 static const struct usb_pipe_methods xhci_device_generic_methods =
3086 {
3087 	.open = xhci_device_generic_open,
3088 	.close = xhci_device_generic_close,
3089 	.enter = xhci_device_generic_enter,
3090 	.start = xhci_device_generic_start,
3091 };
3092 
3093 /*------------------------------------------------------------------------*
3094  * xhci root HUB support
3095  *------------------------------------------------------------------------*
3096  * Simulate a hardware HUB by handling all the necessary requests.
3097  *------------------------------------------------------------------------*/
3098 
3099 #define	HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3100 
3101 static const
3102 struct usb_device_descriptor xhci_devd =
3103 {
3104 	.bLength = sizeof(xhci_devd),
3105 	.bDescriptorType = UDESC_DEVICE,	/* type */
3106 	HSETW(.bcdUSB, 0x0300),			/* USB version */
3107 	.bDeviceClass = UDCLASS_HUB,		/* class */
3108 	.bDeviceSubClass = UDSUBCLASS_HUB,	/* subclass */
3109 	.bDeviceProtocol = UDPROTO_SSHUB,	/* protocol */
3110 	.bMaxPacketSize = 9,			/* max packet size */
3111 	HSETW(.idVendor, 0x0000),		/* vendor */
3112 	HSETW(.idProduct, 0x0000),		/* product */
3113 	HSETW(.bcdDevice, 0x0100),		/* device version */
3114 	.iManufacturer = 1,
3115 	.iProduct = 2,
3116 	.iSerialNumber = 0,
3117 	.bNumConfigurations = 1,		/* # of configurations */
3118 };
3119 
3120 static const
3121 struct xhci_bos_desc xhci_bosd = {
3122 	.bosd = {
3123 		.bLength = sizeof(xhci_bosd.bosd),
3124 		.bDescriptorType = UDESC_BOS,
3125 		HSETW(.wTotalLength, sizeof(xhci_bosd)),
3126 		.bNumDeviceCaps = 3,
3127 	},
3128 	.usb2extd = {
3129 		.bLength = sizeof(xhci_bosd.usb2extd),
3130 		.bDescriptorType = 1,
3131 		.bDevCapabilityType = 2,
3132 		.bmAttributes[0] = 2,
3133 	},
3134 	.usbdcd = {
3135 		.bLength = sizeof(xhci_bosd.usbdcd),
3136 		.bDescriptorType = UDESC_DEVICE_CAPABILITY,
3137 		.bDevCapabilityType = 3,
3138 		.bmAttributes = 0, /* XXX */
3139 		HSETW(.wSpeedsSupported, 0x000C),
3140 		.bFunctionalitySupport = 8,
3141 		.bU1DevExitLat = 255,	/* dummy - not used */
3142 		.wU2DevExitLat = { 0x00, 0x08 },
3143 	},
3144 	.cidd = {
3145 		.bLength = sizeof(xhci_bosd.cidd),
3146 		.bDescriptorType = 1,
3147 		.bDevCapabilityType = 4,
3148 		.bReserved = 0,
3149 		.bContainerID = 0, /* XXX */
3150 	},
3151 };
3152 
3153 static const
3154 struct xhci_config_desc xhci_confd = {
3155 	.confd = {
3156 		.bLength = sizeof(xhci_confd.confd),
3157 		.bDescriptorType = UDESC_CONFIG,
3158 		.wTotalLength[0] = sizeof(xhci_confd),
3159 		.bNumInterface = 1,
3160 		.bConfigurationValue = 1,
3161 		.iConfiguration = 0,
3162 		.bmAttributes = UC_SELF_POWERED,
3163 		.bMaxPower = 0		/* max power */
3164 	},
3165 	.ifcd = {
3166 		.bLength = sizeof(xhci_confd.ifcd),
3167 		.bDescriptorType = UDESC_INTERFACE,
3168 		.bNumEndpoints = 1,
3169 		.bInterfaceClass = UICLASS_HUB,
3170 		.bInterfaceSubClass = UISUBCLASS_HUB,
3171 		.bInterfaceProtocol = 0,
3172 	},
3173 	.endpd = {
3174 		.bLength = sizeof(xhci_confd.endpd),
3175 		.bDescriptorType = UDESC_ENDPOINT,
3176 		.bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3177 		.bmAttributes = UE_INTERRUPT,
3178 		.wMaxPacketSize[0] = 2,		/* max 15 ports */
3179 		.bInterval = 255,
3180 	},
3181 	.endpcd = {
3182 		.bLength = sizeof(xhci_confd.endpcd),
3183 		.bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3184 		.bMaxBurst = 0,
3185 		.bmAttributes = 0,
3186 	},
3187 };
3188 
3189 static const
3190 struct usb_hub_ss_descriptor xhci_hubd = {
3191 	.bLength = sizeof(xhci_hubd),
3192 	.bDescriptorType = UDESC_SS_HUB,
3193 };
3194 
3195 static usb_error_t
3196 xhci_roothub_exec(struct usb_device *udev,
3197     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3198 {
3199 	struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3200 	const char *str_ptr;
3201 	const void *ptr;
3202 	uint32_t port;
3203 	uint32_t v;
3204 	uint16_t len;
3205 	uint16_t i;
3206 	uint16_t value;
3207 	uint16_t index;
3208 	uint8_t j;
3209 	usb_error_t err;
3210 
3211 	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3212 
3213 	/* buffer reset */
3214 	ptr = (const void *)&sc->sc_hub_desc;
3215 	len = 0;
3216 	err = 0;
3217 
3218 	value = UGETW(req->wValue);
3219 	index = UGETW(req->wIndex);
3220 
3221 	DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3222 	    "wValue=0x%04x wIndex=0x%04x\n",
3223 	    req->bmRequestType, req->bRequest,
3224 	    UGETW(req->wLength), value, index);
3225 
3226 #define	C(x,y) ((x) | ((y) << 8))
3227 	switch (C(req->bRequest, req->bmRequestType)) {
3228 	case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3229 	case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3230 	case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3231 		/*
3232 		 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3233 		 * for the integrated root hub.
3234 		 */
3235 		break;
3236 	case C(UR_GET_CONFIG, UT_READ_DEVICE):
3237 		len = 1;
3238 		sc->sc_hub_desc.temp[0] = sc->sc_conf;
3239 		break;
3240 	case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3241 		switch (value >> 8) {
3242 		case UDESC_DEVICE:
3243 			if ((value & 0xff) != 0) {
3244 				err = USB_ERR_IOERROR;
3245 				goto done;
3246 			}
3247 			len = sizeof(xhci_devd);
3248 			ptr = (const void *)&xhci_devd;
3249 			break;
3250 
3251 		case UDESC_BOS:
3252 			if ((value & 0xff) != 0) {
3253 				err = USB_ERR_IOERROR;
3254 				goto done;
3255 			}
3256 			len = sizeof(xhci_bosd);
3257 			ptr = (const void *)&xhci_bosd;
3258 			break;
3259 
3260 		case UDESC_CONFIG:
3261 			if ((value & 0xff) != 0) {
3262 				err = USB_ERR_IOERROR;
3263 				goto done;
3264 			}
3265 			len = sizeof(xhci_confd);
3266 			ptr = (const void *)&xhci_confd;
3267 			break;
3268 
3269 		case UDESC_STRING:
3270 			switch (value & 0xff) {
3271 			case 0:	/* Language table */
3272 				str_ptr = "\001";
3273 				break;
3274 
3275 			case 1:	/* Vendor */
3276 				str_ptr = sc->sc_vendor;
3277 				break;
3278 
3279 			case 2:	/* Product */
3280 				str_ptr = "XHCI root HUB";
3281 				break;
3282 
3283 			default:
3284 				str_ptr = "";
3285 				break;
3286 			}
3287 
3288 			len = usb_make_str_desc(
3289 			    sc->sc_hub_desc.temp,
3290 			    sizeof(sc->sc_hub_desc.temp),
3291 			    str_ptr);
3292 			break;
3293 
3294 		default:
3295 			err = USB_ERR_IOERROR;
3296 			goto done;
3297 		}
3298 		break;
3299 	case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3300 		len = 1;
3301 		sc->sc_hub_desc.temp[0] = 0;
3302 		break;
3303 	case C(UR_GET_STATUS, UT_READ_DEVICE):
3304 		len = 2;
3305 		USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3306 		break;
3307 	case C(UR_GET_STATUS, UT_READ_INTERFACE):
3308 	case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3309 		len = 2;
3310 		USETW(sc->sc_hub_desc.stat.wStatus, 0);
3311 		break;
3312 	case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3313 		if (value >= XHCI_MAX_DEVICES) {
3314 			err = USB_ERR_IOERROR;
3315 			goto done;
3316 		}
3317 		break;
3318 	case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3319 		if (value != 0 && value != 1) {
3320 			err = USB_ERR_IOERROR;
3321 			goto done;
3322 		}
3323 		sc->sc_conf = value;
3324 		break;
3325 	case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3326 		break;
3327 	case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3328 	case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3329 	case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3330 		err = USB_ERR_IOERROR;
3331 		goto done;
3332 	case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3333 		break;
3334 	case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3335 		break;
3336 		/* Hub requests */
3337 	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3338 		break;
3339 	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3340 		DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3341 
3342 		if ((index < 1) ||
3343 		    (index > sc->sc_noport)) {
3344 			err = USB_ERR_IOERROR;
3345 			goto done;
3346 		}
3347 		port = XHCI_PORTSC(index);
3348 
3349 		v = XREAD4(sc, oper, port);
3350 		i = XHCI_PS_PLS_GET(v);
3351 		v &= ~XHCI_PS_CLEAR;
3352 
3353 		switch (value) {
3354 		case UHF_C_BH_PORT_RESET:
3355 			XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3356 			break;
3357 		case UHF_C_PORT_CONFIG_ERROR:
3358 			XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3359 			break;
3360 		case UHF_C_PORT_SUSPEND:
3361 		case UHF_C_PORT_LINK_STATE:
3362 			XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3363 			break;
3364 		case UHF_C_PORT_CONNECTION:
3365 			XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3366 			break;
3367 		case UHF_C_PORT_ENABLE:
3368 			XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3369 			break;
3370 		case UHF_C_PORT_OVER_CURRENT:
3371 			XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3372 			break;
3373 		case UHF_C_PORT_RESET:
3374 			XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3375 			break;
3376 		case UHF_PORT_ENABLE:
3377 			XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3378 			break;
3379 		case UHF_PORT_POWER:
3380 			XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3381 			break;
3382 		case UHF_PORT_INDICATOR:
3383 			XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3384 			break;
3385 		case UHF_PORT_SUSPEND:
3386 
3387 			/* U3 -> U15 */
3388 			if (i == 3) {
3389 				XWRITE4(sc, oper, port, v |
3390 				    XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3391 			}
3392 
3393 			/* wait 20ms for resume sequence to complete */
3394 			usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3395 
3396 			/* U0 */
3397 			XWRITE4(sc, oper, port, v |
3398 			    XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3399 			break;
3400 		default:
3401 			err = USB_ERR_IOERROR;
3402 			goto done;
3403 		}
3404 		break;
3405 
3406 	case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3407 		if ((value & 0xff) != 0) {
3408 			err = USB_ERR_IOERROR;
3409 			goto done;
3410 		}
3411 
3412 		v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3413 
3414 		sc->sc_hub_desc.hubd = xhci_hubd;
3415 
3416 		sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3417 
3418 		if (XHCI_HCS0_PPC(v))
3419 			i = UHD_PWR_INDIVIDUAL;
3420 		else
3421 			i = UHD_PWR_GANGED;
3422 
3423 		if (XHCI_HCS0_PIND(v))
3424 			i |= UHD_PORT_IND;
3425 
3426 		i |= UHD_OC_INDIVIDUAL;
3427 
3428 		USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3429 
3430 		/* see XHCI section 5.4.9: */
3431 		sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3432 
3433 		for (j = 1; j <= sc->sc_noport; j++) {
3434 
3435 			v = XREAD4(sc, oper, XHCI_PORTSC(j));
3436 			if (v & XHCI_PS_DR) {
3437 				sc->sc_hub_desc.hubd.
3438 				    DeviceRemovable[j / 8] |= 1U << (j % 8);
3439 			}
3440 		}
3441 		len = sc->sc_hub_desc.hubd.bLength;
3442 		break;
3443 
3444 	case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3445 		len = 16;
3446 		memset(sc->sc_hub_desc.temp, 0, 16);
3447 		break;
3448 
3449 	case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3450 		DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3451 
3452 		if ((index < 1) ||
3453 		    (index > sc->sc_noport)) {
3454 			err = USB_ERR_IOERROR;
3455 			goto done;
3456 		}
3457 
3458 		v = XREAD4(sc, oper, XHCI_PORTSC(index));
3459 
3460 		DPRINTFN(9, "port status=0x%08x\n", v);
3461 
3462 		i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3463 
3464 		switch (XHCI_PS_SPEED_GET(v)) {
3465 		case 3:
3466 			i |= UPS_HIGH_SPEED;
3467 			break;
3468 		case 2:
3469 			i |= UPS_LOW_SPEED;
3470 			break;
3471 		case 1:
3472 			/* FULL speed */
3473 			break;
3474 		default:
3475 			i |= UPS_OTHER_SPEED;
3476 			break;
3477 		}
3478 
3479 		if (v & XHCI_PS_CCS)
3480 			i |= UPS_CURRENT_CONNECT_STATUS;
3481 		if (v & XHCI_PS_PED)
3482 			i |= UPS_PORT_ENABLED;
3483 		if (v & XHCI_PS_OCA)
3484 			i |= UPS_OVERCURRENT_INDICATOR;
3485 		if (v & XHCI_PS_PR)
3486 			i |= UPS_RESET;
3487 		if (v & XHCI_PS_PP) {
3488 			/*
3489 			 * The USB 3.0 RH is using the
3490 			 * USB 2.0's power bit
3491 			 */
3492 			i |= UPS_PORT_POWER;
3493 		}
3494 		USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3495 
3496 		i = 0;
3497 		if (v & XHCI_PS_CSC)
3498 			i |= UPS_C_CONNECT_STATUS;
3499 		if (v & XHCI_PS_PEC)
3500 			i |= UPS_C_PORT_ENABLED;
3501 		if (v & XHCI_PS_OCC)
3502 			i |= UPS_C_OVERCURRENT_INDICATOR;
3503 		if (v & XHCI_PS_WRC)
3504 			i |= UPS_C_BH_PORT_RESET;
3505 		if (v & XHCI_PS_PRC)
3506 			i |= UPS_C_PORT_RESET;
3507 		if (v & XHCI_PS_PLC)
3508 			i |= UPS_C_PORT_LINK_STATE;
3509 		if (v & XHCI_PS_CEC)
3510 			i |= UPS_C_PORT_CONFIG_ERROR;
3511 
3512 		USETW(sc->sc_hub_desc.ps.wPortChange, i);
3513 		len = sizeof(sc->sc_hub_desc.ps);
3514 		break;
3515 
3516 	case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3517 		err = USB_ERR_IOERROR;
3518 		goto done;
3519 
3520 	case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3521 		break;
3522 
3523 	case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3524 
3525 		i = index >> 8;
3526 		index &= 0x00FF;
3527 
3528 		if ((index < 1) ||
3529 		    (index > sc->sc_noport)) {
3530 			err = USB_ERR_IOERROR;
3531 			goto done;
3532 		}
3533 
3534 		port = XHCI_PORTSC(index);
3535 		v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3536 
3537 		switch (value) {
3538 		case UHF_PORT_U1_TIMEOUT:
3539 			if (XHCI_PS_SPEED_GET(v) != 4) {
3540 				err = USB_ERR_IOERROR;
3541 				goto done;
3542 			}
3543 			port = XHCI_PORTPMSC(index);
3544 			v = XREAD4(sc, oper, port);
3545 			v &= ~XHCI_PM3_U1TO_SET(0xFF);
3546 			v |= XHCI_PM3_U1TO_SET(i);
3547 			XWRITE4(sc, oper, port, v);
3548 			break;
3549 		case UHF_PORT_U2_TIMEOUT:
3550 			if (XHCI_PS_SPEED_GET(v) != 4) {
3551 				err = USB_ERR_IOERROR;
3552 				goto done;
3553 			}
3554 			port = XHCI_PORTPMSC(index);
3555 			v = XREAD4(sc, oper, port);
3556 			v &= ~XHCI_PM3_U2TO_SET(0xFF);
3557 			v |= XHCI_PM3_U2TO_SET(i);
3558 			XWRITE4(sc, oper, port, v);
3559 			break;
3560 		case UHF_BH_PORT_RESET:
3561 			XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3562 			break;
3563 		case UHF_PORT_LINK_STATE:
3564 			XWRITE4(sc, oper, port, v |
3565 			    XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3566 			/* 4ms settle time */
3567 			usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3568 			break;
3569 		case UHF_PORT_ENABLE:
3570 			DPRINTFN(3, "set port enable %d\n", index);
3571 			break;
3572 		case UHF_PORT_SUSPEND:
3573 			DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3574 			j = XHCI_PS_SPEED_GET(v);
3575 			if ((j < 1) || (j > 3)) {
3576 				/* non-supported speed */
3577 				err = USB_ERR_IOERROR;
3578 				goto done;
3579 			}
3580 			XWRITE4(sc, oper, port, v |
3581 			    XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3582 			break;
3583 		case UHF_PORT_RESET:
3584 			DPRINTFN(6, "reset port %d\n", index);
3585 			XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3586 			break;
3587 		case UHF_PORT_POWER:
3588 			DPRINTFN(3, "set port power %d\n", index);
3589 			XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3590 			break;
3591 		case UHF_PORT_TEST:
3592 			DPRINTFN(3, "set port test %d\n", index);
3593 			break;
3594 		case UHF_PORT_INDICATOR:
3595 			DPRINTFN(3, "set port indicator %d\n", index);
3596 
3597 			v &= ~XHCI_PS_PIC_SET(3);
3598 			v |= XHCI_PS_PIC_SET(1);
3599 
3600 			XWRITE4(sc, oper, port, v);
3601 			break;
3602 		default:
3603 			err = USB_ERR_IOERROR;
3604 			goto done;
3605 		}
3606 		break;
3607 
3608 	case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3609 	case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3610 	case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3611 	case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3612 		break;
3613 	default:
3614 		err = USB_ERR_IOERROR;
3615 		goto done;
3616 	}
3617 done:
3618 	*plength = len;
3619 	*pptr = ptr;
3620 	return (err);
3621 }
3622 
3623 static void
3624 xhci_xfer_setup(struct usb_setup_params *parm)
3625 {
3626 	struct usb_page_search page_info;
3627 	struct usb_page_cache *pc;
3628 	struct xhci_softc *sc;
3629 	struct usb_xfer *xfer;
3630 	void *last_obj;
3631 	uint32_t ntd;
3632 	uint32_t n;
3633 
3634 	sc = XHCI_BUS2SC(parm->udev->bus);
3635 	xfer = parm->curr_xfer;
3636 
3637 	/*
3638 	 * The proof for the "ntd" formula is illustrated like this:
3639 	 *
3640 	 * +------------------------------------+
3641 	 * |                                    |
3642 	 * |         |remainder ->              |
3643 	 * |   +-----+---+                      |
3644 	 * |   | xxx | x | frm 0                |
3645 	 * |   +-----+---++                     |
3646 	 * |   | xxx | xx | frm 1               |
3647 	 * |   +-----+----+                     |
3648 	 * |            ...                     |
3649 	 * +------------------------------------+
3650 	 *
3651 	 * "xxx" means a completely full USB transfer descriptor
3652 	 *
3653 	 * "x" and "xx" means a short USB packet
3654 	 *
3655 	 * For the remainder of an USB transfer modulo
3656 	 * "max_data_length" we need two USB transfer descriptors.
3657 	 * One to transfer the remaining data and one to finalise with
3658 	 * a zero length packet in case the "force_short_xfer" flag is
3659 	 * set. We only need two USB transfer descriptors in the case
3660 	 * where the transfer length of the first one is a factor of
3661 	 * "max_frame_size". The rest of the needed USB transfer
3662 	 * descriptors is given by the buffer size divided by the
3663 	 * maximum data payload.
3664 	 */
3665 	parm->hc_max_packet_size = 0x400;
3666 	parm->hc_max_packet_count = 16 * 3;
3667 	parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3668 
3669 	xfer->flags_int.bdma_enable = 1;
3670 
3671 	usbd_transfer_setup_sub(parm);
3672 
3673 	if (xfer->flags_int.isochronous_xfr) {
3674 		ntd = ((1 * xfer->nframes)
3675 		    + (xfer->max_data_length / xfer->max_hc_frame_size));
3676 	} else if (xfer->flags_int.control_xfr) {
3677 		ntd = ((2 * xfer->nframes) + 1	/* STATUS */
3678 		    + (xfer->max_data_length / xfer->max_hc_frame_size));
3679 	} else {
3680 		ntd = ((2 * xfer->nframes)
3681 		    + (xfer->max_data_length / xfer->max_hc_frame_size));
3682 	}
3683 
3684 alloc_dma_set:
3685 
3686 	if (parm->err)
3687 		return;
3688 
3689 	/*
3690 	 * Allocate queue heads and transfer descriptors
3691 	 */
3692 	last_obj = NULL;
3693 
3694 	if (usbd_transfer_setup_sub_malloc(
3695 	    parm, &pc, sizeof(struct xhci_td),
3696 	    XHCI_TD_ALIGN, ntd)) {
3697 		parm->err = USB_ERR_NOMEM;
3698 		return;
3699 	}
3700 	if (parm->buf) {
3701 		for (n = 0; n != ntd; n++) {
3702 			struct xhci_td *td;
3703 
3704 			usbd_get_page(pc + n, 0, &page_info);
3705 
3706 			td = page_info.buffer;
3707 
3708 			/* init TD */
3709 			td->td_self = page_info.physaddr;
3710 			td->obj_next = last_obj;
3711 			td->page_cache = pc + n;
3712 
3713 			last_obj = td;
3714 
3715 			usb_pc_cpu_flush(pc + n);
3716 		}
3717 	}
3718 	xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3719 
3720 	if (!xfer->flags_int.curr_dma_set) {
3721 		xfer->flags_int.curr_dma_set = 1;
3722 		goto alloc_dma_set;
3723 	}
3724 }
3725 
3726 static usb_error_t
3727 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3728 {
3729 	struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3730 	struct usb_page_search buf_inp;
3731 	struct usb_device *udev;
3732 	struct xhci_endpoint_ext *pepext;
3733 	struct usb_endpoint_descriptor *edesc;
3734 	struct usb_page_cache *pcinp;
3735 	usb_error_t err;
3736 	usb_stream_t stream_id;
3737 	uint8_t index;
3738 	uint8_t epno;
3739 
3740 	pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3741 	    xfer->endpoint->edesc);
3742 
3743 	udev = xfer->xroot->udev;
3744 	index = udev->controller_slot_id;
3745 
3746 	pcinp = &sc->sc_hw.devs[index].input_pc;
3747 
3748 	usbd_get_page(pcinp, 0, &buf_inp);
3749 
3750 	edesc = xfer->endpoint->edesc;
3751 
3752 	epno = edesc->bEndpointAddress;
3753 	stream_id = xfer->stream_id;
3754 
3755 	if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3756 		epno |= UE_DIR_IN;
3757 
3758 	epno = XHCI_EPNO2EPID(epno);
3759 
3760  	if (epno == 0)
3761 		return (USB_ERR_NO_PIPE);		/* invalid */
3762 
3763 	XHCI_CMD_LOCK(sc);
3764 
3765 	/* configure endpoint */
3766 
3767 	err = xhci_configure_endpoint_by_xfer(xfer);
3768 
3769 	if (err != 0) {
3770 		XHCI_CMD_UNLOCK(sc);
3771 		return (err);
3772 	}
3773 
3774 	/*
3775 	 * Get the endpoint into the stopped state according to the
3776 	 * endpoint context state diagram in the XHCI specification:
3777 	 */
3778 
3779 	err = xhci_cmd_stop_ep(sc, 0, epno, index);
3780 
3781 	if (err != 0)
3782 		DPRINTF("Could not stop endpoint %u\n", epno);
3783 
3784 	err = xhci_cmd_reset_ep(sc, 0, epno, index);
3785 
3786 	if (err != 0)
3787 		DPRINTF("Could not reset endpoint %u\n", epno);
3788 
3789 	err = xhci_cmd_set_tr_dequeue_ptr(sc,
3790 	    (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3791 	    XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3792 	    stream_id, epno, index);
3793 
3794 	if (err != 0)
3795 		DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3796 
3797 	/*
3798 	 * Get the endpoint into the running state according to the
3799 	 * endpoint context state diagram in the XHCI specification:
3800 	 */
3801 
3802 	xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3803 
3804 	err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3805 
3806 	if (err != 0)
3807 		DPRINTF("Could not configure endpoint %u\n", epno);
3808 
3809 	err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3810 
3811 	if (err != 0)
3812 		DPRINTF("Could not configure endpoint %u\n", epno);
3813 
3814 	XHCI_CMD_UNLOCK(sc);
3815 
3816 	return (0);
3817 }
3818 
3819 static void
3820 xhci_xfer_unsetup(struct usb_xfer *xfer)
3821 {
3822 	return;
3823 }
3824 
3825 static void
3826 xhci_start_dma_delay(struct usb_xfer *xfer)
3827 {
3828 	struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3829 
3830 	/* put transfer on interrupt queue (again) */
3831 	usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3832 
3833 	(void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3834 	    &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3835 }
3836 
3837 static void
3838 xhci_configure_msg(struct usb_proc_msg *pm)
3839 {
3840 	struct xhci_softc *sc;
3841 	struct xhci_endpoint_ext *pepext;
3842 	struct usb_xfer *xfer;
3843 
3844 	sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3845 
3846 restart:
3847 	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3848 
3849 		pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3850 		    xfer->endpoint->edesc);
3851 
3852 		if ((pepext->trb_halted != 0) ||
3853 		    (pepext->trb_running == 0)) {
3854 
3855 			uint16_t i;
3856 
3857 			/* clear halted and running */
3858 			pepext->trb_halted = 0;
3859 			pepext->trb_running = 0;
3860 
3861 			/* nuke remaining buffered transfers */
3862 
3863 			for (i = 0; i != (XHCI_MAX_TRANSFERS *
3864 			    XHCI_MAX_STREAMS); i++) {
3865 				/*
3866 				 * NOTE: We need to use the timeout
3867 				 * error code here else existing
3868 				 * isochronous clients can get
3869 				 * confused:
3870 				 */
3871 				if (pepext->xfer[i] != NULL) {
3872 					xhci_device_done(pepext->xfer[i],
3873 					    USB_ERR_TIMEOUT);
3874 				}
3875 			}
3876 
3877 			/*
3878 			 * NOTE: The USB transfer cannot vanish in
3879 			 * this state!
3880 			 */
3881 
3882 			USB_BUS_UNLOCK(&sc->sc_bus);
3883 
3884 			xhci_configure_reset_endpoint(xfer);
3885 
3886 			USB_BUS_LOCK(&sc->sc_bus);
3887 
3888 			/* check if halted is still cleared */
3889 			if (pepext->trb_halted == 0) {
3890 				pepext->trb_running = 1;
3891 				memset(pepext->trb_index, 0,
3892 				    sizeof(pepext->trb_index));
3893 			}
3894 			goto restart;
3895 		}
3896 
3897 		if (xfer->flags_int.did_dma_delay) {
3898 
3899 			/* remove transfer from interrupt queue (again) */
3900 			usbd_transfer_dequeue(xfer);
3901 
3902 			/* we are finally done */
3903 			usb_dma_delay_done_cb(xfer);
3904 
3905 			/* queue changed - restart */
3906 			goto restart;
3907 		}
3908 	}
3909 
3910 	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3911 
3912 		/* try to insert xfer on HW queue */
3913 		xhci_transfer_insert(xfer);
3914 
3915 		/* try to multi buffer */
3916 		xhci_device_generic_multi_enter(xfer->endpoint,
3917 		    xfer->stream_id, NULL);
3918 	}
3919 }
3920 
3921 static void
3922 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3923     struct usb_endpoint *ep)
3924 {
3925 	struct xhci_endpoint_ext *pepext;
3926 
3927 	DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3928 	    ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3929 
3930 	if (udev->parent_hub == NULL) {
3931 		/* root HUB has special endpoint handling */
3932 		return;
3933 	}
3934 
3935 	ep->methods = &xhci_device_generic_methods;
3936 
3937 	pepext = xhci_get_endpoint_ext(udev, edesc);
3938 
3939 	USB_BUS_LOCK(udev->bus);
3940 	pepext->trb_halted = 1;
3941 	pepext->trb_running = 0;
3942 	USB_BUS_UNLOCK(udev->bus);
3943 }
3944 
3945 static void
3946 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3947 {
3948 
3949 }
3950 
3951 static void
3952 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3953 {
3954 	struct xhci_endpoint_ext *pepext;
3955 
3956 	DPRINTF("\n");
3957 
3958 	if (udev->flags.usb_mode != USB_MODE_HOST) {
3959 		/* not supported */
3960 		return;
3961 	}
3962 	if (udev->parent_hub == NULL) {
3963 		/* root HUB has special endpoint handling */
3964 		return;
3965 	}
3966 
3967 	pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3968 
3969 	USB_BUS_LOCK(udev->bus);
3970 	pepext->trb_halted = 1;
3971 	pepext->trb_running = 0;
3972 	USB_BUS_UNLOCK(udev->bus);
3973 }
3974 
3975 static usb_error_t
3976 xhci_device_init(struct usb_device *udev)
3977 {
3978 	struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3979 	usb_error_t err;
3980 	uint8_t temp;
3981 
3982 	/* no init for root HUB */
3983 	if (udev->parent_hub == NULL)
3984 		return (0);
3985 
3986 	XHCI_CMD_LOCK(sc);
3987 
3988 	/* set invalid default */
3989 
3990 	udev->controller_slot_id = sc->sc_noslot + 1;
3991 
3992 	/* try to get a new slot ID from the XHCI */
3993 
3994 	err = xhci_cmd_enable_slot(sc, &temp);
3995 
3996 	if (err) {
3997 		XHCI_CMD_UNLOCK(sc);
3998 		return (err);
3999 	}
4000 
4001 	if (temp > sc->sc_noslot) {
4002 		XHCI_CMD_UNLOCK(sc);
4003 		return (USB_ERR_BAD_ADDRESS);
4004 	}
4005 
4006 	if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4007 		DPRINTF("slot %u already allocated.\n", temp);
4008 		XHCI_CMD_UNLOCK(sc);
4009 		return (USB_ERR_BAD_ADDRESS);
4010 	}
4011 
4012 	/* store slot ID for later reference */
4013 
4014 	udev->controller_slot_id = temp;
4015 
4016 	/* reset data structure */
4017 
4018 	memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4019 
4020 	/* set mark slot allocated */
4021 
4022 	sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4023 
4024 	err = xhci_alloc_device_ext(udev);
4025 
4026 	XHCI_CMD_UNLOCK(sc);
4027 
4028 	/* get device into default state */
4029 
4030 	if (err == 0)
4031 		err = xhci_set_address(udev, NULL, 0);
4032 
4033 	return (err);
4034 }
4035 
4036 static void
4037 xhci_device_uninit(struct usb_device *udev)
4038 {
4039 	struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4040 	uint8_t index;
4041 
4042 	/* no init for root HUB */
4043 	if (udev->parent_hub == NULL)
4044 		return;
4045 
4046 	XHCI_CMD_LOCK(sc);
4047 
4048 	index = udev->controller_slot_id;
4049 
4050 	if (index <= sc->sc_noslot) {
4051 		xhci_cmd_disable_slot(sc, index);
4052 		sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4053 
4054 		/* free device extension */
4055 		xhci_free_device_ext(udev);
4056 	}
4057 
4058 	XHCI_CMD_UNLOCK(sc);
4059 }
4060 
4061 static void
4062 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4063 {
4064 	/*
4065 	 * Wait until the hardware has finished any possible use of
4066 	 * the transfer descriptor(s)
4067 	 */
4068 	*pus = 2048;			/* microseconds */
4069 }
4070 
4071 static void
4072 xhci_device_resume(struct usb_device *udev)
4073 {
4074 	struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4075 	uint8_t index;
4076 	uint8_t n;
4077 	uint8_t p;
4078 
4079 	DPRINTF("\n");
4080 
4081 	/* check for root HUB */
4082 	if (udev->parent_hub == NULL)
4083 		return;
4084 
4085 	index = udev->controller_slot_id;
4086 
4087 	XHCI_CMD_LOCK(sc);
4088 
4089 	/* blindly resume all endpoints */
4090 
4091 	USB_BUS_LOCK(udev->bus);
4092 
4093 	for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4094 		for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4095 			XWRITE4(sc, door, XHCI_DOORBELL(index),
4096 			    n | XHCI_DB_SID_SET(p));
4097 		}
4098 	}
4099 
4100 	USB_BUS_UNLOCK(udev->bus);
4101 
4102 	XHCI_CMD_UNLOCK(sc);
4103 }
4104 
4105 static void
4106 xhci_device_suspend(struct usb_device *udev)
4107 {
4108 	struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4109 	uint8_t index;
4110 	uint8_t n;
4111 	usb_error_t err;
4112 
4113 	DPRINTF("\n");
4114 
4115 	/* check for root HUB */
4116 	if (udev->parent_hub == NULL)
4117 		return;
4118 
4119 	index = udev->controller_slot_id;
4120 
4121 	XHCI_CMD_LOCK(sc);
4122 
4123 	/* blindly suspend all endpoints */
4124 
4125 	for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4126 		err = xhci_cmd_stop_ep(sc, 1, n, index);
4127 		if (err != 0) {
4128 			DPRINTF("Failed to suspend endpoint "
4129 			    "%u on slot %u (ignored).\n", n, index);
4130 		}
4131 	}
4132 
4133 	XHCI_CMD_UNLOCK(sc);
4134 }
4135 
4136 static void
4137 xhci_set_hw_power(struct usb_bus *bus)
4138 {
4139 	DPRINTF("\n");
4140 }
4141 
4142 static void
4143 xhci_device_state_change(struct usb_device *udev)
4144 {
4145 	struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4146 	struct usb_page_search buf_inp;
4147 	usb_error_t err;
4148 	uint8_t index;
4149 
4150 	/* check for root HUB */
4151 	if (udev->parent_hub == NULL)
4152 		return;
4153 
4154 	index = udev->controller_slot_id;
4155 
4156 	DPRINTF("\n");
4157 
4158 	if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4159 		err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4160 		    &sc->sc_hw.devs[index].tt);
4161 		if (err != 0)
4162 			sc->sc_hw.devs[index].nports = 0;
4163 	}
4164 
4165 	XHCI_CMD_LOCK(sc);
4166 
4167 	switch (usb_get_device_state(udev)) {
4168 	case USB_STATE_POWERED:
4169 		if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4170 			break;
4171 
4172 		/* set default state */
4173 		sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4174 
4175 		/* reset number of contexts */
4176 		sc->sc_hw.devs[index].context_num = 0;
4177 
4178 		err = xhci_cmd_reset_dev(sc, index);
4179 
4180 		if (err != 0) {
4181 			DPRINTF("Device reset failed "
4182 			    "for slot %u.\n", index);
4183 		}
4184 		break;
4185 
4186 	case USB_STATE_ADDRESSED:
4187 		if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4188 			break;
4189 
4190 		sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4191 
4192 		err = xhci_cmd_configure_ep(sc, 0, 1, index);
4193 
4194 		if (err) {
4195 			DPRINTF("Failed to deconfigure "
4196 			    "slot %u.\n", index);
4197 		}
4198 		break;
4199 
4200 	case USB_STATE_CONFIGURED:
4201 		if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4202 			break;
4203 
4204 		/* set configured state */
4205 		sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4206 
4207 		/* reset number of contexts */
4208 		sc->sc_hw.devs[index].context_num = 0;
4209 
4210 		usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4211 
4212 		xhci_configure_mask(udev, 3, 0);
4213 
4214 		err = xhci_configure_device(udev);
4215 		if (err != 0) {
4216 			DPRINTF("Could not configure device "
4217 			    "at slot %u.\n", index);
4218 		}
4219 
4220 		err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4221 		if (err != 0) {
4222 			DPRINTF("Could not evaluate device "
4223 			    "context at slot %u.\n", index);
4224 		}
4225 		break;
4226 
4227 	default:
4228 		break;
4229 	}
4230 	XHCI_CMD_UNLOCK(sc);
4231 }
4232 
4233 static usb_error_t
4234 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4235     uint8_t ep_mode)
4236 {
4237 	switch (ep_mode) {
4238 	case USB_EP_MODE_DEFAULT:
4239 		return (0);
4240 	case USB_EP_MODE_STREAMS:
4241 		if (xhcistreams == 0 ||
4242 		    (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4243 		    udev->speed != USB_SPEED_SUPER)
4244 			return (USB_ERR_INVAL);
4245 		return (0);
4246 	default:
4247 		return (USB_ERR_INVAL);
4248 	}
4249 }
4250 
4251 static const struct usb_bus_methods xhci_bus_methods = {
4252 	.endpoint_init = xhci_ep_init,
4253 	.endpoint_uninit = xhci_ep_uninit,
4254 	.xfer_setup = xhci_xfer_setup,
4255 	.xfer_unsetup = xhci_xfer_unsetup,
4256 	.get_dma_delay = xhci_get_dma_delay,
4257 	.device_init = xhci_device_init,
4258 	.device_uninit = xhci_device_uninit,
4259 	.device_resume = xhci_device_resume,
4260 	.device_suspend = xhci_device_suspend,
4261 	.set_hw_power = xhci_set_hw_power,
4262 	.roothub_exec = xhci_roothub_exec,
4263 	.xfer_poll = xhci_do_poll,
4264 	.start_dma_delay = xhci_start_dma_delay,
4265 	.set_address = xhci_set_address,
4266 	.clear_stall = xhci_ep_clear_stall,
4267 	.device_state_change = xhci_device_state_change,
4268 	.set_hw_power_sleep = xhci_set_hw_power_sleep,
4269 	.set_endpoint_mode = xhci_set_endpoint_mode,
4270 };
4271