1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 28 * 29 * The XHCI 1.0 spec can be found at 30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 31 * and the USB 3.0 spec at 32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 33 */ 34 35 /* 36 * A few words about the design implementation: This driver emulates 37 * the concept about TDs which is found in EHCI specification. This 38 * way we avoid too much diveration among USB drivers. 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/stdint.h> 45 #include <sys/stddef.h> 46 #include <sys/param.h> 47 #include <sys/queue.h> 48 #include <sys/types.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/bus.h> 52 #include <sys/module.h> 53 #include <sys/lock.h> 54 #include <sys/mutex.h> 55 #include <sys/condvar.h> 56 #include <sys/sysctl.h> 57 #include <sys/sx.h> 58 #include <sys/unistd.h> 59 #include <sys/callout.h> 60 #include <sys/malloc.h> 61 #include <sys/priv.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 66 #define USB_DEBUG_VAR xhcidebug 67 68 #include <dev/usb/usb_core.h> 69 #include <dev/usb/usb_debug.h> 70 #include <dev/usb/usb_busdma.h> 71 #include <dev/usb/usb_process.h> 72 #include <dev/usb/usb_transfer.h> 73 #include <dev/usb/usb_device.h> 74 #include <dev/usb/usb_hub.h> 75 #include <dev/usb/usb_util.h> 76 77 #include <dev/usb/usb_controller.h> 78 #include <dev/usb/usb_bus.h> 79 #include <dev/usb/controller/xhci.h> 80 #include <dev/usb/controller/xhcireg.h> 81 82 #define XHCI_BUS2SC(bus) \ 83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 85 86 #ifdef USB_DEBUG 87 static int xhcidebug = 0; 88 89 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 90 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW, 91 &xhcidebug, 0, "Debug level"); 92 93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 94 95 #endif 96 97 #define XHCI_INTR_ENDPT 1 98 99 struct xhci_std_temp { 100 struct xhci_softc *sc; 101 struct usb_page_cache *pc; 102 struct xhci_td *td; 103 struct xhci_td *td_next; 104 uint32_t len; 105 uint32_t offset; 106 uint32_t max_packet_size; 107 uint32_t average; 108 uint16_t isoc_delta; 109 uint16_t isoc_frame; 110 uint8_t shortpkt; 111 uint8_t multishort; 112 uint8_t last_frame; 113 uint8_t trb_type; 114 uint8_t direction; 115 uint8_t tbc; 116 uint8_t tlbpc; 117 uint8_t step_td; 118 uint8_t do_isoc_sync; 119 }; 120 121 static void xhci_do_poll(struct usb_bus *); 122 static void xhci_device_done(struct usb_xfer *, usb_error_t); 123 static void xhci_root_intr(struct xhci_softc *); 124 static void xhci_free_device_ext(struct usb_device *); 125 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 126 struct usb_endpoint_descriptor *); 127 static usb_proc_callback_t xhci_configure_msg; 128 static usb_error_t xhci_configure_device(struct usb_device *); 129 static usb_error_t xhci_configure_endpoint(struct usb_device *, 130 struct usb_endpoint_descriptor *, uint64_t, uint16_t, 131 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t); 132 static usb_error_t xhci_configure_mask(struct usb_device *, 133 uint32_t, uint8_t); 134 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 135 uint64_t, uint8_t); 136 static void xhci_endpoint_doorbell(struct usb_xfer *); 137 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 138 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 139 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 140 #ifdef USB_DEBUG 141 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 142 #endif 143 144 extern struct usb_bus_methods xhci_bus_methods; 145 146 #ifdef USB_DEBUG 147 static void 148 xhci_dump_trb(struct xhci_trb *trb) 149 { 150 DPRINTFN(5, "trb = %p\n", trb); 151 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 152 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 153 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 154 } 155 156 static void 157 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 158 { 159 DPRINTFN(5, "pep = %p\n", pep); 160 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 161 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 162 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 163 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 164 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 165 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 166 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 167 } 168 169 static void 170 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 171 { 172 DPRINTFN(5, "psl = %p\n", psl); 173 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 174 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 175 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 176 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 177 } 178 #endif 179 180 static void 181 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 182 { 183 struct xhci_softc *sc = XHCI_BUS2SC(bus); 184 uint8_t i; 185 186 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 187 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 188 189 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 190 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 191 192 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 193 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 194 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 195 } 196 } 197 198 static void 199 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 200 { 201 if (sc->sc_ctx_is_64_byte) { 202 uint32_t offset; 203 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 204 /* all contexts are initially 32-bytes */ 205 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 206 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 207 } 208 *ptr = htole32(val); 209 } 210 211 static uint32_t 212 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 213 { 214 if (sc->sc_ctx_is_64_byte) { 215 uint32_t offset; 216 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 217 /* all contexts are initially 32-bytes */ 218 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 219 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 220 } 221 return (le32toh(*ptr)); 222 } 223 224 static void 225 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 226 { 227 if (sc->sc_ctx_is_64_byte) { 228 uint32_t offset; 229 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 230 /* all contexts are initially 32-bytes */ 231 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 232 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 233 } 234 *ptr = htole64(val); 235 } 236 237 #ifdef USB_DEBUG 238 static uint64_t 239 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 240 { 241 if (sc->sc_ctx_is_64_byte) { 242 uint32_t offset; 243 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 244 /* all contexts are initially 32-bytes */ 245 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 246 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 247 } 248 return (le64toh(*ptr)); 249 } 250 #endif 251 252 usb_error_t 253 xhci_start_controller(struct xhci_softc *sc) 254 { 255 struct usb_page_search buf_res; 256 struct xhci_hw_root *phwr; 257 struct xhci_dev_ctx_addr *pdctxa; 258 uint64_t addr; 259 uint32_t temp; 260 uint16_t i; 261 262 DPRINTF("\n"); 263 264 sc->sc_capa_off = 0; 265 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 266 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 267 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 268 269 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 270 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 271 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 272 273 sc->sc_event_ccs = 1; 274 sc->sc_event_idx = 0; 275 sc->sc_command_ccs = 1; 276 sc->sc_command_idx = 0; 277 278 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 279 280 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 281 282 DPRINTF("HCS0 = 0x%08x\n", temp); 283 284 if (XHCI_HCS0_CSZ(temp)) { 285 sc->sc_ctx_is_64_byte = 1; 286 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 287 } else { 288 sc->sc_ctx_is_64_byte = 0; 289 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 290 } 291 292 /* Reset controller */ 293 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 294 295 for (i = 0; i != 100; i++) { 296 usb_pause_mtx(NULL, hz / 100); 297 temp = XREAD4(sc, oper, XHCI_USBCMD) & 298 (XHCI_CMD_HCRST | XHCI_STS_CNR); 299 if (!temp) 300 break; 301 } 302 303 if (temp) { 304 device_printf(sc->sc_bus.parent, "Controller " 305 "reset timeout.\n"); 306 return (USB_ERR_IOERROR); 307 } 308 309 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 310 device_printf(sc->sc_bus.parent, "Controller does " 311 "not support 4K page size.\n"); 312 return (USB_ERR_IOERROR); 313 } 314 315 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 316 317 i = XHCI_HCS1_N_PORTS(temp); 318 319 if (i == 0) { 320 device_printf(sc->sc_bus.parent, "Invalid number " 321 "of ports: %u\n", i); 322 return (USB_ERR_IOERROR); 323 } 324 325 sc->sc_noport = i; 326 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 327 328 if (sc->sc_noslot > XHCI_MAX_DEVICES) 329 sc->sc_noslot = XHCI_MAX_DEVICES; 330 331 /* setup number of device slots */ 332 333 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 334 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 335 336 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 337 338 DPRINTF("Max slots: %u\n", sc->sc_noslot); 339 340 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 341 342 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 343 344 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 345 device_printf(sc->sc_bus.parent, "XHCI request " 346 "too many scratchpads\n"); 347 return (USB_ERR_NOMEM); 348 } 349 350 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 351 352 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 353 354 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 355 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 356 357 temp = XREAD4(sc, oper, XHCI_USBSTS); 358 359 /* clear interrupts */ 360 XWRITE4(sc, oper, XHCI_USBSTS, temp); 361 /* disable all device notifications */ 362 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 363 364 /* setup device context base address */ 365 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 366 pdctxa = buf_res.buffer; 367 memset(pdctxa, 0, sizeof(*pdctxa)); 368 369 addr = buf_res.physaddr; 370 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 371 372 /* slot 0 points to the table of scratchpad pointers */ 373 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 374 375 for (i = 0; i != sc->sc_noscratch; i++) { 376 struct usb_page_search buf_scp; 377 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 378 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 379 } 380 381 addr = buf_res.physaddr; 382 383 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 384 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 385 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 386 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 387 388 /* Setup event table size */ 389 390 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 391 392 DPRINTF("HCS2=0x%08x\n", temp); 393 394 temp = XHCI_HCS2_ERST_MAX(temp); 395 temp = 1U << temp; 396 if (temp > XHCI_MAX_RSEG) 397 temp = XHCI_MAX_RSEG; 398 399 sc->sc_erst_max = temp; 400 401 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 402 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 403 404 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 405 406 /* Setup interrupt rate */ 407 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 408 409 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 410 411 phwr = buf_res.buffer; 412 addr = buf_res.physaddr; 413 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 414 415 /* reset hardware root structure */ 416 memset(phwr, 0, sizeof(*phwr)); 417 418 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 419 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 420 421 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 422 423 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 424 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 425 426 addr = (uint64_t)buf_res.physaddr; 427 428 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 429 430 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 431 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 432 433 /* Setup interrupter registers */ 434 435 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 436 temp |= XHCI_IMAN_INTR_ENA; 437 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 438 439 /* setup command ring control base address */ 440 addr = buf_res.physaddr; 441 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 442 443 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 444 445 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 446 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 447 448 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 449 450 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 451 452 /* Go! */ 453 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 454 XHCI_CMD_INTE | XHCI_CMD_HSEE); 455 456 for (i = 0; i != 100; i++) { 457 usb_pause_mtx(NULL, hz / 100); 458 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 459 if (!temp) 460 break; 461 } 462 if (temp) { 463 XWRITE4(sc, oper, XHCI_USBCMD, 0); 464 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 465 return (USB_ERR_IOERROR); 466 } 467 468 /* catch any lost interrupts */ 469 xhci_do_poll(&sc->sc_bus); 470 471 return (0); 472 } 473 474 usb_error_t 475 xhci_halt_controller(struct xhci_softc *sc) 476 { 477 uint32_t temp; 478 uint16_t i; 479 480 DPRINTF("\n"); 481 482 sc->sc_capa_off = 0; 483 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 484 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 485 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 486 487 /* Halt controller */ 488 XWRITE4(sc, oper, XHCI_USBCMD, 0); 489 490 for (i = 0; i != 100; i++) { 491 usb_pause_mtx(NULL, hz / 100); 492 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 493 if (temp) 494 break; 495 } 496 497 if (!temp) { 498 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 499 return (USB_ERR_IOERROR); 500 } 501 return (0); 502 } 503 504 usb_error_t 505 xhci_init(struct xhci_softc *sc, device_t self) 506 { 507 /* initialise some bus fields */ 508 sc->sc_bus.parent = self; 509 510 /* set the bus revision */ 511 sc->sc_bus.usbrev = USB_REV_3_0; 512 513 /* set up the bus struct */ 514 sc->sc_bus.methods = &xhci_bus_methods; 515 516 /* setup devices array */ 517 sc->sc_bus.devices = sc->sc_devices; 518 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 519 520 /* setup command queue mutex and condition varible */ 521 cv_init(&sc->sc_cmd_cv, "CMDQ"); 522 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 523 524 /* get all DMA memory */ 525 if (usb_bus_mem_alloc_all(&sc->sc_bus, 526 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 527 return (ENOMEM); 528 } 529 530 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 531 sc->sc_config_msg[0].bus = &sc->sc_bus; 532 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 533 sc->sc_config_msg[1].bus = &sc->sc_bus; 534 535 if (usb_proc_create(&sc->sc_config_proc, 536 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) { 537 printf("WARNING: Creation of XHCI configure " 538 "callback process failed.\n"); 539 } 540 return (0); 541 } 542 543 void 544 xhci_uninit(struct xhci_softc *sc) 545 { 546 usb_proc_free(&sc->sc_config_proc); 547 548 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 549 550 cv_destroy(&sc->sc_cmd_cv); 551 sx_destroy(&sc->sc_cmd_sx); 552 } 553 554 static void 555 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 556 { 557 struct xhci_softc *sc = XHCI_BUS2SC(bus); 558 559 switch (state) { 560 case USB_HW_POWER_SUSPEND: 561 DPRINTF("Stopping the XHCI\n"); 562 xhci_halt_controller(sc); 563 break; 564 case USB_HW_POWER_SHUTDOWN: 565 DPRINTF("Stopping the XHCI\n"); 566 xhci_halt_controller(sc); 567 break; 568 case USB_HW_POWER_RESUME: 569 DPRINTF("Starting the XHCI\n"); 570 xhci_start_controller(sc); 571 break; 572 default: 573 break; 574 } 575 } 576 577 static usb_error_t 578 xhci_generic_done_sub(struct usb_xfer *xfer) 579 { 580 struct xhci_td *td; 581 struct xhci_td *td_alt_next; 582 uint32_t len; 583 uint8_t status; 584 585 td = xfer->td_transfer_cache; 586 td_alt_next = td->alt_next; 587 588 if (xfer->aframes != xfer->nframes) 589 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 590 591 while (1) { 592 593 usb_pc_cpu_invalidate(td->page_cache); 594 595 status = td->status; 596 len = td->remainder; 597 598 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 599 xfer, (unsigned int)xfer->aframes, 600 (unsigned int)xfer->nframes, 601 (unsigned int)len, (unsigned int)td->len, 602 (unsigned int)status); 603 604 /* 605 * Verify the status length and 606 * add the length to "frlengths[]": 607 */ 608 if (len > td->len) { 609 /* should not happen */ 610 DPRINTF("Invalid status length, " 611 "0x%04x/0x%04x bytes\n", len, td->len); 612 status = XHCI_TRB_ERROR_LENGTH; 613 } else if (xfer->aframes != xfer->nframes) { 614 xfer->frlengths[xfer->aframes] += td->len - len; 615 } 616 /* Check for last transfer */ 617 if (((void *)td) == xfer->td_transfer_last) { 618 td = NULL; 619 break; 620 } 621 /* Check for transfer error */ 622 if (status != XHCI_TRB_ERROR_SHORT_PKT && 623 status != XHCI_TRB_ERROR_SUCCESS) { 624 /* the transfer is finished */ 625 td = NULL; 626 break; 627 } 628 /* Check for short transfer */ 629 if (len > 0) { 630 if (xfer->flags_int.short_frames_ok || 631 xfer->flags_int.isochronous_xfr || 632 xfer->flags_int.control_xfr) { 633 /* follow alt next */ 634 td = td->alt_next; 635 } else { 636 /* the transfer is finished */ 637 td = NULL; 638 } 639 break; 640 } 641 td = td->obj_next; 642 643 if (td->alt_next != td_alt_next) { 644 /* this USB frame is complete */ 645 break; 646 } 647 } 648 649 /* update transfer cache */ 650 651 xfer->td_transfer_cache = td; 652 653 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 654 (status != XHCI_TRB_ERROR_SHORT_PKT && 655 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 656 USB_ERR_NORMAL_COMPLETION); 657 } 658 659 static void 660 xhci_generic_done(struct usb_xfer *xfer) 661 { 662 usb_error_t err = 0; 663 664 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 665 xfer, xfer->endpoint); 666 667 /* reset scanner */ 668 669 xfer->td_transfer_cache = xfer->td_transfer_first; 670 671 if (xfer->flags_int.control_xfr) { 672 673 if (xfer->flags_int.control_hdr) 674 err = xhci_generic_done_sub(xfer); 675 676 xfer->aframes = 1; 677 678 if (xfer->td_transfer_cache == NULL) 679 goto done; 680 } 681 682 while (xfer->aframes != xfer->nframes) { 683 684 err = xhci_generic_done_sub(xfer); 685 xfer->aframes++; 686 687 if (xfer->td_transfer_cache == NULL) 688 goto done; 689 } 690 691 if (xfer->flags_int.control_xfr && 692 !xfer->flags_int.control_act) 693 err = xhci_generic_done_sub(xfer); 694 done: 695 /* transfer is complete */ 696 xhci_device_done(xfer, err); 697 } 698 699 static void 700 xhci_activate_transfer(struct usb_xfer *xfer) 701 { 702 struct xhci_td *td; 703 704 td = xfer->td_transfer_cache; 705 706 usb_pc_cpu_invalidate(td->page_cache); 707 708 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 709 710 /* activate the transfer */ 711 712 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 713 usb_pc_cpu_flush(td->page_cache); 714 715 xhci_endpoint_doorbell(xfer); 716 } 717 } 718 719 static void 720 xhci_skip_transfer(struct usb_xfer *xfer) 721 { 722 struct xhci_td *td; 723 struct xhci_td *td_last; 724 725 td = xfer->td_transfer_cache; 726 td_last = xfer->td_transfer_last; 727 728 td = td->alt_next; 729 730 usb_pc_cpu_invalidate(td->page_cache); 731 732 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 733 734 usb_pc_cpu_invalidate(td_last->page_cache); 735 736 /* copy LINK TRB to current waiting location */ 737 738 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 739 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 740 usb_pc_cpu_flush(td->page_cache); 741 742 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 743 usb_pc_cpu_flush(td->page_cache); 744 745 xhci_endpoint_doorbell(xfer); 746 } 747 } 748 749 /*------------------------------------------------------------------------* 750 * xhci_check_transfer 751 *------------------------------------------------------------------------*/ 752 static void 753 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 754 { 755 int64_t offset; 756 uint64_t td_event; 757 uint32_t temp; 758 uint32_t remainder; 759 uint8_t status; 760 uint8_t halted; 761 uint8_t epno; 762 uint8_t index; 763 uint8_t i; 764 765 /* decode TRB */ 766 td_event = le64toh(trb->qwTrb0); 767 temp = le32toh(trb->dwTrb2); 768 769 remainder = XHCI_TRB_2_REM_GET(temp); 770 status = XHCI_TRB_2_ERROR_GET(temp); 771 772 temp = le32toh(trb->dwTrb3); 773 epno = XHCI_TRB_3_EP_GET(temp); 774 index = XHCI_TRB_3_SLOT_GET(temp); 775 776 /* check if error means halted */ 777 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 778 status != XHCI_TRB_ERROR_SUCCESS); 779 780 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 781 index, epno, remainder, status); 782 783 if (index > sc->sc_noslot) { 784 DPRINTF("Invalid slot.\n"); 785 return; 786 } 787 788 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 789 DPRINTF("Invalid endpoint.\n"); 790 return; 791 } 792 793 /* try to find the USB transfer that generated the event */ 794 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 795 struct usb_xfer *xfer; 796 struct xhci_td *td; 797 struct xhci_endpoint_ext *pepext; 798 799 pepext = &sc->sc_hw.devs[index].endp[epno]; 800 801 xfer = pepext->xfer[i]; 802 if (xfer == NULL) 803 continue; 804 805 td = xfer->td_transfer_cache; 806 807 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 808 (long long)td_event, 809 (long long)td->td_self, 810 (long long)td->td_self + sizeof(td->td_trb)); 811 812 /* 813 * NOTE: Some XHCI implementations might not trigger 814 * an event on the last LINK TRB so we need to 815 * consider both the last and second last event 816 * address as conditions for a successful transfer. 817 * 818 * NOTE: We assume that the XHCI will only trigger one 819 * event per chain of TRBs. 820 */ 821 822 offset = td_event - td->td_self; 823 824 if (offset >= 0 && 825 offset < (int64_t)sizeof(td->td_trb)) { 826 827 usb_pc_cpu_invalidate(td->page_cache); 828 829 /* compute rest of remainder, if any */ 830 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 831 temp = le32toh(td->td_trb[i].dwTrb2); 832 remainder += XHCI_TRB_2_BYTES_GET(temp); 833 } 834 835 DPRINTFN(5, "New remainder: %u\n", remainder); 836 837 /* clear isochronous transfer errors */ 838 if (xfer->flags_int.isochronous_xfr) { 839 if (halted) { 840 halted = 0; 841 status = XHCI_TRB_ERROR_SUCCESS; 842 remainder = td->len; 843 } 844 } 845 846 /* "td->remainder" is verified later */ 847 td->remainder = remainder; 848 td->status = status; 849 850 usb_pc_cpu_flush(td->page_cache); 851 852 /* 853 * 1) Last transfer descriptor makes the 854 * transfer done 855 */ 856 if (((void *)td) == xfer->td_transfer_last) { 857 DPRINTF("TD is last\n"); 858 xhci_generic_done(xfer); 859 break; 860 } 861 862 /* 863 * 2) Any kind of error makes the transfer 864 * done 865 */ 866 if (halted) { 867 DPRINTF("TD has I/O error\n"); 868 xhci_generic_done(xfer); 869 break; 870 } 871 872 /* 873 * 3) If there is no alternate next transfer, 874 * a short packet also makes the transfer done 875 */ 876 if (td->remainder > 0) { 877 DPRINTF("TD has short pkt\n"); 878 if (xfer->flags_int.short_frames_ok || 879 xfer->flags_int.isochronous_xfr || 880 xfer->flags_int.control_xfr) { 881 /* follow the alt next */ 882 xfer->td_transfer_cache = td->alt_next; 883 xhci_activate_transfer(xfer); 884 break; 885 } 886 xhci_skip_transfer(xfer); 887 xhci_generic_done(xfer); 888 break; 889 } 890 891 /* 892 * 4) Transfer complete - go to next TD 893 */ 894 DPRINTF("Following next TD\n"); 895 xfer->td_transfer_cache = td->obj_next; 896 xhci_activate_transfer(xfer); 897 break; /* there should only be one match */ 898 } 899 } 900 } 901 902 static void 903 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 904 { 905 if (sc->sc_cmd_addr == trb->qwTrb0) { 906 DPRINTF("Received command event\n"); 907 sc->sc_cmd_result[0] = trb->dwTrb2; 908 sc->sc_cmd_result[1] = trb->dwTrb3; 909 cv_signal(&sc->sc_cmd_cv); 910 } 911 } 912 913 static void 914 xhci_interrupt_poll(struct xhci_softc *sc) 915 { 916 struct usb_page_search buf_res; 917 struct xhci_hw_root *phwr; 918 uint64_t addr; 919 uint32_t temp; 920 uint16_t i; 921 uint8_t event; 922 uint8_t j; 923 uint8_t k; 924 uint8_t t; 925 926 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 927 928 phwr = buf_res.buffer; 929 930 /* Receive any events */ 931 932 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 933 934 i = sc->sc_event_idx; 935 j = sc->sc_event_ccs; 936 t = 2; 937 938 while (1) { 939 940 temp = le32toh(phwr->hwr_events[i].dwTrb3); 941 942 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 943 944 if (j != k) 945 break; 946 947 event = XHCI_TRB_3_TYPE_GET(temp); 948 949 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 950 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 951 (long)le32toh(phwr->hwr_events[i].dwTrb2), 952 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 953 954 switch (event) { 955 case XHCI_TRB_EVENT_TRANSFER: 956 xhci_check_transfer(sc, &phwr->hwr_events[i]); 957 break; 958 case XHCI_TRB_EVENT_CMD_COMPLETE: 959 xhci_check_command(sc, &phwr->hwr_events[i]); 960 break; 961 default: 962 DPRINTF("Unhandled event = %u\n", event); 963 break; 964 } 965 966 i++; 967 968 if (i == XHCI_MAX_EVENTS) { 969 i = 0; 970 j ^= 1; 971 972 /* check for timeout */ 973 if (!--t) 974 break; 975 } 976 } 977 978 sc->sc_event_idx = i; 979 sc->sc_event_ccs = j; 980 981 /* 982 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 983 * latched. That means to activate the register we need to 984 * write both the low and high double word of the 64-bit 985 * register. 986 */ 987 988 addr = (uint32_t)buf_res.physaddr; 989 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 990 991 /* try to clear busy bit */ 992 addr |= XHCI_ERDP_LO_BUSY; 993 994 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 995 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 996 } 997 998 static usb_error_t 999 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1000 uint16_t timeout_ms) 1001 { 1002 struct usb_page_search buf_res; 1003 struct xhci_hw_root *phwr; 1004 uint64_t addr; 1005 uint32_t temp; 1006 uint8_t i; 1007 uint8_t j; 1008 int err; 1009 1010 XHCI_CMD_ASSERT_LOCKED(sc); 1011 1012 /* get hardware root structure */ 1013 1014 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1015 1016 phwr = buf_res.buffer; 1017 1018 /* Queue command */ 1019 1020 USB_BUS_LOCK(&sc->sc_bus); 1021 1022 i = sc->sc_command_idx; 1023 j = sc->sc_command_ccs; 1024 1025 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1026 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1027 (long long)le64toh(trb->qwTrb0), 1028 (long)le32toh(trb->dwTrb2), 1029 (long)le32toh(trb->dwTrb3)); 1030 1031 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1032 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1033 1034 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1035 1036 temp = trb->dwTrb3; 1037 1038 if (j) 1039 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1040 else 1041 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1042 1043 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1044 1045 phwr->hwr_commands[i].dwTrb3 = temp; 1046 1047 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1048 1049 addr = buf_res.physaddr; 1050 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1051 1052 sc->sc_cmd_addr = htole64(addr); 1053 1054 i++; 1055 1056 if (i == (XHCI_MAX_COMMANDS - 1)) { 1057 1058 if (j) { 1059 temp = htole32(XHCI_TRB_3_TC_BIT | 1060 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1061 XHCI_TRB_3_CYCLE_BIT); 1062 } else { 1063 temp = htole32(XHCI_TRB_3_TC_BIT | 1064 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1065 } 1066 1067 phwr->hwr_commands[i].dwTrb3 = temp; 1068 1069 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1070 1071 i = 0; 1072 j ^= 1; 1073 } 1074 1075 sc->sc_command_idx = i; 1076 sc->sc_command_ccs = j; 1077 1078 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1079 1080 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1081 USB_MS_TO_TICKS(timeout_ms)); 1082 1083 if (err) { 1084 DPRINTFN(0, "Command timeout!\n"); 1085 err = USB_ERR_TIMEOUT; 1086 trb->dwTrb2 = 0; 1087 trb->dwTrb3 = 0; 1088 } else { 1089 temp = le32toh(sc->sc_cmd_result[0]); 1090 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1091 err = USB_ERR_IOERROR; 1092 1093 trb->dwTrb2 = sc->sc_cmd_result[0]; 1094 trb->dwTrb3 = sc->sc_cmd_result[1]; 1095 } 1096 1097 USB_BUS_UNLOCK(&sc->sc_bus); 1098 1099 return (err); 1100 } 1101 1102 #if 0 1103 static usb_error_t 1104 xhci_cmd_nop(struct xhci_softc *sc) 1105 { 1106 struct xhci_trb trb; 1107 uint32_t temp; 1108 1109 DPRINTF("\n"); 1110 1111 trb.qwTrb0 = 0; 1112 trb.dwTrb2 = 0; 1113 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1114 1115 trb.dwTrb3 = htole32(temp); 1116 1117 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1118 } 1119 #endif 1120 1121 static usb_error_t 1122 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1123 { 1124 struct xhci_trb trb; 1125 uint32_t temp; 1126 usb_error_t err; 1127 1128 DPRINTF("\n"); 1129 1130 trb.qwTrb0 = 0; 1131 trb.dwTrb2 = 0; 1132 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1133 1134 err = xhci_do_command(sc, &trb, 100 /* ms */); 1135 if (err) 1136 goto done; 1137 1138 temp = le32toh(trb.dwTrb3); 1139 1140 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1141 1142 done: 1143 return (err); 1144 } 1145 1146 static usb_error_t 1147 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1148 { 1149 struct xhci_trb trb; 1150 uint32_t temp; 1151 1152 DPRINTF("\n"); 1153 1154 trb.qwTrb0 = 0; 1155 trb.dwTrb2 = 0; 1156 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1157 XHCI_TRB_3_SLOT_SET(slot_id); 1158 1159 trb.dwTrb3 = htole32(temp); 1160 1161 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1162 } 1163 1164 static usb_error_t 1165 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1166 uint8_t bsr, uint8_t slot_id) 1167 { 1168 struct xhci_trb trb; 1169 uint32_t temp; 1170 1171 DPRINTF("\n"); 1172 1173 trb.qwTrb0 = htole64(input_ctx); 1174 trb.dwTrb2 = 0; 1175 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1176 XHCI_TRB_3_SLOT_SET(slot_id); 1177 1178 if (bsr) 1179 temp |= XHCI_TRB_3_BSR_BIT; 1180 1181 trb.dwTrb3 = htole32(temp); 1182 1183 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1184 } 1185 1186 static usb_error_t 1187 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1188 { 1189 struct usb_page_search buf_inp; 1190 struct usb_page_search buf_dev; 1191 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1192 struct xhci_hw_dev *hdev; 1193 struct xhci_dev_ctx *pdev; 1194 struct xhci_endpoint_ext *pepext; 1195 uint32_t temp; 1196 uint16_t mps; 1197 usb_error_t err; 1198 uint8_t index; 1199 1200 /* the root HUB case is not handled here */ 1201 if (udev->parent_hub == NULL) 1202 return (USB_ERR_INVAL); 1203 1204 index = udev->controller_slot_id; 1205 1206 hdev = &sc->sc_hw.devs[index]; 1207 1208 if (mtx != NULL) 1209 mtx_unlock(mtx); 1210 1211 XHCI_CMD_LOCK(sc); 1212 1213 switch (hdev->state) { 1214 case XHCI_ST_DEFAULT: 1215 case XHCI_ST_ENABLED: 1216 1217 hdev->state = XHCI_ST_ENABLED; 1218 1219 /* set configure mask to slot and EP0 */ 1220 xhci_configure_mask(udev, 3, 0); 1221 1222 /* configure input slot context structure */ 1223 err = xhci_configure_device(udev); 1224 1225 if (err != 0) { 1226 DPRINTF("Could not configure device\n"); 1227 break; 1228 } 1229 1230 /* configure input endpoint context structure */ 1231 switch (udev->speed) { 1232 case USB_SPEED_LOW: 1233 case USB_SPEED_FULL: 1234 mps = 8; 1235 break; 1236 case USB_SPEED_HIGH: 1237 mps = 64; 1238 break; 1239 default: 1240 mps = 512; 1241 break; 1242 } 1243 1244 pepext = xhci_get_endpoint_ext(udev, 1245 &udev->ctrl_ep_desc); 1246 err = xhci_configure_endpoint(udev, 1247 &udev->ctrl_ep_desc, pepext->physaddr, 1248 0, 1, 1, 0, mps, mps); 1249 1250 if (err != 0) { 1251 DPRINTF("Could not configure default endpoint\n"); 1252 break; 1253 } 1254 1255 /* execute set address command */ 1256 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1257 1258 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1259 (address == 0), index); 1260 1261 if (err != 0) { 1262 DPRINTF("Could not set address " 1263 "for slot %u.\n", index); 1264 if (address != 0) 1265 break; 1266 } 1267 1268 /* update device address to new value */ 1269 1270 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1271 pdev = buf_dev.buffer; 1272 usb_pc_cpu_invalidate(&hdev->device_pc); 1273 1274 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1275 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1276 1277 /* update device state to new value */ 1278 1279 if (address != 0) 1280 hdev->state = XHCI_ST_ADDRESSED; 1281 else 1282 hdev->state = XHCI_ST_DEFAULT; 1283 break; 1284 1285 default: 1286 DPRINTF("Wrong state for set address.\n"); 1287 err = USB_ERR_IOERROR; 1288 break; 1289 } 1290 XHCI_CMD_UNLOCK(sc); 1291 1292 if (mtx != NULL) 1293 mtx_lock(mtx); 1294 1295 return (err); 1296 } 1297 1298 static usb_error_t 1299 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1300 uint8_t deconfigure, uint8_t slot_id) 1301 { 1302 struct xhci_trb trb; 1303 uint32_t temp; 1304 1305 DPRINTF("\n"); 1306 1307 trb.qwTrb0 = htole64(input_ctx); 1308 trb.dwTrb2 = 0; 1309 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1310 XHCI_TRB_3_SLOT_SET(slot_id); 1311 1312 if (deconfigure) 1313 temp |= XHCI_TRB_3_DCEP_BIT; 1314 1315 trb.dwTrb3 = htole32(temp); 1316 1317 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1318 } 1319 1320 static usb_error_t 1321 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1322 uint8_t slot_id) 1323 { 1324 struct xhci_trb trb; 1325 uint32_t temp; 1326 1327 DPRINTF("\n"); 1328 1329 trb.qwTrb0 = htole64(input_ctx); 1330 trb.dwTrb2 = 0; 1331 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1332 XHCI_TRB_3_SLOT_SET(slot_id); 1333 trb.dwTrb3 = htole32(temp); 1334 1335 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1336 } 1337 1338 static usb_error_t 1339 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1340 uint8_t ep_id, uint8_t slot_id) 1341 { 1342 struct xhci_trb trb; 1343 uint32_t temp; 1344 1345 DPRINTF("\n"); 1346 1347 trb.qwTrb0 = 0; 1348 trb.dwTrb2 = 0; 1349 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1350 XHCI_TRB_3_SLOT_SET(slot_id) | 1351 XHCI_TRB_3_EP_SET(ep_id); 1352 1353 if (preserve) 1354 temp |= XHCI_TRB_3_PRSV_BIT; 1355 1356 trb.dwTrb3 = htole32(temp); 1357 1358 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1359 } 1360 1361 static usb_error_t 1362 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1363 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1364 { 1365 struct xhci_trb trb; 1366 uint32_t temp; 1367 1368 DPRINTF("\n"); 1369 1370 trb.qwTrb0 = htole64(dequeue_ptr); 1371 1372 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1373 trb.dwTrb2 = htole32(temp); 1374 1375 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1376 XHCI_TRB_3_SLOT_SET(slot_id) | 1377 XHCI_TRB_3_EP_SET(ep_id); 1378 trb.dwTrb3 = htole32(temp); 1379 1380 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1381 } 1382 1383 static usb_error_t 1384 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1385 uint8_t ep_id, uint8_t slot_id) 1386 { 1387 struct xhci_trb trb; 1388 uint32_t temp; 1389 1390 DPRINTF("\n"); 1391 1392 trb.qwTrb0 = 0; 1393 trb.dwTrb2 = 0; 1394 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1395 XHCI_TRB_3_SLOT_SET(slot_id) | 1396 XHCI_TRB_3_EP_SET(ep_id); 1397 1398 if (suspend) 1399 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1400 1401 trb.dwTrb3 = htole32(temp); 1402 1403 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1404 } 1405 1406 static usb_error_t 1407 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1408 { 1409 struct xhci_trb trb; 1410 uint32_t temp; 1411 1412 DPRINTF("\n"); 1413 1414 trb.qwTrb0 = 0; 1415 trb.dwTrb2 = 0; 1416 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1417 XHCI_TRB_3_SLOT_SET(slot_id); 1418 1419 trb.dwTrb3 = htole32(temp); 1420 1421 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1422 } 1423 1424 /*------------------------------------------------------------------------* 1425 * xhci_interrupt - XHCI interrupt handler 1426 *------------------------------------------------------------------------*/ 1427 void 1428 xhci_interrupt(struct xhci_softc *sc) 1429 { 1430 uint32_t status; 1431 uint32_t temp; 1432 1433 USB_BUS_LOCK(&sc->sc_bus); 1434 1435 status = XREAD4(sc, oper, XHCI_USBSTS); 1436 1437 /* acknowledge interrupts */ 1438 1439 XWRITE4(sc, oper, XHCI_USBSTS, status); 1440 1441 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1442 1443 /* acknowledge pending event */ 1444 1445 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1446 1447 DPRINTFN(16, "real interrupt (sts=0x%08x, " 1448 "iman=0x%08x)\n", status, temp); 1449 1450 if (status != 0) { 1451 if (status & XHCI_STS_PCD) { 1452 xhci_root_intr(sc); 1453 } 1454 1455 if (status & XHCI_STS_HCH) { 1456 printf("%s: host controller halted\n", 1457 __FUNCTION__); 1458 } 1459 1460 if (status & XHCI_STS_HSE) { 1461 printf("%s: host system error\n", 1462 __FUNCTION__); 1463 } 1464 1465 if (status & XHCI_STS_HCE) { 1466 printf("%s: host controller error\n", 1467 __FUNCTION__); 1468 } 1469 } 1470 1471 xhci_interrupt_poll(sc); 1472 1473 USB_BUS_UNLOCK(&sc->sc_bus); 1474 } 1475 1476 /*------------------------------------------------------------------------* 1477 * xhci_timeout - XHCI timeout handler 1478 *------------------------------------------------------------------------*/ 1479 static void 1480 xhci_timeout(void *arg) 1481 { 1482 struct usb_xfer *xfer = arg; 1483 1484 DPRINTF("xfer=%p\n", xfer); 1485 1486 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1487 1488 /* transfer is transferred */ 1489 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1490 } 1491 1492 static void 1493 xhci_do_poll(struct usb_bus *bus) 1494 { 1495 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1496 1497 USB_BUS_LOCK(&sc->sc_bus); 1498 xhci_interrupt_poll(sc); 1499 USB_BUS_UNLOCK(&sc->sc_bus); 1500 } 1501 1502 static void 1503 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1504 { 1505 struct usb_page_search buf_res; 1506 struct xhci_td *td; 1507 struct xhci_td *td_next; 1508 struct xhci_td *td_alt_next; 1509 uint32_t buf_offset; 1510 uint32_t average; 1511 uint32_t len_old; 1512 uint32_t dword; 1513 uint8_t shortpkt_old; 1514 uint8_t precompute; 1515 uint8_t x; 1516 1517 td_alt_next = NULL; 1518 buf_offset = 0; 1519 shortpkt_old = temp->shortpkt; 1520 len_old = temp->len; 1521 precompute = 1; 1522 1523 restart: 1524 1525 td = temp->td; 1526 td_next = temp->td_next; 1527 1528 while (1) { 1529 1530 if (temp->len == 0) { 1531 1532 if (temp->shortpkt) 1533 break; 1534 1535 /* send a Zero Length Packet, ZLP, last */ 1536 1537 temp->shortpkt = 1; 1538 average = 0; 1539 1540 } else { 1541 1542 average = temp->average; 1543 1544 if (temp->len < average) { 1545 if (temp->len % temp->max_packet_size) { 1546 temp->shortpkt = 1; 1547 } 1548 average = temp->len; 1549 } 1550 } 1551 1552 if (td_next == NULL) 1553 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1554 1555 /* get next TD */ 1556 1557 td = td_next; 1558 td_next = td->obj_next; 1559 1560 /* check if we are pre-computing */ 1561 1562 if (precompute) { 1563 1564 /* update remaining length */ 1565 1566 temp->len -= average; 1567 1568 continue; 1569 } 1570 /* fill out current TD */ 1571 1572 td->len = average; 1573 td->remainder = 0; 1574 td->status = 0; 1575 1576 /* update remaining length */ 1577 1578 temp->len -= average; 1579 1580 /* reset TRB index */ 1581 1582 x = 0; 1583 1584 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1585 /* immediate data */ 1586 1587 if (average > 8) 1588 average = 8; 1589 1590 td->td_trb[0].qwTrb0 = 0; 1591 1592 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1593 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1594 average); 1595 1596 dword = XHCI_TRB_2_BYTES_SET(8) | 1597 XHCI_TRB_2_TDSZ_SET(0) | 1598 XHCI_TRB_2_IRQ_SET(0); 1599 1600 td->td_trb[0].dwTrb2 = htole32(dword); 1601 1602 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1603 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1604 1605 /* check wLength */ 1606 if (td->td_trb[0].qwTrb0 & 1607 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1608 if (td->td_trb[0].qwTrb0 & htole64(1)) 1609 dword |= XHCI_TRB_3_TRT_IN; 1610 else 1611 dword |= XHCI_TRB_3_TRT_OUT; 1612 } 1613 1614 td->td_trb[0].dwTrb3 = htole32(dword); 1615 #ifdef USB_DEBUG 1616 xhci_dump_trb(&td->td_trb[x]); 1617 #endif 1618 x++; 1619 1620 } else do { 1621 1622 uint32_t npkt; 1623 1624 /* fill out buffer pointers */ 1625 1626 if (average == 0) { 1627 npkt = 1; 1628 memset(&buf_res, 0, sizeof(buf_res)); 1629 } else { 1630 usbd_get_page(temp->pc, temp->offset + 1631 buf_offset, &buf_res); 1632 1633 /* get length to end of page */ 1634 if (buf_res.length > average) 1635 buf_res.length = average; 1636 1637 /* check for maximum length */ 1638 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1639 buf_res.length = XHCI_TD_PAGE_SIZE; 1640 1641 /* setup npkt */ 1642 npkt = (average + temp->max_packet_size - 1) / 1643 temp->max_packet_size; 1644 1645 if (npkt > 31) 1646 npkt = 31; 1647 } 1648 1649 /* fill out TRB's */ 1650 td->td_trb[x].qwTrb0 = 1651 htole64((uint64_t)buf_res.physaddr); 1652 1653 dword = 1654 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1655 XHCI_TRB_2_TDSZ_SET(npkt) | 1656 XHCI_TRB_2_IRQ_SET(0); 1657 1658 td->td_trb[x].dwTrb2 = htole32(dword); 1659 1660 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1661 XHCI_TRB_3_TYPE_SET(temp->trb_type) | 1662 (temp->do_isoc_sync ? 1663 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) : 1664 XHCI_TRB_3_ISO_SIA_BIT) | 1665 XHCI_TRB_3_TBC_SET(temp->tbc) | 1666 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1667 1668 temp->do_isoc_sync = 0; 1669 1670 if (temp->direction == UE_DIR_IN) { 1671 dword |= XHCI_TRB_3_DIR_IN; 1672 1673 /* 1674 * NOTE: Only the SETUP stage should 1675 * use the IDT bit. Else transactions 1676 * can be sent using the wrong data 1677 * toggle value. 1678 */ 1679 if (temp->trb_type != 1680 XHCI_TRB_TYPE_SETUP_STAGE && 1681 temp->trb_type != 1682 XHCI_TRB_TYPE_STATUS_STAGE) 1683 dword |= XHCI_TRB_3_ISP_BIT; 1684 } 1685 1686 td->td_trb[x].dwTrb3 = htole32(dword); 1687 1688 average -= buf_res.length; 1689 buf_offset += buf_res.length; 1690 #ifdef USB_DEBUG 1691 xhci_dump_trb(&td->td_trb[x]); 1692 #endif 1693 x++; 1694 1695 } while (average != 0); 1696 1697 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1698 1699 /* store number of data TRB's */ 1700 1701 td->ntrb = x; 1702 1703 DPRINTF("NTRB=%u\n", x); 1704 1705 /* fill out link TRB */ 1706 1707 if (td_next != NULL) { 1708 /* link the current TD with the next one */ 1709 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1710 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1711 } else { 1712 /* this field will get updated later */ 1713 DPRINTF("NOLINK\n"); 1714 } 1715 1716 dword = XHCI_TRB_2_IRQ_SET(0); 1717 1718 td->td_trb[x].dwTrb2 = htole32(dword); 1719 1720 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1721 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT; 1722 1723 td->td_trb[x].dwTrb3 = htole32(dword); 1724 1725 td->alt_next = td_alt_next; 1726 #ifdef USB_DEBUG 1727 xhci_dump_trb(&td->td_trb[x]); 1728 #endif 1729 usb_pc_cpu_flush(td->page_cache); 1730 } 1731 1732 if (precompute) { 1733 precompute = 0; 1734 1735 /* setup alt next pointer, if any */ 1736 if (temp->last_frame) { 1737 td_alt_next = NULL; 1738 } else { 1739 /* we use this field internally */ 1740 td_alt_next = td_next; 1741 } 1742 1743 /* restore */ 1744 temp->shortpkt = shortpkt_old; 1745 temp->len = len_old; 1746 goto restart; 1747 } 1748 1749 /* remove cycle bit from first if we are stepping the TRBs */ 1750 if (temp->step_td) 1751 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1752 1753 /* remove chain bit because this is the last TRB in the chain */ 1754 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1755 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1756 1757 usb_pc_cpu_flush(td->page_cache); 1758 1759 temp->td = td; 1760 temp->td_next = td_next; 1761 } 1762 1763 static void 1764 xhci_setup_generic_chain(struct usb_xfer *xfer) 1765 { 1766 struct xhci_std_temp temp; 1767 struct xhci_td *td; 1768 uint32_t x; 1769 uint32_t y; 1770 uint8_t mult; 1771 1772 temp.do_isoc_sync = 0; 1773 temp.step_td = 0; 1774 temp.tbc = 0; 1775 temp.tlbpc = 0; 1776 temp.average = xfer->max_hc_frame_size; 1777 temp.max_packet_size = xfer->max_packet_size; 1778 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1779 temp.pc = NULL; 1780 temp.last_frame = 0; 1781 temp.offset = 0; 1782 temp.multishort = xfer->flags_int.isochronous_xfr || 1783 xfer->flags_int.control_xfr || 1784 xfer->flags_int.short_frames_ok; 1785 1786 /* toggle the DMA set we are using */ 1787 xfer->flags_int.curr_dma_set ^= 1; 1788 1789 /* get next DMA set */ 1790 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1791 1792 temp.td = NULL; 1793 temp.td_next = td; 1794 1795 xfer->td_transfer_first = td; 1796 xfer->td_transfer_cache = td; 1797 1798 if (xfer->flags_int.isochronous_xfr) { 1799 uint8_t shift; 1800 1801 /* compute multiplier for ISOCHRONOUS transfers */ 1802 mult = xfer->endpoint->ecomp ? 1803 (xfer->endpoint->ecomp->bmAttributes & 3) : 0; 1804 /* check for USB 2.0 multiplier */ 1805 if (mult == 0) { 1806 mult = (xfer->endpoint->edesc-> 1807 wMaxPacketSize[1] >> 3) & 3; 1808 } 1809 /* range check */ 1810 if (mult > 2) 1811 mult = 3; 1812 else 1813 mult++; 1814 1815 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 1816 1817 DPRINTF("MFINDEX=0x%08x\n", x); 1818 1819 switch (usbd_get_speed(xfer->xroot->udev)) { 1820 case USB_SPEED_FULL: 1821 shift = 3; 1822 temp.isoc_delta = 8; /* 1ms */ 1823 x += temp.isoc_delta - 1; 1824 x &= ~(temp.isoc_delta - 1); 1825 break; 1826 default: 1827 shift = usbd_xfer_get_fps_shift(xfer); 1828 temp.isoc_delta = 1U << shift; 1829 x += temp.isoc_delta - 1; 1830 x &= ~(temp.isoc_delta - 1); 1831 /* simple frame load balancing */ 1832 x += xfer->endpoint->usb_uframe; 1833 break; 1834 } 1835 1836 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 1837 1838 if ((xfer->endpoint->is_synced == 0) || 1839 (y < (xfer->nframes << shift)) || 1840 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 1841 /* 1842 * If there is data underflow or the pipe 1843 * queue is empty we schedule the transfer a 1844 * few frames ahead of the current frame 1845 * position. Else two isochronous transfers 1846 * might overlap. 1847 */ 1848 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 1849 xfer->endpoint->is_synced = 1; 1850 temp.do_isoc_sync = 1; 1851 1852 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1853 } 1854 1855 /* compute isochronous completion time */ 1856 1857 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 1858 1859 xfer->isoc_time_complete = 1860 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 1861 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 1862 1863 x = 0; 1864 temp.isoc_frame = xfer->endpoint->isoc_next; 1865 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 1866 1867 xfer->endpoint->isoc_next += xfer->nframes << shift; 1868 1869 } else if (xfer->flags_int.control_xfr) { 1870 1871 /* check if we should prepend a setup message */ 1872 1873 if (xfer->flags_int.control_hdr) { 1874 1875 temp.len = xfer->frlengths[0]; 1876 temp.pc = xfer->frbuffers + 0; 1877 temp.shortpkt = temp.len ? 1 : 0; 1878 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 1879 temp.direction = 0; 1880 1881 /* check for last frame */ 1882 if (xfer->nframes == 1) { 1883 /* no STATUS stage yet, SETUP is last */ 1884 if (xfer->flags_int.control_act) 1885 temp.last_frame = 1; 1886 } 1887 1888 xhci_setup_generic_chain_sub(&temp); 1889 } 1890 x = 1; 1891 mult = 1; 1892 temp.isoc_delta = 0; 1893 temp.isoc_frame = 0; 1894 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 1895 } else { 1896 x = 0; 1897 mult = 1; 1898 temp.isoc_delta = 0; 1899 temp.isoc_frame = 0; 1900 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 1901 } 1902 1903 if (x != xfer->nframes) { 1904 /* setup page_cache pointer */ 1905 temp.pc = xfer->frbuffers + x; 1906 /* set endpoint direction */ 1907 temp.direction = UE_GET_DIR(xfer->endpointno); 1908 } 1909 1910 while (x != xfer->nframes) { 1911 1912 /* DATA0 / DATA1 message */ 1913 1914 temp.len = xfer->frlengths[x]; 1915 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 1916 x != 0 && temp.multishort == 0); 1917 1918 x++; 1919 1920 if (x == xfer->nframes) { 1921 if (xfer->flags_int.control_xfr) { 1922 /* no STATUS stage yet, DATA is last */ 1923 if (xfer->flags_int.control_act) 1924 temp.last_frame = 1; 1925 } else { 1926 temp.last_frame = 1; 1927 } 1928 } 1929 if (temp.len == 0) { 1930 1931 /* make sure that we send an USB packet */ 1932 1933 temp.shortpkt = 0; 1934 1935 temp.tbc = 0; 1936 temp.tlbpc = mult - 1; 1937 1938 } else if (xfer->flags_int.isochronous_xfr) { 1939 1940 uint8_t tdpc; 1941 1942 /* 1943 * Isochronous transfers don't have short 1944 * packet termination: 1945 */ 1946 1947 temp.shortpkt = 1; 1948 1949 /* isochronous transfers have a transfer limit */ 1950 1951 if (temp.len > xfer->max_frame_size) 1952 temp.len = xfer->max_frame_size; 1953 1954 /* compute TD packet count */ 1955 tdpc = (temp.len + xfer->max_packet_size - 1) / 1956 xfer->max_packet_size; 1957 1958 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 1959 temp.tlbpc = (tdpc % mult); 1960 1961 if (temp.tlbpc == 0) 1962 temp.tlbpc = mult - 1; 1963 else 1964 temp.tlbpc--; 1965 } else { 1966 1967 /* regular data transfer */ 1968 1969 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 1970 } 1971 1972 xhci_setup_generic_chain_sub(&temp); 1973 1974 if (xfer->flags_int.isochronous_xfr) { 1975 temp.offset += xfer->frlengths[x - 1]; 1976 temp.isoc_frame += temp.isoc_delta; 1977 } else { 1978 /* get next Page Cache pointer */ 1979 temp.pc = xfer->frbuffers + x; 1980 } 1981 } 1982 1983 /* check if we should append a status stage */ 1984 1985 if (xfer->flags_int.control_xfr && 1986 !xfer->flags_int.control_act) { 1987 1988 /* 1989 * Send a DATA1 message and invert the current 1990 * endpoint direction. 1991 */ 1992 temp.step_td = (xfer->nframes != 0); 1993 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 1994 temp.len = 0; 1995 temp.pc = NULL; 1996 temp.shortpkt = 0; 1997 temp.last_frame = 1; 1998 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 1999 2000 xhci_setup_generic_chain_sub(&temp); 2001 } 2002 2003 td = temp.td; 2004 2005 /* must have at least one frame! */ 2006 2007 xfer->td_transfer_last = td; 2008 2009 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2010 } 2011 2012 static void 2013 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2014 { 2015 struct usb_page_search buf_res; 2016 struct xhci_dev_ctx_addr *pdctxa; 2017 2018 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2019 2020 pdctxa = buf_res.buffer; 2021 2022 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2023 2024 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2025 2026 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2027 } 2028 2029 static usb_error_t 2030 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2031 { 2032 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2033 struct usb_page_search buf_inp; 2034 struct xhci_input_dev_ctx *pinp; 2035 uint8_t index; 2036 2037 index = udev->controller_slot_id; 2038 2039 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2040 2041 pinp = buf_inp.buffer; 2042 2043 if (drop) { 2044 mask &= XHCI_INCTX_NON_CTRL_MASK; 2045 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2046 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2047 } else { 2048 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2049 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2050 } 2051 return (0); 2052 } 2053 2054 static usb_error_t 2055 xhci_configure_endpoint(struct usb_device *udev, 2056 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr, 2057 uint16_t interval, uint8_t max_packet_count, uint8_t mult, 2058 uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size) 2059 { 2060 struct usb_page_search buf_inp; 2061 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2062 struct xhci_input_dev_ctx *pinp; 2063 uint32_t temp; 2064 uint8_t index; 2065 uint8_t epno; 2066 uint8_t type; 2067 2068 index = udev->controller_slot_id; 2069 2070 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2071 2072 pinp = buf_inp.buffer; 2073 2074 epno = edesc->bEndpointAddress; 2075 type = edesc->bmAttributes & UE_XFERTYPE; 2076 2077 if (type == UE_CONTROL) 2078 epno |= UE_DIR_IN; 2079 2080 epno = XHCI_EPNO2EPID(epno); 2081 2082 if (epno == 0) 2083 return (USB_ERR_NO_PIPE); /* invalid */ 2084 2085 if (max_packet_count == 0) 2086 return (USB_ERR_BAD_BUFSIZE); 2087 2088 max_packet_count--; 2089 2090 if (mult == 0) 2091 return (USB_ERR_BAD_BUFSIZE); 2092 2093 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2094 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2095 XHCI_EPCTX_0_LSA_SET(0); 2096 2097 switch (udev->speed) { 2098 case USB_SPEED_FULL: 2099 case USB_SPEED_LOW: 2100 /* 1ms -> 125us */ 2101 fps_shift += 3; 2102 break; 2103 default: 2104 break; 2105 } 2106 2107 switch (type) { 2108 case UE_INTERRUPT: 2109 if (fps_shift > 3) 2110 fps_shift--; 2111 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2112 break; 2113 case UE_ISOCHRONOUS: 2114 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2115 2116 switch (udev->speed) { 2117 case USB_SPEED_SUPER: 2118 if (mult > 3) 2119 mult = 3; 2120 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2121 max_packet_count /= mult; 2122 break; 2123 default: 2124 break; 2125 } 2126 break; 2127 default: 2128 break; 2129 } 2130 2131 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2132 2133 temp = 2134 XHCI_EPCTX_1_HID_SET(0) | 2135 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2136 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2137 2138 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2139 if (type != UE_ISOCHRONOUS) 2140 temp |= XHCI_EPCTX_1_CERR_SET(3); 2141 } 2142 2143 switch (type) { 2144 case UE_CONTROL: 2145 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2146 break; 2147 case UE_ISOCHRONOUS: 2148 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2149 break; 2150 case UE_BULK: 2151 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2152 break; 2153 default: 2154 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2155 break; 2156 } 2157 2158 /* check for IN direction */ 2159 if (epno & 1) 2160 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2161 2162 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2163 2164 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2165 2166 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2167 2168 switch (edesc->bmAttributes & UE_XFERTYPE) { 2169 case UE_INTERRUPT: 2170 case UE_ISOCHRONOUS: 2171 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2172 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2173 max_frame_size)); 2174 break; 2175 case UE_CONTROL: 2176 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2177 break; 2178 default: 2179 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2180 break; 2181 } 2182 2183 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2184 2185 #ifdef USB_DEBUG 2186 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2187 #endif 2188 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2189 2190 return (0); /* success */ 2191 } 2192 2193 static usb_error_t 2194 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2195 { 2196 struct xhci_endpoint_ext *pepext; 2197 struct usb_endpoint_ss_comp_descriptor *ecomp; 2198 2199 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2200 xfer->endpoint->edesc); 2201 2202 ecomp = xfer->endpoint->ecomp; 2203 2204 pepext->trb[0].dwTrb3 = 0; /* halt any transfers */ 2205 usb_pc_cpu_flush(pepext->page_cache); 2206 2207 return (xhci_configure_endpoint(xfer->xroot->udev, 2208 xfer->endpoint->edesc, pepext->physaddr, 2209 xfer->interval, xfer->max_packet_count, 2210 (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1, 2211 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2212 xfer->max_frame_size)); 2213 } 2214 2215 static usb_error_t 2216 xhci_configure_device(struct usb_device *udev) 2217 { 2218 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2219 struct usb_page_search buf_inp; 2220 struct usb_page_cache *pcinp; 2221 struct xhci_input_dev_ctx *pinp; 2222 struct usb_device *hubdev; 2223 uint32_t temp; 2224 uint32_t route; 2225 uint32_t rh_port; 2226 uint8_t is_hub; 2227 uint8_t index; 2228 uint8_t depth; 2229 2230 index = udev->controller_slot_id; 2231 2232 DPRINTF("index=%u\n", index); 2233 2234 pcinp = &sc->sc_hw.devs[index].input_pc; 2235 2236 usbd_get_page(pcinp, 0, &buf_inp); 2237 2238 pinp = buf_inp.buffer; 2239 2240 rh_port = 0; 2241 route = 0; 2242 2243 /* figure out route string and root HUB port number */ 2244 2245 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2246 2247 if (hubdev->parent_hub == NULL) 2248 break; 2249 2250 depth = hubdev->parent_hub->depth; 2251 2252 /* 2253 * NOTE: HS/FS/LS devices and the SS root HUB can have 2254 * more than 15 ports 2255 */ 2256 2257 rh_port = hubdev->port_no; 2258 2259 if (depth == 0) 2260 break; 2261 2262 if (rh_port > 15) 2263 rh_port = 15; 2264 2265 if (depth < 6) 2266 route |= rh_port << (4 * (depth - 1)); 2267 } 2268 2269 DPRINTF("Route=0x%08x\n", route); 2270 2271 temp = XHCI_SCTX_0_ROUTE_SET(route); 2272 2273 switch (sc->sc_hw.devs[index].state) { 2274 case XHCI_ST_CONFIGURED: 2275 temp |= XHCI_SCTX_0_CTX_NUM_SET(XHCI_MAX_ENDPOINTS - 1); 2276 break; 2277 default: 2278 temp |= XHCI_SCTX_0_CTX_NUM_SET(1); 2279 break; 2280 } 2281 2282 switch (udev->speed) { 2283 case USB_SPEED_LOW: 2284 temp |= XHCI_SCTX_0_SPEED_SET(2); 2285 if (udev->parent_hs_hub != NULL && 2286 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2287 UDPROTO_HSHUBMTT) { 2288 DPRINTF("Device inherits MTT\n"); 2289 temp |= XHCI_SCTX_0_MTT_SET(1); 2290 } 2291 break; 2292 case USB_SPEED_HIGH: 2293 temp |= XHCI_SCTX_0_SPEED_SET(3); 2294 if (sc->sc_hw.devs[index].nports != 0 && 2295 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2296 DPRINTF("HUB supports MTT\n"); 2297 temp |= XHCI_SCTX_0_MTT_SET(1); 2298 } 2299 break; 2300 case USB_SPEED_FULL: 2301 temp |= XHCI_SCTX_0_SPEED_SET(1); 2302 if (udev->parent_hs_hub != NULL && 2303 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2304 UDPROTO_HSHUBMTT) { 2305 DPRINTF("Device inherits MTT\n"); 2306 temp |= XHCI_SCTX_0_MTT_SET(1); 2307 } 2308 break; 2309 default: 2310 temp |= XHCI_SCTX_0_SPEED_SET(4); 2311 break; 2312 } 2313 2314 is_hub = sc->sc_hw.devs[index].nports != 0 && 2315 (udev->speed == USB_SPEED_SUPER || 2316 udev->speed == USB_SPEED_HIGH); 2317 2318 if (is_hub) 2319 temp |= XHCI_SCTX_0_HUB_SET(1); 2320 2321 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2322 2323 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2324 2325 if (is_hub) { 2326 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2327 sc->sc_hw.devs[index].nports); 2328 } 2329 2330 switch (udev->speed) { 2331 case USB_SPEED_SUPER: 2332 switch (sc->sc_hw.devs[index].state) { 2333 case XHCI_ST_ADDRESSED: 2334 case XHCI_ST_CONFIGURED: 2335 /* enable power save */ 2336 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2337 break; 2338 default: 2339 /* disable power save */ 2340 break; 2341 } 2342 break; 2343 default: 2344 break; 2345 } 2346 2347 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2348 2349 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2350 2351 if (is_hub) { 2352 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2353 sc->sc_hw.devs[index].tt); 2354 } 2355 2356 hubdev = udev->parent_hs_hub; 2357 2358 /* check if we should activate the transaction translator */ 2359 switch (udev->speed) { 2360 case USB_SPEED_FULL: 2361 case USB_SPEED_LOW: 2362 if (hubdev != NULL) { 2363 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2364 hubdev->controller_slot_id); 2365 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2366 udev->hs_port_no); 2367 } 2368 break; 2369 default: 2370 break; 2371 } 2372 2373 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2374 2375 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) | 2376 XHCI_SCTX_3_SLOT_STATE_SET(0); 2377 2378 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2379 2380 #ifdef USB_DEBUG 2381 xhci_dump_device(sc, &pinp->ctx_slot); 2382 #endif 2383 usb_pc_cpu_flush(pcinp); 2384 2385 return (0); /* success */ 2386 } 2387 2388 static usb_error_t 2389 xhci_alloc_device_ext(struct usb_device *udev) 2390 { 2391 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2392 struct usb_page_search buf_dev; 2393 struct usb_page_search buf_ep; 2394 struct xhci_trb *trb; 2395 struct usb_page_cache *pc; 2396 struct usb_page *pg; 2397 uint64_t addr; 2398 uint8_t index; 2399 uint8_t i; 2400 2401 index = udev->controller_slot_id; 2402 2403 pc = &sc->sc_hw.devs[index].device_pc; 2404 pg = &sc->sc_hw.devs[index].device_pg; 2405 2406 /* need to initialize the page cache */ 2407 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2408 2409 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2410 (2 * sizeof(struct xhci_dev_ctx)) : 2411 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2412 goto error; 2413 2414 usbd_get_page(pc, 0, &buf_dev); 2415 2416 pc = &sc->sc_hw.devs[index].input_pc; 2417 pg = &sc->sc_hw.devs[index].input_pg; 2418 2419 /* need to initialize the page cache */ 2420 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2421 2422 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2423 (2 * sizeof(struct xhci_input_dev_ctx)) : 2424 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) 2425 goto error; 2426 2427 pc = &sc->sc_hw.devs[index].endpoint_pc; 2428 pg = &sc->sc_hw.devs[index].endpoint_pg; 2429 2430 /* need to initialize the page cache */ 2431 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2432 2433 if (usb_pc_alloc_mem(pc, pg, sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) 2434 goto error; 2435 2436 /* initialise all endpoint LINK TRBs */ 2437 2438 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2439 2440 /* lookup endpoint TRB ring */ 2441 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2442 2443 /* get TRB pointer */ 2444 trb = buf_ep.buffer; 2445 trb += XHCI_MAX_TRANSFERS - 1; 2446 2447 /* get TRB start address */ 2448 addr = buf_ep.physaddr; 2449 2450 /* create LINK TRB */ 2451 trb->qwTrb0 = htole64(addr); 2452 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2453 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2454 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2455 } 2456 2457 usb_pc_cpu_flush(pc); 2458 2459 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2460 2461 return (0); 2462 2463 error: 2464 xhci_free_device_ext(udev); 2465 2466 return (USB_ERR_NOMEM); 2467 } 2468 2469 static void 2470 xhci_free_device_ext(struct usb_device *udev) 2471 { 2472 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2473 uint8_t index; 2474 2475 index = udev->controller_slot_id; 2476 xhci_set_slot_pointer(sc, index, 0); 2477 2478 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2479 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2480 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2481 } 2482 2483 static struct xhci_endpoint_ext * 2484 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2485 { 2486 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2487 struct xhci_endpoint_ext *pepext; 2488 struct usb_page_cache *pc; 2489 struct usb_page_search buf_ep; 2490 uint8_t epno; 2491 uint8_t index; 2492 2493 epno = edesc->bEndpointAddress; 2494 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2495 epno |= UE_DIR_IN; 2496 2497 epno = XHCI_EPNO2EPID(epno); 2498 2499 index = udev->controller_slot_id; 2500 2501 pc = &sc->sc_hw.devs[index].endpoint_pc; 2502 2503 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep); 2504 2505 pepext = &sc->sc_hw.devs[index].endp[epno]; 2506 pepext->page_cache = pc; 2507 pepext->trb = buf_ep.buffer; 2508 pepext->physaddr = buf_ep.physaddr; 2509 2510 return (pepext); 2511 } 2512 2513 static void 2514 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2515 { 2516 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2517 uint8_t epno; 2518 uint8_t index; 2519 2520 epno = xfer->endpointno; 2521 if (xfer->flags_int.control_xfr) 2522 epno |= UE_DIR_IN; 2523 2524 epno = XHCI_EPNO2EPID(epno); 2525 index = xfer->xroot->udev->controller_slot_id; 2526 2527 if (xfer->xroot->udev->flags.self_suspended == 0) 2528 XWRITE4(sc, door, XHCI_DOORBELL(index), epno | XHCI_DB_SID_SET(0)); 2529 } 2530 2531 static void 2532 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2533 { 2534 struct xhci_endpoint_ext *pepext; 2535 2536 if (xfer->flags_int.bandwidth_reclaimed) { 2537 xfer->flags_int.bandwidth_reclaimed = 0; 2538 2539 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2540 xfer->endpoint->edesc); 2541 2542 pepext->trb_used--; 2543 2544 pepext->xfer[xfer->qh_pos] = NULL; 2545 2546 if (error && pepext->trb_running != 0) { 2547 pepext->trb_halted = 1; 2548 pepext->trb_running = 0; 2549 } 2550 } 2551 } 2552 2553 static usb_error_t 2554 xhci_transfer_insert(struct usb_xfer *xfer) 2555 { 2556 struct xhci_td *td_first; 2557 struct xhci_td *td_last; 2558 struct xhci_endpoint_ext *pepext; 2559 uint64_t addr; 2560 uint8_t i; 2561 uint8_t inext; 2562 uint8_t trb_limit; 2563 2564 DPRINTFN(8, "\n"); 2565 2566 /* check if already inserted */ 2567 if (xfer->flags_int.bandwidth_reclaimed) { 2568 DPRINTFN(8, "Already in schedule\n"); 2569 return (0); 2570 } 2571 2572 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2573 xfer->endpoint->edesc); 2574 2575 td_first = xfer->td_transfer_first; 2576 td_last = xfer->td_transfer_last; 2577 addr = pepext->physaddr; 2578 2579 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2580 case UE_CONTROL: 2581 case UE_INTERRUPT: 2582 /* single buffered */ 2583 trb_limit = 1; 2584 break; 2585 default: 2586 /* multi buffered */ 2587 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2588 break; 2589 } 2590 2591 if (pepext->trb_used >= trb_limit) { 2592 DPRINTFN(8, "Too many TDs queued.\n"); 2593 return (USB_ERR_NOMEM); 2594 } 2595 2596 /* check for stopped condition, after putting transfer on interrupt queue */ 2597 if (pepext->trb_running == 0) { 2598 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2599 2600 DPRINTFN(8, "Not running\n"); 2601 2602 /* start configuration */ 2603 (void)usb_proc_msignal(&sc->sc_config_proc, 2604 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2605 return (0); 2606 } 2607 2608 pepext->trb_used++; 2609 2610 /* get current TRB index */ 2611 i = pepext->trb_index; 2612 2613 /* get next TRB index */ 2614 inext = (i + 1); 2615 2616 /* the last entry of the ring is a hardcoded link TRB */ 2617 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2618 inext = 0; 2619 2620 /* compute terminating return address */ 2621 addr += inext * sizeof(struct xhci_trb); 2622 2623 /* update next pointer of last link TRB */ 2624 td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr); 2625 td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2626 td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2627 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2628 2629 #ifdef USB_DEBUG 2630 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2631 #endif 2632 usb_pc_cpu_flush(td_last->page_cache); 2633 2634 /* write ahead chain end marker */ 2635 2636 pepext->trb[inext].qwTrb0 = 0; 2637 pepext->trb[inext].dwTrb2 = 0; 2638 pepext->trb[inext].dwTrb3 = 0; 2639 2640 /* update next pointer of link TRB */ 2641 2642 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2643 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2644 2645 #ifdef USB_DEBUG 2646 xhci_dump_trb(&pepext->trb[i]); 2647 #endif 2648 usb_pc_cpu_flush(pepext->page_cache); 2649 2650 /* toggle cycle bit which activates the transfer chain */ 2651 2652 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2653 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2654 2655 usb_pc_cpu_flush(pepext->page_cache); 2656 2657 DPRINTF("qh_pos = %u\n", i); 2658 2659 pepext->xfer[i] = xfer; 2660 2661 xfer->qh_pos = i; 2662 2663 xfer->flags_int.bandwidth_reclaimed = 1; 2664 2665 pepext->trb_index = inext; 2666 2667 xhci_endpoint_doorbell(xfer); 2668 2669 return (0); 2670 } 2671 2672 static void 2673 xhci_root_intr(struct xhci_softc *sc) 2674 { 2675 uint16_t i; 2676 2677 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2678 2679 /* clear any old interrupt data */ 2680 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2681 2682 for (i = 1; i <= sc->sc_noport; i++) { 2683 /* pick out CHANGE bits from the status register */ 2684 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2685 XHCI_PS_CSC | XHCI_PS_PEC | 2686 XHCI_PS_OCC | XHCI_PS_WRC | 2687 XHCI_PS_PRC | XHCI_PS_PLC | 2688 XHCI_PS_CEC)) { 2689 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2690 DPRINTF("port %d changed\n", i); 2691 } 2692 } 2693 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2694 sizeof(sc->sc_hub_idata)); 2695 } 2696 2697 /*------------------------------------------------------------------------* 2698 * xhci_device_done - XHCI done handler 2699 * 2700 * NOTE: This function can be called two times in a row on 2701 * the same USB transfer. From close and from interrupt. 2702 *------------------------------------------------------------------------*/ 2703 static void 2704 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2705 { 2706 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2707 xfer, xfer->endpoint, error); 2708 2709 /* remove transfer from HW queue */ 2710 xhci_transfer_remove(xfer, error); 2711 2712 /* dequeue transfer and start next transfer */ 2713 usbd_transfer_done(xfer, error); 2714 } 2715 2716 /*------------------------------------------------------------------------* 2717 * XHCI data transfer support (generic type) 2718 *------------------------------------------------------------------------*/ 2719 static void 2720 xhci_device_generic_open(struct usb_xfer *xfer) 2721 { 2722 if (xfer->flags_int.isochronous_xfr) { 2723 switch (xfer->xroot->udev->speed) { 2724 case USB_SPEED_FULL: 2725 break; 2726 default: 2727 usb_hs_bandwidth_alloc(xfer); 2728 break; 2729 } 2730 } 2731 } 2732 2733 static void 2734 xhci_device_generic_close(struct usb_xfer *xfer) 2735 { 2736 DPRINTF("\n"); 2737 2738 xhci_device_done(xfer, USB_ERR_CANCELLED); 2739 2740 if (xfer->flags_int.isochronous_xfr) { 2741 switch (xfer->xroot->udev->speed) { 2742 case USB_SPEED_FULL: 2743 break; 2744 default: 2745 usb_hs_bandwidth_free(xfer); 2746 break; 2747 } 2748 } 2749 } 2750 2751 static void 2752 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 2753 struct usb_xfer *enter_xfer) 2754 { 2755 struct usb_xfer *xfer; 2756 2757 /* check if there is a current transfer */ 2758 xfer = ep->endpoint_q.curr; 2759 if (xfer == NULL) 2760 return; 2761 2762 /* 2763 * Check if the current transfer is started and then pickup 2764 * the next one, if any. Else wait for next start event due to 2765 * block on failure feature. 2766 */ 2767 if (!xfer->flags_int.bandwidth_reclaimed) 2768 return; 2769 2770 xfer = TAILQ_FIRST(&ep->endpoint_q.head); 2771 if (xfer == NULL) { 2772 /* 2773 * In case of enter we have to consider that the 2774 * transfer is queued by the USB core after the enter 2775 * method is called. 2776 */ 2777 xfer = enter_xfer; 2778 2779 if (xfer == NULL) 2780 return; 2781 } 2782 2783 /* try to multi buffer */ 2784 xhci_transfer_insert(xfer); 2785 } 2786 2787 static void 2788 xhci_device_generic_enter(struct usb_xfer *xfer) 2789 { 2790 DPRINTF("\n"); 2791 2792 /* setup TD's and QH */ 2793 xhci_setup_generic_chain(xfer); 2794 2795 xhci_device_generic_multi_enter(xfer->endpoint, xfer); 2796 } 2797 2798 static void 2799 xhci_device_generic_start(struct usb_xfer *xfer) 2800 { 2801 DPRINTF("\n"); 2802 2803 /* try to insert xfer on HW queue */ 2804 xhci_transfer_insert(xfer); 2805 2806 /* try to multi buffer */ 2807 xhci_device_generic_multi_enter(xfer->endpoint, NULL); 2808 2809 /* add transfer last on interrupt queue */ 2810 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2811 2812 /* start timeout, if any */ 2813 if (xfer->timeout != 0) 2814 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 2815 } 2816 2817 struct usb_pipe_methods xhci_device_generic_methods = 2818 { 2819 .open = xhci_device_generic_open, 2820 .close = xhci_device_generic_close, 2821 .enter = xhci_device_generic_enter, 2822 .start = xhci_device_generic_start, 2823 }; 2824 2825 /*------------------------------------------------------------------------* 2826 * xhci root HUB support 2827 *------------------------------------------------------------------------* 2828 * Simulate a hardware HUB by handling all the necessary requests. 2829 *------------------------------------------------------------------------*/ 2830 2831 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 2832 2833 static const 2834 struct usb_device_descriptor xhci_devd = 2835 { 2836 .bLength = sizeof(xhci_devd), 2837 .bDescriptorType = UDESC_DEVICE, /* type */ 2838 HSETW(.bcdUSB, 0x0300), /* USB version */ 2839 .bDeviceClass = UDCLASS_HUB, /* class */ 2840 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 2841 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 2842 .bMaxPacketSize = 9, /* max packet size */ 2843 HSETW(.idVendor, 0x0000), /* vendor */ 2844 HSETW(.idProduct, 0x0000), /* product */ 2845 HSETW(.bcdDevice, 0x0100), /* device version */ 2846 .iManufacturer = 1, 2847 .iProduct = 2, 2848 .iSerialNumber = 0, 2849 .bNumConfigurations = 1, /* # of configurations */ 2850 }; 2851 2852 static const 2853 struct xhci_bos_desc xhci_bosd = { 2854 .bosd = { 2855 .bLength = sizeof(xhci_bosd.bosd), 2856 .bDescriptorType = UDESC_BOS, 2857 HSETW(.wTotalLength, sizeof(xhci_bosd)), 2858 .bNumDeviceCaps = 3, 2859 }, 2860 .usb2extd = { 2861 .bLength = sizeof(xhci_bosd.usb2extd), 2862 .bDescriptorType = 1, 2863 .bDevCapabilityType = 2, 2864 .bmAttributes[0] = 2, 2865 }, 2866 .usbdcd = { 2867 .bLength = sizeof(xhci_bosd.usbdcd), 2868 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 2869 .bDevCapabilityType = 3, 2870 .bmAttributes = 0, /* XXX */ 2871 HSETW(.wSpeedsSupported, 0x000C), 2872 .bFunctionalitySupport = 8, 2873 .bU1DevExitLat = 255, /* dummy - not used */ 2874 .wU2DevExitLat = { 0x00, 0x08 }, 2875 }, 2876 .cidd = { 2877 .bLength = sizeof(xhci_bosd.cidd), 2878 .bDescriptorType = 1, 2879 .bDevCapabilityType = 4, 2880 .bReserved = 0, 2881 .bContainerID = 0, /* XXX */ 2882 }, 2883 }; 2884 2885 static const 2886 struct xhci_config_desc xhci_confd = { 2887 .confd = { 2888 .bLength = sizeof(xhci_confd.confd), 2889 .bDescriptorType = UDESC_CONFIG, 2890 .wTotalLength[0] = sizeof(xhci_confd), 2891 .bNumInterface = 1, 2892 .bConfigurationValue = 1, 2893 .iConfiguration = 0, 2894 .bmAttributes = UC_SELF_POWERED, 2895 .bMaxPower = 0 /* max power */ 2896 }, 2897 .ifcd = { 2898 .bLength = sizeof(xhci_confd.ifcd), 2899 .bDescriptorType = UDESC_INTERFACE, 2900 .bNumEndpoints = 1, 2901 .bInterfaceClass = UICLASS_HUB, 2902 .bInterfaceSubClass = UISUBCLASS_HUB, 2903 .bInterfaceProtocol = 0, 2904 }, 2905 .endpd = { 2906 .bLength = sizeof(xhci_confd.endpd), 2907 .bDescriptorType = UDESC_ENDPOINT, 2908 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 2909 .bmAttributes = UE_INTERRUPT, 2910 .wMaxPacketSize[0] = 2, /* max 15 ports */ 2911 .bInterval = 255, 2912 }, 2913 .endpcd = { 2914 .bLength = sizeof(xhci_confd.endpcd), 2915 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 2916 .bMaxBurst = 0, 2917 .bmAttributes = 0, 2918 }, 2919 }; 2920 2921 static const 2922 struct usb_hub_ss_descriptor xhci_hubd = { 2923 .bLength = sizeof(xhci_hubd), 2924 .bDescriptorType = UDESC_SS_HUB, 2925 }; 2926 2927 static usb_error_t 2928 xhci_roothub_exec(struct usb_device *udev, 2929 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2930 { 2931 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2932 const char *str_ptr; 2933 const void *ptr; 2934 uint32_t port; 2935 uint32_t v; 2936 uint16_t len; 2937 uint16_t i; 2938 uint16_t value; 2939 uint16_t index; 2940 uint8_t j; 2941 usb_error_t err; 2942 2943 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2944 2945 /* buffer reset */ 2946 ptr = (const void *)&sc->sc_hub_desc; 2947 len = 0; 2948 err = 0; 2949 2950 value = UGETW(req->wValue); 2951 index = UGETW(req->wIndex); 2952 2953 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2954 "wValue=0x%04x wIndex=0x%04x\n", 2955 req->bmRequestType, req->bRequest, 2956 UGETW(req->wLength), value, index); 2957 2958 #define C(x,y) ((x) | ((y) << 8)) 2959 switch (C(req->bRequest, req->bmRequestType)) { 2960 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2961 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2962 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2963 /* 2964 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2965 * for the integrated root hub. 2966 */ 2967 break; 2968 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2969 len = 1; 2970 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2971 break; 2972 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2973 switch (value >> 8) { 2974 case UDESC_DEVICE: 2975 if ((value & 0xff) != 0) { 2976 err = USB_ERR_IOERROR; 2977 goto done; 2978 } 2979 len = sizeof(xhci_devd); 2980 ptr = (const void *)&xhci_devd; 2981 break; 2982 2983 case UDESC_BOS: 2984 if ((value & 0xff) != 0) { 2985 err = USB_ERR_IOERROR; 2986 goto done; 2987 } 2988 len = sizeof(xhci_bosd); 2989 ptr = (const void *)&xhci_bosd; 2990 break; 2991 2992 case UDESC_CONFIG: 2993 if ((value & 0xff) != 0) { 2994 err = USB_ERR_IOERROR; 2995 goto done; 2996 } 2997 len = sizeof(xhci_confd); 2998 ptr = (const void *)&xhci_confd; 2999 break; 3000 3001 case UDESC_STRING: 3002 switch (value & 0xff) { 3003 case 0: /* Language table */ 3004 str_ptr = "\001"; 3005 break; 3006 3007 case 1: /* Vendor */ 3008 str_ptr = sc->sc_vendor; 3009 break; 3010 3011 case 2: /* Product */ 3012 str_ptr = "XHCI root HUB"; 3013 break; 3014 3015 default: 3016 str_ptr = ""; 3017 break; 3018 } 3019 3020 len = usb_make_str_desc( 3021 sc->sc_hub_desc.temp, 3022 sizeof(sc->sc_hub_desc.temp), 3023 str_ptr); 3024 break; 3025 3026 default: 3027 err = USB_ERR_IOERROR; 3028 goto done; 3029 } 3030 break; 3031 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3032 len = 1; 3033 sc->sc_hub_desc.temp[0] = 0; 3034 break; 3035 case C(UR_GET_STATUS, UT_READ_DEVICE): 3036 len = 2; 3037 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3038 break; 3039 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3040 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3041 len = 2; 3042 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3043 break; 3044 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3045 if (value >= XHCI_MAX_DEVICES) { 3046 err = USB_ERR_IOERROR; 3047 goto done; 3048 } 3049 break; 3050 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3051 if (value != 0 && value != 1) { 3052 err = USB_ERR_IOERROR; 3053 goto done; 3054 } 3055 sc->sc_conf = value; 3056 break; 3057 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3058 break; 3059 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3060 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3061 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3062 err = USB_ERR_IOERROR; 3063 goto done; 3064 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3065 break; 3066 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3067 break; 3068 /* Hub requests */ 3069 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3070 break; 3071 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3072 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3073 3074 if ((index < 1) || 3075 (index > sc->sc_noport)) { 3076 err = USB_ERR_IOERROR; 3077 goto done; 3078 } 3079 port = XHCI_PORTSC(index); 3080 3081 v = XREAD4(sc, oper, port); 3082 i = XHCI_PS_PLS_GET(v); 3083 v &= ~XHCI_PS_CLEAR; 3084 3085 switch (value) { 3086 case UHF_C_BH_PORT_RESET: 3087 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3088 break; 3089 case UHF_C_PORT_CONFIG_ERROR: 3090 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3091 break; 3092 case UHF_C_PORT_SUSPEND: 3093 case UHF_C_PORT_LINK_STATE: 3094 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3095 break; 3096 case UHF_C_PORT_CONNECTION: 3097 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3098 break; 3099 case UHF_C_PORT_ENABLE: 3100 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3101 break; 3102 case UHF_C_PORT_OVER_CURRENT: 3103 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3104 break; 3105 case UHF_C_PORT_RESET: 3106 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3107 break; 3108 case UHF_PORT_ENABLE: 3109 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3110 break; 3111 case UHF_PORT_POWER: 3112 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3113 break; 3114 case UHF_PORT_INDICATOR: 3115 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3116 break; 3117 case UHF_PORT_SUSPEND: 3118 3119 /* U3 -> U15 */ 3120 if (i == 3) { 3121 XWRITE4(sc, oper, port, v | 3122 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3123 } 3124 3125 /* wait 20ms for resume sequence to complete */ 3126 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3127 3128 /* U0 */ 3129 XWRITE4(sc, oper, port, v | 3130 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3131 break; 3132 default: 3133 err = USB_ERR_IOERROR; 3134 goto done; 3135 } 3136 break; 3137 3138 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3139 if ((value & 0xff) != 0) { 3140 err = USB_ERR_IOERROR; 3141 goto done; 3142 } 3143 3144 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3145 3146 sc->sc_hub_desc.hubd = xhci_hubd; 3147 3148 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3149 3150 if (XHCI_HCS0_PPC(v)) 3151 i = UHD_PWR_INDIVIDUAL; 3152 else 3153 i = UHD_PWR_GANGED; 3154 3155 if (XHCI_HCS0_PIND(v)) 3156 i |= UHD_PORT_IND; 3157 3158 i |= UHD_OC_INDIVIDUAL; 3159 3160 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3161 3162 /* see XHCI section 5.4.9: */ 3163 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3164 3165 for (j = 1; j <= sc->sc_noport; j++) { 3166 3167 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3168 if (v & XHCI_PS_DR) { 3169 sc->sc_hub_desc.hubd. 3170 DeviceRemovable[j / 8] |= 1U << (j % 8); 3171 } 3172 } 3173 len = sc->sc_hub_desc.hubd.bLength; 3174 break; 3175 3176 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3177 len = 16; 3178 memset(sc->sc_hub_desc.temp, 0, 16); 3179 break; 3180 3181 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3182 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3183 3184 if ((index < 1) || 3185 (index > sc->sc_noport)) { 3186 err = USB_ERR_IOERROR; 3187 goto done; 3188 } 3189 3190 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3191 3192 DPRINTFN(9, "port status=0x%08x\n", v); 3193 3194 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3195 3196 switch (XHCI_PS_SPEED_GET(v)) { 3197 case 3: 3198 i |= UPS_HIGH_SPEED; 3199 break; 3200 case 2: 3201 i |= UPS_LOW_SPEED; 3202 break; 3203 case 1: 3204 /* FULL speed */ 3205 break; 3206 default: 3207 i |= UPS_OTHER_SPEED; 3208 break; 3209 } 3210 3211 if (v & XHCI_PS_CCS) 3212 i |= UPS_CURRENT_CONNECT_STATUS; 3213 if (v & XHCI_PS_PED) 3214 i |= UPS_PORT_ENABLED; 3215 if (v & XHCI_PS_OCA) 3216 i |= UPS_OVERCURRENT_INDICATOR; 3217 if (v & XHCI_PS_PR) 3218 i |= UPS_RESET; 3219 if (v & XHCI_PS_PP) { 3220 /* 3221 * The USB 3.0 RH is using the 3222 * USB 2.0's power bit 3223 */ 3224 i |= UPS_PORT_POWER; 3225 } 3226 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3227 3228 i = 0; 3229 if (v & XHCI_PS_CSC) 3230 i |= UPS_C_CONNECT_STATUS; 3231 if (v & XHCI_PS_PEC) 3232 i |= UPS_C_PORT_ENABLED; 3233 if (v & XHCI_PS_OCC) 3234 i |= UPS_C_OVERCURRENT_INDICATOR; 3235 if (v & XHCI_PS_WRC) 3236 i |= UPS_C_BH_PORT_RESET; 3237 if (v & XHCI_PS_PRC) 3238 i |= UPS_C_PORT_RESET; 3239 if (v & XHCI_PS_PLC) 3240 i |= UPS_C_PORT_LINK_STATE; 3241 if (v & XHCI_PS_CEC) 3242 i |= UPS_C_PORT_CONFIG_ERROR; 3243 3244 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3245 len = sizeof(sc->sc_hub_desc.ps); 3246 break; 3247 3248 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3249 err = USB_ERR_IOERROR; 3250 goto done; 3251 3252 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3253 break; 3254 3255 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3256 3257 i = index >> 8; 3258 index &= 0x00FF; 3259 3260 if ((index < 1) || 3261 (index > sc->sc_noport)) { 3262 err = USB_ERR_IOERROR; 3263 goto done; 3264 } 3265 3266 port = XHCI_PORTSC(index); 3267 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3268 3269 switch (value) { 3270 case UHF_PORT_U1_TIMEOUT: 3271 if (XHCI_PS_SPEED_GET(v) != 4) { 3272 err = USB_ERR_IOERROR; 3273 goto done; 3274 } 3275 port = XHCI_PORTPMSC(index); 3276 v = XREAD4(sc, oper, port); 3277 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3278 v |= XHCI_PM3_U1TO_SET(i); 3279 XWRITE4(sc, oper, port, v); 3280 break; 3281 case UHF_PORT_U2_TIMEOUT: 3282 if (XHCI_PS_SPEED_GET(v) != 4) { 3283 err = USB_ERR_IOERROR; 3284 goto done; 3285 } 3286 port = XHCI_PORTPMSC(index); 3287 v = XREAD4(sc, oper, port); 3288 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3289 v |= XHCI_PM3_U2TO_SET(i); 3290 XWRITE4(sc, oper, port, v); 3291 break; 3292 case UHF_BH_PORT_RESET: 3293 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3294 break; 3295 case UHF_PORT_LINK_STATE: 3296 XWRITE4(sc, oper, port, v | 3297 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3298 /* 4ms settle time */ 3299 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3300 break; 3301 case UHF_PORT_ENABLE: 3302 DPRINTFN(3, "set port enable %d\n", index); 3303 break; 3304 case UHF_PORT_SUSPEND: 3305 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3306 j = XHCI_PS_SPEED_GET(v); 3307 if ((j < 1) || (j > 3)) { 3308 /* non-supported speed */ 3309 err = USB_ERR_IOERROR; 3310 goto done; 3311 } 3312 XWRITE4(sc, oper, port, v | 3313 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3314 break; 3315 case UHF_PORT_RESET: 3316 DPRINTFN(6, "reset port %d\n", index); 3317 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3318 break; 3319 case UHF_PORT_POWER: 3320 DPRINTFN(3, "set port power %d\n", index); 3321 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3322 break; 3323 case UHF_PORT_TEST: 3324 DPRINTFN(3, "set port test %d\n", index); 3325 break; 3326 case UHF_PORT_INDICATOR: 3327 DPRINTFN(3, "set port indicator %d\n", index); 3328 3329 v &= ~XHCI_PS_PIC_SET(3); 3330 v |= XHCI_PS_PIC_SET(1); 3331 3332 XWRITE4(sc, oper, port, v); 3333 break; 3334 default: 3335 err = USB_ERR_IOERROR; 3336 goto done; 3337 } 3338 break; 3339 3340 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3341 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3342 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3343 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3344 break; 3345 default: 3346 err = USB_ERR_IOERROR; 3347 goto done; 3348 } 3349 done: 3350 *plength = len; 3351 *pptr = ptr; 3352 return (err); 3353 } 3354 3355 static void 3356 xhci_xfer_setup(struct usb_setup_params *parm) 3357 { 3358 struct usb_page_search page_info; 3359 struct usb_page_cache *pc; 3360 struct xhci_softc *sc; 3361 struct usb_xfer *xfer; 3362 void *last_obj; 3363 uint32_t ntd; 3364 uint32_t n; 3365 3366 sc = XHCI_BUS2SC(parm->udev->bus); 3367 xfer = parm->curr_xfer; 3368 3369 /* 3370 * The proof for the "ntd" formula is illustrated like this: 3371 * 3372 * +------------------------------------+ 3373 * | | 3374 * | |remainder -> | 3375 * | +-----+---+ | 3376 * | | xxx | x | frm 0 | 3377 * | +-----+---++ | 3378 * | | xxx | xx | frm 1 | 3379 * | +-----+----+ | 3380 * | ... | 3381 * +------------------------------------+ 3382 * 3383 * "xxx" means a completely full USB transfer descriptor 3384 * 3385 * "x" and "xx" means a short USB packet 3386 * 3387 * For the remainder of an USB transfer modulo 3388 * "max_data_length" we need two USB transfer descriptors. 3389 * One to transfer the remaining data and one to finalise with 3390 * a zero length packet in case the "force_short_xfer" flag is 3391 * set. We only need two USB transfer descriptors in the case 3392 * where the transfer length of the first one is a factor of 3393 * "max_frame_size". The rest of the needed USB transfer 3394 * descriptors is given by the buffer size divided by the 3395 * maximum data payload. 3396 */ 3397 parm->hc_max_packet_size = 0x400; 3398 parm->hc_max_packet_count = 16 * 3; 3399 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3400 3401 xfer->flags_int.bdma_enable = 1; 3402 3403 usbd_transfer_setup_sub(parm); 3404 3405 if (xfer->flags_int.isochronous_xfr) { 3406 ntd = ((1 * xfer->nframes) 3407 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3408 } else if (xfer->flags_int.control_xfr) { 3409 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3410 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3411 } else { 3412 ntd = ((2 * xfer->nframes) 3413 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3414 } 3415 3416 alloc_dma_set: 3417 3418 if (parm->err) 3419 return; 3420 3421 /* 3422 * Allocate queue heads and transfer descriptors 3423 */ 3424 last_obj = NULL; 3425 3426 if (usbd_transfer_setup_sub_malloc( 3427 parm, &pc, sizeof(struct xhci_td), 3428 XHCI_TD_ALIGN, ntd)) { 3429 parm->err = USB_ERR_NOMEM; 3430 return; 3431 } 3432 if (parm->buf) { 3433 for (n = 0; n != ntd; n++) { 3434 struct xhci_td *td; 3435 3436 usbd_get_page(pc + n, 0, &page_info); 3437 3438 td = page_info.buffer; 3439 3440 /* init TD */ 3441 td->td_self = page_info.physaddr; 3442 td->obj_next = last_obj; 3443 td->page_cache = pc + n; 3444 3445 last_obj = td; 3446 3447 usb_pc_cpu_flush(pc + n); 3448 } 3449 } 3450 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3451 3452 if (!xfer->flags_int.curr_dma_set) { 3453 xfer->flags_int.curr_dma_set = 1; 3454 goto alloc_dma_set; 3455 } 3456 } 3457 3458 static usb_error_t 3459 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3460 { 3461 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3462 struct usb_page_search buf_inp; 3463 struct usb_device *udev; 3464 struct xhci_endpoint_ext *pepext; 3465 struct usb_endpoint_descriptor *edesc; 3466 struct usb_page_cache *pcinp; 3467 usb_error_t err; 3468 uint8_t index; 3469 uint8_t epno; 3470 3471 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3472 xfer->endpoint->edesc); 3473 3474 udev = xfer->xroot->udev; 3475 index = udev->controller_slot_id; 3476 3477 pcinp = &sc->sc_hw.devs[index].input_pc; 3478 3479 usbd_get_page(pcinp, 0, &buf_inp); 3480 3481 edesc = xfer->endpoint->edesc; 3482 3483 epno = edesc->bEndpointAddress; 3484 3485 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3486 epno |= UE_DIR_IN; 3487 3488 epno = XHCI_EPNO2EPID(epno); 3489 3490 if (epno == 0) 3491 return (USB_ERR_NO_PIPE); /* invalid */ 3492 3493 XHCI_CMD_LOCK(sc); 3494 3495 /* configure endpoint */ 3496 3497 err = xhci_configure_endpoint_by_xfer(xfer); 3498 3499 if (err != 0) { 3500 XHCI_CMD_UNLOCK(sc); 3501 return (err); 3502 } 3503 3504 /* 3505 * Get the endpoint into the stopped state according to the 3506 * endpoint context state diagram in the XHCI specification: 3507 */ 3508 3509 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3510 3511 if (err != 0) 3512 DPRINTF("Could not stop endpoint %u\n", epno); 3513 3514 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3515 3516 if (err != 0) 3517 DPRINTF("Could not reset endpoint %u\n", epno); 3518 3519 err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr | 3520 XHCI_EPCTX_2_DCS_SET(1), 0, epno, index); 3521 3522 if (err != 0) 3523 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3524 3525 /* 3526 * Get the endpoint into the running state according to the 3527 * endpoint context state diagram in the XHCI specification: 3528 */ 3529 3530 xhci_configure_mask(udev, 1U << epno, 0); 3531 3532 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3533 3534 if (err != 0) 3535 DPRINTF("Could not configure endpoint %u\n", epno); 3536 3537 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3538 3539 if (err != 0) 3540 DPRINTF("Could not configure endpoint %u\n", epno); 3541 3542 XHCI_CMD_UNLOCK(sc); 3543 3544 return (0); 3545 } 3546 3547 static void 3548 xhci_xfer_unsetup(struct usb_xfer *xfer) 3549 { 3550 return; 3551 } 3552 3553 static void 3554 xhci_start_dma_delay(struct usb_xfer *xfer) 3555 { 3556 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3557 3558 /* put transfer on interrupt queue (again) */ 3559 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3560 3561 (void)usb_proc_msignal(&sc->sc_config_proc, 3562 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3563 } 3564 3565 static void 3566 xhci_configure_msg(struct usb_proc_msg *pm) 3567 { 3568 struct xhci_softc *sc; 3569 struct xhci_endpoint_ext *pepext; 3570 struct usb_xfer *xfer; 3571 3572 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3573 3574 restart: 3575 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3576 3577 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3578 xfer->endpoint->edesc); 3579 3580 if ((pepext->trb_halted != 0) || 3581 (pepext->trb_running == 0)) { 3582 3583 uint8_t i; 3584 3585 /* clear halted and running */ 3586 pepext->trb_halted = 0; 3587 pepext->trb_running = 0; 3588 3589 /* nuke remaining buffered transfers */ 3590 3591 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 3592 /* 3593 * NOTE: We need to use the timeout 3594 * error code here else existing 3595 * isochronous clients can get 3596 * confused: 3597 */ 3598 if (pepext->xfer[i] != NULL) { 3599 xhci_device_done(pepext->xfer[i], 3600 USB_ERR_TIMEOUT); 3601 } 3602 } 3603 3604 /* 3605 * NOTE: The USB transfer cannot vanish in 3606 * this state! 3607 */ 3608 3609 USB_BUS_UNLOCK(&sc->sc_bus); 3610 3611 xhci_configure_reset_endpoint(xfer); 3612 3613 USB_BUS_LOCK(&sc->sc_bus); 3614 3615 /* check if halted is still cleared */ 3616 if (pepext->trb_halted == 0) { 3617 pepext->trb_running = 1; 3618 pepext->trb_index = 0; 3619 } 3620 goto restart; 3621 } 3622 3623 if (xfer->flags_int.did_dma_delay) { 3624 3625 /* remove transfer from interrupt queue (again) */ 3626 usbd_transfer_dequeue(xfer); 3627 3628 /* we are finally done */ 3629 usb_dma_delay_done_cb(xfer); 3630 3631 /* queue changed - restart */ 3632 goto restart; 3633 } 3634 } 3635 3636 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3637 3638 /* try to insert xfer on HW queue */ 3639 xhci_transfer_insert(xfer); 3640 3641 /* try to multi buffer */ 3642 xhci_device_generic_multi_enter(xfer->endpoint, NULL); 3643 } 3644 } 3645 3646 static void 3647 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3648 struct usb_endpoint *ep) 3649 { 3650 struct xhci_endpoint_ext *pepext; 3651 3652 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3653 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3654 3655 if (udev->flags.usb_mode != USB_MODE_HOST) { 3656 /* not supported */ 3657 return; 3658 } 3659 if (udev->parent_hub == NULL) { 3660 /* root HUB has special endpoint handling */ 3661 return; 3662 } 3663 3664 ep->methods = &xhci_device_generic_methods; 3665 3666 pepext = xhci_get_endpoint_ext(udev, edesc); 3667 3668 USB_BUS_LOCK(udev->bus); 3669 pepext->trb_halted = 1; 3670 pepext->trb_running = 0; 3671 USB_BUS_UNLOCK(udev->bus); 3672 } 3673 3674 static void 3675 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3676 { 3677 3678 } 3679 3680 static void 3681 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3682 { 3683 struct xhci_endpoint_ext *pepext; 3684 3685 DPRINTF("\n"); 3686 3687 if (udev->flags.usb_mode != USB_MODE_HOST) { 3688 /* not supported */ 3689 return; 3690 } 3691 if (udev->parent_hub == NULL) { 3692 /* root HUB has special endpoint handling */ 3693 return; 3694 } 3695 3696 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3697 3698 USB_BUS_LOCK(udev->bus); 3699 pepext->trb_halted = 1; 3700 pepext->trb_running = 0; 3701 USB_BUS_UNLOCK(udev->bus); 3702 } 3703 3704 static usb_error_t 3705 xhci_device_init(struct usb_device *udev) 3706 { 3707 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3708 usb_error_t err; 3709 uint8_t temp; 3710 3711 /* no init for root HUB */ 3712 if (udev->parent_hub == NULL) 3713 return (0); 3714 3715 XHCI_CMD_LOCK(sc); 3716 3717 /* set invalid default */ 3718 3719 udev->controller_slot_id = sc->sc_noslot + 1; 3720 3721 /* try to get a new slot ID from the XHCI */ 3722 3723 err = xhci_cmd_enable_slot(sc, &temp); 3724 3725 if (err) { 3726 XHCI_CMD_UNLOCK(sc); 3727 return (err); 3728 } 3729 3730 if (temp > sc->sc_noslot) { 3731 XHCI_CMD_UNLOCK(sc); 3732 return (USB_ERR_BAD_ADDRESS); 3733 } 3734 3735 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 3736 DPRINTF("slot %u already allocated.\n", temp); 3737 XHCI_CMD_UNLOCK(sc); 3738 return (USB_ERR_BAD_ADDRESS); 3739 } 3740 3741 /* store slot ID for later reference */ 3742 3743 udev->controller_slot_id = temp; 3744 3745 /* reset data structure */ 3746 3747 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 3748 3749 /* set mark slot allocated */ 3750 3751 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 3752 3753 err = xhci_alloc_device_ext(udev); 3754 3755 XHCI_CMD_UNLOCK(sc); 3756 3757 /* get device into default state */ 3758 3759 if (err == 0) 3760 err = xhci_set_address(udev, NULL, 0); 3761 3762 return (err); 3763 } 3764 3765 static void 3766 xhci_device_uninit(struct usb_device *udev) 3767 { 3768 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3769 uint8_t index; 3770 3771 /* no init for root HUB */ 3772 if (udev->parent_hub == NULL) 3773 return; 3774 3775 XHCI_CMD_LOCK(sc); 3776 3777 index = udev->controller_slot_id; 3778 3779 if (index <= sc->sc_noslot) { 3780 xhci_cmd_disable_slot(sc, index); 3781 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 3782 3783 /* free device extension */ 3784 xhci_free_device_ext(udev); 3785 } 3786 3787 XHCI_CMD_UNLOCK(sc); 3788 } 3789 3790 static void 3791 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3792 { 3793 /* 3794 * Wait until the hardware has finished any possible use of 3795 * the transfer descriptor(s) 3796 */ 3797 *pus = 2048; /* microseconds */ 3798 } 3799 3800 static void 3801 xhci_device_resume(struct usb_device *udev) 3802 { 3803 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3804 uint8_t index; 3805 uint8_t n; 3806 3807 DPRINTF("\n"); 3808 3809 /* check for root HUB */ 3810 if (udev->parent_hub == NULL) 3811 return; 3812 3813 index = udev->controller_slot_id; 3814 3815 XHCI_CMD_LOCK(sc); 3816 3817 /* blindly resume all endpoints */ 3818 3819 USB_BUS_LOCK(udev->bus); 3820 3821 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) 3822 XWRITE4(sc, door, XHCI_DOORBELL(index), n | XHCI_DB_SID_SET(0)); 3823 3824 USB_BUS_UNLOCK(udev->bus); 3825 3826 XHCI_CMD_UNLOCK(sc); 3827 } 3828 3829 static void 3830 xhci_device_suspend(struct usb_device *udev) 3831 { 3832 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3833 uint8_t index; 3834 uint8_t n; 3835 usb_error_t err; 3836 3837 DPRINTF("\n"); 3838 3839 /* check for root HUB */ 3840 if (udev->parent_hub == NULL) 3841 return; 3842 3843 index = udev->controller_slot_id; 3844 3845 XHCI_CMD_LOCK(sc); 3846 3847 /* blindly suspend all endpoints */ 3848 3849 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3850 err = xhci_cmd_stop_ep(sc, 1, n, index); 3851 if (err != 0) { 3852 DPRINTF("Failed to suspend endpoint " 3853 "%u on slot %u (ignored).\n", n, index); 3854 } 3855 } 3856 3857 XHCI_CMD_UNLOCK(sc); 3858 } 3859 3860 static void 3861 xhci_set_hw_power(struct usb_bus *bus) 3862 { 3863 DPRINTF("\n"); 3864 } 3865 3866 static void 3867 xhci_device_state_change(struct usb_device *udev) 3868 { 3869 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3870 struct usb_page_search buf_inp; 3871 usb_error_t err; 3872 uint8_t index; 3873 3874 /* check for root HUB */ 3875 if (udev->parent_hub == NULL) 3876 return; 3877 3878 index = udev->controller_slot_id; 3879 3880 DPRINTF("\n"); 3881 3882 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 3883 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 3884 &sc->sc_hw.devs[index].tt); 3885 if (err != 0) 3886 sc->sc_hw.devs[index].nports = 0; 3887 } 3888 3889 XHCI_CMD_LOCK(sc); 3890 3891 switch (usb_get_device_state(udev)) { 3892 case USB_STATE_POWERED: 3893 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 3894 break; 3895 3896 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 3897 3898 err = xhci_cmd_reset_dev(sc, index); 3899 3900 if (err != 0) { 3901 DPRINTF("Device reset failed " 3902 "for slot %u.\n", index); 3903 } 3904 break; 3905 3906 case USB_STATE_ADDRESSED: 3907 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 3908 break; 3909 3910 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 3911 3912 err = xhci_cmd_configure_ep(sc, 0, 1, index); 3913 3914 if (err) { 3915 DPRINTF("Failed to deconfigure " 3916 "slot %u.\n", index); 3917 } 3918 break; 3919 3920 case USB_STATE_CONFIGURED: 3921 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 3922 break; 3923 3924 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 3925 3926 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 3927 3928 xhci_configure_mask(udev, 1, 0); 3929 3930 err = xhci_configure_device(udev); 3931 if (err != 0) { 3932 DPRINTF("Could not configure device " 3933 "at slot %u.\n", index); 3934 } 3935 3936 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3937 if (err != 0) { 3938 DPRINTF("Could not evaluate device " 3939 "context at slot %u.\n", index); 3940 } 3941 break; 3942 3943 default: 3944 break; 3945 } 3946 XHCI_CMD_UNLOCK(sc); 3947 } 3948 3949 struct usb_bus_methods xhci_bus_methods = { 3950 .endpoint_init = xhci_ep_init, 3951 .endpoint_uninit = xhci_ep_uninit, 3952 .xfer_setup = xhci_xfer_setup, 3953 .xfer_unsetup = xhci_xfer_unsetup, 3954 .get_dma_delay = xhci_get_dma_delay, 3955 .device_init = xhci_device_init, 3956 .device_uninit = xhci_device_uninit, 3957 .device_resume = xhci_device_resume, 3958 .device_suspend = xhci_device_suspend, 3959 .set_hw_power = xhci_set_hw_power, 3960 .roothub_exec = xhci_roothub_exec, 3961 .xfer_poll = xhci_do_poll, 3962 .start_dma_delay = xhci_start_dma_delay, 3963 .set_address = xhci_set_address, 3964 .clear_stall = xhci_ep_clear_stall, 3965 .device_state_change = xhci_device_state_change, 3966 .set_hw_power_sleep = xhci_set_hw_power_sleep, 3967 }; 3968