1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36 /* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43 #ifdef USB_GLOBAL_INCLUDE_FILE 44 #include USB_GLOBAL_INCLUDE_FILE 45 #else 46 #include <sys/stdint.h> 47 #include <sys/stddef.h> 48 #include <sys/param.h> 49 #include <sys/queue.h> 50 #include <sys/types.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/bus.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/condvar.h> 58 #include <sys/sysctl.h> 59 #include <sys/sx.h> 60 #include <sys/unistd.h> 61 #include <sys/callout.h> 62 #include <sys/malloc.h> 63 #include <sys/priv.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 68 #define USB_DEBUG_VAR xhcidebug 69 70 #include <dev/usb/usb_core.h> 71 #include <dev/usb/usb_debug.h> 72 #include <dev/usb/usb_busdma.h> 73 #include <dev/usb/usb_process.h> 74 #include <dev/usb/usb_transfer.h> 75 #include <dev/usb/usb_device.h> 76 #include <dev/usb/usb_hub.h> 77 #include <dev/usb/usb_util.h> 78 79 #include <dev/usb/usb_controller.h> 80 #include <dev/usb/usb_bus.h> 81 #endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83 #include <dev/usb/controller/xhci.h> 84 #include <dev/usb/controller/xhcireg.h> 85 86 #define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 92 static int xhcistreams; 93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN, 94 &xhcistreams, 0, "Set to enable streams mode support"); 95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams); 96 97 #ifdef USB_DEBUG 98 static int xhcidebug; 99 static int xhciroute; 100 static int xhcipolling; 101 102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 103 &xhcidebug, 0, "Debug level"); 104 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN, 106 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 107 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN, 109 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller"); 110 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling); 111 #endif 112 113 #define XHCI_INTR_ENDPT 1 114 115 struct xhci_std_temp { 116 struct xhci_softc *sc; 117 struct usb_page_cache *pc; 118 struct xhci_td *td; 119 struct xhci_td *td_next; 120 uint32_t len; 121 uint32_t offset; 122 uint32_t max_packet_size; 123 uint32_t average; 124 uint16_t isoc_delta; 125 uint16_t isoc_frame; 126 uint8_t shortpkt; 127 uint8_t multishort; 128 uint8_t last_frame; 129 uint8_t trb_type; 130 uint8_t direction; 131 uint8_t tbc; 132 uint8_t tlbpc; 133 uint8_t step_td; 134 uint8_t do_isoc_sync; 135 }; 136 137 static void xhci_do_poll(struct usb_bus *); 138 static void xhci_device_done(struct usb_xfer *, usb_error_t); 139 static void xhci_root_intr(struct xhci_softc *); 140 static void xhci_free_device_ext(struct usb_device *); 141 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 142 struct usb_endpoint_descriptor *); 143 static usb_proc_callback_t xhci_configure_msg; 144 static usb_error_t xhci_configure_device(struct usb_device *); 145 static usb_error_t xhci_configure_endpoint(struct usb_device *, 146 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 147 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 148 uint8_t); 149 static usb_error_t xhci_configure_mask(struct usb_device *, 150 uint32_t, uint8_t); 151 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 152 uint64_t, uint8_t); 153 static void xhci_endpoint_doorbell(struct usb_xfer *); 154 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 155 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 156 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 157 #ifdef USB_DEBUG 158 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 159 #endif 160 161 extern struct usb_bus_methods xhci_bus_methods; 162 163 #ifdef USB_DEBUG 164 static void 165 xhci_dump_trb(struct xhci_trb *trb) 166 { 167 DPRINTFN(5, "trb = %p\n", trb); 168 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 169 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 170 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 171 } 172 173 static void 174 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 175 { 176 DPRINTFN(5, "pep = %p\n", pep); 177 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 178 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 179 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 180 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 181 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 182 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 183 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 184 } 185 186 static void 187 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 188 { 189 DPRINTFN(5, "psl = %p\n", psl); 190 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 191 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 192 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 193 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 194 } 195 #endif 196 197 uint32_t 198 xhci_get_port_route(void) 199 { 200 #ifdef USB_DEBUG 201 return (0xFFFFFFFFU ^ ((uint32_t)xhciroute)); 202 #else 203 return (0xFFFFFFFFU); 204 #endif 205 } 206 207 uint8_t 208 xhci_use_polling(void) 209 { 210 #ifdef USB_DEBUG 211 return (xhcipolling != 0); 212 #else 213 return (0); 214 #endif 215 } 216 217 static void 218 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 219 { 220 struct xhci_softc *sc = XHCI_BUS2SC(bus); 221 uint8_t i; 222 223 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 224 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 225 226 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 227 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 228 229 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 230 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 231 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 232 } 233 } 234 235 static void 236 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 237 { 238 if (sc->sc_ctx_is_64_byte) { 239 uint32_t offset; 240 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 241 /* all contexts are initially 32-bytes */ 242 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 243 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 244 } 245 *ptr = htole32(val); 246 } 247 248 static uint32_t 249 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 250 { 251 if (sc->sc_ctx_is_64_byte) { 252 uint32_t offset; 253 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 254 /* all contexts are initially 32-bytes */ 255 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 256 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 257 } 258 return (le32toh(*ptr)); 259 } 260 261 static void 262 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 263 { 264 if (sc->sc_ctx_is_64_byte) { 265 uint32_t offset; 266 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 267 /* all contexts are initially 32-bytes */ 268 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 269 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 270 } 271 *ptr = htole64(val); 272 } 273 274 #ifdef USB_DEBUG 275 static uint64_t 276 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 277 { 278 if (sc->sc_ctx_is_64_byte) { 279 uint32_t offset; 280 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 281 /* all contexts are initially 32-bytes */ 282 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 283 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 284 } 285 return (le64toh(*ptr)); 286 } 287 #endif 288 289 usb_error_t 290 xhci_start_controller(struct xhci_softc *sc) 291 { 292 struct usb_page_search buf_res; 293 struct xhci_hw_root *phwr; 294 struct xhci_dev_ctx_addr *pdctxa; 295 uint64_t addr; 296 uint32_t temp; 297 uint16_t i; 298 299 DPRINTF("\n"); 300 301 sc->sc_capa_off = 0; 302 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 303 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 304 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 305 306 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 307 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 308 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 309 310 sc->sc_event_ccs = 1; 311 sc->sc_event_idx = 0; 312 sc->sc_command_ccs = 1; 313 sc->sc_command_idx = 0; 314 315 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 316 317 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 318 319 DPRINTF("HCS0 = 0x%08x\n", temp); 320 321 if (XHCI_HCS0_CSZ(temp)) { 322 sc->sc_ctx_is_64_byte = 1; 323 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 324 } else { 325 sc->sc_ctx_is_64_byte = 0; 326 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 327 } 328 329 /* Reset controller */ 330 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 331 332 for (i = 0; i != 100; i++) { 333 usb_pause_mtx(NULL, hz / 100); 334 temp = XREAD4(sc, oper, XHCI_USBCMD) & 335 (XHCI_CMD_HCRST | XHCI_STS_CNR); 336 if (!temp) 337 break; 338 } 339 340 if (temp) { 341 device_printf(sc->sc_bus.parent, "Controller " 342 "reset timeout.\n"); 343 return (USB_ERR_IOERROR); 344 } 345 346 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 347 device_printf(sc->sc_bus.parent, "Controller does " 348 "not support 4K page size.\n"); 349 return (USB_ERR_IOERROR); 350 } 351 352 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 353 354 i = XHCI_HCS1_N_PORTS(temp); 355 356 if (i == 0) { 357 device_printf(sc->sc_bus.parent, "Invalid number " 358 "of ports: %u\n", i); 359 return (USB_ERR_IOERROR); 360 } 361 362 sc->sc_noport = i; 363 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 364 365 if (sc->sc_noslot > XHCI_MAX_DEVICES) 366 sc->sc_noslot = XHCI_MAX_DEVICES; 367 368 /* setup number of device slots */ 369 370 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 371 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 372 373 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 374 375 DPRINTF("Max slots: %u\n", sc->sc_noslot); 376 377 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 378 379 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 380 381 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 382 device_printf(sc->sc_bus.parent, "XHCI request " 383 "too many scratchpads\n"); 384 return (USB_ERR_NOMEM); 385 } 386 387 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 388 389 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 390 391 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 392 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 393 394 temp = XREAD4(sc, oper, XHCI_USBSTS); 395 396 /* clear interrupts */ 397 XWRITE4(sc, oper, XHCI_USBSTS, temp); 398 /* disable all device notifications */ 399 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 400 401 /* setup device context base address */ 402 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 403 pdctxa = buf_res.buffer; 404 memset(pdctxa, 0, sizeof(*pdctxa)); 405 406 addr = buf_res.physaddr; 407 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 408 409 /* slot 0 points to the table of scratchpad pointers */ 410 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 411 412 for (i = 0; i != sc->sc_noscratch; i++) { 413 struct usb_page_search buf_scp; 414 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 415 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 416 } 417 418 addr = buf_res.physaddr; 419 420 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 421 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 422 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 423 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 424 425 /* Setup event table size */ 426 427 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 428 429 DPRINTF("HCS2=0x%08x\n", temp); 430 431 temp = XHCI_HCS2_ERST_MAX(temp); 432 temp = 1U << temp; 433 if (temp > XHCI_MAX_RSEG) 434 temp = XHCI_MAX_RSEG; 435 436 sc->sc_erst_max = temp; 437 438 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 439 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 440 441 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 442 443 /* Setup interrupt rate */ 444 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 445 446 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 447 448 phwr = buf_res.buffer; 449 addr = buf_res.physaddr; 450 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 451 452 /* reset hardware root structure */ 453 memset(phwr, 0, sizeof(*phwr)); 454 455 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 456 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 457 458 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 459 460 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 461 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 462 463 addr = (uint64_t)buf_res.physaddr; 464 465 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 466 467 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 468 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 469 470 /* Setup interrupter registers */ 471 472 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 473 temp |= XHCI_IMAN_INTR_ENA; 474 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 475 476 /* setup command ring control base address */ 477 addr = buf_res.physaddr; 478 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 479 480 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 481 482 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 483 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 484 485 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 486 487 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 488 489 /* Go! */ 490 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 491 XHCI_CMD_INTE | XHCI_CMD_HSEE); 492 493 for (i = 0; i != 100; i++) { 494 usb_pause_mtx(NULL, hz / 100); 495 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 496 if (!temp) 497 break; 498 } 499 if (temp) { 500 XWRITE4(sc, oper, XHCI_USBCMD, 0); 501 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 502 return (USB_ERR_IOERROR); 503 } 504 505 /* catch any lost interrupts */ 506 xhci_do_poll(&sc->sc_bus); 507 508 return (0); 509 } 510 511 usb_error_t 512 xhci_halt_controller(struct xhci_softc *sc) 513 { 514 uint32_t temp; 515 uint16_t i; 516 517 DPRINTF("\n"); 518 519 sc->sc_capa_off = 0; 520 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 521 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 522 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 523 524 /* Halt controller */ 525 XWRITE4(sc, oper, XHCI_USBCMD, 0); 526 527 for (i = 0; i != 100; i++) { 528 usb_pause_mtx(NULL, hz / 100); 529 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 530 if (temp) 531 break; 532 } 533 534 if (!temp) { 535 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 536 return (USB_ERR_IOERROR); 537 } 538 return (0); 539 } 540 541 usb_error_t 542 xhci_init(struct xhci_softc *sc, device_t self) 543 { 544 /* initialise some bus fields */ 545 sc->sc_bus.parent = self; 546 547 /* set the bus revision */ 548 sc->sc_bus.usbrev = USB_REV_3_0; 549 550 /* set up the bus struct */ 551 sc->sc_bus.methods = &xhci_bus_methods; 552 553 /* setup devices array */ 554 sc->sc_bus.devices = sc->sc_devices; 555 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 556 557 /* setup command queue mutex and condition varible */ 558 cv_init(&sc->sc_cmd_cv, "CMDQ"); 559 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 560 561 /* get all DMA memory */ 562 if (usb_bus_mem_alloc_all(&sc->sc_bus, 563 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 564 return (ENOMEM); 565 } 566 567 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 568 sc->sc_config_msg[0].bus = &sc->sc_bus; 569 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 570 sc->sc_config_msg[1].bus = &sc->sc_bus; 571 572 return (0); 573 } 574 575 void 576 xhci_uninit(struct xhci_softc *sc) 577 { 578 /* 579 * NOTE: At this point the control transfer process is gone 580 * and "xhci_configure_msg" is no longer called. Consequently 581 * waiting for the configuration messages to complete is not 582 * needed. 583 */ 584 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 585 586 cv_destroy(&sc->sc_cmd_cv); 587 sx_destroy(&sc->sc_cmd_sx); 588 } 589 590 static void 591 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 592 { 593 struct xhci_softc *sc = XHCI_BUS2SC(bus); 594 595 switch (state) { 596 case USB_HW_POWER_SUSPEND: 597 DPRINTF("Stopping the XHCI\n"); 598 xhci_halt_controller(sc); 599 break; 600 case USB_HW_POWER_SHUTDOWN: 601 DPRINTF("Stopping the XHCI\n"); 602 xhci_halt_controller(sc); 603 break; 604 case USB_HW_POWER_RESUME: 605 DPRINTF("Starting the XHCI\n"); 606 xhci_start_controller(sc); 607 break; 608 default: 609 break; 610 } 611 } 612 613 static usb_error_t 614 xhci_generic_done_sub(struct usb_xfer *xfer) 615 { 616 struct xhci_td *td; 617 struct xhci_td *td_alt_next; 618 uint32_t len; 619 uint8_t status; 620 621 td = xfer->td_transfer_cache; 622 td_alt_next = td->alt_next; 623 624 if (xfer->aframes != xfer->nframes) 625 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 626 627 while (1) { 628 629 usb_pc_cpu_invalidate(td->page_cache); 630 631 status = td->status; 632 len = td->remainder; 633 634 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 635 xfer, (unsigned int)xfer->aframes, 636 (unsigned int)xfer->nframes, 637 (unsigned int)len, (unsigned int)td->len, 638 (unsigned int)status); 639 640 /* 641 * Verify the status length and 642 * add the length to "frlengths[]": 643 */ 644 if (len > td->len) { 645 /* should not happen */ 646 DPRINTF("Invalid status length, " 647 "0x%04x/0x%04x bytes\n", len, td->len); 648 status = XHCI_TRB_ERROR_LENGTH; 649 } else if (xfer->aframes != xfer->nframes) { 650 xfer->frlengths[xfer->aframes] += td->len - len; 651 } 652 /* Check for last transfer */ 653 if (((void *)td) == xfer->td_transfer_last) { 654 td = NULL; 655 break; 656 } 657 /* Check for transfer error */ 658 if (status != XHCI_TRB_ERROR_SHORT_PKT && 659 status != XHCI_TRB_ERROR_SUCCESS) { 660 /* the transfer is finished */ 661 td = NULL; 662 break; 663 } 664 /* Check for short transfer */ 665 if (len > 0) { 666 if (xfer->flags_int.short_frames_ok || 667 xfer->flags_int.isochronous_xfr || 668 xfer->flags_int.control_xfr) { 669 /* follow alt next */ 670 td = td->alt_next; 671 } else { 672 /* the transfer is finished */ 673 td = NULL; 674 } 675 break; 676 } 677 td = td->obj_next; 678 679 if (td->alt_next != td_alt_next) { 680 /* this USB frame is complete */ 681 break; 682 } 683 } 684 685 /* update transfer cache */ 686 687 xfer->td_transfer_cache = td; 688 689 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 690 (status != XHCI_TRB_ERROR_SHORT_PKT && 691 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 692 USB_ERR_NORMAL_COMPLETION); 693 } 694 695 static void 696 xhci_generic_done(struct usb_xfer *xfer) 697 { 698 usb_error_t err = 0; 699 700 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 701 xfer, xfer->endpoint); 702 703 /* reset scanner */ 704 705 xfer->td_transfer_cache = xfer->td_transfer_first; 706 707 if (xfer->flags_int.control_xfr) { 708 709 if (xfer->flags_int.control_hdr) 710 err = xhci_generic_done_sub(xfer); 711 712 xfer->aframes = 1; 713 714 if (xfer->td_transfer_cache == NULL) 715 goto done; 716 } 717 718 while (xfer->aframes != xfer->nframes) { 719 720 err = xhci_generic_done_sub(xfer); 721 xfer->aframes++; 722 723 if (xfer->td_transfer_cache == NULL) 724 goto done; 725 } 726 727 if (xfer->flags_int.control_xfr && 728 !xfer->flags_int.control_act) 729 err = xhci_generic_done_sub(xfer); 730 done: 731 /* transfer is complete */ 732 xhci_device_done(xfer, err); 733 } 734 735 static void 736 xhci_activate_transfer(struct usb_xfer *xfer) 737 { 738 struct xhci_td *td; 739 740 td = xfer->td_transfer_cache; 741 742 usb_pc_cpu_invalidate(td->page_cache); 743 744 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 745 746 /* activate the transfer */ 747 748 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 749 usb_pc_cpu_flush(td->page_cache); 750 751 xhci_endpoint_doorbell(xfer); 752 } 753 } 754 755 static void 756 xhci_skip_transfer(struct usb_xfer *xfer) 757 { 758 struct xhci_td *td; 759 struct xhci_td *td_last; 760 761 td = xfer->td_transfer_cache; 762 td_last = xfer->td_transfer_last; 763 764 td = td->alt_next; 765 766 usb_pc_cpu_invalidate(td->page_cache); 767 768 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 769 770 usb_pc_cpu_invalidate(td_last->page_cache); 771 772 /* copy LINK TRB to current waiting location */ 773 774 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 775 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 776 usb_pc_cpu_flush(td->page_cache); 777 778 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 779 usb_pc_cpu_flush(td->page_cache); 780 781 xhci_endpoint_doorbell(xfer); 782 } 783 } 784 785 /*------------------------------------------------------------------------* 786 * xhci_check_transfer 787 *------------------------------------------------------------------------*/ 788 static void 789 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 790 { 791 struct xhci_endpoint_ext *pepext; 792 int64_t offset; 793 uint64_t td_event; 794 uint32_t temp; 795 uint32_t remainder; 796 uint16_t stream_id; 797 uint16_t i; 798 uint8_t status; 799 uint8_t halted; 800 uint8_t epno; 801 uint8_t index; 802 803 /* decode TRB */ 804 td_event = le64toh(trb->qwTrb0); 805 temp = le32toh(trb->dwTrb2); 806 807 remainder = XHCI_TRB_2_REM_GET(temp); 808 status = XHCI_TRB_2_ERROR_GET(temp); 809 stream_id = XHCI_TRB_2_STREAM_GET(temp); 810 811 temp = le32toh(trb->dwTrb3); 812 epno = XHCI_TRB_3_EP_GET(temp); 813 index = XHCI_TRB_3_SLOT_GET(temp); 814 815 /* check if error means halted */ 816 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 817 status != XHCI_TRB_ERROR_SUCCESS); 818 819 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 820 index, epno, stream_id, remainder, status); 821 822 if (index > sc->sc_noslot) { 823 DPRINTF("Invalid slot.\n"); 824 return; 825 } 826 827 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 828 DPRINTF("Invalid endpoint.\n"); 829 return; 830 } 831 832 pepext = &sc->sc_hw.devs[index].endp[epno]; 833 834 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 835 stream_id = 0; 836 DPRINTF("stream_id=0\n"); 837 } else if (stream_id >= XHCI_MAX_STREAMS) { 838 DPRINTF("Invalid stream ID.\n"); 839 return; 840 } 841 842 /* try to find the USB transfer that generated the event */ 843 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 844 struct usb_xfer *xfer; 845 struct xhci_td *td; 846 847 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 848 if (xfer == NULL) 849 continue; 850 851 td = xfer->td_transfer_cache; 852 853 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 854 (long long)td_event, 855 (long long)td->td_self, 856 (long long)td->td_self + sizeof(td->td_trb)); 857 858 /* 859 * NOTE: Some XHCI implementations might not trigger 860 * an event on the last LINK TRB so we need to 861 * consider both the last and second last event 862 * address as conditions for a successful transfer. 863 * 864 * NOTE: We assume that the XHCI will only trigger one 865 * event per chain of TRBs. 866 */ 867 868 offset = td_event - td->td_self; 869 870 if (offset >= 0 && 871 offset < (int64_t)sizeof(td->td_trb)) { 872 873 usb_pc_cpu_invalidate(td->page_cache); 874 875 /* compute rest of remainder, if any */ 876 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 877 temp = le32toh(td->td_trb[i].dwTrb2); 878 remainder += XHCI_TRB_2_BYTES_GET(temp); 879 } 880 881 DPRINTFN(5, "New remainder: %u\n", remainder); 882 883 /* clear isochronous transfer errors */ 884 if (xfer->flags_int.isochronous_xfr) { 885 if (halted) { 886 halted = 0; 887 status = XHCI_TRB_ERROR_SUCCESS; 888 remainder = td->len; 889 } 890 } 891 892 /* "td->remainder" is verified later */ 893 td->remainder = remainder; 894 td->status = status; 895 896 usb_pc_cpu_flush(td->page_cache); 897 898 /* 899 * 1) Last transfer descriptor makes the 900 * transfer done 901 */ 902 if (((void *)td) == xfer->td_transfer_last) { 903 DPRINTF("TD is last\n"); 904 xhci_generic_done(xfer); 905 break; 906 } 907 908 /* 909 * 2) Any kind of error makes the transfer 910 * done 911 */ 912 if (halted) { 913 DPRINTF("TD has I/O error\n"); 914 xhci_generic_done(xfer); 915 break; 916 } 917 918 /* 919 * 3) If there is no alternate next transfer, 920 * a short packet also makes the transfer done 921 */ 922 if (td->remainder > 0) { 923 if (td->alt_next == NULL) { 924 DPRINTF( 925 "short TD has no alternate next\n"); 926 xhci_generic_done(xfer); 927 break; 928 } 929 DPRINTF("TD has short pkt\n"); 930 if (xfer->flags_int.short_frames_ok || 931 xfer->flags_int.isochronous_xfr || 932 xfer->flags_int.control_xfr) { 933 /* follow the alt next */ 934 xfer->td_transfer_cache = td->alt_next; 935 xhci_activate_transfer(xfer); 936 break; 937 } 938 xhci_skip_transfer(xfer); 939 xhci_generic_done(xfer); 940 break; 941 } 942 943 /* 944 * 4) Transfer complete - go to next TD 945 */ 946 DPRINTF("Following next TD\n"); 947 xfer->td_transfer_cache = td->obj_next; 948 xhci_activate_transfer(xfer); 949 break; /* there should only be one match */ 950 } 951 } 952 } 953 954 static void 955 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 956 { 957 if (sc->sc_cmd_addr == trb->qwTrb0) { 958 DPRINTF("Received command event\n"); 959 sc->sc_cmd_result[0] = trb->dwTrb2; 960 sc->sc_cmd_result[1] = trb->dwTrb3; 961 cv_signal(&sc->sc_cmd_cv); 962 } 963 } 964 965 static void 966 xhci_interrupt_poll(struct xhci_softc *sc) 967 { 968 struct usb_page_search buf_res; 969 struct xhci_hw_root *phwr; 970 uint64_t addr; 971 uint32_t temp; 972 uint16_t i; 973 uint8_t event; 974 uint8_t j; 975 uint8_t k; 976 uint8_t t; 977 978 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 979 980 phwr = buf_res.buffer; 981 982 /* Receive any events */ 983 984 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 985 986 i = sc->sc_event_idx; 987 j = sc->sc_event_ccs; 988 t = 2; 989 990 while (1) { 991 992 temp = le32toh(phwr->hwr_events[i].dwTrb3); 993 994 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 995 996 if (j != k) 997 break; 998 999 event = XHCI_TRB_3_TYPE_GET(temp); 1000 1001 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1002 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1003 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1004 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1005 1006 switch (event) { 1007 case XHCI_TRB_EVENT_TRANSFER: 1008 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1009 break; 1010 case XHCI_TRB_EVENT_CMD_COMPLETE: 1011 xhci_check_command(sc, &phwr->hwr_events[i]); 1012 break; 1013 default: 1014 DPRINTF("Unhandled event = %u\n", event); 1015 break; 1016 } 1017 1018 i++; 1019 1020 if (i == XHCI_MAX_EVENTS) { 1021 i = 0; 1022 j ^= 1; 1023 1024 /* check for timeout */ 1025 if (!--t) 1026 break; 1027 } 1028 } 1029 1030 sc->sc_event_idx = i; 1031 sc->sc_event_ccs = j; 1032 1033 /* 1034 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1035 * latched. That means to activate the register we need to 1036 * write both the low and high double word of the 64-bit 1037 * register. 1038 */ 1039 1040 addr = (uint32_t)buf_res.physaddr; 1041 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1042 1043 /* try to clear busy bit */ 1044 addr |= XHCI_ERDP_LO_BUSY; 1045 1046 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1047 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1048 } 1049 1050 static usb_error_t 1051 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1052 uint16_t timeout_ms) 1053 { 1054 struct usb_page_search buf_res; 1055 struct xhci_hw_root *phwr; 1056 uint64_t addr; 1057 uint32_t temp; 1058 uint8_t i; 1059 uint8_t j; 1060 int err; 1061 1062 XHCI_CMD_ASSERT_LOCKED(sc); 1063 1064 /* get hardware root structure */ 1065 1066 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1067 1068 phwr = buf_res.buffer; 1069 1070 /* Queue command */ 1071 1072 USB_BUS_LOCK(&sc->sc_bus); 1073 1074 i = sc->sc_command_idx; 1075 j = sc->sc_command_ccs; 1076 1077 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1078 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1079 (long long)le64toh(trb->qwTrb0), 1080 (long)le32toh(trb->dwTrb2), 1081 (long)le32toh(trb->dwTrb3)); 1082 1083 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1084 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1085 1086 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1087 1088 temp = trb->dwTrb3; 1089 1090 if (j) 1091 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1092 else 1093 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1094 1095 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1096 1097 phwr->hwr_commands[i].dwTrb3 = temp; 1098 1099 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1100 1101 addr = buf_res.physaddr; 1102 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1103 1104 sc->sc_cmd_addr = htole64(addr); 1105 1106 i++; 1107 1108 if (i == (XHCI_MAX_COMMANDS - 1)) { 1109 1110 if (j) { 1111 temp = htole32(XHCI_TRB_3_TC_BIT | 1112 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1113 XHCI_TRB_3_CYCLE_BIT); 1114 } else { 1115 temp = htole32(XHCI_TRB_3_TC_BIT | 1116 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1117 } 1118 1119 phwr->hwr_commands[i].dwTrb3 = temp; 1120 1121 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1122 1123 i = 0; 1124 j ^= 1; 1125 } 1126 1127 sc->sc_command_idx = i; 1128 sc->sc_command_ccs = j; 1129 1130 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1131 1132 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1133 USB_MS_TO_TICKS(timeout_ms)); 1134 1135 if (err) { 1136 DPRINTFN(0, "Command timeout!\n"); 1137 err = USB_ERR_TIMEOUT; 1138 trb->dwTrb2 = 0; 1139 trb->dwTrb3 = 0; 1140 } else { 1141 temp = le32toh(sc->sc_cmd_result[0]); 1142 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1143 err = USB_ERR_IOERROR; 1144 1145 trb->dwTrb2 = sc->sc_cmd_result[0]; 1146 trb->dwTrb3 = sc->sc_cmd_result[1]; 1147 } 1148 1149 USB_BUS_UNLOCK(&sc->sc_bus); 1150 1151 return (err); 1152 } 1153 1154 #if 0 1155 static usb_error_t 1156 xhci_cmd_nop(struct xhci_softc *sc) 1157 { 1158 struct xhci_trb trb; 1159 uint32_t temp; 1160 1161 DPRINTF("\n"); 1162 1163 trb.qwTrb0 = 0; 1164 trb.dwTrb2 = 0; 1165 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1166 1167 trb.dwTrb3 = htole32(temp); 1168 1169 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1170 } 1171 #endif 1172 1173 static usb_error_t 1174 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1175 { 1176 struct xhci_trb trb; 1177 uint32_t temp; 1178 usb_error_t err; 1179 1180 DPRINTF("\n"); 1181 1182 trb.qwTrb0 = 0; 1183 trb.dwTrb2 = 0; 1184 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1185 1186 err = xhci_do_command(sc, &trb, 100 /* ms */); 1187 if (err) 1188 goto done; 1189 1190 temp = le32toh(trb.dwTrb3); 1191 1192 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1193 1194 done: 1195 return (err); 1196 } 1197 1198 static usb_error_t 1199 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1200 { 1201 struct xhci_trb trb; 1202 uint32_t temp; 1203 1204 DPRINTF("\n"); 1205 1206 trb.qwTrb0 = 0; 1207 trb.dwTrb2 = 0; 1208 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1209 XHCI_TRB_3_SLOT_SET(slot_id); 1210 1211 trb.dwTrb3 = htole32(temp); 1212 1213 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1214 } 1215 1216 static usb_error_t 1217 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1218 uint8_t bsr, uint8_t slot_id) 1219 { 1220 struct xhci_trb trb; 1221 uint32_t temp; 1222 1223 DPRINTF("\n"); 1224 1225 trb.qwTrb0 = htole64(input_ctx); 1226 trb.dwTrb2 = 0; 1227 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1228 XHCI_TRB_3_SLOT_SET(slot_id); 1229 1230 if (bsr) 1231 temp |= XHCI_TRB_3_BSR_BIT; 1232 1233 trb.dwTrb3 = htole32(temp); 1234 1235 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1236 } 1237 1238 static usb_error_t 1239 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1240 { 1241 struct usb_page_search buf_inp; 1242 struct usb_page_search buf_dev; 1243 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1244 struct xhci_hw_dev *hdev; 1245 struct xhci_dev_ctx *pdev; 1246 struct xhci_endpoint_ext *pepext; 1247 uint32_t temp; 1248 uint16_t mps; 1249 usb_error_t err; 1250 uint8_t index; 1251 1252 /* the root HUB case is not handled here */ 1253 if (udev->parent_hub == NULL) 1254 return (USB_ERR_INVAL); 1255 1256 index = udev->controller_slot_id; 1257 1258 hdev = &sc->sc_hw.devs[index]; 1259 1260 if (mtx != NULL) 1261 mtx_unlock(mtx); 1262 1263 XHCI_CMD_LOCK(sc); 1264 1265 switch (hdev->state) { 1266 case XHCI_ST_DEFAULT: 1267 case XHCI_ST_ENABLED: 1268 1269 hdev->state = XHCI_ST_ENABLED; 1270 1271 /* set configure mask to slot and EP0 */ 1272 xhci_configure_mask(udev, 3, 0); 1273 1274 /* configure input slot context structure */ 1275 err = xhci_configure_device(udev); 1276 1277 if (err != 0) { 1278 DPRINTF("Could not configure device\n"); 1279 break; 1280 } 1281 1282 /* configure input endpoint context structure */ 1283 switch (udev->speed) { 1284 case USB_SPEED_LOW: 1285 case USB_SPEED_FULL: 1286 mps = 8; 1287 break; 1288 case USB_SPEED_HIGH: 1289 mps = 64; 1290 break; 1291 default: 1292 mps = 512; 1293 break; 1294 } 1295 1296 pepext = xhci_get_endpoint_ext(udev, 1297 &udev->ctrl_ep_desc); 1298 err = xhci_configure_endpoint(udev, 1299 &udev->ctrl_ep_desc, pepext, 1300 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1301 1302 if (err != 0) { 1303 DPRINTF("Could not configure default endpoint\n"); 1304 break; 1305 } 1306 1307 /* execute set address command */ 1308 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1309 1310 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1311 (address == 0), index); 1312 1313 if (err != 0) { 1314 DPRINTF("Could not set address " 1315 "for slot %u.\n", index); 1316 if (address != 0) 1317 break; 1318 } 1319 1320 /* update device address to new value */ 1321 1322 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1323 pdev = buf_dev.buffer; 1324 usb_pc_cpu_invalidate(&hdev->device_pc); 1325 1326 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1327 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1328 1329 /* update device state to new value */ 1330 1331 if (address != 0) 1332 hdev->state = XHCI_ST_ADDRESSED; 1333 else 1334 hdev->state = XHCI_ST_DEFAULT; 1335 break; 1336 1337 default: 1338 DPRINTF("Wrong state for set address.\n"); 1339 err = USB_ERR_IOERROR; 1340 break; 1341 } 1342 XHCI_CMD_UNLOCK(sc); 1343 1344 if (mtx != NULL) 1345 mtx_lock(mtx); 1346 1347 return (err); 1348 } 1349 1350 static usb_error_t 1351 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1352 uint8_t deconfigure, uint8_t slot_id) 1353 { 1354 struct xhci_trb trb; 1355 uint32_t temp; 1356 1357 DPRINTF("\n"); 1358 1359 trb.qwTrb0 = htole64(input_ctx); 1360 trb.dwTrb2 = 0; 1361 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1362 XHCI_TRB_3_SLOT_SET(slot_id); 1363 1364 if (deconfigure) 1365 temp |= XHCI_TRB_3_DCEP_BIT; 1366 1367 trb.dwTrb3 = htole32(temp); 1368 1369 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1370 } 1371 1372 static usb_error_t 1373 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1374 uint8_t slot_id) 1375 { 1376 struct xhci_trb trb; 1377 uint32_t temp; 1378 1379 DPRINTF("\n"); 1380 1381 trb.qwTrb0 = htole64(input_ctx); 1382 trb.dwTrb2 = 0; 1383 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1384 XHCI_TRB_3_SLOT_SET(slot_id); 1385 trb.dwTrb3 = htole32(temp); 1386 1387 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1388 } 1389 1390 static usb_error_t 1391 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1392 uint8_t ep_id, uint8_t slot_id) 1393 { 1394 struct xhci_trb trb; 1395 uint32_t temp; 1396 1397 DPRINTF("\n"); 1398 1399 trb.qwTrb0 = 0; 1400 trb.dwTrb2 = 0; 1401 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1402 XHCI_TRB_3_SLOT_SET(slot_id) | 1403 XHCI_TRB_3_EP_SET(ep_id); 1404 1405 if (preserve) 1406 temp |= XHCI_TRB_3_PRSV_BIT; 1407 1408 trb.dwTrb3 = htole32(temp); 1409 1410 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1411 } 1412 1413 static usb_error_t 1414 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1415 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1416 { 1417 struct xhci_trb trb; 1418 uint32_t temp; 1419 1420 DPRINTF("\n"); 1421 1422 trb.qwTrb0 = htole64(dequeue_ptr); 1423 1424 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1425 trb.dwTrb2 = htole32(temp); 1426 1427 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1428 XHCI_TRB_3_SLOT_SET(slot_id) | 1429 XHCI_TRB_3_EP_SET(ep_id); 1430 trb.dwTrb3 = htole32(temp); 1431 1432 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1433 } 1434 1435 static usb_error_t 1436 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1437 uint8_t ep_id, uint8_t slot_id) 1438 { 1439 struct xhci_trb trb; 1440 uint32_t temp; 1441 1442 DPRINTF("\n"); 1443 1444 trb.qwTrb0 = 0; 1445 trb.dwTrb2 = 0; 1446 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1447 XHCI_TRB_3_SLOT_SET(slot_id) | 1448 XHCI_TRB_3_EP_SET(ep_id); 1449 1450 if (suspend) 1451 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1452 1453 trb.dwTrb3 = htole32(temp); 1454 1455 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1456 } 1457 1458 static usb_error_t 1459 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1460 { 1461 struct xhci_trb trb; 1462 uint32_t temp; 1463 1464 DPRINTF("\n"); 1465 1466 trb.qwTrb0 = 0; 1467 trb.dwTrb2 = 0; 1468 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1469 XHCI_TRB_3_SLOT_SET(slot_id); 1470 1471 trb.dwTrb3 = htole32(temp); 1472 1473 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1474 } 1475 1476 /*------------------------------------------------------------------------* 1477 * xhci_interrupt - XHCI interrupt handler 1478 *------------------------------------------------------------------------*/ 1479 void 1480 xhci_interrupt(struct xhci_softc *sc) 1481 { 1482 uint32_t status; 1483 1484 USB_BUS_LOCK(&sc->sc_bus); 1485 1486 status = XREAD4(sc, oper, XHCI_USBSTS); 1487 if (status == 0) 1488 goto done; 1489 1490 /* acknowledge interrupts */ 1491 1492 XWRITE4(sc, oper, XHCI_USBSTS, status); 1493 1494 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1495 1496 if (status & XHCI_STS_EINT) { 1497 /* check for event(s) */ 1498 xhci_interrupt_poll(sc); 1499 } 1500 1501 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1502 XHCI_STS_HSE | XHCI_STS_HCE)) { 1503 1504 if (status & XHCI_STS_PCD) { 1505 xhci_root_intr(sc); 1506 } 1507 1508 if (status & XHCI_STS_HCH) { 1509 printf("%s: host controller halted\n", 1510 __FUNCTION__); 1511 } 1512 1513 if (status & XHCI_STS_HSE) { 1514 printf("%s: host system error\n", 1515 __FUNCTION__); 1516 } 1517 1518 if (status & XHCI_STS_HCE) { 1519 printf("%s: host controller error\n", 1520 __FUNCTION__); 1521 } 1522 } 1523 done: 1524 USB_BUS_UNLOCK(&sc->sc_bus); 1525 } 1526 1527 /*------------------------------------------------------------------------* 1528 * xhci_timeout - XHCI timeout handler 1529 *------------------------------------------------------------------------*/ 1530 static void 1531 xhci_timeout(void *arg) 1532 { 1533 struct usb_xfer *xfer = arg; 1534 1535 DPRINTF("xfer=%p\n", xfer); 1536 1537 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1538 1539 /* transfer is transferred */ 1540 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1541 } 1542 1543 static void 1544 xhci_do_poll(struct usb_bus *bus) 1545 { 1546 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1547 1548 USB_BUS_LOCK(&sc->sc_bus); 1549 xhci_interrupt_poll(sc); 1550 USB_BUS_UNLOCK(&sc->sc_bus); 1551 } 1552 1553 static void 1554 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1555 { 1556 struct usb_page_search buf_res; 1557 struct xhci_td *td; 1558 struct xhci_td *td_next; 1559 struct xhci_td *td_alt_next; 1560 struct xhci_td *td_first; 1561 uint32_t buf_offset; 1562 uint32_t average; 1563 uint32_t len_old; 1564 uint32_t npkt_off; 1565 uint32_t dword; 1566 uint8_t shortpkt_old; 1567 uint8_t precompute; 1568 uint8_t x; 1569 1570 td_alt_next = NULL; 1571 buf_offset = 0; 1572 shortpkt_old = temp->shortpkt; 1573 len_old = temp->len; 1574 npkt_off = 0; 1575 precompute = 1; 1576 1577 restart: 1578 1579 td = temp->td; 1580 td_next = td_first = temp->td_next; 1581 1582 while (1) { 1583 1584 if (temp->len == 0) { 1585 1586 if (temp->shortpkt) 1587 break; 1588 1589 /* send a Zero Length Packet, ZLP, last */ 1590 1591 temp->shortpkt = 1; 1592 average = 0; 1593 1594 } else { 1595 1596 average = temp->average; 1597 1598 if (temp->len < average) { 1599 if (temp->len % temp->max_packet_size) { 1600 temp->shortpkt = 1; 1601 } 1602 average = temp->len; 1603 } 1604 } 1605 1606 if (td_next == NULL) 1607 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1608 1609 /* get next TD */ 1610 1611 td = td_next; 1612 td_next = td->obj_next; 1613 1614 /* check if we are pre-computing */ 1615 1616 if (precompute) { 1617 1618 /* update remaining length */ 1619 1620 temp->len -= average; 1621 1622 continue; 1623 } 1624 /* fill out current TD */ 1625 1626 td->len = average; 1627 td->remainder = 0; 1628 td->status = 0; 1629 1630 /* update remaining length */ 1631 1632 temp->len -= average; 1633 1634 /* reset TRB index */ 1635 1636 x = 0; 1637 1638 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1639 /* immediate data */ 1640 1641 if (average > 8) 1642 average = 8; 1643 1644 td->td_trb[0].qwTrb0 = 0; 1645 1646 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1647 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1648 average); 1649 1650 dword = XHCI_TRB_2_BYTES_SET(8) | 1651 XHCI_TRB_2_TDSZ_SET(0) | 1652 XHCI_TRB_2_IRQ_SET(0); 1653 1654 td->td_trb[0].dwTrb2 = htole32(dword); 1655 1656 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1657 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1658 1659 /* check wLength */ 1660 if (td->td_trb[0].qwTrb0 & 1661 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1662 if (td->td_trb[0].qwTrb0 & htole64(1)) 1663 dword |= XHCI_TRB_3_TRT_IN; 1664 else 1665 dword |= XHCI_TRB_3_TRT_OUT; 1666 } 1667 1668 td->td_trb[0].dwTrb3 = htole32(dword); 1669 #ifdef USB_DEBUG 1670 xhci_dump_trb(&td->td_trb[x]); 1671 #endif 1672 x++; 1673 1674 } else do { 1675 1676 uint32_t npkt; 1677 1678 /* fill out buffer pointers */ 1679 1680 if (average == 0) { 1681 memset(&buf_res, 0, sizeof(buf_res)); 1682 } else { 1683 usbd_get_page(temp->pc, temp->offset + 1684 buf_offset, &buf_res); 1685 1686 /* get length to end of page */ 1687 if (buf_res.length > average) 1688 buf_res.length = average; 1689 1690 /* check for maximum length */ 1691 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1692 buf_res.length = XHCI_TD_PAGE_SIZE; 1693 1694 npkt_off += buf_res.length; 1695 } 1696 1697 /* setup npkt */ 1698 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1699 temp->max_packet_size; 1700 1701 if (npkt == 0) 1702 npkt = 1; 1703 else if (npkt > 31) 1704 npkt = 31; 1705 1706 /* fill out TRB's */ 1707 td->td_trb[x].qwTrb0 = 1708 htole64((uint64_t)buf_res.physaddr); 1709 1710 dword = 1711 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1712 XHCI_TRB_2_TDSZ_SET(npkt) | 1713 XHCI_TRB_2_IRQ_SET(0); 1714 1715 td->td_trb[x].dwTrb2 = htole32(dword); 1716 1717 switch (temp->trb_type) { 1718 case XHCI_TRB_TYPE_ISOCH: 1719 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1720 XHCI_TRB_3_TBC_SET(temp->tbc) | 1721 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1722 if (td != td_first) { 1723 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1724 } else if (temp->do_isoc_sync != 0) { 1725 temp->do_isoc_sync = 0; 1726 /* wait until "isoc_frame" */ 1727 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1728 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1729 } else { 1730 /* start data transfer at next interval */ 1731 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1732 XHCI_TRB_3_ISO_SIA_BIT; 1733 } 1734 if (temp->direction == UE_DIR_IN) 1735 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1736 break; 1737 case XHCI_TRB_TYPE_DATA_STAGE: 1738 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1739 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 1740 XHCI_TRB_3_TBC_SET(temp->tbc) | 1741 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1742 if (temp->direction == UE_DIR_IN) 1743 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1744 break; 1745 case XHCI_TRB_TYPE_STATUS_STAGE: 1746 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1747 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 1748 XHCI_TRB_3_TBC_SET(temp->tbc) | 1749 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1750 if (temp->direction == UE_DIR_IN) 1751 dword |= XHCI_TRB_3_DIR_IN; 1752 break; 1753 default: /* XHCI_TRB_TYPE_NORMAL */ 1754 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1755 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 1756 XHCI_TRB_3_TBC_SET(temp->tbc) | 1757 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1758 if (temp->direction == UE_DIR_IN) 1759 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1760 break; 1761 } 1762 td->td_trb[x].dwTrb3 = htole32(dword); 1763 1764 average -= buf_res.length; 1765 buf_offset += buf_res.length; 1766 #ifdef USB_DEBUG 1767 xhci_dump_trb(&td->td_trb[x]); 1768 #endif 1769 x++; 1770 1771 } while (average != 0); 1772 1773 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1774 1775 /* store number of data TRB's */ 1776 1777 td->ntrb = x; 1778 1779 DPRINTF("NTRB=%u\n", x); 1780 1781 /* fill out link TRB */ 1782 1783 if (td_next != NULL) { 1784 /* link the current TD with the next one */ 1785 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1786 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1787 } else { 1788 /* this field will get updated later */ 1789 DPRINTF("NOLINK\n"); 1790 } 1791 1792 dword = XHCI_TRB_2_IRQ_SET(0); 1793 1794 td->td_trb[x].dwTrb2 = htole32(dword); 1795 1796 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1797 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT; 1798 1799 td->td_trb[x].dwTrb3 = htole32(dword); 1800 1801 td->alt_next = td_alt_next; 1802 #ifdef USB_DEBUG 1803 xhci_dump_trb(&td->td_trb[x]); 1804 #endif 1805 usb_pc_cpu_flush(td->page_cache); 1806 } 1807 1808 if (precompute) { 1809 precompute = 0; 1810 1811 /* setup alt next pointer, if any */ 1812 if (temp->last_frame) { 1813 td_alt_next = NULL; 1814 } else { 1815 /* we use this field internally */ 1816 td_alt_next = td_next; 1817 } 1818 1819 /* restore */ 1820 temp->shortpkt = shortpkt_old; 1821 temp->len = len_old; 1822 goto restart; 1823 } 1824 1825 /* 1826 * Remove cycle bit from the first TRB if we are 1827 * stepping them: 1828 */ 1829 if (temp->step_td != 0) { 1830 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1831 usb_pc_cpu_flush(td_first->page_cache); 1832 } 1833 1834 /* clear TD SIZE to zero, hence this is the last TRB */ 1835 /* remove chain bit because this is the last TRB in the chain */ 1836 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1837 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1838 1839 usb_pc_cpu_flush(td->page_cache); 1840 1841 temp->td = td; 1842 temp->td_next = td_next; 1843 } 1844 1845 static void 1846 xhci_setup_generic_chain(struct usb_xfer *xfer) 1847 { 1848 struct xhci_std_temp temp; 1849 struct xhci_td *td; 1850 uint32_t x; 1851 uint32_t y; 1852 uint8_t mult; 1853 1854 temp.do_isoc_sync = 0; 1855 temp.step_td = 0; 1856 temp.tbc = 0; 1857 temp.tlbpc = 0; 1858 temp.average = xfer->max_hc_frame_size; 1859 temp.max_packet_size = xfer->max_packet_size; 1860 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1861 temp.pc = NULL; 1862 temp.last_frame = 0; 1863 temp.offset = 0; 1864 temp.multishort = xfer->flags_int.isochronous_xfr || 1865 xfer->flags_int.control_xfr || 1866 xfer->flags_int.short_frames_ok; 1867 1868 /* toggle the DMA set we are using */ 1869 xfer->flags_int.curr_dma_set ^= 1; 1870 1871 /* get next DMA set */ 1872 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1873 1874 temp.td = NULL; 1875 temp.td_next = td; 1876 1877 xfer->td_transfer_first = td; 1878 xfer->td_transfer_cache = td; 1879 1880 if (xfer->flags_int.isochronous_xfr) { 1881 uint8_t shift; 1882 1883 /* compute multiplier for ISOCHRONOUS transfers */ 1884 mult = xfer->endpoint->ecomp ? 1885 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 1886 : 0; 1887 /* check for USB 2.0 multiplier */ 1888 if (mult == 0) { 1889 mult = (xfer->endpoint->edesc-> 1890 wMaxPacketSize[1] >> 3) & 3; 1891 } 1892 /* range check */ 1893 if (mult > 2) 1894 mult = 3; 1895 else 1896 mult++; 1897 1898 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 1899 1900 DPRINTF("MFINDEX=0x%08x\n", x); 1901 1902 switch (usbd_get_speed(xfer->xroot->udev)) { 1903 case USB_SPEED_FULL: 1904 shift = 3; 1905 temp.isoc_delta = 8; /* 1ms */ 1906 x += temp.isoc_delta - 1; 1907 x &= ~(temp.isoc_delta - 1); 1908 break; 1909 default: 1910 shift = usbd_xfer_get_fps_shift(xfer); 1911 temp.isoc_delta = 1U << shift; 1912 x += temp.isoc_delta - 1; 1913 x &= ~(temp.isoc_delta - 1); 1914 /* simple frame load balancing */ 1915 x += xfer->endpoint->usb_uframe; 1916 break; 1917 } 1918 1919 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 1920 1921 if ((xfer->endpoint->is_synced == 0) || 1922 (y < (xfer->nframes << shift)) || 1923 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 1924 /* 1925 * If there is data underflow or the pipe 1926 * queue is empty we schedule the transfer a 1927 * few frames ahead of the current frame 1928 * position. Else two isochronous transfers 1929 * might overlap. 1930 */ 1931 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 1932 xfer->endpoint->is_synced = 1; 1933 temp.do_isoc_sync = 1; 1934 1935 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1936 } 1937 1938 /* compute isochronous completion time */ 1939 1940 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 1941 1942 xfer->isoc_time_complete = 1943 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 1944 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 1945 1946 x = 0; 1947 temp.isoc_frame = xfer->endpoint->isoc_next; 1948 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 1949 1950 xfer->endpoint->isoc_next += xfer->nframes << shift; 1951 1952 } else if (xfer->flags_int.control_xfr) { 1953 1954 /* check if we should prepend a setup message */ 1955 1956 if (xfer->flags_int.control_hdr) { 1957 1958 temp.len = xfer->frlengths[0]; 1959 temp.pc = xfer->frbuffers + 0; 1960 temp.shortpkt = temp.len ? 1 : 0; 1961 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 1962 temp.direction = 0; 1963 1964 /* check for last frame */ 1965 if (xfer->nframes == 1) { 1966 /* no STATUS stage yet, SETUP is last */ 1967 if (xfer->flags_int.control_act) 1968 temp.last_frame = 1; 1969 } 1970 1971 xhci_setup_generic_chain_sub(&temp); 1972 } 1973 x = 1; 1974 mult = 1; 1975 temp.isoc_delta = 0; 1976 temp.isoc_frame = 0; 1977 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 1978 } else { 1979 x = 0; 1980 mult = 1; 1981 temp.isoc_delta = 0; 1982 temp.isoc_frame = 0; 1983 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 1984 } 1985 1986 if (x != xfer->nframes) { 1987 /* setup page_cache pointer */ 1988 temp.pc = xfer->frbuffers + x; 1989 /* set endpoint direction */ 1990 temp.direction = UE_GET_DIR(xfer->endpointno); 1991 } 1992 1993 while (x != xfer->nframes) { 1994 1995 /* DATA0 / DATA1 message */ 1996 1997 temp.len = xfer->frlengths[x]; 1998 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 1999 x != 0 && temp.multishort == 0); 2000 2001 x++; 2002 2003 if (x == xfer->nframes) { 2004 if (xfer->flags_int.control_xfr) { 2005 /* no STATUS stage yet, DATA is last */ 2006 if (xfer->flags_int.control_act) 2007 temp.last_frame = 1; 2008 } else { 2009 temp.last_frame = 1; 2010 } 2011 } 2012 if (temp.len == 0) { 2013 2014 /* make sure that we send an USB packet */ 2015 2016 temp.shortpkt = 0; 2017 2018 temp.tbc = 0; 2019 temp.tlbpc = mult - 1; 2020 2021 } else if (xfer->flags_int.isochronous_xfr) { 2022 2023 uint8_t tdpc; 2024 2025 /* 2026 * Isochronous transfers don't have short 2027 * packet termination: 2028 */ 2029 2030 temp.shortpkt = 1; 2031 2032 /* isochronous transfers have a transfer limit */ 2033 2034 if (temp.len > xfer->max_frame_size) 2035 temp.len = xfer->max_frame_size; 2036 2037 /* compute TD packet count */ 2038 tdpc = (temp.len + xfer->max_packet_size - 1) / 2039 xfer->max_packet_size; 2040 2041 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2042 temp.tlbpc = (tdpc % mult); 2043 2044 if (temp.tlbpc == 0) 2045 temp.tlbpc = mult - 1; 2046 else 2047 temp.tlbpc--; 2048 } else { 2049 2050 /* regular data transfer */ 2051 2052 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2053 } 2054 2055 xhci_setup_generic_chain_sub(&temp); 2056 2057 if (xfer->flags_int.isochronous_xfr) { 2058 temp.offset += xfer->frlengths[x - 1]; 2059 temp.isoc_frame += temp.isoc_delta; 2060 } else { 2061 /* get next Page Cache pointer */ 2062 temp.pc = xfer->frbuffers + x; 2063 } 2064 } 2065 2066 /* check if we should append a status stage */ 2067 2068 if (xfer->flags_int.control_xfr && 2069 !xfer->flags_int.control_act) { 2070 2071 /* 2072 * Send a DATA1 message and invert the current 2073 * endpoint direction. 2074 */ 2075 temp.step_td = (xfer->nframes != 0); 2076 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2077 temp.len = 0; 2078 temp.pc = NULL; 2079 temp.shortpkt = 0; 2080 temp.last_frame = 1; 2081 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2082 2083 xhci_setup_generic_chain_sub(&temp); 2084 } 2085 2086 td = temp.td; 2087 2088 /* must have at least one frame! */ 2089 2090 xfer->td_transfer_last = td; 2091 2092 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2093 } 2094 2095 static void 2096 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2097 { 2098 struct usb_page_search buf_res; 2099 struct xhci_dev_ctx_addr *pdctxa; 2100 2101 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2102 2103 pdctxa = buf_res.buffer; 2104 2105 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2106 2107 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2108 2109 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2110 } 2111 2112 static usb_error_t 2113 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2114 { 2115 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2116 struct usb_page_search buf_inp; 2117 struct xhci_input_dev_ctx *pinp; 2118 uint32_t temp; 2119 uint8_t index; 2120 uint8_t x; 2121 2122 index = udev->controller_slot_id; 2123 2124 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2125 2126 pinp = buf_inp.buffer; 2127 2128 if (drop) { 2129 mask &= XHCI_INCTX_NON_CTRL_MASK; 2130 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2131 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2132 } else { 2133 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2134 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2135 2136 /* find most significant set bit */ 2137 for (x = 31; x != 1; x--) { 2138 if (mask & (1 << x)) 2139 break; 2140 } 2141 2142 /* adjust */ 2143 x--; 2144 2145 /* figure out maximum */ 2146 if (x > sc->sc_hw.devs[index].context_num) { 2147 sc->sc_hw.devs[index].context_num = x; 2148 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2149 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2150 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2151 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2152 } 2153 } 2154 return (0); 2155 } 2156 2157 static usb_error_t 2158 xhci_configure_endpoint(struct usb_device *udev, 2159 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2160 uint16_t interval, uint8_t max_packet_count, 2161 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2162 uint16_t max_frame_size, uint8_t ep_mode) 2163 { 2164 struct usb_page_search buf_inp; 2165 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2166 struct xhci_input_dev_ctx *pinp; 2167 uint64_t ring_addr = pepext->physaddr; 2168 uint32_t temp; 2169 uint8_t index; 2170 uint8_t epno; 2171 uint8_t type; 2172 2173 index = udev->controller_slot_id; 2174 2175 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2176 2177 pinp = buf_inp.buffer; 2178 2179 epno = edesc->bEndpointAddress; 2180 type = edesc->bmAttributes & UE_XFERTYPE; 2181 2182 if (type == UE_CONTROL) 2183 epno |= UE_DIR_IN; 2184 2185 epno = XHCI_EPNO2EPID(epno); 2186 2187 if (epno == 0) 2188 return (USB_ERR_NO_PIPE); /* invalid */ 2189 2190 if (max_packet_count == 0) 2191 return (USB_ERR_BAD_BUFSIZE); 2192 2193 max_packet_count--; 2194 2195 if (mult == 0) 2196 return (USB_ERR_BAD_BUFSIZE); 2197 2198 /* store endpoint mode */ 2199 pepext->trb_ep_mode = ep_mode; 2200 usb_pc_cpu_flush(pepext->page_cache); 2201 2202 if (ep_mode == USB_EP_MODE_STREAMS) { 2203 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2204 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2205 XHCI_EPCTX_0_LSA_SET(1); 2206 2207 ring_addr += sizeof(struct xhci_trb) * 2208 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2209 } else { 2210 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2211 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2212 XHCI_EPCTX_0_LSA_SET(0); 2213 2214 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2215 } 2216 2217 switch (udev->speed) { 2218 case USB_SPEED_FULL: 2219 case USB_SPEED_LOW: 2220 /* 1ms -> 125us */ 2221 fps_shift += 3; 2222 break; 2223 default: 2224 break; 2225 } 2226 2227 switch (type) { 2228 case UE_INTERRUPT: 2229 if (fps_shift > 3) 2230 fps_shift--; 2231 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2232 break; 2233 case UE_ISOCHRONOUS: 2234 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2235 2236 switch (udev->speed) { 2237 case USB_SPEED_SUPER: 2238 if (mult > 3) 2239 mult = 3; 2240 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2241 max_packet_count /= mult; 2242 break; 2243 default: 2244 break; 2245 } 2246 break; 2247 default: 2248 break; 2249 } 2250 2251 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2252 2253 temp = 2254 XHCI_EPCTX_1_HID_SET(0) | 2255 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2256 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2257 2258 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2259 if (type != UE_ISOCHRONOUS) 2260 temp |= XHCI_EPCTX_1_CERR_SET(3); 2261 } 2262 2263 switch (type) { 2264 case UE_CONTROL: 2265 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2266 break; 2267 case UE_ISOCHRONOUS: 2268 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2269 break; 2270 case UE_BULK: 2271 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2272 break; 2273 default: 2274 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2275 break; 2276 } 2277 2278 /* check for IN direction */ 2279 if (epno & 1) 2280 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2281 2282 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2283 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2284 2285 switch (edesc->bmAttributes & UE_XFERTYPE) { 2286 case UE_INTERRUPT: 2287 case UE_ISOCHRONOUS: 2288 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2289 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2290 max_frame_size)); 2291 break; 2292 case UE_CONTROL: 2293 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2294 break; 2295 default: 2296 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2297 break; 2298 } 2299 2300 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2301 2302 #ifdef USB_DEBUG 2303 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2304 #endif 2305 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2306 2307 return (0); /* success */ 2308 } 2309 2310 static usb_error_t 2311 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2312 { 2313 struct xhci_endpoint_ext *pepext; 2314 struct usb_endpoint_ss_comp_descriptor *ecomp; 2315 usb_stream_t x; 2316 2317 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2318 xfer->endpoint->edesc); 2319 2320 ecomp = xfer->endpoint->ecomp; 2321 2322 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2323 uint64_t temp; 2324 2325 /* halt any transfers */ 2326 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2327 2328 /* compute start of TRB ring for stream "x" */ 2329 temp = pepext->physaddr + 2330 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2331 XHCI_SCTX_0_SCT_SEC_TR_RING; 2332 2333 /* make tree structure */ 2334 pepext->trb[(XHCI_MAX_TRANSFERS * 2335 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2336 2337 /* reserved fields */ 2338 pepext->trb[(XHCI_MAX_TRANSFERS * 2339 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2340 pepext->trb[(XHCI_MAX_TRANSFERS * 2341 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2342 } 2343 usb_pc_cpu_flush(pepext->page_cache); 2344 2345 return (xhci_configure_endpoint(xfer->xroot->udev, 2346 xfer->endpoint->edesc, pepext, 2347 xfer->interval, xfer->max_packet_count, 2348 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2349 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2350 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2351 } 2352 2353 static usb_error_t 2354 xhci_configure_device(struct usb_device *udev) 2355 { 2356 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2357 struct usb_page_search buf_inp; 2358 struct usb_page_cache *pcinp; 2359 struct xhci_input_dev_ctx *pinp; 2360 struct usb_device *hubdev; 2361 uint32_t temp; 2362 uint32_t route; 2363 uint32_t rh_port; 2364 uint8_t is_hub; 2365 uint8_t index; 2366 uint8_t depth; 2367 2368 index = udev->controller_slot_id; 2369 2370 DPRINTF("index=%u\n", index); 2371 2372 pcinp = &sc->sc_hw.devs[index].input_pc; 2373 2374 usbd_get_page(pcinp, 0, &buf_inp); 2375 2376 pinp = buf_inp.buffer; 2377 2378 rh_port = 0; 2379 route = 0; 2380 2381 /* figure out route string and root HUB port number */ 2382 2383 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2384 2385 if (hubdev->parent_hub == NULL) 2386 break; 2387 2388 depth = hubdev->parent_hub->depth; 2389 2390 /* 2391 * NOTE: HS/FS/LS devices and the SS root HUB can have 2392 * more than 15 ports 2393 */ 2394 2395 rh_port = hubdev->port_no; 2396 2397 if (depth == 0) 2398 break; 2399 2400 if (rh_port > 15) 2401 rh_port = 15; 2402 2403 if (depth < 6) 2404 route |= rh_port << (4 * (depth - 1)); 2405 } 2406 2407 DPRINTF("Route=0x%08x\n", route); 2408 2409 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2410 XHCI_SCTX_0_CTX_NUM_SET( 2411 sc->sc_hw.devs[index].context_num + 1); 2412 2413 switch (udev->speed) { 2414 case USB_SPEED_LOW: 2415 temp |= XHCI_SCTX_0_SPEED_SET(2); 2416 if (udev->parent_hs_hub != NULL && 2417 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2418 UDPROTO_HSHUBMTT) { 2419 DPRINTF("Device inherits MTT\n"); 2420 temp |= XHCI_SCTX_0_MTT_SET(1); 2421 } 2422 break; 2423 case USB_SPEED_HIGH: 2424 temp |= XHCI_SCTX_0_SPEED_SET(3); 2425 if (sc->sc_hw.devs[index].nports != 0 && 2426 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2427 DPRINTF("HUB supports MTT\n"); 2428 temp |= XHCI_SCTX_0_MTT_SET(1); 2429 } 2430 break; 2431 case USB_SPEED_FULL: 2432 temp |= XHCI_SCTX_0_SPEED_SET(1); 2433 if (udev->parent_hs_hub != NULL && 2434 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2435 UDPROTO_HSHUBMTT) { 2436 DPRINTF("Device inherits MTT\n"); 2437 temp |= XHCI_SCTX_0_MTT_SET(1); 2438 } 2439 break; 2440 default: 2441 temp |= XHCI_SCTX_0_SPEED_SET(4); 2442 break; 2443 } 2444 2445 is_hub = sc->sc_hw.devs[index].nports != 0 && 2446 (udev->speed == USB_SPEED_SUPER || 2447 udev->speed == USB_SPEED_HIGH); 2448 2449 if (is_hub) 2450 temp |= XHCI_SCTX_0_HUB_SET(1); 2451 2452 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2453 2454 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2455 2456 if (is_hub) { 2457 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2458 sc->sc_hw.devs[index].nports); 2459 } 2460 2461 switch (udev->speed) { 2462 case USB_SPEED_SUPER: 2463 switch (sc->sc_hw.devs[index].state) { 2464 case XHCI_ST_ADDRESSED: 2465 case XHCI_ST_CONFIGURED: 2466 /* enable power save */ 2467 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2468 break; 2469 default: 2470 /* disable power save */ 2471 break; 2472 } 2473 break; 2474 default: 2475 break; 2476 } 2477 2478 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2479 2480 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2481 2482 if (is_hub) { 2483 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2484 sc->sc_hw.devs[index].tt); 2485 } 2486 2487 hubdev = udev->parent_hs_hub; 2488 2489 /* check if we should activate the transaction translator */ 2490 switch (udev->speed) { 2491 case USB_SPEED_FULL: 2492 case USB_SPEED_LOW: 2493 if (hubdev != NULL) { 2494 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2495 hubdev->controller_slot_id); 2496 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2497 udev->hs_port_no); 2498 } 2499 break; 2500 default: 2501 break; 2502 } 2503 2504 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2505 2506 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) | 2507 XHCI_SCTX_3_SLOT_STATE_SET(0); 2508 2509 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2510 2511 #ifdef USB_DEBUG 2512 xhci_dump_device(sc, &pinp->ctx_slot); 2513 #endif 2514 usb_pc_cpu_flush(pcinp); 2515 2516 return (0); /* success */ 2517 } 2518 2519 static usb_error_t 2520 xhci_alloc_device_ext(struct usb_device *udev) 2521 { 2522 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2523 struct usb_page_search buf_dev; 2524 struct usb_page_search buf_ep; 2525 struct xhci_trb *trb; 2526 struct usb_page_cache *pc; 2527 struct usb_page *pg; 2528 uint64_t addr; 2529 uint8_t index; 2530 uint8_t i; 2531 2532 index = udev->controller_slot_id; 2533 2534 pc = &sc->sc_hw.devs[index].device_pc; 2535 pg = &sc->sc_hw.devs[index].device_pg; 2536 2537 /* need to initialize the page cache */ 2538 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2539 2540 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2541 (2 * sizeof(struct xhci_dev_ctx)) : 2542 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2543 goto error; 2544 2545 usbd_get_page(pc, 0, &buf_dev); 2546 2547 pc = &sc->sc_hw.devs[index].input_pc; 2548 pg = &sc->sc_hw.devs[index].input_pg; 2549 2550 /* need to initialize the page cache */ 2551 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2552 2553 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2554 (2 * sizeof(struct xhci_input_dev_ctx)) : 2555 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2556 goto error; 2557 } 2558 2559 pc = &sc->sc_hw.devs[index].endpoint_pc; 2560 pg = &sc->sc_hw.devs[index].endpoint_pg; 2561 2562 /* need to initialize the page cache */ 2563 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2564 2565 if (usb_pc_alloc_mem(pc, pg, 2566 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) { 2567 goto error; 2568 } 2569 2570 /* initialise all endpoint LINK TRBs */ 2571 2572 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2573 2574 /* lookup endpoint TRB ring */ 2575 usbd_get_page(pc, (uintptr_t)& 2576 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2577 2578 /* get TRB pointer */ 2579 trb = buf_ep.buffer; 2580 trb += XHCI_MAX_TRANSFERS - 1; 2581 2582 /* get TRB start address */ 2583 addr = buf_ep.physaddr; 2584 2585 /* create LINK TRB */ 2586 trb->qwTrb0 = htole64(addr); 2587 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2588 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2589 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2590 } 2591 2592 usb_pc_cpu_flush(pc); 2593 2594 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2595 2596 return (0); 2597 2598 error: 2599 xhci_free_device_ext(udev); 2600 2601 return (USB_ERR_NOMEM); 2602 } 2603 2604 static void 2605 xhci_free_device_ext(struct usb_device *udev) 2606 { 2607 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2608 uint8_t index; 2609 2610 index = udev->controller_slot_id; 2611 xhci_set_slot_pointer(sc, index, 0); 2612 2613 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2614 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2615 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2616 } 2617 2618 static struct xhci_endpoint_ext * 2619 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2620 { 2621 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2622 struct xhci_endpoint_ext *pepext; 2623 struct usb_page_cache *pc; 2624 struct usb_page_search buf_ep; 2625 uint8_t epno; 2626 uint8_t index; 2627 2628 epno = edesc->bEndpointAddress; 2629 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2630 epno |= UE_DIR_IN; 2631 2632 epno = XHCI_EPNO2EPID(epno); 2633 2634 index = udev->controller_slot_id; 2635 2636 pc = &sc->sc_hw.devs[index].endpoint_pc; 2637 2638 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2639 trb[epno][0], &buf_ep); 2640 2641 pepext = &sc->sc_hw.devs[index].endp[epno]; 2642 pepext->page_cache = pc; 2643 pepext->trb = buf_ep.buffer; 2644 pepext->physaddr = buf_ep.physaddr; 2645 2646 return (pepext); 2647 } 2648 2649 static void 2650 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2651 { 2652 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2653 uint8_t epno; 2654 uint8_t index; 2655 2656 epno = xfer->endpointno; 2657 if (xfer->flags_int.control_xfr) 2658 epno |= UE_DIR_IN; 2659 2660 epno = XHCI_EPNO2EPID(epno); 2661 index = xfer->xroot->udev->controller_slot_id; 2662 2663 if (xfer->xroot->udev->flags.self_suspended == 0) { 2664 XWRITE4(sc, door, XHCI_DOORBELL(index), 2665 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2666 } 2667 } 2668 2669 static void 2670 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2671 { 2672 struct xhci_endpoint_ext *pepext; 2673 2674 if (xfer->flags_int.bandwidth_reclaimed) { 2675 xfer->flags_int.bandwidth_reclaimed = 0; 2676 2677 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2678 xfer->endpoint->edesc); 2679 2680 pepext->trb_used[xfer->stream_id]--; 2681 2682 pepext->xfer[xfer->qh_pos] = NULL; 2683 2684 if (error && pepext->trb_running != 0) { 2685 pepext->trb_halted = 1; 2686 pepext->trb_running = 0; 2687 } 2688 } 2689 } 2690 2691 static usb_error_t 2692 xhci_transfer_insert(struct usb_xfer *xfer) 2693 { 2694 struct xhci_td *td_first; 2695 struct xhci_td *td_last; 2696 struct xhci_trb *trb_link; 2697 struct xhci_endpoint_ext *pepext; 2698 uint64_t addr; 2699 usb_stream_t id; 2700 uint8_t i; 2701 uint8_t inext; 2702 uint8_t trb_limit; 2703 2704 DPRINTFN(8, "\n"); 2705 2706 id = xfer->stream_id; 2707 2708 /* check if already inserted */ 2709 if (xfer->flags_int.bandwidth_reclaimed) { 2710 DPRINTFN(8, "Already in schedule\n"); 2711 return (0); 2712 } 2713 2714 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2715 xfer->endpoint->edesc); 2716 2717 td_first = xfer->td_transfer_first; 2718 td_last = xfer->td_transfer_last; 2719 addr = pepext->physaddr; 2720 2721 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2722 case UE_CONTROL: 2723 case UE_INTERRUPT: 2724 /* single buffered */ 2725 trb_limit = 1; 2726 break; 2727 default: 2728 /* multi buffered */ 2729 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2730 break; 2731 } 2732 2733 if (pepext->trb_used[id] >= trb_limit) { 2734 DPRINTFN(8, "Too many TDs queued.\n"); 2735 return (USB_ERR_NOMEM); 2736 } 2737 2738 /* check for stopped condition, after putting transfer on interrupt queue */ 2739 if (pepext->trb_running == 0) { 2740 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2741 2742 DPRINTFN(8, "Not running\n"); 2743 2744 /* start configuration */ 2745 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2746 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2747 return (0); 2748 } 2749 2750 pepext->trb_used[id]++; 2751 2752 /* get current TRB index */ 2753 i = pepext->trb_index[id]; 2754 2755 /* get next TRB index */ 2756 inext = (i + 1); 2757 2758 /* the last entry of the ring is a hardcoded link TRB */ 2759 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2760 inext = 0; 2761 2762 /* store next TRB index, before stream ID offset is added */ 2763 pepext->trb_index[id] = inext; 2764 2765 /* offset for stream */ 2766 i += id * XHCI_MAX_TRANSFERS; 2767 inext += id * XHCI_MAX_TRANSFERS; 2768 2769 /* compute terminating return address */ 2770 addr += (inext * sizeof(struct xhci_trb)); 2771 2772 /* compute link TRB pointer */ 2773 trb_link = td_last->td_trb + td_last->ntrb; 2774 2775 /* update next pointer of last link TRB */ 2776 trb_link->qwTrb0 = htole64(addr); 2777 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2778 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2779 XHCI_TRB_3_CYCLE_BIT | 2780 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2781 2782 #ifdef USB_DEBUG 2783 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2784 #endif 2785 usb_pc_cpu_flush(td_last->page_cache); 2786 2787 /* write ahead chain end marker */ 2788 2789 pepext->trb[inext].qwTrb0 = 0; 2790 pepext->trb[inext].dwTrb2 = 0; 2791 pepext->trb[inext].dwTrb3 = 0; 2792 2793 /* update next pointer of link TRB */ 2794 2795 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2796 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2797 2798 #ifdef USB_DEBUG 2799 xhci_dump_trb(&pepext->trb[i]); 2800 #endif 2801 usb_pc_cpu_flush(pepext->page_cache); 2802 2803 /* toggle cycle bit which activates the transfer chain */ 2804 2805 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2806 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2807 2808 usb_pc_cpu_flush(pepext->page_cache); 2809 2810 DPRINTF("qh_pos = %u\n", i); 2811 2812 pepext->xfer[i] = xfer; 2813 2814 xfer->qh_pos = i; 2815 2816 xfer->flags_int.bandwidth_reclaimed = 1; 2817 2818 xhci_endpoint_doorbell(xfer); 2819 2820 return (0); 2821 } 2822 2823 static void 2824 xhci_root_intr(struct xhci_softc *sc) 2825 { 2826 uint16_t i; 2827 2828 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2829 2830 /* clear any old interrupt data */ 2831 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2832 2833 for (i = 1; i <= sc->sc_noport; i++) { 2834 /* pick out CHANGE bits from the status register */ 2835 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2836 XHCI_PS_CSC | XHCI_PS_PEC | 2837 XHCI_PS_OCC | XHCI_PS_WRC | 2838 XHCI_PS_PRC | XHCI_PS_PLC | 2839 XHCI_PS_CEC)) { 2840 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2841 DPRINTF("port %d changed\n", i); 2842 } 2843 } 2844 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2845 sizeof(sc->sc_hub_idata)); 2846 } 2847 2848 /*------------------------------------------------------------------------* 2849 * xhci_device_done - XHCI done handler 2850 * 2851 * NOTE: This function can be called two times in a row on 2852 * the same USB transfer. From close and from interrupt. 2853 *------------------------------------------------------------------------*/ 2854 static void 2855 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2856 { 2857 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2858 xfer, xfer->endpoint, error); 2859 2860 /* remove transfer from HW queue */ 2861 xhci_transfer_remove(xfer, error); 2862 2863 /* dequeue transfer and start next transfer */ 2864 usbd_transfer_done(xfer, error); 2865 } 2866 2867 /*------------------------------------------------------------------------* 2868 * XHCI data transfer support (generic type) 2869 *------------------------------------------------------------------------*/ 2870 static void 2871 xhci_device_generic_open(struct usb_xfer *xfer) 2872 { 2873 if (xfer->flags_int.isochronous_xfr) { 2874 switch (xfer->xroot->udev->speed) { 2875 case USB_SPEED_FULL: 2876 break; 2877 default: 2878 usb_hs_bandwidth_alloc(xfer); 2879 break; 2880 } 2881 } 2882 } 2883 2884 static void 2885 xhci_device_generic_close(struct usb_xfer *xfer) 2886 { 2887 DPRINTF("\n"); 2888 2889 xhci_device_done(xfer, USB_ERR_CANCELLED); 2890 2891 if (xfer->flags_int.isochronous_xfr) { 2892 switch (xfer->xroot->udev->speed) { 2893 case USB_SPEED_FULL: 2894 break; 2895 default: 2896 usb_hs_bandwidth_free(xfer); 2897 break; 2898 } 2899 } 2900 } 2901 2902 static void 2903 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 2904 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 2905 { 2906 struct usb_xfer *xfer; 2907 2908 /* check if there is a current transfer */ 2909 xfer = ep->endpoint_q[stream_id].curr; 2910 if (xfer == NULL) 2911 return; 2912 2913 /* 2914 * Check if the current transfer is started and then pickup 2915 * the next one, if any. Else wait for next start event due to 2916 * block on failure feature. 2917 */ 2918 if (!xfer->flags_int.bandwidth_reclaimed) 2919 return; 2920 2921 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 2922 if (xfer == NULL) { 2923 /* 2924 * In case of enter we have to consider that the 2925 * transfer is queued by the USB core after the enter 2926 * method is called. 2927 */ 2928 xfer = enter_xfer; 2929 2930 if (xfer == NULL) 2931 return; 2932 } 2933 2934 /* try to multi buffer */ 2935 xhci_transfer_insert(xfer); 2936 } 2937 2938 static void 2939 xhci_device_generic_enter(struct usb_xfer *xfer) 2940 { 2941 DPRINTF("\n"); 2942 2943 /* setup TD's and QH */ 2944 xhci_setup_generic_chain(xfer); 2945 2946 xhci_device_generic_multi_enter(xfer->endpoint, 2947 xfer->stream_id, xfer); 2948 } 2949 2950 static void 2951 xhci_device_generic_start(struct usb_xfer *xfer) 2952 { 2953 DPRINTF("\n"); 2954 2955 /* try to insert xfer on HW queue */ 2956 xhci_transfer_insert(xfer); 2957 2958 /* try to multi buffer */ 2959 xhci_device_generic_multi_enter(xfer->endpoint, 2960 xfer->stream_id, NULL); 2961 2962 /* add transfer last on interrupt queue */ 2963 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2964 2965 /* start timeout, if any */ 2966 if (xfer->timeout != 0) 2967 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 2968 } 2969 2970 struct usb_pipe_methods xhci_device_generic_methods = 2971 { 2972 .open = xhci_device_generic_open, 2973 .close = xhci_device_generic_close, 2974 .enter = xhci_device_generic_enter, 2975 .start = xhci_device_generic_start, 2976 }; 2977 2978 /*------------------------------------------------------------------------* 2979 * xhci root HUB support 2980 *------------------------------------------------------------------------* 2981 * Simulate a hardware HUB by handling all the necessary requests. 2982 *------------------------------------------------------------------------*/ 2983 2984 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 2985 2986 static const 2987 struct usb_device_descriptor xhci_devd = 2988 { 2989 .bLength = sizeof(xhci_devd), 2990 .bDescriptorType = UDESC_DEVICE, /* type */ 2991 HSETW(.bcdUSB, 0x0300), /* USB version */ 2992 .bDeviceClass = UDCLASS_HUB, /* class */ 2993 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 2994 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 2995 .bMaxPacketSize = 9, /* max packet size */ 2996 HSETW(.idVendor, 0x0000), /* vendor */ 2997 HSETW(.idProduct, 0x0000), /* product */ 2998 HSETW(.bcdDevice, 0x0100), /* device version */ 2999 .iManufacturer = 1, 3000 .iProduct = 2, 3001 .iSerialNumber = 0, 3002 .bNumConfigurations = 1, /* # of configurations */ 3003 }; 3004 3005 static const 3006 struct xhci_bos_desc xhci_bosd = { 3007 .bosd = { 3008 .bLength = sizeof(xhci_bosd.bosd), 3009 .bDescriptorType = UDESC_BOS, 3010 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3011 .bNumDeviceCaps = 3, 3012 }, 3013 .usb2extd = { 3014 .bLength = sizeof(xhci_bosd.usb2extd), 3015 .bDescriptorType = 1, 3016 .bDevCapabilityType = 2, 3017 .bmAttributes[0] = 2, 3018 }, 3019 .usbdcd = { 3020 .bLength = sizeof(xhci_bosd.usbdcd), 3021 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3022 .bDevCapabilityType = 3, 3023 .bmAttributes = 0, /* XXX */ 3024 HSETW(.wSpeedsSupported, 0x000C), 3025 .bFunctionalitySupport = 8, 3026 .bU1DevExitLat = 255, /* dummy - not used */ 3027 .wU2DevExitLat = { 0x00, 0x08 }, 3028 }, 3029 .cidd = { 3030 .bLength = sizeof(xhci_bosd.cidd), 3031 .bDescriptorType = 1, 3032 .bDevCapabilityType = 4, 3033 .bReserved = 0, 3034 .bContainerID = 0, /* XXX */ 3035 }, 3036 }; 3037 3038 static const 3039 struct xhci_config_desc xhci_confd = { 3040 .confd = { 3041 .bLength = sizeof(xhci_confd.confd), 3042 .bDescriptorType = UDESC_CONFIG, 3043 .wTotalLength[0] = sizeof(xhci_confd), 3044 .bNumInterface = 1, 3045 .bConfigurationValue = 1, 3046 .iConfiguration = 0, 3047 .bmAttributes = UC_SELF_POWERED, 3048 .bMaxPower = 0 /* max power */ 3049 }, 3050 .ifcd = { 3051 .bLength = sizeof(xhci_confd.ifcd), 3052 .bDescriptorType = UDESC_INTERFACE, 3053 .bNumEndpoints = 1, 3054 .bInterfaceClass = UICLASS_HUB, 3055 .bInterfaceSubClass = UISUBCLASS_HUB, 3056 .bInterfaceProtocol = 0, 3057 }, 3058 .endpd = { 3059 .bLength = sizeof(xhci_confd.endpd), 3060 .bDescriptorType = UDESC_ENDPOINT, 3061 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3062 .bmAttributes = UE_INTERRUPT, 3063 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3064 .bInterval = 255, 3065 }, 3066 .endpcd = { 3067 .bLength = sizeof(xhci_confd.endpcd), 3068 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3069 .bMaxBurst = 0, 3070 .bmAttributes = 0, 3071 }, 3072 }; 3073 3074 static const 3075 struct usb_hub_ss_descriptor xhci_hubd = { 3076 .bLength = sizeof(xhci_hubd), 3077 .bDescriptorType = UDESC_SS_HUB, 3078 }; 3079 3080 static usb_error_t 3081 xhci_roothub_exec(struct usb_device *udev, 3082 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3083 { 3084 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3085 const char *str_ptr; 3086 const void *ptr; 3087 uint32_t port; 3088 uint32_t v; 3089 uint16_t len; 3090 uint16_t i; 3091 uint16_t value; 3092 uint16_t index; 3093 uint8_t j; 3094 usb_error_t err; 3095 3096 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3097 3098 /* buffer reset */ 3099 ptr = (const void *)&sc->sc_hub_desc; 3100 len = 0; 3101 err = 0; 3102 3103 value = UGETW(req->wValue); 3104 index = UGETW(req->wIndex); 3105 3106 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3107 "wValue=0x%04x wIndex=0x%04x\n", 3108 req->bmRequestType, req->bRequest, 3109 UGETW(req->wLength), value, index); 3110 3111 #define C(x,y) ((x) | ((y) << 8)) 3112 switch (C(req->bRequest, req->bmRequestType)) { 3113 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3114 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3115 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3116 /* 3117 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3118 * for the integrated root hub. 3119 */ 3120 break; 3121 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3122 len = 1; 3123 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3124 break; 3125 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3126 switch (value >> 8) { 3127 case UDESC_DEVICE: 3128 if ((value & 0xff) != 0) { 3129 err = USB_ERR_IOERROR; 3130 goto done; 3131 } 3132 len = sizeof(xhci_devd); 3133 ptr = (const void *)&xhci_devd; 3134 break; 3135 3136 case UDESC_BOS: 3137 if ((value & 0xff) != 0) { 3138 err = USB_ERR_IOERROR; 3139 goto done; 3140 } 3141 len = sizeof(xhci_bosd); 3142 ptr = (const void *)&xhci_bosd; 3143 break; 3144 3145 case UDESC_CONFIG: 3146 if ((value & 0xff) != 0) { 3147 err = USB_ERR_IOERROR; 3148 goto done; 3149 } 3150 len = sizeof(xhci_confd); 3151 ptr = (const void *)&xhci_confd; 3152 break; 3153 3154 case UDESC_STRING: 3155 switch (value & 0xff) { 3156 case 0: /* Language table */ 3157 str_ptr = "\001"; 3158 break; 3159 3160 case 1: /* Vendor */ 3161 str_ptr = sc->sc_vendor; 3162 break; 3163 3164 case 2: /* Product */ 3165 str_ptr = "XHCI root HUB"; 3166 break; 3167 3168 default: 3169 str_ptr = ""; 3170 break; 3171 } 3172 3173 len = usb_make_str_desc( 3174 sc->sc_hub_desc.temp, 3175 sizeof(sc->sc_hub_desc.temp), 3176 str_ptr); 3177 break; 3178 3179 default: 3180 err = USB_ERR_IOERROR; 3181 goto done; 3182 } 3183 break; 3184 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3185 len = 1; 3186 sc->sc_hub_desc.temp[0] = 0; 3187 break; 3188 case C(UR_GET_STATUS, UT_READ_DEVICE): 3189 len = 2; 3190 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3191 break; 3192 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3193 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3194 len = 2; 3195 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3196 break; 3197 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3198 if (value >= XHCI_MAX_DEVICES) { 3199 err = USB_ERR_IOERROR; 3200 goto done; 3201 } 3202 break; 3203 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3204 if (value != 0 && value != 1) { 3205 err = USB_ERR_IOERROR; 3206 goto done; 3207 } 3208 sc->sc_conf = value; 3209 break; 3210 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3211 break; 3212 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3213 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3214 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3215 err = USB_ERR_IOERROR; 3216 goto done; 3217 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3218 break; 3219 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3220 break; 3221 /* Hub requests */ 3222 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3223 break; 3224 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3225 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3226 3227 if ((index < 1) || 3228 (index > sc->sc_noport)) { 3229 err = USB_ERR_IOERROR; 3230 goto done; 3231 } 3232 port = XHCI_PORTSC(index); 3233 3234 v = XREAD4(sc, oper, port); 3235 i = XHCI_PS_PLS_GET(v); 3236 v &= ~XHCI_PS_CLEAR; 3237 3238 switch (value) { 3239 case UHF_C_BH_PORT_RESET: 3240 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3241 break; 3242 case UHF_C_PORT_CONFIG_ERROR: 3243 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3244 break; 3245 case UHF_C_PORT_SUSPEND: 3246 case UHF_C_PORT_LINK_STATE: 3247 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3248 break; 3249 case UHF_C_PORT_CONNECTION: 3250 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3251 break; 3252 case UHF_C_PORT_ENABLE: 3253 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3254 break; 3255 case UHF_C_PORT_OVER_CURRENT: 3256 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3257 break; 3258 case UHF_C_PORT_RESET: 3259 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3260 break; 3261 case UHF_PORT_ENABLE: 3262 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3263 break; 3264 case UHF_PORT_POWER: 3265 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3266 break; 3267 case UHF_PORT_INDICATOR: 3268 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3269 break; 3270 case UHF_PORT_SUSPEND: 3271 3272 /* U3 -> U15 */ 3273 if (i == 3) { 3274 XWRITE4(sc, oper, port, v | 3275 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3276 } 3277 3278 /* wait 20ms for resume sequence to complete */ 3279 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3280 3281 /* U0 */ 3282 XWRITE4(sc, oper, port, v | 3283 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3284 break; 3285 default: 3286 err = USB_ERR_IOERROR; 3287 goto done; 3288 } 3289 break; 3290 3291 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3292 if ((value & 0xff) != 0) { 3293 err = USB_ERR_IOERROR; 3294 goto done; 3295 } 3296 3297 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3298 3299 sc->sc_hub_desc.hubd = xhci_hubd; 3300 3301 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3302 3303 if (XHCI_HCS0_PPC(v)) 3304 i = UHD_PWR_INDIVIDUAL; 3305 else 3306 i = UHD_PWR_GANGED; 3307 3308 if (XHCI_HCS0_PIND(v)) 3309 i |= UHD_PORT_IND; 3310 3311 i |= UHD_OC_INDIVIDUAL; 3312 3313 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3314 3315 /* see XHCI section 5.4.9: */ 3316 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3317 3318 for (j = 1; j <= sc->sc_noport; j++) { 3319 3320 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3321 if (v & XHCI_PS_DR) { 3322 sc->sc_hub_desc.hubd. 3323 DeviceRemovable[j / 8] |= 1U << (j % 8); 3324 } 3325 } 3326 len = sc->sc_hub_desc.hubd.bLength; 3327 break; 3328 3329 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3330 len = 16; 3331 memset(sc->sc_hub_desc.temp, 0, 16); 3332 break; 3333 3334 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3335 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3336 3337 if ((index < 1) || 3338 (index > sc->sc_noport)) { 3339 err = USB_ERR_IOERROR; 3340 goto done; 3341 } 3342 3343 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3344 3345 DPRINTFN(9, "port status=0x%08x\n", v); 3346 3347 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3348 3349 switch (XHCI_PS_SPEED_GET(v)) { 3350 case 3: 3351 i |= UPS_HIGH_SPEED; 3352 break; 3353 case 2: 3354 i |= UPS_LOW_SPEED; 3355 break; 3356 case 1: 3357 /* FULL speed */ 3358 break; 3359 default: 3360 i |= UPS_OTHER_SPEED; 3361 break; 3362 } 3363 3364 if (v & XHCI_PS_CCS) 3365 i |= UPS_CURRENT_CONNECT_STATUS; 3366 if (v & XHCI_PS_PED) 3367 i |= UPS_PORT_ENABLED; 3368 if (v & XHCI_PS_OCA) 3369 i |= UPS_OVERCURRENT_INDICATOR; 3370 if (v & XHCI_PS_PR) 3371 i |= UPS_RESET; 3372 if (v & XHCI_PS_PP) { 3373 /* 3374 * The USB 3.0 RH is using the 3375 * USB 2.0's power bit 3376 */ 3377 i |= UPS_PORT_POWER; 3378 } 3379 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3380 3381 i = 0; 3382 if (v & XHCI_PS_CSC) 3383 i |= UPS_C_CONNECT_STATUS; 3384 if (v & XHCI_PS_PEC) 3385 i |= UPS_C_PORT_ENABLED; 3386 if (v & XHCI_PS_OCC) 3387 i |= UPS_C_OVERCURRENT_INDICATOR; 3388 if (v & XHCI_PS_WRC) 3389 i |= UPS_C_BH_PORT_RESET; 3390 if (v & XHCI_PS_PRC) 3391 i |= UPS_C_PORT_RESET; 3392 if (v & XHCI_PS_PLC) 3393 i |= UPS_C_PORT_LINK_STATE; 3394 if (v & XHCI_PS_CEC) 3395 i |= UPS_C_PORT_CONFIG_ERROR; 3396 3397 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3398 len = sizeof(sc->sc_hub_desc.ps); 3399 break; 3400 3401 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3402 err = USB_ERR_IOERROR; 3403 goto done; 3404 3405 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3406 break; 3407 3408 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3409 3410 i = index >> 8; 3411 index &= 0x00FF; 3412 3413 if ((index < 1) || 3414 (index > sc->sc_noport)) { 3415 err = USB_ERR_IOERROR; 3416 goto done; 3417 } 3418 3419 port = XHCI_PORTSC(index); 3420 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3421 3422 switch (value) { 3423 case UHF_PORT_U1_TIMEOUT: 3424 if (XHCI_PS_SPEED_GET(v) != 4) { 3425 err = USB_ERR_IOERROR; 3426 goto done; 3427 } 3428 port = XHCI_PORTPMSC(index); 3429 v = XREAD4(sc, oper, port); 3430 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3431 v |= XHCI_PM3_U1TO_SET(i); 3432 XWRITE4(sc, oper, port, v); 3433 break; 3434 case UHF_PORT_U2_TIMEOUT: 3435 if (XHCI_PS_SPEED_GET(v) != 4) { 3436 err = USB_ERR_IOERROR; 3437 goto done; 3438 } 3439 port = XHCI_PORTPMSC(index); 3440 v = XREAD4(sc, oper, port); 3441 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3442 v |= XHCI_PM3_U2TO_SET(i); 3443 XWRITE4(sc, oper, port, v); 3444 break; 3445 case UHF_BH_PORT_RESET: 3446 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3447 break; 3448 case UHF_PORT_LINK_STATE: 3449 XWRITE4(sc, oper, port, v | 3450 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3451 /* 4ms settle time */ 3452 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3453 break; 3454 case UHF_PORT_ENABLE: 3455 DPRINTFN(3, "set port enable %d\n", index); 3456 break; 3457 case UHF_PORT_SUSPEND: 3458 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3459 j = XHCI_PS_SPEED_GET(v); 3460 if ((j < 1) || (j > 3)) { 3461 /* non-supported speed */ 3462 err = USB_ERR_IOERROR; 3463 goto done; 3464 } 3465 XWRITE4(sc, oper, port, v | 3466 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3467 break; 3468 case UHF_PORT_RESET: 3469 DPRINTFN(6, "reset port %d\n", index); 3470 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3471 break; 3472 case UHF_PORT_POWER: 3473 DPRINTFN(3, "set port power %d\n", index); 3474 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3475 break; 3476 case UHF_PORT_TEST: 3477 DPRINTFN(3, "set port test %d\n", index); 3478 break; 3479 case UHF_PORT_INDICATOR: 3480 DPRINTFN(3, "set port indicator %d\n", index); 3481 3482 v &= ~XHCI_PS_PIC_SET(3); 3483 v |= XHCI_PS_PIC_SET(1); 3484 3485 XWRITE4(sc, oper, port, v); 3486 break; 3487 default: 3488 err = USB_ERR_IOERROR; 3489 goto done; 3490 } 3491 break; 3492 3493 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3494 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3495 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3496 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3497 break; 3498 default: 3499 err = USB_ERR_IOERROR; 3500 goto done; 3501 } 3502 done: 3503 *plength = len; 3504 *pptr = ptr; 3505 return (err); 3506 } 3507 3508 static void 3509 xhci_xfer_setup(struct usb_setup_params *parm) 3510 { 3511 struct usb_page_search page_info; 3512 struct usb_page_cache *pc; 3513 struct xhci_softc *sc; 3514 struct usb_xfer *xfer; 3515 void *last_obj; 3516 uint32_t ntd; 3517 uint32_t n; 3518 3519 sc = XHCI_BUS2SC(parm->udev->bus); 3520 xfer = parm->curr_xfer; 3521 3522 /* 3523 * The proof for the "ntd" formula is illustrated like this: 3524 * 3525 * +------------------------------------+ 3526 * | | 3527 * | |remainder -> | 3528 * | +-----+---+ | 3529 * | | xxx | x | frm 0 | 3530 * | +-----+---++ | 3531 * | | xxx | xx | frm 1 | 3532 * | +-----+----+ | 3533 * | ... | 3534 * +------------------------------------+ 3535 * 3536 * "xxx" means a completely full USB transfer descriptor 3537 * 3538 * "x" and "xx" means a short USB packet 3539 * 3540 * For the remainder of an USB transfer modulo 3541 * "max_data_length" we need two USB transfer descriptors. 3542 * One to transfer the remaining data and one to finalise with 3543 * a zero length packet in case the "force_short_xfer" flag is 3544 * set. We only need two USB transfer descriptors in the case 3545 * where the transfer length of the first one is a factor of 3546 * "max_frame_size". The rest of the needed USB transfer 3547 * descriptors is given by the buffer size divided by the 3548 * maximum data payload. 3549 */ 3550 parm->hc_max_packet_size = 0x400; 3551 parm->hc_max_packet_count = 16 * 3; 3552 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3553 3554 xfer->flags_int.bdma_enable = 1; 3555 3556 usbd_transfer_setup_sub(parm); 3557 3558 if (xfer->flags_int.isochronous_xfr) { 3559 ntd = ((1 * xfer->nframes) 3560 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3561 } else if (xfer->flags_int.control_xfr) { 3562 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3563 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3564 } else { 3565 ntd = ((2 * xfer->nframes) 3566 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3567 } 3568 3569 alloc_dma_set: 3570 3571 if (parm->err) 3572 return; 3573 3574 /* 3575 * Allocate queue heads and transfer descriptors 3576 */ 3577 last_obj = NULL; 3578 3579 if (usbd_transfer_setup_sub_malloc( 3580 parm, &pc, sizeof(struct xhci_td), 3581 XHCI_TD_ALIGN, ntd)) { 3582 parm->err = USB_ERR_NOMEM; 3583 return; 3584 } 3585 if (parm->buf) { 3586 for (n = 0; n != ntd; n++) { 3587 struct xhci_td *td; 3588 3589 usbd_get_page(pc + n, 0, &page_info); 3590 3591 td = page_info.buffer; 3592 3593 /* init TD */ 3594 td->td_self = page_info.physaddr; 3595 td->obj_next = last_obj; 3596 td->page_cache = pc + n; 3597 3598 last_obj = td; 3599 3600 usb_pc_cpu_flush(pc + n); 3601 } 3602 } 3603 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3604 3605 if (!xfer->flags_int.curr_dma_set) { 3606 xfer->flags_int.curr_dma_set = 1; 3607 goto alloc_dma_set; 3608 } 3609 } 3610 3611 static usb_error_t 3612 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3613 { 3614 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3615 struct usb_page_search buf_inp; 3616 struct usb_device *udev; 3617 struct xhci_endpoint_ext *pepext; 3618 struct usb_endpoint_descriptor *edesc; 3619 struct usb_page_cache *pcinp; 3620 usb_error_t err; 3621 usb_stream_t stream_id; 3622 uint8_t index; 3623 uint8_t epno; 3624 3625 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3626 xfer->endpoint->edesc); 3627 3628 udev = xfer->xroot->udev; 3629 index = udev->controller_slot_id; 3630 3631 pcinp = &sc->sc_hw.devs[index].input_pc; 3632 3633 usbd_get_page(pcinp, 0, &buf_inp); 3634 3635 edesc = xfer->endpoint->edesc; 3636 3637 epno = edesc->bEndpointAddress; 3638 stream_id = xfer->stream_id; 3639 3640 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3641 epno |= UE_DIR_IN; 3642 3643 epno = XHCI_EPNO2EPID(epno); 3644 3645 if (epno == 0) 3646 return (USB_ERR_NO_PIPE); /* invalid */ 3647 3648 XHCI_CMD_LOCK(sc); 3649 3650 /* configure endpoint */ 3651 3652 err = xhci_configure_endpoint_by_xfer(xfer); 3653 3654 if (err != 0) { 3655 XHCI_CMD_UNLOCK(sc); 3656 return (err); 3657 } 3658 3659 /* 3660 * Get the endpoint into the stopped state according to the 3661 * endpoint context state diagram in the XHCI specification: 3662 */ 3663 3664 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3665 3666 if (err != 0) 3667 DPRINTF("Could not stop endpoint %u\n", epno); 3668 3669 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3670 3671 if (err != 0) 3672 DPRINTF("Could not reset endpoint %u\n", epno); 3673 3674 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3675 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3676 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3677 stream_id, epno, index); 3678 3679 if (err != 0) 3680 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3681 3682 /* 3683 * Get the endpoint into the running state according to the 3684 * endpoint context state diagram in the XHCI specification: 3685 */ 3686 3687 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3688 3689 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3690 3691 if (err != 0) 3692 DPRINTF("Could not configure endpoint %u\n", epno); 3693 3694 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3695 3696 if (err != 0) 3697 DPRINTF("Could not configure endpoint %u\n", epno); 3698 3699 XHCI_CMD_UNLOCK(sc); 3700 3701 return (0); 3702 } 3703 3704 static void 3705 xhci_xfer_unsetup(struct usb_xfer *xfer) 3706 { 3707 return; 3708 } 3709 3710 static void 3711 xhci_start_dma_delay(struct usb_xfer *xfer) 3712 { 3713 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3714 3715 /* put transfer on interrupt queue (again) */ 3716 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3717 3718 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3719 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3720 } 3721 3722 static void 3723 xhci_configure_msg(struct usb_proc_msg *pm) 3724 { 3725 struct xhci_softc *sc; 3726 struct xhci_endpoint_ext *pepext; 3727 struct usb_xfer *xfer; 3728 3729 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3730 3731 restart: 3732 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3733 3734 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3735 xfer->endpoint->edesc); 3736 3737 if ((pepext->trb_halted != 0) || 3738 (pepext->trb_running == 0)) { 3739 3740 uint16_t i; 3741 3742 /* clear halted and running */ 3743 pepext->trb_halted = 0; 3744 pepext->trb_running = 0; 3745 3746 /* nuke remaining buffered transfers */ 3747 3748 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3749 XHCI_MAX_STREAMS); i++) { 3750 /* 3751 * NOTE: We need to use the timeout 3752 * error code here else existing 3753 * isochronous clients can get 3754 * confused: 3755 */ 3756 if (pepext->xfer[i] != NULL) { 3757 xhci_device_done(pepext->xfer[i], 3758 USB_ERR_TIMEOUT); 3759 } 3760 } 3761 3762 /* 3763 * NOTE: The USB transfer cannot vanish in 3764 * this state! 3765 */ 3766 3767 USB_BUS_UNLOCK(&sc->sc_bus); 3768 3769 xhci_configure_reset_endpoint(xfer); 3770 3771 USB_BUS_LOCK(&sc->sc_bus); 3772 3773 /* check if halted is still cleared */ 3774 if (pepext->trb_halted == 0) { 3775 pepext->trb_running = 1; 3776 memset(pepext->trb_index, 0, 3777 sizeof(pepext->trb_index)); 3778 } 3779 goto restart; 3780 } 3781 3782 if (xfer->flags_int.did_dma_delay) { 3783 3784 /* remove transfer from interrupt queue (again) */ 3785 usbd_transfer_dequeue(xfer); 3786 3787 /* we are finally done */ 3788 usb_dma_delay_done_cb(xfer); 3789 3790 /* queue changed - restart */ 3791 goto restart; 3792 } 3793 } 3794 3795 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3796 3797 /* try to insert xfer on HW queue */ 3798 xhci_transfer_insert(xfer); 3799 3800 /* try to multi buffer */ 3801 xhci_device_generic_multi_enter(xfer->endpoint, 3802 xfer->stream_id, NULL); 3803 } 3804 } 3805 3806 static void 3807 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3808 struct usb_endpoint *ep) 3809 { 3810 struct xhci_endpoint_ext *pepext; 3811 3812 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3813 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3814 3815 if (udev->parent_hub == NULL) { 3816 /* root HUB has special endpoint handling */ 3817 return; 3818 } 3819 3820 ep->methods = &xhci_device_generic_methods; 3821 3822 pepext = xhci_get_endpoint_ext(udev, edesc); 3823 3824 USB_BUS_LOCK(udev->bus); 3825 pepext->trb_halted = 1; 3826 pepext->trb_running = 0; 3827 USB_BUS_UNLOCK(udev->bus); 3828 } 3829 3830 static void 3831 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3832 { 3833 3834 } 3835 3836 static void 3837 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3838 { 3839 struct xhci_endpoint_ext *pepext; 3840 3841 DPRINTF("\n"); 3842 3843 if (udev->flags.usb_mode != USB_MODE_HOST) { 3844 /* not supported */ 3845 return; 3846 } 3847 if (udev->parent_hub == NULL) { 3848 /* root HUB has special endpoint handling */ 3849 return; 3850 } 3851 3852 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3853 3854 USB_BUS_LOCK(udev->bus); 3855 pepext->trb_halted = 1; 3856 pepext->trb_running = 0; 3857 USB_BUS_UNLOCK(udev->bus); 3858 } 3859 3860 static usb_error_t 3861 xhci_device_init(struct usb_device *udev) 3862 { 3863 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3864 usb_error_t err; 3865 uint8_t temp; 3866 3867 /* no init for root HUB */ 3868 if (udev->parent_hub == NULL) 3869 return (0); 3870 3871 XHCI_CMD_LOCK(sc); 3872 3873 /* set invalid default */ 3874 3875 udev->controller_slot_id = sc->sc_noslot + 1; 3876 3877 /* try to get a new slot ID from the XHCI */ 3878 3879 err = xhci_cmd_enable_slot(sc, &temp); 3880 3881 if (err) { 3882 XHCI_CMD_UNLOCK(sc); 3883 return (err); 3884 } 3885 3886 if (temp > sc->sc_noslot) { 3887 XHCI_CMD_UNLOCK(sc); 3888 return (USB_ERR_BAD_ADDRESS); 3889 } 3890 3891 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 3892 DPRINTF("slot %u already allocated.\n", temp); 3893 XHCI_CMD_UNLOCK(sc); 3894 return (USB_ERR_BAD_ADDRESS); 3895 } 3896 3897 /* store slot ID for later reference */ 3898 3899 udev->controller_slot_id = temp; 3900 3901 /* reset data structure */ 3902 3903 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 3904 3905 /* set mark slot allocated */ 3906 3907 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 3908 3909 err = xhci_alloc_device_ext(udev); 3910 3911 XHCI_CMD_UNLOCK(sc); 3912 3913 /* get device into default state */ 3914 3915 if (err == 0) 3916 err = xhci_set_address(udev, NULL, 0); 3917 3918 return (err); 3919 } 3920 3921 static void 3922 xhci_device_uninit(struct usb_device *udev) 3923 { 3924 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3925 uint8_t index; 3926 3927 /* no init for root HUB */ 3928 if (udev->parent_hub == NULL) 3929 return; 3930 3931 XHCI_CMD_LOCK(sc); 3932 3933 index = udev->controller_slot_id; 3934 3935 if (index <= sc->sc_noslot) { 3936 xhci_cmd_disable_slot(sc, index); 3937 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 3938 3939 /* free device extension */ 3940 xhci_free_device_ext(udev); 3941 } 3942 3943 XHCI_CMD_UNLOCK(sc); 3944 } 3945 3946 static void 3947 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3948 { 3949 /* 3950 * Wait until the hardware has finished any possible use of 3951 * the transfer descriptor(s) 3952 */ 3953 *pus = 2048; /* microseconds */ 3954 } 3955 3956 static void 3957 xhci_device_resume(struct usb_device *udev) 3958 { 3959 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3960 uint8_t index; 3961 uint8_t n; 3962 uint8_t p; 3963 3964 DPRINTF("\n"); 3965 3966 /* check for root HUB */ 3967 if (udev->parent_hub == NULL) 3968 return; 3969 3970 index = udev->controller_slot_id; 3971 3972 XHCI_CMD_LOCK(sc); 3973 3974 /* blindly resume all endpoints */ 3975 3976 USB_BUS_LOCK(udev->bus); 3977 3978 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3979 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 3980 XWRITE4(sc, door, XHCI_DOORBELL(index), 3981 n | XHCI_DB_SID_SET(p)); 3982 } 3983 } 3984 3985 USB_BUS_UNLOCK(udev->bus); 3986 3987 XHCI_CMD_UNLOCK(sc); 3988 } 3989 3990 static void 3991 xhci_device_suspend(struct usb_device *udev) 3992 { 3993 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3994 uint8_t index; 3995 uint8_t n; 3996 usb_error_t err; 3997 3998 DPRINTF("\n"); 3999 4000 /* check for root HUB */ 4001 if (udev->parent_hub == NULL) 4002 return; 4003 4004 index = udev->controller_slot_id; 4005 4006 XHCI_CMD_LOCK(sc); 4007 4008 /* blindly suspend all endpoints */ 4009 4010 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4011 err = xhci_cmd_stop_ep(sc, 1, n, index); 4012 if (err != 0) { 4013 DPRINTF("Failed to suspend endpoint " 4014 "%u on slot %u (ignored).\n", n, index); 4015 } 4016 } 4017 4018 XHCI_CMD_UNLOCK(sc); 4019 } 4020 4021 static void 4022 xhci_set_hw_power(struct usb_bus *bus) 4023 { 4024 DPRINTF("\n"); 4025 } 4026 4027 static void 4028 xhci_device_state_change(struct usb_device *udev) 4029 { 4030 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4031 struct usb_page_search buf_inp; 4032 usb_error_t err; 4033 uint8_t index; 4034 4035 /* check for root HUB */ 4036 if (udev->parent_hub == NULL) 4037 return; 4038 4039 index = udev->controller_slot_id; 4040 4041 DPRINTF("\n"); 4042 4043 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4044 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4045 &sc->sc_hw.devs[index].tt); 4046 if (err != 0) 4047 sc->sc_hw.devs[index].nports = 0; 4048 } 4049 4050 XHCI_CMD_LOCK(sc); 4051 4052 switch (usb_get_device_state(udev)) { 4053 case USB_STATE_POWERED: 4054 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4055 break; 4056 4057 /* set default state */ 4058 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4059 4060 /* reset number of contexts */ 4061 sc->sc_hw.devs[index].context_num = 0; 4062 4063 err = xhci_cmd_reset_dev(sc, index); 4064 4065 if (err != 0) { 4066 DPRINTF("Device reset failed " 4067 "for slot %u.\n", index); 4068 } 4069 break; 4070 4071 case USB_STATE_ADDRESSED: 4072 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4073 break; 4074 4075 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4076 4077 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4078 4079 if (err) { 4080 DPRINTF("Failed to deconfigure " 4081 "slot %u.\n", index); 4082 } 4083 break; 4084 4085 case USB_STATE_CONFIGURED: 4086 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4087 break; 4088 4089 /* set configured state */ 4090 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4091 4092 /* reset number of contexts */ 4093 sc->sc_hw.devs[index].context_num = 0; 4094 4095 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4096 4097 xhci_configure_mask(udev, 3, 0); 4098 4099 err = xhci_configure_device(udev); 4100 if (err != 0) { 4101 DPRINTF("Could not configure device " 4102 "at slot %u.\n", index); 4103 } 4104 4105 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4106 if (err != 0) { 4107 DPRINTF("Could not evaluate device " 4108 "context at slot %u.\n", index); 4109 } 4110 break; 4111 4112 default: 4113 break; 4114 } 4115 XHCI_CMD_UNLOCK(sc); 4116 } 4117 4118 static usb_error_t 4119 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4120 uint8_t ep_mode) 4121 { 4122 switch (ep_mode) { 4123 case USB_EP_MODE_DEFAULT: 4124 return (0); 4125 case USB_EP_MODE_STREAMS: 4126 if (xhcistreams == 0 || 4127 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4128 udev->speed != USB_SPEED_SUPER) 4129 return (USB_ERR_INVAL); 4130 return (0); 4131 default: 4132 return (USB_ERR_INVAL); 4133 } 4134 } 4135 4136 struct usb_bus_methods xhci_bus_methods = { 4137 .endpoint_init = xhci_ep_init, 4138 .endpoint_uninit = xhci_ep_uninit, 4139 .xfer_setup = xhci_xfer_setup, 4140 .xfer_unsetup = xhci_xfer_unsetup, 4141 .get_dma_delay = xhci_get_dma_delay, 4142 .device_init = xhci_device_init, 4143 .device_uninit = xhci_device_uninit, 4144 .device_resume = xhci_device_resume, 4145 .device_suspend = xhci_device_suspend, 4146 .set_hw_power = xhci_set_hw_power, 4147 .roothub_exec = xhci_roothub_exec, 4148 .xfer_poll = xhci_do_poll, 4149 .start_dma_delay = xhci_start_dma_delay, 4150 .set_address = xhci_set_address, 4151 .clear_stall = xhci_ep_clear_stall, 4152 .device_state_change = xhci_device_state_change, 4153 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4154 .set_endpoint_mode = xhci_set_endpoint_mode, 4155 }; 4156