1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 31 * 32 * The XHCI 1.0 spec can be found at 33 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 34 * and the USB 3.0 spec at 35 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 36 */ 37 38 /* 39 * A few words about the design implementation: This driver emulates 40 * the concept about TDs which is found in EHCI specification. This 41 * way we achieve that the USB controller drivers look similar to 42 * eachother which makes it easier to understand the code. 43 */ 44 45 #ifdef USB_GLOBAL_INCLUDE_FILE 46 #include USB_GLOBAL_INCLUDE_FILE 47 #else 48 #include <sys/stdint.h> 49 #include <sys/stddef.h> 50 #include <sys/param.h> 51 #include <sys/queue.h> 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/bus.h> 56 #include <sys/module.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/condvar.h> 60 #include <sys/sysctl.h> 61 #include <sys/sx.h> 62 #include <sys/unistd.h> 63 #include <sys/callout.h> 64 #include <sys/malloc.h> 65 #include <sys/priv.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 70 #define USB_DEBUG_VAR xhcidebug 71 72 #include <dev/usb/usb_core.h> 73 #include <dev/usb/usb_debug.h> 74 #include <dev/usb/usb_busdma.h> 75 #include <dev/usb/usb_process.h> 76 #include <dev/usb/usb_transfer.h> 77 #include <dev/usb/usb_device.h> 78 #include <dev/usb/usb_hub.h> 79 #include <dev/usb/usb_util.h> 80 81 #include <dev/usb/usb_controller.h> 82 #include <dev/usb/usb_bus.h> 83 #endif /* USB_GLOBAL_INCLUDE_FILE */ 84 85 #include <dev/usb/controller/xhci.h> 86 #include <dev/usb/controller/xhcireg.h> 87 88 #define XHCI_BUS2SC(bus) \ 89 __containerof(bus, struct xhci_softc, sc_bus) 90 91 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 92 "USB XHCI"); 93 94 static int xhcistreams; 95 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN, 96 &xhcistreams, 0, "Set to enable streams mode support"); 97 98 static int xhcictlquirk = 1; 99 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlquirk, CTLFLAG_RWTUN, 100 &xhcictlquirk, 0, "Set to enable control endpoint quirk"); 101 102 #ifdef USB_DEBUG 103 static int xhcidebug; 104 static int xhciroute; 105 static int xhcipolling; 106 static int xhcidma32; 107 static int xhcictlstep; 108 109 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN, 110 &xhcidebug, 0, "Debug level"); 111 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN, 112 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller"); 113 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN, 114 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller"); 115 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN, 116 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller"); 117 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN, 118 &xhcictlstep, 0, "Set to enable control endpoint status stage stepping"); 119 #else 120 #define xhciroute 0 121 #define xhcidma32 0 122 #define xhcictlstep 0 123 #endif 124 125 #define XHCI_INTR_ENDPT 1 126 127 struct xhci_std_temp { 128 struct xhci_softc *sc; 129 struct usb_page_cache *pc; 130 struct xhci_td *td; 131 struct xhci_td *td_next; 132 uint32_t len; 133 uint32_t offset; 134 uint32_t max_packet_size; 135 uint32_t average; 136 uint16_t isoc_delta; 137 uint16_t isoc_frame; 138 uint8_t shortpkt; 139 uint8_t multishort; 140 uint8_t last_frame; 141 uint8_t trb_type; 142 uint8_t direction; 143 uint8_t tbc; 144 uint8_t tlbpc; 145 uint8_t step_td; 146 uint8_t do_isoc_sync; 147 }; 148 149 static void xhci_do_poll(struct usb_bus *); 150 static void xhci_device_done(struct usb_xfer *, usb_error_t); 151 static void xhci_root_intr(struct xhci_softc *); 152 static void xhci_free_device_ext(struct usb_device *); 153 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 154 struct usb_endpoint_descriptor *); 155 static usb_proc_callback_t xhci_configure_msg; 156 static usb_error_t xhci_configure_device(struct usb_device *); 157 static usb_error_t xhci_configure_endpoint(struct usb_device *, 158 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 159 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 160 uint8_t); 161 static usb_error_t xhci_configure_mask(struct usb_device *, 162 uint32_t, uint8_t); 163 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 164 uint64_t, uint8_t); 165 static void xhci_endpoint_doorbell(struct usb_xfer *); 166 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 167 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 168 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 169 #ifdef USB_DEBUG 170 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 171 #endif 172 173 static const struct usb_bus_methods xhci_bus_methods; 174 175 #ifdef USB_DEBUG 176 static void 177 xhci_dump_trb(struct xhci_trb *trb) 178 { 179 DPRINTFN(5, "trb = %p\n", trb); 180 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 181 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 182 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 183 } 184 185 static void 186 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 187 { 188 DPRINTFN(5, "pep = %p\n", pep); 189 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 190 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 191 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 192 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 193 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 194 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 195 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 196 } 197 198 static void 199 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 200 { 201 DPRINTFN(5, "psl = %p\n", psl); 202 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 203 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 204 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 205 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 206 } 207 #endif 208 209 uint8_t 210 xhci_use_polling(void) 211 { 212 #ifdef USB_DEBUG 213 return (xhcipolling != 0); 214 #else 215 return (0); 216 #endif 217 } 218 219 static void 220 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 221 { 222 struct xhci_softc *sc = XHCI_BUS2SC(bus); 223 uint16_t i; 224 225 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 226 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 227 228 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 229 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 230 231 for (i = 0; i != sc->sc_noscratch; i++) { 232 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 233 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 234 } 235 } 236 237 static void 238 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 239 { 240 if (sc->sc_ctx_is_64_byte) { 241 uint32_t offset; 242 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 243 /* all contexts are initially 32-bytes */ 244 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 245 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 246 } 247 *ptr = htole32(val); 248 } 249 250 static uint32_t 251 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 252 { 253 if (sc->sc_ctx_is_64_byte) { 254 uint32_t offset; 255 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 256 /* all contexts are initially 32-bytes */ 257 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 258 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 259 } 260 return (le32toh(*ptr)); 261 } 262 263 static void 264 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 265 { 266 if (sc->sc_ctx_is_64_byte) { 267 uint32_t offset; 268 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 269 /* all contexts are initially 32-bytes */ 270 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 271 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 272 } 273 *ptr = htole64(val); 274 } 275 276 #ifdef USB_DEBUG 277 static uint64_t 278 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 279 { 280 if (sc->sc_ctx_is_64_byte) { 281 uint32_t offset; 282 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 283 /* all contexts are initially 32-bytes */ 284 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 285 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 286 } 287 return (le64toh(*ptr)); 288 } 289 #endif 290 291 static int 292 xhci_reset_command_queue_locked(struct xhci_softc *sc) 293 { 294 struct usb_page_search buf_res; 295 struct xhci_hw_root *phwr; 296 uint64_t addr; 297 uint32_t temp; 298 299 DPRINTF("\n"); 300 301 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 302 if (temp & XHCI_CRCR_LO_CRR) { 303 DPRINTF("Command ring running\n"); 304 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 305 306 /* 307 * Try to abort the last command as per section 308 * 4.6.1.2 "Aborting a Command" of the XHCI 309 * specification: 310 */ 311 312 /* stop and cancel */ 313 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 314 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 315 316 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 317 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 318 319 /* wait 250ms */ 320 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 321 322 /* check if command ring is still running */ 323 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 324 if (temp & XHCI_CRCR_LO_CRR) { 325 DPRINTF("Comand ring still running\n"); 326 return (USB_ERR_IOERROR); 327 } 328 } 329 330 /* reset command ring */ 331 sc->sc_command_ccs = 1; 332 sc->sc_command_idx = 0; 333 334 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 335 336 /* set up command ring control base address */ 337 addr = buf_res.physaddr; 338 phwr = buf_res.buffer; 339 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 340 341 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 342 343 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 344 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 345 346 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 347 348 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 349 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 350 351 return (0); 352 } 353 354 usb_error_t 355 xhci_start_controller(struct xhci_softc *sc) 356 { 357 struct usb_page_search buf_res; 358 struct xhci_hw_root *phwr; 359 struct xhci_dev_ctx_addr *pdctxa; 360 usb_error_t err; 361 uint64_t addr; 362 uint32_t temp; 363 uint16_t i; 364 365 DPRINTF("\n"); 366 367 sc->sc_event_ccs = 1; 368 sc->sc_event_idx = 0; 369 sc->sc_command_ccs = 1; 370 sc->sc_command_idx = 0; 371 372 err = xhci_reset_controller(sc); 373 if (err) 374 return (err); 375 376 /* set up number of device slots */ 377 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 378 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 379 380 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 381 382 temp = XREAD4(sc, oper, XHCI_USBSTS); 383 384 /* clear interrupts */ 385 XWRITE4(sc, oper, XHCI_USBSTS, temp); 386 /* disable all device notifications */ 387 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 388 389 /* set up device context base address */ 390 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 391 pdctxa = buf_res.buffer; 392 memset(pdctxa, 0, sizeof(*pdctxa)); 393 394 addr = buf_res.physaddr; 395 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 396 397 /* slot 0 points to the table of scratchpad pointers */ 398 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 399 400 for (i = 0; i != sc->sc_noscratch; i++) { 401 struct usb_page_search buf_scp; 402 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 403 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 404 } 405 406 addr = buf_res.physaddr; 407 408 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 409 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 410 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 411 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 412 413 /* set up event table size */ 414 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 415 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max); 416 417 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max)); 418 419 /* set up interrupt rate */ 420 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 421 422 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 423 424 phwr = buf_res.buffer; 425 addr = buf_res.physaddr; 426 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 427 428 /* reset hardware root structure */ 429 memset(phwr, 0, sizeof(*phwr)); 430 431 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 432 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 433 434 /* 435 * PR 237666: 436 * 437 * According to the XHCI specification, the XWRITE4's to 438 * XHCI_ERSTBA_LO and _HI lead to the XHCI to copy the 439 * qwEvrsTablePtr and dwEvrsTableSize values above at that 440 * time, as the XHCI initializes its event ring support. This 441 * is before the event ring starts to pay attention to the 442 * RUN/STOP bit. Thus, make sure the values are observable to 443 * the XHCI before that point. 444 */ 445 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 446 447 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 448 449 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 450 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 451 452 addr = buf_res.physaddr; 453 454 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 455 456 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 457 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 458 459 /* set up interrupter registers */ 460 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 461 temp |= XHCI_IMAN_INTR_ENA; 462 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 463 464 /* set up command ring control base address */ 465 addr = buf_res.physaddr; 466 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 467 468 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 469 470 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 471 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 472 473 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 474 475 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 476 477 /* Go! */ 478 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 479 XHCI_CMD_INTE | XHCI_CMD_HSEE); 480 481 for (i = 0; i != 100; i++) { 482 usb_pause_mtx(NULL, hz / 100); 483 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 484 if (!temp) 485 break; 486 } 487 if (temp) { 488 XWRITE4(sc, oper, XHCI_USBCMD, 0); 489 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 490 return (USB_ERR_IOERROR); 491 } 492 493 /* catch any lost interrupts */ 494 xhci_do_poll(&sc->sc_bus); 495 496 if (sc->sc_port_route != NULL) { 497 /* Route all ports to the XHCI by default */ 498 sc->sc_port_route(sc->sc_bus.parent, 499 ~xhciroute, xhciroute); 500 } 501 return (0); 502 } 503 504 usb_error_t 505 xhci_halt_controller(struct xhci_softc *sc) 506 { 507 uint32_t temp; 508 uint16_t i; 509 510 DPRINTF("\n"); 511 512 sc->sc_capa_off = 0; 513 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 514 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 515 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 516 517 /* Halt controller */ 518 XWRITE4(sc, oper, XHCI_USBCMD, 0); 519 520 for (i = 0; i != 100; i++) { 521 usb_pause_mtx(NULL, hz / 100); 522 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 523 if (temp) 524 break; 525 } 526 527 if (!temp) { 528 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 529 return (USB_ERR_IOERROR); 530 } 531 return (0); 532 } 533 534 usb_error_t 535 xhci_reset_controller(struct xhci_softc *sc) 536 { 537 uint32_t temp = 0; 538 uint16_t i; 539 540 DPRINTF("\n"); 541 542 /* Reset controller */ 543 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 544 545 for (i = 0; i != 100; i++) { 546 usb_pause_mtx(NULL, hz / 100); 547 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 548 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 549 if (!temp) 550 break; 551 } 552 553 if (temp) { 554 device_printf(sc->sc_bus.parent, "Controller " 555 "reset timeout.\n"); 556 return (USB_ERR_IOERROR); 557 } 558 return (0); 559 } 560 561 usb_error_t 562 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32) 563 { 564 uint32_t temp; 565 566 DPRINTF("\n"); 567 568 /* initialize some bus fields */ 569 sc->sc_bus.parent = self; 570 571 /* set the bus revision */ 572 sc->sc_bus.usbrev = USB_REV_3_0; 573 574 /* set up the bus struct */ 575 sc->sc_bus.methods = &xhci_bus_methods; 576 577 /* set up devices array */ 578 sc->sc_bus.devices = sc->sc_devices; 579 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 580 581 /* set default cycle state in case of early interrupts */ 582 sc->sc_event_ccs = 1; 583 sc->sc_command_ccs = 1; 584 585 /* set up bus space offsets */ 586 sc->sc_capa_off = 0; 587 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 588 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 589 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 590 591 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 592 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 593 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 594 595 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 596 597 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 598 device_printf(sc->sc_bus.parent, "Controller does " 599 "not support 4K page size.\n"); 600 return (ENXIO); 601 } 602 603 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 604 605 DPRINTF("HCS0 = 0x%08x\n", temp); 606 607 /* set up context size */ 608 if (XHCI_HCS0_CSZ(temp)) { 609 sc->sc_ctx_is_64_byte = 1; 610 } else { 611 sc->sc_ctx_is_64_byte = 0; 612 } 613 614 /* get DMA bits */ 615 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && 616 xhcidma32 == 0 && dma32 == 0) ? 64 : 32; 617 618 device_printf(self, "%d bytes context size, %d-bit DMA\n", 619 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); 620 621 /* enable 64Kbyte control endpoint quirk */ 622 sc->sc_bus.control_ep_quirk = (xhcictlquirk ? 1 : 0); 623 624 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 625 626 /* get number of device slots */ 627 sc->sc_noport = XHCI_HCS1_N_PORTS(temp); 628 629 if (sc->sc_noport == 0) { 630 device_printf(sc->sc_bus.parent, "Invalid number " 631 "of ports: %u\n", sc->sc_noport); 632 return (ENXIO); 633 } 634 635 sc->sc_noport = sc->sc_noport; 636 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 637 638 DPRINTF("Max slots: %u\n", sc->sc_noslot); 639 640 if (sc->sc_noslot > XHCI_MAX_DEVICES) 641 sc->sc_noslot = XHCI_MAX_DEVICES; 642 643 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 644 645 DPRINTF("HCS2=0x%08x\n", temp); 646 647 /* get number of scratchpads */ 648 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 649 650 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 651 device_printf(sc->sc_bus.parent, "XHCI request " 652 "too many scratchpads\n"); 653 return (ENOMEM); 654 } 655 656 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 657 658 /* get event table size */ 659 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); 660 if (sc->sc_erst_max > XHCI_MAX_RSEG) 661 sc->sc_erst_max = XHCI_MAX_RSEG; 662 663 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 664 665 /* get maximum exit latency */ 666 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 667 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 668 669 /* Check if we should use the default IMOD value. */ 670 if (sc->sc_imod_default == 0) 671 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 672 673 /* get all DMA memory */ 674 if (usb_bus_mem_alloc_all(&sc->sc_bus, 675 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 676 return (ENOMEM); 677 } 678 679 /* set up command queue mutex and condition varible */ 680 cv_init(&sc->sc_cmd_cv, "CMDQ"); 681 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 682 683 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 684 sc->sc_config_msg[0].bus = &sc->sc_bus; 685 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 686 sc->sc_config_msg[1].bus = &sc->sc_bus; 687 688 return (0); 689 } 690 691 void 692 xhci_uninit(struct xhci_softc *sc) 693 { 694 /* 695 * NOTE: At this point the control transfer process is gone 696 * and "xhci_configure_msg" is no longer called. Consequently 697 * waiting for the configuration messages to complete is not 698 * needed. 699 */ 700 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 701 702 cv_destroy(&sc->sc_cmd_cv); 703 sx_destroy(&sc->sc_cmd_sx); 704 } 705 706 static void 707 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 708 { 709 struct xhci_softc *sc = XHCI_BUS2SC(bus); 710 711 switch (state) { 712 case USB_HW_POWER_SUSPEND: 713 DPRINTF("Stopping the XHCI\n"); 714 xhci_halt_controller(sc); 715 xhci_reset_controller(sc); 716 break; 717 case USB_HW_POWER_SHUTDOWN: 718 DPRINTF("Stopping the XHCI\n"); 719 xhci_halt_controller(sc); 720 xhci_reset_controller(sc); 721 break; 722 case USB_HW_POWER_RESUME: 723 DPRINTF("Starting the XHCI\n"); 724 xhci_start_controller(sc); 725 break; 726 default: 727 break; 728 } 729 } 730 731 static usb_error_t 732 xhci_generic_done_sub(struct usb_xfer *xfer) 733 { 734 struct xhci_td *td; 735 struct xhci_td *td_alt_next; 736 uint32_t len; 737 uint8_t status; 738 739 td = xfer->td_transfer_cache; 740 td_alt_next = td->alt_next; 741 742 if (xfer->aframes != xfer->nframes) 743 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 744 745 while (1) { 746 usb_pc_cpu_invalidate(td->page_cache); 747 748 status = td->status; 749 len = td->remainder; 750 751 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 752 xfer, (unsigned int)xfer->aframes, 753 (unsigned int)xfer->nframes, 754 (unsigned int)len, (unsigned int)td->len, 755 (unsigned int)status); 756 757 /* 758 * Verify the status length and 759 * add the length to "frlengths[]": 760 */ 761 if (len > td->len) { 762 /* should not happen */ 763 DPRINTF("Invalid status length, " 764 "0x%04x/0x%04x bytes\n", len, td->len); 765 status = XHCI_TRB_ERROR_LENGTH; 766 } else if (xfer->aframes != xfer->nframes) { 767 xfer->frlengths[xfer->aframes] += td->len - len; 768 } 769 /* Check for last transfer */ 770 if (((void *)td) == xfer->td_transfer_last) { 771 td = NULL; 772 break; 773 } 774 /* Check for transfer error */ 775 if (status != XHCI_TRB_ERROR_SHORT_PKT && 776 status != XHCI_TRB_ERROR_SUCCESS) { 777 /* the transfer is finished */ 778 td = NULL; 779 break; 780 } 781 /* Check for short transfer */ 782 if (len > 0) { 783 if (xfer->flags_int.short_frames_ok || 784 xfer->flags_int.isochronous_xfr || 785 xfer->flags_int.control_xfr) { 786 /* follow alt next */ 787 td = td->alt_next; 788 } else { 789 /* the transfer is finished */ 790 td = NULL; 791 } 792 break; 793 } 794 td = td->obj_next; 795 796 if (td->alt_next != td_alt_next) { 797 /* this USB frame is complete */ 798 break; 799 } 800 } 801 802 /* update transfer cache */ 803 804 xfer->td_transfer_cache = td; 805 806 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 807 (status != XHCI_TRB_ERROR_SHORT_PKT && 808 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 809 USB_ERR_NORMAL_COMPLETION); 810 } 811 812 static void 813 xhci_generic_done(struct usb_xfer *xfer) 814 { 815 usb_error_t err = 0; 816 817 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 818 xfer, xfer->endpoint); 819 820 /* reset scanner */ 821 822 xfer->td_transfer_cache = xfer->td_transfer_first; 823 824 if (xfer->flags_int.control_xfr) { 825 if (xfer->flags_int.control_hdr) 826 err = xhci_generic_done_sub(xfer); 827 828 xfer->aframes = 1; 829 830 if (xfer->td_transfer_cache == NULL) 831 goto done; 832 } 833 834 while (xfer->aframes != xfer->nframes) { 835 err = xhci_generic_done_sub(xfer); 836 xfer->aframes++; 837 838 if (xfer->td_transfer_cache == NULL) 839 goto done; 840 } 841 842 if (xfer->flags_int.control_xfr && 843 !xfer->flags_int.control_act) 844 err = xhci_generic_done_sub(xfer); 845 done: 846 /* transfer is complete */ 847 xhci_device_done(xfer, err); 848 } 849 850 static void 851 xhci_activate_transfer(struct usb_xfer *xfer) 852 { 853 struct xhci_td *td; 854 855 td = xfer->td_transfer_cache; 856 857 usb_pc_cpu_invalidate(td->page_cache); 858 859 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 860 /* activate the transfer */ 861 862 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 863 usb_pc_cpu_flush(td->page_cache); 864 865 xhci_endpoint_doorbell(xfer); 866 } 867 } 868 869 static void 870 xhci_skip_transfer(struct usb_xfer *xfer) 871 { 872 struct xhci_td *td; 873 struct xhci_td *td_last; 874 875 td = xfer->td_transfer_cache; 876 td_last = xfer->td_transfer_last; 877 878 td = td->alt_next; 879 880 usb_pc_cpu_invalidate(td->page_cache); 881 882 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 883 usb_pc_cpu_invalidate(td_last->page_cache); 884 885 /* copy LINK TRB to current waiting location */ 886 887 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 888 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 889 usb_pc_cpu_flush(td->page_cache); 890 891 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 892 usb_pc_cpu_flush(td->page_cache); 893 894 xhci_endpoint_doorbell(xfer); 895 } 896 } 897 898 /*------------------------------------------------------------------------* 899 * xhci_check_transfer 900 *------------------------------------------------------------------------*/ 901 static void 902 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 903 { 904 struct xhci_endpoint_ext *pepext; 905 int64_t offset; 906 uint64_t td_event; 907 uint32_t temp; 908 uint32_t remainder; 909 uint16_t stream_id = 0; 910 uint16_t i; 911 uint8_t status; 912 uint8_t halted; 913 uint8_t epno; 914 uint8_t index; 915 916 /* decode TRB */ 917 td_event = le64toh(trb->qwTrb0); 918 temp = le32toh(trb->dwTrb2); 919 920 remainder = XHCI_TRB_2_REM_GET(temp); 921 status = XHCI_TRB_2_ERROR_GET(temp); 922 923 temp = le32toh(trb->dwTrb3); 924 epno = XHCI_TRB_3_EP_GET(temp); 925 index = XHCI_TRB_3_SLOT_GET(temp); 926 927 /* check if error means halted */ 928 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 929 status != XHCI_TRB_ERROR_SUCCESS); 930 931 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 932 index, epno, remainder, status); 933 934 if (index > sc->sc_noslot) { 935 DPRINTF("Invalid slot.\n"); 936 return; 937 } 938 939 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 940 DPRINTF("Invalid endpoint.\n"); 941 return; 942 } 943 944 pepext = &sc->sc_hw.devs[index].endp[epno]; 945 946 /* try to find the USB transfer that generated the event */ 947 for (i = 0;; i++) { 948 struct usb_xfer *xfer; 949 struct xhci_td *td; 950 951 if (i == (XHCI_MAX_TRANSFERS - 1)) { 952 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS || 953 stream_id == (XHCI_MAX_STREAMS - 1)) 954 break; 955 stream_id++; 956 i = 0; 957 DPRINTFN(5, "stream_id=%u\n", stream_id); 958 } 959 960 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 961 if (xfer == NULL) 962 continue; 963 964 td = xfer->td_transfer_cache; 965 966 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 967 (long long)td_event, 968 (long long)td->td_self, 969 (long long)td->td_self + sizeof(td->td_trb)); 970 971 /* 972 * NOTE: Some XHCI implementations might not trigger 973 * an event on the last LINK TRB so we need to 974 * consider both the last and second last event 975 * address as conditions for a successful transfer. 976 * 977 * NOTE: We assume that the XHCI will only trigger one 978 * event per chain of TRBs. 979 */ 980 981 offset = td_event - td->td_self; 982 983 if (offset >= 0 && 984 offset < (int64_t)sizeof(td->td_trb)) { 985 usb_pc_cpu_invalidate(td->page_cache); 986 987 /* compute rest of remainder, if any */ 988 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 989 temp = le32toh(td->td_trb[i].dwTrb2); 990 remainder += XHCI_TRB_2_BYTES_GET(temp); 991 } 992 993 DPRINTFN(5, "New remainder: %u\n", remainder); 994 995 /* clear isochronous transfer errors */ 996 if (xfer->flags_int.isochronous_xfr) { 997 if (halted) { 998 halted = 0; 999 status = XHCI_TRB_ERROR_SUCCESS; 1000 remainder = td->len; 1001 } 1002 } 1003 1004 /* "td->remainder" is verified later */ 1005 td->remainder = remainder; 1006 td->status = status; 1007 1008 usb_pc_cpu_flush(td->page_cache); 1009 1010 /* 1011 * 1) Last transfer descriptor makes the 1012 * transfer done 1013 */ 1014 if (((void *)td) == xfer->td_transfer_last) { 1015 DPRINTF("TD is last\n"); 1016 xhci_generic_done(xfer); 1017 break; 1018 } 1019 1020 /* 1021 * 2) Any kind of error makes the transfer 1022 * done 1023 */ 1024 if (halted) { 1025 DPRINTF("TD has I/O error\n"); 1026 xhci_generic_done(xfer); 1027 break; 1028 } 1029 1030 /* 1031 * 3) If there is no alternate next transfer, 1032 * a short packet also makes the transfer done 1033 */ 1034 if (td->remainder > 0) { 1035 if (td->alt_next == NULL) { 1036 DPRINTF( 1037 "short TD has no alternate next\n"); 1038 xhci_generic_done(xfer); 1039 break; 1040 } 1041 DPRINTF("TD has short pkt\n"); 1042 if (xfer->flags_int.short_frames_ok || 1043 xfer->flags_int.isochronous_xfr || 1044 xfer->flags_int.control_xfr) { 1045 /* follow the alt next */ 1046 xfer->td_transfer_cache = td->alt_next; 1047 xhci_activate_transfer(xfer); 1048 break; 1049 } 1050 xhci_skip_transfer(xfer); 1051 xhci_generic_done(xfer); 1052 break; 1053 } 1054 1055 /* 1056 * 4) Transfer complete - go to next TD 1057 */ 1058 DPRINTF("Following next TD\n"); 1059 xfer->td_transfer_cache = td->obj_next; 1060 xhci_activate_transfer(xfer); 1061 break; /* there should only be one match */ 1062 } 1063 } 1064 } 1065 1066 static int 1067 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1068 { 1069 if (sc->sc_cmd_addr == trb->qwTrb0) { 1070 DPRINTF("Received command event\n"); 1071 sc->sc_cmd_result[0] = trb->dwTrb2; 1072 sc->sc_cmd_result[1] = trb->dwTrb3; 1073 cv_signal(&sc->sc_cmd_cv); 1074 return (1); /* command match */ 1075 } 1076 return (0); 1077 } 1078 1079 static int 1080 xhci_interrupt_poll(struct xhci_softc *sc) 1081 { 1082 struct usb_page_search buf_res; 1083 struct xhci_hw_root *phwr; 1084 uint64_t addr; 1085 uint32_t temp; 1086 int retval = 0; 1087 uint16_t i; 1088 uint8_t event; 1089 uint8_t j; 1090 uint8_t k; 1091 uint8_t t; 1092 1093 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1094 1095 phwr = buf_res.buffer; 1096 1097 /* Receive any events */ 1098 1099 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1100 1101 i = sc->sc_event_idx; 1102 j = sc->sc_event_ccs; 1103 t = 2; 1104 1105 while (1) { 1106 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1107 1108 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1109 1110 if (j != k) 1111 break; 1112 1113 event = XHCI_TRB_3_TYPE_GET(temp); 1114 1115 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1116 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1117 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1118 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1119 1120 switch (event) { 1121 case XHCI_TRB_EVENT_TRANSFER: 1122 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1123 break; 1124 case XHCI_TRB_EVENT_CMD_COMPLETE: 1125 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1126 break; 1127 default: 1128 DPRINTF("Unhandled event = %u\n", event); 1129 break; 1130 } 1131 1132 i++; 1133 1134 if (i == XHCI_MAX_EVENTS) { 1135 i = 0; 1136 j ^= 1; 1137 1138 /* check for timeout */ 1139 if (!--t) 1140 break; 1141 } 1142 } 1143 1144 sc->sc_event_idx = i; 1145 sc->sc_event_ccs = j; 1146 1147 /* 1148 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1149 * latched. That means to activate the register we need to 1150 * write both the low and high double word of the 64-bit 1151 * register. 1152 */ 1153 1154 addr = buf_res.physaddr; 1155 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1156 1157 /* try to clear busy bit */ 1158 addr |= XHCI_ERDP_LO_BUSY; 1159 1160 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1161 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1162 1163 return (retval); 1164 } 1165 1166 static usb_error_t 1167 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1168 uint16_t timeout_ms) 1169 { 1170 struct usb_page_search buf_res; 1171 struct xhci_hw_root *phwr; 1172 uint64_t addr; 1173 uint32_t temp; 1174 uint8_t i; 1175 uint8_t j; 1176 uint8_t timeout = 0; 1177 int err; 1178 1179 XHCI_CMD_ASSERT_LOCKED(sc); 1180 1181 /* get hardware root structure */ 1182 1183 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1184 1185 phwr = buf_res.buffer; 1186 1187 /* Queue command */ 1188 1189 USB_BUS_LOCK(&sc->sc_bus); 1190 retry: 1191 i = sc->sc_command_idx; 1192 j = sc->sc_command_ccs; 1193 1194 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1195 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1196 (long long)le64toh(trb->qwTrb0), 1197 (long)le32toh(trb->dwTrb2), 1198 (long)le32toh(trb->dwTrb3)); 1199 1200 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1201 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1202 1203 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1204 1205 temp = trb->dwTrb3; 1206 1207 if (j) 1208 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1209 else 1210 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1211 1212 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1213 1214 phwr->hwr_commands[i].dwTrb3 = temp; 1215 1216 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1217 1218 addr = buf_res.physaddr; 1219 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1220 1221 sc->sc_cmd_addr = htole64(addr); 1222 1223 i++; 1224 1225 if (i == (XHCI_MAX_COMMANDS - 1)) { 1226 if (j) { 1227 temp = htole32(XHCI_TRB_3_TC_BIT | 1228 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1229 XHCI_TRB_3_CYCLE_BIT); 1230 } else { 1231 temp = htole32(XHCI_TRB_3_TC_BIT | 1232 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1233 } 1234 1235 phwr->hwr_commands[i].dwTrb3 = temp; 1236 1237 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1238 1239 i = 0; 1240 j ^= 1; 1241 } 1242 1243 sc->sc_command_idx = i; 1244 sc->sc_command_ccs = j; 1245 1246 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1247 1248 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1249 USB_MS_TO_TICKS(timeout_ms)); 1250 1251 /* 1252 * In some error cases event interrupts are not generated. 1253 * Poll one time to see if the command has completed. 1254 */ 1255 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1256 DPRINTF("Command was completed when polling\n"); 1257 err = 0; 1258 } 1259 if (err != 0) { 1260 DPRINTF("Command timeout!\n"); 1261 /* 1262 * After some weeks of continuous operation, it has 1263 * been observed that the ASMedia Technology, ASM1042 1264 * SuperSpeed USB Host Controller can suddenly stop 1265 * accepting commands via the command queue. Try to 1266 * first reset the command queue. If that fails do a 1267 * host controller reset. 1268 */ 1269 if (timeout == 0 && 1270 xhci_reset_command_queue_locked(sc) == 0) { 1271 temp = le32toh(trb->dwTrb3); 1272 1273 /* 1274 * Avoid infinite XHCI reset loops if the set 1275 * address command fails to respond due to a 1276 * non-enumerating device: 1277 */ 1278 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1279 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1280 DPRINTF("Set address timeout\n"); 1281 } else { 1282 timeout = 1; 1283 goto retry; 1284 } 1285 } else { 1286 DPRINTF("Controller reset!\n"); 1287 usb_bus_reset_async_locked(&sc->sc_bus); 1288 } 1289 err = USB_ERR_TIMEOUT; 1290 trb->dwTrb2 = 0; 1291 trb->dwTrb3 = 0; 1292 } else { 1293 temp = le32toh(sc->sc_cmd_result[0]); 1294 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1295 err = USB_ERR_IOERROR; 1296 1297 trb->dwTrb2 = sc->sc_cmd_result[0]; 1298 trb->dwTrb3 = sc->sc_cmd_result[1]; 1299 } 1300 1301 USB_BUS_UNLOCK(&sc->sc_bus); 1302 1303 return (err); 1304 } 1305 1306 #if 0 1307 static usb_error_t 1308 xhci_cmd_nop(struct xhci_softc *sc) 1309 { 1310 struct xhci_trb trb; 1311 uint32_t temp; 1312 1313 DPRINTF("\n"); 1314 1315 trb.qwTrb0 = 0; 1316 trb.dwTrb2 = 0; 1317 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1318 1319 trb.dwTrb3 = htole32(temp); 1320 1321 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1322 } 1323 #endif 1324 1325 static usb_error_t 1326 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1327 { 1328 struct xhci_trb trb; 1329 uint32_t temp; 1330 usb_error_t err; 1331 1332 DPRINTF("\n"); 1333 1334 trb.qwTrb0 = 0; 1335 trb.dwTrb2 = 0; 1336 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1337 1338 err = xhci_do_command(sc, &trb, 100 /* ms */); 1339 if (err) 1340 goto done; 1341 1342 temp = le32toh(trb.dwTrb3); 1343 1344 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1345 1346 done: 1347 return (err); 1348 } 1349 1350 static usb_error_t 1351 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1352 { 1353 struct xhci_trb trb; 1354 uint32_t temp; 1355 1356 DPRINTF("\n"); 1357 1358 trb.qwTrb0 = 0; 1359 trb.dwTrb2 = 0; 1360 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1361 XHCI_TRB_3_SLOT_SET(slot_id); 1362 1363 trb.dwTrb3 = htole32(temp); 1364 1365 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1366 } 1367 1368 static usb_error_t 1369 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1370 uint8_t bsr, uint8_t slot_id) 1371 { 1372 struct xhci_trb trb; 1373 uint32_t temp; 1374 1375 DPRINTF("\n"); 1376 1377 trb.qwTrb0 = htole64(input_ctx); 1378 trb.dwTrb2 = 0; 1379 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1380 XHCI_TRB_3_SLOT_SET(slot_id); 1381 1382 if (bsr) 1383 temp |= XHCI_TRB_3_BSR_BIT; 1384 1385 trb.dwTrb3 = htole32(temp); 1386 1387 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1388 } 1389 1390 static usb_error_t 1391 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1392 { 1393 struct usb_page_search buf_inp; 1394 struct usb_page_search buf_dev; 1395 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1396 struct xhci_hw_dev *hdev; 1397 struct xhci_dev_ctx *pdev; 1398 struct xhci_endpoint_ext *pepext; 1399 uint32_t temp; 1400 uint16_t mps; 1401 usb_error_t err; 1402 uint8_t index; 1403 1404 /* the root HUB case is not handled here */ 1405 if (udev->parent_hub == NULL) 1406 return (USB_ERR_INVAL); 1407 1408 index = udev->controller_slot_id; 1409 1410 hdev = &sc->sc_hw.devs[index]; 1411 1412 if (mtx != NULL) 1413 mtx_unlock(mtx); 1414 1415 XHCI_CMD_LOCK(sc); 1416 1417 switch (hdev->state) { 1418 case XHCI_ST_DEFAULT: 1419 case XHCI_ST_ENABLED: 1420 1421 hdev->state = XHCI_ST_ENABLED; 1422 1423 /* set configure mask to slot and EP0 */ 1424 xhci_configure_mask(udev, 3, 0); 1425 1426 /* configure input slot context structure */ 1427 err = xhci_configure_device(udev); 1428 1429 if (err != 0) { 1430 DPRINTF("Could not configure device\n"); 1431 break; 1432 } 1433 1434 /* configure input endpoint context structure */ 1435 switch (udev->speed) { 1436 case USB_SPEED_LOW: 1437 case USB_SPEED_FULL: 1438 mps = 8; 1439 break; 1440 case USB_SPEED_HIGH: 1441 mps = 64; 1442 break; 1443 default: 1444 mps = 512; 1445 break; 1446 } 1447 1448 pepext = xhci_get_endpoint_ext(udev, 1449 &udev->ctrl_ep_desc); 1450 1451 /* ensure the control endpoint is setup again */ 1452 USB_BUS_LOCK(udev->bus); 1453 pepext->trb_halted = 1; 1454 pepext->trb_running = 0; 1455 USB_BUS_UNLOCK(udev->bus); 1456 1457 err = xhci_configure_endpoint(udev, 1458 &udev->ctrl_ep_desc, pepext, 1459 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1460 1461 if (err != 0) { 1462 DPRINTF("Could not configure default endpoint\n"); 1463 break; 1464 } 1465 1466 /* execute set address command */ 1467 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1468 1469 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1470 (address == 0), index); 1471 1472 if (err != 0) { 1473 temp = le32toh(sc->sc_cmd_result[0]); 1474 if (address == 0 && sc->sc_port_route != NULL && 1475 XHCI_TRB_2_ERROR_GET(temp) == 1476 XHCI_TRB_ERROR_PARAMETER) { 1477 /* LynxPoint XHCI - ports are not switchable */ 1478 /* Un-route all ports from the XHCI */ 1479 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1480 } 1481 DPRINTF("Could not set address " 1482 "for slot %u.\n", index); 1483 if (address != 0) 1484 break; 1485 } 1486 1487 /* update device address to new value */ 1488 1489 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1490 pdev = buf_dev.buffer; 1491 usb_pc_cpu_invalidate(&hdev->device_pc); 1492 1493 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1494 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1495 1496 /* update device state to new value */ 1497 1498 if (address != 0) 1499 hdev->state = XHCI_ST_ADDRESSED; 1500 else 1501 hdev->state = XHCI_ST_DEFAULT; 1502 break; 1503 1504 default: 1505 DPRINTF("Wrong state for set address.\n"); 1506 err = USB_ERR_IOERROR; 1507 break; 1508 } 1509 XHCI_CMD_UNLOCK(sc); 1510 1511 if (mtx != NULL) 1512 mtx_lock(mtx); 1513 1514 return (err); 1515 } 1516 1517 static usb_error_t 1518 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1519 uint8_t deconfigure, uint8_t slot_id) 1520 { 1521 struct xhci_trb trb; 1522 uint32_t temp; 1523 1524 DPRINTF("\n"); 1525 1526 trb.qwTrb0 = htole64(input_ctx); 1527 trb.dwTrb2 = 0; 1528 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1529 XHCI_TRB_3_SLOT_SET(slot_id); 1530 1531 if (deconfigure) 1532 temp |= XHCI_TRB_3_DCEP_BIT; 1533 1534 trb.dwTrb3 = htole32(temp); 1535 1536 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1537 } 1538 1539 static usb_error_t 1540 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1541 uint8_t slot_id) 1542 { 1543 struct xhci_trb trb; 1544 uint32_t temp; 1545 1546 DPRINTF("\n"); 1547 1548 trb.qwTrb0 = htole64(input_ctx); 1549 trb.dwTrb2 = 0; 1550 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1551 XHCI_TRB_3_SLOT_SET(slot_id); 1552 trb.dwTrb3 = htole32(temp); 1553 1554 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1555 } 1556 1557 static usb_error_t 1558 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1559 uint8_t ep_id, uint8_t slot_id) 1560 { 1561 struct xhci_trb trb; 1562 uint32_t temp; 1563 1564 DPRINTF("\n"); 1565 1566 trb.qwTrb0 = 0; 1567 trb.dwTrb2 = 0; 1568 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1569 XHCI_TRB_3_SLOT_SET(slot_id) | 1570 XHCI_TRB_3_EP_SET(ep_id); 1571 1572 if (preserve) 1573 temp |= XHCI_TRB_3_PRSV_BIT; 1574 1575 trb.dwTrb3 = htole32(temp); 1576 1577 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1578 } 1579 1580 static usb_error_t 1581 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1582 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1583 { 1584 struct xhci_trb trb; 1585 uint32_t temp; 1586 1587 DPRINTF("\n"); 1588 1589 trb.qwTrb0 = htole64(dequeue_ptr); 1590 1591 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1592 trb.dwTrb2 = htole32(temp); 1593 1594 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1595 XHCI_TRB_3_SLOT_SET(slot_id) | 1596 XHCI_TRB_3_EP_SET(ep_id); 1597 trb.dwTrb3 = htole32(temp); 1598 1599 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1600 } 1601 1602 static usb_error_t 1603 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1604 uint8_t ep_id, uint8_t slot_id) 1605 { 1606 struct xhci_trb trb; 1607 uint32_t temp; 1608 1609 DPRINTF("\n"); 1610 1611 trb.qwTrb0 = 0; 1612 trb.dwTrb2 = 0; 1613 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1614 XHCI_TRB_3_SLOT_SET(slot_id) | 1615 XHCI_TRB_3_EP_SET(ep_id); 1616 1617 if (suspend) 1618 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1619 1620 trb.dwTrb3 = htole32(temp); 1621 1622 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1623 } 1624 1625 static usb_error_t 1626 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1627 { 1628 struct xhci_trb trb; 1629 uint32_t temp; 1630 1631 DPRINTF("\n"); 1632 1633 trb.qwTrb0 = 0; 1634 trb.dwTrb2 = 0; 1635 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1636 XHCI_TRB_3_SLOT_SET(slot_id); 1637 1638 trb.dwTrb3 = htole32(temp); 1639 1640 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1641 } 1642 1643 /*------------------------------------------------------------------------* 1644 * xhci_interrupt - XHCI interrupt handler 1645 *------------------------------------------------------------------------*/ 1646 void 1647 xhci_interrupt(struct xhci_softc *sc) 1648 { 1649 uint32_t status; 1650 uint32_t temp; 1651 1652 USB_BUS_LOCK(&sc->sc_bus); 1653 1654 status = XREAD4(sc, oper, XHCI_USBSTS); 1655 1656 /* acknowledge interrupts, if any */ 1657 if (status != 0) { 1658 XWRITE4(sc, oper, XHCI_USBSTS, status); 1659 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1660 } 1661 1662 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1663 1664 /* force clearing of pending interrupts */ 1665 if (temp & XHCI_IMAN_INTR_PEND) 1666 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1667 1668 /* check for event(s) */ 1669 xhci_interrupt_poll(sc); 1670 1671 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1672 XHCI_STS_HSE | XHCI_STS_HCE)) { 1673 if (status & XHCI_STS_PCD) { 1674 xhci_root_intr(sc); 1675 } 1676 1677 if (status & XHCI_STS_HCH) { 1678 printf("%s: host controller halted\n", 1679 __FUNCTION__); 1680 } 1681 1682 if (status & XHCI_STS_HSE) { 1683 printf("%s: host system error\n", 1684 __FUNCTION__); 1685 } 1686 1687 if (status & XHCI_STS_HCE) { 1688 printf("%s: host controller error\n", 1689 __FUNCTION__); 1690 } 1691 } 1692 USB_BUS_UNLOCK(&sc->sc_bus); 1693 } 1694 1695 /*------------------------------------------------------------------------* 1696 * xhci_timeout - XHCI timeout handler 1697 *------------------------------------------------------------------------*/ 1698 static void 1699 xhci_timeout(void *arg) 1700 { 1701 struct usb_xfer *xfer = arg; 1702 1703 DPRINTF("xfer=%p\n", xfer); 1704 1705 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1706 1707 /* transfer is transferred */ 1708 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1709 } 1710 1711 static void 1712 xhci_do_poll(struct usb_bus *bus) 1713 { 1714 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1715 1716 USB_BUS_LOCK(&sc->sc_bus); 1717 xhci_interrupt_poll(sc); 1718 USB_BUS_UNLOCK(&sc->sc_bus); 1719 } 1720 1721 static void 1722 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1723 { 1724 struct usb_page_search buf_res; 1725 struct xhci_td *td; 1726 struct xhci_td *td_next; 1727 struct xhci_td *td_alt_next; 1728 struct xhci_td *td_first; 1729 uint32_t buf_offset; 1730 uint32_t average; 1731 uint32_t len_old; 1732 uint32_t npkt_off; 1733 uint32_t dword; 1734 uint8_t shortpkt_old; 1735 uint8_t precompute; 1736 uint8_t x; 1737 1738 td_alt_next = NULL; 1739 buf_offset = 0; 1740 shortpkt_old = temp->shortpkt; 1741 len_old = temp->len; 1742 npkt_off = 0; 1743 precompute = 1; 1744 1745 restart: 1746 1747 td = temp->td; 1748 td_next = td_first = temp->td_next; 1749 1750 while (1) { 1751 if (temp->len == 0) { 1752 if (temp->shortpkt) 1753 break; 1754 1755 /* send a Zero Length Packet, ZLP, last */ 1756 1757 temp->shortpkt = 1; 1758 average = 0; 1759 1760 } else { 1761 average = temp->average; 1762 1763 if (temp->len < average) { 1764 if (temp->len % temp->max_packet_size) { 1765 temp->shortpkt = 1; 1766 } 1767 average = temp->len; 1768 } 1769 } 1770 1771 if (td_next == NULL) 1772 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1773 1774 /* get next TD */ 1775 1776 td = td_next; 1777 td_next = td->obj_next; 1778 1779 /* check if we are pre-computing */ 1780 1781 if (precompute) { 1782 /* update remaining length */ 1783 1784 temp->len -= average; 1785 1786 continue; 1787 } 1788 /* fill out current TD */ 1789 1790 td->len = average; 1791 td->remainder = 0; 1792 td->status = 0; 1793 1794 /* update remaining length */ 1795 1796 temp->len -= average; 1797 1798 /* reset TRB index */ 1799 1800 x = 0; 1801 1802 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1803 /* immediate data */ 1804 1805 if (average > 8) 1806 average = 8; 1807 1808 td->td_trb[0].qwTrb0 = 0; 1809 1810 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1811 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1812 average); 1813 1814 dword = XHCI_TRB_2_BYTES_SET(8) | 1815 XHCI_TRB_2_TDSZ_SET(0) | 1816 XHCI_TRB_2_IRQ_SET(0); 1817 1818 td->td_trb[0].dwTrb2 = htole32(dword); 1819 1820 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1821 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1822 1823 /* check wLength */ 1824 if (td->td_trb[0].qwTrb0 & 1825 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1826 if (td->td_trb[0].qwTrb0 & 1827 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1828 dword |= XHCI_TRB_3_TRT_IN; 1829 else 1830 dword |= XHCI_TRB_3_TRT_OUT; 1831 } 1832 1833 td->td_trb[0].dwTrb3 = htole32(dword); 1834 #ifdef USB_DEBUG 1835 xhci_dump_trb(&td->td_trb[x]); 1836 #endif 1837 x++; 1838 1839 } else do { 1840 uint32_t npkt; 1841 1842 /* fill out buffer pointers */ 1843 1844 if (average == 0) { 1845 memset(&buf_res, 0, sizeof(buf_res)); 1846 } else { 1847 usbd_get_page(temp->pc, temp->offset + 1848 buf_offset, &buf_res); 1849 1850 /* get length to end of page */ 1851 if (buf_res.length > average) 1852 buf_res.length = average; 1853 1854 /* check for maximum length */ 1855 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1856 buf_res.length = XHCI_TD_PAGE_SIZE; 1857 1858 npkt_off += buf_res.length; 1859 } 1860 1861 /* set up npkt */ 1862 npkt = howmany(len_old - npkt_off, 1863 temp->max_packet_size); 1864 1865 if (npkt == 0) 1866 npkt = 1; 1867 else if (npkt > 31) 1868 npkt = 31; 1869 1870 /* fill out TRB's */ 1871 td->td_trb[x].qwTrb0 = 1872 htole64((uint64_t)buf_res.physaddr); 1873 1874 dword = 1875 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1876 XHCI_TRB_2_TDSZ_SET(npkt) | 1877 XHCI_TRB_2_IRQ_SET(0); 1878 1879 td->td_trb[x].dwTrb2 = htole32(dword); 1880 1881 switch (temp->trb_type) { 1882 case XHCI_TRB_TYPE_ISOCH: 1883 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1884 XHCI_TRB_3_TBC_SET(temp->tbc) | 1885 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1886 if (td != td_first) { 1887 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1888 } else if (temp->do_isoc_sync != 0) { 1889 temp->do_isoc_sync = 0; 1890 /* wait until "isoc_frame" */ 1891 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1892 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1893 } else { 1894 /* start data transfer at next interval */ 1895 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1896 XHCI_TRB_3_ISO_SIA_BIT; 1897 } 1898 if (temp->direction == UE_DIR_IN) 1899 dword |= XHCI_TRB_3_ISP_BIT; 1900 break; 1901 case XHCI_TRB_TYPE_DATA_STAGE: 1902 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1903 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1904 if (temp->direction == UE_DIR_IN) 1905 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1906 /* 1907 * Section 3.2.9 in the XHCI 1908 * specification about control 1909 * transfers says that we should use a 1910 * normal-TRB if there are more TRBs 1911 * extending the data-stage 1912 * TRB. Update the "trb_type". 1913 */ 1914 temp->trb_type = XHCI_TRB_TYPE_NORMAL; 1915 break; 1916 case XHCI_TRB_TYPE_STATUS_STAGE: 1917 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1918 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1919 if (temp->direction == UE_DIR_IN) 1920 dword |= XHCI_TRB_3_DIR_IN; 1921 break; 1922 default: /* XHCI_TRB_TYPE_NORMAL */ 1923 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1924 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1925 if (temp->direction == UE_DIR_IN) 1926 dword |= XHCI_TRB_3_ISP_BIT; 1927 break; 1928 } 1929 td->td_trb[x].dwTrb3 = htole32(dword); 1930 1931 average -= buf_res.length; 1932 buf_offset += buf_res.length; 1933 #ifdef USB_DEBUG 1934 xhci_dump_trb(&td->td_trb[x]); 1935 #endif 1936 x++; 1937 1938 } while (average != 0); 1939 1940 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1941 1942 /* store number of data TRB's */ 1943 1944 td->ntrb = x; 1945 1946 DPRINTF("NTRB=%u\n", x); 1947 1948 /* fill out link TRB */ 1949 1950 if (td_next != NULL) { 1951 /* link the current TD with the next one */ 1952 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1953 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1954 } else { 1955 /* this field will get updated later */ 1956 DPRINTF("NOLINK\n"); 1957 } 1958 1959 dword = XHCI_TRB_2_IRQ_SET(0); 1960 1961 td->td_trb[x].dwTrb2 = htole32(dword); 1962 1963 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1964 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1965 /* 1966 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1967 * frame only receives a single short packet event 1968 * by setting the CHAIN bit in the LINK field. In 1969 * addition some XHCI controllers have problems 1970 * sending a ZLP unless the CHAIN-BIT is set in 1971 * the LINK TRB. 1972 */ 1973 XHCI_TRB_3_CHAIN_BIT; 1974 1975 td->td_trb[x].dwTrb3 = htole32(dword); 1976 1977 td->alt_next = td_alt_next; 1978 #ifdef USB_DEBUG 1979 xhci_dump_trb(&td->td_trb[x]); 1980 #endif 1981 usb_pc_cpu_flush(td->page_cache); 1982 } 1983 1984 if (precompute) { 1985 precompute = 0; 1986 1987 /* set up alt next pointer, if any */ 1988 if (temp->last_frame) { 1989 td_alt_next = NULL; 1990 } else { 1991 /* we use this field internally */ 1992 td_alt_next = td_next; 1993 } 1994 1995 /* restore */ 1996 temp->shortpkt = shortpkt_old; 1997 temp->len = len_old; 1998 goto restart; 1999 } 2000 2001 /* 2002 * Remove cycle bit from the first TRB if we are 2003 * stepping them: 2004 */ 2005 if (temp->step_td != 0) { 2006 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2007 usb_pc_cpu_flush(td_first->page_cache); 2008 } 2009 2010 /* clear TD SIZE to zero, hence this is the last TRB */ 2011 /* remove chain bit because this is the last data TRB in the chain */ 2012 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31)); 2013 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 2014 /* remove CHAIN-BIT from last LINK TRB */ 2015 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 2016 2017 usb_pc_cpu_flush(td->page_cache); 2018 2019 temp->td = td; 2020 temp->td_next = td_next; 2021 } 2022 2023 static void 2024 xhci_setup_generic_chain(struct usb_xfer *xfer) 2025 { 2026 struct xhci_std_temp temp; 2027 struct xhci_td *td; 2028 uint32_t x; 2029 uint32_t y; 2030 uint8_t mult; 2031 2032 temp.do_isoc_sync = 0; 2033 temp.step_td = 0; 2034 temp.tbc = 0; 2035 temp.tlbpc = 0; 2036 temp.average = xfer->max_hc_frame_size; 2037 temp.max_packet_size = xfer->max_packet_size; 2038 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 2039 temp.pc = NULL; 2040 temp.last_frame = 0; 2041 temp.offset = 0; 2042 temp.multishort = xfer->flags_int.isochronous_xfr || 2043 xfer->flags_int.control_xfr || 2044 xfer->flags_int.short_frames_ok; 2045 2046 /* toggle the DMA set we are using */ 2047 xfer->flags_int.curr_dma_set ^= 1; 2048 2049 /* get next DMA set */ 2050 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2051 2052 temp.td = NULL; 2053 temp.td_next = td; 2054 2055 xfer->td_transfer_first = td; 2056 xfer->td_transfer_cache = td; 2057 2058 if (xfer->flags_int.isochronous_xfr) { 2059 uint8_t shift; 2060 2061 /* compute multiplier for ISOCHRONOUS transfers */ 2062 mult = xfer->endpoint->ecomp ? 2063 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2064 : 0; 2065 /* check for USB 2.0 multiplier */ 2066 if (mult == 0) { 2067 mult = (xfer->endpoint->edesc-> 2068 wMaxPacketSize[1] >> 3) & 3; 2069 } 2070 /* range check */ 2071 if (mult > 2) 2072 mult = 3; 2073 else 2074 mult++; 2075 2076 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2077 2078 DPRINTF("MFINDEX=0x%08x\n", x); 2079 2080 switch (usbd_get_speed(xfer->xroot->udev)) { 2081 case USB_SPEED_FULL: 2082 shift = 3; 2083 temp.isoc_delta = 8; /* 1ms */ 2084 x += temp.isoc_delta - 1; 2085 x &= ~(temp.isoc_delta - 1); 2086 break; 2087 default: 2088 shift = usbd_xfer_get_fps_shift(xfer); 2089 temp.isoc_delta = 1U << shift; 2090 x += temp.isoc_delta - 1; 2091 x &= ~(temp.isoc_delta - 1); 2092 /* simple frame load balancing */ 2093 x += xfer->endpoint->usb_uframe; 2094 break; 2095 } 2096 2097 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2098 2099 if ((xfer->endpoint->is_synced == 0) || 2100 (y < (xfer->nframes << shift)) || 2101 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2102 /* 2103 * If there is data underflow or the pipe 2104 * queue is empty we schedule the transfer a 2105 * few frames ahead of the current frame 2106 * position. Else two isochronous transfers 2107 * might overlap. 2108 */ 2109 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2110 xfer->endpoint->is_synced = 1; 2111 temp.do_isoc_sync = 1; 2112 2113 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2114 } 2115 2116 /* compute isochronous completion time */ 2117 2118 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2119 2120 xfer->isoc_time_complete = 2121 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2122 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2123 2124 x = 0; 2125 temp.isoc_frame = xfer->endpoint->isoc_next; 2126 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2127 2128 xfer->endpoint->isoc_next += xfer->nframes << shift; 2129 2130 } else if (xfer->flags_int.control_xfr) { 2131 /* check if we should prepend a setup message */ 2132 2133 if (xfer->flags_int.control_hdr) { 2134 temp.len = xfer->frlengths[0]; 2135 temp.pc = xfer->frbuffers + 0; 2136 temp.shortpkt = temp.len ? 1 : 0; 2137 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2138 temp.direction = 0; 2139 2140 /* check for last frame */ 2141 if (xfer->nframes == 1) { 2142 /* no STATUS stage yet, SETUP is last */ 2143 if (xfer->flags_int.control_act) 2144 temp.last_frame = 1; 2145 } 2146 2147 xhci_setup_generic_chain_sub(&temp); 2148 } 2149 x = 1; 2150 mult = 1; 2151 temp.isoc_delta = 0; 2152 temp.isoc_frame = 0; 2153 temp.trb_type = xfer->flags_int.control_did_data ? 2154 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE; 2155 } else { 2156 x = 0; 2157 mult = 1; 2158 temp.isoc_delta = 0; 2159 temp.isoc_frame = 0; 2160 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2161 } 2162 2163 if (x != xfer->nframes) { 2164 /* set up page_cache pointer */ 2165 temp.pc = xfer->frbuffers + x; 2166 /* set endpoint direction */ 2167 temp.direction = UE_GET_DIR(xfer->endpointno); 2168 } 2169 2170 while (x != xfer->nframes) { 2171 /* DATA0 / DATA1 message */ 2172 2173 temp.len = xfer->frlengths[x]; 2174 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2175 x != 0 && temp.multishort == 0); 2176 2177 x++; 2178 2179 if (x == xfer->nframes) { 2180 if (xfer->flags_int.control_xfr) { 2181 /* no STATUS stage yet, DATA is last */ 2182 if (xfer->flags_int.control_act) 2183 temp.last_frame = 1; 2184 } else { 2185 temp.last_frame = 1; 2186 } 2187 } 2188 if (temp.len == 0) { 2189 /* make sure that we send an USB packet */ 2190 2191 temp.shortpkt = 0; 2192 2193 temp.tbc = 0; 2194 temp.tlbpc = mult - 1; 2195 2196 } else if (xfer->flags_int.isochronous_xfr) { 2197 uint8_t tdpc; 2198 2199 /* 2200 * Isochronous transfers don't have short 2201 * packet termination: 2202 */ 2203 2204 temp.shortpkt = 1; 2205 2206 /* isochronous transfers have a transfer limit */ 2207 2208 if (temp.len > xfer->max_frame_size) 2209 temp.len = xfer->max_frame_size; 2210 2211 /* compute TD packet count */ 2212 tdpc = howmany(temp.len, xfer->max_packet_size); 2213 2214 temp.tbc = howmany(tdpc, mult) - 1; 2215 temp.tlbpc = (tdpc % mult); 2216 2217 if (temp.tlbpc == 0) 2218 temp.tlbpc = mult - 1; 2219 else 2220 temp.tlbpc--; 2221 } else { 2222 /* regular data transfer */ 2223 2224 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2225 } 2226 2227 xhci_setup_generic_chain_sub(&temp); 2228 2229 if (xfer->flags_int.isochronous_xfr) { 2230 temp.offset += xfer->frlengths[x - 1]; 2231 temp.isoc_frame += temp.isoc_delta; 2232 } else { 2233 /* get next Page Cache pointer */ 2234 temp.pc = xfer->frbuffers + x; 2235 } 2236 } 2237 2238 /* check if we should append a status stage */ 2239 2240 if (xfer->flags_int.control_xfr && 2241 !xfer->flags_int.control_act) { 2242 /* 2243 * Send a DATA1 message and invert the current 2244 * endpoint direction. 2245 */ 2246 if (xhcictlstep || temp.sc->sc_ctlstep) { 2247 /* 2248 * Some XHCI controllers will not delay the 2249 * status stage until the next SOF. Force this 2250 * behaviour to avoid failed control 2251 * transfers. 2252 */ 2253 temp.step_td = (xfer->nframes != 0); 2254 } else { 2255 temp.step_td = 0; 2256 } 2257 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2258 temp.len = 0; 2259 temp.pc = NULL; 2260 temp.shortpkt = 0; 2261 temp.last_frame = 1; 2262 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2263 2264 xhci_setup_generic_chain_sub(&temp); 2265 } 2266 2267 td = temp.td; 2268 2269 /* must have at least one frame! */ 2270 2271 xfer->td_transfer_last = td; 2272 2273 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2274 } 2275 2276 static void 2277 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2278 { 2279 struct usb_page_search buf_res; 2280 struct xhci_dev_ctx_addr *pdctxa; 2281 2282 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2283 2284 pdctxa = buf_res.buffer; 2285 2286 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2287 2288 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2289 2290 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2291 } 2292 2293 static usb_error_t 2294 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2295 { 2296 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2297 struct usb_page_search buf_inp; 2298 struct xhci_input_dev_ctx *pinp; 2299 uint32_t temp; 2300 uint8_t index; 2301 uint8_t x; 2302 2303 index = udev->controller_slot_id; 2304 2305 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2306 2307 pinp = buf_inp.buffer; 2308 2309 if (drop) { 2310 mask &= XHCI_INCTX_NON_CTRL_MASK; 2311 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2312 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2313 } else { 2314 /* 2315 * Some hardware requires that we drop the endpoint 2316 * context before adding it again: 2317 */ 2318 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 2319 mask & XHCI_INCTX_NON_CTRL_MASK); 2320 2321 /* Add new endpoint context */ 2322 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2323 2324 /* find most significant set bit */ 2325 for (x = 31; x != 1; x--) { 2326 if (mask & (1 << x)) 2327 break; 2328 } 2329 2330 /* adjust */ 2331 x--; 2332 2333 /* figure out the maximum number of contexts */ 2334 if (x > sc->sc_hw.devs[index].context_num) 2335 sc->sc_hw.devs[index].context_num = x; 2336 else 2337 x = sc->sc_hw.devs[index].context_num; 2338 2339 /* update number of contexts */ 2340 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2341 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2342 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2343 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2344 } 2345 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2346 return (0); 2347 } 2348 2349 static usb_error_t 2350 xhci_configure_endpoint(struct usb_device *udev, 2351 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2352 uint16_t interval, uint8_t max_packet_count, 2353 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2354 uint16_t max_frame_size, uint8_t ep_mode) 2355 { 2356 struct usb_page_search buf_inp; 2357 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2358 struct xhci_input_dev_ctx *pinp; 2359 uint64_t ring_addr = pepext->physaddr; 2360 uint32_t temp; 2361 uint8_t index; 2362 uint8_t epno; 2363 uint8_t type; 2364 2365 index = udev->controller_slot_id; 2366 2367 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2368 2369 pinp = buf_inp.buffer; 2370 2371 epno = edesc->bEndpointAddress; 2372 type = edesc->bmAttributes & UE_XFERTYPE; 2373 2374 if (type == UE_CONTROL) 2375 epno |= UE_DIR_IN; 2376 2377 epno = XHCI_EPNO2EPID(epno); 2378 2379 if (epno == 0) 2380 return (USB_ERR_NO_PIPE); /* invalid */ 2381 2382 if (max_packet_count == 0) 2383 return (USB_ERR_BAD_BUFSIZE); 2384 2385 max_packet_count--; 2386 2387 if (mult == 0) 2388 return (USB_ERR_BAD_BUFSIZE); 2389 2390 /* store endpoint mode */ 2391 pepext->trb_ep_mode = ep_mode; 2392 /* store bMaxPacketSize for control endpoints */ 2393 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0]; 2394 usb_pc_cpu_flush(pepext->page_cache); 2395 2396 if (ep_mode == USB_EP_MODE_STREAMS) { 2397 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2398 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2399 XHCI_EPCTX_0_LSA_SET(1); 2400 2401 ring_addr += sizeof(struct xhci_trb) * 2402 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2403 } else { 2404 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2405 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2406 XHCI_EPCTX_0_LSA_SET(0); 2407 2408 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2409 } 2410 2411 switch (udev->speed) { 2412 case USB_SPEED_FULL: 2413 case USB_SPEED_LOW: 2414 /* 1ms -> 125us */ 2415 fps_shift += 3; 2416 break; 2417 default: 2418 break; 2419 } 2420 2421 switch (type) { 2422 case UE_INTERRUPT: 2423 if (fps_shift > 3) 2424 fps_shift--; 2425 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2426 break; 2427 case UE_ISOCHRONOUS: 2428 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2429 2430 switch (udev->speed) { 2431 case USB_SPEED_SUPER: 2432 if (mult > 3) 2433 mult = 3; 2434 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2435 max_packet_count /= mult; 2436 break; 2437 default: 2438 break; 2439 } 2440 break; 2441 default: 2442 break; 2443 } 2444 2445 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2446 2447 temp = 2448 XHCI_EPCTX_1_HID_SET(0) | 2449 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2450 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2451 2452 /* 2453 * Always enable the "three strikes and you are gone" feature 2454 * except for ISOCHRONOUS endpoints. This is suggested by 2455 * section 4.3.3 in the XHCI specification about device slot 2456 * initialisation. 2457 */ 2458 if (type != UE_ISOCHRONOUS) 2459 temp |= XHCI_EPCTX_1_CERR_SET(3); 2460 2461 switch (type) { 2462 case UE_CONTROL: 2463 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2464 break; 2465 case UE_ISOCHRONOUS: 2466 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2467 break; 2468 case UE_BULK: 2469 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2470 break; 2471 default: 2472 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2473 break; 2474 } 2475 2476 /* check for IN direction */ 2477 if (epno & 1) 2478 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2479 2480 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2481 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2482 2483 switch (edesc->bmAttributes & UE_XFERTYPE) { 2484 case UE_INTERRUPT: 2485 case UE_ISOCHRONOUS: 2486 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2487 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2488 max_frame_size)); 2489 break; 2490 case UE_CONTROL: 2491 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2492 break; 2493 default: 2494 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2495 break; 2496 } 2497 2498 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2499 2500 #ifdef USB_DEBUG 2501 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2502 #endif 2503 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2504 2505 return (0); /* success */ 2506 } 2507 2508 static usb_error_t 2509 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2510 { 2511 struct xhci_endpoint_ext *pepext; 2512 struct usb_endpoint_ss_comp_descriptor *ecomp; 2513 usb_stream_t x; 2514 2515 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2516 xfer->endpoint->edesc); 2517 2518 ecomp = xfer->endpoint->ecomp; 2519 2520 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2521 uint64_t temp; 2522 2523 /* halt any transfers */ 2524 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2525 2526 /* compute start of TRB ring for stream "x" */ 2527 temp = pepext->physaddr + 2528 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2529 XHCI_SCTX_0_SCT_SEC_TR_RING; 2530 2531 /* make tree structure */ 2532 pepext->trb[(XHCI_MAX_TRANSFERS * 2533 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2534 2535 /* reserved fields */ 2536 pepext->trb[(XHCI_MAX_TRANSFERS * 2537 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2538 pepext->trb[(XHCI_MAX_TRANSFERS * 2539 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2540 } 2541 usb_pc_cpu_flush(pepext->page_cache); 2542 2543 return (xhci_configure_endpoint(xfer->xroot->udev, 2544 xfer->endpoint->edesc, pepext, 2545 xfer->interval, xfer->max_packet_count, 2546 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2547 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2548 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2549 } 2550 2551 static usb_error_t 2552 xhci_configure_device(struct usb_device *udev) 2553 { 2554 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2555 struct usb_page_search buf_inp; 2556 struct usb_page_cache *pcinp; 2557 struct xhci_input_dev_ctx *pinp; 2558 struct usb_device *hubdev; 2559 uint32_t temp; 2560 uint32_t route; 2561 uint32_t rh_port; 2562 uint8_t is_hub; 2563 uint8_t index; 2564 uint8_t depth; 2565 2566 index = udev->controller_slot_id; 2567 2568 DPRINTF("index=%u\n", index); 2569 2570 pcinp = &sc->sc_hw.devs[index].input_pc; 2571 2572 usbd_get_page(pcinp, 0, &buf_inp); 2573 2574 pinp = buf_inp.buffer; 2575 2576 rh_port = 0; 2577 route = 0; 2578 2579 /* figure out route string and root HUB port number */ 2580 2581 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2582 if (hubdev->parent_hub == NULL) 2583 break; 2584 2585 depth = hubdev->parent_hub->depth; 2586 2587 /* 2588 * NOTE: HS/FS/LS devices and the SS root HUB can have 2589 * more than 15 ports 2590 */ 2591 2592 rh_port = hubdev->port_no; 2593 2594 if (depth == 0) 2595 break; 2596 2597 if (rh_port > 15) 2598 rh_port = 15; 2599 2600 if (depth < 6) 2601 route |= rh_port << (4 * (depth - 1)); 2602 } 2603 2604 DPRINTF("Route=0x%08x\n", route); 2605 2606 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2607 XHCI_SCTX_0_CTX_NUM_SET( 2608 sc->sc_hw.devs[index].context_num + 1); 2609 2610 switch (udev->speed) { 2611 case USB_SPEED_LOW: 2612 temp |= XHCI_SCTX_0_SPEED_SET(2); 2613 if (udev->parent_hs_hub != NULL && 2614 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2615 UDPROTO_HSHUBMTT) { 2616 DPRINTF("Device inherits MTT\n"); 2617 temp |= XHCI_SCTX_0_MTT_SET(1); 2618 } 2619 break; 2620 case USB_SPEED_HIGH: 2621 temp |= XHCI_SCTX_0_SPEED_SET(3); 2622 if (sc->sc_hw.devs[index].nports != 0 && 2623 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2624 DPRINTF("HUB supports MTT\n"); 2625 temp |= XHCI_SCTX_0_MTT_SET(1); 2626 } 2627 break; 2628 case USB_SPEED_FULL: 2629 temp |= XHCI_SCTX_0_SPEED_SET(1); 2630 if (udev->parent_hs_hub != NULL && 2631 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2632 UDPROTO_HSHUBMTT) { 2633 DPRINTF("Device inherits MTT\n"); 2634 temp |= XHCI_SCTX_0_MTT_SET(1); 2635 } 2636 break; 2637 default: 2638 temp |= XHCI_SCTX_0_SPEED_SET(4); 2639 break; 2640 } 2641 2642 is_hub = sc->sc_hw.devs[index].nports != 0 && 2643 (udev->speed == USB_SPEED_SUPER || 2644 udev->speed == USB_SPEED_HIGH); 2645 2646 if (is_hub) 2647 temp |= XHCI_SCTX_0_HUB_SET(1); 2648 2649 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2650 2651 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2652 2653 if (is_hub) { 2654 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2655 sc->sc_hw.devs[index].nports); 2656 } 2657 2658 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2659 2660 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2661 2662 if (is_hub) { 2663 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2664 sc->sc_hw.devs[index].tt); 2665 } 2666 2667 hubdev = udev->parent_hs_hub; 2668 2669 /* check if we should activate the transaction translator */ 2670 switch (udev->speed) { 2671 case USB_SPEED_FULL: 2672 case USB_SPEED_LOW: 2673 if (hubdev != NULL) { 2674 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2675 hubdev->controller_slot_id); 2676 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2677 udev->hs_port_no); 2678 } 2679 break; 2680 default: 2681 break; 2682 } 2683 2684 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2685 2686 /* 2687 * These fields should be initialized to zero, according to 2688 * XHCI section 6.2.2 - slot context: 2689 */ 2690 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2691 XHCI_SCTX_3_SLOT_STATE_SET(0); 2692 2693 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2694 2695 #ifdef USB_DEBUG 2696 xhci_dump_device(sc, &pinp->ctx_slot); 2697 #endif 2698 usb_pc_cpu_flush(pcinp); 2699 2700 return (0); /* success */ 2701 } 2702 2703 static usb_error_t 2704 xhci_alloc_device_ext(struct usb_device *udev) 2705 { 2706 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2707 struct usb_page_search buf_dev; 2708 struct usb_page_search buf_ep; 2709 struct xhci_trb *trb; 2710 struct usb_page_cache *pc; 2711 struct usb_page *pg; 2712 uint64_t addr; 2713 uint8_t index; 2714 uint8_t i; 2715 2716 index = udev->controller_slot_id; 2717 2718 pc = &sc->sc_hw.devs[index].device_pc; 2719 pg = &sc->sc_hw.devs[index].device_pg; 2720 2721 /* need to initialize the page cache */ 2722 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2723 2724 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2725 (2 * sizeof(struct xhci_dev_ctx)) : 2726 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2727 goto error; 2728 2729 usbd_get_page(pc, 0, &buf_dev); 2730 2731 pc = &sc->sc_hw.devs[index].input_pc; 2732 pg = &sc->sc_hw.devs[index].input_pg; 2733 2734 /* need to initialize the page cache */ 2735 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2736 2737 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2738 (2 * sizeof(struct xhci_input_dev_ctx)) : 2739 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2740 goto error; 2741 } 2742 2743 /* initialize all endpoint LINK TRBs */ 2744 2745 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2746 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2747 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2748 2749 /* need to initialize the page cache */ 2750 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2751 2752 if (usb_pc_alloc_mem(pc, pg, 2753 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2754 goto error; 2755 } 2756 2757 /* lookup endpoint TRB ring */ 2758 usbd_get_page(pc, 0, &buf_ep); 2759 2760 /* get TRB pointer */ 2761 trb = buf_ep.buffer; 2762 trb += XHCI_MAX_TRANSFERS - 1; 2763 2764 /* get TRB start address */ 2765 addr = buf_ep.physaddr; 2766 2767 /* create LINK TRB */ 2768 trb->qwTrb0 = htole64(addr); 2769 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2770 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2771 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2772 2773 usb_pc_cpu_flush(pc); 2774 } 2775 2776 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2777 2778 return (0); 2779 2780 error: 2781 xhci_free_device_ext(udev); 2782 2783 return (USB_ERR_NOMEM); 2784 } 2785 2786 static void 2787 xhci_free_device_ext(struct usb_device *udev) 2788 { 2789 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2790 uint8_t index; 2791 uint8_t i; 2792 2793 index = udev->controller_slot_id; 2794 xhci_set_slot_pointer(sc, index, 0); 2795 2796 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2797 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2798 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2799 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2800 } 2801 2802 static struct xhci_endpoint_ext * 2803 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2804 { 2805 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2806 struct xhci_endpoint_ext *pepext; 2807 struct usb_page_cache *pc; 2808 struct usb_page_search buf_ep; 2809 uint8_t epno; 2810 uint8_t index; 2811 2812 epno = edesc->bEndpointAddress; 2813 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2814 epno |= UE_DIR_IN; 2815 2816 epno = XHCI_EPNO2EPID(epno); 2817 2818 index = udev->controller_slot_id; 2819 2820 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2821 2822 usbd_get_page(pc, 0, &buf_ep); 2823 2824 pepext = &sc->sc_hw.devs[index].endp[epno]; 2825 pepext->page_cache = pc; 2826 pepext->trb = buf_ep.buffer; 2827 pepext->physaddr = buf_ep.physaddr; 2828 2829 return (pepext); 2830 } 2831 2832 static void 2833 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2834 { 2835 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2836 uint8_t epno; 2837 uint8_t index; 2838 2839 epno = xfer->endpointno; 2840 if (xfer->flags_int.control_xfr) 2841 epno |= UE_DIR_IN; 2842 2843 epno = XHCI_EPNO2EPID(epno); 2844 index = xfer->xroot->udev->controller_slot_id; 2845 2846 if (xfer->xroot->udev->flags.self_suspended == 0) { 2847 XWRITE4(sc, door, XHCI_DOORBELL(index), 2848 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2849 } 2850 } 2851 2852 static void 2853 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2854 { 2855 struct xhci_endpoint_ext *pepext; 2856 2857 if (xfer->flags_int.bandwidth_reclaimed) { 2858 xfer->flags_int.bandwidth_reclaimed = 0; 2859 2860 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2861 xfer->endpoint->edesc); 2862 2863 pepext->trb_used[xfer->stream_id]--; 2864 2865 pepext->xfer[xfer->qh_pos] = NULL; 2866 2867 if (error && pepext->trb_running != 0) { 2868 pepext->trb_halted = 1; 2869 pepext->trb_running = 0; 2870 } 2871 } 2872 } 2873 2874 static usb_error_t 2875 xhci_transfer_insert(struct usb_xfer *xfer) 2876 { 2877 struct xhci_td *td_first; 2878 struct xhci_td *td_last; 2879 struct xhci_trb *trb_link; 2880 struct xhci_endpoint_ext *pepext; 2881 uint64_t addr; 2882 usb_stream_t id; 2883 uint8_t i; 2884 uint8_t inext; 2885 uint8_t trb_limit; 2886 2887 DPRINTFN(8, "\n"); 2888 2889 id = xfer->stream_id; 2890 2891 /* check if already inserted */ 2892 if (xfer->flags_int.bandwidth_reclaimed) { 2893 DPRINTFN(8, "Already in schedule\n"); 2894 return (0); 2895 } 2896 2897 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2898 xfer->endpoint->edesc); 2899 2900 td_first = xfer->td_transfer_first; 2901 td_last = xfer->td_transfer_last; 2902 addr = pepext->physaddr; 2903 2904 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2905 case UE_CONTROL: 2906 case UE_INTERRUPT: 2907 /* single buffered */ 2908 trb_limit = 1; 2909 break; 2910 default: 2911 /* multi buffered */ 2912 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2913 break; 2914 } 2915 2916 if (pepext->trb_used[id] >= trb_limit) { 2917 DPRINTFN(8, "Too many TDs queued.\n"); 2918 return (USB_ERR_NOMEM); 2919 } 2920 2921 /* check if bMaxPacketSize changed */ 2922 if (xfer->flags_int.control_xfr != 0 && 2923 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) { 2924 DPRINTFN(8, "Reconfigure control endpoint\n"); 2925 2926 /* force driver to reconfigure endpoint */ 2927 pepext->trb_halted = 1; 2928 pepext->trb_running = 0; 2929 } 2930 2931 /* check for stopped condition, after putting transfer on interrupt queue */ 2932 if (pepext->trb_running == 0) { 2933 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2934 2935 DPRINTFN(8, "Not running\n"); 2936 2937 /* start configuration */ 2938 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2939 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2940 return (0); 2941 } 2942 2943 pepext->trb_used[id]++; 2944 2945 /* get current TRB index */ 2946 i = pepext->trb_index[id]; 2947 2948 /* get next TRB index */ 2949 inext = (i + 1); 2950 2951 /* the last entry of the ring is a hardcoded link TRB */ 2952 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2953 inext = 0; 2954 2955 /* store next TRB index, before stream ID offset is added */ 2956 pepext->trb_index[id] = inext; 2957 2958 /* offset for stream */ 2959 i += id * XHCI_MAX_TRANSFERS; 2960 inext += id * XHCI_MAX_TRANSFERS; 2961 2962 /* compute terminating return address */ 2963 addr += (inext * sizeof(struct xhci_trb)); 2964 2965 /* compute link TRB pointer */ 2966 trb_link = td_last->td_trb + td_last->ntrb; 2967 2968 /* update next pointer of last link TRB */ 2969 trb_link->qwTrb0 = htole64(addr); 2970 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2971 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2972 XHCI_TRB_3_CYCLE_BIT | 2973 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2974 2975 #ifdef USB_DEBUG 2976 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2977 #endif 2978 usb_pc_cpu_flush(td_last->page_cache); 2979 2980 /* write ahead chain end marker */ 2981 2982 pepext->trb[inext].qwTrb0 = 0; 2983 pepext->trb[inext].dwTrb2 = 0; 2984 pepext->trb[inext].dwTrb3 = 0; 2985 2986 /* update next pointer of link TRB */ 2987 2988 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2989 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2990 2991 #ifdef USB_DEBUG 2992 xhci_dump_trb(&pepext->trb[i]); 2993 #endif 2994 usb_pc_cpu_flush(pepext->page_cache); 2995 2996 /* toggle cycle bit which activates the transfer chain */ 2997 2998 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2999 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 3000 3001 usb_pc_cpu_flush(pepext->page_cache); 3002 3003 DPRINTF("qh_pos = %u\n", i); 3004 3005 pepext->xfer[i] = xfer; 3006 3007 xfer->qh_pos = i; 3008 3009 xfer->flags_int.bandwidth_reclaimed = 1; 3010 3011 xhci_endpoint_doorbell(xfer); 3012 3013 return (0); 3014 } 3015 3016 static void 3017 xhci_root_intr(struct xhci_softc *sc) 3018 { 3019 uint16_t i; 3020 3021 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3022 3023 /* clear any old interrupt data */ 3024 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 3025 3026 for (i = 1; i <= sc->sc_noport; i++) { 3027 /* pick out CHANGE bits from the status register */ 3028 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 3029 XHCI_PS_CSC | XHCI_PS_PEC | 3030 XHCI_PS_OCC | XHCI_PS_WRC | 3031 XHCI_PS_PRC | XHCI_PS_PLC | 3032 XHCI_PS_CEC)) { 3033 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 3034 DPRINTF("port %d changed\n", i); 3035 } 3036 } 3037 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3038 sizeof(sc->sc_hub_idata)); 3039 } 3040 3041 /*------------------------------------------------------------------------* 3042 * xhci_device_done - XHCI done handler 3043 * 3044 * NOTE: This function can be called two times in a row on 3045 * the same USB transfer. From close and from interrupt. 3046 *------------------------------------------------------------------------*/ 3047 static void 3048 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 3049 { 3050 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 3051 xfer, xfer->endpoint, error); 3052 3053 /* remove transfer from HW queue */ 3054 xhci_transfer_remove(xfer, error); 3055 3056 /* dequeue transfer and start next transfer */ 3057 usbd_transfer_done(xfer, error); 3058 } 3059 3060 /*------------------------------------------------------------------------* 3061 * XHCI data transfer support (generic type) 3062 *------------------------------------------------------------------------*/ 3063 static void 3064 xhci_device_generic_open(struct usb_xfer *xfer) 3065 { 3066 if (xfer->flags_int.isochronous_xfr) { 3067 switch (xfer->xroot->udev->speed) { 3068 case USB_SPEED_FULL: 3069 break; 3070 default: 3071 usb_hs_bandwidth_alloc(xfer); 3072 break; 3073 } 3074 } 3075 } 3076 3077 static void 3078 xhci_device_generic_close(struct usb_xfer *xfer) 3079 { 3080 DPRINTF("\n"); 3081 3082 xhci_device_done(xfer, USB_ERR_CANCELLED); 3083 3084 if (xfer->flags_int.isochronous_xfr) { 3085 switch (xfer->xroot->udev->speed) { 3086 case USB_SPEED_FULL: 3087 break; 3088 default: 3089 usb_hs_bandwidth_free(xfer); 3090 break; 3091 } 3092 } 3093 } 3094 3095 static void 3096 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3097 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3098 { 3099 struct usb_xfer *xfer; 3100 3101 /* check if there is a current transfer */ 3102 xfer = ep->endpoint_q[stream_id].curr; 3103 if (xfer == NULL) 3104 return; 3105 3106 /* 3107 * Check if the current transfer is started and then pickup 3108 * the next one, if any. Else wait for next start event due to 3109 * block on failure feature. 3110 */ 3111 if (!xfer->flags_int.bandwidth_reclaimed) 3112 return; 3113 3114 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3115 if (xfer == NULL) { 3116 /* 3117 * In case of enter we have to consider that the 3118 * transfer is queued by the USB core after the enter 3119 * method is called. 3120 */ 3121 xfer = enter_xfer; 3122 3123 if (xfer == NULL) 3124 return; 3125 } 3126 3127 /* try to multi buffer */ 3128 xhci_transfer_insert(xfer); 3129 } 3130 3131 static void 3132 xhci_device_generic_enter(struct usb_xfer *xfer) 3133 { 3134 DPRINTF("\n"); 3135 3136 /* set up TD's and QH */ 3137 xhci_setup_generic_chain(xfer); 3138 3139 xhci_device_generic_multi_enter(xfer->endpoint, 3140 xfer->stream_id, xfer); 3141 } 3142 3143 static void 3144 xhci_device_generic_start(struct usb_xfer *xfer) 3145 { 3146 DPRINTF("\n"); 3147 3148 /* try to insert xfer on HW queue */ 3149 xhci_transfer_insert(xfer); 3150 3151 /* try to multi buffer */ 3152 xhci_device_generic_multi_enter(xfer->endpoint, 3153 xfer->stream_id, NULL); 3154 3155 /* add transfer last on interrupt queue */ 3156 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3157 3158 /* start timeout, if any */ 3159 if (xfer->timeout != 0) 3160 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3161 } 3162 3163 static const struct usb_pipe_methods xhci_device_generic_methods = 3164 { 3165 .open = xhci_device_generic_open, 3166 .close = xhci_device_generic_close, 3167 .enter = xhci_device_generic_enter, 3168 .start = xhci_device_generic_start, 3169 }; 3170 3171 /*------------------------------------------------------------------------* 3172 * xhci root HUB support 3173 *------------------------------------------------------------------------* 3174 * Simulate a hardware HUB by handling all the necessary requests. 3175 *------------------------------------------------------------------------*/ 3176 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3177 3178 static const 3179 struct usb_device_descriptor xhci_devd = 3180 { 3181 .bLength = sizeof(xhci_devd), 3182 .bDescriptorType = UDESC_DEVICE, /* type */ 3183 HSETW(.bcdUSB, 0x0300), /* USB version */ 3184 .bDeviceClass = UDCLASS_HUB, /* class */ 3185 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3186 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3187 .bMaxPacketSize = 9, /* max packet size */ 3188 HSETW(.idVendor, 0x0000), /* vendor */ 3189 HSETW(.idProduct, 0x0000), /* product */ 3190 HSETW(.bcdDevice, 0x0100), /* device version */ 3191 .iManufacturer = 1, 3192 .iProduct = 2, 3193 .iSerialNumber = 0, 3194 .bNumConfigurations = 1, /* # of configurations */ 3195 }; 3196 3197 static const 3198 struct xhci_bos_desc xhci_bosd = { 3199 .bosd = { 3200 .bLength = sizeof(xhci_bosd.bosd), 3201 .bDescriptorType = UDESC_BOS, 3202 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3203 .bNumDeviceCaps = 3, 3204 }, 3205 .usb2extd = { 3206 .bLength = sizeof(xhci_bosd.usb2extd), 3207 .bDescriptorType = 1, 3208 .bDevCapabilityType = 2, 3209 .bmAttributes[0] = 2, 3210 }, 3211 .usbdcd = { 3212 .bLength = sizeof(xhci_bosd.usbdcd), 3213 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3214 .bDevCapabilityType = 3, 3215 .bmAttributes = 0, /* XXX */ 3216 HSETW(.wSpeedsSupported, 0x000C), 3217 .bFunctionalitySupport = 8, 3218 .bU1DevExitLat = 255, /* dummy - not used */ 3219 .wU2DevExitLat = { 0x00, 0x08 }, 3220 }, 3221 .cidd = { 3222 .bLength = sizeof(xhci_bosd.cidd), 3223 .bDescriptorType = 1, 3224 .bDevCapabilityType = 4, 3225 .bReserved = 0, 3226 .bContainerID = 0, /* XXX */ 3227 }, 3228 }; 3229 3230 static const 3231 struct xhci_config_desc xhci_confd = { 3232 .confd = { 3233 .bLength = sizeof(xhci_confd.confd), 3234 .bDescriptorType = UDESC_CONFIG, 3235 .wTotalLength[0] = sizeof(xhci_confd), 3236 .bNumInterface = 1, 3237 .bConfigurationValue = 1, 3238 .iConfiguration = 0, 3239 .bmAttributes = UC_SELF_POWERED, 3240 .bMaxPower = 0 /* max power */ 3241 }, 3242 .ifcd = { 3243 .bLength = sizeof(xhci_confd.ifcd), 3244 .bDescriptorType = UDESC_INTERFACE, 3245 .bNumEndpoints = 1, 3246 .bInterfaceClass = UICLASS_HUB, 3247 .bInterfaceSubClass = UISUBCLASS_HUB, 3248 .bInterfaceProtocol = 0, 3249 }, 3250 .endpd = { 3251 .bLength = sizeof(xhci_confd.endpd), 3252 .bDescriptorType = UDESC_ENDPOINT, 3253 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3254 .bmAttributes = UE_INTERRUPT, 3255 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3256 .bInterval = 255, 3257 }, 3258 .endpcd = { 3259 .bLength = sizeof(xhci_confd.endpcd), 3260 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3261 .bMaxBurst = 0, 3262 .bmAttributes = 0, 3263 }, 3264 }; 3265 3266 static const 3267 struct usb_hub_ss_descriptor xhci_hubd = { 3268 .bLength = sizeof(xhci_hubd), 3269 .bDescriptorType = UDESC_SS_HUB, 3270 }; 3271 3272 static usb_error_t 3273 xhci_roothub_exec(struct usb_device *udev, 3274 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3275 { 3276 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3277 const char *str_ptr; 3278 const void *ptr; 3279 uint32_t port; 3280 uint32_t v; 3281 uint16_t len; 3282 uint16_t i; 3283 uint16_t value; 3284 uint16_t index; 3285 uint8_t j; 3286 usb_error_t err; 3287 3288 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3289 3290 /* buffer reset */ 3291 ptr = (const void *)&sc->sc_hub_desc; 3292 len = 0; 3293 err = 0; 3294 3295 value = UGETW(req->wValue); 3296 index = UGETW(req->wIndex); 3297 3298 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3299 "wValue=0x%04x wIndex=0x%04x\n", 3300 req->bmRequestType, req->bRequest, 3301 UGETW(req->wLength), value, index); 3302 3303 #define C(x,y) ((x) | ((y) << 8)) 3304 switch (C(req->bRequest, req->bmRequestType)) { 3305 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3306 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3307 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3308 /* 3309 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3310 * for the integrated root hub. 3311 */ 3312 break; 3313 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3314 len = 1; 3315 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3316 break; 3317 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3318 switch (value >> 8) { 3319 case UDESC_DEVICE: 3320 if ((value & 0xff) != 0) { 3321 err = USB_ERR_IOERROR; 3322 goto done; 3323 } 3324 len = sizeof(xhci_devd); 3325 ptr = (const void *)&xhci_devd; 3326 break; 3327 3328 case UDESC_BOS: 3329 if ((value & 0xff) != 0) { 3330 err = USB_ERR_IOERROR; 3331 goto done; 3332 } 3333 len = sizeof(xhci_bosd); 3334 ptr = (const void *)&xhci_bosd; 3335 break; 3336 3337 case UDESC_CONFIG: 3338 if ((value & 0xff) != 0) { 3339 err = USB_ERR_IOERROR; 3340 goto done; 3341 } 3342 len = sizeof(xhci_confd); 3343 ptr = (const void *)&xhci_confd; 3344 break; 3345 3346 case UDESC_STRING: 3347 switch (value & 0xff) { 3348 case 0: /* Language table */ 3349 str_ptr = "\001"; 3350 break; 3351 3352 case 1: /* Vendor */ 3353 str_ptr = sc->sc_vendor; 3354 break; 3355 3356 case 2: /* Product */ 3357 str_ptr = "XHCI root HUB"; 3358 break; 3359 3360 default: 3361 str_ptr = ""; 3362 break; 3363 } 3364 3365 len = usb_make_str_desc( 3366 sc->sc_hub_desc.temp, 3367 sizeof(sc->sc_hub_desc.temp), 3368 str_ptr); 3369 break; 3370 3371 default: 3372 err = USB_ERR_IOERROR; 3373 goto done; 3374 } 3375 break; 3376 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3377 len = 1; 3378 sc->sc_hub_desc.temp[0] = 0; 3379 break; 3380 case C(UR_GET_STATUS, UT_READ_DEVICE): 3381 len = 2; 3382 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3383 break; 3384 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3385 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3386 len = 2; 3387 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3388 break; 3389 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3390 if (value >= XHCI_MAX_DEVICES) { 3391 err = USB_ERR_IOERROR; 3392 goto done; 3393 } 3394 break; 3395 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3396 if (value != 0 && value != 1) { 3397 err = USB_ERR_IOERROR; 3398 goto done; 3399 } 3400 sc->sc_conf = value; 3401 break; 3402 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3403 break; 3404 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3405 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3406 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3407 err = USB_ERR_IOERROR; 3408 goto done; 3409 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3410 break; 3411 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3412 break; 3413 /* Hub requests */ 3414 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3415 break; 3416 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3417 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3418 3419 if ((index < 1) || 3420 (index > sc->sc_noport)) { 3421 err = USB_ERR_IOERROR; 3422 goto done; 3423 } 3424 port = XHCI_PORTSC(index); 3425 3426 v = XREAD4(sc, oper, port); 3427 i = XHCI_PS_PLS_GET(v); 3428 v &= ~XHCI_PS_CLEAR; 3429 3430 switch (value) { 3431 case UHF_C_BH_PORT_RESET: 3432 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3433 break; 3434 case UHF_C_PORT_CONFIG_ERROR: 3435 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3436 break; 3437 case UHF_C_PORT_SUSPEND: 3438 case UHF_C_PORT_LINK_STATE: 3439 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3440 break; 3441 case UHF_C_PORT_CONNECTION: 3442 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3443 break; 3444 case UHF_C_PORT_ENABLE: 3445 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3446 break; 3447 case UHF_C_PORT_OVER_CURRENT: 3448 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3449 break; 3450 case UHF_C_PORT_RESET: 3451 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3452 break; 3453 case UHF_PORT_ENABLE: 3454 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3455 break; 3456 case UHF_PORT_POWER: 3457 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3458 break; 3459 case UHF_PORT_INDICATOR: 3460 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3461 break; 3462 case UHF_PORT_SUSPEND: 3463 3464 /* U3 -> U15 */ 3465 if (i == 3) { 3466 XWRITE4(sc, oper, port, v | 3467 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3468 } 3469 3470 /* wait 20ms for resume sequence to complete */ 3471 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3472 3473 /* U0 */ 3474 XWRITE4(sc, oper, port, v | 3475 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3476 break; 3477 default: 3478 err = USB_ERR_IOERROR; 3479 goto done; 3480 } 3481 break; 3482 3483 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3484 if ((value & 0xff) != 0) { 3485 err = USB_ERR_IOERROR; 3486 goto done; 3487 } 3488 3489 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3490 3491 sc->sc_hub_desc.hubd = xhci_hubd; 3492 3493 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3494 3495 if (XHCI_HCS0_PPC(v)) 3496 i = UHD_PWR_INDIVIDUAL; 3497 else 3498 i = UHD_PWR_GANGED; 3499 3500 if (XHCI_HCS0_PIND(v)) 3501 i |= UHD_PORT_IND; 3502 3503 i |= UHD_OC_INDIVIDUAL; 3504 3505 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3506 3507 /* see XHCI section 5.4.9: */ 3508 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3509 3510 for (j = 1; j <= sc->sc_noport; j++) { 3511 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3512 if (v & XHCI_PS_DR) { 3513 sc->sc_hub_desc.hubd. 3514 DeviceRemovable[j / 8] |= 1U << (j % 8); 3515 } 3516 } 3517 len = sc->sc_hub_desc.hubd.bLength; 3518 break; 3519 3520 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3521 len = 16; 3522 memset(sc->sc_hub_desc.temp, 0, 16); 3523 break; 3524 3525 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3526 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3527 3528 if ((index < 1) || 3529 (index > sc->sc_noport)) { 3530 err = USB_ERR_IOERROR; 3531 goto done; 3532 } 3533 3534 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3535 3536 DPRINTFN(9, "port status=0x%08x\n", v); 3537 3538 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3539 3540 switch (XHCI_PS_SPEED_GET(v)) { 3541 case 3: 3542 i |= UPS_HIGH_SPEED; 3543 break; 3544 case 2: 3545 i |= UPS_LOW_SPEED; 3546 break; 3547 case 1: 3548 /* FULL speed */ 3549 break; 3550 default: 3551 i |= UPS_OTHER_SPEED; 3552 break; 3553 } 3554 3555 if (v & XHCI_PS_CCS) 3556 i |= UPS_CURRENT_CONNECT_STATUS; 3557 if (v & XHCI_PS_PED) 3558 i |= UPS_PORT_ENABLED; 3559 if (v & XHCI_PS_OCA) 3560 i |= UPS_OVERCURRENT_INDICATOR; 3561 if (v & XHCI_PS_PR) 3562 i |= UPS_RESET; 3563 #if 0 3564 if (v & XHCI_PS_PP) 3565 /* XXX undefined */ 3566 #endif 3567 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3568 3569 i = 0; 3570 if (v & XHCI_PS_CSC) 3571 i |= UPS_C_CONNECT_STATUS; 3572 if (v & XHCI_PS_PEC) 3573 i |= UPS_C_PORT_ENABLED; 3574 if (v & XHCI_PS_OCC) 3575 i |= UPS_C_OVERCURRENT_INDICATOR; 3576 if (v & XHCI_PS_WRC) 3577 i |= UPS_C_BH_PORT_RESET; 3578 if (v & XHCI_PS_PRC) 3579 i |= UPS_C_PORT_RESET; 3580 if (v & XHCI_PS_PLC) 3581 i |= UPS_C_PORT_LINK_STATE; 3582 if (v & XHCI_PS_CEC) 3583 i |= UPS_C_PORT_CONFIG_ERROR; 3584 3585 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3586 len = sizeof(sc->sc_hub_desc.ps); 3587 break; 3588 3589 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3590 err = USB_ERR_IOERROR; 3591 goto done; 3592 3593 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3594 break; 3595 3596 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3597 3598 i = index >> 8; 3599 index &= 0x00FF; 3600 3601 if ((index < 1) || 3602 (index > sc->sc_noport)) { 3603 err = USB_ERR_IOERROR; 3604 goto done; 3605 } 3606 3607 port = XHCI_PORTSC(index); 3608 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3609 3610 switch (value) { 3611 case UHF_PORT_U1_TIMEOUT: 3612 if (XHCI_PS_SPEED_GET(v) != 4) { 3613 err = USB_ERR_IOERROR; 3614 goto done; 3615 } 3616 port = XHCI_PORTPMSC(index); 3617 v = XREAD4(sc, oper, port); 3618 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3619 v |= XHCI_PM3_U1TO_SET(i); 3620 XWRITE4(sc, oper, port, v); 3621 break; 3622 case UHF_PORT_U2_TIMEOUT: 3623 if (XHCI_PS_SPEED_GET(v) != 4) { 3624 err = USB_ERR_IOERROR; 3625 goto done; 3626 } 3627 port = XHCI_PORTPMSC(index); 3628 v = XREAD4(sc, oper, port); 3629 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3630 v |= XHCI_PM3_U2TO_SET(i); 3631 XWRITE4(sc, oper, port, v); 3632 break; 3633 case UHF_BH_PORT_RESET: 3634 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3635 break; 3636 case UHF_PORT_LINK_STATE: 3637 XWRITE4(sc, oper, port, v | 3638 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3639 /* 4ms settle time */ 3640 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3641 break; 3642 case UHF_PORT_ENABLE: 3643 DPRINTFN(3, "set port enable %d\n", index); 3644 break; 3645 case UHF_PORT_SUSPEND: 3646 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3647 j = XHCI_PS_SPEED_GET(v); 3648 if ((j < 1) || (j > 3)) { 3649 /* non-supported speed */ 3650 err = USB_ERR_IOERROR; 3651 goto done; 3652 } 3653 XWRITE4(sc, oper, port, v | 3654 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3655 break; 3656 case UHF_PORT_RESET: 3657 DPRINTFN(6, "reset port %d\n", index); 3658 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3659 break; 3660 case UHF_PORT_POWER: 3661 DPRINTFN(3, "set port power %d\n", index); 3662 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3663 break; 3664 case UHF_PORT_TEST: 3665 DPRINTFN(3, "set port test %d\n", index); 3666 break; 3667 case UHF_PORT_INDICATOR: 3668 DPRINTFN(3, "set port indicator %d\n", index); 3669 3670 v &= ~XHCI_PS_PIC_SET(3); 3671 v |= XHCI_PS_PIC_SET(1); 3672 3673 XWRITE4(sc, oper, port, v); 3674 break; 3675 default: 3676 err = USB_ERR_IOERROR; 3677 goto done; 3678 } 3679 break; 3680 3681 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3682 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3683 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3684 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3685 break; 3686 default: 3687 err = USB_ERR_IOERROR; 3688 goto done; 3689 } 3690 done: 3691 *plength = len; 3692 *pptr = ptr; 3693 return (err); 3694 } 3695 3696 static void 3697 xhci_xfer_setup(struct usb_setup_params *parm) 3698 { 3699 struct usb_page_search page_info; 3700 struct usb_page_cache *pc; 3701 struct usb_xfer *xfer; 3702 void *last_obj; 3703 uint32_t ntd; 3704 uint32_t n; 3705 3706 xfer = parm->curr_xfer; 3707 3708 /* 3709 * The proof for the "ntd" formula is illustrated like this: 3710 * 3711 * +------------------------------------+ 3712 * | | 3713 * | |remainder -> | 3714 * | +-----+---+ | 3715 * | | xxx | x | frm 0 | 3716 * | +-----+---++ | 3717 * | | xxx | xx | frm 1 | 3718 * | +-----+----+ | 3719 * | ... | 3720 * +------------------------------------+ 3721 * 3722 * "xxx" means a completely full USB transfer descriptor 3723 * 3724 * "x" and "xx" means a short USB packet 3725 * 3726 * For the remainder of an USB transfer modulo 3727 * "max_data_length" we need two USB transfer descriptors. 3728 * One to transfer the remaining data and one to finalise with 3729 * a zero length packet in case the "force_short_xfer" flag is 3730 * set. We only need two USB transfer descriptors in the case 3731 * where the transfer length of the first one is a factor of 3732 * "max_frame_size". The rest of the needed USB transfer 3733 * descriptors is given by the buffer size divided by the 3734 * maximum data payload. 3735 */ 3736 parm->hc_max_packet_size = 0x400; 3737 parm->hc_max_packet_count = 16 * 3; 3738 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3739 3740 xfer->flags_int.bdma_enable = 1; 3741 3742 usbd_transfer_setup_sub(parm); 3743 3744 if (xfer->flags_int.isochronous_xfr) { 3745 ntd = ((1 * xfer->nframes) 3746 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3747 } else if (xfer->flags_int.control_xfr) { 3748 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3749 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3750 } else { 3751 ntd = ((2 * xfer->nframes) 3752 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3753 } 3754 3755 alloc_dma_set: 3756 3757 if (parm->err) 3758 return; 3759 3760 /* 3761 * Allocate queue heads and transfer descriptors 3762 */ 3763 last_obj = NULL; 3764 3765 if (usbd_transfer_setup_sub_malloc( 3766 parm, &pc, sizeof(struct xhci_td), 3767 XHCI_TD_ALIGN, ntd)) { 3768 parm->err = USB_ERR_NOMEM; 3769 return; 3770 } 3771 if (parm->buf) { 3772 for (n = 0; n != ntd; n++) { 3773 struct xhci_td *td; 3774 3775 usbd_get_page(pc + n, 0, &page_info); 3776 3777 td = page_info.buffer; 3778 3779 /* init TD */ 3780 td->td_self = page_info.physaddr; 3781 td->obj_next = last_obj; 3782 td->page_cache = pc + n; 3783 3784 last_obj = td; 3785 3786 usb_pc_cpu_flush(pc + n); 3787 } 3788 } 3789 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3790 3791 if (!xfer->flags_int.curr_dma_set) { 3792 xfer->flags_int.curr_dma_set = 1; 3793 goto alloc_dma_set; 3794 } 3795 } 3796 3797 static uint8_t 3798 xhci_get_endpoint_state(struct usb_device *udev, uint8_t epno) 3799 { 3800 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3801 struct usb_page_search buf_dev; 3802 struct xhci_hw_dev *hdev; 3803 struct xhci_dev_ctx *pdev; 3804 uint32_t temp; 3805 3806 MPASS(epno != 0); 3807 3808 hdev = &sc->sc_hw.devs[udev->controller_slot_id]; 3809 3810 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 3811 pdev = buf_dev.buffer; 3812 usb_pc_cpu_invalidate(&hdev->device_pc); 3813 3814 temp = xhci_ctx_get_le32(sc, &pdev->ctx_ep[epno - 1].dwEpCtx0); 3815 3816 return (XHCI_EPCTX_0_EPSTATE_GET(temp)); 3817 } 3818 3819 static usb_error_t 3820 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3821 { 3822 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3823 struct usb_page_search buf_inp; 3824 struct usb_device *udev; 3825 struct xhci_endpoint_ext *pepext; 3826 struct usb_endpoint_descriptor *edesc; 3827 struct usb_page_cache *pcinp; 3828 usb_error_t err; 3829 usb_stream_t stream_id; 3830 uint32_t mask; 3831 uint8_t index; 3832 uint8_t epno; 3833 3834 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3835 xfer->endpoint->edesc); 3836 3837 udev = xfer->xroot->udev; 3838 index = udev->controller_slot_id; 3839 3840 pcinp = &sc->sc_hw.devs[index].input_pc; 3841 3842 usbd_get_page(pcinp, 0, &buf_inp); 3843 3844 edesc = xfer->endpoint->edesc; 3845 3846 epno = edesc->bEndpointAddress; 3847 stream_id = xfer->stream_id; 3848 3849 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3850 epno |= UE_DIR_IN; 3851 3852 epno = XHCI_EPNO2EPID(epno); 3853 3854 if (epno == 0) 3855 return (USB_ERR_NO_PIPE); /* invalid */ 3856 3857 XHCI_CMD_LOCK(sc); 3858 3859 /* configure endpoint */ 3860 3861 err = xhci_configure_endpoint_by_xfer(xfer); 3862 3863 if (err != 0) { 3864 XHCI_CMD_UNLOCK(sc); 3865 return (err); 3866 } 3867 3868 /* 3869 * Get the endpoint into the stopped state according to the 3870 * endpoint context state diagram in the XHCI specification: 3871 */ 3872 switch (xhci_get_endpoint_state(udev, epno)) { 3873 case XHCI_EPCTX_0_EPSTATE_DISABLED: 3874 break; 3875 case XHCI_EPCTX_0_EPSTATE_STOPPED: 3876 break; 3877 case XHCI_EPCTX_0_EPSTATE_HALTED: 3878 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3879 if (err != 0) 3880 DPRINTF("Could not reset endpoint %u\n", epno); 3881 break; 3882 default: 3883 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3884 if (err != 0) 3885 DPRINTF("Could not stop endpoint %u\n", epno); 3886 break; 3887 } 3888 3889 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3890 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3891 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3892 stream_id, epno, index); 3893 3894 if (err != 0) 3895 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3896 3897 /* 3898 * Get the endpoint into the running state according to the 3899 * endpoint context state diagram in the XHCI specification: 3900 */ 3901 3902 mask = (1U << epno); 3903 xhci_configure_mask(udev, mask | 1U, 0); 3904 3905 if (!(sc->sc_hw.devs[index].ep_configured & mask)) { 3906 sc->sc_hw.devs[index].ep_configured |= mask; 3907 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3908 } else { 3909 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3910 } 3911 3912 if (err != 0) { 3913 DPRINTF("Could not configure " 3914 "endpoint %u at slot %u.\n", epno, index); 3915 } 3916 XHCI_CMD_UNLOCK(sc); 3917 3918 return (0); 3919 } 3920 3921 static void 3922 xhci_xfer_unsetup(struct usb_xfer *xfer) 3923 { 3924 return; 3925 } 3926 3927 static void 3928 xhci_start_dma_delay(struct usb_xfer *xfer) 3929 { 3930 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3931 3932 /* put transfer on interrupt queue (again) */ 3933 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3934 3935 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3936 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3937 } 3938 3939 static void 3940 xhci_configure_msg(struct usb_proc_msg *pm) 3941 { 3942 struct xhci_softc *sc; 3943 struct xhci_endpoint_ext *pepext; 3944 struct usb_xfer *xfer; 3945 3946 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3947 3948 restart: 3949 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3950 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3951 xfer->endpoint->edesc); 3952 3953 if ((pepext->trb_halted != 0) || 3954 (pepext->trb_running == 0)) { 3955 uint16_t i; 3956 3957 /* clear halted and running */ 3958 pepext->trb_halted = 0; 3959 pepext->trb_running = 0; 3960 3961 /* nuke remaining buffered transfers */ 3962 3963 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3964 XHCI_MAX_STREAMS); i++) { 3965 /* 3966 * NOTE: We need to use the timeout 3967 * error code here else existing 3968 * isochronous clients can get 3969 * confused: 3970 */ 3971 if (pepext->xfer[i] != NULL) { 3972 xhci_device_done(pepext->xfer[i], 3973 USB_ERR_TIMEOUT); 3974 } 3975 } 3976 3977 /* 3978 * NOTE: The USB transfer cannot vanish in 3979 * this state! 3980 */ 3981 3982 USB_BUS_UNLOCK(&sc->sc_bus); 3983 3984 xhci_configure_reset_endpoint(xfer); 3985 3986 USB_BUS_LOCK(&sc->sc_bus); 3987 3988 /* check if halted is still cleared */ 3989 if (pepext->trb_halted == 0) { 3990 pepext->trb_running = 1; 3991 memset(pepext->trb_index, 0, 3992 sizeof(pepext->trb_index)); 3993 } 3994 goto restart; 3995 } 3996 3997 if (xfer->flags_int.did_dma_delay) { 3998 /* remove transfer from interrupt queue (again) */ 3999 usbd_transfer_dequeue(xfer); 4000 4001 /* we are finally done */ 4002 usb_dma_delay_done_cb(xfer); 4003 4004 /* queue changed - restart */ 4005 goto restart; 4006 } 4007 } 4008 4009 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4010 /* try to insert xfer on HW queue */ 4011 xhci_transfer_insert(xfer); 4012 4013 /* try to multi buffer */ 4014 xhci_device_generic_multi_enter(xfer->endpoint, 4015 xfer->stream_id, NULL); 4016 } 4017 } 4018 4019 static void 4020 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4021 struct usb_endpoint *ep) 4022 { 4023 struct xhci_endpoint_ext *pepext; 4024 struct xhci_softc *sc; 4025 uint8_t index; 4026 uint8_t epno; 4027 4028 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 4029 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 4030 4031 if (udev->parent_hub == NULL) { 4032 /* root HUB has special endpoint handling */ 4033 return; 4034 } 4035 4036 ep->methods = &xhci_device_generic_methods; 4037 4038 pepext = xhci_get_endpoint_ext(udev, edesc); 4039 4040 USB_BUS_LOCK(udev->bus); 4041 pepext->trb_halted = 1; 4042 pepext->trb_running = 0; 4043 4044 /* 4045 * When doing an alternate setting, except for control 4046 * endpoints, we need to re-configure the XHCI endpoint 4047 * context: 4048 */ 4049 if ((edesc->bEndpointAddress & UE_ADDR) != 0) { 4050 sc = XHCI_BUS2SC(udev->bus); 4051 index = udev->controller_slot_id; 4052 epno = XHCI_EPNO2EPID(edesc->bEndpointAddress); 4053 sc->sc_hw.devs[index].ep_configured &= ~(1U << epno); 4054 } 4055 USB_BUS_UNLOCK(udev->bus); 4056 } 4057 4058 static void 4059 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 4060 { 4061 4062 } 4063 4064 static void 4065 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 4066 { 4067 struct xhci_endpoint_ext *pepext; 4068 4069 DPRINTF("\n"); 4070 4071 if (udev->flags.usb_mode != USB_MODE_HOST) { 4072 /* not supported */ 4073 return; 4074 } 4075 if (udev->parent_hub == NULL) { 4076 /* root HUB has special endpoint handling */ 4077 return; 4078 } 4079 4080 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 4081 4082 USB_BUS_LOCK(udev->bus); 4083 pepext->trb_halted = 1; 4084 pepext->trb_running = 0; 4085 USB_BUS_UNLOCK(udev->bus); 4086 } 4087 4088 static usb_error_t 4089 xhci_device_init(struct usb_device *udev) 4090 { 4091 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4092 usb_error_t err; 4093 uint8_t temp; 4094 4095 /* no init for root HUB */ 4096 if (udev->parent_hub == NULL) 4097 return (0); 4098 4099 XHCI_CMD_LOCK(sc); 4100 4101 /* set invalid default */ 4102 4103 udev->controller_slot_id = sc->sc_noslot + 1; 4104 4105 /* try to get a new slot ID from the XHCI */ 4106 4107 err = xhci_cmd_enable_slot(sc, &temp); 4108 4109 if (err) { 4110 XHCI_CMD_UNLOCK(sc); 4111 return (err); 4112 } 4113 4114 if (temp > sc->sc_noslot) { 4115 XHCI_CMD_UNLOCK(sc); 4116 return (USB_ERR_BAD_ADDRESS); 4117 } 4118 4119 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4120 DPRINTF("slot %u already allocated.\n", temp); 4121 XHCI_CMD_UNLOCK(sc); 4122 return (USB_ERR_BAD_ADDRESS); 4123 } 4124 4125 /* store slot ID for later reference */ 4126 4127 udev->controller_slot_id = temp; 4128 4129 /* reset data structure */ 4130 4131 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4132 4133 /* set mark slot allocated */ 4134 4135 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4136 4137 err = xhci_alloc_device_ext(udev); 4138 4139 XHCI_CMD_UNLOCK(sc); 4140 4141 /* get device into default state */ 4142 4143 if (err == 0) 4144 err = xhci_set_address(udev, NULL, 0); 4145 4146 return (err); 4147 } 4148 4149 static void 4150 xhci_device_uninit(struct usb_device *udev) 4151 { 4152 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4153 uint8_t index; 4154 4155 /* no init for root HUB */ 4156 if (udev->parent_hub == NULL) 4157 return; 4158 4159 XHCI_CMD_LOCK(sc); 4160 4161 index = udev->controller_slot_id; 4162 4163 if (index <= sc->sc_noslot) { 4164 xhci_cmd_disable_slot(sc, index); 4165 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4166 4167 /* free device extension */ 4168 xhci_free_device_ext(udev); 4169 } 4170 4171 XHCI_CMD_UNLOCK(sc); 4172 } 4173 4174 static void 4175 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4176 { 4177 /* 4178 * Wait until the hardware has finished any possible use of 4179 * the transfer descriptor(s) 4180 */ 4181 *pus = 2048; /* microseconds */ 4182 } 4183 4184 static void 4185 xhci_device_resume(struct usb_device *udev) 4186 { 4187 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4188 uint8_t index; 4189 uint8_t n; 4190 uint8_t p; 4191 4192 DPRINTF("\n"); 4193 4194 /* check for root HUB */ 4195 if (udev->parent_hub == NULL) 4196 return; 4197 4198 index = udev->controller_slot_id; 4199 4200 XHCI_CMD_LOCK(sc); 4201 4202 /* blindly resume all endpoints */ 4203 4204 USB_BUS_LOCK(udev->bus); 4205 4206 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4207 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4208 XWRITE4(sc, door, XHCI_DOORBELL(index), 4209 n | XHCI_DB_SID_SET(p)); 4210 } 4211 } 4212 4213 USB_BUS_UNLOCK(udev->bus); 4214 4215 XHCI_CMD_UNLOCK(sc); 4216 } 4217 4218 static void 4219 xhci_device_suspend(struct usb_device *udev) 4220 { 4221 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4222 uint8_t index; 4223 uint8_t n; 4224 usb_error_t err; 4225 4226 DPRINTF("\n"); 4227 4228 /* check for root HUB */ 4229 if (udev->parent_hub == NULL) 4230 return; 4231 4232 index = udev->controller_slot_id; 4233 4234 XHCI_CMD_LOCK(sc); 4235 4236 /* blindly suspend all endpoints */ 4237 4238 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4239 err = xhci_cmd_stop_ep(sc, 1, n, index); 4240 if (err != 0) { 4241 DPRINTF("Failed to suspend endpoint " 4242 "%u on slot %u (ignored).\n", n, index); 4243 } 4244 } 4245 4246 XHCI_CMD_UNLOCK(sc); 4247 } 4248 4249 static void 4250 xhci_set_hw_power(struct usb_bus *bus) 4251 { 4252 DPRINTF("\n"); 4253 } 4254 4255 static void 4256 xhci_device_state_change(struct usb_device *udev) 4257 { 4258 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4259 struct usb_page_search buf_inp; 4260 usb_error_t err; 4261 uint8_t index; 4262 4263 /* check for root HUB */ 4264 if (udev->parent_hub == NULL) 4265 return; 4266 4267 index = udev->controller_slot_id; 4268 4269 DPRINTF("\n"); 4270 4271 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4272 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4273 &sc->sc_hw.devs[index].tt); 4274 if (err != 0) 4275 sc->sc_hw.devs[index].nports = 0; 4276 } 4277 4278 XHCI_CMD_LOCK(sc); 4279 4280 switch (usb_get_device_state(udev)) { 4281 case USB_STATE_POWERED: 4282 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4283 break; 4284 4285 /* set default state */ 4286 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4287 sc->sc_hw.devs[index].ep_configured = 3U; 4288 4289 /* reset number of contexts */ 4290 sc->sc_hw.devs[index].context_num = 0; 4291 4292 err = xhci_cmd_reset_dev(sc, index); 4293 4294 if (err != 0) { 4295 DPRINTF("Device reset failed " 4296 "for slot %u.\n", index); 4297 } 4298 break; 4299 4300 case USB_STATE_ADDRESSED: 4301 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4302 break; 4303 4304 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4305 sc->sc_hw.devs[index].ep_configured = 3U; 4306 4307 /* set configure mask to slot only */ 4308 xhci_configure_mask(udev, 1, 0); 4309 4310 /* deconfigure all endpoints, except EP0 */ 4311 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4312 4313 if (err) { 4314 DPRINTF("Failed to deconfigure " 4315 "slot %u.\n", index); 4316 } 4317 break; 4318 4319 case USB_STATE_CONFIGURED: 4320 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) { 4321 /* deconfigure all endpoints, except EP0 */ 4322 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4323 4324 if (err) { 4325 DPRINTF("Failed to deconfigure " 4326 "slot %u.\n", index); 4327 } 4328 } 4329 4330 /* set configured state */ 4331 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4332 sc->sc_hw.devs[index].ep_configured = 3U; 4333 4334 /* reset number of contexts */ 4335 sc->sc_hw.devs[index].context_num = 0; 4336 4337 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4338 4339 xhci_configure_mask(udev, 3, 0); 4340 4341 err = xhci_configure_device(udev); 4342 if (err != 0) { 4343 DPRINTF("Could not configure device " 4344 "at slot %u.\n", index); 4345 } 4346 4347 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4348 if (err != 0) { 4349 DPRINTF("Could not evaluate device " 4350 "context at slot %u.\n", index); 4351 } 4352 break; 4353 4354 default: 4355 break; 4356 } 4357 XHCI_CMD_UNLOCK(sc); 4358 } 4359 4360 static usb_error_t 4361 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4362 uint8_t ep_mode) 4363 { 4364 switch (ep_mode) { 4365 case USB_EP_MODE_DEFAULT: 4366 return (0); 4367 case USB_EP_MODE_STREAMS: 4368 if (xhcistreams == 0 || 4369 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4370 udev->speed != USB_SPEED_SUPER) 4371 return (USB_ERR_INVAL); 4372 return (0); 4373 default: 4374 return (USB_ERR_INVAL); 4375 } 4376 } 4377 4378 static const struct usb_bus_methods xhci_bus_methods = { 4379 .endpoint_init = xhci_ep_init, 4380 .endpoint_uninit = xhci_ep_uninit, 4381 .xfer_setup = xhci_xfer_setup, 4382 .xfer_unsetup = xhci_xfer_unsetup, 4383 .get_dma_delay = xhci_get_dma_delay, 4384 .device_init = xhci_device_init, 4385 .device_uninit = xhci_device_uninit, 4386 .device_resume = xhci_device_resume, 4387 .device_suspend = xhci_device_suspend, 4388 .set_hw_power = xhci_set_hw_power, 4389 .roothub_exec = xhci_roothub_exec, 4390 .xfer_poll = xhci_do_poll, 4391 .start_dma_delay = xhci_start_dma_delay, 4392 .set_address = xhci_set_address, 4393 .clear_stall = xhci_ep_clear_stall, 4394 .device_state_change = xhci_device_state_change, 4395 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4396 .set_endpoint_mode = xhci_set_endpoint_mode, 4397 }; 4398