1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 31 * 32 * The XHCI 1.0 spec can be found at 33 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 34 * and the USB 3.0 spec at 35 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 36 */ 37 38 /* 39 * A few words about the design implementation: This driver emulates 40 * the concept about TDs which is found in EHCI specification. This 41 * way we achieve that the USB controller drivers look similar to 42 * eachother which makes it easier to understand the code. 43 */ 44 45 #ifdef USB_GLOBAL_INCLUDE_FILE 46 #include USB_GLOBAL_INCLUDE_FILE 47 #else 48 #include <sys/stdint.h> 49 #include <sys/stddef.h> 50 #include <sys/param.h> 51 #include <sys/queue.h> 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/bus.h> 56 #include <sys/module.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/condvar.h> 60 #include <sys/sysctl.h> 61 #include <sys/sx.h> 62 #include <sys/unistd.h> 63 #include <sys/callout.h> 64 #include <sys/malloc.h> 65 #include <sys/priv.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 70 #define USB_DEBUG_VAR xhcidebug 71 72 #include <dev/usb/usb_core.h> 73 #include <dev/usb/usb_debug.h> 74 #include <dev/usb/usb_busdma.h> 75 #include <dev/usb/usb_process.h> 76 #include <dev/usb/usb_transfer.h> 77 #include <dev/usb/usb_device.h> 78 #include <dev/usb/usb_hub.h> 79 #include <dev/usb/usb_util.h> 80 81 #include <dev/usb/usb_controller.h> 82 #include <dev/usb/usb_bus.h> 83 #endif /* USB_GLOBAL_INCLUDE_FILE */ 84 85 #include <dev/usb/controller/xhci.h> 86 #include <dev/usb/controller/xhcireg.h> 87 88 #define XHCI_BUS2SC(bus) \ 89 __containerof(bus, struct xhci_softc, sc_bus) 90 91 #define XHCI_GET_CTX(sc, which, field, ptr) \ 92 ((sc)->sc_ctx_is_64_byte ? \ 93 &((struct which##64 *)(ptr))->field.ctx : \ 94 &((struct which *)(ptr))->field) 95 96 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 97 "USB XHCI"); 98 99 static int xhcistreams; 100 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN, 101 &xhcistreams, 0, "Set to enable streams mode support"); 102 103 static int xhcictlquirk = 1; 104 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlquirk, CTLFLAG_RWTUN, 105 &xhcictlquirk, 0, "Set to enable control endpoint quirk"); 106 107 #ifdef USB_DEBUG 108 static int xhcidebug; 109 static int xhciroute; 110 static int xhcipolling; 111 static int xhcidma32; 112 static int xhcictlstep; 113 114 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN, 115 &xhcidebug, 0, "Debug level"); 116 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN, 117 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller"); 118 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN, 119 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller"); 120 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN, 121 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller"); 122 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN, 123 &xhcictlstep, 0, "Set to enable control endpoint status stage stepping"); 124 #else 125 #define xhciroute 0 126 #define xhcidma32 0 127 #define xhcictlstep 0 128 #endif 129 130 #define XHCI_INTR_ENDPT 1 131 132 struct xhci_std_temp { 133 struct xhci_softc *sc; 134 struct usb_page_cache *pc; 135 struct xhci_td *td; 136 struct xhci_td *td_next; 137 uint32_t len; 138 uint32_t offset; 139 uint32_t max_packet_size; 140 uint32_t average; 141 uint32_t isoc_frame; 142 uint16_t isoc_delta; 143 uint8_t shortpkt; 144 uint8_t multishort; 145 uint8_t last_frame; 146 uint8_t trb_type; 147 uint8_t direction; 148 uint8_t tbc; 149 uint8_t tlbpc; 150 uint8_t step_td; 151 uint8_t do_isoc_sync; 152 }; 153 154 static void xhci_do_poll(struct usb_bus *); 155 static void xhci_device_done(struct usb_xfer *, usb_error_t); 156 static void xhci_root_intr(struct xhci_softc *); 157 static void xhci_free_device_ext(struct usb_device *); 158 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 159 struct usb_endpoint_descriptor *); 160 static usb_proc_callback_t xhci_configure_msg; 161 static usb_error_t xhci_configure_device(struct usb_device *); 162 static usb_error_t xhci_configure_endpoint(struct usb_device *, 163 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 164 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 165 uint8_t); 166 static usb_error_t xhci_configure_mask(struct usb_device *, 167 uint32_t, uint8_t); 168 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 169 uint64_t, uint8_t); 170 static void xhci_endpoint_doorbell(struct usb_xfer *); 171 172 static const struct usb_bus_methods xhci_bus_methods; 173 174 #ifdef USB_DEBUG 175 static void 176 xhci_dump_trb(struct xhci_trb *trb) 177 { 178 DPRINTFN(5, "trb = %p\n", trb); 179 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 180 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 181 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 182 } 183 184 static void 185 xhci_dump_endpoint(struct xhci_endp_ctx *pep) 186 { 187 DPRINTFN(5, "pep = %p\n", pep); 188 DPRINTFN(5, "dwEpCtx0=0x%08x\n", le32toh(pep->dwEpCtx0)); 189 DPRINTFN(5, "dwEpCtx1=0x%08x\n", le32toh(pep->dwEpCtx1)); 190 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)le64toh(pep->qwEpCtx2)); 191 DPRINTFN(5, "dwEpCtx4=0x%08x\n", le32toh(pep->dwEpCtx4)); 192 DPRINTFN(5, "dwEpCtx5=0x%08x\n", le32toh(pep->dwEpCtx5)); 193 DPRINTFN(5, "dwEpCtx6=0x%08x\n", le32toh(pep->dwEpCtx6)); 194 DPRINTFN(5, "dwEpCtx7=0x%08x\n", le32toh(pep->dwEpCtx7)); 195 } 196 197 static void 198 xhci_dump_device(struct xhci_slot_ctx *psl) 199 { 200 DPRINTFN(5, "psl = %p\n", psl); 201 DPRINTFN(5, "dwSctx0=0x%08x\n", le32toh(psl->dwSctx0)); 202 DPRINTFN(5, "dwSctx1=0x%08x\n", le32toh(psl->dwSctx1)); 203 DPRINTFN(5, "dwSctx2=0x%08x\n", le32toh(psl->dwSctx2)); 204 DPRINTFN(5, "dwSctx3=0x%08x\n", le32toh(psl->dwSctx3)); 205 } 206 #endif 207 208 uint8_t 209 xhci_use_polling(void) 210 { 211 #ifdef USB_DEBUG 212 return (xhcipolling != 0); 213 #else 214 return (0); 215 #endif 216 } 217 218 static void 219 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 220 { 221 struct xhci_softc *sc = XHCI_BUS2SC(bus); 222 uint16_t i; 223 224 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 225 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 226 227 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 228 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 229 230 for (i = 0; i != sc->sc_noscratch; i++) { 231 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 232 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 233 } 234 } 235 236 static int 237 xhci_reset_command_queue_locked(struct xhci_softc *sc) 238 { 239 struct usb_page_search buf_res; 240 struct xhci_hw_root *phwr; 241 uint64_t addr; 242 uint32_t temp; 243 244 DPRINTF("\n"); 245 246 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 247 if (temp & XHCI_CRCR_LO_CRR) { 248 DPRINTF("Command ring running\n"); 249 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 250 251 /* 252 * Try to abort the last command as per section 253 * 4.6.1.2 "Aborting a Command" of the XHCI 254 * specification: 255 */ 256 257 /* stop and cancel */ 258 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 259 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 260 261 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 262 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 263 264 /* wait 250ms */ 265 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 266 267 /* check if command ring is still running */ 268 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 269 if (temp & XHCI_CRCR_LO_CRR) { 270 DPRINTF("Comand ring still running\n"); 271 return (USB_ERR_IOERROR); 272 } 273 } 274 275 /* reset command ring */ 276 sc->sc_command_ccs = 1; 277 sc->sc_command_idx = 0; 278 279 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 280 281 /* set up command ring control base address */ 282 addr = buf_res.physaddr; 283 phwr = buf_res.buffer; 284 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 285 286 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 287 288 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 289 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 290 291 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 292 293 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 294 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 295 296 return (0); 297 } 298 299 usb_error_t 300 xhci_start_controller(struct xhci_softc *sc) 301 { 302 struct usb_page_search buf_res; 303 struct xhci_hw_root *phwr; 304 struct xhci_dev_ctx_addr *pdctxa; 305 usb_error_t err; 306 uint64_t addr; 307 uint32_t temp; 308 uint16_t i; 309 310 DPRINTF("\n"); 311 312 sc->sc_event_ccs = 1; 313 sc->sc_event_idx = 0; 314 sc->sc_command_ccs = 1; 315 sc->sc_command_idx = 0; 316 317 err = xhci_reset_controller(sc); 318 if (err) 319 return (err); 320 321 /* set up number of device slots */ 322 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 323 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 324 325 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 326 327 temp = XREAD4(sc, oper, XHCI_USBSTS); 328 329 /* clear interrupts */ 330 XWRITE4(sc, oper, XHCI_USBSTS, temp); 331 /* disable all device notifications */ 332 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 333 334 /* set up device context base address */ 335 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 336 pdctxa = buf_res.buffer; 337 memset(pdctxa, 0, sizeof(*pdctxa)); 338 339 addr = buf_res.physaddr; 340 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 341 342 /* slot 0 points to the table of scratchpad pointers */ 343 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 344 345 for (i = 0; i != sc->sc_noscratch; i++) { 346 struct usb_page_search buf_scp; 347 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 348 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 349 } 350 351 addr = buf_res.physaddr; 352 353 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 354 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 355 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 356 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 357 358 /* set up event table size */ 359 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 360 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max); 361 362 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max)); 363 364 /* set up interrupt rate */ 365 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 366 367 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 368 369 phwr = buf_res.buffer; 370 addr = buf_res.physaddr; 371 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 372 373 /* reset hardware root structure */ 374 memset(phwr, 0, sizeof(*phwr)); 375 376 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 377 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 378 379 /* 380 * PR 237666: 381 * 382 * According to the XHCI specification, the XWRITE4's to 383 * XHCI_ERSTBA_LO and _HI lead to the XHCI to copy the 384 * qwEvrsTablePtr and dwEvrsTableSize values above at that 385 * time, as the XHCI initializes its event ring support. This 386 * is before the event ring starts to pay attention to the 387 * RUN/STOP bit. Thus, make sure the values are observable to 388 * the XHCI before that point. 389 */ 390 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 391 392 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 393 394 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 395 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 396 397 addr = buf_res.physaddr; 398 399 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 400 401 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 402 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 403 404 /* set up interrupter registers */ 405 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 406 temp |= XHCI_IMAN_INTR_ENA; 407 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 408 409 /* set up command ring control base address */ 410 addr = buf_res.physaddr; 411 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 412 413 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 414 415 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 416 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 417 418 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 419 420 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 421 422 /* Go! */ 423 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 424 XHCI_CMD_INTE | XHCI_CMD_HSEE); 425 426 for (i = 0; i != 100; i++) { 427 usb_pause_mtx(NULL, hz / 100); 428 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 429 if (!temp) 430 break; 431 } 432 if (temp) { 433 XWRITE4(sc, oper, XHCI_USBCMD, 0); 434 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 435 return (USB_ERR_IOERROR); 436 } 437 438 /* catch any lost interrupts */ 439 xhci_do_poll(&sc->sc_bus); 440 441 if (sc->sc_port_route != NULL) { 442 /* Route all ports to the XHCI by default */ 443 sc->sc_port_route(sc->sc_bus.parent, 444 ~xhciroute, xhciroute); 445 } 446 return (0); 447 } 448 449 usb_error_t 450 xhci_halt_controller(struct xhci_softc *sc) 451 { 452 uint32_t temp; 453 uint16_t i; 454 455 DPRINTF("\n"); 456 457 sc->sc_capa_off = 0; 458 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 459 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 460 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 461 462 /* Halt controller */ 463 XWRITE4(sc, oper, XHCI_USBCMD, 0); 464 465 for (i = 0; i != 100; i++) { 466 usb_pause_mtx(NULL, hz / 100); 467 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 468 if (temp) 469 break; 470 } 471 472 if (!temp) { 473 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 474 return (USB_ERR_IOERROR); 475 } 476 return (0); 477 } 478 479 usb_error_t 480 xhci_reset_controller(struct xhci_softc *sc) 481 { 482 uint32_t temp = 0; 483 uint16_t i; 484 485 DPRINTF("\n"); 486 487 /* Reset controller */ 488 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 489 490 for (i = 0; i != 100; i++) { 491 usb_pause_mtx(NULL, hz / 100); 492 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 493 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 494 if (!temp) 495 break; 496 } 497 498 if (temp) { 499 device_printf(sc->sc_bus.parent, "Controller " 500 "reset timeout.\n"); 501 return (USB_ERR_IOERROR); 502 } 503 return (0); 504 } 505 506 usb_error_t 507 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32) 508 { 509 uint32_t temp; 510 511 DPRINTF("\n"); 512 513 /* initialize some bus fields */ 514 sc->sc_bus.parent = self; 515 516 /* set the bus revision */ 517 sc->sc_bus.usbrev = USB_REV_3_0; 518 519 /* set up the bus struct */ 520 sc->sc_bus.methods = &xhci_bus_methods; 521 522 /* set up devices array */ 523 sc->sc_bus.devices = sc->sc_devices; 524 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 525 526 /* set default cycle state in case of early interrupts */ 527 sc->sc_event_ccs = 1; 528 sc->sc_command_ccs = 1; 529 530 /* set up bus space offsets */ 531 sc->sc_capa_off = 0; 532 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 533 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 534 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 535 536 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 537 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 538 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 539 540 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 541 542 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 543 device_printf(sc->sc_bus.parent, "Controller does " 544 "not support 4K page size.\n"); 545 return (ENXIO); 546 } 547 548 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 549 550 DPRINTF("HCS0 = 0x%08x\n", temp); 551 552 /* set up context size */ 553 if (XHCI_HCS0_CSZ(temp)) { 554 sc->sc_ctx_is_64_byte = 1; 555 } else { 556 sc->sc_ctx_is_64_byte = 0; 557 } 558 559 /* get DMA bits */ 560 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && 561 xhcidma32 == 0 && dma32 == 0) ? 64 : 32; 562 563 device_printf(self, "%d bytes context size, %d-bit DMA\n", 564 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); 565 566 /* enable 64Kbyte control endpoint quirk */ 567 sc->sc_bus.control_ep_quirk = (xhcictlquirk ? 1 : 0); 568 569 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 570 571 /* get number of device slots */ 572 sc->sc_noport = XHCI_HCS1_N_PORTS(temp); 573 574 if (sc->sc_noport == 0) { 575 device_printf(sc->sc_bus.parent, "Invalid number " 576 "of ports: %u\n", sc->sc_noport); 577 return (ENXIO); 578 } 579 580 sc->sc_noport = sc->sc_noport; 581 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 582 583 DPRINTF("Max slots: %u\n", sc->sc_noslot); 584 585 if (sc->sc_noslot > XHCI_MAX_DEVICES) 586 sc->sc_noslot = XHCI_MAX_DEVICES; 587 588 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 589 590 DPRINTF("HCS2=0x%08x\n", temp); 591 592 /* get isochronous scheduling threshold */ 593 sc->sc_ist = XHCI_HCS2_IST(temp); 594 595 /* get number of scratchpads */ 596 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 597 598 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 599 device_printf(sc->sc_bus.parent, "XHCI request " 600 "too many scratchpads\n"); 601 return (ENOMEM); 602 } 603 604 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 605 606 /* get event table size */ 607 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); 608 if (sc->sc_erst_max > XHCI_MAX_RSEG) 609 sc->sc_erst_max = XHCI_MAX_RSEG; 610 611 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 612 613 /* get maximum exit latency */ 614 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 615 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 616 617 /* Check if we should use the default IMOD value. */ 618 if (sc->sc_imod_default == 0) 619 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 620 621 /* get all DMA memory */ 622 if (usb_bus_mem_alloc_all(&sc->sc_bus, 623 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 624 return (ENOMEM); 625 } 626 627 /* set up command queue mutex and condition varible */ 628 cv_init(&sc->sc_cmd_cv, "CMDQ"); 629 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 630 631 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 632 sc->sc_config_msg[0].bus = &sc->sc_bus; 633 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 634 sc->sc_config_msg[1].bus = &sc->sc_bus; 635 636 return (0); 637 } 638 639 void 640 xhci_uninit(struct xhci_softc *sc) 641 { 642 /* 643 * NOTE: At this point the control transfer process is gone 644 * and "xhci_configure_msg" is no longer called. Consequently 645 * waiting for the configuration messages to complete is not 646 * needed. 647 */ 648 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 649 650 cv_destroy(&sc->sc_cmd_cv); 651 sx_destroy(&sc->sc_cmd_sx); 652 } 653 654 static void 655 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 656 { 657 struct xhci_softc *sc = XHCI_BUS2SC(bus); 658 659 switch (state) { 660 case USB_HW_POWER_SUSPEND: 661 DPRINTF("Stopping the XHCI\n"); 662 xhci_halt_controller(sc); 663 xhci_reset_controller(sc); 664 break; 665 case USB_HW_POWER_SHUTDOWN: 666 DPRINTF("Stopping the XHCI\n"); 667 xhci_halt_controller(sc); 668 xhci_reset_controller(sc); 669 break; 670 case USB_HW_POWER_RESUME: 671 DPRINTF("Starting the XHCI\n"); 672 xhci_start_controller(sc); 673 break; 674 default: 675 break; 676 } 677 } 678 679 static usb_error_t 680 xhci_generic_done_sub(struct usb_xfer *xfer) 681 { 682 struct xhci_td *td; 683 struct xhci_td *td_alt_next; 684 uint32_t len; 685 uint8_t status; 686 687 td = xfer->td_transfer_cache; 688 td_alt_next = td->alt_next; 689 690 if (xfer->aframes != xfer->nframes) 691 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 692 693 while (1) { 694 usb_pc_cpu_invalidate(td->page_cache); 695 696 status = td->status; 697 len = td->remainder; 698 699 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 700 xfer, (unsigned int)xfer->aframes, 701 (unsigned int)xfer->nframes, 702 (unsigned int)len, (unsigned int)td->len, 703 (unsigned int)status); 704 705 /* 706 * Verify the status length and 707 * add the length to "frlengths[]": 708 */ 709 if (len > td->len) { 710 /* should not happen */ 711 DPRINTF("Invalid status length, " 712 "0x%04x/0x%04x bytes\n", len, td->len); 713 status = XHCI_TRB_ERROR_LENGTH; 714 } else if (xfer->aframes != xfer->nframes) { 715 xfer->frlengths[xfer->aframes] += td->len - len; 716 } 717 /* Check for last transfer */ 718 if (((void *)td) == xfer->td_transfer_last) { 719 td = NULL; 720 break; 721 } 722 /* Check for transfer error */ 723 if (status != XHCI_TRB_ERROR_SHORT_PKT && 724 status != XHCI_TRB_ERROR_SUCCESS) { 725 /* the transfer is finished */ 726 td = NULL; 727 break; 728 } 729 /* Check for short transfer */ 730 if (len > 0) { 731 if (xfer->flags_int.short_frames_ok || 732 xfer->flags_int.isochronous_xfr || 733 xfer->flags_int.control_xfr) { 734 /* follow alt next */ 735 td = td->alt_next; 736 } else { 737 /* the transfer is finished */ 738 td = NULL; 739 } 740 break; 741 } 742 td = td->obj_next; 743 744 if (td->alt_next != td_alt_next) { 745 /* this USB frame is complete */ 746 break; 747 } 748 } 749 750 /* update transfer cache */ 751 752 xfer->td_transfer_cache = td; 753 754 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 755 (status != XHCI_TRB_ERROR_SHORT_PKT && 756 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 757 USB_ERR_NORMAL_COMPLETION); 758 } 759 760 static void 761 xhci_generic_done(struct usb_xfer *xfer) 762 { 763 usb_error_t err = 0; 764 765 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 766 xfer, xfer->endpoint); 767 768 /* reset scanner */ 769 770 xfer->td_transfer_cache = xfer->td_transfer_first; 771 772 if (xfer->flags_int.control_xfr) { 773 if (xfer->flags_int.control_hdr) 774 err = xhci_generic_done_sub(xfer); 775 776 xfer->aframes = 1; 777 778 if (xfer->td_transfer_cache == NULL) 779 goto done; 780 } 781 782 while (xfer->aframes != xfer->nframes) { 783 err = xhci_generic_done_sub(xfer); 784 xfer->aframes++; 785 786 if (xfer->td_transfer_cache == NULL) 787 goto done; 788 } 789 790 if (xfer->flags_int.control_xfr && 791 !xfer->flags_int.control_act) 792 err = xhci_generic_done_sub(xfer); 793 done: 794 /* transfer is complete */ 795 xhci_device_done(xfer, err); 796 } 797 798 static void 799 xhci_activate_transfer(struct usb_xfer *xfer) 800 { 801 struct xhci_td *td; 802 803 td = xfer->td_transfer_cache; 804 805 usb_pc_cpu_invalidate(td->page_cache); 806 807 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 808 /* activate the transfer */ 809 810 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 811 usb_pc_cpu_flush(td->page_cache); 812 813 xhci_endpoint_doorbell(xfer); 814 } 815 } 816 817 static void 818 xhci_skip_transfer(struct usb_xfer *xfer) 819 { 820 struct xhci_td *td; 821 struct xhci_td *td_last; 822 823 td = xfer->td_transfer_cache; 824 td_last = xfer->td_transfer_last; 825 826 td = td->alt_next; 827 828 usb_pc_cpu_invalidate(td->page_cache); 829 830 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 831 usb_pc_cpu_invalidate(td_last->page_cache); 832 833 /* copy LINK TRB to current waiting location */ 834 835 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 836 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 837 usb_pc_cpu_flush(td->page_cache); 838 839 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 840 usb_pc_cpu_flush(td->page_cache); 841 842 xhci_endpoint_doorbell(xfer); 843 } 844 } 845 846 /*------------------------------------------------------------------------* 847 * xhci_check_transfer 848 *------------------------------------------------------------------------*/ 849 static void 850 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 851 { 852 struct xhci_endpoint_ext *pepext; 853 int64_t offset; 854 uint64_t td_event; 855 uint32_t temp; 856 uint32_t remainder; 857 uint16_t stream_id = 0; 858 uint16_t i; 859 uint8_t status; 860 uint8_t halted; 861 uint8_t epno; 862 uint8_t index; 863 864 /* decode TRB */ 865 td_event = le64toh(trb->qwTrb0); 866 temp = le32toh(trb->dwTrb2); 867 868 remainder = XHCI_TRB_2_REM_GET(temp); 869 status = XHCI_TRB_2_ERROR_GET(temp); 870 871 temp = le32toh(trb->dwTrb3); 872 epno = XHCI_TRB_3_EP_GET(temp); 873 index = XHCI_TRB_3_SLOT_GET(temp); 874 875 /* check if error means halted */ 876 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 877 status != XHCI_TRB_ERROR_SUCCESS); 878 879 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 880 index, epno, remainder, status); 881 882 if (index > sc->sc_noslot) { 883 DPRINTF("Invalid slot.\n"); 884 return; 885 } 886 887 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 888 DPRINTF("Invalid endpoint.\n"); 889 return; 890 } 891 892 pepext = &sc->sc_hw.devs[index].endp[epno]; 893 894 /* try to find the USB transfer that generated the event */ 895 for (i = 0;; i++) { 896 struct usb_xfer *xfer; 897 struct xhci_td *td; 898 899 if (i == (XHCI_MAX_TRANSFERS - 1)) { 900 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS || 901 stream_id == (XHCI_MAX_STREAMS - 1)) 902 break; 903 stream_id++; 904 i = 0; 905 DPRINTFN(5, "stream_id=%u\n", stream_id); 906 } 907 908 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 909 if (xfer == NULL) 910 continue; 911 912 td = xfer->td_transfer_cache; 913 914 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 915 (long long)td_event, 916 (long long)td->td_self, 917 (long long)td->td_self + sizeof(td->td_trb)); 918 919 /* 920 * NOTE: Some XHCI implementations might not trigger 921 * an event on the last LINK TRB so we need to 922 * consider both the last and second last event 923 * address as conditions for a successful transfer. 924 * 925 * NOTE: We assume that the XHCI will only trigger one 926 * event per chain of TRBs. 927 */ 928 929 offset = td_event - td->td_self; 930 931 if (offset >= 0 && 932 offset < (int64_t)sizeof(td->td_trb)) { 933 usb_pc_cpu_invalidate(td->page_cache); 934 935 /* compute rest of remainder, if any */ 936 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 937 temp = le32toh(td->td_trb[i].dwTrb2); 938 remainder += XHCI_TRB_2_BYTES_GET(temp); 939 } 940 941 DPRINTFN(5, "New remainder: %u\n", remainder); 942 943 /* clear isochronous transfer errors */ 944 if (xfer->flags_int.isochronous_xfr) { 945 if (halted) { 946 halted = 0; 947 status = XHCI_TRB_ERROR_SUCCESS; 948 remainder = td->len; 949 } 950 } 951 952 /* "td->remainder" is verified later */ 953 td->remainder = remainder; 954 td->status = status; 955 956 usb_pc_cpu_flush(td->page_cache); 957 958 /* 959 * 1) Last transfer descriptor makes the 960 * transfer done 961 */ 962 if (((void *)td) == xfer->td_transfer_last) { 963 DPRINTF("TD is last\n"); 964 xhci_generic_done(xfer); 965 break; 966 } 967 968 /* 969 * 2) Any kind of error makes the transfer 970 * done 971 */ 972 if (halted) { 973 DPRINTF("TD has I/O error\n"); 974 xhci_generic_done(xfer); 975 break; 976 } 977 978 /* 979 * 3) If there is no alternate next transfer, 980 * a short packet also makes the transfer done 981 */ 982 if (td->remainder > 0) { 983 if (td->alt_next == NULL) { 984 DPRINTF( 985 "short TD has no alternate next\n"); 986 xhci_generic_done(xfer); 987 break; 988 } 989 DPRINTF("TD has short pkt\n"); 990 if (xfer->flags_int.short_frames_ok || 991 xfer->flags_int.isochronous_xfr || 992 xfer->flags_int.control_xfr) { 993 /* follow the alt next */ 994 xfer->td_transfer_cache = td->alt_next; 995 xhci_activate_transfer(xfer); 996 break; 997 } 998 xhci_skip_transfer(xfer); 999 xhci_generic_done(xfer); 1000 break; 1001 } 1002 1003 /* 1004 * 4) Transfer complete - go to next TD 1005 */ 1006 DPRINTF("Following next TD\n"); 1007 xfer->td_transfer_cache = td->obj_next; 1008 xhci_activate_transfer(xfer); 1009 break; /* there should only be one match */ 1010 } 1011 } 1012 } 1013 1014 static int 1015 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1016 { 1017 if (sc->sc_cmd_addr == trb->qwTrb0) { 1018 DPRINTF("Received command event\n"); 1019 sc->sc_cmd_result[0] = trb->dwTrb2; 1020 sc->sc_cmd_result[1] = trb->dwTrb3; 1021 cv_signal(&sc->sc_cmd_cv); 1022 return (1); /* command match */ 1023 } 1024 return (0); 1025 } 1026 1027 static int 1028 xhci_interrupt_poll(struct xhci_softc *sc) 1029 { 1030 struct usb_page_search buf_res; 1031 struct xhci_hw_root *phwr; 1032 uint64_t addr; 1033 uint32_t temp; 1034 int retval = 0; 1035 uint16_t i; 1036 uint8_t event; 1037 uint8_t j; 1038 uint8_t k; 1039 uint8_t t; 1040 1041 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1042 1043 phwr = buf_res.buffer; 1044 1045 /* Receive any events */ 1046 1047 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1048 1049 i = sc->sc_event_idx; 1050 j = sc->sc_event_ccs; 1051 t = 2; 1052 1053 while (1) { 1054 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1055 1056 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1057 1058 if (j != k) 1059 break; 1060 1061 event = XHCI_TRB_3_TYPE_GET(temp); 1062 1063 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1064 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1065 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1066 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1067 1068 switch (event) { 1069 case XHCI_TRB_EVENT_TRANSFER: 1070 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1071 break; 1072 case XHCI_TRB_EVENT_CMD_COMPLETE: 1073 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1074 break; 1075 default: 1076 DPRINTF("Unhandled event = %u\n", event); 1077 break; 1078 } 1079 1080 i++; 1081 1082 if (i == XHCI_MAX_EVENTS) { 1083 i = 0; 1084 j ^= 1; 1085 1086 /* check for timeout */ 1087 if (!--t) 1088 break; 1089 } 1090 } 1091 1092 sc->sc_event_idx = i; 1093 sc->sc_event_ccs = j; 1094 1095 /* 1096 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1097 * latched. That means to activate the register we need to 1098 * write both the low and high double word of the 64-bit 1099 * register. 1100 */ 1101 1102 addr = buf_res.physaddr; 1103 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1104 1105 /* try to clear busy bit */ 1106 addr |= XHCI_ERDP_LO_BUSY; 1107 1108 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1109 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1110 1111 return (retval); 1112 } 1113 1114 static usb_error_t 1115 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1116 uint16_t timeout_ms) 1117 { 1118 struct usb_page_search buf_res; 1119 struct xhci_hw_root *phwr; 1120 uint64_t addr; 1121 uint32_t temp; 1122 uint8_t i; 1123 uint8_t j; 1124 uint8_t timeout = 0; 1125 int err; 1126 1127 XHCI_CMD_ASSERT_LOCKED(sc); 1128 1129 /* get hardware root structure */ 1130 1131 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1132 1133 phwr = buf_res.buffer; 1134 1135 /* Queue command */ 1136 1137 USB_BUS_LOCK(&sc->sc_bus); 1138 retry: 1139 i = sc->sc_command_idx; 1140 j = sc->sc_command_ccs; 1141 1142 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1143 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1144 (long long)le64toh(trb->qwTrb0), 1145 (long)le32toh(trb->dwTrb2), 1146 (long)le32toh(trb->dwTrb3)); 1147 1148 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1149 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1150 1151 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1152 1153 temp = trb->dwTrb3; 1154 1155 if (j) 1156 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1157 else 1158 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1159 1160 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1161 1162 phwr->hwr_commands[i].dwTrb3 = temp; 1163 1164 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1165 1166 addr = buf_res.physaddr; 1167 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1168 1169 sc->sc_cmd_addr = htole64(addr); 1170 1171 i++; 1172 1173 if (i == (XHCI_MAX_COMMANDS - 1)) { 1174 if (j) { 1175 temp = htole32(XHCI_TRB_3_TC_BIT | 1176 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1177 XHCI_TRB_3_CYCLE_BIT); 1178 } else { 1179 temp = htole32(XHCI_TRB_3_TC_BIT | 1180 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1181 } 1182 1183 phwr->hwr_commands[i].dwTrb3 = temp; 1184 1185 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1186 1187 i = 0; 1188 j ^= 1; 1189 } 1190 1191 sc->sc_command_idx = i; 1192 sc->sc_command_ccs = j; 1193 1194 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1195 1196 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1197 USB_MS_TO_TICKS(timeout_ms)); 1198 1199 /* 1200 * In some error cases event interrupts are not generated. 1201 * Poll one time to see if the command has completed. 1202 */ 1203 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1204 DPRINTF("Command was completed when polling\n"); 1205 err = 0; 1206 } 1207 if (err != 0) { 1208 DPRINTF("Command timeout!\n"); 1209 /* 1210 * After some weeks of continuous operation, it has 1211 * been observed that the ASMedia Technology, ASM1042 1212 * SuperSpeed USB Host Controller can suddenly stop 1213 * accepting commands via the command queue. Try to 1214 * first reset the command queue. If that fails do a 1215 * host controller reset. 1216 */ 1217 if (timeout == 0 && 1218 xhci_reset_command_queue_locked(sc) == 0) { 1219 temp = le32toh(trb->dwTrb3); 1220 1221 /* 1222 * Avoid infinite XHCI reset loops if the set 1223 * address command fails to respond due to a 1224 * non-enumerating device: 1225 */ 1226 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1227 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1228 DPRINTF("Set address timeout\n"); 1229 } else { 1230 timeout = 1; 1231 goto retry; 1232 } 1233 } else { 1234 DPRINTF("Controller reset!\n"); 1235 usb_bus_reset_async_locked(&sc->sc_bus); 1236 } 1237 err = USB_ERR_TIMEOUT; 1238 trb->dwTrb2 = 0; 1239 trb->dwTrb3 = 0; 1240 } else { 1241 temp = le32toh(sc->sc_cmd_result[0]); 1242 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1243 err = USB_ERR_IOERROR; 1244 1245 trb->dwTrb2 = sc->sc_cmd_result[0]; 1246 trb->dwTrb3 = sc->sc_cmd_result[1]; 1247 } 1248 1249 USB_BUS_UNLOCK(&sc->sc_bus); 1250 1251 return (err); 1252 } 1253 1254 #if 0 1255 static usb_error_t 1256 xhci_cmd_nop(struct xhci_softc *sc) 1257 { 1258 struct xhci_trb trb; 1259 uint32_t temp; 1260 1261 DPRINTF("\n"); 1262 1263 trb.qwTrb0 = 0; 1264 trb.dwTrb2 = 0; 1265 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1266 1267 trb.dwTrb3 = htole32(temp); 1268 1269 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1270 } 1271 #endif 1272 1273 static usb_error_t 1274 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1275 { 1276 struct xhci_trb trb; 1277 uint32_t temp; 1278 usb_error_t err; 1279 1280 DPRINTF("\n"); 1281 1282 trb.qwTrb0 = 0; 1283 trb.dwTrb2 = 0; 1284 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1285 1286 err = xhci_do_command(sc, &trb, 100 /* ms */); 1287 if (err) 1288 goto done; 1289 1290 temp = le32toh(trb.dwTrb3); 1291 1292 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1293 1294 done: 1295 return (err); 1296 } 1297 1298 static usb_error_t 1299 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1300 { 1301 struct xhci_trb trb; 1302 uint32_t temp; 1303 1304 DPRINTF("\n"); 1305 1306 trb.qwTrb0 = 0; 1307 trb.dwTrb2 = 0; 1308 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1309 XHCI_TRB_3_SLOT_SET(slot_id); 1310 1311 trb.dwTrb3 = htole32(temp); 1312 1313 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1314 } 1315 1316 static usb_error_t 1317 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1318 uint8_t bsr, uint8_t slot_id) 1319 { 1320 struct xhci_trb trb; 1321 uint32_t temp; 1322 1323 DPRINTF("\n"); 1324 1325 trb.qwTrb0 = htole64(input_ctx); 1326 trb.dwTrb2 = 0; 1327 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1328 XHCI_TRB_3_SLOT_SET(slot_id); 1329 1330 if (bsr) 1331 temp |= XHCI_TRB_3_BSR_BIT; 1332 1333 trb.dwTrb3 = htole32(temp); 1334 1335 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1336 } 1337 1338 static usb_error_t 1339 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1340 { 1341 struct usb_page_search buf_inp; 1342 struct usb_page_search buf_dev; 1343 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1344 struct xhci_hw_dev *hdev; 1345 struct xhci_slot_ctx *slot; 1346 struct xhci_endpoint_ext *pepext; 1347 uint32_t temp; 1348 uint16_t mps; 1349 usb_error_t err; 1350 uint8_t index; 1351 1352 /* the root HUB case is not handled here */ 1353 if (udev->parent_hub == NULL) 1354 return (USB_ERR_INVAL); 1355 1356 index = udev->controller_slot_id; 1357 1358 hdev = &sc->sc_hw.devs[index]; 1359 1360 if (mtx != NULL) 1361 mtx_unlock(mtx); 1362 1363 XHCI_CMD_LOCK(sc); 1364 1365 switch (hdev->state) { 1366 case XHCI_ST_DEFAULT: 1367 case XHCI_ST_ENABLED: 1368 1369 hdev->state = XHCI_ST_ENABLED; 1370 1371 /* set configure mask to slot and EP0 */ 1372 xhci_configure_mask(udev, 3, 0); 1373 1374 /* configure input slot context structure */ 1375 err = xhci_configure_device(udev); 1376 1377 if (err != 0) { 1378 DPRINTF("Could not configure device\n"); 1379 break; 1380 } 1381 1382 /* configure input endpoint context structure */ 1383 switch (udev->speed) { 1384 case USB_SPEED_LOW: 1385 case USB_SPEED_FULL: 1386 mps = 8; 1387 break; 1388 case USB_SPEED_HIGH: 1389 mps = 64; 1390 break; 1391 default: 1392 mps = 512; 1393 break; 1394 } 1395 1396 pepext = xhci_get_endpoint_ext(udev, 1397 &udev->ctrl_ep_desc); 1398 1399 /* ensure the control endpoint is setup again */ 1400 USB_BUS_LOCK(udev->bus); 1401 pepext->trb_halted = 1; 1402 pepext->trb_running = 0; 1403 USB_BUS_UNLOCK(udev->bus); 1404 1405 err = xhci_configure_endpoint(udev, 1406 &udev->ctrl_ep_desc, pepext, 1407 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1408 1409 if (err != 0) { 1410 DPRINTF("Could not configure default endpoint\n"); 1411 break; 1412 } 1413 1414 /* execute set address command */ 1415 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1416 1417 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1418 (address == 0), index); 1419 1420 if (err != 0) { 1421 temp = le32toh(sc->sc_cmd_result[0]); 1422 if (address == 0 && sc->sc_port_route != NULL && 1423 XHCI_TRB_2_ERROR_GET(temp) == 1424 XHCI_TRB_ERROR_PARAMETER) { 1425 /* LynxPoint XHCI - ports are not switchable */ 1426 /* Un-route all ports from the XHCI */ 1427 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1428 } 1429 DPRINTF("Could not set address " 1430 "for slot %u.\n", index); 1431 if (address != 0) 1432 break; 1433 } 1434 1435 /* update device address to new value */ 1436 1437 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1438 slot = XHCI_GET_CTX(sc, xhci_dev_ctx, ctx_slot, 1439 buf_dev.buffer); 1440 usb_pc_cpu_invalidate(&hdev->device_pc); 1441 1442 temp = le32toh(slot->dwSctx3); 1443 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1444 1445 /* update device state to new value */ 1446 1447 if (address != 0) 1448 hdev->state = XHCI_ST_ADDRESSED; 1449 else 1450 hdev->state = XHCI_ST_DEFAULT; 1451 break; 1452 1453 default: 1454 DPRINTF("Wrong state for set address.\n"); 1455 err = USB_ERR_IOERROR; 1456 break; 1457 } 1458 XHCI_CMD_UNLOCK(sc); 1459 1460 if (mtx != NULL) 1461 mtx_lock(mtx); 1462 1463 return (err); 1464 } 1465 1466 static usb_error_t 1467 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1468 uint8_t deconfigure, uint8_t slot_id) 1469 { 1470 struct xhci_trb trb; 1471 uint32_t temp; 1472 1473 DPRINTF("\n"); 1474 1475 trb.qwTrb0 = htole64(input_ctx); 1476 trb.dwTrb2 = 0; 1477 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1478 XHCI_TRB_3_SLOT_SET(slot_id); 1479 1480 if (deconfigure) 1481 temp |= XHCI_TRB_3_DCEP_BIT; 1482 1483 trb.dwTrb3 = htole32(temp); 1484 1485 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1486 } 1487 1488 static usb_error_t 1489 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1490 uint8_t slot_id) 1491 { 1492 struct xhci_trb trb; 1493 uint32_t temp; 1494 1495 DPRINTF("\n"); 1496 1497 trb.qwTrb0 = htole64(input_ctx); 1498 trb.dwTrb2 = 0; 1499 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1500 XHCI_TRB_3_SLOT_SET(slot_id); 1501 trb.dwTrb3 = htole32(temp); 1502 1503 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1504 } 1505 1506 static usb_error_t 1507 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1508 uint8_t ep_id, uint8_t slot_id) 1509 { 1510 struct xhci_trb trb; 1511 uint32_t temp; 1512 1513 DPRINTF("\n"); 1514 1515 trb.qwTrb0 = 0; 1516 trb.dwTrb2 = 0; 1517 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1518 XHCI_TRB_3_SLOT_SET(slot_id) | 1519 XHCI_TRB_3_EP_SET(ep_id); 1520 1521 if (preserve) 1522 temp |= XHCI_TRB_3_PRSV_BIT; 1523 1524 trb.dwTrb3 = htole32(temp); 1525 1526 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1527 } 1528 1529 static usb_error_t 1530 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1531 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1532 { 1533 struct xhci_trb trb; 1534 uint32_t temp; 1535 1536 DPRINTF("\n"); 1537 1538 trb.qwTrb0 = htole64(dequeue_ptr); 1539 1540 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1541 trb.dwTrb2 = htole32(temp); 1542 1543 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1544 XHCI_TRB_3_SLOT_SET(slot_id) | 1545 XHCI_TRB_3_EP_SET(ep_id); 1546 trb.dwTrb3 = htole32(temp); 1547 1548 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1549 } 1550 1551 static usb_error_t 1552 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1553 uint8_t ep_id, uint8_t slot_id) 1554 { 1555 struct xhci_trb trb; 1556 uint32_t temp; 1557 1558 DPRINTF("\n"); 1559 1560 trb.qwTrb0 = 0; 1561 trb.dwTrb2 = 0; 1562 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1563 XHCI_TRB_3_SLOT_SET(slot_id) | 1564 XHCI_TRB_3_EP_SET(ep_id); 1565 1566 if (suspend) 1567 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1568 1569 trb.dwTrb3 = htole32(temp); 1570 1571 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1572 } 1573 1574 static usb_error_t 1575 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1576 { 1577 struct xhci_trb trb; 1578 uint32_t temp; 1579 1580 DPRINTF("\n"); 1581 1582 trb.qwTrb0 = 0; 1583 trb.dwTrb2 = 0; 1584 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1585 XHCI_TRB_3_SLOT_SET(slot_id); 1586 1587 trb.dwTrb3 = htole32(temp); 1588 1589 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1590 } 1591 1592 /*------------------------------------------------------------------------* 1593 * xhci_interrupt - XHCI interrupt handler 1594 *------------------------------------------------------------------------*/ 1595 void 1596 xhci_interrupt(struct xhci_softc *sc) 1597 { 1598 uint32_t status; 1599 uint32_t temp; 1600 1601 USB_BUS_LOCK(&sc->sc_bus); 1602 1603 status = XREAD4(sc, oper, XHCI_USBSTS); 1604 1605 /* acknowledge interrupts, if any */ 1606 if (status != 0) { 1607 XWRITE4(sc, oper, XHCI_USBSTS, status); 1608 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1609 } 1610 1611 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1612 1613 /* force clearing of pending interrupts */ 1614 if (temp & XHCI_IMAN_INTR_PEND) 1615 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1616 1617 /* check for event(s) */ 1618 xhci_interrupt_poll(sc); 1619 1620 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1621 XHCI_STS_HSE | XHCI_STS_HCE)) { 1622 if (status & XHCI_STS_PCD) { 1623 xhci_root_intr(sc); 1624 } 1625 1626 if (status & XHCI_STS_HCH) { 1627 printf("%s: host controller halted\n", 1628 __FUNCTION__); 1629 } 1630 1631 if (status & XHCI_STS_HSE) { 1632 printf("%s: host system error\n", 1633 __FUNCTION__); 1634 } 1635 1636 if (status & XHCI_STS_HCE) { 1637 printf("%s: host controller error\n", 1638 __FUNCTION__); 1639 } 1640 } 1641 USB_BUS_UNLOCK(&sc->sc_bus); 1642 } 1643 1644 /*------------------------------------------------------------------------* 1645 * xhci_timeout - XHCI timeout handler 1646 *------------------------------------------------------------------------*/ 1647 static void 1648 xhci_timeout(void *arg) 1649 { 1650 struct usb_xfer *xfer = arg; 1651 1652 DPRINTF("xfer=%p\n", xfer); 1653 1654 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1655 1656 /* transfer is transferred */ 1657 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1658 } 1659 1660 static void 1661 xhci_do_poll(struct usb_bus *bus) 1662 { 1663 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1664 1665 USB_BUS_LOCK(&sc->sc_bus); 1666 xhci_interrupt_poll(sc); 1667 USB_BUS_UNLOCK(&sc->sc_bus); 1668 } 1669 1670 static void 1671 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1672 { 1673 struct usb_page_search buf_res; 1674 struct xhci_td *td; 1675 struct xhci_td *td_next; 1676 struct xhci_td *td_alt_next; 1677 struct xhci_td *td_first; 1678 uint32_t buf_offset; 1679 uint32_t average; 1680 uint32_t len_old; 1681 uint32_t npkt_off; 1682 uint32_t dword; 1683 uint8_t shortpkt_old; 1684 uint8_t precompute; 1685 uint8_t x; 1686 1687 td_alt_next = NULL; 1688 buf_offset = 0; 1689 shortpkt_old = temp->shortpkt; 1690 len_old = temp->len; 1691 npkt_off = 0; 1692 precompute = 1; 1693 1694 restart: 1695 1696 td = temp->td; 1697 td_next = td_first = temp->td_next; 1698 1699 while (1) { 1700 if (temp->len == 0) { 1701 if (temp->shortpkt) 1702 break; 1703 1704 /* send a Zero Length Packet, ZLP, last */ 1705 1706 temp->shortpkt = 1; 1707 average = 0; 1708 1709 } else { 1710 average = temp->average; 1711 1712 if (temp->len < average) { 1713 if (temp->len % temp->max_packet_size) { 1714 temp->shortpkt = 1; 1715 } 1716 average = temp->len; 1717 } 1718 } 1719 1720 if (td_next == NULL) 1721 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1722 1723 /* get next TD */ 1724 1725 td = td_next; 1726 td_next = td->obj_next; 1727 1728 /* check if we are pre-computing */ 1729 1730 if (precompute) { 1731 /* update remaining length */ 1732 1733 temp->len -= average; 1734 1735 continue; 1736 } 1737 /* fill out current TD */ 1738 1739 td->len = average; 1740 td->remainder = 0; 1741 td->status = 0; 1742 1743 /* update remaining length */ 1744 1745 temp->len -= average; 1746 1747 /* reset TRB index */ 1748 1749 x = 0; 1750 1751 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1752 /* immediate data */ 1753 1754 if (average > 8) 1755 average = 8; 1756 1757 td->td_trb[0].qwTrb0 = 0; 1758 1759 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1760 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1761 average); 1762 1763 dword = XHCI_TRB_2_BYTES_SET(8) | 1764 XHCI_TRB_2_TDSZ_SET(0) | 1765 XHCI_TRB_2_IRQ_SET(0); 1766 1767 td->td_trb[0].dwTrb2 = htole32(dword); 1768 1769 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1770 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1771 1772 /* check wLength */ 1773 if (td->td_trb[0].qwTrb0 & 1774 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1775 if (td->td_trb[0].qwTrb0 & 1776 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1777 dword |= XHCI_TRB_3_TRT_IN; 1778 else 1779 dword |= XHCI_TRB_3_TRT_OUT; 1780 } 1781 1782 td->td_trb[0].dwTrb3 = htole32(dword); 1783 #ifdef USB_DEBUG 1784 xhci_dump_trb(&td->td_trb[x]); 1785 #endif 1786 x++; 1787 1788 } else do { 1789 uint32_t npkt; 1790 1791 /* fill out buffer pointers */ 1792 1793 if (average == 0) { 1794 memset(&buf_res, 0, sizeof(buf_res)); 1795 } else { 1796 usbd_get_page(temp->pc, temp->offset + 1797 buf_offset, &buf_res); 1798 1799 /* get length to end of page */ 1800 if (buf_res.length > average) 1801 buf_res.length = average; 1802 1803 /* check for maximum length */ 1804 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1805 buf_res.length = XHCI_TD_PAGE_SIZE; 1806 1807 npkt_off += buf_res.length; 1808 } 1809 1810 /* set up npkt */ 1811 npkt = howmany(len_old - npkt_off, 1812 temp->max_packet_size); 1813 1814 if (npkt == 0) 1815 npkt = 1; 1816 else if (npkt > 31) 1817 npkt = 31; 1818 1819 /* fill out TRB's */ 1820 td->td_trb[x].qwTrb0 = 1821 htole64((uint64_t)buf_res.physaddr); 1822 1823 dword = 1824 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1825 XHCI_TRB_2_TDSZ_SET(npkt) | 1826 XHCI_TRB_2_IRQ_SET(0); 1827 1828 td->td_trb[x].dwTrb2 = htole32(dword); 1829 1830 switch (temp->trb_type) { 1831 case XHCI_TRB_TYPE_ISOCH: 1832 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1833 XHCI_TRB_3_TBC_SET(temp->tbc) | 1834 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1835 if (td != td_first) { 1836 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1837 } else if (temp->do_isoc_sync != 0) { 1838 temp->do_isoc_sync = 0; 1839 /* wait until "isoc_frame" */ 1840 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1841 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1842 } else { 1843 /* start data transfer at next interval */ 1844 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1845 XHCI_TRB_3_ISO_SIA_BIT; 1846 } 1847 if (temp->direction == UE_DIR_IN) 1848 dword |= XHCI_TRB_3_ISP_BIT; 1849 break; 1850 case XHCI_TRB_TYPE_DATA_STAGE: 1851 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1852 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1853 if (temp->direction == UE_DIR_IN) 1854 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1855 /* 1856 * Section 3.2.9 in the XHCI 1857 * specification about control 1858 * transfers says that we should use a 1859 * normal-TRB if there are more TRBs 1860 * extending the data-stage 1861 * TRB. Update the "trb_type". 1862 */ 1863 temp->trb_type = XHCI_TRB_TYPE_NORMAL; 1864 break; 1865 case XHCI_TRB_TYPE_STATUS_STAGE: 1866 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1867 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1868 if (temp->direction == UE_DIR_IN) 1869 dword |= XHCI_TRB_3_DIR_IN; 1870 break; 1871 default: /* XHCI_TRB_TYPE_NORMAL */ 1872 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1873 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1874 if (temp->direction == UE_DIR_IN) 1875 dword |= XHCI_TRB_3_ISP_BIT; 1876 break; 1877 } 1878 td->td_trb[x].dwTrb3 = htole32(dword); 1879 1880 average -= buf_res.length; 1881 buf_offset += buf_res.length; 1882 #ifdef USB_DEBUG 1883 xhci_dump_trb(&td->td_trb[x]); 1884 #endif 1885 x++; 1886 1887 } while (average != 0); 1888 1889 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1890 1891 /* store number of data TRB's */ 1892 1893 td->ntrb = x; 1894 1895 DPRINTF("NTRB=%u\n", x); 1896 1897 /* fill out link TRB */ 1898 1899 if (td_next != NULL) { 1900 /* link the current TD with the next one */ 1901 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1902 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1903 } else { 1904 /* this field will get updated later */ 1905 DPRINTF("NOLINK\n"); 1906 } 1907 1908 dword = XHCI_TRB_2_IRQ_SET(0); 1909 1910 td->td_trb[x].dwTrb2 = htole32(dword); 1911 1912 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1913 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1914 /* 1915 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1916 * frame only receives a single short packet event 1917 * by setting the CHAIN bit in the LINK field. In 1918 * addition some XHCI controllers have problems 1919 * sending a ZLP unless the CHAIN-BIT is set in 1920 * the LINK TRB. 1921 */ 1922 XHCI_TRB_3_CHAIN_BIT; 1923 1924 td->td_trb[x].dwTrb3 = htole32(dword); 1925 1926 td->alt_next = td_alt_next; 1927 #ifdef USB_DEBUG 1928 xhci_dump_trb(&td->td_trb[x]); 1929 #endif 1930 usb_pc_cpu_flush(td->page_cache); 1931 } 1932 1933 if (precompute) { 1934 precompute = 0; 1935 1936 /* set up alt next pointer, if any */ 1937 if (temp->last_frame) { 1938 td_alt_next = NULL; 1939 } else { 1940 /* we use this field internally */ 1941 td_alt_next = td_next; 1942 } 1943 1944 /* restore */ 1945 temp->shortpkt = shortpkt_old; 1946 temp->len = len_old; 1947 goto restart; 1948 } 1949 1950 /* 1951 * Remove cycle bit from the first TRB if we are 1952 * stepping them: 1953 */ 1954 if (temp->step_td != 0) { 1955 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1956 usb_pc_cpu_flush(td_first->page_cache); 1957 } 1958 1959 /* clear TD SIZE to zero, hence this is the last TRB */ 1960 /* remove chain bit because this is the last data TRB in the chain */ 1961 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31)); 1962 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1963 /* remove CHAIN-BIT from last LINK TRB */ 1964 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1965 1966 usb_pc_cpu_flush(td->page_cache); 1967 1968 temp->td = td; 1969 temp->td_next = td_next; 1970 } 1971 1972 static void 1973 xhci_setup_generic_chain(struct usb_xfer *xfer) 1974 { 1975 struct xhci_std_temp temp; 1976 struct xhci_td *td; 1977 uint32_t x; 1978 uint32_t y; 1979 uint8_t mult; 1980 1981 temp.do_isoc_sync = 0; 1982 temp.step_td = 0; 1983 temp.tbc = 0; 1984 temp.tlbpc = 0; 1985 temp.average = xfer->max_hc_frame_size; 1986 temp.max_packet_size = xfer->max_packet_size; 1987 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1988 temp.pc = NULL; 1989 temp.last_frame = 0; 1990 temp.offset = 0; 1991 temp.multishort = xfer->flags_int.isochronous_xfr || 1992 xfer->flags_int.control_xfr || 1993 xfer->flags_int.short_frames_ok; 1994 1995 /* toggle the DMA set we are using */ 1996 xfer->flags_int.curr_dma_set ^= 1; 1997 1998 /* get next DMA set */ 1999 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2000 2001 temp.td = NULL; 2002 temp.td_next = td; 2003 2004 xfer->td_transfer_first = td; 2005 xfer->td_transfer_cache = td; 2006 2007 if (xfer->flags_int.isochronous_xfr) { 2008 uint8_t shift; 2009 2010 /* compute multiplier for ISOCHRONOUS transfers */ 2011 mult = xfer->endpoint->ecomp ? 2012 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2013 : 0; 2014 /* check for USB 2.0 multiplier */ 2015 if (mult == 0) { 2016 mult = (xfer->endpoint->edesc-> 2017 wMaxPacketSize[1] >> 3) & 3; 2018 } 2019 /* range check */ 2020 if (mult > 2) 2021 mult = 3; 2022 else 2023 mult++; 2024 2025 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2026 2027 DPRINTF("MFINDEX=0x%08x IST=0x%x\n", x, temp.sc->sc_ist); 2028 2029 switch (usbd_get_speed(xfer->xroot->udev)) { 2030 case USB_SPEED_FULL: 2031 shift = 3; 2032 temp.isoc_delta = 8; /* 1ms */ 2033 break; 2034 default: 2035 shift = usbd_xfer_get_fps_shift(xfer); 2036 temp.isoc_delta = 1U << shift; 2037 break; 2038 } 2039 2040 /* Compute isochronous scheduling threshold. */ 2041 if (temp.sc->sc_ist & 8) 2042 y = (temp.sc->sc_ist & 7) << 3; 2043 else 2044 y = (temp.sc->sc_ist & 7); 2045 2046 /* Range check the IST. */ 2047 if (y < 8) { 2048 y = 0; 2049 } else if (y > 15) { 2050 DPRINTFN(3, "IST(%d) is too big!\n", temp.sc->sc_ist); 2051 /* 2052 * The USB stack minimum isochronous transfer 2053 * size is typically 2x2 ms of payload. If the 2054 * IST makes is above 15 microframes, we have 2055 * an effective scheduling delay of more than 2056 * or equal to 2 milliseconds, which is too 2057 * much. 2058 */ 2059 y = 7; 2060 } else { 2061 /* 2062 * Subtract one millisecond, because the 2063 * generic code adds that to the latency. 2064 */ 2065 y -= 8; 2066 } 2067 2068 if (usbd_xfer_get_isochronous_start_frame( 2069 xfer, x, y, 8, XHCI_MFINDEX_GET(-1), &temp.isoc_frame)) { 2070 /* Start isochronous transfer at specified time. */ 2071 temp.do_isoc_sync = 1; 2072 2073 DPRINTFN(3, "start next=%d\n", temp.isoc_frame); 2074 } 2075 2076 x = 0; 2077 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2078 2079 } else if (xfer->flags_int.control_xfr) { 2080 /* check if we should prepend a setup message */ 2081 2082 if (xfer->flags_int.control_hdr) { 2083 temp.len = xfer->frlengths[0]; 2084 temp.pc = xfer->frbuffers + 0; 2085 temp.shortpkt = temp.len ? 1 : 0; 2086 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2087 temp.direction = 0; 2088 2089 /* check for last frame */ 2090 if (xfer->nframes == 1) { 2091 /* no STATUS stage yet, SETUP is last */ 2092 if (xfer->flags_int.control_act) 2093 temp.last_frame = 1; 2094 } 2095 2096 xhci_setup_generic_chain_sub(&temp); 2097 } 2098 x = 1; 2099 mult = 1; 2100 temp.isoc_delta = 0; 2101 temp.isoc_frame = 0; 2102 temp.trb_type = xfer->flags_int.control_did_data ? 2103 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE; 2104 } else { 2105 x = 0; 2106 mult = 1; 2107 temp.isoc_delta = 0; 2108 temp.isoc_frame = 0; 2109 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2110 } 2111 2112 if (x != xfer->nframes) { 2113 /* set up page_cache pointer */ 2114 temp.pc = xfer->frbuffers + x; 2115 /* set endpoint direction */ 2116 temp.direction = UE_GET_DIR(xfer->endpointno); 2117 } 2118 2119 while (x != xfer->nframes) { 2120 /* DATA0 / DATA1 message */ 2121 2122 temp.len = xfer->frlengths[x]; 2123 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2124 x != 0 && temp.multishort == 0); 2125 2126 x++; 2127 2128 if (x == xfer->nframes) { 2129 if (xfer->flags_int.control_xfr) { 2130 /* no STATUS stage yet, DATA is last */ 2131 if (xfer->flags_int.control_act) 2132 temp.last_frame = 1; 2133 } else { 2134 temp.last_frame = 1; 2135 } 2136 } 2137 if (temp.len == 0) { 2138 /* make sure that we send an USB packet */ 2139 2140 temp.shortpkt = 0; 2141 2142 temp.tbc = 0; 2143 temp.tlbpc = mult - 1; 2144 2145 } else if (xfer->flags_int.isochronous_xfr) { 2146 uint8_t tdpc; 2147 2148 /* 2149 * Isochronous transfers don't have short 2150 * packet termination: 2151 */ 2152 2153 temp.shortpkt = 1; 2154 2155 /* isochronous transfers have a transfer limit */ 2156 2157 if (temp.len > xfer->max_frame_size) 2158 temp.len = xfer->max_frame_size; 2159 2160 /* compute TD packet count */ 2161 tdpc = howmany(temp.len, xfer->max_packet_size); 2162 2163 temp.tbc = howmany(tdpc, mult) - 1; 2164 temp.tlbpc = (tdpc % mult); 2165 2166 if (temp.tlbpc == 0) 2167 temp.tlbpc = mult - 1; 2168 else 2169 temp.tlbpc--; 2170 } else { 2171 /* regular data transfer */ 2172 2173 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2174 } 2175 2176 xhci_setup_generic_chain_sub(&temp); 2177 2178 if (xfer->flags_int.isochronous_xfr) { 2179 temp.offset += xfer->frlengths[x - 1]; 2180 temp.isoc_frame += temp.isoc_delta; 2181 } else { 2182 /* get next Page Cache pointer */ 2183 temp.pc = xfer->frbuffers + x; 2184 } 2185 } 2186 2187 /* check if we should append a status stage */ 2188 2189 if (xfer->flags_int.control_xfr && 2190 !xfer->flags_int.control_act) { 2191 /* 2192 * Send a DATA1 message and invert the current 2193 * endpoint direction. 2194 */ 2195 if (xhcictlstep || temp.sc->sc_ctlstep) { 2196 /* 2197 * Some XHCI controllers will not delay the 2198 * status stage until the next SOF. Force this 2199 * behaviour to avoid failed control 2200 * transfers. 2201 */ 2202 temp.step_td = (xfer->nframes != 0); 2203 } else { 2204 temp.step_td = 0; 2205 } 2206 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2207 temp.len = 0; 2208 temp.pc = NULL; 2209 temp.shortpkt = 0; 2210 temp.last_frame = 1; 2211 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2212 2213 xhci_setup_generic_chain_sub(&temp); 2214 } 2215 2216 td = temp.td; 2217 2218 /* must have at least one frame! */ 2219 2220 xfer->td_transfer_last = td; 2221 2222 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2223 } 2224 2225 static void 2226 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2227 { 2228 struct usb_page_search buf_res; 2229 struct xhci_dev_ctx_addr *pdctxa; 2230 2231 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2232 2233 pdctxa = buf_res.buffer; 2234 2235 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2236 2237 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2238 2239 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2240 } 2241 2242 static usb_error_t 2243 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2244 { 2245 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2246 struct usb_page_search buf_inp; 2247 struct xhci_input_ctx *input; 2248 struct xhci_slot_ctx *slot; 2249 uint32_t temp; 2250 uint8_t index; 2251 uint8_t x; 2252 2253 index = udev->controller_slot_id; 2254 2255 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2256 2257 input = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_input, 2258 buf_inp.buffer); 2259 slot = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_slot, buf_inp.buffer); 2260 2261 if (drop) { 2262 mask &= XHCI_INCTX_NON_CTRL_MASK; 2263 input->dwInCtx0 = htole32(mask); 2264 input->dwInCtx1 = htole32(0); 2265 } else { 2266 /* 2267 * Some hardware requires that we drop the endpoint 2268 * context before adding it again: 2269 */ 2270 input->dwInCtx0 = htole32(mask & XHCI_INCTX_NON_CTRL_MASK); 2271 2272 /* Add new endpoint context */ 2273 input->dwInCtx1 = htole32(mask); 2274 2275 /* find most significant set bit */ 2276 for (x = 31; x != 1; x--) { 2277 if (mask & (1 << x)) 2278 break; 2279 } 2280 2281 /* adjust */ 2282 x--; 2283 2284 /* figure out the maximum number of contexts */ 2285 if (x > sc->sc_hw.devs[index].context_num) 2286 sc->sc_hw.devs[index].context_num = x; 2287 else 2288 x = sc->sc_hw.devs[index].context_num; 2289 2290 /* update number of contexts */ 2291 temp = le32toh(slot->dwSctx0); 2292 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2293 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2294 slot->dwSctx0 = htole32(temp); 2295 } 2296 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2297 return (0); 2298 } 2299 2300 static usb_error_t 2301 xhci_configure_endpoint(struct usb_device *udev, 2302 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2303 uint16_t interval, uint8_t max_packet_count, 2304 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2305 uint16_t max_frame_size, uint8_t ep_mode) 2306 { 2307 struct usb_page_search buf_inp; 2308 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2309 struct xhci_endp_ctx *endp; 2310 uint64_t ring_addr = pepext->physaddr; 2311 uint32_t temp; 2312 uint8_t index; 2313 uint8_t epno; 2314 uint8_t type; 2315 2316 index = udev->controller_slot_id; 2317 2318 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2319 2320 epno = edesc->bEndpointAddress; 2321 type = edesc->bmAttributes & UE_XFERTYPE; 2322 2323 if (type == UE_CONTROL) 2324 epno |= UE_DIR_IN; 2325 2326 epno = XHCI_EPNO2EPID(epno); 2327 2328 if (epno == 0) 2329 return (USB_ERR_NO_PIPE); /* invalid */ 2330 2331 if (max_packet_count == 0) 2332 return (USB_ERR_BAD_BUFSIZE); 2333 2334 max_packet_count--; 2335 2336 if (mult == 0) 2337 return (USB_ERR_BAD_BUFSIZE); 2338 2339 endp = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_ep[epno - 1], 2340 buf_inp.buffer); 2341 2342 /* store endpoint mode */ 2343 pepext->trb_ep_mode = ep_mode; 2344 /* store bMaxPacketSize for control endpoints */ 2345 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0]; 2346 usb_pc_cpu_flush(pepext->page_cache); 2347 2348 if (ep_mode == USB_EP_MODE_STREAMS) { 2349 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2350 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2351 XHCI_EPCTX_0_LSA_SET(1); 2352 2353 ring_addr += sizeof(struct xhci_trb) * 2354 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2355 } else { 2356 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2357 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2358 XHCI_EPCTX_0_LSA_SET(0); 2359 2360 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2361 } 2362 2363 switch (udev->speed) { 2364 case USB_SPEED_FULL: 2365 case USB_SPEED_LOW: 2366 /* 1ms -> 125us */ 2367 fps_shift += 3; 2368 break; 2369 default: 2370 break; 2371 } 2372 2373 switch (type) { 2374 case UE_INTERRUPT: 2375 if (fps_shift > 3) 2376 fps_shift--; 2377 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2378 break; 2379 case UE_ISOCHRONOUS: 2380 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2381 2382 switch (udev->speed) { 2383 case USB_SPEED_SUPER: 2384 if (mult > 3) 2385 mult = 3; 2386 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2387 max_packet_count /= mult; 2388 break; 2389 default: 2390 break; 2391 } 2392 break; 2393 default: 2394 break; 2395 } 2396 2397 endp->dwEpCtx0 = htole32(temp); 2398 2399 temp = 2400 XHCI_EPCTX_1_HID_SET(0) | 2401 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2402 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2403 2404 /* 2405 * Always enable the "three strikes and you are gone" feature 2406 * except for ISOCHRONOUS endpoints. This is suggested by 2407 * section 4.3.3 in the XHCI specification about device slot 2408 * initialisation. 2409 */ 2410 if (type != UE_ISOCHRONOUS) 2411 temp |= XHCI_EPCTX_1_CERR_SET(3); 2412 2413 switch (type) { 2414 case UE_CONTROL: 2415 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2416 break; 2417 case UE_ISOCHRONOUS: 2418 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2419 break; 2420 case UE_BULK: 2421 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2422 break; 2423 default: 2424 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2425 break; 2426 } 2427 2428 /* check for IN direction */ 2429 if (epno & 1) 2430 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2431 2432 endp->dwEpCtx1 = htole32(temp); 2433 endp->qwEpCtx2 = htole64(ring_addr); 2434 2435 switch (edesc->bmAttributes & UE_XFERTYPE) { 2436 case UE_INTERRUPT: 2437 case UE_ISOCHRONOUS: 2438 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2439 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2440 max_frame_size)); 2441 break; 2442 case UE_CONTROL: 2443 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2444 break; 2445 default: 2446 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2447 break; 2448 } 2449 2450 endp->dwEpCtx4 = htole32(temp); 2451 2452 #ifdef USB_DEBUG 2453 xhci_dump_endpoint(endp); 2454 #endif 2455 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2456 2457 return (0); /* success */ 2458 } 2459 2460 static usb_error_t 2461 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2462 { 2463 struct xhci_endpoint_ext *pepext; 2464 struct usb_endpoint_ss_comp_descriptor *ecomp; 2465 usb_stream_t x; 2466 2467 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2468 xfer->endpoint->edesc); 2469 2470 ecomp = xfer->endpoint->ecomp; 2471 2472 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2473 uint64_t temp; 2474 2475 /* halt any transfers */ 2476 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2477 2478 /* compute start of TRB ring for stream "x" */ 2479 temp = pepext->physaddr + 2480 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2481 XHCI_SCTX_0_SCT_SEC_TR_RING; 2482 2483 /* make tree structure */ 2484 pepext->trb[(XHCI_MAX_TRANSFERS * 2485 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2486 2487 /* reserved fields */ 2488 pepext->trb[(XHCI_MAX_TRANSFERS * 2489 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2490 pepext->trb[(XHCI_MAX_TRANSFERS * 2491 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2492 } 2493 usb_pc_cpu_flush(pepext->page_cache); 2494 2495 return (xhci_configure_endpoint(xfer->xroot->udev, 2496 xfer->endpoint->edesc, pepext, 2497 xfer->interval, xfer->max_packet_count, 2498 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2499 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2500 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2501 } 2502 2503 static usb_error_t 2504 xhci_configure_device(struct usb_device *udev) 2505 { 2506 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2507 struct usb_page_search buf_inp; 2508 struct usb_page_cache *pcinp; 2509 struct xhci_slot_ctx *slot; 2510 struct usb_device *hubdev; 2511 uint32_t temp; 2512 uint32_t route; 2513 uint32_t rh_port; 2514 uint8_t is_hub; 2515 uint8_t index; 2516 uint8_t depth; 2517 2518 index = udev->controller_slot_id; 2519 2520 DPRINTF("index=%u\n", index); 2521 2522 pcinp = &sc->sc_hw.devs[index].input_pc; 2523 2524 usbd_get_page(pcinp, 0, &buf_inp); 2525 2526 slot = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_slot, buf_inp.buffer); 2527 2528 rh_port = 0; 2529 route = 0; 2530 2531 /* figure out route string and root HUB port number */ 2532 2533 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2534 if (hubdev->parent_hub == NULL) 2535 break; 2536 2537 depth = hubdev->parent_hub->depth; 2538 2539 /* 2540 * NOTE: HS/FS/LS devices and the SS root HUB can have 2541 * more than 15 ports 2542 */ 2543 2544 rh_port = hubdev->port_no; 2545 2546 if (depth == 0) 2547 break; 2548 2549 if (rh_port > 15) 2550 rh_port = 15; 2551 2552 if (depth < 6) 2553 route |= rh_port << (4 * (depth - 1)); 2554 } 2555 2556 DPRINTF("Route=0x%08x\n", route); 2557 2558 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2559 XHCI_SCTX_0_CTX_NUM_SET( 2560 sc->sc_hw.devs[index].context_num + 1); 2561 2562 switch (udev->speed) { 2563 case USB_SPEED_LOW: 2564 temp |= XHCI_SCTX_0_SPEED_SET(2); 2565 if (udev->parent_hs_hub != NULL && 2566 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2567 UDPROTO_HSHUBMTT) { 2568 DPRINTF("Device inherits MTT\n"); 2569 temp |= XHCI_SCTX_0_MTT_SET(1); 2570 } 2571 break; 2572 case USB_SPEED_HIGH: 2573 temp |= XHCI_SCTX_0_SPEED_SET(3); 2574 if (sc->sc_hw.devs[index].nports != 0 && 2575 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2576 DPRINTF("HUB supports MTT\n"); 2577 temp |= XHCI_SCTX_0_MTT_SET(1); 2578 } 2579 break; 2580 case USB_SPEED_FULL: 2581 temp |= XHCI_SCTX_0_SPEED_SET(1); 2582 if (udev->parent_hs_hub != NULL && 2583 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2584 UDPROTO_HSHUBMTT) { 2585 DPRINTF("Device inherits MTT\n"); 2586 temp |= XHCI_SCTX_0_MTT_SET(1); 2587 } 2588 break; 2589 default: 2590 temp |= XHCI_SCTX_0_SPEED_SET(4); 2591 break; 2592 } 2593 2594 is_hub = sc->sc_hw.devs[index].nports != 0 && 2595 (udev->speed == USB_SPEED_SUPER || 2596 udev->speed == USB_SPEED_HIGH); 2597 2598 if (is_hub) 2599 temp |= XHCI_SCTX_0_HUB_SET(1); 2600 2601 slot->dwSctx0 = htole32(temp); 2602 2603 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2604 2605 if (is_hub) { 2606 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2607 sc->sc_hw.devs[index].nports); 2608 } 2609 2610 slot->dwSctx1 = htole32(temp); 2611 2612 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2613 2614 if (is_hub) { 2615 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2616 sc->sc_hw.devs[index].tt); 2617 } 2618 2619 hubdev = udev->parent_hs_hub; 2620 2621 /* check if we should activate the transaction translator */ 2622 switch (udev->speed) { 2623 case USB_SPEED_FULL: 2624 case USB_SPEED_LOW: 2625 if (hubdev != NULL) { 2626 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2627 hubdev->controller_slot_id); 2628 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2629 udev->hs_port_no); 2630 } 2631 break; 2632 default: 2633 break; 2634 } 2635 2636 slot->dwSctx2 = htole32(temp); 2637 2638 /* 2639 * These fields should be initialized to zero, according to 2640 * XHCI section 6.2.2 - slot context: 2641 */ 2642 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2643 XHCI_SCTX_3_SLOT_STATE_SET(0); 2644 2645 slot->dwSctx3 = htole32(temp); 2646 2647 #ifdef USB_DEBUG 2648 xhci_dump_device(slot); 2649 #endif 2650 usb_pc_cpu_flush(pcinp); 2651 2652 return (0); /* success */ 2653 } 2654 2655 static usb_error_t 2656 xhci_alloc_device_ext(struct usb_device *udev) 2657 { 2658 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2659 struct usb_page_search buf_dev; 2660 struct usb_page_search buf_ep; 2661 struct xhci_trb *trb; 2662 struct usb_page_cache *pc; 2663 struct usb_page *pg; 2664 uint64_t addr; 2665 uint8_t index; 2666 uint8_t i; 2667 2668 index = udev->controller_slot_id; 2669 2670 pc = &sc->sc_hw.devs[index].device_pc; 2671 pg = &sc->sc_hw.devs[index].device_pg; 2672 2673 /* need to initialize the page cache */ 2674 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2675 2676 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2677 sizeof(struct xhci_dev_ctx64) : 2678 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2679 goto error; 2680 2681 usbd_get_page(pc, 0, &buf_dev); 2682 2683 pc = &sc->sc_hw.devs[index].input_pc; 2684 pg = &sc->sc_hw.devs[index].input_pg; 2685 2686 /* need to initialize the page cache */ 2687 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2688 2689 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2690 sizeof(struct xhci_input_dev_ctx64) : 2691 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2692 goto error; 2693 } 2694 2695 /* initialize all endpoint LINK TRBs */ 2696 2697 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2698 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2699 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2700 2701 /* need to initialize the page cache */ 2702 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2703 2704 if (usb_pc_alloc_mem(pc, pg, 2705 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2706 goto error; 2707 } 2708 2709 /* lookup endpoint TRB ring */ 2710 usbd_get_page(pc, 0, &buf_ep); 2711 2712 /* get TRB pointer */ 2713 trb = buf_ep.buffer; 2714 trb += XHCI_MAX_TRANSFERS - 1; 2715 2716 /* get TRB start address */ 2717 addr = buf_ep.physaddr; 2718 2719 /* create LINK TRB */ 2720 trb->qwTrb0 = htole64(addr); 2721 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2722 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2723 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2724 2725 usb_pc_cpu_flush(pc); 2726 } 2727 2728 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2729 2730 return (0); 2731 2732 error: 2733 xhci_free_device_ext(udev); 2734 2735 return (USB_ERR_NOMEM); 2736 } 2737 2738 static void 2739 xhci_free_device_ext(struct usb_device *udev) 2740 { 2741 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2742 uint8_t index; 2743 uint8_t i; 2744 2745 index = udev->controller_slot_id; 2746 xhci_set_slot_pointer(sc, index, 0); 2747 2748 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2749 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2750 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2751 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2752 } 2753 2754 static struct xhci_endpoint_ext * 2755 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2756 { 2757 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2758 struct xhci_endpoint_ext *pepext; 2759 struct usb_page_cache *pc; 2760 struct usb_page_search buf_ep; 2761 uint8_t epno; 2762 uint8_t index; 2763 2764 epno = edesc->bEndpointAddress; 2765 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2766 epno |= UE_DIR_IN; 2767 2768 epno = XHCI_EPNO2EPID(epno); 2769 2770 index = udev->controller_slot_id; 2771 2772 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2773 2774 usbd_get_page(pc, 0, &buf_ep); 2775 2776 pepext = &sc->sc_hw.devs[index].endp[epno]; 2777 pepext->page_cache = pc; 2778 pepext->trb = buf_ep.buffer; 2779 pepext->physaddr = buf_ep.physaddr; 2780 2781 return (pepext); 2782 } 2783 2784 static void 2785 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2786 { 2787 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2788 uint8_t epno; 2789 uint8_t index; 2790 2791 epno = xfer->endpointno; 2792 if (xfer->flags_int.control_xfr) 2793 epno |= UE_DIR_IN; 2794 2795 epno = XHCI_EPNO2EPID(epno); 2796 index = xfer->xroot->udev->controller_slot_id; 2797 2798 if (xfer->xroot->udev->flags.self_suspended == 0) { 2799 XWRITE4(sc, door, XHCI_DOORBELL(index), 2800 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2801 } 2802 } 2803 2804 static void 2805 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2806 { 2807 struct xhci_endpoint_ext *pepext; 2808 2809 if (xfer->flags_int.bandwidth_reclaimed) { 2810 xfer->flags_int.bandwidth_reclaimed = 0; 2811 2812 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2813 xfer->endpoint->edesc); 2814 2815 pepext->trb_used[xfer->stream_id]--; 2816 2817 pepext->xfer[xfer->qh_pos] = NULL; 2818 2819 if (error && pepext->trb_running != 0) { 2820 pepext->trb_halted = 1; 2821 pepext->trb_running = 0; 2822 } 2823 } 2824 } 2825 2826 static usb_error_t 2827 xhci_transfer_insert(struct usb_xfer *xfer) 2828 { 2829 struct xhci_td *td_first; 2830 struct xhci_td *td_last; 2831 struct xhci_trb *trb_link; 2832 struct xhci_endpoint_ext *pepext; 2833 uint64_t addr; 2834 usb_stream_t id; 2835 uint8_t i; 2836 uint8_t inext; 2837 uint8_t trb_limit; 2838 2839 DPRINTFN(8, "\n"); 2840 2841 id = xfer->stream_id; 2842 2843 /* check if already inserted */ 2844 if (xfer->flags_int.bandwidth_reclaimed) { 2845 DPRINTFN(8, "Already in schedule\n"); 2846 return (0); 2847 } 2848 2849 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2850 xfer->endpoint->edesc); 2851 2852 td_first = xfer->td_transfer_first; 2853 td_last = xfer->td_transfer_last; 2854 addr = pepext->physaddr; 2855 2856 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2857 case UE_CONTROL: 2858 case UE_INTERRUPT: 2859 /* single buffered */ 2860 trb_limit = 1; 2861 break; 2862 default: 2863 /* multi buffered */ 2864 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2865 break; 2866 } 2867 2868 if (pepext->trb_used[id] >= trb_limit) { 2869 DPRINTFN(8, "Too many TDs queued.\n"); 2870 return (USB_ERR_NOMEM); 2871 } 2872 2873 /* check if bMaxPacketSize changed */ 2874 if (xfer->flags_int.control_xfr != 0 && 2875 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) { 2876 DPRINTFN(8, "Reconfigure control endpoint\n"); 2877 2878 /* force driver to reconfigure endpoint */ 2879 pepext->trb_halted = 1; 2880 pepext->trb_running = 0; 2881 } 2882 2883 /* check for stopped condition, after putting transfer on interrupt queue */ 2884 if (pepext->trb_running == 0) { 2885 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2886 2887 DPRINTFN(8, "Not running\n"); 2888 2889 /* start configuration */ 2890 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2891 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2892 return (0); 2893 } 2894 2895 pepext->trb_used[id]++; 2896 2897 /* get current TRB index */ 2898 i = pepext->trb_index[id]; 2899 2900 /* get next TRB index */ 2901 inext = (i + 1); 2902 2903 /* the last entry of the ring is a hardcoded link TRB */ 2904 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2905 inext = 0; 2906 2907 /* store next TRB index, before stream ID offset is added */ 2908 pepext->trb_index[id] = inext; 2909 2910 /* offset for stream */ 2911 i += id * XHCI_MAX_TRANSFERS; 2912 inext += id * XHCI_MAX_TRANSFERS; 2913 2914 /* compute terminating return address */ 2915 addr += (inext * sizeof(struct xhci_trb)); 2916 2917 /* compute link TRB pointer */ 2918 trb_link = td_last->td_trb + td_last->ntrb; 2919 2920 /* update next pointer of last link TRB */ 2921 trb_link->qwTrb0 = htole64(addr); 2922 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2923 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2924 XHCI_TRB_3_CYCLE_BIT | 2925 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2926 2927 #ifdef USB_DEBUG 2928 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2929 #endif 2930 usb_pc_cpu_flush(td_last->page_cache); 2931 2932 /* write ahead chain end marker */ 2933 2934 pepext->trb[inext].qwTrb0 = 0; 2935 pepext->trb[inext].dwTrb2 = 0; 2936 pepext->trb[inext].dwTrb3 = 0; 2937 2938 /* update next pointer of link TRB */ 2939 2940 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2941 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2942 2943 #ifdef USB_DEBUG 2944 xhci_dump_trb(&pepext->trb[i]); 2945 #endif 2946 usb_pc_cpu_flush(pepext->page_cache); 2947 2948 /* toggle cycle bit which activates the transfer chain */ 2949 2950 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2951 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2952 2953 usb_pc_cpu_flush(pepext->page_cache); 2954 2955 DPRINTF("qh_pos = %u\n", i); 2956 2957 pepext->xfer[i] = xfer; 2958 2959 xfer->qh_pos = i; 2960 2961 xfer->flags_int.bandwidth_reclaimed = 1; 2962 2963 xhci_endpoint_doorbell(xfer); 2964 2965 return (0); 2966 } 2967 2968 static void 2969 xhci_root_intr(struct xhci_softc *sc) 2970 { 2971 uint16_t i; 2972 2973 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2974 2975 /* clear any old interrupt data */ 2976 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2977 2978 for (i = 1; i <= sc->sc_noport; i++) { 2979 /* pick out CHANGE bits from the status register */ 2980 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2981 XHCI_PS_CSC | XHCI_PS_PEC | 2982 XHCI_PS_OCC | XHCI_PS_WRC | 2983 XHCI_PS_PRC | XHCI_PS_PLC | 2984 XHCI_PS_CEC)) { 2985 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2986 DPRINTF("port %d changed\n", i); 2987 } 2988 } 2989 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2990 sizeof(sc->sc_hub_idata)); 2991 } 2992 2993 /*------------------------------------------------------------------------* 2994 * xhci_device_done - XHCI done handler 2995 * 2996 * NOTE: This function can be called two times in a row on 2997 * the same USB transfer. From close and from interrupt. 2998 *------------------------------------------------------------------------*/ 2999 static void 3000 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 3001 { 3002 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 3003 xfer, xfer->endpoint, error); 3004 3005 /* remove transfer from HW queue */ 3006 xhci_transfer_remove(xfer, error); 3007 3008 /* dequeue transfer and start next transfer */ 3009 usbd_transfer_done(xfer, error); 3010 } 3011 3012 /*------------------------------------------------------------------------* 3013 * XHCI data transfer support (generic type) 3014 *------------------------------------------------------------------------*/ 3015 static void 3016 xhci_device_generic_open(struct usb_xfer *xfer) 3017 { 3018 DPRINTF("\n"); 3019 } 3020 3021 static void 3022 xhci_device_generic_close(struct usb_xfer *xfer) 3023 { 3024 DPRINTF("\n"); 3025 3026 xhci_device_done(xfer, USB_ERR_CANCELLED); 3027 } 3028 3029 static void 3030 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3031 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3032 { 3033 struct usb_xfer *xfer; 3034 3035 /* check if there is a current transfer */ 3036 xfer = ep->endpoint_q[stream_id].curr; 3037 if (xfer == NULL) 3038 return; 3039 3040 /* 3041 * Check if the current transfer is started and then pickup 3042 * the next one, if any. Else wait for next start event due to 3043 * block on failure feature. 3044 */ 3045 if (!xfer->flags_int.bandwidth_reclaimed) 3046 return; 3047 3048 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3049 if (xfer == NULL) { 3050 /* 3051 * In case of enter we have to consider that the 3052 * transfer is queued by the USB core after the enter 3053 * method is called. 3054 */ 3055 xfer = enter_xfer; 3056 3057 if (xfer == NULL) 3058 return; 3059 } 3060 3061 /* try to multi buffer */ 3062 xhci_transfer_insert(xfer); 3063 } 3064 3065 static void 3066 xhci_device_generic_enter(struct usb_xfer *xfer) 3067 { 3068 DPRINTF("\n"); 3069 3070 /* set up TD's and QH */ 3071 xhci_setup_generic_chain(xfer); 3072 3073 xhci_device_generic_multi_enter(xfer->endpoint, 3074 xfer->stream_id, xfer); 3075 } 3076 3077 static void 3078 xhci_device_generic_start(struct usb_xfer *xfer) 3079 { 3080 DPRINTF("\n"); 3081 3082 /* try to insert xfer on HW queue */ 3083 xhci_transfer_insert(xfer); 3084 3085 /* try to multi buffer */ 3086 xhci_device_generic_multi_enter(xfer->endpoint, 3087 xfer->stream_id, NULL); 3088 3089 /* add transfer last on interrupt queue */ 3090 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3091 3092 /* start timeout, if any */ 3093 if (xfer->timeout != 0) 3094 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3095 } 3096 3097 static const struct usb_pipe_methods xhci_device_generic_methods = 3098 { 3099 .open = xhci_device_generic_open, 3100 .close = xhci_device_generic_close, 3101 .enter = xhci_device_generic_enter, 3102 .start = xhci_device_generic_start, 3103 }; 3104 3105 /*------------------------------------------------------------------------* 3106 * xhci root HUB support 3107 *------------------------------------------------------------------------* 3108 * Simulate a hardware HUB by handling all the necessary requests. 3109 *------------------------------------------------------------------------*/ 3110 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3111 3112 static const 3113 struct usb_device_descriptor xhci_devd = 3114 { 3115 .bLength = sizeof(xhci_devd), 3116 .bDescriptorType = UDESC_DEVICE, /* type */ 3117 HSETW(.bcdUSB, 0x0300), /* USB version */ 3118 .bDeviceClass = UDCLASS_HUB, /* class */ 3119 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3120 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3121 .bMaxPacketSize = 9, /* max packet size */ 3122 HSETW(.idVendor, 0x0000), /* vendor */ 3123 HSETW(.idProduct, 0x0000), /* product */ 3124 HSETW(.bcdDevice, 0x0100), /* device version */ 3125 .iManufacturer = 1, 3126 .iProduct = 2, 3127 .iSerialNumber = 0, 3128 .bNumConfigurations = 1, /* # of configurations */ 3129 }; 3130 3131 static const 3132 struct xhci_bos_desc xhci_bosd = { 3133 .bosd = { 3134 .bLength = sizeof(xhci_bosd.bosd), 3135 .bDescriptorType = UDESC_BOS, 3136 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3137 .bNumDeviceCaps = 3, 3138 }, 3139 .usb2extd = { 3140 .bLength = sizeof(xhci_bosd.usb2extd), 3141 .bDescriptorType = 1, 3142 .bDevCapabilityType = 2, 3143 .bmAttributes[0] = 2, 3144 }, 3145 .usbdcd = { 3146 .bLength = sizeof(xhci_bosd.usbdcd), 3147 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3148 .bDevCapabilityType = 3, 3149 .bmAttributes = 0, /* XXX */ 3150 HSETW(.wSpeedsSupported, 0x000C), 3151 .bFunctionalitySupport = 8, 3152 .bU1DevExitLat = 255, /* dummy - not used */ 3153 .wU2DevExitLat = { 0x00, 0x08 }, 3154 }, 3155 .cidd = { 3156 .bLength = sizeof(xhci_bosd.cidd), 3157 .bDescriptorType = 1, 3158 .bDevCapabilityType = 4, 3159 .bReserved = 0, 3160 .bContainerID = 0, /* XXX */ 3161 }, 3162 }; 3163 3164 static const 3165 struct xhci_config_desc xhci_confd = { 3166 .confd = { 3167 .bLength = sizeof(xhci_confd.confd), 3168 .bDescriptorType = UDESC_CONFIG, 3169 .wTotalLength[0] = sizeof(xhci_confd), 3170 .bNumInterface = 1, 3171 .bConfigurationValue = 1, 3172 .iConfiguration = 0, 3173 .bmAttributes = UC_SELF_POWERED, 3174 .bMaxPower = 0 /* max power */ 3175 }, 3176 .ifcd = { 3177 .bLength = sizeof(xhci_confd.ifcd), 3178 .bDescriptorType = UDESC_INTERFACE, 3179 .bNumEndpoints = 1, 3180 .bInterfaceClass = UICLASS_HUB, 3181 .bInterfaceSubClass = UISUBCLASS_HUB, 3182 .bInterfaceProtocol = 0, 3183 }, 3184 .endpd = { 3185 .bLength = sizeof(xhci_confd.endpd), 3186 .bDescriptorType = UDESC_ENDPOINT, 3187 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3188 .bmAttributes = UE_INTERRUPT, 3189 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3190 .bInterval = 255, 3191 }, 3192 .endpcd = { 3193 .bLength = sizeof(xhci_confd.endpcd), 3194 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3195 .bMaxBurst = 0, 3196 .bmAttributes = 0, 3197 }, 3198 }; 3199 3200 static const 3201 struct usb_hub_ss_descriptor xhci_hubd = { 3202 .bLength = sizeof(xhci_hubd), 3203 .bDescriptorType = UDESC_SS_HUB, 3204 }; 3205 3206 static usb_error_t 3207 xhci_roothub_exec(struct usb_device *udev, 3208 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3209 { 3210 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3211 const char *str_ptr; 3212 const void *ptr; 3213 uint32_t port; 3214 uint32_t v; 3215 uint16_t len; 3216 uint16_t i; 3217 uint16_t value; 3218 uint16_t index; 3219 uint8_t j; 3220 usb_error_t err; 3221 3222 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3223 3224 /* buffer reset */ 3225 ptr = (const void *)&sc->sc_hub_desc; 3226 len = 0; 3227 err = 0; 3228 3229 value = UGETW(req->wValue); 3230 index = UGETW(req->wIndex); 3231 3232 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3233 "wValue=0x%04x wIndex=0x%04x\n", 3234 req->bmRequestType, req->bRequest, 3235 UGETW(req->wLength), value, index); 3236 3237 #define C(x,y) ((x) | ((y) << 8)) 3238 switch (C(req->bRequest, req->bmRequestType)) { 3239 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3240 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3241 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3242 /* 3243 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3244 * for the integrated root hub. 3245 */ 3246 break; 3247 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3248 len = 1; 3249 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3250 break; 3251 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3252 switch (value >> 8) { 3253 case UDESC_DEVICE: 3254 if ((value & 0xff) != 0) { 3255 err = USB_ERR_IOERROR; 3256 goto done; 3257 } 3258 len = sizeof(xhci_devd); 3259 ptr = (const void *)&xhci_devd; 3260 break; 3261 3262 case UDESC_BOS: 3263 if ((value & 0xff) != 0) { 3264 err = USB_ERR_IOERROR; 3265 goto done; 3266 } 3267 len = sizeof(xhci_bosd); 3268 ptr = (const void *)&xhci_bosd; 3269 break; 3270 3271 case UDESC_CONFIG: 3272 if ((value & 0xff) != 0) { 3273 err = USB_ERR_IOERROR; 3274 goto done; 3275 } 3276 len = sizeof(xhci_confd); 3277 ptr = (const void *)&xhci_confd; 3278 break; 3279 3280 case UDESC_STRING: 3281 switch (value & 0xff) { 3282 case 0: /* Language table */ 3283 str_ptr = "\001"; 3284 break; 3285 3286 case 1: /* Vendor */ 3287 str_ptr = sc->sc_vendor; 3288 break; 3289 3290 case 2: /* Product */ 3291 str_ptr = "XHCI root HUB"; 3292 break; 3293 3294 default: 3295 str_ptr = ""; 3296 break; 3297 } 3298 3299 len = usb_make_str_desc( 3300 sc->sc_hub_desc.temp, 3301 sizeof(sc->sc_hub_desc.temp), 3302 str_ptr); 3303 break; 3304 3305 default: 3306 err = USB_ERR_IOERROR; 3307 goto done; 3308 } 3309 break; 3310 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3311 len = 1; 3312 sc->sc_hub_desc.temp[0] = 0; 3313 break; 3314 case C(UR_GET_STATUS, UT_READ_DEVICE): 3315 len = 2; 3316 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3317 break; 3318 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3319 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3320 len = 2; 3321 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3322 break; 3323 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3324 if (value >= XHCI_MAX_DEVICES) { 3325 err = USB_ERR_IOERROR; 3326 goto done; 3327 } 3328 break; 3329 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3330 if (value != 0 && value != 1) { 3331 err = USB_ERR_IOERROR; 3332 goto done; 3333 } 3334 sc->sc_conf = value; 3335 break; 3336 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3337 break; 3338 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3339 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3340 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3341 err = USB_ERR_IOERROR; 3342 goto done; 3343 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3344 break; 3345 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3346 break; 3347 /* Hub requests */ 3348 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3349 break; 3350 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3351 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3352 3353 if ((index < 1) || 3354 (index > sc->sc_noport)) { 3355 err = USB_ERR_IOERROR; 3356 goto done; 3357 } 3358 port = XHCI_PORTSC(index); 3359 3360 v = XREAD4(sc, oper, port); 3361 i = XHCI_PS_PLS_GET(v); 3362 v &= ~XHCI_PS_CLEAR; 3363 3364 switch (value) { 3365 case UHF_C_BH_PORT_RESET: 3366 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3367 break; 3368 case UHF_C_PORT_CONFIG_ERROR: 3369 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3370 break; 3371 case UHF_C_PORT_SUSPEND: 3372 case UHF_C_PORT_LINK_STATE: 3373 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3374 break; 3375 case UHF_C_PORT_CONNECTION: 3376 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3377 break; 3378 case UHF_C_PORT_ENABLE: 3379 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3380 break; 3381 case UHF_C_PORT_OVER_CURRENT: 3382 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3383 break; 3384 case UHF_C_PORT_RESET: 3385 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3386 break; 3387 case UHF_PORT_ENABLE: 3388 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3389 break; 3390 case UHF_PORT_POWER: 3391 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3392 break; 3393 case UHF_PORT_INDICATOR: 3394 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3395 break; 3396 case UHF_PORT_SUSPEND: 3397 3398 /* U3 -> U15 */ 3399 if (i == 3) { 3400 XWRITE4(sc, oper, port, v | 3401 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3402 } 3403 3404 /* wait 20ms for resume sequence to complete */ 3405 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3406 3407 /* U0 */ 3408 XWRITE4(sc, oper, port, v | 3409 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3410 break; 3411 default: 3412 err = USB_ERR_IOERROR; 3413 goto done; 3414 } 3415 break; 3416 3417 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3418 if ((value & 0xff) != 0) { 3419 err = USB_ERR_IOERROR; 3420 goto done; 3421 } 3422 3423 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3424 3425 sc->sc_hub_desc.hubd = xhci_hubd; 3426 3427 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3428 3429 if (XHCI_HCS0_PPC(v)) 3430 i = UHD_PWR_INDIVIDUAL; 3431 else 3432 i = UHD_PWR_GANGED; 3433 3434 if (XHCI_HCS0_PIND(v)) 3435 i |= UHD_PORT_IND; 3436 3437 i |= UHD_OC_INDIVIDUAL; 3438 3439 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3440 3441 /* see XHCI section 5.4.9: */ 3442 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3443 3444 for (j = 1; j <= sc->sc_noport; j++) { 3445 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3446 if (v & XHCI_PS_DR) { 3447 sc->sc_hub_desc.hubd. 3448 DeviceRemovable[j / 8] |= 1U << (j % 8); 3449 } 3450 } 3451 len = sc->sc_hub_desc.hubd.bLength; 3452 break; 3453 3454 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3455 len = 16; 3456 memset(sc->sc_hub_desc.temp, 0, 16); 3457 break; 3458 3459 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3460 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3461 3462 if ((index < 1) || 3463 (index > sc->sc_noport)) { 3464 err = USB_ERR_IOERROR; 3465 goto done; 3466 } 3467 3468 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3469 3470 DPRINTFN(9, "port status=0x%08x\n", v); 3471 3472 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3473 3474 switch (XHCI_PS_SPEED_GET(v)) { 3475 case 3: 3476 i |= UPS_HIGH_SPEED; 3477 break; 3478 case 2: 3479 i |= UPS_LOW_SPEED; 3480 break; 3481 case 1: 3482 /* FULL speed */ 3483 break; 3484 default: 3485 i |= UPS_OTHER_SPEED; 3486 break; 3487 } 3488 3489 if (v & XHCI_PS_CCS) 3490 i |= UPS_CURRENT_CONNECT_STATUS; 3491 if (v & XHCI_PS_PED) 3492 i |= UPS_PORT_ENABLED; 3493 if (v & XHCI_PS_OCA) 3494 i |= UPS_OVERCURRENT_INDICATOR; 3495 if (v & XHCI_PS_PR) 3496 i |= UPS_RESET; 3497 #if 0 3498 if (v & XHCI_PS_PP) 3499 /* XXX undefined */ 3500 #endif 3501 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3502 3503 i = 0; 3504 if (v & XHCI_PS_CSC) 3505 i |= UPS_C_CONNECT_STATUS; 3506 if (v & XHCI_PS_PEC) 3507 i |= UPS_C_PORT_ENABLED; 3508 if (v & XHCI_PS_OCC) 3509 i |= UPS_C_OVERCURRENT_INDICATOR; 3510 if (v & XHCI_PS_WRC) 3511 i |= UPS_C_BH_PORT_RESET; 3512 if (v & XHCI_PS_PRC) 3513 i |= UPS_C_PORT_RESET; 3514 if (v & XHCI_PS_PLC) 3515 i |= UPS_C_PORT_LINK_STATE; 3516 if (v & XHCI_PS_CEC) 3517 i |= UPS_C_PORT_CONFIG_ERROR; 3518 3519 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3520 len = sizeof(sc->sc_hub_desc.ps); 3521 break; 3522 3523 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3524 err = USB_ERR_IOERROR; 3525 goto done; 3526 3527 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3528 break; 3529 3530 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3531 3532 i = index >> 8; 3533 index &= 0x00FF; 3534 3535 if ((index < 1) || 3536 (index > sc->sc_noport)) { 3537 err = USB_ERR_IOERROR; 3538 goto done; 3539 } 3540 3541 port = XHCI_PORTSC(index); 3542 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3543 3544 switch (value) { 3545 case UHF_PORT_U1_TIMEOUT: 3546 if (XHCI_PS_SPEED_GET(v) != 4) { 3547 err = USB_ERR_IOERROR; 3548 goto done; 3549 } 3550 port = XHCI_PORTPMSC(index); 3551 v = XREAD4(sc, oper, port); 3552 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3553 v |= XHCI_PM3_U1TO_SET(i); 3554 XWRITE4(sc, oper, port, v); 3555 break; 3556 case UHF_PORT_U2_TIMEOUT: 3557 if (XHCI_PS_SPEED_GET(v) != 4) { 3558 err = USB_ERR_IOERROR; 3559 goto done; 3560 } 3561 port = XHCI_PORTPMSC(index); 3562 v = XREAD4(sc, oper, port); 3563 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3564 v |= XHCI_PM3_U2TO_SET(i); 3565 XWRITE4(sc, oper, port, v); 3566 break; 3567 case UHF_BH_PORT_RESET: 3568 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3569 break; 3570 case UHF_PORT_LINK_STATE: 3571 XWRITE4(sc, oper, port, v | 3572 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3573 /* 4ms settle time */ 3574 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3575 break; 3576 case UHF_PORT_ENABLE: 3577 DPRINTFN(3, "set port enable %d\n", index); 3578 break; 3579 case UHF_PORT_SUSPEND: 3580 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3581 j = XHCI_PS_SPEED_GET(v); 3582 if ((j < 1) || (j > 3)) { 3583 /* non-supported speed */ 3584 err = USB_ERR_IOERROR; 3585 goto done; 3586 } 3587 XWRITE4(sc, oper, port, v | 3588 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3589 break; 3590 case UHF_PORT_RESET: 3591 DPRINTFN(6, "reset port %d\n", index); 3592 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3593 break; 3594 case UHF_PORT_POWER: 3595 DPRINTFN(3, "set port power %d\n", index); 3596 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3597 break; 3598 case UHF_PORT_TEST: 3599 DPRINTFN(3, "set port test %d\n", index); 3600 break; 3601 case UHF_PORT_INDICATOR: 3602 DPRINTFN(3, "set port indicator %d\n", index); 3603 3604 v &= ~XHCI_PS_PIC_SET(3); 3605 v |= XHCI_PS_PIC_SET(1); 3606 3607 XWRITE4(sc, oper, port, v); 3608 break; 3609 default: 3610 err = USB_ERR_IOERROR; 3611 goto done; 3612 } 3613 break; 3614 3615 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3616 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3617 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3618 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3619 break; 3620 default: 3621 err = USB_ERR_IOERROR; 3622 goto done; 3623 } 3624 done: 3625 *plength = len; 3626 *pptr = ptr; 3627 return (err); 3628 } 3629 3630 static void 3631 xhci_xfer_setup(struct usb_setup_params *parm) 3632 { 3633 struct usb_page_search page_info; 3634 struct usb_page_cache *pc; 3635 struct usb_xfer *xfer; 3636 void *last_obj; 3637 uint32_t ntd; 3638 uint32_t n; 3639 3640 xfer = parm->curr_xfer; 3641 3642 /* 3643 * The proof for the "ntd" formula is illustrated like this: 3644 * 3645 * +------------------------------------+ 3646 * | | 3647 * | |remainder -> | 3648 * | +-----+---+ | 3649 * | | xxx | x | frm 0 | 3650 * | +-----+---++ | 3651 * | | xxx | xx | frm 1 | 3652 * | +-----+----+ | 3653 * | ... | 3654 * +------------------------------------+ 3655 * 3656 * "xxx" means a completely full USB transfer descriptor 3657 * 3658 * "x" and "xx" means a short USB packet 3659 * 3660 * For the remainder of an USB transfer modulo 3661 * "max_data_length" we need two USB transfer descriptors. 3662 * One to transfer the remaining data and one to finalise with 3663 * a zero length packet in case the "force_short_xfer" flag is 3664 * set. We only need two USB transfer descriptors in the case 3665 * where the transfer length of the first one is a factor of 3666 * "max_frame_size". The rest of the needed USB transfer 3667 * descriptors is given by the buffer size divided by the 3668 * maximum data payload. 3669 */ 3670 parm->hc_max_packet_size = 0x400; 3671 parm->hc_max_packet_count = 16 * 3; 3672 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3673 3674 xfer->flags_int.bdma_enable = 1; 3675 3676 usbd_transfer_setup_sub(parm); 3677 3678 if (xfer->flags_int.isochronous_xfr) { 3679 ntd = ((1 * xfer->nframes) 3680 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3681 } else if (xfer->flags_int.control_xfr) { 3682 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3683 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3684 } else { 3685 ntd = ((2 * xfer->nframes) 3686 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3687 } 3688 3689 alloc_dma_set: 3690 3691 if (parm->err) 3692 return; 3693 3694 /* 3695 * Allocate queue heads and transfer descriptors 3696 */ 3697 last_obj = NULL; 3698 3699 if (usbd_transfer_setup_sub_malloc( 3700 parm, &pc, sizeof(struct xhci_td), 3701 XHCI_TD_ALIGN, ntd)) { 3702 parm->err = USB_ERR_NOMEM; 3703 return; 3704 } 3705 if (parm->buf) { 3706 for (n = 0; n != ntd; n++) { 3707 struct xhci_td *td; 3708 3709 usbd_get_page(pc + n, 0, &page_info); 3710 3711 td = page_info.buffer; 3712 3713 /* init TD */ 3714 td->td_self = page_info.physaddr; 3715 td->obj_next = last_obj; 3716 td->page_cache = pc + n; 3717 3718 last_obj = td; 3719 3720 usb_pc_cpu_flush(pc + n); 3721 } 3722 } 3723 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3724 3725 if (!xfer->flags_int.curr_dma_set) { 3726 xfer->flags_int.curr_dma_set = 1; 3727 goto alloc_dma_set; 3728 } 3729 } 3730 3731 static uint8_t 3732 xhci_get_endpoint_state(struct usb_device *udev, uint8_t epno) 3733 { 3734 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3735 struct usb_page_search buf_dev; 3736 struct xhci_hw_dev *hdev; 3737 struct xhci_endp_ctx *endp; 3738 uint32_t temp; 3739 3740 MPASS(epno != 0); 3741 3742 hdev = &sc->sc_hw.devs[udev->controller_slot_id]; 3743 3744 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 3745 endp = XHCI_GET_CTX(sc, xhci_dev_ctx, ctx_ep[epno - 1], 3746 buf_dev.buffer); 3747 usb_pc_cpu_invalidate(&hdev->device_pc); 3748 3749 temp = le32toh(endp->dwEpCtx0); 3750 3751 return (XHCI_EPCTX_0_EPSTATE_GET(temp)); 3752 } 3753 3754 static usb_error_t 3755 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3756 { 3757 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3758 struct usb_page_search buf_inp; 3759 struct usb_device *udev; 3760 struct xhci_endpoint_ext *pepext; 3761 struct usb_endpoint_descriptor *edesc; 3762 struct usb_page_cache *pcinp; 3763 usb_error_t err; 3764 usb_stream_t stream_id; 3765 uint32_t mask; 3766 uint8_t index; 3767 uint8_t epno; 3768 3769 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3770 xfer->endpoint->edesc); 3771 3772 udev = xfer->xroot->udev; 3773 index = udev->controller_slot_id; 3774 3775 pcinp = &sc->sc_hw.devs[index].input_pc; 3776 3777 usbd_get_page(pcinp, 0, &buf_inp); 3778 3779 edesc = xfer->endpoint->edesc; 3780 3781 epno = edesc->bEndpointAddress; 3782 stream_id = xfer->stream_id; 3783 3784 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3785 epno |= UE_DIR_IN; 3786 3787 epno = XHCI_EPNO2EPID(epno); 3788 3789 if (epno == 0) 3790 return (USB_ERR_NO_PIPE); /* invalid */ 3791 3792 XHCI_CMD_LOCK(sc); 3793 3794 /* configure endpoint */ 3795 3796 err = xhci_configure_endpoint_by_xfer(xfer); 3797 3798 if (err != 0) { 3799 XHCI_CMD_UNLOCK(sc); 3800 return (err); 3801 } 3802 3803 /* 3804 * Get the endpoint into the stopped state according to the 3805 * endpoint context state diagram in the XHCI specification: 3806 */ 3807 switch (xhci_get_endpoint_state(udev, epno)) { 3808 case XHCI_EPCTX_0_EPSTATE_DISABLED: 3809 break; 3810 case XHCI_EPCTX_0_EPSTATE_STOPPED: 3811 break; 3812 case XHCI_EPCTX_0_EPSTATE_HALTED: 3813 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3814 if (err != 0) 3815 DPRINTF("Could not reset endpoint %u\n", epno); 3816 break; 3817 default: 3818 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3819 if (err != 0) 3820 DPRINTF("Could not stop endpoint %u\n", epno); 3821 break; 3822 } 3823 3824 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3825 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3826 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3827 stream_id, epno, index); 3828 3829 if (err != 0) 3830 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3831 3832 /* 3833 * Get the endpoint into the running state according to the 3834 * endpoint context state diagram in the XHCI specification: 3835 */ 3836 3837 mask = (1U << epno); 3838 xhci_configure_mask(udev, mask | 1U, 0); 3839 3840 if (!(sc->sc_hw.devs[index].ep_configured & mask)) { 3841 sc->sc_hw.devs[index].ep_configured |= mask; 3842 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3843 } else { 3844 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3845 } 3846 3847 if (err != 0) { 3848 DPRINTF("Could not configure " 3849 "endpoint %u at slot %u.\n", epno, index); 3850 } 3851 XHCI_CMD_UNLOCK(sc); 3852 3853 return (0); 3854 } 3855 3856 static void 3857 xhci_xfer_unsetup(struct usb_xfer *xfer) 3858 { 3859 return; 3860 } 3861 3862 static void 3863 xhci_start_dma_delay(struct usb_xfer *xfer) 3864 { 3865 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3866 3867 /* put transfer on interrupt queue (again) */ 3868 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3869 3870 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3871 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3872 } 3873 3874 static void 3875 xhci_configure_msg(struct usb_proc_msg *pm) 3876 { 3877 struct xhci_softc *sc; 3878 struct xhci_endpoint_ext *pepext; 3879 struct usb_xfer *xfer; 3880 3881 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3882 3883 restart: 3884 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3885 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3886 xfer->endpoint->edesc); 3887 3888 if ((pepext->trb_halted != 0) || 3889 (pepext->trb_running == 0)) { 3890 uint16_t i; 3891 3892 /* clear halted and running */ 3893 pepext->trb_halted = 0; 3894 pepext->trb_running = 0; 3895 3896 /* nuke remaining buffered transfers */ 3897 3898 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3899 XHCI_MAX_STREAMS); i++) { 3900 /* 3901 * NOTE: We need to use the timeout 3902 * error code here else existing 3903 * isochronous clients can get 3904 * confused: 3905 */ 3906 if (pepext->xfer[i] != NULL) { 3907 xhci_device_done(pepext->xfer[i], 3908 USB_ERR_TIMEOUT); 3909 } 3910 } 3911 3912 /* 3913 * NOTE: The USB transfer cannot vanish in 3914 * this state! 3915 */ 3916 3917 USB_BUS_UNLOCK(&sc->sc_bus); 3918 3919 xhci_configure_reset_endpoint(xfer); 3920 3921 USB_BUS_LOCK(&sc->sc_bus); 3922 3923 /* check if halted is still cleared */ 3924 if (pepext->trb_halted == 0) { 3925 pepext->trb_running = 1; 3926 memset(pepext->trb_index, 0, 3927 sizeof(pepext->trb_index)); 3928 } 3929 goto restart; 3930 } 3931 3932 if (xfer->flags_int.did_dma_delay) { 3933 /* remove transfer from interrupt queue (again) */ 3934 usbd_transfer_dequeue(xfer); 3935 3936 /* we are finally done */ 3937 usb_dma_delay_done_cb(xfer); 3938 3939 /* queue changed - restart */ 3940 goto restart; 3941 } 3942 } 3943 3944 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3945 /* try to insert xfer on HW queue */ 3946 xhci_transfer_insert(xfer); 3947 3948 /* try to multi buffer */ 3949 xhci_device_generic_multi_enter(xfer->endpoint, 3950 xfer->stream_id, NULL); 3951 } 3952 } 3953 3954 static void 3955 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3956 struct usb_endpoint *ep) 3957 { 3958 struct xhci_endpoint_ext *pepext; 3959 struct xhci_softc *sc; 3960 uint8_t index; 3961 uint8_t epno; 3962 3963 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3964 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3965 3966 if (udev->parent_hub == NULL) { 3967 /* root HUB has special endpoint handling */ 3968 return; 3969 } 3970 3971 ep->methods = &xhci_device_generic_methods; 3972 3973 pepext = xhci_get_endpoint_ext(udev, edesc); 3974 3975 USB_BUS_LOCK(udev->bus); 3976 pepext->trb_halted = 1; 3977 pepext->trb_running = 0; 3978 3979 /* 3980 * When doing an alternate setting, except for control 3981 * endpoints, we need to re-configure the XHCI endpoint 3982 * context: 3983 */ 3984 if ((edesc->bEndpointAddress & UE_ADDR) != 0) { 3985 sc = XHCI_BUS2SC(udev->bus); 3986 index = udev->controller_slot_id; 3987 epno = XHCI_EPNO2EPID(edesc->bEndpointAddress); 3988 sc->sc_hw.devs[index].ep_configured &= ~(1U << epno); 3989 } 3990 USB_BUS_UNLOCK(udev->bus); 3991 } 3992 3993 static void 3994 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3995 { 3996 3997 } 3998 3999 static void 4000 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 4001 { 4002 struct xhci_endpoint_ext *pepext; 4003 4004 DPRINTF("\n"); 4005 4006 if (udev->flags.usb_mode != USB_MODE_HOST) { 4007 /* not supported */ 4008 return; 4009 } 4010 if (udev->parent_hub == NULL) { 4011 /* root HUB has special endpoint handling */ 4012 return; 4013 } 4014 4015 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 4016 4017 USB_BUS_LOCK(udev->bus); 4018 pepext->trb_halted = 1; 4019 pepext->trb_running = 0; 4020 USB_BUS_UNLOCK(udev->bus); 4021 } 4022 4023 static usb_error_t 4024 xhci_device_init(struct usb_device *udev) 4025 { 4026 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4027 usb_error_t err; 4028 uint8_t temp; 4029 4030 /* no init for root HUB */ 4031 if (udev->parent_hub == NULL) 4032 return (0); 4033 4034 XHCI_CMD_LOCK(sc); 4035 4036 /* set invalid default */ 4037 4038 udev->controller_slot_id = sc->sc_noslot + 1; 4039 4040 /* try to get a new slot ID from the XHCI */ 4041 4042 err = xhci_cmd_enable_slot(sc, &temp); 4043 4044 if (err) { 4045 XHCI_CMD_UNLOCK(sc); 4046 return (err); 4047 } 4048 4049 if (temp > sc->sc_noslot) { 4050 XHCI_CMD_UNLOCK(sc); 4051 return (USB_ERR_BAD_ADDRESS); 4052 } 4053 4054 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4055 DPRINTF("slot %u already allocated.\n", temp); 4056 XHCI_CMD_UNLOCK(sc); 4057 return (USB_ERR_BAD_ADDRESS); 4058 } 4059 4060 /* store slot ID for later reference */ 4061 4062 udev->controller_slot_id = temp; 4063 4064 /* reset data structure */ 4065 4066 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4067 4068 /* set mark slot allocated */ 4069 4070 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4071 4072 err = xhci_alloc_device_ext(udev); 4073 4074 XHCI_CMD_UNLOCK(sc); 4075 4076 /* get device into default state */ 4077 4078 if (err == 0) 4079 err = xhci_set_address(udev, NULL, 0); 4080 4081 return (err); 4082 } 4083 4084 static void 4085 xhci_device_uninit(struct usb_device *udev) 4086 { 4087 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4088 uint8_t index; 4089 4090 /* no init for root HUB */ 4091 if (udev->parent_hub == NULL) 4092 return; 4093 4094 XHCI_CMD_LOCK(sc); 4095 4096 index = udev->controller_slot_id; 4097 4098 if (index <= sc->sc_noslot) { 4099 xhci_cmd_disable_slot(sc, index); 4100 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4101 4102 /* free device extension */ 4103 xhci_free_device_ext(udev); 4104 } 4105 4106 XHCI_CMD_UNLOCK(sc); 4107 } 4108 4109 static void 4110 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4111 { 4112 /* 4113 * Wait until the hardware has finished any possible use of 4114 * the transfer descriptor(s) 4115 */ 4116 *pus = 2048; /* microseconds */ 4117 } 4118 4119 static void 4120 xhci_device_resume(struct usb_device *udev) 4121 { 4122 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4123 uint8_t index; 4124 uint8_t n; 4125 uint8_t p; 4126 4127 DPRINTF("\n"); 4128 4129 /* check for root HUB */ 4130 if (udev->parent_hub == NULL) 4131 return; 4132 4133 index = udev->controller_slot_id; 4134 4135 XHCI_CMD_LOCK(sc); 4136 4137 /* blindly resume all endpoints */ 4138 4139 USB_BUS_LOCK(udev->bus); 4140 4141 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4142 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4143 XWRITE4(sc, door, XHCI_DOORBELL(index), 4144 n | XHCI_DB_SID_SET(p)); 4145 } 4146 } 4147 4148 USB_BUS_UNLOCK(udev->bus); 4149 4150 XHCI_CMD_UNLOCK(sc); 4151 } 4152 4153 static void 4154 xhci_device_suspend(struct usb_device *udev) 4155 { 4156 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4157 uint8_t index; 4158 uint8_t n; 4159 usb_error_t err; 4160 4161 DPRINTF("\n"); 4162 4163 /* check for root HUB */ 4164 if (udev->parent_hub == NULL) 4165 return; 4166 4167 index = udev->controller_slot_id; 4168 4169 XHCI_CMD_LOCK(sc); 4170 4171 /* blindly suspend all endpoints */ 4172 4173 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4174 err = xhci_cmd_stop_ep(sc, 1, n, index); 4175 if (err != 0) { 4176 DPRINTF("Failed to suspend endpoint " 4177 "%u on slot %u (ignored).\n", n, index); 4178 } 4179 } 4180 4181 XHCI_CMD_UNLOCK(sc); 4182 } 4183 4184 static void 4185 xhci_set_hw_power(struct usb_bus *bus) 4186 { 4187 DPRINTF("\n"); 4188 } 4189 4190 static void 4191 xhci_device_state_change(struct usb_device *udev) 4192 { 4193 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4194 struct usb_page_search buf_inp; 4195 usb_error_t err; 4196 uint8_t index; 4197 4198 /* check for root HUB */ 4199 if (udev->parent_hub == NULL) 4200 return; 4201 4202 index = udev->controller_slot_id; 4203 4204 DPRINTF("\n"); 4205 4206 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4207 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4208 &sc->sc_hw.devs[index].tt); 4209 if (err != 0) 4210 sc->sc_hw.devs[index].nports = 0; 4211 } 4212 4213 XHCI_CMD_LOCK(sc); 4214 4215 switch (usb_get_device_state(udev)) { 4216 case USB_STATE_POWERED: 4217 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4218 break; 4219 4220 /* set default state */ 4221 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4222 sc->sc_hw.devs[index].ep_configured = 3U; 4223 4224 /* reset number of contexts */ 4225 sc->sc_hw.devs[index].context_num = 0; 4226 4227 err = xhci_cmd_reset_dev(sc, index); 4228 4229 if (err != 0) { 4230 DPRINTF("Device reset failed " 4231 "for slot %u.\n", index); 4232 } 4233 break; 4234 4235 case USB_STATE_ADDRESSED: 4236 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4237 break; 4238 4239 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4240 sc->sc_hw.devs[index].ep_configured = 3U; 4241 4242 /* set configure mask to slot only */ 4243 xhci_configure_mask(udev, 1, 0); 4244 4245 /* deconfigure all endpoints, except EP0 */ 4246 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4247 4248 if (err) { 4249 DPRINTF("Failed to deconfigure " 4250 "slot %u.\n", index); 4251 } 4252 break; 4253 4254 case USB_STATE_CONFIGURED: 4255 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) { 4256 /* deconfigure all endpoints, except EP0 */ 4257 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4258 4259 if (err) { 4260 DPRINTF("Failed to deconfigure " 4261 "slot %u.\n", index); 4262 } 4263 } 4264 4265 /* set configured state */ 4266 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4267 sc->sc_hw.devs[index].ep_configured = 3U; 4268 4269 /* reset number of contexts */ 4270 sc->sc_hw.devs[index].context_num = 0; 4271 4272 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4273 4274 xhci_configure_mask(udev, 3, 0); 4275 4276 err = xhci_configure_device(udev); 4277 if (err != 0) { 4278 DPRINTF("Could not configure device " 4279 "at slot %u.\n", index); 4280 } 4281 4282 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4283 if (err != 0) { 4284 DPRINTF("Could not evaluate device " 4285 "context at slot %u.\n", index); 4286 } 4287 break; 4288 4289 default: 4290 break; 4291 } 4292 XHCI_CMD_UNLOCK(sc); 4293 } 4294 4295 static usb_error_t 4296 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4297 uint8_t ep_mode) 4298 { 4299 switch (ep_mode) { 4300 case USB_EP_MODE_DEFAULT: 4301 return (0); 4302 case USB_EP_MODE_STREAMS: 4303 if (xhcistreams == 0 || 4304 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4305 udev->speed != USB_SPEED_SUPER) 4306 return (USB_ERR_INVAL); 4307 return (0); 4308 default: 4309 return (USB_ERR_INVAL); 4310 } 4311 } 4312 4313 static const struct usb_bus_methods xhci_bus_methods = { 4314 .endpoint_init = xhci_ep_init, 4315 .endpoint_uninit = xhci_ep_uninit, 4316 .xfer_setup = xhci_xfer_setup, 4317 .xfer_unsetup = xhci_xfer_unsetup, 4318 .get_dma_delay = xhci_get_dma_delay, 4319 .device_init = xhci_device_init, 4320 .device_uninit = xhci_device_uninit, 4321 .device_resume = xhci_device_resume, 4322 .device_suspend = xhci_device_suspend, 4323 .set_hw_power = xhci_set_hw_power, 4324 .roothub_exec = xhci_roothub_exec, 4325 .xfer_poll = xhci_do_poll, 4326 .start_dma_delay = xhci_start_dma_delay, 4327 .set_address = xhci_set_address, 4328 .clear_stall = xhci_ep_clear_stall, 4329 .device_state_change = xhci_device_state_change, 4330 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4331 .set_endpoint_mode = xhci_set_endpoint_mode, 4332 }; 4333