1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36 /* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43 #ifdef USB_GLOBAL_INCLUDE_FILE 44 #include USB_GLOBAL_INCLUDE_FILE 45 #else 46 #include <sys/stdint.h> 47 #include <sys/stddef.h> 48 #include <sys/param.h> 49 #include <sys/queue.h> 50 #include <sys/types.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/bus.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/condvar.h> 58 #include <sys/sysctl.h> 59 #include <sys/sx.h> 60 #include <sys/unistd.h> 61 #include <sys/callout.h> 62 #include <sys/malloc.h> 63 #include <sys/priv.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 68 #define USB_DEBUG_VAR xhcidebug 69 70 #include <dev/usb/usb_core.h> 71 #include <dev/usb/usb_debug.h> 72 #include <dev/usb/usb_busdma.h> 73 #include <dev/usb/usb_process.h> 74 #include <dev/usb/usb_transfer.h> 75 #include <dev/usb/usb_device.h> 76 #include <dev/usb/usb_hub.h> 77 #include <dev/usb/usb_util.h> 78 79 #include <dev/usb/usb_controller.h> 80 #include <dev/usb/usb_bus.h> 81 #endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83 #include <dev/usb/controller/xhci.h> 84 #include <dev/usb/controller/xhcireg.h> 85 86 #define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 92 static int xhcistreams; 93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN, 94 &xhcistreams, 0, "Set to enable streams mode support"); 95 96 #ifdef USB_DEBUG 97 static int xhcidebug; 98 static int xhciroute; 99 static int xhcipolling; 100 101 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN, 102 &xhcidebug, 0, "Debug level"); 103 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN, 104 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN, 106 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller"); 107 #else 108 #define xhciroute 0 109 #endif 110 111 #define XHCI_INTR_ENDPT 1 112 113 struct xhci_std_temp { 114 struct xhci_softc *sc; 115 struct usb_page_cache *pc; 116 struct xhci_td *td; 117 struct xhci_td *td_next; 118 uint32_t len; 119 uint32_t offset; 120 uint32_t max_packet_size; 121 uint32_t average; 122 uint16_t isoc_delta; 123 uint16_t isoc_frame; 124 uint8_t shortpkt; 125 uint8_t multishort; 126 uint8_t last_frame; 127 uint8_t trb_type; 128 uint8_t direction; 129 uint8_t tbc; 130 uint8_t tlbpc; 131 uint8_t step_td; 132 uint8_t do_isoc_sync; 133 }; 134 135 static void xhci_do_poll(struct usb_bus *); 136 static void xhci_device_done(struct usb_xfer *, usb_error_t); 137 static void xhci_root_intr(struct xhci_softc *); 138 static void xhci_free_device_ext(struct usb_device *); 139 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 140 struct usb_endpoint_descriptor *); 141 static usb_proc_callback_t xhci_configure_msg; 142 static usb_error_t xhci_configure_device(struct usb_device *); 143 static usb_error_t xhci_configure_endpoint(struct usb_device *, 144 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 145 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 146 uint8_t); 147 static usb_error_t xhci_configure_mask(struct usb_device *, 148 uint32_t, uint8_t); 149 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 150 uint64_t, uint8_t); 151 static void xhci_endpoint_doorbell(struct usb_xfer *); 152 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 153 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 154 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 155 #ifdef USB_DEBUG 156 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 157 #endif 158 159 static const struct usb_bus_methods xhci_bus_methods; 160 161 #ifdef USB_DEBUG 162 static void 163 xhci_dump_trb(struct xhci_trb *trb) 164 { 165 DPRINTFN(5, "trb = %p\n", trb); 166 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 167 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 168 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 169 } 170 171 static void 172 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 173 { 174 DPRINTFN(5, "pep = %p\n", pep); 175 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 176 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 177 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 178 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 179 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 180 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 181 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 182 } 183 184 static void 185 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 186 { 187 DPRINTFN(5, "psl = %p\n", psl); 188 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 189 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 190 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 191 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 192 } 193 #endif 194 195 uint8_t 196 xhci_use_polling(void) 197 { 198 #ifdef USB_DEBUG 199 return (xhcipolling != 0); 200 #else 201 return (0); 202 #endif 203 } 204 205 static void 206 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 207 { 208 struct xhci_softc *sc = XHCI_BUS2SC(bus); 209 uint8_t i; 210 211 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 212 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 213 214 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 215 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 216 217 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 218 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 219 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 220 } 221 } 222 223 static void 224 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 225 { 226 if (sc->sc_ctx_is_64_byte) { 227 uint32_t offset; 228 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 229 /* all contexts are initially 32-bytes */ 230 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 231 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 232 } 233 *ptr = htole32(val); 234 } 235 236 static uint32_t 237 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 238 { 239 if (sc->sc_ctx_is_64_byte) { 240 uint32_t offset; 241 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 242 /* all contexts are initially 32-bytes */ 243 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 244 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 245 } 246 return (le32toh(*ptr)); 247 } 248 249 static void 250 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 251 { 252 if (sc->sc_ctx_is_64_byte) { 253 uint32_t offset; 254 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 255 /* all contexts are initially 32-bytes */ 256 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 257 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 258 } 259 *ptr = htole64(val); 260 } 261 262 #ifdef USB_DEBUG 263 static uint64_t 264 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 265 { 266 if (sc->sc_ctx_is_64_byte) { 267 uint32_t offset; 268 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 269 /* all contexts are initially 32-bytes */ 270 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 271 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 272 } 273 return (le64toh(*ptr)); 274 } 275 #endif 276 277 static int 278 xhci_reset_command_queue_locked(struct xhci_softc *sc) 279 { 280 struct usb_page_search buf_res; 281 struct xhci_hw_root *phwr; 282 uint64_t addr; 283 uint32_t temp; 284 285 DPRINTF("\n"); 286 287 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 288 if (temp & XHCI_CRCR_LO_CRR) { 289 DPRINTF("Command ring running\n"); 290 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 291 292 /* 293 * Try to abort the last command as per section 294 * 4.6.1.2 "Aborting a Command" of the XHCI 295 * specification: 296 */ 297 298 /* stop and cancel */ 299 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 300 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 301 302 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 303 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 304 305 /* wait 250ms */ 306 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 307 308 /* check if command ring is still running */ 309 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 310 if (temp & XHCI_CRCR_LO_CRR) { 311 DPRINTF("Comand ring still running\n"); 312 return (USB_ERR_IOERROR); 313 } 314 } 315 316 /* reset command ring */ 317 sc->sc_command_ccs = 1; 318 sc->sc_command_idx = 0; 319 320 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 321 322 /* set up command ring control base address */ 323 addr = buf_res.physaddr; 324 phwr = buf_res.buffer; 325 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 326 327 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 328 329 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 330 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 331 332 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 333 334 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 335 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 336 337 return (0); 338 } 339 340 usb_error_t 341 xhci_start_controller(struct xhci_softc *sc) 342 { 343 struct usb_page_search buf_res; 344 struct xhci_hw_root *phwr; 345 struct xhci_dev_ctx_addr *pdctxa; 346 uint64_t addr; 347 uint32_t temp; 348 uint16_t i; 349 350 DPRINTF("\n"); 351 352 sc->sc_event_ccs = 1; 353 sc->sc_event_idx = 0; 354 sc->sc_command_ccs = 1; 355 sc->sc_command_idx = 0; 356 357 /* Reset controller */ 358 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 359 360 for (i = 0; i != 100; i++) { 361 usb_pause_mtx(NULL, hz / 100); 362 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 363 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 364 if (!temp) 365 break; 366 } 367 368 if (temp) { 369 device_printf(sc->sc_bus.parent, "Controller " 370 "reset timeout.\n"); 371 return (USB_ERR_IOERROR); 372 } 373 374 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 375 device_printf(sc->sc_bus.parent, "Controller does " 376 "not support 4K page size.\n"); 377 return (USB_ERR_IOERROR); 378 } 379 380 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 381 382 i = XHCI_HCS1_N_PORTS(temp); 383 384 if (i == 0) { 385 device_printf(sc->sc_bus.parent, "Invalid number " 386 "of ports: %u\n", i); 387 return (USB_ERR_IOERROR); 388 } 389 390 sc->sc_noport = i; 391 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 392 393 if (sc->sc_noslot > XHCI_MAX_DEVICES) 394 sc->sc_noslot = XHCI_MAX_DEVICES; 395 396 /* set up number of device slots */ 397 398 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 399 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 400 401 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 402 403 DPRINTF("Max slots: %u\n", sc->sc_noslot); 404 405 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 406 407 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 408 409 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 410 device_printf(sc->sc_bus.parent, "XHCI request " 411 "too many scratchpads\n"); 412 return (USB_ERR_NOMEM); 413 } 414 415 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 416 417 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 418 419 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 420 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 421 422 temp = XREAD4(sc, oper, XHCI_USBSTS); 423 424 /* clear interrupts */ 425 XWRITE4(sc, oper, XHCI_USBSTS, temp); 426 /* disable all device notifications */ 427 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 428 429 /* set up device context base address */ 430 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 431 pdctxa = buf_res.buffer; 432 memset(pdctxa, 0, sizeof(*pdctxa)); 433 434 addr = buf_res.physaddr; 435 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 436 437 /* slot 0 points to the table of scratchpad pointers */ 438 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 439 440 for (i = 0; i != sc->sc_noscratch; i++) { 441 struct usb_page_search buf_scp; 442 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 443 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 444 } 445 446 addr = buf_res.physaddr; 447 448 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 449 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 450 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 451 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 452 453 /* Setup event table size */ 454 455 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 456 457 DPRINTF("HCS2=0x%08x\n", temp); 458 459 temp = XHCI_HCS2_ERST_MAX(temp); 460 temp = 1U << temp; 461 if (temp > XHCI_MAX_RSEG) 462 temp = XHCI_MAX_RSEG; 463 464 sc->sc_erst_max = temp; 465 466 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 467 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 468 469 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 470 471 /* Check if we should use the default IMOD value */ 472 if (sc->sc_imod_default == 0) 473 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 474 475 /* Setup interrupt rate */ 476 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 477 478 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 479 480 phwr = buf_res.buffer; 481 addr = buf_res.physaddr; 482 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 483 484 /* reset hardware root structure */ 485 memset(phwr, 0, sizeof(*phwr)); 486 487 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 488 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 489 490 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 491 492 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 493 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 494 495 addr = (uint64_t)buf_res.physaddr; 496 497 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 498 499 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 500 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 501 502 /* Setup interrupter registers */ 503 504 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 505 temp |= XHCI_IMAN_INTR_ENA; 506 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 507 508 /* set up command ring control base address */ 509 addr = buf_res.physaddr; 510 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 511 512 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 513 514 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 515 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 516 517 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 518 519 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 520 521 /* Go! */ 522 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 523 XHCI_CMD_INTE | XHCI_CMD_HSEE); 524 525 for (i = 0; i != 100; i++) { 526 usb_pause_mtx(NULL, hz / 100); 527 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 528 if (!temp) 529 break; 530 } 531 if (temp) { 532 XWRITE4(sc, oper, XHCI_USBCMD, 0); 533 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 534 return (USB_ERR_IOERROR); 535 } 536 537 /* catch any lost interrupts */ 538 xhci_do_poll(&sc->sc_bus); 539 540 if (sc->sc_port_route != NULL) { 541 /* Route all ports to the XHCI by default */ 542 sc->sc_port_route(sc->sc_bus.parent, 543 ~xhciroute, xhciroute); 544 } 545 return (0); 546 } 547 548 usb_error_t 549 xhci_halt_controller(struct xhci_softc *sc) 550 { 551 uint32_t temp; 552 uint16_t i; 553 554 DPRINTF("\n"); 555 556 sc->sc_capa_off = 0; 557 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 558 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 559 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 560 561 /* Halt controller */ 562 XWRITE4(sc, oper, XHCI_USBCMD, 0); 563 564 for (i = 0; i != 100; i++) { 565 usb_pause_mtx(NULL, hz / 100); 566 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 567 if (temp) 568 break; 569 } 570 571 if (!temp) { 572 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 573 return (USB_ERR_IOERROR); 574 } 575 return (0); 576 } 577 578 usb_error_t 579 xhci_init(struct xhci_softc *sc, device_t self) 580 { 581 uint32_t temp; 582 583 DPRINTF("\n"); 584 585 /* initialize some bus fields */ 586 sc->sc_bus.parent = self; 587 588 /* set the bus revision */ 589 sc->sc_bus.usbrev = USB_REV_3_0; 590 591 /* set up the bus struct */ 592 sc->sc_bus.methods = &xhci_bus_methods; 593 594 /* set up devices array */ 595 sc->sc_bus.devices = sc->sc_devices; 596 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 597 598 /* set default cycle state in case of early interrupts */ 599 sc->sc_event_ccs = 1; 600 sc->sc_command_ccs = 1; 601 602 /* set up bus space offsets */ 603 sc->sc_capa_off = 0; 604 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 605 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 606 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 607 608 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 609 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 610 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 611 612 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 613 614 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 615 616 DPRINTF("HCS0 = 0x%08x\n", temp); 617 618 /* set up context size */ 619 if (XHCI_HCS0_CSZ(temp)) { 620 sc->sc_ctx_is_64_byte = 1; 621 } else { 622 sc->sc_ctx_is_64_byte = 0; 623 } 624 625 /* get DMA bits */ 626 sc->sc_bus.dma_bits = XHCI_HCS0_AC64(temp) ? 64 : 32; 627 628 device_printf(self, "%d bytes context size, %d-bit DMA\n", 629 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); 630 631 /* get all DMA memory */ 632 if (usb_bus_mem_alloc_all(&sc->sc_bus, 633 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 634 return (ENOMEM); 635 } 636 637 /* set up command queue mutex and condition varible */ 638 cv_init(&sc->sc_cmd_cv, "CMDQ"); 639 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 640 641 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 642 sc->sc_config_msg[0].bus = &sc->sc_bus; 643 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 644 sc->sc_config_msg[1].bus = &sc->sc_bus; 645 646 return (0); 647 } 648 649 void 650 xhci_uninit(struct xhci_softc *sc) 651 { 652 /* 653 * NOTE: At this point the control transfer process is gone 654 * and "xhci_configure_msg" is no longer called. Consequently 655 * waiting for the configuration messages to complete is not 656 * needed. 657 */ 658 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 659 660 cv_destroy(&sc->sc_cmd_cv); 661 sx_destroy(&sc->sc_cmd_sx); 662 } 663 664 static void 665 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 666 { 667 struct xhci_softc *sc = XHCI_BUS2SC(bus); 668 669 switch (state) { 670 case USB_HW_POWER_SUSPEND: 671 DPRINTF("Stopping the XHCI\n"); 672 xhci_halt_controller(sc); 673 break; 674 case USB_HW_POWER_SHUTDOWN: 675 DPRINTF("Stopping the XHCI\n"); 676 xhci_halt_controller(sc); 677 break; 678 case USB_HW_POWER_RESUME: 679 DPRINTF("Starting the XHCI\n"); 680 xhci_start_controller(sc); 681 break; 682 default: 683 break; 684 } 685 } 686 687 static usb_error_t 688 xhci_generic_done_sub(struct usb_xfer *xfer) 689 { 690 struct xhci_td *td; 691 struct xhci_td *td_alt_next; 692 uint32_t len; 693 uint8_t status; 694 695 td = xfer->td_transfer_cache; 696 td_alt_next = td->alt_next; 697 698 if (xfer->aframes != xfer->nframes) 699 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 700 701 while (1) { 702 703 usb_pc_cpu_invalidate(td->page_cache); 704 705 status = td->status; 706 len = td->remainder; 707 708 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 709 xfer, (unsigned int)xfer->aframes, 710 (unsigned int)xfer->nframes, 711 (unsigned int)len, (unsigned int)td->len, 712 (unsigned int)status); 713 714 /* 715 * Verify the status length and 716 * add the length to "frlengths[]": 717 */ 718 if (len > td->len) { 719 /* should not happen */ 720 DPRINTF("Invalid status length, " 721 "0x%04x/0x%04x bytes\n", len, td->len); 722 status = XHCI_TRB_ERROR_LENGTH; 723 } else if (xfer->aframes != xfer->nframes) { 724 xfer->frlengths[xfer->aframes] += td->len - len; 725 } 726 /* Check for last transfer */ 727 if (((void *)td) == xfer->td_transfer_last) { 728 td = NULL; 729 break; 730 } 731 /* Check for transfer error */ 732 if (status != XHCI_TRB_ERROR_SHORT_PKT && 733 status != XHCI_TRB_ERROR_SUCCESS) { 734 /* the transfer is finished */ 735 td = NULL; 736 break; 737 } 738 /* Check for short transfer */ 739 if (len > 0) { 740 if (xfer->flags_int.short_frames_ok || 741 xfer->flags_int.isochronous_xfr || 742 xfer->flags_int.control_xfr) { 743 /* follow alt next */ 744 td = td->alt_next; 745 } else { 746 /* the transfer is finished */ 747 td = NULL; 748 } 749 break; 750 } 751 td = td->obj_next; 752 753 if (td->alt_next != td_alt_next) { 754 /* this USB frame is complete */ 755 break; 756 } 757 } 758 759 /* update transfer cache */ 760 761 xfer->td_transfer_cache = td; 762 763 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 764 (status != XHCI_TRB_ERROR_SHORT_PKT && 765 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 766 USB_ERR_NORMAL_COMPLETION); 767 } 768 769 static void 770 xhci_generic_done(struct usb_xfer *xfer) 771 { 772 usb_error_t err = 0; 773 774 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 775 xfer, xfer->endpoint); 776 777 /* reset scanner */ 778 779 xfer->td_transfer_cache = xfer->td_transfer_first; 780 781 if (xfer->flags_int.control_xfr) { 782 783 if (xfer->flags_int.control_hdr) 784 err = xhci_generic_done_sub(xfer); 785 786 xfer->aframes = 1; 787 788 if (xfer->td_transfer_cache == NULL) 789 goto done; 790 } 791 792 while (xfer->aframes != xfer->nframes) { 793 794 err = xhci_generic_done_sub(xfer); 795 xfer->aframes++; 796 797 if (xfer->td_transfer_cache == NULL) 798 goto done; 799 } 800 801 if (xfer->flags_int.control_xfr && 802 !xfer->flags_int.control_act) 803 err = xhci_generic_done_sub(xfer); 804 done: 805 /* transfer is complete */ 806 xhci_device_done(xfer, err); 807 } 808 809 static void 810 xhci_activate_transfer(struct usb_xfer *xfer) 811 { 812 struct xhci_td *td; 813 814 td = xfer->td_transfer_cache; 815 816 usb_pc_cpu_invalidate(td->page_cache); 817 818 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 819 820 /* activate the transfer */ 821 822 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 823 usb_pc_cpu_flush(td->page_cache); 824 825 xhci_endpoint_doorbell(xfer); 826 } 827 } 828 829 static void 830 xhci_skip_transfer(struct usb_xfer *xfer) 831 { 832 struct xhci_td *td; 833 struct xhci_td *td_last; 834 835 td = xfer->td_transfer_cache; 836 td_last = xfer->td_transfer_last; 837 838 td = td->alt_next; 839 840 usb_pc_cpu_invalidate(td->page_cache); 841 842 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 843 844 usb_pc_cpu_invalidate(td_last->page_cache); 845 846 /* copy LINK TRB to current waiting location */ 847 848 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 849 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 850 usb_pc_cpu_flush(td->page_cache); 851 852 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 853 usb_pc_cpu_flush(td->page_cache); 854 855 xhci_endpoint_doorbell(xfer); 856 } 857 } 858 859 /*------------------------------------------------------------------------* 860 * xhci_check_transfer 861 *------------------------------------------------------------------------*/ 862 static void 863 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 864 { 865 struct xhci_endpoint_ext *pepext; 866 int64_t offset; 867 uint64_t td_event; 868 uint32_t temp; 869 uint32_t remainder; 870 uint16_t stream_id; 871 uint16_t i; 872 uint8_t status; 873 uint8_t halted; 874 uint8_t epno; 875 uint8_t index; 876 877 /* decode TRB */ 878 td_event = le64toh(trb->qwTrb0); 879 temp = le32toh(trb->dwTrb2); 880 881 remainder = XHCI_TRB_2_REM_GET(temp); 882 status = XHCI_TRB_2_ERROR_GET(temp); 883 stream_id = XHCI_TRB_2_STREAM_GET(temp); 884 885 temp = le32toh(trb->dwTrb3); 886 epno = XHCI_TRB_3_EP_GET(temp); 887 index = XHCI_TRB_3_SLOT_GET(temp); 888 889 /* check if error means halted */ 890 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 891 status != XHCI_TRB_ERROR_SUCCESS); 892 893 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 894 index, epno, stream_id, remainder, status); 895 896 if (index > sc->sc_noslot) { 897 DPRINTF("Invalid slot.\n"); 898 return; 899 } 900 901 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 902 DPRINTF("Invalid endpoint.\n"); 903 return; 904 } 905 906 pepext = &sc->sc_hw.devs[index].endp[epno]; 907 908 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 909 stream_id = 0; 910 DPRINTF("stream_id=0\n"); 911 } else if (stream_id >= XHCI_MAX_STREAMS) { 912 DPRINTF("Invalid stream ID.\n"); 913 return; 914 } 915 916 /* try to find the USB transfer that generated the event */ 917 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 918 struct usb_xfer *xfer; 919 struct xhci_td *td; 920 921 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 922 if (xfer == NULL) 923 continue; 924 925 td = xfer->td_transfer_cache; 926 927 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 928 (long long)td_event, 929 (long long)td->td_self, 930 (long long)td->td_self + sizeof(td->td_trb)); 931 932 /* 933 * NOTE: Some XHCI implementations might not trigger 934 * an event on the last LINK TRB so we need to 935 * consider both the last and second last event 936 * address as conditions for a successful transfer. 937 * 938 * NOTE: We assume that the XHCI will only trigger one 939 * event per chain of TRBs. 940 */ 941 942 offset = td_event - td->td_self; 943 944 if (offset >= 0 && 945 offset < (int64_t)sizeof(td->td_trb)) { 946 947 usb_pc_cpu_invalidate(td->page_cache); 948 949 /* compute rest of remainder, if any */ 950 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 951 temp = le32toh(td->td_trb[i].dwTrb2); 952 remainder += XHCI_TRB_2_BYTES_GET(temp); 953 } 954 955 DPRINTFN(5, "New remainder: %u\n", remainder); 956 957 /* clear isochronous transfer errors */ 958 if (xfer->flags_int.isochronous_xfr) { 959 if (halted) { 960 halted = 0; 961 status = XHCI_TRB_ERROR_SUCCESS; 962 remainder = td->len; 963 } 964 } 965 966 /* "td->remainder" is verified later */ 967 td->remainder = remainder; 968 td->status = status; 969 970 usb_pc_cpu_flush(td->page_cache); 971 972 /* 973 * 1) Last transfer descriptor makes the 974 * transfer done 975 */ 976 if (((void *)td) == xfer->td_transfer_last) { 977 DPRINTF("TD is last\n"); 978 xhci_generic_done(xfer); 979 break; 980 } 981 982 /* 983 * 2) Any kind of error makes the transfer 984 * done 985 */ 986 if (halted) { 987 DPRINTF("TD has I/O error\n"); 988 xhci_generic_done(xfer); 989 break; 990 } 991 992 /* 993 * 3) If there is no alternate next transfer, 994 * a short packet also makes the transfer done 995 */ 996 if (td->remainder > 0) { 997 if (td->alt_next == NULL) { 998 DPRINTF( 999 "short TD has no alternate next\n"); 1000 xhci_generic_done(xfer); 1001 break; 1002 } 1003 DPRINTF("TD has short pkt\n"); 1004 if (xfer->flags_int.short_frames_ok || 1005 xfer->flags_int.isochronous_xfr || 1006 xfer->flags_int.control_xfr) { 1007 /* follow the alt next */ 1008 xfer->td_transfer_cache = td->alt_next; 1009 xhci_activate_transfer(xfer); 1010 break; 1011 } 1012 xhci_skip_transfer(xfer); 1013 xhci_generic_done(xfer); 1014 break; 1015 } 1016 1017 /* 1018 * 4) Transfer complete - go to next TD 1019 */ 1020 DPRINTF("Following next TD\n"); 1021 xfer->td_transfer_cache = td->obj_next; 1022 xhci_activate_transfer(xfer); 1023 break; /* there should only be one match */ 1024 } 1025 } 1026 } 1027 1028 static int 1029 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1030 { 1031 if (sc->sc_cmd_addr == trb->qwTrb0) { 1032 DPRINTF("Received command event\n"); 1033 sc->sc_cmd_result[0] = trb->dwTrb2; 1034 sc->sc_cmd_result[1] = trb->dwTrb3; 1035 cv_signal(&sc->sc_cmd_cv); 1036 return (1); /* command match */ 1037 } 1038 return (0); 1039 } 1040 1041 static int 1042 xhci_interrupt_poll(struct xhci_softc *sc) 1043 { 1044 struct usb_page_search buf_res; 1045 struct xhci_hw_root *phwr; 1046 uint64_t addr; 1047 uint32_t temp; 1048 int retval = 0; 1049 uint16_t i; 1050 uint8_t event; 1051 uint8_t j; 1052 uint8_t k; 1053 uint8_t t; 1054 1055 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1056 1057 phwr = buf_res.buffer; 1058 1059 /* Receive any events */ 1060 1061 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1062 1063 i = sc->sc_event_idx; 1064 j = sc->sc_event_ccs; 1065 t = 2; 1066 1067 while (1) { 1068 1069 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1070 1071 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1072 1073 if (j != k) 1074 break; 1075 1076 event = XHCI_TRB_3_TYPE_GET(temp); 1077 1078 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1079 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1080 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1081 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1082 1083 switch (event) { 1084 case XHCI_TRB_EVENT_TRANSFER: 1085 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1086 break; 1087 case XHCI_TRB_EVENT_CMD_COMPLETE: 1088 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1089 break; 1090 default: 1091 DPRINTF("Unhandled event = %u\n", event); 1092 break; 1093 } 1094 1095 i++; 1096 1097 if (i == XHCI_MAX_EVENTS) { 1098 i = 0; 1099 j ^= 1; 1100 1101 /* check for timeout */ 1102 if (!--t) 1103 break; 1104 } 1105 } 1106 1107 sc->sc_event_idx = i; 1108 sc->sc_event_ccs = j; 1109 1110 /* 1111 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1112 * latched. That means to activate the register we need to 1113 * write both the low and high double word of the 64-bit 1114 * register. 1115 */ 1116 1117 addr = (uint32_t)buf_res.physaddr; 1118 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1119 1120 /* try to clear busy bit */ 1121 addr |= XHCI_ERDP_LO_BUSY; 1122 1123 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1124 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1125 1126 return (retval); 1127 } 1128 1129 static usb_error_t 1130 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1131 uint16_t timeout_ms) 1132 { 1133 struct usb_page_search buf_res; 1134 struct xhci_hw_root *phwr; 1135 uint64_t addr; 1136 uint32_t temp; 1137 uint8_t i; 1138 uint8_t j; 1139 uint8_t timeout = 0; 1140 int err; 1141 1142 XHCI_CMD_ASSERT_LOCKED(sc); 1143 1144 /* get hardware root structure */ 1145 1146 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1147 1148 phwr = buf_res.buffer; 1149 1150 /* Queue command */ 1151 1152 USB_BUS_LOCK(&sc->sc_bus); 1153 retry: 1154 i = sc->sc_command_idx; 1155 j = sc->sc_command_ccs; 1156 1157 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1158 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1159 (long long)le64toh(trb->qwTrb0), 1160 (long)le32toh(trb->dwTrb2), 1161 (long)le32toh(trb->dwTrb3)); 1162 1163 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1164 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1165 1166 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1167 1168 temp = trb->dwTrb3; 1169 1170 if (j) 1171 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1172 else 1173 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1174 1175 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1176 1177 phwr->hwr_commands[i].dwTrb3 = temp; 1178 1179 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1180 1181 addr = buf_res.physaddr; 1182 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1183 1184 sc->sc_cmd_addr = htole64(addr); 1185 1186 i++; 1187 1188 if (i == (XHCI_MAX_COMMANDS - 1)) { 1189 1190 if (j) { 1191 temp = htole32(XHCI_TRB_3_TC_BIT | 1192 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1193 XHCI_TRB_3_CYCLE_BIT); 1194 } else { 1195 temp = htole32(XHCI_TRB_3_TC_BIT | 1196 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1197 } 1198 1199 phwr->hwr_commands[i].dwTrb3 = temp; 1200 1201 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1202 1203 i = 0; 1204 j ^= 1; 1205 } 1206 1207 sc->sc_command_idx = i; 1208 sc->sc_command_ccs = j; 1209 1210 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1211 1212 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1213 USB_MS_TO_TICKS(timeout_ms)); 1214 1215 /* 1216 * In some error cases event interrupts are not generated. 1217 * Poll one time to see if the command has completed. 1218 */ 1219 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1220 DPRINTF("Command was completed when polling\n"); 1221 err = 0; 1222 } 1223 if (err != 0) { 1224 DPRINTF("Command timeout!\n"); 1225 /* 1226 * After some weeks of continuous operation, it has 1227 * been observed that the ASMedia Technology, ASM1042 1228 * SuperSpeed USB Host Controller can suddenly stop 1229 * accepting commands via the command queue. Try to 1230 * first reset the command queue. If that fails do a 1231 * host controller reset. 1232 */ 1233 if (timeout == 0 && 1234 xhci_reset_command_queue_locked(sc) == 0) { 1235 temp = le32toh(trb->dwTrb3); 1236 1237 /* 1238 * Avoid infinite XHCI reset loops if the set 1239 * address command fails to respond due to a 1240 * non-enumerating device: 1241 */ 1242 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1243 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1244 DPRINTF("Set address timeout\n"); 1245 } else { 1246 timeout = 1; 1247 goto retry; 1248 } 1249 } else { 1250 DPRINTF("Controller reset!\n"); 1251 usb_bus_reset_async_locked(&sc->sc_bus); 1252 } 1253 err = USB_ERR_TIMEOUT; 1254 trb->dwTrb2 = 0; 1255 trb->dwTrb3 = 0; 1256 } else { 1257 temp = le32toh(sc->sc_cmd_result[0]); 1258 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1259 err = USB_ERR_IOERROR; 1260 1261 trb->dwTrb2 = sc->sc_cmd_result[0]; 1262 trb->dwTrb3 = sc->sc_cmd_result[1]; 1263 } 1264 1265 USB_BUS_UNLOCK(&sc->sc_bus); 1266 1267 return (err); 1268 } 1269 1270 #if 0 1271 static usb_error_t 1272 xhci_cmd_nop(struct xhci_softc *sc) 1273 { 1274 struct xhci_trb trb; 1275 uint32_t temp; 1276 1277 DPRINTF("\n"); 1278 1279 trb.qwTrb0 = 0; 1280 trb.dwTrb2 = 0; 1281 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1282 1283 trb.dwTrb3 = htole32(temp); 1284 1285 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1286 } 1287 #endif 1288 1289 static usb_error_t 1290 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1291 { 1292 struct xhci_trb trb; 1293 uint32_t temp; 1294 usb_error_t err; 1295 1296 DPRINTF("\n"); 1297 1298 trb.qwTrb0 = 0; 1299 trb.dwTrb2 = 0; 1300 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1301 1302 err = xhci_do_command(sc, &trb, 100 /* ms */); 1303 if (err) 1304 goto done; 1305 1306 temp = le32toh(trb.dwTrb3); 1307 1308 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1309 1310 done: 1311 return (err); 1312 } 1313 1314 static usb_error_t 1315 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1316 { 1317 struct xhci_trb trb; 1318 uint32_t temp; 1319 1320 DPRINTF("\n"); 1321 1322 trb.qwTrb0 = 0; 1323 trb.dwTrb2 = 0; 1324 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1325 XHCI_TRB_3_SLOT_SET(slot_id); 1326 1327 trb.dwTrb3 = htole32(temp); 1328 1329 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1330 } 1331 1332 static usb_error_t 1333 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1334 uint8_t bsr, uint8_t slot_id) 1335 { 1336 struct xhci_trb trb; 1337 uint32_t temp; 1338 1339 DPRINTF("\n"); 1340 1341 trb.qwTrb0 = htole64(input_ctx); 1342 trb.dwTrb2 = 0; 1343 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1344 XHCI_TRB_3_SLOT_SET(slot_id); 1345 1346 if (bsr) 1347 temp |= XHCI_TRB_3_BSR_BIT; 1348 1349 trb.dwTrb3 = htole32(temp); 1350 1351 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1352 } 1353 1354 static usb_error_t 1355 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1356 { 1357 struct usb_page_search buf_inp; 1358 struct usb_page_search buf_dev; 1359 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1360 struct xhci_hw_dev *hdev; 1361 struct xhci_dev_ctx *pdev; 1362 struct xhci_endpoint_ext *pepext; 1363 uint32_t temp; 1364 uint16_t mps; 1365 usb_error_t err; 1366 uint8_t index; 1367 1368 /* the root HUB case is not handled here */ 1369 if (udev->parent_hub == NULL) 1370 return (USB_ERR_INVAL); 1371 1372 index = udev->controller_slot_id; 1373 1374 hdev = &sc->sc_hw.devs[index]; 1375 1376 if (mtx != NULL) 1377 mtx_unlock(mtx); 1378 1379 XHCI_CMD_LOCK(sc); 1380 1381 switch (hdev->state) { 1382 case XHCI_ST_DEFAULT: 1383 case XHCI_ST_ENABLED: 1384 1385 hdev->state = XHCI_ST_ENABLED; 1386 1387 /* set configure mask to slot and EP0 */ 1388 xhci_configure_mask(udev, 3, 0); 1389 1390 /* configure input slot context structure */ 1391 err = xhci_configure_device(udev); 1392 1393 if (err != 0) { 1394 DPRINTF("Could not configure device\n"); 1395 break; 1396 } 1397 1398 /* configure input endpoint context structure */ 1399 switch (udev->speed) { 1400 case USB_SPEED_LOW: 1401 case USB_SPEED_FULL: 1402 mps = 8; 1403 break; 1404 case USB_SPEED_HIGH: 1405 mps = 64; 1406 break; 1407 default: 1408 mps = 512; 1409 break; 1410 } 1411 1412 pepext = xhci_get_endpoint_ext(udev, 1413 &udev->ctrl_ep_desc); 1414 err = xhci_configure_endpoint(udev, 1415 &udev->ctrl_ep_desc, pepext, 1416 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1417 1418 if (err != 0) { 1419 DPRINTF("Could not configure default endpoint\n"); 1420 break; 1421 } 1422 1423 /* execute set address command */ 1424 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1425 1426 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1427 (address == 0), index); 1428 1429 if (err != 0) { 1430 temp = le32toh(sc->sc_cmd_result[0]); 1431 if (address == 0 && sc->sc_port_route != NULL && 1432 XHCI_TRB_2_ERROR_GET(temp) == 1433 XHCI_TRB_ERROR_PARAMETER) { 1434 /* LynxPoint XHCI - ports are not switchable */ 1435 /* Un-route all ports from the XHCI */ 1436 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1437 } 1438 DPRINTF("Could not set address " 1439 "for slot %u.\n", index); 1440 if (address != 0) 1441 break; 1442 } 1443 1444 /* update device address to new value */ 1445 1446 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1447 pdev = buf_dev.buffer; 1448 usb_pc_cpu_invalidate(&hdev->device_pc); 1449 1450 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1451 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1452 1453 /* update device state to new value */ 1454 1455 if (address != 0) 1456 hdev->state = XHCI_ST_ADDRESSED; 1457 else 1458 hdev->state = XHCI_ST_DEFAULT; 1459 break; 1460 1461 default: 1462 DPRINTF("Wrong state for set address.\n"); 1463 err = USB_ERR_IOERROR; 1464 break; 1465 } 1466 XHCI_CMD_UNLOCK(sc); 1467 1468 if (mtx != NULL) 1469 mtx_lock(mtx); 1470 1471 return (err); 1472 } 1473 1474 static usb_error_t 1475 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1476 uint8_t deconfigure, uint8_t slot_id) 1477 { 1478 struct xhci_trb trb; 1479 uint32_t temp; 1480 1481 DPRINTF("\n"); 1482 1483 trb.qwTrb0 = htole64(input_ctx); 1484 trb.dwTrb2 = 0; 1485 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1486 XHCI_TRB_3_SLOT_SET(slot_id); 1487 1488 if (deconfigure) 1489 temp |= XHCI_TRB_3_DCEP_BIT; 1490 1491 trb.dwTrb3 = htole32(temp); 1492 1493 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1494 } 1495 1496 static usb_error_t 1497 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1498 uint8_t slot_id) 1499 { 1500 struct xhci_trb trb; 1501 uint32_t temp; 1502 1503 DPRINTF("\n"); 1504 1505 trb.qwTrb0 = htole64(input_ctx); 1506 trb.dwTrb2 = 0; 1507 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1508 XHCI_TRB_3_SLOT_SET(slot_id); 1509 trb.dwTrb3 = htole32(temp); 1510 1511 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1512 } 1513 1514 static usb_error_t 1515 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1516 uint8_t ep_id, uint8_t slot_id) 1517 { 1518 struct xhci_trb trb; 1519 uint32_t temp; 1520 1521 DPRINTF("\n"); 1522 1523 trb.qwTrb0 = 0; 1524 trb.dwTrb2 = 0; 1525 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1526 XHCI_TRB_3_SLOT_SET(slot_id) | 1527 XHCI_TRB_3_EP_SET(ep_id); 1528 1529 if (preserve) 1530 temp |= XHCI_TRB_3_PRSV_BIT; 1531 1532 trb.dwTrb3 = htole32(temp); 1533 1534 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1535 } 1536 1537 static usb_error_t 1538 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1539 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1540 { 1541 struct xhci_trb trb; 1542 uint32_t temp; 1543 1544 DPRINTF("\n"); 1545 1546 trb.qwTrb0 = htole64(dequeue_ptr); 1547 1548 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1549 trb.dwTrb2 = htole32(temp); 1550 1551 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1552 XHCI_TRB_3_SLOT_SET(slot_id) | 1553 XHCI_TRB_3_EP_SET(ep_id); 1554 trb.dwTrb3 = htole32(temp); 1555 1556 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1557 } 1558 1559 static usb_error_t 1560 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1561 uint8_t ep_id, uint8_t slot_id) 1562 { 1563 struct xhci_trb trb; 1564 uint32_t temp; 1565 1566 DPRINTF("\n"); 1567 1568 trb.qwTrb0 = 0; 1569 trb.dwTrb2 = 0; 1570 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1571 XHCI_TRB_3_SLOT_SET(slot_id) | 1572 XHCI_TRB_3_EP_SET(ep_id); 1573 1574 if (suspend) 1575 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1576 1577 trb.dwTrb3 = htole32(temp); 1578 1579 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1580 } 1581 1582 static usb_error_t 1583 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1584 { 1585 struct xhci_trb trb; 1586 uint32_t temp; 1587 1588 DPRINTF("\n"); 1589 1590 trb.qwTrb0 = 0; 1591 trb.dwTrb2 = 0; 1592 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1593 XHCI_TRB_3_SLOT_SET(slot_id); 1594 1595 trb.dwTrb3 = htole32(temp); 1596 1597 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1598 } 1599 1600 /*------------------------------------------------------------------------* 1601 * xhci_interrupt - XHCI interrupt handler 1602 *------------------------------------------------------------------------*/ 1603 void 1604 xhci_interrupt(struct xhci_softc *sc) 1605 { 1606 uint32_t status; 1607 uint32_t temp; 1608 1609 USB_BUS_LOCK(&sc->sc_bus); 1610 1611 status = XREAD4(sc, oper, XHCI_USBSTS); 1612 1613 /* acknowledge interrupts, if any */ 1614 if (status != 0) { 1615 XWRITE4(sc, oper, XHCI_USBSTS, status); 1616 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1617 } 1618 1619 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1620 1621 /* force clearing of pending interrupts */ 1622 if (temp & XHCI_IMAN_INTR_PEND) 1623 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1624 1625 /* check for event(s) */ 1626 xhci_interrupt_poll(sc); 1627 1628 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1629 XHCI_STS_HSE | XHCI_STS_HCE)) { 1630 1631 if (status & XHCI_STS_PCD) { 1632 xhci_root_intr(sc); 1633 } 1634 1635 if (status & XHCI_STS_HCH) { 1636 printf("%s: host controller halted\n", 1637 __FUNCTION__); 1638 } 1639 1640 if (status & XHCI_STS_HSE) { 1641 printf("%s: host system error\n", 1642 __FUNCTION__); 1643 } 1644 1645 if (status & XHCI_STS_HCE) { 1646 printf("%s: host controller error\n", 1647 __FUNCTION__); 1648 } 1649 } 1650 USB_BUS_UNLOCK(&sc->sc_bus); 1651 } 1652 1653 /*------------------------------------------------------------------------* 1654 * xhci_timeout - XHCI timeout handler 1655 *------------------------------------------------------------------------*/ 1656 static void 1657 xhci_timeout(void *arg) 1658 { 1659 struct usb_xfer *xfer = arg; 1660 1661 DPRINTF("xfer=%p\n", xfer); 1662 1663 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1664 1665 /* transfer is transferred */ 1666 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1667 } 1668 1669 static void 1670 xhci_do_poll(struct usb_bus *bus) 1671 { 1672 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1673 1674 USB_BUS_LOCK(&sc->sc_bus); 1675 xhci_interrupt_poll(sc); 1676 USB_BUS_UNLOCK(&sc->sc_bus); 1677 } 1678 1679 static void 1680 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1681 { 1682 struct usb_page_search buf_res; 1683 struct xhci_td *td; 1684 struct xhci_td *td_next; 1685 struct xhci_td *td_alt_next; 1686 struct xhci_td *td_first; 1687 uint32_t buf_offset; 1688 uint32_t average; 1689 uint32_t len_old; 1690 uint32_t npkt_off; 1691 uint32_t dword; 1692 uint8_t shortpkt_old; 1693 uint8_t precompute; 1694 uint8_t x; 1695 1696 td_alt_next = NULL; 1697 buf_offset = 0; 1698 shortpkt_old = temp->shortpkt; 1699 len_old = temp->len; 1700 npkt_off = 0; 1701 precompute = 1; 1702 1703 restart: 1704 1705 td = temp->td; 1706 td_next = td_first = temp->td_next; 1707 1708 while (1) { 1709 1710 if (temp->len == 0) { 1711 1712 if (temp->shortpkt) 1713 break; 1714 1715 /* send a Zero Length Packet, ZLP, last */ 1716 1717 temp->shortpkt = 1; 1718 average = 0; 1719 1720 } else { 1721 1722 average = temp->average; 1723 1724 if (temp->len < average) { 1725 if (temp->len % temp->max_packet_size) { 1726 temp->shortpkt = 1; 1727 } 1728 average = temp->len; 1729 } 1730 } 1731 1732 if (td_next == NULL) 1733 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1734 1735 /* get next TD */ 1736 1737 td = td_next; 1738 td_next = td->obj_next; 1739 1740 /* check if we are pre-computing */ 1741 1742 if (precompute) { 1743 1744 /* update remaining length */ 1745 1746 temp->len -= average; 1747 1748 continue; 1749 } 1750 /* fill out current TD */ 1751 1752 td->len = average; 1753 td->remainder = 0; 1754 td->status = 0; 1755 1756 /* update remaining length */ 1757 1758 temp->len -= average; 1759 1760 /* reset TRB index */ 1761 1762 x = 0; 1763 1764 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1765 /* immediate data */ 1766 1767 if (average > 8) 1768 average = 8; 1769 1770 td->td_trb[0].qwTrb0 = 0; 1771 1772 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1773 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1774 average); 1775 1776 dword = XHCI_TRB_2_BYTES_SET(8) | 1777 XHCI_TRB_2_TDSZ_SET(0) | 1778 XHCI_TRB_2_IRQ_SET(0); 1779 1780 td->td_trb[0].dwTrb2 = htole32(dword); 1781 1782 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1783 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1784 1785 /* check wLength */ 1786 if (td->td_trb[0].qwTrb0 & 1787 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1788 if (td->td_trb[0].qwTrb0 & 1789 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1790 dword |= XHCI_TRB_3_TRT_IN; 1791 else 1792 dword |= XHCI_TRB_3_TRT_OUT; 1793 } 1794 1795 td->td_trb[0].dwTrb3 = htole32(dword); 1796 #ifdef USB_DEBUG 1797 xhci_dump_trb(&td->td_trb[x]); 1798 #endif 1799 x++; 1800 1801 } else do { 1802 1803 uint32_t npkt; 1804 1805 /* fill out buffer pointers */ 1806 1807 if (average == 0) { 1808 memset(&buf_res, 0, sizeof(buf_res)); 1809 } else { 1810 usbd_get_page(temp->pc, temp->offset + 1811 buf_offset, &buf_res); 1812 1813 /* get length to end of page */ 1814 if (buf_res.length > average) 1815 buf_res.length = average; 1816 1817 /* check for maximum length */ 1818 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1819 buf_res.length = XHCI_TD_PAGE_SIZE; 1820 1821 npkt_off += buf_res.length; 1822 } 1823 1824 /* set up npkt */ 1825 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1826 temp->max_packet_size; 1827 1828 if (npkt == 0) 1829 npkt = 1; 1830 else if (npkt > 31) 1831 npkt = 31; 1832 1833 /* fill out TRB's */ 1834 td->td_trb[x].qwTrb0 = 1835 htole64((uint64_t)buf_res.physaddr); 1836 1837 dword = 1838 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1839 XHCI_TRB_2_TDSZ_SET(npkt) | 1840 XHCI_TRB_2_IRQ_SET(0); 1841 1842 td->td_trb[x].dwTrb2 = htole32(dword); 1843 1844 switch (temp->trb_type) { 1845 case XHCI_TRB_TYPE_ISOCH: 1846 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1847 XHCI_TRB_3_TBC_SET(temp->tbc) | 1848 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1849 if (td != td_first) { 1850 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1851 } else if (temp->do_isoc_sync != 0) { 1852 temp->do_isoc_sync = 0; 1853 /* wait until "isoc_frame" */ 1854 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1855 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1856 } else { 1857 /* start data transfer at next interval */ 1858 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1859 XHCI_TRB_3_ISO_SIA_BIT; 1860 } 1861 if (temp->direction == UE_DIR_IN) 1862 dword |= XHCI_TRB_3_ISP_BIT; 1863 break; 1864 case XHCI_TRB_TYPE_DATA_STAGE: 1865 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1866 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1867 if (temp->direction == UE_DIR_IN) 1868 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1869 break; 1870 case XHCI_TRB_TYPE_STATUS_STAGE: 1871 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1872 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1873 if (temp->direction == UE_DIR_IN) 1874 dword |= XHCI_TRB_3_DIR_IN; 1875 break; 1876 default: /* XHCI_TRB_TYPE_NORMAL */ 1877 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1878 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1879 if (temp->direction == UE_DIR_IN) 1880 dword |= XHCI_TRB_3_ISP_BIT; 1881 break; 1882 } 1883 td->td_trb[x].dwTrb3 = htole32(dword); 1884 1885 average -= buf_res.length; 1886 buf_offset += buf_res.length; 1887 #ifdef USB_DEBUG 1888 xhci_dump_trb(&td->td_trb[x]); 1889 #endif 1890 x++; 1891 1892 } while (average != 0); 1893 1894 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1895 1896 /* store number of data TRB's */ 1897 1898 td->ntrb = x; 1899 1900 DPRINTF("NTRB=%u\n", x); 1901 1902 /* fill out link TRB */ 1903 1904 if (td_next != NULL) { 1905 /* link the current TD with the next one */ 1906 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1907 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1908 } else { 1909 /* this field will get updated later */ 1910 DPRINTF("NOLINK\n"); 1911 } 1912 1913 dword = XHCI_TRB_2_IRQ_SET(0); 1914 1915 td->td_trb[x].dwTrb2 = htole32(dword); 1916 1917 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1918 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1919 /* 1920 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1921 * frame only receives a single short packet event 1922 * by setting the CHAIN bit in the LINK field. In 1923 * addition some XHCI controllers have problems 1924 * sending a ZLP unless the CHAIN-BIT is set in 1925 * the LINK TRB. 1926 */ 1927 XHCI_TRB_3_CHAIN_BIT; 1928 1929 td->td_trb[x].dwTrb3 = htole32(dword); 1930 1931 td->alt_next = td_alt_next; 1932 #ifdef USB_DEBUG 1933 xhci_dump_trb(&td->td_trb[x]); 1934 #endif 1935 usb_pc_cpu_flush(td->page_cache); 1936 } 1937 1938 if (precompute) { 1939 precompute = 0; 1940 1941 /* set up alt next pointer, if any */ 1942 if (temp->last_frame) { 1943 td_alt_next = NULL; 1944 } else { 1945 /* we use this field internally */ 1946 td_alt_next = td_next; 1947 } 1948 1949 /* restore */ 1950 temp->shortpkt = shortpkt_old; 1951 temp->len = len_old; 1952 goto restart; 1953 } 1954 1955 /* 1956 * Remove cycle bit from the first TRB if we are 1957 * stepping them: 1958 */ 1959 if (temp->step_td != 0) { 1960 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1961 usb_pc_cpu_flush(td_first->page_cache); 1962 } 1963 1964 /* clear TD SIZE to zero, hence this is the last TRB */ 1965 /* remove chain bit because this is the last data TRB in the chain */ 1966 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1967 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1968 /* remove CHAIN-BIT from last LINK TRB */ 1969 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1970 1971 usb_pc_cpu_flush(td->page_cache); 1972 1973 temp->td = td; 1974 temp->td_next = td_next; 1975 } 1976 1977 static void 1978 xhci_setup_generic_chain(struct usb_xfer *xfer) 1979 { 1980 struct xhci_std_temp temp; 1981 struct xhci_td *td; 1982 uint32_t x; 1983 uint32_t y; 1984 uint8_t mult; 1985 1986 temp.do_isoc_sync = 0; 1987 temp.step_td = 0; 1988 temp.tbc = 0; 1989 temp.tlbpc = 0; 1990 temp.average = xfer->max_hc_frame_size; 1991 temp.max_packet_size = xfer->max_packet_size; 1992 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1993 temp.pc = NULL; 1994 temp.last_frame = 0; 1995 temp.offset = 0; 1996 temp.multishort = xfer->flags_int.isochronous_xfr || 1997 xfer->flags_int.control_xfr || 1998 xfer->flags_int.short_frames_ok; 1999 2000 /* toggle the DMA set we are using */ 2001 xfer->flags_int.curr_dma_set ^= 1; 2002 2003 /* get next DMA set */ 2004 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2005 2006 temp.td = NULL; 2007 temp.td_next = td; 2008 2009 xfer->td_transfer_first = td; 2010 xfer->td_transfer_cache = td; 2011 2012 if (xfer->flags_int.isochronous_xfr) { 2013 uint8_t shift; 2014 2015 /* compute multiplier for ISOCHRONOUS transfers */ 2016 mult = xfer->endpoint->ecomp ? 2017 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2018 : 0; 2019 /* check for USB 2.0 multiplier */ 2020 if (mult == 0) { 2021 mult = (xfer->endpoint->edesc-> 2022 wMaxPacketSize[1] >> 3) & 3; 2023 } 2024 /* range check */ 2025 if (mult > 2) 2026 mult = 3; 2027 else 2028 mult++; 2029 2030 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2031 2032 DPRINTF("MFINDEX=0x%08x\n", x); 2033 2034 switch (usbd_get_speed(xfer->xroot->udev)) { 2035 case USB_SPEED_FULL: 2036 shift = 3; 2037 temp.isoc_delta = 8; /* 1ms */ 2038 x += temp.isoc_delta - 1; 2039 x &= ~(temp.isoc_delta - 1); 2040 break; 2041 default: 2042 shift = usbd_xfer_get_fps_shift(xfer); 2043 temp.isoc_delta = 1U << shift; 2044 x += temp.isoc_delta - 1; 2045 x &= ~(temp.isoc_delta - 1); 2046 /* simple frame load balancing */ 2047 x += xfer->endpoint->usb_uframe; 2048 break; 2049 } 2050 2051 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2052 2053 if ((xfer->endpoint->is_synced == 0) || 2054 (y < (xfer->nframes << shift)) || 2055 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2056 /* 2057 * If there is data underflow or the pipe 2058 * queue is empty we schedule the transfer a 2059 * few frames ahead of the current frame 2060 * position. Else two isochronous transfers 2061 * might overlap. 2062 */ 2063 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2064 xfer->endpoint->is_synced = 1; 2065 temp.do_isoc_sync = 1; 2066 2067 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2068 } 2069 2070 /* compute isochronous completion time */ 2071 2072 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2073 2074 xfer->isoc_time_complete = 2075 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2076 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2077 2078 x = 0; 2079 temp.isoc_frame = xfer->endpoint->isoc_next; 2080 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2081 2082 xfer->endpoint->isoc_next += xfer->nframes << shift; 2083 2084 } else if (xfer->flags_int.control_xfr) { 2085 2086 /* check if we should prepend a setup message */ 2087 2088 if (xfer->flags_int.control_hdr) { 2089 2090 temp.len = xfer->frlengths[0]; 2091 temp.pc = xfer->frbuffers + 0; 2092 temp.shortpkt = temp.len ? 1 : 0; 2093 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2094 temp.direction = 0; 2095 2096 /* check for last frame */ 2097 if (xfer->nframes == 1) { 2098 /* no STATUS stage yet, SETUP is last */ 2099 if (xfer->flags_int.control_act) 2100 temp.last_frame = 1; 2101 } 2102 2103 xhci_setup_generic_chain_sub(&temp); 2104 } 2105 x = 1; 2106 mult = 1; 2107 temp.isoc_delta = 0; 2108 temp.isoc_frame = 0; 2109 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 2110 } else { 2111 x = 0; 2112 mult = 1; 2113 temp.isoc_delta = 0; 2114 temp.isoc_frame = 0; 2115 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2116 } 2117 2118 if (x != xfer->nframes) { 2119 /* set up page_cache pointer */ 2120 temp.pc = xfer->frbuffers + x; 2121 /* set endpoint direction */ 2122 temp.direction = UE_GET_DIR(xfer->endpointno); 2123 } 2124 2125 while (x != xfer->nframes) { 2126 2127 /* DATA0 / DATA1 message */ 2128 2129 temp.len = xfer->frlengths[x]; 2130 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2131 x != 0 && temp.multishort == 0); 2132 2133 x++; 2134 2135 if (x == xfer->nframes) { 2136 if (xfer->flags_int.control_xfr) { 2137 /* no STATUS stage yet, DATA is last */ 2138 if (xfer->flags_int.control_act) 2139 temp.last_frame = 1; 2140 } else { 2141 temp.last_frame = 1; 2142 } 2143 } 2144 if (temp.len == 0) { 2145 2146 /* make sure that we send an USB packet */ 2147 2148 temp.shortpkt = 0; 2149 2150 temp.tbc = 0; 2151 temp.tlbpc = mult - 1; 2152 2153 } else if (xfer->flags_int.isochronous_xfr) { 2154 2155 uint8_t tdpc; 2156 2157 /* 2158 * Isochronous transfers don't have short 2159 * packet termination: 2160 */ 2161 2162 temp.shortpkt = 1; 2163 2164 /* isochronous transfers have a transfer limit */ 2165 2166 if (temp.len > xfer->max_frame_size) 2167 temp.len = xfer->max_frame_size; 2168 2169 /* compute TD packet count */ 2170 tdpc = (temp.len + xfer->max_packet_size - 1) / 2171 xfer->max_packet_size; 2172 2173 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2174 temp.tlbpc = (tdpc % mult); 2175 2176 if (temp.tlbpc == 0) 2177 temp.tlbpc = mult - 1; 2178 else 2179 temp.tlbpc--; 2180 } else { 2181 2182 /* regular data transfer */ 2183 2184 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2185 } 2186 2187 xhci_setup_generic_chain_sub(&temp); 2188 2189 if (xfer->flags_int.isochronous_xfr) { 2190 temp.offset += xfer->frlengths[x - 1]; 2191 temp.isoc_frame += temp.isoc_delta; 2192 } else { 2193 /* get next Page Cache pointer */ 2194 temp.pc = xfer->frbuffers + x; 2195 } 2196 } 2197 2198 /* check if we should append a status stage */ 2199 2200 if (xfer->flags_int.control_xfr && 2201 !xfer->flags_int.control_act) { 2202 2203 /* 2204 * Send a DATA1 message and invert the current 2205 * endpoint direction. 2206 */ 2207 temp.step_td = (xfer->nframes != 0); 2208 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2209 temp.len = 0; 2210 temp.pc = NULL; 2211 temp.shortpkt = 0; 2212 temp.last_frame = 1; 2213 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2214 2215 xhci_setup_generic_chain_sub(&temp); 2216 } 2217 2218 td = temp.td; 2219 2220 /* must have at least one frame! */ 2221 2222 xfer->td_transfer_last = td; 2223 2224 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2225 } 2226 2227 static void 2228 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2229 { 2230 struct usb_page_search buf_res; 2231 struct xhci_dev_ctx_addr *pdctxa; 2232 2233 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2234 2235 pdctxa = buf_res.buffer; 2236 2237 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2238 2239 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2240 2241 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2242 } 2243 2244 static usb_error_t 2245 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2246 { 2247 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2248 struct usb_page_search buf_inp; 2249 struct xhci_input_dev_ctx *pinp; 2250 uint32_t temp; 2251 uint8_t index; 2252 uint8_t x; 2253 2254 index = udev->controller_slot_id; 2255 2256 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2257 2258 pinp = buf_inp.buffer; 2259 2260 if (drop) { 2261 mask &= XHCI_INCTX_NON_CTRL_MASK; 2262 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2263 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2264 } else { 2265 /* 2266 * Some hardware requires that we drop the endpoint 2267 * context before adding it again: 2268 */ 2269 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 2270 mask & XHCI_INCTX_NON_CTRL_MASK); 2271 2272 /* Add new endpoint context */ 2273 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2274 2275 /* find most significant set bit */ 2276 for (x = 31; x != 1; x--) { 2277 if (mask & (1 << x)) 2278 break; 2279 } 2280 2281 /* adjust */ 2282 x--; 2283 2284 /* figure out the maximum number of contexts */ 2285 if (x > sc->sc_hw.devs[index].context_num) 2286 sc->sc_hw.devs[index].context_num = x; 2287 else 2288 x = sc->sc_hw.devs[index].context_num; 2289 2290 /* update number of contexts */ 2291 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2292 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2293 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2294 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2295 } 2296 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2297 return (0); 2298 } 2299 2300 static usb_error_t 2301 xhci_configure_endpoint(struct usb_device *udev, 2302 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2303 uint16_t interval, uint8_t max_packet_count, 2304 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2305 uint16_t max_frame_size, uint8_t ep_mode) 2306 { 2307 struct usb_page_search buf_inp; 2308 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2309 struct xhci_input_dev_ctx *pinp; 2310 uint64_t ring_addr = pepext->physaddr; 2311 uint32_t temp; 2312 uint8_t index; 2313 uint8_t epno; 2314 uint8_t type; 2315 2316 index = udev->controller_slot_id; 2317 2318 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2319 2320 pinp = buf_inp.buffer; 2321 2322 epno = edesc->bEndpointAddress; 2323 type = edesc->bmAttributes & UE_XFERTYPE; 2324 2325 if (type == UE_CONTROL) 2326 epno |= UE_DIR_IN; 2327 2328 epno = XHCI_EPNO2EPID(epno); 2329 2330 if (epno == 0) 2331 return (USB_ERR_NO_PIPE); /* invalid */ 2332 2333 if (max_packet_count == 0) 2334 return (USB_ERR_BAD_BUFSIZE); 2335 2336 max_packet_count--; 2337 2338 if (mult == 0) 2339 return (USB_ERR_BAD_BUFSIZE); 2340 2341 /* store endpoint mode */ 2342 pepext->trb_ep_mode = ep_mode; 2343 usb_pc_cpu_flush(pepext->page_cache); 2344 2345 if (ep_mode == USB_EP_MODE_STREAMS) { 2346 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2347 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2348 XHCI_EPCTX_0_LSA_SET(1); 2349 2350 ring_addr += sizeof(struct xhci_trb) * 2351 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2352 } else { 2353 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2354 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2355 XHCI_EPCTX_0_LSA_SET(0); 2356 2357 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2358 } 2359 2360 switch (udev->speed) { 2361 case USB_SPEED_FULL: 2362 case USB_SPEED_LOW: 2363 /* 1ms -> 125us */ 2364 fps_shift += 3; 2365 break; 2366 default: 2367 break; 2368 } 2369 2370 switch (type) { 2371 case UE_INTERRUPT: 2372 if (fps_shift > 3) 2373 fps_shift--; 2374 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2375 break; 2376 case UE_ISOCHRONOUS: 2377 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2378 2379 switch (udev->speed) { 2380 case USB_SPEED_SUPER: 2381 if (mult > 3) 2382 mult = 3; 2383 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2384 max_packet_count /= mult; 2385 break; 2386 default: 2387 break; 2388 } 2389 break; 2390 default: 2391 break; 2392 } 2393 2394 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2395 2396 temp = 2397 XHCI_EPCTX_1_HID_SET(0) | 2398 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2399 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2400 2401 /* 2402 * Always enable the "three strikes and you are gone" feature 2403 * except for ISOCHRONOUS endpoints. This is suggested by 2404 * section 4.3.3 in the XHCI specification about device slot 2405 * initialisation. 2406 */ 2407 if (type != UE_ISOCHRONOUS) 2408 temp |= XHCI_EPCTX_1_CERR_SET(3); 2409 2410 switch (type) { 2411 case UE_CONTROL: 2412 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2413 break; 2414 case UE_ISOCHRONOUS: 2415 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2416 break; 2417 case UE_BULK: 2418 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2419 break; 2420 default: 2421 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2422 break; 2423 } 2424 2425 /* check for IN direction */ 2426 if (epno & 1) 2427 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2428 2429 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2430 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2431 2432 switch (edesc->bmAttributes & UE_XFERTYPE) { 2433 case UE_INTERRUPT: 2434 case UE_ISOCHRONOUS: 2435 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2436 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2437 max_frame_size)); 2438 break; 2439 case UE_CONTROL: 2440 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2441 break; 2442 default: 2443 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2444 break; 2445 } 2446 2447 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2448 2449 #ifdef USB_DEBUG 2450 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2451 #endif 2452 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2453 2454 return (0); /* success */ 2455 } 2456 2457 static usb_error_t 2458 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2459 { 2460 struct xhci_endpoint_ext *pepext; 2461 struct usb_endpoint_ss_comp_descriptor *ecomp; 2462 usb_stream_t x; 2463 2464 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2465 xfer->endpoint->edesc); 2466 2467 ecomp = xfer->endpoint->ecomp; 2468 2469 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2470 uint64_t temp; 2471 2472 /* halt any transfers */ 2473 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2474 2475 /* compute start of TRB ring for stream "x" */ 2476 temp = pepext->physaddr + 2477 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2478 XHCI_SCTX_0_SCT_SEC_TR_RING; 2479 2480 /* make tree structure */ 2481 pepext->trb[(XHCI_MAX_TRANSFERS * 2482 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2483 2484 /* reserved fields */ 2485 pepext->trb[(XHCI_MAX_TRANSFERS * 2486 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2487 pepext->trb[(XHCI_MAX_TRANSFERS * 2488 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2489 } 2490 usb_pc_cpu_flush(pepext->page_cache); 2491 2492 return (xhci_configure_endpoint(xfer->xroot->udev, 2493 xfer->endpoint->edesc, pepext, 2494 xfer->interval, xfer->max_packet_count, 2495 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2496 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2497 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2498 } 2499 2500 static usb_error_t 2501 xhci_configure_device(struct usb_device *udev) 2502 { 2503 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2504 struct usb_page_search buf_inp; 2505 struct usb_page_cache *pcinp; 2506 struct xhci_input_dev_ctx *pinp; 2507 struct usb_device *hubdev; 2508 uint32_t temp; 2509 uint32_t route; 2510 uint32_t rh_port; 2511 uint8_t is_hub; 2512 uint8_t index; 2513 uint8_t depth; 2514 2515 index = udev->controller_slot_id; 2516 2517 DPRINTF("index=%u\n", index); 2518 2519 pcinp = &sc->sc_hw.devs[index].input_pc; 2520 2521 usbd_get_page(pcinp, 0, &buf_inp); 2522 2523 pinp = buf_inp.buffer; 2524 2525 rh_port = 0; 2526 route = 0; 2527 2528 /* figure out route string and root HUB port number */ 2529 2530 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2531 2532 if (hubdev->parent_hub == NULL) 2533 break; 2534 2535 depth = hubdev->parent_hub->depth; 2536 2537 /* 2538 * NOTE: HS/FS/LS devices and the SS root HUB can have 2539 * more than 15 ports 2540 */ 2541 2542 rh_port = hubdev->port_no; 2543 2544 if (depth == 0) 2545 break; 2546 2547 if (rh_port > 15) 2548 rh_port = 15; 2549 2550 if (depth < 6) 2551 route |= rh_port << (4 * (depth - 1)); 2552 } 2553 2554 DPRINTF("Route=0x%08x\n", route); 2555 2556 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2557 XHCI_SCTX_0_CTX_NUM_SET( 2558 sc->sc_hw.devs[index].context_num + 1); 2559 2560 switch (udev->speed) { 2561 case USB_SPEED_LOW: 2562 temp |= XHCI_SCTX_0_SPEED_SET(2); 2563 if (udev->parent_hs_hub != NULL && 2564 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2565 UDPROTO_HSHUBMTT) { 2566 DPRINTF("Device inherits MTT\n"); 2567 temp |= XHCI_SCTX_0_MTT_SET(1); 2568 } 2569 break; 2570 case USB_SPEED_HIGH: 2571 temp |= XHCI_SCTX_0_SPEED_SET(3); 2572 if (sc->sc_hw.devs[index].nports != 0 && 2573 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2574 DPRINTF("HUB supports MTT\n"); 2575 temp |= XHCI_SCTX_0_MTT_SET(1); 2576 } 2577 break; 2578 case USB_SPEED_FULL: 2579 temp |= XHCI_SCTX_0_SPEED_SET(1); 2580 if (udev->parent_hs_hub != NULL && 2581 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2582 UDPROTO_HSHUBMTT) { 2583 DPRINTF("Device inherits MTT\n"); 2584 temp |= XHCI_SCTX_0_MTT_SET(1); 2585 } 2586 break; 2587 default: 2588 temp |= XHCI_SCTX_0_SPEED_SET(4); 2589 break; 2590 } 2591 2592 is_hub = sc->sc_hw.devs[index].nports != 0 && 2593 (udev->speed == USB_SPEED_SUPER || 2594 udev->speed == USB_SPEED_HIGH); 2595 2596 if (is_hub) 2597 temp |= XHCI_SCTX_0_HUB_SET(1); 2598 2599 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2600 2601 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2602 2603 if (is_hub) { 2604 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2605 sc->sc_hw.devs[index].nports); 2606 } 2607 2608 switch (udev->speed) { 2609 case USB_SPEED_SUPER: 2610 switch (sc->sc_hw.devs[index].state) { 2611 case XHCI_ST_ADDRESSED: 2612 case XHCI_ST_CONFIGURED: 2613 /* enable power save */ 2614 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2615 break; 2616 default: 2617 /* disable power save */ 2618 break; 2619 } 2620 break; 2621 default: 2622 break; 2623 } 2624 2625 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2626 2627 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2628 2629 if (is_hub) { 2630 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2631 sc->sc_hw.devs[index].tt); 2632 } 2633 2634 hubdev = udev->parent_hs_hub; 2635 2636 /* check if we should activate the transaction translator */ 2637 switch (udev->speed) { 2638 case USB_SPEED_FULL: 2639 case USB_SPEED_LOW: 2640 if (hubdev != NULL) { 2641 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2642 hubdev->controller_slot_id); 2643 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2644 udev->hs_port_no); 2645 } 2646 break; 2647 default: 2648 break; 2649 } 2650 2651 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2652 2653 /* 2654 * These fields should be initialized to zero, according to 2655 * XHCI section 6.2.2 - slot context: 2656 */ 2657 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2658 XHCI_SCTX_3_SLOT_STATE_SET(0); 2659 2660 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2661 2662 #ifdef USB_DEBUG 2663 xhci_dump_device(sc, &pinp->ctx_slot); 2664 #endif 2665 usb_pc_cpu_flush(pcinp); 2666 2667 return (0); /* success */ 2668 } 2669 2670 static usb_error_t 2671 xhci_alloc_device_ext(struct usb_device *udev) 2672 { 2673 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2674 struct usb_page_search buf_dev; 2675 struct usb_page_search buf_ep; 2676 struct xhci_trb *trb; 2677 struct usb_page_cache *pc; 2678 struct usb_page *pg; 2679 uint64_t addr; 2680 uint8_t index; 2681 uint8_t i; 2682 2683 index = udev->controller_slot_id; 2684 2685 pc = &sc->sc_hw.devs[index].device_pc; 2686 pg = &sc->sc_hw.devs[index].device_pg; 2687 2688 /* need to initialize the page cache */ 2689 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2690 2691 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2692 (2 * sizeof(struct xhci_dev_ctx)) : 2693 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2694 goto error; 2695 2696 usbd_get_page(pc, 0, &buf_dev); 2697 2698 pc = &sc->sc_hw.devs[index].input_pc; 2699 pg = &sc->sc_hw.devs[index].input_pg; 2700 2701 /* need to initialize the page cache */ 2702 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2703 2704 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2705 (2 * sizeof(struct xhci_input_dev_ctx)) : 2706 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2707 goto error; 2708 } 2709 2710 /* initialize all endpoint LINK TRBs */ 2711 2712 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2713 2714 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2715 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2716 2717 /* need to initialize the page cache */ 2718 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2719 2720 if (usb_pc_alloc_mem(pc, pg, 2721 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2722 goto error; 2723 } 2724 2725 /* lookup endpoint TRB ring */ 2726 usbd_get_page(pc, 0, &buf_ep); 2727 2728 /* get TRB pointer */ 2729 trb = buf_ep.buffer; 2730 trb += XHCI_MAX_TRANSFERS - 1; 2731 2732 /* get TRB start address */ 2733 addr = buf_ep.physaddr; 2734 2735 /* create LINK TRB */ 2736 trb->qwTrb0 = htole64(addr); 2737 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2738 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2739 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2740 2741 usb_pc_cpu_flush(pc); 2742 } 2743 2744 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2745 2746 return (0); 2747 2748 error: 2749 xhci_free_device_ext(udev); 2750 2751 return (USB_ERR_NOMEM); 2752 } 2753 2754 static void 2755 xhci_free_device_ext(struct usb_device *udev) 2756 { 2757 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2758 uint8_t index; 2759 uint8_t i; 2760 2761 index = udev->controller_slot_id; 2762 xhci_set_slot_pointer(sc, index, 0); 2763 2764 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2765 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2766 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2767 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2768 } 2769 2770 static struct xhci_endpoint_ext * 2771 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2772 { 2773 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2774 struct xhci_endpoint_ext *pepext; 2775 struct usb_page_cache *pc; 2776 struct usb_page_search buf_ep; 2777 uint8_t epno; 2778 uint8_t index; 2779 2780 epno = edesc->bEndpointAddress; 2781 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2782 epno |= UE_DIR_IN; 2783 2784 epno = XHCI_EPNO2EPID(epno); 2785 2786 index = udev->controller_slot_id; 2787 2788 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2789 2790 usbd_get_page(pc, 0, &buf_ep); 2791 2792 pepext = &sc->sc_hw.devs[index].endp[epno]; 2793 pepext->page_cache = pc; 2794 pepext->trb = buf_ep.buffer; 2795 pepext->physaddr = buf_ep.physaddr; 2796 2797 return (pepext); 2798 } 2799 2800 static void 2801 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2802 { 2803 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2804 uint8_t epno; 2805 uint8_t index; 2806 2807 epno = xfer->endpointno; 2808 if (xfer->flags_int.control_xfr) 2809 epno |= UE_DIR_IN; 2810 2811 epno = XHCI_EPNO2EPID(epno); 2812 index = xfer->xroot->udev->controller_slot_id; 2813 2814 if (xfer->xroot->udev->flags.self_suspended == 0) { 2815 XWRITE4(sc, door, XHCI_DOORBELL(index), 2816 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2817 } 2818 } 2819 2820 static void 2821 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2822 { 2823 struct xhci_endpoint_ext *pepext; 2824 2825 if (xfer->flags_int.bandwidth_reclaimed) { 2826 xfer->flags_int.bandwidth_reclaimed = 0; 2827 2828 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2829 xfer->endpoint->edesc); 2830 2831 pepext->trb_used[xfer->stream_id]--; 2832 2833 pepext->xfer[xfer->qh_pos] = NULL; 2834 2835 if (error && pepext->trb_running != 0) { 2836 pepext->trb_halted = 1; 2837 pepext->trb_running = 0; 2838 } 2839 } 2840 } 2841 2842 static usb_error_t 2843 xhci_transfer_insert(struct usb_xfer *xfer) 2844 { 2845 struct xhci_td *td_first; 2846 struct xhci_td *td_last; 2847 struct xhci_trb *trb_link; 2848 struct xhci_endpoint_ext *pepext; 2849 uint64_t addr; 2850 usb_stream_t id; 2851 uint8_t i; 2852 uint8_t inext; 2853 uint8_t trb_limit; 2854 2855 DPRINTFN(8, "\n"); 2856 2857 id = xfer->stream_id; 2858 2859 /* check if already inserted */ 2860 if (xfer->flags_int.bandwidth_reclaimed) { 2861 DPRINTFN(8, "Already in schedule\n"); 2862 return (0); 2863 } 2864 2865 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2866 xfer->endpoint->edesc); 2867 2868 td_first = xfer->td_transfer_first; 2869 td_last = xfer->td_transfer_last; 2870 addr = pepext->physaddr; 2871 2872 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2873 case UE_CONTROL: 2874 case UE_INTERRUPT: 2875 /* single buffered */ 2876 trb_limit = 1; 2877 break; 2878 default: 2879 /* multi buffered */ 2880 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2881 break; 2882 } 2883 2884 if (pepext->trb_used[id] >= trb_limit) { 2885 DPRINTFN(8, "Too many TDs queued.\n"); 2886 return (USB_ERR_NOMEM); 2887 } 2888 2889 /* check for stopped condition, after putting transfer on interrupt queue */ 2890 if (pepext->trb_running == 0) { 2891 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2892 2893 DPRINTFN(8, "Not running\n"); 2894 2895 /* start configuration */ 2896 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2897 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2898 return (0); 2899 } 2900 2901 pepext->trb_used[id]++; 2902 2903 /* get current TRB index */ 2904 i = pepext->trb_index[id]; 2905 2906 /* get next TRB index */ 2907 inext = (i + 1); 2908 2909 /* the last entry of the ring is a hardcoded link TRB */ 2910 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2911 inext = 0; 2912 2913 /* store next TRB index, before stream ID offset is added */ 2914 pepext->trb_index[id] = inext; 2915 2916 /* offset for stream */ 2917 i += id * XHCI_MAX_TRANSFERS; 2918 inext += id * XHCI_MAX_TRANSFERS; 2919 2920 /* compute terminating return address */ 2921 addr += (inext * sizeof(struct xhci_trb)); 2922 2923 /* compute link TRB pointer */ 2924 trb_link = td_last->td_trb + td_last->ntrb; 2925 2926 /* update next pointer of last link TRB */ 2927 trb_link->qwTrb0 = htole64(addr); 2928 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2929 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2930 XHCI_TRB_3_CYCLE_BIT | 2931 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2932 2933 #ifdef USB_DEBUG 2934 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2935 #endif 2936 usb_pc_cpu_flush(td_last->page_cache); 2937 2938 /* write ahead chain end marker */ 2939 2940 pepext->trb[inext].qwTrb0 = 0; 2941 pepext->trb[inext].dwTrb2 = 0; 2942 pepext->trb[inext].dwTrb3 = 0; 2943 2944 /* update next pointer of link TRB */ 2945 2946 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2947 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2948 2949 #ifdef USB_DEBUG 2950 xhci_dump_trb(&pepext->trb[i]); 2951 #endif 2952 usb_pc_cpu_flush(pepext->page_cache); 2953 2954 /* toggle cycle bit which activates the transfer chain */ 2955 2956 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2957 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2958 2959 usb_pc_cpu_flush(pepext->page_cache); 2960 2961 DPRINTF("qh_pos = %u\n", i); 2962 2963 pepext->xfer[i] = xfer; 2964 2965 xfer->qh_pos = i; 2966 2967 xfer->flags_int.bandwidth_reclaimed = 1; 2968 2969 xhci_endpoint_doorbell(xfer); 2970 2971 return (0); 2972 } 2973 2974 static void 2975 xhci_root_intr(struct xhci_softc *sc) 2976 { 2977 uint16_t i; 2978 2979 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2980 2981 /* clear any old interrupt data */ 2982 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2983 2984 for (i = 1; i <= sc->sc_noport; i++) { 2985 /* pick out CHANGE bits from the status register */ 2986 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2987 XHCI_PS_CSC | XHCI_PS_PEC | 2988 XHCI_PS_OCC | XHCI_PS_WRC | 2989 XHCI_PS_PRC | XHCI_PS_PLC | 2990 XHCI_PS_CEC)) { 2991 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2992 DPRINTF("port %d changed\n", i); 2993 } 2994 } 2995 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2996 sizeof(sc->sc_hub_idata)); 2997 } 2998 2999 /*------------------------------------------------------------------------* 3000 * xhci_device_done - XHCI done handler 3001 * 3002 * NOTE: This function can be called two times in a row on 3003 * the same USB transfer. From close and from interrupt. 3004 *------------------------------------------------------------------------*/ 3005 static void 3006 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 3007 { 3008 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 3009 xfer, xfer->endpoint, error); 3010 3011 /* remove transfer from HW queue */ 3012 xhci_transfer_remove(xfer, error); 3013 3014 /* dequeue transfer and start next transfer */ 3015 usbd_transfer_done(xfer, error); 3016 } 3017 3018 /*------------------------------------------------------------------------* 3019 * XHCI data transfer support (generic type) 3020 *------------------------------------------------------------------------*/ 3021 static void 3022 xhci_device_generic_open(struct usb_xfer *xfer) 3023 { 3024 if (xfer->flags_int.isochronous_xfr) { 3025 switch (xfer->xroot->udev->speed) { 3026 case USB_SPEED_FULL: 3027 break; 3028 default: 3029 usb_hs_bandwidth_alloc(xfer); 3030 break; 3031 } 3032 } 3033 } 3034 3035 static void 3036 xhci_device_generic_close(struct usb_xfer *xfer) 3037 { 3038 DPRINTF("\n"); 3039 3040 xhci_device_done(xfer, USB_ERR_CANCELLED); 3041 3042 if (xfer->flags_int.isochronous_xfr) { 3043 switch (xfer->xroot->udev->speed) { 3044 case USB_SPEED_FULL: 3045 break; 3046 default: 3047 usb_hs_bandwidth_free(xfer); 3048 break; 3049 } 3050 } 3051 } 3052 3053 static void 3054 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3055 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3056 { 3057 struct usb_xfer *xfer; 3058 3059 /* check if there is a current transfer */ 3060 xfer = ep->endpoint_q[stream_id].curr; 3061 if (xfer == NULL) 3062 return; 3063 3064 /* 3065 * Check if the current transfer is started and then pickup 3066 * the next one, if any. Else wait for next start event due to 3067 * block on failure feature. 3068 */ 3069 if (!xfer->flags_int.bandwidth_reclaimed) 3070 return; 3071 3072 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3073 if (xfer == NULL) { 3074 /* 3075 * In case of enter we have to consider that the 3076 * transfer is queued by the USB core after the enter 3077 * method is called. 3078 */ 3079 xfer = enter_xfer; 3080 3081 if (xfer == NULL) 3082 return; 3083 } 3084 3085 /* try to multi buffer */ 3086 xhci_transfer_insert(xfer); 3087 } 3088 3089 static void 3090 xhci_device_generic_enter(struct usb_xfer *xfer) 3091 { 3092 DPRINTF("\n"); 3093 3094 /* set up TD's and QH */ 3095 xhci_setup_generic_chain(xfer); 3096 3097 xhci_device_generic_multi_enter(xfer->endpoint, 3098 xfer->stream_id, xfer); 3099 } 3100 3101 static void 3102 xhci_device_generic_start(struct usb_xfer *xfer) 3103 { 3104 DPRINTF("\n"); 3105 3106 /* try to insert xfer on HW queue */ 3107 xhci_transfer_insert(xfer); 3108 3109 /* try to multi buffer */ 3110 xhci_device_generic_multi_enter(xfer->endpoint, 3111 xfer->stream_id, NULL); 3112 3113 /* add transfer last on interrupt queue */ 3114 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3115 3116 /* start timeout, if any */ 3117 if (xfer->timeout != 0) 3118 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3119 } 3120 3121 static const struct usb_pipe_methods xhci_device_generic_methods = 3122 { 3123 .open = xhci_device_generic_open, 3124 .close = xhci_device_generic_close, 3125 .enter = xhci_device_generic_enter, 3126 .start = xhci_device_generic_start, 3127 }; 3128 3129 /*------------------------------------------------------------------------* 3130 * xhci root HUB support 3131 *------------------------------------------------------------------------* 3132 * Simulate a hardware HUB by handling all the necessary requests. 3133 *------------------------------------------------------------------------*/ 3134 3135 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3136 3137 static const 3138 struct usb_device_descriptor xhci_devd = 3139 { 3140 .bLength = sizeof(xhci_devd), 3141 .bDescriptorType = UDESC_DEVICE, /* type */ 3142 HSETW(.bcdUSB, 0x0300), /* USB version */ 3143 .bDeviceClass = UDCLASS_HUB, /* class */ 3144 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3145 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3146 .bMaxPacketSize = 9, /* max packet size */ 3147 HSETW(.idVendor, 0x0000), /* vendor */ 3148 HSETW(.idProduct, 0x0000), /* product */ 3149 HSETW(.bcdDevice, 0x0100), /* device version */ 3150 .iManufacturer = 1, 3151 .iProduct = 2, 3152 .iSerialNumber = 0, 3153 .bNumConfigurations = 1, /* # of configurations */ 3154 }; 3155 3156 static const 3157 struct xhci_bos_desc xhci_bosd = { 3158 .bosd = { 3159 .bLength = sizeof(xhci_bosd.bosd), 3160 .bDescriptorType = UDESC_BOS, 3161 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3162 .bNumDeviceCaps = 3, 3163 }, 3164 .usb2extd = { 3165 .bLength = sizeof(xhci_bosd.usb2extd), 3166 .bDescriptorType = 1, 3167 .bDevCapabilityType = 2, 3168 .bmAttributes[0] = 2, 3169 }, 3170 .usbdcd = { 3171 .bLength = sizeof(xhci_bosd.usbdcd), 3172 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3173 .bDevCapabilityType = 3, 3174 .bmAttributes = 0, /* XXX */ 3175 HSETW(.wSpeedsSupported, 0x000C), 3176 .bFunctionalitySupport = 8, 3177 .bU1DevExitLat = 255, /* dummy - not used */ 3178 .wU2DevExitLat = { 0x00, 0x08 }, 3179 }, 3180 .cidd = { 3181 .bLength = sizeof(xhci_bosd.cidd), 3182 .bDescriptorType = 1, 3183 .bDevCapabilityType = 4, 3184 .bReserved = 0, 3185 .bContainerID = 0, /* XXX */ 3186 }, 3187 }; 3188 3189 static const 3190 struct xhci_config_desc xhci_confd = { 3191 .confd = { 3192 .bLength = sizeof(xhci_confd.confd), 3193 .bDescriptorType = UDESC_CONFIG, 3194 .wTotalLength[0] = sizeof(xhci_confd), 3195 .bNumInterface = 1, 3196 .bConfigurationValue = 1, 3197 .iConfiguration = 0, 3198 .bmAttributes = UC_SELF_POWERED, 3199 .bMaxPower = 0 /* max power */ 3200 }, 3201 .ifcd = { 3202 .bLength = sizeof(xhci_confd.ifcd), 3203 .bDescriptorType = UDESC_INTERFACE, 3204 .bNumEndpoints = 1, 3205 .bInterfaceClass = UICLASS_HUB, 3206 .bInterfaceSubClass = UISUBCLASS_HUB, 3207 .bInterfaceProtocol = 0, 3208 }, 3209 .endpd = { 3210 .bLength = sizeof(xhci_confd.endpd), 3211 .bDescriptorType = UDESC_ENDPOINT, 3212 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3213 .bmAttributes = UE_INTERRUPT, 3214 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3215 .bInterval = 255, 3216 }, 3217 .endpcd = { 3218 .bLength = sizeof(xhci_confd.endpcd), 3219 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3220 .bMaxBurst = 0, 3221 .bmAttributes = 0, 3222 }, 3223 }; 3224 3225 static const 3226 struct usb_hub_ss_descriptor xhci_hubd = { 3227 .bLength = sizeof(xhci_hubd), 3228 .bDescriptorType = UDESC_SS_HUB, 3229 }; 3230 3231 static usb_error_t 3232 xhci_roothub_exec(struct usb_device *udev, 3233 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3234 { 3235 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3236 const char *str_ptr; 3237 const void *ptr; 3238 uint32_t port; 3239 uint32_t v; 3240 uint16_t len; 3241 uint16_t i; 3242 uint16_t value; 3243 uint16_t index; 3244 uint8_t j; 3245 usb_error_t err; 3246 3247 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3248 3249 /* buffer reset */ 3250 ptr = (const void *)&sc->sc_hub_desc; 3251 len = 0; 3252 err = 0; 3253 3254 value = UGETW(req->wValue); 3255 index = UGETW(req->wIndex); 3256 3257 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3258 "wValue=0x%04x wIndex=0x%04x\n", 3259 req->bmRequestType, req->bRequest, 3260 UGETW(req->wLength), value, index); 3261 3262 #define C(x,y) ((x) | ((y) << 8)) 3263 switch (C(req->bRequest, req->bmRequestType)) { 3264 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3265 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3266 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3267 /* 3268 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3269 * for the integrated root hub. 3270 */ 3271 break; 3272 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3273 len = 1; 3274 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3275 break; 3276 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3277 switch (value >> 8) { 3278 case UDESC_DEVICE: 3279 if ((value & 0xff) != 0) { 3280 err = USB_ERR_IOERROR; 3281 goto done; 3282 } 3283 len = sizeof(xhci_devd); 3284 ptr = (const void *)&xhci_devd; 3285 break; 3286 3287 case UDESC_BOS: 3288 if ((value & 0xff) != 0) { 3289 err = USB_ERR_IOERROR; 3290 goto done; 3291 } 3292 len = sizeof(xhci_bosd); 3293 ptr = (const void *)&xhci_bosd; 3294 break; 3295 3296 case UDESC_CONFIG: 3297 if ((value & 0xff) != 0) { 3298 err = USB_ERR_IOERROR; 3299 goto done; 3300 } 3301 len = sizeof(xhci_confd); 3302 ptr = (const void *)&xhci_confd; 3303 break; 3304 3305 case UDESC_STRING: 3306 switch (value & 0xff) { 3307 case 0: /* Language table */ 3308 str_ptr = "\001"; 3309 break; 3310 3311 case 1: /* Vendor */ 3312 str_ptr = sc->sc_vendor; 3313 break; 3314 3315 case 2: /* Product */ 3316 str_ptr = "XHCI root HUB"; 3317 break; 3318 3319 default: 3320 str_ptr = ""; 3321 break; 3322 } 3323 3324 len = usb_make_str_desc( 3325 sc->sc_hub_desc.temp, 3326 sizeof(sc->sc_hub_desc.temp), 3327 str_ptr); 3328 break; 3329 3330 default: 3331 err = USB_ERR_IOERROR; 3332 goto done; 3333 } 3334 break; 3335 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3336 len = 1; 3337 sc->sc_hub_desc.temp[0] = 0; 3338 break; 3339 case C(UR_GET_STATUS, UT_READ_DEVICE): 3340 len = 2; 3341 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3342 break; 3343 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3344 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3345 len = 2; 3346 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3347 break; 3348 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3349 if (value >= XHCI_MAX_DEVICES) { 3350 err = USB_ERR_IOERROR; 3351 goto done; 3352 } 3353 break; 3354 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3355 if (value != 0 && value != 1) { 3356 err = USB_ERR_IOERROR; 3357 goto done; 3358 } 3359 sc->sc_conf = value; 3360 break; 3361 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3362 break; 3363 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3364 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3365 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3366 err = USB_ERR_IOERROR; 3367 goto done; 3368 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3369 break; 3370 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3371 break; 3372 /* Hub requests */ 3373 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3374 break; 3375 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3376 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3377 3378 if ((index < 1) || 3379 (index > sc->sc_noport)) { 3380 err = USB_ERR_IOERROR; 3381 goto done; 3382 } 3383 port = XHCI_PORTSC(index); 3384 3385 v = XREAD4(sc, oper, port); 3386 i = XHCI_PS_PLS_GET(v); 3387 v &= ~XHCI_PS_CLEAR; 3388 3389 switch (value) { 3390 case UHF_C_BH_PORT_RESET: 3391 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3392 break; 3393 case UHF_C_PORT_CONFIG_ERROR: 3394 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3395 break; 3396 case UHF_C_PORT_SUSPEND: 3397 case UHF_C_PORT_LINK_STATE: 3398 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3399 break; 3400 case UHF_C_PORT_CONNECTION: 3401 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3402 break; 3403 case UHF_C_PORT_ENABLE: 3404 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3405 break; 3406 case UHF_C_PORT_OVER_CURRENT: 3407 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3408 break; 3409 case UHF_C_PORT_RESET: 3410 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3411 break; 3412 case UHF_PORT_ENABLE: 3413 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3414 break; 3415 case UHF_PORT_POWER: 3416 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3417 break; 3418 case UHF_PORT_INDICATOR: 3419 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3420 break; 3421 case UHF_PORT_SUSPEND: 3422 3423 /* U3 -> U15 */ 3424 if (i == 3) { 3425 XWRITE4(sc, oper, port, v | 3426 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3427 } 3428 3429 /* wait 20ms for resume sequence to complete */ 3430 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3431 3432 /* U0 */ 3433 XWRITE4(sc, oper, port, v | 3434 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3435 break; 3436 default: 3437 err = USB_ERR_IOERROR; 3438 goto done; 3439 } 3440 break; 3441 3442 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3443 if ((value & 0xff) != 0) { 3444 err = USB_ERR_IOERROR; 3445 goto done; 3446 } 3447 3448 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3449 3450 sc->sc_hub_desc.hubd = xhci_hubd; 3451 3452 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3453 3454 if (XHCI_HCS0_PPC(v)) 3455 i = UHD_PWR_INDIVIDUAL; 3456 else 3457 i = UHD_PWR_GANGED; 3458 3459 if (XHCI_HCS0_PIND(v)) 3460 i |= UHD_PORT_IND; 3461 3462 i |= UHD_OC_INDIVIDUAL; 3463 3464 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3465 3466 /* see XHCI section 5.4.9: */ 3467 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3468 3469 for (j = 1; j <= sc->sc_noport; j++) { 3470 3471 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3472 if (v & XHCI_PS_DR) { 3473 sc->sc_hub_desc.hubd. 3474 DeviceRemovable[j / 8] |= 1U << (j % 8); 3475 } 3476 } 3477 len = sc->sc_hub_desc.hubd.bLength; 3478 break; 3479 3480 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3481 len = 16; 3482 memset(sc->sc_hub_desc.temp, 0, 16); 3483 break; 3484 3485 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3486 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3487 3488 if ((index < 1) || 3489 (index > sc->sc_noport)) { 3490 err = USB_ERR_IOERROR; 3491 goto done; 3492 } 3493 3494 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3495 3496 DPRINTFN(9, "port status=0x%08x\n", v); 3497 3498 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3499 3500 switch (XHCI_PS_SPEED_GET(v)) { 3501 case 3: 3502 i |= UPS_HIGH_SPEED; 3503 break; 3504 case 2: 3505 i |= UPS_LOW_SPEED; 3506 break; 3507 case 1: 3508 /* FULL speed */ 3509 break; 3510 default: 3511 i |= UPS_OTHER_SPEED; 3512 break; 3513 } 3514 3515 if (v & XHCI_PS_CCS) 3516 i |= UPS_CURRENT_CONNECT_STATUS; 3517 if (v & XHCI_PS_PED) 3518 i |= UPS_PORT_ENABLED; 3519 if (v & XHCI_PS_OCA) 3520 i |= UPS_OVERCURRENT_INDICATOR; 3521 if (v & XHCI_PS_PR) 3522 i |= UPS_RESET; 3523 if (v & XHCI_PS_PP) { 3524 /* 3525 * The USB 3.0 RH is using the 3526 * USB 2.0's power bit 3527 */ 3528 i |= UPS_PORT_POWER; 3529 } 3530 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3531 3532 i = 0; 3533 if (v & XHCI_PS_CSC) 3534 i |= UPS_C_CONNECT_STATUS; 3535 if (v & XHCI_PS_PEC) 3536 i |= UPS_C_PORT_ENABLED; 3537 if (v & XHCI_PS_OCC) 3538 i |= UPS_C_OVERCURRENT_INDICATOR; 3539 if (v & XHCI_PS_WRC) 3540 i |= UPS_C_BH_PORT_RESET; 3541 if (v & XHCI_PS_PRC) 3542 i |= UPS_C_PORT_RESET; 3543 if (v & XHCI_PS_PLC) 3544 i |= UPS_C_PORT_LINK_STATE; 3545 if (v & XHCI_PS_CEC) 3546 i |= UPS_C_PORT_CONFIG_ERROR; 3547 3548 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3549 len = sizeof(sc->sc_hub_desc.ps); 3550 break; 3551 3552 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3553 err = USB_ERR_IOERROR; 3554 goto done; 3555 3556 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3557 break; 3558 3559 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3560 3561 i = index >> 8; 3562 index &= 0x00FF; 3563 3564 if ((index < 1) || 3565 (index > sc->sc_noport)) { 3566 err = USB_ERR_IOERROR; 3567 goto done; 3568 } 3569 3570 port = XHCI_PORTSC(index); 3571 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3572 3573 switch (value) { 3574 case UHF_PORT_U1_TIMEOUT: 3575 if (XHCI_PS_SPEED_GET(v) != 4) { 3576 err = USB_ERR_IOERROR; 3577 goto done; 3578 } 3579 port = XHCI_PORTPMSC(index); 3580 v = XREAD4(sc, oper, port); 3581 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3582 v |= XHCI_PM3_U1TO_SET(i); 3583 XWRITE4(sc, oper, port, v); 3584 break; 3585 case UHF_PORT_U2_TIMEOUT: 3586 if (XHCI_PS_SPEED_GET(v) != 4) { 3587 err = USB_ERR_IOERROR; 3588 goto done; 3589 } 3590 port = XHCI_PORTPMSC(index); 3591 v = XREAD4(sc, oper, port); 3592 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3593 v |= XHCI_PM3_U2TO_SET(i); 3594 XWRITE4(sc, oper, port, v); 3595 break; 3596 case UHF_BH_PORT_RESET: 3597 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3598 break; 3599 case UHF_PORT_LINK_STATE: 3600 XWRITE4(sc, oper, port, v | 3601 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3602 /* 4ms settle time */ 3603 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3604 break; 3605 case UHF_PORT_ENABLE: 3606 DPRINTFN(3, "set port enable %d\n", index); 3607 break; 3608 case UHF_PORT_SUSPEND: 3609 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3610 j = XHCI_PS_SPEED_GET(v); 3611 if ((j < 1) || (j > 3)) { 3612 /* non-supported speed */ 3613 err = USB_ERR_IOERROR; 3614 goto done; 3615 } 3616 XWRITE4(sc, oper, port, v | 3617 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3618 break; 3619 case UHF_PORT_RESET: 3620 DPRINTFN(6, "reset port %d\n", index); 3621 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3622 break; 3623 case UHF_PORT_POWER: 3624 DPRINTFN(3, "set port power %d\n", index); 3625 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3626 break; 3627 case UHF_PORT_TEST: 3628 DPRINTFN(3, "set port test %d\n", index); 3629 break; 3630 case UHF_PORT_INDICATOR: 3631 DPRINTFN(3, "set port indicator %d\n", index); 3632 3633 v &= ~XHCI_PS_PIC_SET(3); 3634 v |= XHCI_PS_PIC_SET(1); 3635 3636 XWRITE4(sc, oper, port, v); 3637 break; 3638 default: 3639 err = USB_ERR_IOERROR; 3640 goto done; 3641 } 3642 break; 3643 3644 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3645 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3646 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3647 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3648 break; 3649 default: 3650 err = USB_ERR_IOERROR; 3651 goto done; 3652 } 3653 done: 3654 *plength = len; 3655 *pptr = ptr; 3656 return (err); 3657 } 3658 3659 static void 3660 xhci_xfer_setup(struct usb_setup_params *parm) 3661 { 3662 struct usb_page_search page_info; 3663 struct usb_page_cache *pc; 3664 struct xhci_softc *sc; 3665 struct usb_xfer *xfer; 3666 void *last_obj; 3667 uint32_t ntd; 3668 uint32_t n; 3669 3670 sc = XHCI_BUS2SC(parm->udev->bus); 3671 xfer = parm->curr_xfer; 3672 3673 /* 3674 * The proof for the "ntd" formula is illustrated like this: 3675 * 3676 * +------------------------------------+ 3677 * | | 3678 * | |remainder -> | 3679 * | +-----+---+ | 3680 * | | xxx | x | frm 0 | 3681 * | +-----+---++ | 3682 * | | xxx | xx | frm 1 | 3683 * | +-----+----+ | 3684 * | ... | 3685 * +------------------------------------+ 3686 * 3687 * "xxx" means a completely full USB transfer descriptor 3688 * 3689 * "x" and "xx" means a short USB packet 3690 * 3691 * For the remainder of an USB transfer modulo 3692 * "max_data_length" we need two USB transfer descriptors. 3693 * One to transfer the remaining data and one to finalise with 3694 * a zero length packet in case the "force_short_xfer" flag is 3695 * set. We only need two USB transfer descriptors in the case 3696 * where the transfer length of the first one is a factor of 3697 * "max_frame_size". The rest of the needed USB transfer 3698 * descriptors is given by the buffer size divided by the 3699 * maximum data payload. 3700 */ 3701 parm->hc_max_packet_size = 0x400; 3702 parm->hc_max_packet_count = 16 * 3; 3703 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3704 3705 xfer->flags_int.bdma_enable = 1; 3706 3707 usbd_transfer_setup_sub(parm); 3708 3709 if (xfer->flags_int.isochronous_xfr) { 3710 ntd = ((1 * xfer->nframes) 3711 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3712 } else if (xfer->flags_int.control_xfr) { 3713 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3714 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3715 } else { 3716 ntd = ((2 * xfer->nframes) 3717 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3718 } 3719 3720 alloc_dma_set: 3721 3722 if (parm->err) 3723 return; 3724 3725 /* 3726 * Allocate queue heads and transfer descriptors 3727 */ 3728 last_obj = NULL; 3729 3730 if (usbd_transfer_setup_sub_malloc( 3731 parm, &pc, sizeof(struct xhci_td), 3732 XHCI_TD_ALIGN, ntd)) { 3733 parm->err = USB_ERR_NOMEM; 3734 return; 3735 } 3736 if (parm->buf) { 3737 for (n = 0; n != ntd; n++) { 3738 struct xhci_td *td; 3739 3740 usbd_get_page(pc + n, 0, &page_info); 3741 3742 td = page_info.buffer; 3743 3744 /* init TD */ 3745 td->td_self = page_info.physaddr; 3746 td->obj_next = last_obj; 3747 td->page_cache = pc + n; 3748 3749 last_obj = td; 3750 3751 usb_pc_cpu_flush(pc + n); 3752 } 3753 } 3754 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3755 3756 if (!xfer->flags_int.curr_dma_set) { 3757 xfer->flags_int.curr_dma_set = 1; 3758 goto alloc_dma_set; 3759 } 3760 } 3761 3762 static usb_error_t 3763 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3764 { 3765 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3766 struct usb_page_search buf_inp; 3767 struct usb_device *udev; 3768 struct xhci_endpoint_ext *pepext; 3769 struct usb_endpoint_descriptor *edesc; 3770 struct usb_page_cache *pcinp; 3771 usb_error_t err; 3772 usb_stream_t stream_id; 3773 uint8_t index; 3774 uint8_t epno; 3775 3776 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3777 xfer->endpoint->edesc); 3778 3779 udev = xfer->xroot->udev; 3780 index = udev->controller_slot_id; 3781 3782 pcinp = &sc->sc_hw.devs[index].input_pc; 3783 3784 usbd_get_page(pcinp, 0, &buf_inp); 3785 3786 edesc = xfer->endpoint->edesc; 3787 3788 epno = edesc->bEndpointAddress; 3789 stream_id = xfer->stream_id; 3790 3791 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3792 epno |= UE_DIR_IN; 3793 3794 epno = XHCI_EPNO2EPID(epno); 3795 3796 if (epno == 0) 3797 return (USB_ERR_NO_PIPE); /* invalid */ 3798 3799 XHCI_CMD_LOCK(sc); 3800 3801 /* configure endpoint */ 3802 3803 err = xhci_configure_endpoint_by_xfer(xfer); 3804 3805 if (err != 0) { 3806 XHCI_CMD_UNLOCK(sc); 3807 return (err); 3808 } 3809 3810 /* 3811 * Get the endpoint into the stopped state according to the 3812 * endpoint context state diagram in the XHCI specification: 3813 */ 3814 3815 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3816 3817 if (err != 0) 3818 DPRINTF("Could not stop endpoint %u\n", epno); 3819 3820 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3821 3822 if (err != 0) 3823 DPRINTF("Could not reset endpoint %u\n", epno); 3824 3825 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3826 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3827 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3828 stream_id, epno, index); 3829 3830 if (err != 0) 3831 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3832 3833 /* 3834 * Get the endpoint into the running state according to the 3835 * endpoint context state diagram in the XHCI specification: 3836 */ 3837 3838 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3839 3840 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3841 3842 if (err != 0) 3843 DPRINTF("Could not configure endpoint %u\n", epno); 3844 3845 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3846 3847 if (err != 0) 3848 DPRINTF("Could not configure endpoint %u\n", epno); 3849 3850 XHCI_CMD_UNLOCK(sc); 3851 3852 return (0); 3853 } 3854 3855 static void 3856 xhci_xfer_unsetup(struct usb_xfer *xfer) 3857 { 3858 return; 3859 } 3860 3861 static void 3862 xhci_start_dma_delay(struct usb_xfer *xfer) 3863 { 3864 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3865 3866 /* put transfer on interrupt queue (again) */ 3867 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3868 3869 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3870 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3871 } 3872 3873 static void 3874 xhci_configure_msg(struct usb_proc_msg *pm) 3875 { 3876 struct xhci_softc *sc; 3877 struct xhci_endpoint_ext *pepext; 3878 struct usb_xfer *xfer; 3879 3880 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3881 3882 restart: 3883 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3884 3885 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3886 xfer->endpoint->edesc); 3887 3888 if ((pepext->trb_halted != 0) || 3889 (pepext->trb_running == 0)) { 3890 3891 uint16_t i; 3892 3893 /* clear halted and running */ 3894 pepext->trb_halted = 0; 3895 pepext->trb_running = 0; 3896 3897 /* nuke remaining buffered transfers */ 3898 3899 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3900 XHCI_MAX_STREAMS); i++) { 3901 /* 3902 * NOTE: We need to use the timeout 3903 * error code here else existing 3904 * isochronous clients can get 3905 * confused: 3906 */ 3907 if (pepext->xfer[i] != NULL) { 3908 xhci_device_done(pepext->xfer[i], 3909 USB_ERR_TIMEOUT); 3910 } 3911 } 3912 3913 /* 3914 * NOTE: The USB transfer cannot vanish in 3915 * this state! 3916 */ 3917 3918 USB_BUS_UNLOCK(&sc->sc_bus); 3919 3920 xhci_configure_reset_endpoint(xfer); 3921 3922 USB_BUS_LOCK(&sc->sc_bus); 3923 3924 /* check if halted is still cleared */ 3925 if (pepext->trb_halted == 0) { 3926 pepext->trb_running = 1; 3927 memset(pepext->trb_index, 0, 3928 sizeof(pepext->trb_index)); 3929 } 3930 goto restart; 3931 } 3932 3933 if (xfer->flags_int.did_dma_delay) { 3934 3935 /* remove transfer from interrupt queue (again) */ 3936 usbd_transfer_dequeue(xfer); 3937 3938 /* we are finally done */ 3939 usb_dma_delay_done_cb(xfer); 3940 3941 /* queue changed - restart */ 3942 goto restart; 3943 } 3944 } 3945 3946 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3947 3948 /* try to insert xfer on HW queue */ 3949 xhci_transfer_insert(xfer); 3950 3951 /* try to multi buffer */ 3952 xhci_device_generic_multi_enter(xfer->endpoint, 3953 xfer->stream_id, NULL); 3954 } 3955 } 3956 3957 static void 3958 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3959 struct usb_endpoint *ep) 3960 { 3961 struct xhci_endpoint_ext *pepext; 3962 3963 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3964 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3965 3966 if (udev->parent_hub == NULL) { 3967 /* root HUB has special endpoint handling */ 3968 return; 3969 } 3970 3971 ep->methods = &xhci_device_generic_methods; 3972 3973 pepext = xhci_get_endpoint_ext(udev, edesc); 3974 3975 USB_BUS_LOCK(udev->bus); 3976 pepext->trb_halted = 1; 3977 pepext->trb_running = 0; 3978 USB_BUS_UNLOCK(udev->bus); 3979 } 3980 3981 static void 3982 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3983 { 3984 3985 } 3986 3987 static void 3988 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3989 { 3990 struct xhci_endpoint_ext *pepext; 3991 3992 DPRINTF("\n"); 3993 3994 if (udev->flags.usb_mode != USB_MODE_HOST) { 3995 /* not supported */ 3996 return; 3997 } 3998 if (udev->parent_hub == NULL) { 3999 /* root HUB has special endpoint handling */ 4000 return; 4001 } 4002 4003 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 4004 4005 USB_BUS_LOCK(udev->bus); 4006 pepext->trb_halted = 1; 4007 pepext->trb_running = 0; 4008 USB_BUS_UNLOCK(udev->bus); 4009 } 4010 4011 static usb_error_t 4012 xhci_device_init(struct usb_device *udev) 4013 { 4014 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4015 usb_error_t err; 4016 uint8_t temp; 4017 4018 /* no init for root HUB */ 4019 if (udev->parent_hub == NULL) 4020 return (0); 4021 4022 XHCI_CMD_LOCK(sc); 4023 4024 /* set invalid default */ 4025 4026 udev->controller_slot_id = sc->sc_noslot + 1; 4027 4028 /* try to get a new slot ID from the XHCI */ 4029 4030 err = xhci_cmd_enable_slot(sc, &temp); 4031 4032 if (err) { 4033 XHCI_CMD_UNLOCK(sc); 4034 return (err); 4035 } 4036 4037 if (temp > sc->sc_noslot) { 4038 XHCI_CMD_UNLOCK(sc); 4039 return (USB_ERR_BAD_ADDRESS); 4040 } 4041 4042 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4043 DPRINTF("slot %u already allocated.\n", temp); 4044 XHCI_CMD_UNLOCK(sc); 4045 return (USB_ERR_BAD_ADDRESS); 4046 } 4047 4048 /* store slot ID for later reference */ 4049 4050 udev->controller_slot_id = temp; 4051 4052 /* reset data structure */ 4053 4054 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4055 4056 /* set mark slot allocated */ 4057 4058 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4059 4060 err = xhci_alloc_device_ext(udev); 4061 4062 XHCI_CMD_UNLOCK(sc); 4063 4064 /* get device into default state */ 4065 4066 if (err == 0) 4067 err = xhci_set_address(udev, NULL, 0); 4068 4069 return (err); 4070 } 4071 4072 static void 4073 xhci_device_uninit(struct usb_device *udev) 4074 { 4075 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4076 uint8_t index; 4077 4078 /* no init for root HUB */ 4079 if (udev->parent_hub == NULL) 4080 return; 4081 4082 XHCI_CMD_LOCK(sc); 4083 4084 index = udev->controller_slot_id; 4085 4086 if (index <= sc->sc_noslot) { 4087 xhci_cmd_disable_slot(sc, index); 4088 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4089 4090 /* free device extension */ 4091 xhci_free_device_ext(udev); 4092 } 4093 4094 XHCI_CMD_UNLOCK(sc); 4095 } 4096 4097 static void 4098 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4099 { 4100 /* 4101 * Wait until the hardware has finished any possible use of 4102 * the transfer descriptor(s) 4103 */ 4104 *pus = 2048; /* microseconds */ 4105 } 4106 4107 static void 4108 xhci_device_resume(struct usb_device *udev) 4109 { 4110 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4111 uint8_t index; 4112 uint8_t n; 4113 uint8_t p; 4114 4115 DPRINTF("\n"); 4116 4117 /* check for root HUB */ 4118 if (udev->parent_hub == NULL) 4119 return; 4120 4121 index = udev->controller_slot_id; 4122 4123 XHCI_CMD_LOCK(sc); 4124 4125 /* blindly resume all endpoints */ 4126 4127 USB_BUS_LOCK(udev->bus); 4128 4129 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4130 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4131 XWRITE4(sc, door, XHCI_DOORBELL(index), 4132 n | XHCI_DB_SID_SET(p)); 4133 } 4134 } 4135 4136 USB_BUS_UNLOCK(udev->bus); 4137 4138 XHCI_CMD_UNLOCK(sc); 4139 } 4140 4141 static void 4142 xhci_device_suspend(struct usb_device *udev) 4143 { 4144 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4145 uint8_t index; 4146 uint8_t n; 4147 usb_error_t err; 4148 4149 DPRINTF("\n"); 4150 4151 /* check for root HUB */ 4152 if (udev->parent_hub == NULL) 4153 return; 4154 4155 index = udev->controller_slot_id; 4156 4157 XHCI_CMD_LOCK(sc); 4158 4159 /* blindly suspend all endpoints */ 4160 4161 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4162 err = xhci_cmd_stop_ep(sc, 1, n, index); 4163 if (err != 0) { 4164 DPRINTF("Failed to suspend endpoint " 4165 "%u on slot %u (ignored).\n", n, index); 4166 } 4167 } 4168 4169 XHCI_CMD_UNLOCK(sc); 4170 } 4171 4172 static void 4173 xhci_set_hw_power(struct usb_bus *bus) 4174 { 4175 DPRINTF("\n"); 4176 } 4177 4178 static void 4179 xhci_device_state_change(struct usb_device *udev) 4180 { 4181 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4182 struct usb_page_search buf_inp; 4183 usb_error_t err; 4184 uint8_t index; 4185 4186 /* check for root HUB */ 4187 if (udev->parent_hub == NULL) 4188 return; 4189 4190 index = udev->controller_slot_id; 4191 4192 DPRINTF("\n"); 4193 4194 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4195 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4196 &sc->sc_hw.devs[index].tt); 4197 if (err != 0) 4198 sc->sc_hw.devs[index].nports = 0; 4199 } 4200 4201 XHCI_CMD_LOCK(sc); 4202 4203 switch (usb_get_device_state(udev)) { 4204 case USB_STATE_POWERED: 4205 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4206 break; 4207 4208 /* set default state */ 4209 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4210 4211 /* reset number of contexts */ 4212 sc->sc_hw.devs[index].context_num = 0; 4213 4214 err = xhci_cmd_reset_dev(sc, index); 4215 4216 if (err != 0) { 4217 DPRINTF("Device reset failed " 4218 "for slot %u.\n", index); 4219 } 4220 break; 4221 4222 case USB_STATE_ADDRESSED: 4223 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4224 break; 4225 4226 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4227 4228 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4229 4230 if (err) { 4231 DPRINTF("Failed to deconfigure " 4232 "slot %u.\n", index); 4233 } 4234 break; 4235 4236 case USB_STATE_CONFIGURED: 4237 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4238 break; 4239 4240 /* set configured state */ 4241 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4242 4243 /* reset number of contexts */ 4244 sc->sc_hw.devs[index].context_num = 0; 4245 4246 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4247 4248 xhci_configure_mask(udev, 3, 0); 4249 4250 err = xhci_configure_device(udev); 4251 if (err != 0) { 4252 DPRINTF("Could not configure device " 4253 "at slot %u.\n", index); 4254 } 4255 4256 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4257 if (err != 0) { 4258 DPRINTF("Could not evaluate device " 4259 "context at slot %u.\n", index); 4260 } 4261 break; 4262 4263 default: 4264 break; 4265 } 4266 XHCI_CMD_UNLOCK(sc); 4267 } 4268 4269 static usb_error_t 4270 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4271 uint8_t ep_mode) 4272 { 4273 switch (ep_mode) { 4274 case USB_EP_MODE_DEFAULT: 4275 return (0); 4276 case USB_EP_MODE_STREAMS: 4277 if (xhcistreams == 0 || 4278 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4279 udev->speed != USB_SPEED_SUPER) 4280 return (USB_ERR_INVAL); 4281 return (0); 4282 default: 4283 return (USB_ERR_INVAL); 4284 } 4285 } 4286 4287 static const struct usb_bus_methods xhci_bus_methods = { 4288 .endpoint_init = xhci_ep_init, 4289 .endpoint_uninit = xhci_ep_uninit, 4290 .xfer_setup = xhci_xfer_setup, 4291 .xfer_unsetup = xhci_xfer_unsetup, 4292 .get_dma_delay = xhci_get_dma_delay, 4293 .device_init = xhci_device_init, 4294 .device_uninit = xhci_device_uninit, 4295 .device_resume = xhci_device_resume, 4296 .device_suspend = xhci_device_suspend, 4297 .set_hw_power = xhci_set_hw_power, 4298 .roothub_exec = xhci_roothub_exec, 4299 .xfer_poll = xhci_do_poll, 4300 .start_dma_delay = xhci_start_dma_delay, 4301 .set_address = xhci_set_address, 4302 .clear_stall = xhci_ep_clear_stall, 4303 .device_state_change = xhci_device_state_change, 4304 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4305 .set_endpoint_mode = xhci_set_endpoint_mode, 4306 }; 4307