1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010-2022 Hans Petter Selasky 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 30 * 31 * The XHCI 1.0 spec can be found at 32 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 33 * and the USB 3.0 spec at 34 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 35 */ 36 37 /* 38 * A few words about the design implementation: This driver emulates 39 * the concept about TDs which is found in EHCI specification. This 40 * way we achieve that the USB controller drivers look similar to 41 * eachother which makes it easier to understand the code. 42 */ 43 44 #ifdef USB_GLOBAL_INCLUDE_FILE 45 #include USB_GLOBAL_INCLUDE_FILE 46 #else 47 #include <sys/stdint.h> 48 #include <sys/stddef.h> 49 #include <sys/param.h> 50 #include <sys/queue.h> 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 #include <sys/kernel.h> 54 #include <sys/bus.h> 55 #include <sys/module.h> 56 #include <sys/lock.h> 57 #include <sys/mutex.h> 58 #include <sys/condvar.h> 59 #include <sys/sysctl.h> 60 #include <sys/sx.h> 61 #include <sys/unistd.h> 62 #include <sys/callout.h> 63 #include <sys/malloc.h> 64 #include <sys/priv.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 69 #define USB_DEBUG_VAR xhcidebug 70 71 #include <dev/usb/usb_core.h> 72 #include <dev/usb/usb_debug.h> 73 #include <dev/usb/usb_busdma.h> 74 #include <dev/usb/usb_process.h> 75 #include <dev/usb/usb_transfer.h> 76 #include <dev/usb/usb_device.h> 77 #include <dev/usb/usb_hub.h> 78 #include <dev/usb/usb_util.h> 79 80 #include <dev/usb/usb_controller.h> 81 #include <dev/usb/usb_bus.h> 82 #endif /* USB_GLOBAL_INCLUDE_FILE */ 83 84 #include <dev/usb/controller/xhci.h> 85 #include <dev/usb/controller/xhcireg.h> 86 87 #define XHCI_BUS2SC(bus) \ 88 __containerof(bus, struct xhci_softc, sc_bus) 89 90 #define XHCI_GET_CTX(sc, which, field, ptr) \ 91 ((sc)->sc_ctx_is_64_byte ? \ 92 &((struct which##64 *)(ptr))->field.ctx : \ 93 &((struct which *)(ptr))->field) 94 95 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 96 "USB XHCI"); 97 98 static int xhcistreams; 99 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN, 100 &xhcistreams, 0, "Set to enable streams mode support"); 101 102 static int xhcictlquirk = 1; 103 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlquirk, CTLFLAG_RWTUN, 104 &xhcictlquirk, 0, "Set to enable control endpoint quirk"); 105 106 static int xhcidcepquirk; 107 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dcepquirk, CTLFLAG_RWTUN, 108 &xhcidcepquirk, 0, "Set to disable endpoint deconfigure command"); 109 110 #ifdef USB_DEBUG 111 static int xhcidebug; 112 static int xhciroute; 113 static int xhcipolling; 114 static int xhcidma32; 115 static int xhcictlstep; 116 117 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN, 118 &xhcidebug, 0, "Debug level"); 119 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN, 120 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller"); 121 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN, 122 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller"); 123 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN, 124 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller"); 125 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN, 126 &xhcictlstep, 0, "Set to enable control endpoint status stage stepping"); 127 #else 128 #define xhciroute 0 129 #define xhcidma32 0 130 #define xhcictlstep 0 131 #endif 132 133 #define XHCI_INTR_ENDPT 1 134 135 static void xhci_do_poll(struct usb_bus *); 136 static void xhci_device_done(struct usb_xfer *, usb_error_t); 137 static void xhci_get_xecp(struct xhci_softc *); 138 static void xhci_root_intr(struct xhci_softc *); 139 static void xhci_free_device_ext(struct usb_device *); 140 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 141 struct usb_endpoint_descriptor *); 142 static usb_proc_callback_t xhci_configure_msg; 143 static usb_error_t xhci_configure_device(struct usb_device *); 144 static usb_error_t xhci_configure_endpoint(struct usb_device *, 145 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 146 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 147 uint8_t); 148 static usb_error_t xhci_configure_mask(struct usb_device *, 149 uint32_t, uint8_t); 150 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 151 uint64_t, uint8_t); 152 static void xhci_endpoint_doorbell(struct usb_xfer *); 153 154 static const struct usb_bus_methods xhci_bus_methods; 155 156 #ifdef USB_DEBUG 157 static void 158 xhci_dump_trb(struct xhci_trb *trb) 159 { 160 DPRINTFN(5, "trb = %p\n", trb); 161 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 162 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 163 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 164 } 165 166 static void 167 xhci_dump_endpoint(struct xhci_endp_ctx *pep) 168 { 169 DPRINTFN(5, "pep = %p\n", pep); 170 DPRINTFN(5, "dwEpCtx0=0x%08x\n", le32toh(pep->dwEpCtx0)); 171 DPRINTFN(5, "dwEpCtx1=0x%08x\n", le32toh(pep->dwEpCtx1)); 172 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)le64toh(pep->qwEpCtx2)); 173 DPRINTFN(5, "dwEpCtx4=0x%08x\n", le32toh(pep->dwEpCtx4)); 174 DPRINTFN(5, "dwEpCtx5=0x%08x\n", le32toh(pep->dwEpCtx5)); 175 DPRINTFN(5, "dwEpCtx6=0x%08x\n", le32toh(pep->dwEpCtx6)); 176 DPRINTFN(5, "dwEpCtx7=0x%08x\n", le32toh(pep->dwEpCtx7)); 177 } 178 179 static void 180 xhci_dump_device(struct xhci_slot_ctx *psl) 181 { 182 DPRINTFN(5, "psl = %p\n", psl); 183 DPRINTFN(5, "dwSctx0=0x%08x\n", le32toh(psl->dwSctx0)); 184 DPRINTFN(5, "dwSctx1=0x%08x\n", le32toh(psl->dwSctx1)); 185 DPRINTFN(5, "dwSctx2=0x%08x\n", le32toh(psl->dwSctx2)); 186 DPRINTFN(5, "dwSctx3=0x%08x\n", le32toh(psl->dwSctx3)); 187 } 188 #endif 189 190 uint8_t 191 xhci_use_polling(void) 192 { 193 #ifdef USB_DEBUG 194 return (xhcipolling != 0); 195 #else 196 return (0); 197 #endif 198 } 199 200 static void 201 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 202 { 203 struct xhci_softc *sc = XHCI_BUS2SC(bus); 204 uint16_t i; 205 206 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 207 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 208 209 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 210 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 211 212 for (i = 0; i != sc->sc_noscratch; i++) { 213 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 214 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 215 } 216 } 217 218 static int 219 xhci_reset_command_queue_locked(struct xhci_softc *sc) 220 { 221 struct usb_page_search buf_res; 222 struct xhci_hw_root *phwr; 223 uint64_t addr; 224 uint32_t temp; 225 226 DPRINTF("\n"); 227 228 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 229 if (temp & XHCI_CRCR_LO_CRR) { 230 DPRINTF("Command ring running\n"); 231 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 232 233 /* 234 * Try to abort the last command as per section 235 * 4.6.1.2 "Aborting a Command" of the XHCI 236 * specification: 237 */ 238 239 /* stop and cancel */ 240 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 241 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 242 243 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 244 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 245 246 /* wait 250ms */ 247 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 248 249 /* check if command ring is still running */ 250 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 251 if (temp & XHCI_CRCR_LO_CRR) { 252 DPRINTF("Comand ring still running\n"); 253 return (USB_ERR_IOERROR); 254 } 255 } 256 257 /* reset command ring */ 258 sc->sc_command_ccs = 1; 259 sc->sc_command_idx = 0; 260 261 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 262 263 /* set up command ring control base address */ 264 addr = buf_res.physaddr; 265 phwr = buf_res.buffer; 266 addr += __offsetof(struct xhci_hw_root, hwr_commands[0]); 267 268 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 269 270 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 271 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 272 273 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 274 275 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 276 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 277 278 return (0); 279 } 280 281 usb_error_t 282 xhci_start_controller(struct xhci_softc *sc) 283 { 284 struct usb_page_search buf_res; 285 struct xhci_hw_root *phwr; 286 struct xhci_dev_ctx_addr *pdctxa; 287 usb_error_t err; 288 uint64_t addr; 289 uint32_t temp; 290 uint16_t i; 291 292 DPRINTF("\n"); 293 294 sc->sc_event_ccs = 1; 295 sc->sc_event_idx = 0; 296 sc->sc_command_ccs = 1; 297 sc->sc_command_idx = 0; 298 299 err = xhci_reset_controller(sc); 300 if (err) 301 return (err); 302 303 /* set up number of device slots */ 304 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 305 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 306 307 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 308 309 temp = XREAD4(sc, oper, XHCI_USBSTS); 310 311 /* clear interrupts */ 312 XWRITE4(sc, oper, XHCI_USBSTS, temp); 313 /* disable all device notifications */ 314 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 315 316 /* set up device context base address */ 317 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 318 pdctxa = buf_res.buffer; 319 memset(pdctxa, 0, sizeof(*pdctxa)); 320 321 addr = buf_res.physaddr; 322 addr += __offsetof(struct xhci_dev_ctx_addr, qwSpBufPtr[0]); 323 324 /* slot 0 points to the table of scratchpad pointers */ 325 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 326 327 for (i = 0; i != sc->sc_noscratch; i++) { 328 struct usb_page_search buf_scp; 329 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 330 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 331 } 332 333 addr = buf_res.physaddr; 334 335 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 336 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 337 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 338 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 339 340 /* set up event table size */ 341 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 342 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max); 343 344 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max)); 345 346 /* set up interrupt rate */ 347 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 348 349 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 350 351 phwr = buf_res.buffer; 352 addr = buf_res.physaddr; 353 addr += __offsetof(struct xhci_hw_root, hwr_events[0]); 354 355 /* reset hardware root structure */ 356 memset(phwr, 0, sizeof(*phwr)); 357 358 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 359 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 360 361 /* 362 * PR 237666: 363 * 364 * According to the XHCI specification, the XWRITE4's to 365 * XHCI_ERSTBA_LO and _HI lead to the XHCI to copy the 366 * qwEvrsTablePtr and dwEvrsTableSize values above at that 367 * time, as the XHCI initializes its event ring support. This 368 * is before the event ring starts to pay attention to the 369 * RUN/STOP bit. Thus, make sure the values are observable to 370 * the XHCI before that point. 371 */ 372 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 373 374 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 375 376 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 377 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 378 379 addr = buf_res.physaddr; 380 381 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 382 383 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 384 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 385 386 /* set up interrupter registers */ 387 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 388 temp |= XHCI_IMAN_INTR_ENA; 389 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 390 391 /* set up command ring control base address */ 392 addr = buf_res.physaddr; 393 addr += __offsetof(struct xhci_hw_root, hwr_commands[0]); 394 395 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 396 397 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 398 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 399 400 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 401 402 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 403 404 /* Go! */ 405 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 406 XHCI_CMD_INTE | XHCI_CMD_HSEE); 407 408 for (i = 0; i != 100; i++) { 409 usb_pause_mtx(NULL, hz / 100); 410 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 411 if (!temp) 412 break; 413 } 414 if (temp) { 415 XWRITE4(sc, oper, XHCI_USBCMD, 0); 416 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 417 return (USB_ERR_IOERROR); 418 } 419 420 /* catch any lost interrupts */ 421 xhci_do_poll(&sc->sc_bus); 422 423 if (sc->sc_port_route != NULL) { 424 /* Route all ports to the XHCI by default */ 425 sc->sc_port_route(sc->sc_bus.parent, 426 ~xhciroute, xhciroute); 427 } 428 return (0); 429 } 430 431 usb_error_t 432 xhci_halt_controller(struct xhci_softc *sc) 433 { 434 uint32_t temp; 435 uint16_t i; 436 437 DPRINTF("\n"); 438 439 sc->sc_capa_off = 0; 440 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 441 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 442 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 443 444 /* Halt controller */ 445 XWRITE4(sc, oper, XHCI_USBCMD, 0); 446 447 for (i = 0; i != 100; i++) { 448 usb_pause_mtx(NULL, hz / 100); 449 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 450 if (temp) 451 break; 452 } 453 454 if (!temp) { 455 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 456 return (USB_ERR_IOERROR); 457 } 458 return (0); 459 } 460 461 usb_error_t 462 xhci_reset_controller(struct xhci_softc *sc) 463 { 464 uint32_t temp = 0; 465 uint16_t i; 466 467 DPRINTF("\n"); 468 469 /* Reset controller */ 470 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 471 472 for (i = 0; i != 100; i++) { 473 usb_pause_mtx(NULL, hz / 100); 474 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 475 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 476 if (!temp) 477 break; 478 } 479 480 if (temp) { 481 device_printf(sc->sc_bus.parent, "Controller " 482 "reset timeout.\n"); 483 return (USB_ERR_IOERROR); 484 } 485 return (0); 486 } 487 488 usb_error_t 489 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32) 490 { 491 uint32_t temp; 492 493 DPRINTF("\n"); 494 495 /* initialize some bus fields */ 496 sc->sc_bus.parent = self; 497 498 /* set the bus revision */ 499 sc->sc_bus.usbrev = USB_REV_3_0; 500 501 /* set up the bus struct */ 502 sc->sc_bus.methods = &xhci_bus_methods; 503 504 /* set up devices array */ 505 sc->sc_bus.devices = sc->sc_devices; 506 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 507 508 /* set default cycle state in case of early interrupts */ 509 sc->sc_event_ccs = 1; 510 sc->sc_command_ccs = 1; 511 512 /* set up bus space offsets */ 513 sc->sc_capa_off = 0; 514 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 515 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 516 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 517 518 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 519 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 520 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 521 522 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 523 524 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 525 device_printf(sc->sc_bus.parent, "Controller does " 526 "not support 4K page size.\n"); 527 return (ENXIO); 528 } 529 530 temp = XREAD4(sc, capa, XHCI_HCCPARAMS1); 531 532 DPRINTF("HCS0 = 0x%08x\n", temp); 533 534 /* set up context size */ 535 if (XHCI_HCS0_CSZ(temp)) { 536 sc->sc_ctx_is_64_byte = 1; 537 } else { 538 sc->sc_ctx_is_64_byte = 0; 539 } 540 541 /* get DMA bits */ 542 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && 543 xhcidma32 == 0 && dma32 == 0) ? 64 : 32; 544 545 device_printf(self, "%d bytes context size, %d-bit DMA\n", 546 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); 547 548 xhci_get_xecp(sc); 549 550 /* enable 64Kbyte control endpoint quirk */ 551 sc->sc_bus.control_ep_quirk = (xhcictlquirk ? 1 : 0); 552 553 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 554 555 /* get number of device slots */ 556 sc->sc_noport = XHCI_HCS1_N_PORTS(temp); 557 558 if (sc->sc_noport == 0) { 559 device_printf(sc->sc_bus.parent, "Invalid number " 560 "of ports: %u\n", sc->sc_noport); 561 return (ENXIO); 562 } 563 564 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 565 566 DPRINTF("Max slots: %u\n", sc->sc_noslot); 567 568 if (sc->sc_noslot > XHCI_MAX_DEVICES) 569 sc->sc_noslot = XHCI_MAX_DEVICES; 570 571 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 572 573 DPRINTF("HCS2=0x%08x\n", temp); 574 575 /* get isochronous scheduling threshold */ 576 sc->sc_ist = XHCI_HCS2_IST(temp); 577 578 /* get number of scratchpads */ 579 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 580 581 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 582 device_printf(sc->sc_bus.parent, "XHCI request " 583 "too many scratchpads\n"); 584 return (ENOMEM); 585 } 586 587 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 588 589 /* get event table size */ 590 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp); 591 if (sc->sc_erst_max > XHCI_MAX_RSEG) 592 sc->sc_erst_max = XHCI_MAX_RSEG; 593 594 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 595 596 /* get maximum exit latency */ 597 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 598 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 599 600 /* Check if we should use the default IMOD value. */ 601 if (sc->sc_imod_default == 0) 602 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 603 604 /* get all DMA memory */ 605 if (usb_bus_mem_alloc_all(&sc->sc_bus, 606 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 607 return (ENOMEM); 608 } 609 610 /* set up command queue mutex and condition varible */ 611 cv_init(&sc->sc_cmd_cv, "CMDQ"); 612 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 613 614 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 615 sc->sc_config_msg[0].bus = &sc->sc_bus; 616 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 617 sc->sc_config_msg[1].bus = &sc->sc_bus; 618 619 return (0); 620 } 621 622 void 623 xhci_uninit(struct xhci_softc *sc) 624 { 625 /* 626 * NOTE: At this point the control transfer process is gone 627 * and "xhci_configure_msg" is no longer called. Consequently 628 * waiting for the configuration messages to complete is not 629 * needed. 630 */ 631 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 632 633 cv_destroy(&sc->sc_cmd_cv); 634 sx_destroy(&sc->sc_cmd_sx); 635 } 636 637 static void 638 xhci_get_xecp(struct xhci_softc *sc) 639 { 640 641 uint32_t hccp1; 642 uint32_t eec; 643 uint32_t eecp; 644 bool first = true; 645 646 hccp1 = XREAD4(sc, capa, XHCI_HCCPARAMS1); 647 648 if (XHCI_HCS0_XECP(hccp1) == 0) { 649 device_printf(sc->sc_bus.parent, 650 "xECP: no capabilities found\n"); 651 return; 652 } 653 654 /* 655 * Parse the xECP Capabilities table and print known caps. 656 * Implemented, vendor and reserved xECP Capabilities values are 657 * documented in Table 7.2 of eXtensible Host Controller Interface for 658 * Universal Serial Bus (xHCI) Rev 1.2b 2023. 659 */ 660 device_printf(sc->sc_bus.parent, "xECP capabilities <"); 661 662 eec = -1; 663 for (eecp = XHCI_HCS0_XECP(hccp1) << 2; 664 eecp != 0 && XHCI_XECP_NEXT(eec) != 0; 665 eecp += XHCI_XECP_NEXT(eec) << 2) { 666 eec = XREAD4(sc, capa, eecp); 667 668 uint8_t xecpid = XHCI_XECP_ID(eec); 669 670 if ((xecpid >= 11 && xecpid <= 16) || 671 (xecpid >= 19 && xecpid <= 191)) { 672 if (!first) 673 printf(","); 674 printf("RES(%x)", xecpid); 675 } else if (xecpid > 191) { 676 if (!first) 677 printf(","); 678 printf("VEND(%x)", xecpid); 679 } else { 680 if (!first) 681 printf(","); 682 switch (xecpid) 683 { 684 case XHCI_ID_USB_LEGACY: 685 printf("LEGACY"); 686 break; 687 case XHCI_ID_PROTOCOLS: 688 printf("PROTO"); 689 break; 690 case XHCI_ID_POWER_MGMT: 691 printf("POWER"); 692 break; 693 case XHCI_ID_VIRTUALIZATION: 694 printf("VIRT"); 695 break; 696 case XHCI_ID_MSG_IRQ: 697 printf("MSG IRQ"); 698 break; 699 case XHCI_ID_USB_LOCAL_MEM: 700 printf("LOCAL MEM"); 701 break; 702 case XHCI_ID_USB_DEBUG: 703 printf("DEBUG"); 704 break; 705 case XHCI_ID_EXT_MSI: 706 printf("EXT MSI"); 707 break; 708 case XHCI_ID_USB3_TUN: 709 printf("TUN"); 710 break; 711 712 } 713 } 714 first = false; 715 } 716 printf(">\n"); 717 } 718 719 static void 720 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 721 { 722 struct xhci_softc *sc = XHCI_BUS2SC(bus); 723 724 switch (state) { 725 case USB_HW_POWER_SUSPEND: 726 DPRINTF("Stopping the XHCI\n"); 727 xhci_halt_controller(sc); 728 xhci_reset_controller(sc); 729 break; 730 case USB_HW_POWER_SHUTDOWN: 731 DPRINTF("Stopping the XHCI\n"); 732 xhci_halt_controller(sc); 733 xhci_reset_controller(sc); 734 break; 735 case USB_HW_POWER_RESUME: 736 DPRINTF("Starting the XHCI\n"); 737 xhci_start_controller(sc); 738 break; 739 default: 740 break; 741 } 742 } 743 744 static usb_error_t 745 xhci_generic_done_sub(struct usb_xfer *xfer) 746 { 747 struct xhci_td *td; 748 struct xhci_td *td_alt_next; 749 uint32_t len; 750 uint8_t status; 751 752 td = xfer->td_transfer_cache; 753 td_alt_next = td->alt_next; 754 755 if (xfer->aframes != xfer->nframes) 756 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 757 758 while (1) { 759 usb_pc_cpu_invalidate(td->page_cache); 760 761 status = td->status; 762 len = td->remainder; 763 764 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 765 xfer, (unsigned)xfer->aframes, 766 (unsigned)xfer->nframes, 767 (unsigned)len, (unsigned)td->len, 768 (unsigned)status); 769 770 /* 771 * Verify the status length and 772 * add the length to "frlengths[]": 773 */ 774 if (len > td->len) { 775 /* should not happen */ 776 DPRINTF("Invalid status length, " 777 "0x%04x/0x%04x bytes\n", len, td->len); 778 status = XHCI_TRB_ERROR_LENGTH; 779 } else if (xfer->aframes != xfer->nframes) { 780 xfer->frlengths[xfer->aframes] += td->len - len; 781 } 782 /* Check for last transfer */ 783 if (((void *)td) == xfer->td_transfer_last) { 784 td = NULL; 785 break; 786 } 787 /* Check for transfer error */ 788 if (status != XHCI_TRB_ERROR_SHORT_PKT && 789 status != XHCI_TRB_ERROR_SUCCESS) { 790 /* the transfer is finished */ 791 td = NULL; 792 break; 793 } 794 /* Check for short transfer */ 795 if (len > 0) { 796 if (xfer->flags_int.short_frames_ok || 797 xfer->flags_int.isochronous_xfr || 798 xfer->flags_int.control_xfr) { 799 /* follow alt next */ 800 td = td->alt_next; 801 } else { 802 /* the transfer is finished */ 803 td = NULL; 804 } 805 break; 806 } 807 td = td->obj_next; 808 809 if (td->alt_next != td_alt_next) { 810 /* this USB frame is complete */ 811 break; 812 } 813 } 814 815 /* update transfer cache */ 816 817 xfer->td_transfer_cache = td; 818 819 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 820 (status != XHCI_TRB_ERROR_SHORT_PKT && 821 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 822 USB_ERR_NORMAL_COMPLETION); 823 } 824 825 static void 826 xhci_generic_done(struct usb_xfer *xfer) 827 { 828 usb_error_t err = 0; 829 830 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 831 xfer, xfer->endpoint); 832 833 /* reset scanner */ 834 835 xfer->td_transfer_cache = xfer->td_transfer_first; 836 837 if (xfer->flags_int.control_xfr) { 838 if (xfer->flags_int.control_hdr) 839 err = xhci_generic_done_sub(xfer); 840 841 xfer->aframes = 1; 842 843 if (xfer->td_transfer_cache == NULL) 844 goto done; 845 } 846 847 while (xfer->aframes != xfer->nframes) { 848 err = xhci_generic_done_sub(xfer); 849 xfer->aframes++; 850 851 if (xfer->td_transfer_cache == NULL) 852 goto done; 853 } 854 855 if (xfer->flags_int.control_xfr && 856 !xfer->flags_int.control_act) 857 err = xhci_generic_done_sub(xfer); 858 done: 859 /* transfer is complete */ 860 xhci_device_done(xfer, err); 861 } 862 863 static void 864 xhci_activate_transfer(struct usb_xfer *xfer) 865 { 866 struct xhci_td *td; 867 868 td = xfer->td_transfer_cache; 869 870 usb_pc_cpu_invalidate(td->page_cache); 871 872 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 873 /* activate the transfer */ 874 875 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 876 usb_pc_cpu_flush(td->page_cache); 877 878 xhci_endpoint_doorbell(xfer); 879 } 880 } 881 882 static void 883 xhci_skip_transfer(struct usb_xfer *xfer) 884 { 885 struct xhci_td *td; 886 struct xhci_td *td_last; 887 888 td = xfer->td_transfer_cache; 889 td_last = xfer->td_transfer_last; 890 891 td = td->alt_next; 892 893 usb_pc_cpu_invalidate(td->page_cache); 894 895 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 896 usb_pc_cpu_invalidate(td_last->page_cache); 897 898 /* copy LINK TRB to current waiting location */ 899 900 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 901 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 902 usb_pc_cpu_flush(td->page_cache); 903 904 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 905 usb_pc_cpu_flush(td->page_cache); 906 907 xhci_endpoint_doorbell(xfer); 908 } 909 } 910 911 /*------------------------------------------------------------------------* 912 * xhci_check_transfer 913 *------------------------------------------------------------------------*/ 914 static void 915 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 916 { 917 struct xhci_endpoint_ext *pepext; 918 int64_t offset; 919 uint64_t td_event; 920 uint32_t temp; 921 uint32_t remainder; 922 uint16_t stream_id = 0; 923 uint16_t i; 924 uint8_t status; 925 uint8_t halted; 926 uint8_t epno; 927 uint8_t index; 928 929 /* decode TRB */ 930 td_event = le64toh(trb->qwTrb0); 931 temp = le32toh(trb->dwTrb2); 932 933 remainder = XHCI_TRB_2_REM_GET(temp); 934 status = XHCI_TRB_2_ERROR_GET(temp); 935 936 temp = le32toh(trb->dwTrb3); 937 epno = XHCI_TRB_3_EP_GET(temp); 938 index = XHCI_TRB_3_SLOT_GET(temp); 939 940 /* check if error means halted */ 941 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 942 status != XHCI_TRB_ERROR_SUCCESS); 943 944 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 945 index, epno, remainder, status); 946 947 if (index > sc->sc_noslot) { 948 DPRINTF("Invalid slot.\n"); 949 return; 950 } 951 952 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 953 DPRINTF("Invalid endpoint.\n"); 954 return; 955 } 956 957 pepext = &sc->sc_hw.devs[index].endp[epno]; 958 959 /* try to find the USB transfer that generated the event */ 960 for (i = 0;; i++) { 961 struct usb_xfer *xfer; 962 struct xhci_td *td; 963 964 if (i == (XHCI_MAX_TRANSFERS - 1)) { 965 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS || 966 stream_id == (XHCI_MAX_STREAMS - 1)) 967 break; 968 stream_id++; 969 i = 0; 970 DPRINTFN(5, "stream_id=%u\n", stream_id); 971 } 972 973 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 974 if (xfer == NULL) 975 continue; 976 977 td = xfer->td_transfer_cache; 978 if (td == NULL) 979 continue; 980 981 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 982 (long long)td_event, 983 (long long)td->td_self, 984 (long long)td->td_self + sizeof(td->td_trb)); 985 986 /* 987 * NOTE: Some XHCI implementations might not trigger 988 * an event on the last LINK TRB so we need to 989 * consider both the last and second last event 990 * address as conditions for a successful transfer. 991 * 992 * NOTE: We assume that the XHCI will only trigger one 993 * event per chain of TRBs. 994 */ 995 996 offset = td_event - td->td_self; 997 998 if (offset >= 0 && 999 offset < (int64_t)sizeof(td->td_trb)) { 1000 usb_pc_cpu_invalidate(td->page_cache); 1001 1002 /* compute rest of remainder, if any */ 1003 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 1004 temp = le32toh(td->td_trb[i].dwTrb2); 1005 remainder += XHCI_TRB_2_BYTES_GET(temp); 1006 } 1007 1008 DPRINTFN(5, "New remainder: %u\n", remainder); 1009 1010 /* clear isochronous transfer errors */ 1011 if (xfer->flags_int.isochronous_xfr) { 1012 if (halted) { 1013 halted = 0; 1014 status = XHCI_TRB_ERROR_SUCCESS; 1015 remainder = td->len; 1016 } 1017 } 1018 1019 /* "td->remainder" is verified later */ 1020 td->remainder = remainder; 1021 td->status = status; 1022 1023 usb_pc_cpu_flush(td->page_cache); 1024 1025 /* 1026 * 1) Last transfer descriptor makes the 1027 * transfer done 1028 */ 1029 if (((void *)td) == xfer->td_transfer_last) { 1030 DPRINTF("TD is last\n"); 1031 xhci_generic_done(xfer); 1032 break; 1033 } 1034 1035 /* 1036 * 2) Any kind of error makes the transfer 1037 * done 1038 */ 1039 if (halted) { 1040 DPRINTF("TD has I/O error\n"); 1041 xhci_generic_done(xfer); 1042 break; 1043 } 1044 1045 /* 1046 * 3) If there is no alternate next transfer, 1047 * a short packet also makes the transfer done 1048 */ 1049 if (td->remainder > 0) { 1050 if (td->alt_next == NULL) { 1051 DPRINTF( 1052 "short TD has no alternate next\n"); 1053 xhci_generic_done(xfer); 1054 break; 1055 } 1056 DPRINTF("TD has short pkt\n"); 1057 if (xfer->flags_int.short_frames_ok || 1058 xfer->flags_int.isochronous_xfr || 1059 xfer->flags_int.control_xfr) { 1060 /* follow the alt next */ 1061 xfer->td_transfer_cache = td->alt_next; 1062 xhci_activate_transfer(xfer); 1063 break; 1064 } 1065 xhci_skip_transfer(xfer); 1066 xhci_generic_done(xfer); 1067 break; 1068 } 1069 1070 /* 1071 * 4) Transfer complete - go to next TD 1072 */ 1073 DPRINTF("Following next TD\n"); 1074 xfer->td_transfer_cache = td->obj_next; 1075 xhci_activate_transfer(xfer); 1076 break; /* there should only be one match */ 1077 } 1078 } 1079 } 1080 1081 static int 1082 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1083 { 1084 if (sc->sc_cmd_addr == trb->qwTrb0) { 1085 DPRINTF("Received command event\n"); 1086 sc->sc_cmd_result[0] = trb->dwTrb2; 1087 sc->sc_cmd_result[1] = trb->dwTrb3; 1088 cv_signal(&sc->sc_cmd_cv); 1089 return (1); /* command match */ 1090 } 1091 return (0); 1092 } 1093 1094 static int 1095 xhci_interrupt_poll(struct xhci_softc *sc) 1096 { 1097 struct usb_page_search buf_res; 1098 struct xhci_hw_root *phwr; 1099 uint64_t addr; 1100 uint32_t temp; 1101 int retval = 0; 1102 uint16_t i; 1103 uint8_t event; 1104 uint8_t j; 1105 uint8_t k; 1106 uint8_t t; 1107 1108 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1109 1110 phwr = buf_res.buffer; 1111 1112 /* Receive any events */ 1113 1114 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1115 1116 i = sc->sc_event_idx; 1117 j = sc->sc_event_ccs; 1118 t = 2; 1119 1120 while (1) { 1121 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1122 1123 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1124 1125 if (j != k) 1126 break; 1127 1128 event = XHCI_TRB_3_TYPE_GET(temp); 1129 1130 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1131 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1132 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1133 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1134 1135 switch (event) { 1136 case XHCI_TRB_EVENT_TRANSFER: 1137 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1138 break; 1139 case XHCI_TRB_EVENT_CMD_COMPLETE: 1140 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1141 break; 1142 default: 1143 DPRINTF("Unhandled event = %u\n", event); 1144 break; 1145 } 1146 1147 i++; 1148 1149 if (i == XHCI_MAX_EVENTS) { 1150 i = 0; 1151 j ^= 1; 1152 1153 /* check for timeout */ 1154 if (!--t) 1155 break; 1156 } 1157 } 1158 1159 sc->sc_event_idx = i; 1160 sc->sc_event_ccs = j; 1161 1162 /* 1163 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1164 * latched. That means to activate the register we need to 1165 * write both the low and high double word of the 64-bit 1166 * register. 1167 */ 1168 1169 addr = buf_res.physaddr; 1170 addr += __offsetof(struct xhci_hw_root, hwr_events[i]); 1171 1172 /* try to clear busy bit */ 1173 addr |= XHCI_ERDP_LO_BUSY; 1174 1175 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1176 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1177 1178 return (retval); 1179 } 1180 1181 static usb_error_t 1182 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1183 uint16_t timeout_ms) 1184 { 1185 struct usb_page_search buf_res; 1186 struct xhci_hw_root *phwr; 1187 uint64_t addr; 1188 uint32_t temp; 1189 uint8_t i; 1190 uint8_t j; 1191 uint8_t timeout = 0; 1192 int err; 1193 1194 XHCI_CMD_ASSERT_LOCKED(sc); 1195 1196 /* get hardware root structure */ 1197 1198 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1199 1200 phwr = buf_res.buffer; 1201 1202 /* Queue command */ 1203 1204 USB_BUS_LOCK(&sc->sc_bus); 1205 retry: 1206 i = sc->sc_command_idx; 1207 j = sc->sc_command_ccs; 1208 1209 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1210 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1211 (long long)le64toh(trb->qwTrb0), 1212 (long)le32toh(trb->dwTrb2), 1213 (long)le32toh(trb->dwTrb3)); 1214 1215 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1216 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1217 1218 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1219 1220 temp = trb->dwTrb3; 1221 1222 if (j) 1223 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1224 else 1225 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1226 1227 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1228 1229 phwr->hwr_commands[i].dwTrb3 = temp; 1230 1231 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1232 1233 addr = buf_res.physaddr; 1234 addr += __offsetof(struct xhci_hw_root, hwr_commands[i]); 1235 1236 sc->sc_cmd_addr = htole64(addr); 1237 1238 i++; 1239 1240 if (i == (XHCI_MAX_COMMANDS - 1)) { 1241 if (j) { 1242 temp = htole32(XHCI_TRB_3_TC_BIT | 1243 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1244 XHCI_TRB_3_CYCLE_BIT); 1245 } else { 1246 temp = htole32(XHCI_TRB_3_TC_BIT | 1247 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1248 } 1249 1250 phwr->hwr_commands[i].dwTrb3 = temp; 1251 1252 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1253 1254 i = 0; 1255 j ^= 1; 1256 } 1257 1258 sc->sc_command_idx = i; 1259 sc->sc_command_ccs = j; 1260 1261 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1262 1263 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1264 USB_MS_TO_TICKS(timeout_ms)); 1265 1266 /* 1267 * In some error cases event interrupts are not generated. 1268 * Poll one time to see if the command has completed. 1269 */ 1270 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1271 DPRINTF("Command was completed when polling\n"); 1272 err = 0; 1273 } 1274 if (err != 0) { 1275 DPRINTF("Command timeout!\n"); 1276 /* 1277 * After some weeks of continuous operation, it has 1278 * been observed that the ASMedia Technology, ASM1042 1279 * SuperSpeed USB Host Controller can suddenly stop 1280 * accepting commands via the command queue. Try to 1281 * first reset the command queue. If that fails do a 1282 * host controller reset. 1283 */ 1284 if (timeout == 0 && 1285 xhci_reset_command_queue_locked(sc) == 0) { 1286 temp = le32toh(trb->dwTrb3); 1287 1288 /* 1289 * Avoid infinite XHCI reset loops if the set 1290 * address command fails to respond due to a 1291 * non-enumerating device: 1292 */ 1293 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1294 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1295 DPRINTF("Set address timeout\n"); 1296 } else { 1297 timeout = 1; 1298 goto retry; 1299 } 1300 } else { 1301 DPRINTF("Controller reset!\n"); 1302 usb_bus_reset_async_locked(&sc->sc_bus); 1303 } 1304 err = USB_ERR_TIMEOUT; 1305 trb->dwTrb2 = 0; 1306 trb->dwTrb3 = 0; 1307 } else { 1308 temp = le32toh(sc->sc_cmd_result[0]); 1309 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1310 err = USB_ERR_IOERROR; 1311 1312 trb->dwTrb2 = sc->sc_cmd_result[0]; 1313 trb->dwTrb3 = sc->sc_cmd_result[1]; 1314 } 1315 1316 USB_BUS_UNLOCK(&sc->sc_bus); 1317 1318 return (err); 1319 } 1320 1321 #if 0 1322 static usb_error_t 1323 xhci_cmd_nop(struct xhci_softc *sc) 1324 { 1325 struct xhci_trb trb; 1326 uint32_t temp; 1327 1328 DPRINTF("\n"); 1329 1330 trb.qwTrb0 = 0; 1331 trb.dwTrb2 = 0; 1332 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1333 1334 trb.dwTrb3 = htole32(temp); 1335 1336 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1337 } 1338 #endif 1339 1340 static usb_error_t 1341 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1342 { 1343 struct xhci_trb trb; 1344 uint32_t temp; 1345 usb_error_t err; 1346 1347 DPRINTF("\n"); 1348 1349 trb.qwTrb0 = 0; 1350 trb.dwTrb2 = 0; 1351 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1352 1353 err = xhci_do_command(sc, &trb, 100 /* ms */); 1354 if (err) 1355 goto done; 1356 1357 temp = le32toh(trb.dwTrb3); 1358 1359 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1360 1361 done: 1362 return (err); 1363 } 1364 1365 static usb_error_t 1366 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1367 { 1368 struct xhci_trb trb; 1369 uint32_t temp; 1370 1371 DPRINTF("\n"); 1372 1373 trb.qwTrb0 = 0; 1374 trb.dwTrb2 = 0; 1375 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1376 XHCI_TRB_3_SLOT_SET(slot_id); 1377 1378 trb.dwTrb3 = htole32(temp); 1379 1380 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1381 } 1382 1383 static usb_error_t 1384 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1385 uint8_t bsr, uint8_t slot_id) 1386 { 1387 struct xhci_trb trb; 1388 uint32_t temp; 1389 1390 DPRINTF("\n"); 1391 1392 trb.qwTrb0 = htole64(input_ctx); 1393 trb.dwTrb2 = 0; 1394 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1395 XHCI_TRB_3_SLOT_SET(slot_id); 1396 1397 if (bsr) 1398 temp |= XHCI_TRB_3_BSR_BIT; 1399 1400 trb.dwTrb3 = htole32(temp); 1401 1402 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1403 } 1404 1405 static usb_error_t 1406 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1407 { 1408 struct usb_page_search buf_inp; 1409 struct usb_page_search buf_dev; 1410 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1411 struct xhci_hw_dev *hdev; 1412 struct xhci_slot_ctx *slot; 1413 struct xhci_endpoint_ext *pepext; 1414 uint32_t temp; 1415 uint16_t mps; 1416 usb_error_t err; 1417 uint8_t index; 1418 1419 /* the root HUB case is not handled here */ 1420 if (udev->parent_hub == NULL) 1421 return (USB_ERR_INVAL); 1422 1423 index = udev->controller_slot_id; 1424 1425 hdev = &sc->sc_hw.devs[index]; 1426 1427 if (mtx != NULL) 1428 mtx_unlock(mtx); 1429 1430 XHCI_CMD_LOCK(sc); 1431 1432 switch (hdev->state) { 1433 case XHCI_ST_DEFAULT: 1434 case XHCI_ST_ENABLED: 1435 1436 hdev->state = XHCI_ST_ENABLED; 1437 1438 /* set configure mask to slot and EP0 */ 1439 xhci_configure_mask(udev, 3, 0); 1440 1441 /* configure input slot context structure */ 1442 err = xhci_configure_device(udev); 1443 1444 if (err != 0) { 1445 DPRINTF("Could not configure device\n"); 1446 break; 1447 } 1448 1449 /* configure input endpoint context structure */ 1450 switch (udev->speed) { 1451 case USB_SPEED_LOW: 1452 case USB_SPEED_FULL: 1453 mps = 8; 1454 break; 1455 case USB_SPEED_HIGH: 1456 mps = 64; 1457 break; 1458 default: 1459 mps = 512; 1460 break; 1461 } 1462 1463 pepext = xhci_get_endpoint_ext(udev, 1464 &udev->ctrl_ep_desc); 1465 1466 /* ensure the control endpoint is setup again */ 1467 USB_BUS_LOCK(udev->bus); 1468 pepext->trb_halted = 1; 1469 pepext->trb_running = 0; 1470 USB_BUS_UNLOCK(udev->bus); 1471 1472 err = xhci_configure_endpoint(udev, 1473 &udev->ctrl_ep_desc, pepext, 1474 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1475 1476 if (err != 0) { 1477 DPRINTF("Could not configure default endpoint\n"); 1478 break; 1479 } 1480 1481 /* execute set address command */ 1482 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1483 1484 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1485 (address == 0), index); 1486 1487 if (err != 0) { 1488 temp = le32toh(sc->sc_cmd_result[0]); 1489 if (address == 0 && sc->sc_port_route != NULL && 1490 XHCI_TRB_2_ERROR_GET(temp) == 1491 XHCI_TRB_ERROR_PARAMETER) { 1492 /* LynxPoint XHCI - ports are not switchable */ 1493 /* Un-route all ports from the XHCI */ 1494 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1495 } 1496 DPRINTF("Could not set address " 1497 "for slot %u.\n", index); 1498 if (address != 0) 1499 break; 1500 } 1501 1502 /* update device address to new value */ 1503 1504 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1505 slot = XHCI_GET_CTX(sc, xhci_dev_ctx, ctx_slot, 1506 buf_dev.buffer); 1507 usb_pc_cpu_invalidate(&hdev->device_pc); 1508 1509 temp = le32toh(slot->dwSctx3); 1510 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1511 1512 /* update device state to new value */ 1513 1514 if (address != 0) 1515 hdev->state = XHCI_ST_ADDRESSED; 1516 else 1517 hdev->state = XHCI_ST_DEFAULT; 1518 break; 1519 1520 default: 1521 DPRINTF("Wrong state for set address.\n"); 1522 err = USB_ERR_IOERROR; 1523 break; 1524 } 1525 XHCI_CMD_UNLOCK(sc); 1526 1527 if (mtx != NULL) 1528 mtx_lock(mtx); 1529 1530 return (err); 1531 } 1532 1533 static usb_error_t 1534 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1535 uint8_t deconfigure, uint8_t slot_id) 1536 { 1537 struct xhci_trb trb; 1538 uint32_t temp; 1539 1540 DPRINTF("\n"); 1541 1542 trb.qwTrb0 = htole64(input_ctx); 1543 trb.dwTrb2 = 0; 1544 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1545 XHCI_TRB_3_SLOT_SET(slot_id); 1546 1547 if (deconfigure) { 1548 if (sc->sc_no_deconfigure != 0 || xhcidcepquirk != 0) 1549 return (0); /* Success */ 1550 temp |= XHCI_TRB_3_DCEP_BIT; 1551 } 1552 1553 trb.dwTrb3 = htole32(temp); 1554 1555 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1556 } 1557 1558 static usb_error_t 1559 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1560 uint8_t slot_id) 1561 { 1562 struct xhci_trb trb; 1563 uint32_t temp; 1564 1565 DPRINTF("\n"); 1566 1567 trb.qwTrb0 = htole64(input_ctx); 1568 trb.dwTrb2 = 0; 1569 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1570 XHCI_TRB_3_SLOT_SET(slot_id); 1571 trb.dwTrb3 = htole32(temp); 1572 1573 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1574 } 1575 1576 static usb_error_t 1577 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1578 uint8_t ep_id, uint8_t slot_id) 1579 { 1580 struct xhci_trb trb; 1581 uint32_t temp; 1582 1583 DPRINTF("\n"); 1584 1585 trb.qwTrb0 = 0; 1586 trb.dwTrb2 = 0; 1587 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1588 XHCI_TRB_3_SLOT_SET(slot_id) | 1589 XHCI_TRB_3_EP_SET(ep_id); 1590 1591 if (preserve) 1592 temp |= XHCI_TRB_3_PRSV_BIT; 1593 1594 trb.dwTrb3 = htole32(temp); 1595 1596 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1597 } 1598 1599 static usb_error_t 1600 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1601 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1602 { 1603 struct xhci_trb trb; 1604 uint32_t temp; 1605 1606 DPRINTF("\n"); 1607 1608 trb.qwTrb0 = htole64(dequeue_ptr); 1609 1610 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1611 trb.dwTrb2 = htole32(temp); 1612 1613 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1614 XHCI_TRB_3_SLOT_SET(slot_id) | 1615 XHCI_TRB_3_EP_SET(ep_id); 1616 trb.dwTrb3 = htole32(temp); 1617 1618 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1619 } 1620 1621 static usb_error_t 1622 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1623 uint8_t ep_id, uint8_t slot_id) 1624 { 1625 struct xhci_trb trb; 1626 uint32_t temp; 1627 1628 DPRINTF("\n"); 1629 1630 trb.qwTrb0 = 0; 1631 trb.dwTrb2 = 0; 1632 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1633 XHCI_TRB_3_SLOT_SET(slot_id) | 1634 XHCI_TRB_3_EP_SET(ep_id); 1635 1636 if (suspend) 1637 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1638 1639 trb.dwTrb3 = htole32(temp); 1640 1641 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1642 } 1643 1644 static usb_error_t 1645 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1646 { 1647 struct xhci_trb trb; 1648 uint32_t temp; 1649 1650 DPRINTF("\n"); 1651 1652 trb.qwTrb0 = 0; 1653 trb.dwTrb2 = 0; 1654 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1655 XHCI_TRB_3_SLOT_SET(slot_id); 1656 1657 trb.dwTrb3 = htole32(temp); 1658 1659 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1660 } 1661 1662 /*------------------------------------------------------------------------* 1663 * xhci_interrupt - XHCI interrupt handler 1664 *------------------------------------------------------------------------*/ 1665 void 1666 xhci_interrupt(struct xhci_softc *sc) 1667 { 1668 uint32_t status; 1669 uint32_t temp; 1670 1671 USB_BUS_LOCK(&sc->sc_bus); 1672 1673 status = XREAD4(sc, oper, XHCI_USBSTS); 1674 1675 /* acknowledge interrupts, if any */ 1676 if (status != 0) { 1677 XWRITE4(sc, oper, XHCI_USBSTS, status); 1678 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1679 } 1680 1681 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1682 1683 /* force clearing of pending interrupts */ 1684 if (temp & XHCI_IMAN_INTR_PEND) 1685 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1686 1687 /* check for event(s) */ 1688 xhci_interrupt_poll(sc); 1689 1690 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1691 XHCI_STS_HSE | XHCI_STS_HCE)) { 1692 if (status & XHCI_STS_PCD) { 1693 xhci_root_intr(sc); 1694 } 1695 1696 if (status & XHCI_STS_HCH) { 1697 printf("%s: host controller halted\n", 1698 __FUNCTION__); 1699 } 1700 1701 if (status & XHCI_STS_HSE) { 1702 printf("%s: host system error\n", 1703 __FUNCTION__); 1704 } 1705 1706 if (status & XHCI_STS_HCE) { 1707 printf("%s: host controller error\n", 1708 __FUNCTION__); 1709 } 1710 } 1711 USB_BUS_UNLOCK(&sc->sc_bus); 1712 } 1713 1714 /*------------------------------------------------------------------------* 1715 * xhci_timeout - XHCI timeout handler 1716 *------------------------------------------------------------------------*/ 1717 static void 1718 xhci_timeout(void *arg) 1719 { 1720 struct usb_xfer *xfer = arg; 1721 1722 DPRINTF("xfer=%p\n", xfer); 1723 1724 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1725 1726 /* transfer is transferred */ 1727 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1728 } 1729 1730 static void 1731 xhci_do_poll(struct usb_bus *bus) 1732 { 1733 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1734 1735 USB_BUS_LOCK(&sc->sc_bus); 1736 xhci_interrupt_poll(sc); 1737 USB_BUS_UNLOCK(&sc->sc_bus); 1738 } 1739 1740 /* 1741 * Fill the link TRB at td->td_trb[td->ntrb]. 1742 * 1743 * td_next: the TD to link to (qwTrb0 is set to its physical address), or 1744 * NULL when this is the end of the static chain (xhci_transfer_insert 1745 * will later overwrite qwTrb0 with the ring-return address). 1746 * chain: when true, CHAIN_BIT is set on this link TRB so the hardware 1747 * continues into td_next without a TD boundary; this is used when 1748 * one transfer frame spans multiple xhci_td objects. When false 1749 * the link TRB ends the hardware TD. 1750 * 1751 * NOTE: link TRBs between two frames must not use chain=true; in particular 1752 * isochronous frames must never be chained, see xhci_setup_isoc(). 1753 */ 1754 static void 1755 xhci_td_fill_link(struct xhci_td *td, struct xhci_td *td_next, bool chain) 1756 { 1757 struct xhci_trb *trb; 1758 uint32_t dword; 1759 1760 trb = &td->td_trb[td->ntrb]; 1761 trb->qwTrb0 = td_next != NULL ? htole64(td_next->td_self) : 0; 1762 trb->dwTrb2 = 0; 1763 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | XHCI_TRB_3_CYCLE_BIT | 1764 XHCI_TRB_3_IOC_BIT; 1765 if (chain) 1766 dword |= XHCI_TRB_3_CHAIN_BIT; 1767 trb->dwTrb3 = htole32(dword); 1768 } 1769 1770 /* 1771 * Build Normal TRBs for one transfer frame. 1772 * 1773 * A single xhci_td holds TRBs for at most XHCI_TD_PAYLOAD_MAX bytes. 1774 * Larger frames are split across consecutive TDs, pre-allocated by 1775 * xhci_xfer_setup(), whose link TRBs carry CHAIN_BIT so that the hardware 1776 * treats the whole frame as one TD. Returns the last TD used; the caller 1777 * must take its obj_next to reach the TD for the next frame. 1778 * 1779 * cache: DMA page cache containing the data. 1780 * offset: byte offset within cache (non-zero for isochronous frames that 1781 * share a single frbuffer[0]). 1782 * len: number of bytes in this frame (0 = zero-length packet). 1783 * mps: maximum packet size of the endpoint. 1784 * td: first transfer descriptor to fill. 1785 * is_in: true for an IN endpoint (ISP_BIT is set on data TRBs). 1786 * step_td: if true, leave CYCLE_BIT clear on the first TRB so that 1787 * xhci_activate_transfer() can start it later (bulk IN stepping). 1788 * last: true if this is the last frame of the transfer. 1789 */ 1790 static struct xhci_td * 1791 xhci_setup_normal_trbs(struct usb_page_cache *cache, uint32_t offset, 1792 uint32_t len, uint32_t mps, struct xhci_td *td, bool is_in, bool step_td, 1793 bool last) 1794 { 1795 struct xhci_trb *trb; 1796 struct usb_page_search search; 1797 struct xhci_td *td_first; 1798 struct xhci_td *td_alt_next; 1799 uint32_t cur_len, td_end, seg_len, npkt, dword; 1800 bool is_final; 1801 int i; 1802 1803 td_first = td; 1804 cur_len = 0; 1805 1806 for (;;) { 1807 /* Number of bytes described by the current TD */ 1808 td->len = len - cur_len; 1809 if (td->len > XHCI_TD_PAYLOAD_MAX) 1810 td->len = XHCI_TD_PAYLOAD_MAX; 1811 td_end = cur_len + td->len; 1812 1813 i = 0; 1814 do { 1815 trb = &td->td_trb[i]; 1816 if (len > 0) { 1817 usbd_get_page(cache, offset + cur_len, &search); 1818 seg_len = search.length; 1819 if (cur_len + seg_len > td_end) 1820 seg_len = td_end - cur_len; 1821 if (seg_len > XHCI_TD_PAGE_SIZE) 1822 seg_len = XHCI_TD_PAGE_SIZE; 1823 cur_len += seg_len; 1824 } else { 1825 /* Zero-length packet: no data buffer */ 1826 memset(&search, 0, sizeof(search)); 1827 seg_len = 0; 1828 } 1829 1830 /* TD size counts the packets left in the frame */ 1831 npkt = howmany(len - cur_len, mps); 1832 if (npkt > 31) 1833 npkt = 31; 1834 1835 trb->qwTrb0 = htole64(search.physaddr); 1836 trb->dwTrb2 = htole32(XHCI_TRB_2_BYTES_SET(seg_len) | 1837 XHCI_TRB_2_TDSZ_SET(npkt)); 1838 dword = XHCI_TRB_3_CHAIN_BIT | 1839 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1840 if (is_in) 1841 dword |= XHCI_TRB_3_ISP_BIT; 1842 /* First TRB of the frame: omit CYCLE if stepping */ 1843 if (td != td_first || i > 0 || !step_td) 1844 dword |= XHCI_TRB_3_CYCLE_BIT; 1845 trb->dwTrb3 = htole32(dword); 1846 i++; 1847 } while (cur_len < td_end); 1848 1849 is_final = (cur_len == len); 1850 1851 /* 1852 * Last data TRB of each TD: add IOC so that the interrupt 1853 * handler gets an event to advance td_transfer_cache. On 1854 * the frame's final data TRB additionally remove CHAIN and 1855 * clear the TD size. 1856 */ 1857 trb->dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1858 if (is_final) { 1859 trb->dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1860 trb->dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31)); 1861 } 1862 1863 td->ntrb = i; 1864 td->remainder = 0; 1865 td->status = 0; 1866 1867 /* 1868 * Intermediate link TRBs keep CHAIN_BIT set so that the 1869 * frame continues into the next TD without a TD boundary. 1870 */ 1871 xhci_td_fill_link(td, (is_final && last) ? NULL : td->obj_next, 1872 !is_final); 1873 1874 if (is_final) 1875 break; 1876 1877 if (td->obj_next == NULL) 1878 panic("%s: out of XHCI transfer descriptors!", 1879 __FUNCTION__); 1880 td = td->obj_next; 1881 } 1882 1883 /* 1884 * All TDs of one frame must share the same alt_next: 1885 * xhci_generic_done_sub() uses an alt_next change to detect the end 1886 * of a frame, and a short packet must skip ahead to the next frame, 1887 * not to the next TD of the same frame. 1888 */ 1889 td_alt_next = last ? NULL : td->obj_next; 1890 for (;;) { 1891 td_first->alt_next = td_alt_next; 1892 usb_pc_cpu_flush(td_first->page_cache); 1893 if (td_first == td) 1894 break; 1895 td_first = td_first->obj_next; 1896 } 1897 1898 return (td); 1899 } 1900 1901 /* 1902 * Build TRBs for a control transfer. Each stage (Setup, Data, Status) 1903 * occupies its own xhci_td so that xhci_generic_done_sub() can account 1904 * for each frame independently. Returns the last TD used. 1905 */ 1906 static struct xhci_td * 1907 xhci_setup_ctrl(struct usb_xfer *xfer, struct xhci_td *td) 1908 { 1909 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 1910 struct xhci_trb *trb; 1911 struct usb_page_search search; 1912 uint32_t dword, len, cur_len, seg_len, npkt; 1913 int x, i; 1914 bool is_in, use_data_stage, step_td, is_last; 1915 1916 is_in = !!(xfer->endpointno & UE_DIR_IN); 1917 use_data_stage = !xfer->flags_int.control_did_data; 1918 1919 /* ---- Setup stage ---- */ 1920 if (xfer->flags_int.control_hdr) { 1921 /* setup_only: no data or status to follow */ 1922 bool setup_only = (xfer->nframes == 1) && 1923 xfer->flags_int.control_act; 1924 1925 trb = &td->td_trb[0]; 1926 usbd_copy_out(&xfer->frbuffers[0], 0, 1927 (uint8_t *)(uintptr_t)&trb->qwTrb0, 8); 1928 trb->dwTrb2 = htole32( 1929 XHCI_TRB_2_BYTES_SET(8) | XHCI_TRB_2_TDSZ_SET(0)); 1930 /* 1931 * IOC: the Setup stage is a complete one-TRB TD; without IOC 1932 * the controller generates no Transfer Event for it and 1933 * td_transfer_cache never advances past the Setup stage, so the 1934 * control transfer (and thus enumeration) hangs. 1935 */ 1936 dword = XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IDT_BIT | 1937 XHCI_TRB_3_IOC_BIT | 1938 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE); 1939 /* TRT field: set only when wLength != 0 (XHCI 1.2 §4.11.2.2) */ 1940 if (trb->qwTrb0 & htole64(XHCI_TRB_0_WLENGTH_MASK)) 1941 dword |= (trb->qwTrb0 & 1942 htole64(XHCI_TRB_0_DIR_IN_MASK)) ? 1943 XHCI_TRB_3_TRT_IN : 1944 XHCI_TRB_3_TRT_OUT; 1945 trb->dwTrb3 = htole32(dword); 1946 1947 td->ntrb = 1; 1948 td->len = 8; 1949 td->remainder = 0; 1950 td->status = 0; 1951 td->alt_next = setup_only ? NULL : td->obj_next; 1952 1953 xhci_td_fill_link(td, setup_only ? NULL : td->obj_next, false); 1954 usb_pc_cpu_flush(td->page_cache); 1955 1956 if (setup_only) 1957 return (td); 1958 td = td->obj_next; 1959 } 1960 1961 /* ---- Data stages (frame indices 1 .. nframes-1) ---- */ 1962 for (x = 1; x < xfer->nframes; x++) { 1963 len = xfer->frlengths[x]; 1964 is_last = (x == xfer->nframes - 1) && 1965 xfer->flags_int.control_act; 1966 1967 cur_len = 0; 1968 i = 0; 1969 1970 do { 1971 trb = &td->td_trb[i]; 1972 usbd_get_page(&xfer->frbuffers[x], cur_len, &search); 1973 seg_len = search.length; 1974 if (cur_len + seg_len > len) 1975 seg_len = len - cur_len; 1976 if (seg_len > XHCI_TD_PAGE_SIZE) 1977 seg_len = XHCI_TD_PAGE_SIZE; 1978 cur_len += seg_len; 1979 1980 npkt = howmany(len - cur_len, xfer->max_packet_size); 1981 if (npkt > 31) 1982 npkt = 31; 1983 1984 trb->qwTrb0 = htole64(search.physaddr); 1985 trb->dwTrb2 = htole32(XHCI_TRB_2_BYTES_SET(seg_len) | 1986 XHCI_TRB_2_TDSZ_SET(npkt)); 1987 1988 /* 1989 * XHCI 1.2 §4.11.2.2: first TRB of the data 1990 * phase must be Data Stage type; subsequent 1991 * TRBs (same or later data frame) use Normal. 1992 */ 1993 if (use_data_stage) { 1994 dword = XHCI_TRB_3_CYCLE_BIT | 1995 XHCI_TRB_3_CHAIN_BIT | 1996 XHCI_TRB_3_TYPE_SET( 1997 XHCI_TRB_TYPE_DATA_STAGE); 1998 if (is_in) 1999 dword |= XHCI_TRB_3_DIR_IN | 2000 XHCI_TRB_3_ISP_BIT; 2001 use_data_stage = false; 2002 } else { 2003 dword = XHCI_TRB_3_CYCLE_BIT | 2004 XHCI_TRB_3_CHAIN_BIT | 2005 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 2006 if (is_in) 2007 dword |= XHCI_TRB_3_ISP_BIT; 2008 } 2009 trb->dwTrb3 = htole32(dword); 2010 i++; 2011 } while (cur_len < len); 2012 /* Fix last data TRB */ 2013 trb->dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 2014 trb->dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 2015 trb->dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31)); 2016 2017 td->ntrb = i; 2018 td->len = len; 2019 td->remainder = 0; 2020 td->status = 0; 2021 td->alt_next = is_last ? NULL : td->obj_next; 2022 2023 xhci_td_fill_link(td, is_last ? NULL : td->obj_next, false); 2024 usb_pc_cpu_flush(td->page_cache); 2025 2026 if (is_last) 2027 return (td); 2028 td = td->obj_next; 2029 } 2030 2031 /* ---- Status stage ---- */ 2032 2033 /* 2034 * Some XHCI controllers will not delay the status stage until the 2035 * next SOF, causing control transfer failures. When ctlstep is 2036 * set we leave CYCLE_BIT clear; xhci_activate_transfer() enables it 2037 * after the data stage has completed. 2038 */ 2039 step_td = (xhcictlstep || sc->sc_ctlstep) && (xfer->nframes != 0); 2040 2041 trb = &td->td_trb[0]; 2042 trb->qwTrb0 = 0; 2043 trb->dwTrb2 = htole32(XHCI_TRB_2_BYTES_SET(0) | XHCI_TRB_2_TDSZ_SET(0)); 2044 dword = XHCI_TRB_3_IOC_BIT | 2045 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 2046 /* Status direction is opposite to the data direction */ 2047 if (!is_in) 2048 dword |= XHCI_TRB_3_DIR_IN; 2049 if (!step_td) 2050 dword |= XHCI_TRB_3_CYCLE_BIT; 2051 trb->dwTrb3 = htole32(dword); 2052 2053 td->ntrb = 1; 2054 td->len = 0; 2055 td->remainder = 0; 2056 td->status = 0; 2057 td->alt_next = NULL; 2058 2059 xhci_td_fill_link(td, NULL, false); 2060 usb_pc_cpu_flush(td->page_cache); 2061 2062 return (td); 2063 } 2064 2065 /* 2066 * Build TRBs for a bulk (or interrupt) transfer. 2067 * Each frame gets its own xhci_td. Returns the last TD used. 2068 */ 2069 static struct xhci_td * 2070 xhci_setup_bulk(struct usb_xfer *xfer, struct xhci_td *td) 2071 { 2072 bool is_in = !!(xfer->endpointno & UE_DIR_IN); 2073 bool multishort = xfer->flags_int.short_frames_ok; 2074 struct xhci_td *td_last; 2075 int i; 2076 2077 td_last = td; 2078 for (i = 0; i < xfer->nframes; i++) { 2079 bool is_last = (i == xfer->nframes - 1); 2080 /* 2081 * Bulk IN: skip CYCLE on the first TRB of non-first frames 2082 * (unless short frames are allowed) so that the host 2083 * controller does not start the next frame before software 2084 * calls xhci_activate_transfer(). 2085 */ 2086 bool step_td = is_in && (i != 0) && !multishort; 2087 2088 td = xhci_setup_normal_trbs(&xfer->frbuffers[i], 0, 2089 xfer->frlengths[i], xfer->max_packet_size, td, is_in, 2090 step_td, is_last); 2091 td_last = td; 2092 td = td->obj_next; 2093 } 2094 2095 /* 2096 * If force_short_xfer is set and the last frame length is a non-zero 2097 * multiple of the max packet size, the hardware will not generate a 2098 * short packet naturally, so we must append a zero-length TD. 2099 * 2100 * The last regular-frame TD was set up with qwTrb0=0 in its link TRB 2101 * (the placeholder that xhci_transfer_insert would normally overwrite 2102 * for the final TD). Since the ZLP TD is now the true final TD, that 2103 * link TRB must be patched: qwTrb0 must point to the ZLP TD, and 2104 * CHAIN_BIT must be set. Some xHCI controllers refuse to send a ZLP 2105 * if the preceding link TRB does not have CHAIN_BIT set. 2106 */ 2107 if (xfer->flags.force_short_xfer && xfer->nframes > 0) { 2108 uint32_t last_len = xfer->frlengths[xfer->nframes - 1]; 2109 2110 if (last_len > 0 && (last_len % xfer->max_packet_size) == 0) { 2111 xhci_setup_normal_trbs(NULL, 0, 0, 2112 xfer->max_packet_size, td, is_in, false, true); 2113 /* 2114 * Fix the previous TD's link TRB: point to the ZLP TD 2115 * and set CHAIN_BIT. The address fix is necessary 2116 * because xhci_transfer_insert only patches td_last's 2117 * link TRB. The CHAIN_BIT is required because some 2118 * xHCI controllers will not emit a ZLP unless the 2119 * preceding link TRB has CHAIN_BIT set. 2120 */ 2121 td_last->td_trb[td_last->ntrb].qwTrb0 = 2122 htole64(td->td_self); 2123 td_last->td_trb[td_last->ntrb].dwTrb3 |= htole32( 2124 XHCI_TRB_3_CHAIN_BIT); 2125 usb_pc_cpu_flush(td_last->page_cache); 2126 td_last = td; 2127 } 2128 } 2129 return (td_last); 2130 } 2131 2132 /* 2133 * Build TRBs for an isochronous transfer. 2134 * 2135 * All isochronous frame data lives in a single contiguous DMA buffer 2136 * (frbuffers[0]); frlengths[x] gives the size of each frame. Each frame 2137 * maps to one xhci_td whose first TRB is of type ISOCH and whose remaining 2138 * TRBs (if data spans multiple pages) are of type NORMAL. 2139 * 2140 * Returns the last TD used. 2141 */ 2142 static struct xhci_td * 2143 xhci_setup_isoc(struct usb_xfer *xfer, struct xhci_td *td) 2144 { 2145 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2146 struct xhci_trb *trb; 2147 struct usb_page_search search; 2148 uint32_t dword, len, cur_len, buf_offset, seg_len, npkt; 2149 uint32_t mfindex, isoc_frame, isoc_delta; 2150 uint8_t mult, tdpc, tbc, tlbpc, shift, ist, y; 2151 int x, i; 2152 bool is_in = !!(xfer->endpointno & UE_DIR_IN); 2153 bool do_isoc_sync = false; 2154 struct xhci_td *td_last; 2155 2156 /* Compute burst multiplier (SuperSpeed or USB 2.0 high-bandwidth) */ 2157 mult = xfer->endpoint->ecomp ? 2158 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) : 2159 0; 2160 if (mult == 0) 2161 mult = (xfer->endpoint->edesc->wMaxPacketSize[1] >> 3) & 3; 2162 if (mult > 2) 2163 mult = 3; 2164 else 2165 mult++; 2166 2167 mfindex = XREAD4(sc, runt, XHCI_MFINDEX); 2168 DPRINTF("MFINDEX=0x%08x IST=0x%x\n", mfindex, sc->sc_ist); 2169 2170 switch (usbd_get_speed(xfer->xroot->udev)) { 2171 case USB_SPEED_FULL: 2172 shift = 3; 2173 isoc_delta = 8; /* 1 ms = 8 microframes */ 2174 break; 2175 default: 2176 shift = usbd_xfer_get_fps_shift(xfer); 2177 isoc_delta = 1U << shift; 2178 break; 2179 } 2180 2181 /* Compute isochronous scheduling threshold (XHCI 1.2 §4.14.2) */ 2182 ist = sc->sc_ist; 2183 if (ist & 8) 2184 y = (ist & 7) << 3; 2185 else 2186 y = (ist & 7); 2187 if (y < 8) { 2188 y = 0; 2189 } else if (y > 15) { 2190 DPRINTFN(3, "IST(%d) is too big!\n", ist); 2191 /* 2192 * The USB stack minimum isochronous transfer size is typically 2193 * 2x2 ms of payload. An IST above 15 microframes gives a 2194 * scheduling delay >= 2 ms, which is too much. 2195 */ 2196 y = 7; 2197 } else { 2198 /* Subtract one millisecond added by the generic layer */ 2199 y -= 8; 2200 } 2201 2202 if (usbd_xfer_get_isochronous_start_frame(xfer, mfindex, y, 8, 2203 XHCI_MFINDEX_GET(-1), &isoc_frame)) { 2204 /* Synchronise to a specific frame number */ 2205 do_isoc_sync = true; 2206 DPRINTFN(3, "start next=%d\n", isoc_frame); 2207 } 2208 2209 buf_offset = 0; 2210 td_last = td; 2211 2212 for (x = 0; x < xfer->nframes; x++) { 2213 bool is_last = (x == xfer->nframes - 1); 2214 struct xhci_td *td_next = is_last ? NULL : td->obj_next; 2215 2216 len = xfer->frlengths[x]; 2217 if (len > xfer->max_frame_size) 2218 len = xfer->max_frame_size; 2219 2220 /* Compute TBC and TLBPC (XHCI 1.2 §4.11.2.3) */ 2221 if (len == 0) { 2222 tbc = 0; 2223 tlbpc = mult - 1; 2224 } else { 2225 tdpc = howmany(len, xfer->max_packet_size); 2226 tbc = howmany(tdpc, mult) - 1; 2227 tlbpc = tdpc % mult; 2228 if (tlbpc == 0) 2229 tlbpc = mult - 1; 2230 else 2231 tlbpc--; 2232 } 2233 2234 cur_len = 0; 2235 i = 0; 2236 2237 if (len == 0) { 2238 /* Zero-length isochronous frame */ 2239 trb = &td->td_trb[0]; 2240 trb->qwTrb0 = 0; 2241 trb->dwTrb2 = htole32( 2242 XHCI_TRB_2_BYTES_SET(0) | XHCI_TRB_2_TDSZ_SET(0)); 2243 dword = XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 2244 XHCI_TRB_3_TBC_SET(tbc) | 2245 XHCI_TRB_3_TLBPC_SET(tlbpc) | 2246 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH); 2247 if (do_isoc_sync) { 2248 do_isoc_sync = false; 2249 dword |= XHCI_TRB_3_FRID_SET(isoc_frame / 8); 2250 } else { 2251 dword |= XHCI_TRB_3_ISO_SIA_BIT; 2252 } 2253 if (is_in) 2254 dword |= XHCI_TRB_3_ISP_BIT; 2255 trb->dwTrb3 = htole32(dword); 2256 i = 1; 2257 } else { 2258 while (cur_len < len) { 2259 trb = &td->td_trb[i]; 2260 usbd_get_page(&xfer->frbuffers[0], 2261 buf_offset + cur_len, &search); 2262 seg_len = search.length; 2263 if (cur_len + seg_len > len) 2264 seg_len = len - cur_len; 2265 if (seg_len > XHCI_TD_PAGE_SIZE) 2266 seg_len = XHCI_TD_PAGE_SIZE; 2267 cur_len += seg_len; 2268 2269 npkt = howmany(len - cur_len, 2270 xfer->max_packet_size); 2271 if (npkt > 31) 2272 npkt = 31; 2273 2274 trb->qwTrb0 = htole64(search.physaddr); 2275 trb->dwTrb2 = htole32( 2276 XHCI_TRB_2_BYTES_SET(seg_len) | 2277 XHCI_TRB_2_TDSZ_SET(npkt)); 2278 2279 /* 2280 * TBC and TLBPC are placed in the same bit 2281 * positions for both ISOCH and NORMAL TRBs 2282 * within an isochronous frame. 2283 */ 2284 dword = XHCI_TRB_3_CYCLE_BIT | 2285 XHCI_TRB_3_CHAIN_BIT | 2286 XHCI_TRB_3_TBC_SET(tbc) | 2287 XHCI_TRB_3_TLBPC_SET(tlbpc); 2288 if (i == 0) { 2289 /* First TRB: ISOCH type */ 2290 if (do_isoc_sync) { 2291 do_isoc_sync = false; 2292 dword |= 2293 XHCI_TRB_3_TYPE_SET( 2294 XHCI_TRB_TYPE_ISOCH) | 2295 XHCI_TRB_3_FRID_SET( 2296 isoc_frame / 8); 2297 } else { 2298 dword |= 2299 XHCI_TRB_3_TYPE_SET( 2300 XHCI_TRB_TYPE_ISOCH) | 2301 XHCI_TRB_3_ISO_SIA_BIT; 2302 } 2303 } else { 2304 /* Subsequent TRBs: NORMAL type */ 2305 dword |= XHCI_TRB_3_TYPE_SET( 2306 XHCI_TRB_TYPE_NORMAL); 2307 } 2308 if (is_in) 2309 dword |= XHCI_TRB_3_ISP_BIT; 2310 trb->dwTrb3 = htole32(dword); 2311 i++; 2312 } 2313 /* Fix last data TRB */ 2314 trb->dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 2315 trb->dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 2316 trb->dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31)); 2317 } 2318 2319 td->ntrb = i; 2320 td->len = len; 2321 td->remainder = 0; 2322 td->status = 0; 2323 /* For isochronous, alt_next always follows to the next frame */ 2324 td->alt_next = is_last ? NULL : td->obj_next; 2325 2326 /* 2327 * Isochronous frames must NOT have CHAIN set on their link 2328 * TRBs. The old xhci_setup_generic_chain_sub always removed 2329 * CHAIN from the link TRB at the end of each per-frame call. 2330 * With CHAIN set, some controllers treat consecutive ISOCH TDs 2331 * as a single chained TD and generate only one Transfer Event 2332 * for the whole transfer instead of one per frame, which causes 2333 * td_transfer_cache to stall on the first frame and time out. 2334 * Pass chain=false unconditionally so qwTrb0 is still written 2335 * with td_next's address while CHAIN is suppressed. 2336 */ 2337 xhci_td_fill_link(td, td_next, false); 2338 usb_pc_cpu_flush(td->page_cache); 2339 2340 td_last = td; 2341 td = td->obj_next; 2342 buf_offset += xfer->frlengths[x]; 2343 isoc_frame += isoc_delta; 2344 } 2345 2346 return (td_last); 2347 } 2348 2349 static void 2350 xhci_setup_generic_chain(struct usb_xfer *xfer) 2351 { 2352 struct xhci_td *td; 2353 2354 /* Toggle the DMA set we are using */ 2355 xfer->flags_int.curr_dma_set ^= 1; 2356 2357 /* Get the first TD of this DMA set */ 2358 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2359 2360 xfer->td_transfer_first = td; 2361 xfer->td_transfer_cache = td; 2362 2363 if (xfer->flags_int.isochronous_xfr) 2364 td = xhci_setup_isoc(xfer, td); 2365 else if (xfer->flags_int.control_xfr) 2366 td = xhci_setup_ctrl(xfer, td); 2367 else 2368 td = xhci_setup_bulk(xfer, td); 2369 2370 xfer->td_transfer_last = td; 2371 2372 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2373 } 2374 2375 static void 2376 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2377 { 2378 struct usb_page_search buf_res; 2379 struct xhci_dev_ctx_addr *pdctxa; 2380 2381 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2382 2383 pdctxa = buf_res.buffer; 2384 2385 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2386 2387 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2388 2389 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2390 } 2391 2392 static usb_error_t 2393 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2394 { 2395 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2396 struct usb_page_search buf_inp; 2397 struct xhci_input_ctx *input; 2398 struct xhci_slot_ctx *slot; 2399 uint32_t temp; 2400 uint8_t index; 2401 uint8_t x; 2402 2403 index = udev->controller_slot_id; 2404 2405 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2406 2407 input = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_input, 2408 buf_inp.buffer); 2409 slot = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_slot, buf_inp.buffer); 2410 2411 if (drop) { 2412 mask &= XHCI_INCTX_NON_CTRL_MASK; 2413 input->dwInCtx0 = htole32(mask); 2414 input->dwInCtx1 = htole32(0); 2415 } else { 2416 /* 2417 * Some hardware requires that we drop the endpoint 2418 * context before adding it again: 2419 */ 2420 input->dwInCtx0 = htole32(mask & XHCI_INCTX_NON_CTRL_MASK); 2421 2422 /* Add new endpoint context */ 2423 input->dwInCtx1 = htole32(mask); 2424 2425 /* find most significant set bit */ 2426 for (x = 31; x != 1; x--) { 2427 if (mask & (1 << x)) 2428 break; 2429 } 2430 2431 /* adjust */ 2432 x--; 2433 2434 /* figure out the maximum number of contexts */ 2435 if (x > sc->sc_hw.devs[index].context_num) 2436 sc->sc_hw.devs[index].context_num = x; 2437 else 2438 x = sc->sc_hw.devs[index].context_num; 2439 2440 /* update number of contexts */ 2441 temp = le32toh(slot->dwSctx0); 2442 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2443 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2444 slot->dwSctx0 = htole32(temp); 2445 } 2446 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2447 return (0); 2448 } 2449 2450 static usb_error_t 2451 xhci_configure_endpoint(struct usb_device *udev, 2452 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2453 uint16_t interval, uint8_t max_packet_count, 2454 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2455 uint16_t max_frame_size, uint8_t ep_mode) 2456 { 2457 struct usb_page_search buf_inp; 2458 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2459 struct xhci_endp_ctx *endp; 2460 uint64_t ring_addr = pepext->physaddr; 2461 uint32_t temp; 2462 uint8_t index; 2463 uint8_t epno; 2464 uint8_t type; 2465 2466 index = udev->controller_slot_id; 2467 2468 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2469 2470 epno = edesc->bEndpointAddress; 2471 type = edesc->bmAttributes & UE_XFERTYPE; 2472 2473 if (type == UE_CONTROL) 2474 epno |= UE_DIR_IN; 2475 2476 epno = XHCI_EPNO2EPID(epno); 2477 2478 if (epno == 0) 2479 return (USB_ERR_NO_PIPE); /* invalid */ 2480 2481 if (max_packet_count == 0) 2482 return (USB_ERR_BAD_BUFSIZE); 2483 2484 max_packet_count--; 2485 2486 if (mult == 0) 2487 return (USB_ERR_BAD_BUFSIZE); 2488 2489 endp = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_ep[epno - 1], 2490 buf_inp.buffer); 2491 2492 /* store endpoint mode */ 2493 pepext->trb_ep_mode = ep_mode; 2494 /* store bMaxPacketSize for control endpoints */ 2495 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0]; 2496 usb_pc_cpu_flush(pepext->page_cache); 2497 2498 if (ep_mode == USB_EP_MODE_STREAMS) { 2499 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2500 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2501 XHCI_EPCTX_0_LSA_SET(1); 2502 2503 ring_addr += sizeof(struct xhci_trb) * 2504 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2505 } else { 2506 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2507 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2508 XHCI_EPCTX_0_LSA_SET(0); 2509 2510 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2511 } 2512 2513 switch (udev->speed) { 2514 case USB_SPEED_FULL: 2515 case USB_SPEED_LOW: 2516 /* 1ms -> 125us */ 2517 fps_shift += 3; 2518 break; 2519 default: 2520 break; 2521 } 2522 2523 switch (type) { 2524 case UE_INTERRUPT: 2525 if (fps_shift > 3) 2526 fps_shift--; 2527 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2528 break; 2529 case UE_ISOCHRONOUS: 2530 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2531 2532 switch (udev->speed) { 2533 case USB_SPEED_SUPER: 2534 if (mult > 3) 2535 mult = 3; 2536 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2537 max_packet_count /= mult; 2538 break; 2539 default: 2540 break; 2541 } 2542 break; 2543 default: 2544 break; 2545 } 2546 2547 endp->dwEpCtx0 = htole32(temp); 2548 2549 temp = 2550 XHCI_EPCTX_1_HID_SET(0) | 2551 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2552 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2553 2554 /* 2555 * Always enable the "three strikes and you are gone" feature 2556 * except for ISOCHRONOUS endpoints. This is suggested by 2557 * section 4.3.3 in the XHCI specification about device slot 2558 * initialisation. 2559 */ 2560 if (type != UE_ISOCHRONOUS) 2561 temp |= XHCI_EPCTX_1_CERR_SET(3); 2562 2563 switch (type) { 2564 case UE_CONTROL: 2565 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2566 break; 2567 case UE_ISOCHRONOUS: 2568 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2569 break; 2570 case UE_BULK: 2571 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2572 break; 2573 default: 2574 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2575 break; 2576 } 2577 2578 /* check for IN direction */ 2579 if (epno & 1) 2580 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2581 2582 endp->dwEpCtx1 = htole32(temp); 2583 endp->qwEpCtx2 = htole64(ring_addr); 2584 2585 switch (edesc->bmAttributes & UE_XFERTYPE) { 2586 case UE_INTERRUPT: 2587 case UE_ISOCHRONOUS: 2588 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2589 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2590 max_frame_size)); 2591 break; 2592 case UE_CONTROL: 2593 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2594 break; 2595 default: 2596 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2597 break; 2598 } 2599 2600 endp->dwEpCtx4 = htole32(temp); 2601 2602 #ifdef USB_DEBUG 2603 xhci_dump_endpoint(endp); 2604 #endif 2605 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2606 2607 return (0); /* success */ 2608 } 2609 2610 static usb_error_t 2611 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2612 { 2613 struct xhci_endpoint_ext *pepext; 2614 struct usb_endpoint_ss_comp_descriptor *ecomp; 2615 usb_stream_t x; 2616 2617 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2618 xfer->endpoint->edesc); 2619 2620 ecomp = xfer->endpoint->ecomp; 2621 2622 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2623 uint64_t temp; 2624 2625 /* halt any transfers */ 2626 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2627 2628 /* compute start of TRB ring for stream "x" */ 2629 temp = pepext->physaddr + 2630 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2631 XHCI_SCTX_0_SCT_SEC_TR_RING; 2632 2633 /* make tree structure */ 2634 pepext->trb[(XHCI_MAX_TRANSFERS * 2635 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2636 2637 /* reserved fields */ 2638 pepext->trb[(XHCI_MAX_TRANSFERS * 2639 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2640 pepext->trb[(XHCI_MAX_TRANSFERS * 2641 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2642 } 2643 usb_pc_cpu_flush(pepext->page_cache); 2644 2645 return (xhci_configure_endpoint(xfer->xroot->udev, 2646 xfer->endpoint->edesc, pepext, 2647 xfer->interval, xfer->max_packet_count, 2648 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2649 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2650 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2651 } 2652 2653 static usb_error_t 2654 xhci_configure_device(struct usb_device *udev) 2655 { 2656 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2657 struct usb_page_search buf_inp; 2658 struct usb_page_cache *pcinp; 2659 struct xhci_slot_ctx *slot; 2660 struct usb_device *hubdev; 2661 uint32_t temp; 2662 uint32_t route; 2663 uint32_t rh_port; 2664 uint8_t is_hub; 2665 uint8_t index; 2666 uint8_t depth; 2667 2668 index = udev->controller_slot_id; 2669 2670 DPRINTF("index=%u\n", index); 2671 2672 pcinp = &sc->sc_hw.devs[index].input_pc; 2673 2674 usbd_get_page(pcinp, 0, &buf_inp); 2675 2676 slot = XHCI_GET_CTX(sc, xhci_input_dev_ctx, ctx_slot, buf_inp.buffer); 2677 2678 rh_port = 0; 2679 route = 0; 2680 2681 /* figure out route string and root HUB port number */ 2682 2683 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2684 if (hubdev->parent_hub == NULL) 2685 break; 2686 2687 depth = hubdev->parent_hub->depth; 2688 2689 /* 2690 * NOTE: HS/FS/LS devices and the SS root HUB can have 2691 * more than 15 ports 2692 */ 2693 2694 rh_port = hubdev->port_no; 2695 2696 if (depth == 0) 2697 break; 2698 2699 if (rh_port > 15) 2700 rh_port = 15; 2701 2702 if (depth < 6) 2703 route |= rh_port << (4 * (depth - 1)); 2704 } 2705 2706 DPRINTF("Route=0x%08x\n", route); 2707 2708 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2709 XHCI_SCTX_0_CTX_NUM_SET( 2710 sc->sc_hw.devs[index].context_num + 1); 2711 2712 switch (udev->speed) { 2713 case USB_SPEED_LOW: 2714 temp |= XHCI_SCTX_0_SPEED_SET(2); 2715 if (udev->parent_hs_hub != NULL && 2716 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2717 UDPROTO_HSHUBMTT) { 2718 DPRINTF("Device inherits MTT\n"); 2719 temp |= XHCI_SCTX_0_MTT_SET(1); 2720 } 2721 break; 2722 case USB_SPEED_HIGH: 2723 temp |= XHCI_SCTX_0_SPEED_SET(3); 2724 if (sc->sc_hw.devs[index].nports != 0 && 2725 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2726 DPRINTF("HUB supports MTT\n"); 2727 temp |= XHCI_SCTX_0_MTT_SET(1); 2728 } 2729 break; 2730 case USB_SPEED_FULL: 2731 temp |= XHCI_SCTX_0_SPEED_SET(1); 2732 if (udev->parent_hs_hub != NULL && 2733 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2734 UDPROTO_HSHUBMTT) { 2735 DPRINTF("Device inherits MTT\n"); 2736 temp |= XHCI_SCTX_0_MTT_SET(1); 2737 } 2738 break; 2739 default: 2740 temp |= XHCI_SCTX_0_SPEED_SET(4); 2741 break; 2742 } 2743 2744 is_hub = sc->sc_hw.devs[index].nports != 0 && 2745 (udev->speed == USB_SPEED_SUPER || 2746 udev->speed == USB_SPEED_HIGH); 2747 2748 if (is_hub) 2749 temp |= XHCI_SCTX_0_HUB_SET(1); 2750 2751 slot->dwSctx0 = htole32(temp); 2752 2753 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2754 2755 if (is_hub) { 2756 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2757 sc->sc_hw.devs[index].nports); 2758 } 2759 2760 slot->dwSctx1 = htole32(temp); 2761 2762 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2763 2764 if (is_hub) { 2765 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2766 sc->sc_hw.devs[index].tt); 2767 } 2768 2769 hubdev = udev->parent_hs_hub; 2770 2771 /* check if we should activate the transaction translator */ 2772 switch (udev->speed) { 2773 case USB_SPEED_FULL: 2774 case USB_SPEED_LOW: 2775 if (hubdev != NULL) { 2776 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2777 hubdev->controller_slot_id); 2778 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2779 udev->hs_port_no); 2780 } 2781 break; 2782 default: 2783 break; 2784 } 2785 2786 slot->dwSctx2 = htole32(temp); 2787 2788 /* 2789 * These fields should be initialized to zero, according to 2790 * XHCI section 6.2.2 - slot context: 2791 */ 2792 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2793 XHCI_SCTX_3_SLOT_STATE_SET(0); 2794 2795 slot->dwSctx3 = htole32(temp); 2796 2797 #ifdef USB_DEBUG 2798 xhci_dump_device(slot); 2799 #endif 2800 usb_pc_cpu_flush(pcinp); 2801 2802 return (0); /* success */ 2803 } 2804 2805 static usb_error_t 2806 xhci_alloc_device_ext(struct usb_device *udev) 2807 { 2808 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2809 struct usb_page_search buf_dev; 2810 struct usb_page_search buf_ep; 2811 struct xhci_trb *trb; 2812 struct usb_page_cache *pc; 2813 struct usb_page *pg; 2814 uint64_t addr; 2815 uint8_t index; 2816 uint8_t i; 2817 2818 index = udev->controller_slot_id; 2819 2820 pc = &sc->sc_hw.devs[index].device_pc; 2821 pg = &sc->sc_hw.devs[index].device_pg; 2822 2823 /* need to initialize the page cache */ 2824 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2825 2826 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2827 sizeof(struct xhci_dev_ctx64) : 2828 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2829 goto error; 2830 2831 usbd_get_page(pc, 0, &buf_dev); 2832 2833 pc = &sc->sc_hw.devs[index].input_pc; 2834 pg = &sc->sc_hw.devs[index].input_pg; 2835 2836 /* need to initialize the page cache */ 2837 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2838 2839 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2840 sizeof(struct xhci_input_dev_ctx64) : 2841 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2842 goto error; 2843 } 2844 2845 /* initialize all endpoint LINK TRBs */ 2846 2847 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2848 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2849 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2850 2851 /* need to initialize the page cache */ 2852 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2853 2854 if (usb_pc_alloc_mem(pc, pg, 2855 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2856 goto error; 2857 } 2858 2859 /* lookup endpoint TRB ring */ 2860 usbd_get_page(pc, 0, &buf_ep); 2861 2862 /* get TRB pointer */ 2863 trb = buf_ep.buffer; 2864 trb += XHCI_MAX_TRANSFERS - 1; 2865 2866 /* get TRB start address */ 2867 addr = buf_ep.physaddr; 2868 2869 /* create LINK TRB */ 2870 trb->qwTrb0 = htole64(addr); 2871 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2872 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2873 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2874 2875 usb_pc_cpu_flush(pc); 2876 } 2877 2878 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2879 2880 return (0); 2881 2882 error: 2883 xhci_free_device_ext(udev); 2884 2885 return (USB_ERR_NOMEM); 2886 } 2887 2888 static void 2889 xhci_free_device_ext(struct usb_device *udev) 2890 { 2891 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2892 uint8_t index; 2893 uint8_t i; 2894 2895 index = udev->controller_slot_id; 2896 xhci_set_slot_pointer(sc, index, 0); 2897 2898 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2899 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2900 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2901 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2902 } 2903 2904 static struct xhci_endpoint_ext * 2905 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2906 { 2907 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2908 struct xhci_endpoint_ext *pepext; 2909 struct usb_page_cache *pc; 2910 struct usb_page_search buf_ep; 2911 uint8_t epno; 2912 uint8_t index; 2913 2914 epno = edesc->bEndpointAddress; 2915 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2916 epno |= UE_DIR_IN; 2917 2918 epno = XHCI_EPNO2EPID(epno); 2919 2920 index = udev->controller_slot_id; 2921 2922 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2923 2924 usbd_get_page(pc, 0, &buf_ep); 2925 2926 pepext = &sc->sc_hw.devs[index].endp[epno]; 2927 pepext->page_cache = pc; 2928 pepext->trb = buf_ep.buffer; 2929 pepext->physaddr = buf_ep.physaddr; 2930 2931 return (pepext); 2932 } 2933 2934 static void 2935 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2936 { 2937 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2938 uint8_t epno; 2939 uint8_t index; 2940 2941 epno = xfer->endpointno; 2942 if (xfer->flags_int.control_xfr) 2943 epno |= UE_DIR_IN; 2944 2945 epno = XHCI_EPNO2EPID(epno); 2946 index = xfer->xroot->udev->controller_slot_id; 2947 2948 if (xfer->xroot->udev->flags.self_suspended == 0) { 2949 XWRITE4(sc, door, XHCI_DOORBELL(index), 2950 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2951 } 2952 } 2953 2954 static void 2955 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2956 { 2957 struct xhci_endpoint_ext *pepext; 2958 2959 if (xfer->flags_int.bandwidth_reclaimed) { 2960 xfer->flags_int.bandwidth_reclaimed = 0; 2961 2962 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2963 xfer->endpoint->edesc); 2964 2965 pepext->trb_used[xfer->stream_id]--; 2966 2967 pepext->xfer[xfer->qh_pos] = NULL; 2968 2969 if (error && pepext->trb_running != 0) { 2970 pepext->trb_halted = 1; 2971 pepext->trb_running = 0; 2972 } 2973 } 2974 } 2975 2976 static usb_error_t 2977 xhci_transfer_insert(struct usb_xfer *xfer) 2978 { 2979 struct xhci_td *td_first; 2980 struct xhci_td *td_last; 2981 struct xhci_trb *trb_link; 2982 struct xhci_endpoint_ext *pepext; 2983 uint64_t addr; 2984 usb_stream_t id; 2985 uint8_t i; 2986 uint8_t inext; 2987 uint8_t trb_limit; 2988 2989 DPRINTFN(8, "\n"); 2990 2991 id = xfer->stream_id; 2992 2993 /* check if already inserted */ 2994 if (xfer->flags_int.bandwidth_reclaimed) { 2995 DPRINTFN(8, "Already in schedule\n"); 2996 return (0); 2997 } 2998 2999 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3000 xfer->endpoint->edesc); 3001 3002 td_first = xfer->td_transfer_first; 3003 td_last = xfer->td_transfer_last; 3004 addr = pepext->physaddr; 3005 3006 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 3007 case UE_CONTROL: 3008 case UE_INTERRUPT: 3009 /* single buffered */ 3010 trb_limit = 1; 3011 break; 3012 default: 3013 /* multi buffered */ 3014 trb_limit = (XHCI_MAX_TRANSFERS - 2); 3015 break; 3016 } 3017 3018 if (pepext->trb_used[id] >= trb_limit) { 3019 DPRINTFN(8, "Too many TDs queued.\n"); 3020 return (USB_ERR_NOMEM); 3021 } 3022 3023 /* check if bMaxPacketSize changed */ 3024 if (xfer->flags_int.control_xfr != 0 && 3025 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) { 3026 DPRINTFN(8, "Reconfigure control endpoint\n"); 3027 3028 /* force driver to reconfigure endpoint */ 3029 pepext->trb_halted = 1; 3030 pepext->trb_running = 0; 3031 } 3032 3033 /* check for stopped condition, after putting transfer on interrupt queue */ 3034 if (pepext->trb_running == 0) { 3035 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3036 3037 DPRINTFN(8, "Not running\n"); 3038 3039 /* start configuration */ 3040 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3041 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3042 return (0); 3043 } 3044 3045 pepext->trb_used[id]++; 3046 3047 /* get current TRB index */ 3048 i = pepext->trb_index[id]; 3049 3050 /* get next TRB index */ 3051 inext = (i + 1); 3052 3053 /* the last entry of the ring is a hardcoded link TRB */ 3054 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 3055 inext = 0; 3056 3057 /* store next TRB index, before stream ID offset is added */ 3058 pepext->trb_index[id] = inext; 3059 3060 /* offset for stream */ 3061 i += id * XHCI_MAX_TRANSFERS; 3062 inext += id * XHCI_MAX_TRANSFERS; 3063 3064 /* compute terminating return address */ 3065 addr += (inext * sizeof(struct xhci_trb)); 3066 3067 /* compute link TRB pointer */ 3068 trb_link = td_last->td_trb + td_last->ntrb; 3069 3070 /* update next pointer of last link TRB */ 3071 trb_link->qwTrb0 = htole64(addr); 3072 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 3073 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 3074 XHCI_TRB_3_CYCLE_BIT | 3075 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 3076 3077 #ifdef USB_DEBUG 3078 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 3079 #endif 3080 usb_pc_cpu_flush(td_last->page_cache); 3081 3082 /* write ahead chain end marker */ 3083 3084 pepext->trb[inext].qwTrb0 = 0; 3085 pepext->trb[inext].dwTrb2 = 0; 3086 pepext->trb[inext].dwTrb3 = 0; 3087 3088 /* update next pointer of link TRB */ 3089 3090 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 3091 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 3092 3093 #ifdef USB_DEBUG 3094 xhci_dump_trb(&pepext->trb[i]); 3095 #endif 3096 usb_pc_cpu_flush(pepext->page_cache); 3097 3098 /* toggle cycle bit which activates the transfer chain */ 3099 3100 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 3101 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 3102 3103 usb_pc_cpu_flush(pepext->page_cache); 3104 3105 DPRINTF("qh_pos = %u\n", i); 3106 3107 pepext->xfer[i] = xfer; 3108 3109 xfer->qh_pos = i; 3110 3111 xfer->flags_int.bandwidth_reclaimed = 1; 3112 3113 xhci_endpoint_doorbell(xfer); 3114 3115 return (0); 3116 } 3117 3118 static void 3119 xhci_root_intr(struct xhci_softc *sc) 3120 { 3121 uint16_t i; 3122 3123 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3124 3125 /* clear any old interrupt data */ 3126 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 3127 3128 for (i = 1; i <= sc->sc_noport; i++) { 3129 /* pick out CHANGE bits from the status register */ 3130 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 3131 XHCI_PS_CSC | XHCI_PS_PEC | 3132 XHCI_PS_OCC | XHCI_PS_WRC | 3133 XHCI_PS_PRC | XHCI_PS_PLC | 3134 XHCI_PS_CEC)) { 3135 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 3136 DPRINTF("port %d changed\n", i); 3137 } 3138 } 3139 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3140 sizeof(sc->sc_hub_idata)); 3141 } 3142 3143 /*------------------------------------------------------------------------* 3144 * xhci_device_done - XHCI done handler 3145 * 3146 * NOTE: This function can be called two times in a row on 3147 * the same USB transfer. From close and from interrupt. 3148 *------------------------------------------------------------------------*/ 3149 static void 3150 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 3151 { 3152 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 3153 xfer, xfer->endpoint, error); 3154 3155 /* remove transfer from HW queue */ 3156 xhci_transfer_remove(xfer, error); 3157 3158 /* dequeue transfer and start next transfer */ 3159 usbd_transfer_done(xfer, error); 3160 } 3161 3162 /*------------------------------------------------------------------------* 3163 * XHCI data transfer support (generic type) 3164 *------------------------------------------------------------------------*/ 3165 static void 3166 xhci_device_generic_open(struct usb_xfer *xfer) 3167 { 3168 DPRINTF("\n"); 3169 } 3170 3171 static void 3172 xhci_device_generic_close(struct usb_xfer *xfer) 3173 { 3174 DPRINTF("\n"); 3175 3176 xhci_device_done(xfer, USB_ERR_CANCELLED); 3177 } 3178 3179 static void 3180 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3181 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3182 { 3183 struct usb_xfer *xfer; 3184 3185 /* check if there is a current transfer */ 3186 xfer = ep->endpoint_q[stream_id].curr; 3187 if (xfer == NULL) 3188 return; 3189 3190 /* 3191 * Check if the current transfer is started and then pickup 3192 * the next one, if any. Else wait for next start event due to 3193 * block on failure feature. 3194 */ 3195 if (!xfer->flags_int.bandwidth_reclaimed) 3196 return; 3197 3198 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3199 if (xfer == NULL) { 3200 /* 3201 * In case of enter we have to consider that the 3202 * transfer is queued by the USB core after the enter 3203 * method is called. 3204 */ 3205 xfer = enter_xfer; 3206 3207 if (xfer == NULL) 3208 return; 3209 } 3210 3211 /* try to multi buffer */ 3212 xhci_transfer_insert(xfer); 3213 } 3214 3215 static void 3216 xhci_device_generic_enter(struct usb_xfer *xfer) 3217 { 3218 DPRINTF("\n"); 3219 3220 /* set up TD's and QH */ 3221 xhci_setup_generic_chain(xfer); 3222 3223 xhci_device_generic_multi_enter(xfer->endpoint, 3224 xfer->stream_id, xfer); 3225 } 3226 3227 static void 3228 xhci_device_generic_start(struct usb_xfer *xfer) 3229 { 3230 DPRINTF("\n"); 3231 3232 /* try to insert xfer on HW queue */ 3233 xhci_transfer_insert(xfer); 3234 3235 /* try to multi buffer */ 3236 xhci_device_generic_multi_enter(xfer->endpoint, 3237 xfer->stream_id, NULL); 3238 3239 /* add transfer last on interrupt queue */ 3240 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3241 3242 /* start timeout, if any */ 3243 if (xfer->timeout != 0) 3244 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3245 } 3246 3247 static const struct usb_pipe_methods xhci_device_generic_methods = { 3248 .open = xhci_device_generic_open, 3249 .close = xhci_device_generic_close, 3250 .enter = xhci_device_generic_enter, 3251 .start = xhci_device_generic_start, 3252 }; 3253 3254 /*------------------------------------------------------------------------* 3255 * xhci root HUB support 3256 *------------------------------------------------------------------------* 3257 * Simulate a hardware HUB by handling all the necessary requests. 3258 *------------------------------------------------------------------------*/ 3259 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3260 3261 static const 3262 struct usb_device_descriptor xhci_devd = 3263 { 3264 .bLength = sizeof(xhci_devd), 3265 .bDescriptorType = UDESC_DEVICE, /* type */ 3266 HSETW(.bcdUSB, 0x0300), /* USB version */ 3267 .bDeviceClass = UDCLASS_HUB, /* class */ 3268 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3269 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3270 .bMaxPacketSize = 9, /* max packet size */ 3271 HSETW(.idVendor, 0x0000), /* vendor */ 3272 HSETW(.idProduct, 0x0000), /* product */ 3273 HSETW(.bcdDevice, 0x0100), /* device version */ 3274 .iManufacturer = 1, 3275 .iProduct = 2, 3276 .iSerialNumber = 0, 3277 .bNumConfigurations = 1, /* # of configurations */ 3278 }; 3279 3280 static const 3281 struct xhci_bos_desc xhci_bosd = { 3282 .bosd = { 3283 .bLength = sizeof(xhci_bosd.bosd), 3284 .bDescriptorType = UDESC_BOS, 3285 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3286 .bNumDeviceCaps = 3, 3287 }, 3288 .usb2extd = { 3289 .bLength = sizeof(xhci_bosd.usb2extd), 3290 .bDescriptorType = 1, 3291 .bDevCapabilityType = 2, 3292 .bmAttributes[0] = 2, 3293 }, 3294 .usbdcd = { 3295 .bLength = sizeof(xhci_bosd.usbdcd), 3296 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3297 .bDevCapabilityType = 3, 3298 .bmAttributes = 0, /* XXX */ 3299 HSETW(.wSpeedsSupported, 0x000C), 3300 .bFunctionalitySupport = 8, 3301 .bU1DevExitLat = 255, /* dummy - not used */ 3302 .wU2DevExitLat = { 0x00, 0x08 }, 3303 }, 3304 .cidd = { 3305 .bLength = sizeof(xhci_bosd.cidd), 3306 .bDescriptorType = 1, 3307 .bDevCapabilityType = 4, 3308 .bReserved = 0, 3309 .bContainerID = 0, /* XXX */ 3310 }, 3311 }; 3312 3313 static const 3314 struct xhci_config_desc xhci_confd = { 3315 .confd = { 3316 .bLength = sizeof(xhci_confd.confd), 3317 .bDescriptorType = UDESC_CONFIG, 3318 .wTotalLength[0] = sizeof(xhci_confd), 3319 .bNumInterface = 1, 3320 .bConfigurationValue = 1, 3321 .iConfiguration = 0, 3322 .bmAttributes = UC_SELF_POWERED, 3323 .bMaxPower = 0 /* max power */ 3324 }, 3325 .ifcd = { 3326 .bLength = sizeof(xhci_confd.ifcd), 3327 .bDescriptorType = UDESC_INTERFACE, 3328 .bNumEndpoints = 1, 3329 .bInterfaceClass = UICLASS_HUB, 3330 .bInterfaceSubClass = UISUBCLASS_HUB, 3331 .bInterfaceProtocol = 0, 3332 }, 3333 .endpd = { 3334 .bLength = sizeof(xhci_confd.endpd), 3335 .bDescriptorType = UDESC_ENDPOINT, 3336 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3337 .bmAttributes = UE_INTERRUPT, 3338 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3339 .bInterval = 255, 3340 }, 3341 .endpcd = { 3342 .bLength = sizeof(xhci_confd.endpcd), 3343 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3344 .bMaxBurst = 0, 3345 .bmAttributes = 0, 3346 }, 3347 }; 3348 3349 static const 3350 struct usb_hub_ss_descriptor xhci_hubd = { 3351 .bLength = sizeof(xhci_hubd), 3352 .bDescriptorType = UDESC_SS_HUB, 3353 }; 3354 3355 static usb_error_t 3356 xhci_roothub_exec(struct usb_device *udev, 3357 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3358 { 3359 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3360 const char *str_ptr; 3361 const void *ptr; 3362 uint32_t port; 3363 uint32_t v; 3364 uint16_t len; 3365 uint16_t i; 3366 uint16_t value; 3367 uint16_t index; 3368 uint8_t j; 3369 usb_error_t err; 3370 3371 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3372 3373 /* buffer reset */ 3374 ptr = (const void *)&sc->sc_hub_desc; 3375 len = 0; 3376 err = 0; 3377 3378 value = UGETW(req->wValue); 3379 index = UGETW(req->wIndex); 3380 3381 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3382 "wValue=0x%04x wIndex=0x%04x\n", 3383 req->bmRequestType, req->bRequest, 3384 UGETW(req->wLength), value, index); 3385 3386 #define C(x,y) ((x) | ((y) << 8)) 3387 switch (C(req->bRequest, req->bmRequestType)) { 3388 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3389 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3390 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3391 /* 3392 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3393 * for the integrated root hub. 3394 */ 3395 break; 3396 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3397 len = 1; 3398 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3399 break; 3400 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3401 switch (value >> 8) { 3402 case UDESC_DEVICE: 3403 if ((value & 0xff) != 0) { 3404 err = USB_ERR_IOERROR; 3405 goto done; 3406 } 3407 len = sizeof(xhci_devd); 3408 ptr = (const void *)&xhci_devd; 3409 break; 3410 3411 case UDESC_BOS: 3412 if ((value & 0xff) != 0) { 3413 err = USB_ERR_IOERROR; 3414 goto done; 3415 } 3416 len = sizeof(xhci_bosd); 3417 ptr = (const void *)&xhci_bosd; 3418 break; 3419 3420 case UDESC_CONFIG: 3421 if ((value & 0xff) != 0) { 3422 err = USB_ERR_IOERROR; 3423 goto done; 3424 } 3425 len = sizeof(xhci_confd); 3426 ptr = (const void *)&xhci_confd; 3427 break; 3428 3429 case UDESC_STRING: 3430 switch (value & 0xff) { 3431 case 0: /* Language table */ 3432 str_ptr = "\001"; 3433 break; 3434 3435 case 1: /* Vendor */ 3436 str_ptr = sc->sc_vendor; 3437 break; 3438 3439 case 2: /* Product */ 3440 str_ptr = "XHCI root HUB"; 3441 break; 3442 3443 default: 3444 str_ptr = ""; 3445 break; 3446 } 3447 3448 len = usb_make_str_desc( 3449 sc->sc_hub_desc.temp, 3450 sizeof(sc->sc_hub_desc.temp), 3451 str_ptr); 3452 break; 3453 3454 default: 3455 err = USB_ERR_IOERROR; 3456 goto done; 3457 } 3458 break; 3459 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3460 len = 1; 3461 sc->sc_hub_desc.temp[0] = 0; 3462 break; 3463 case C(UR_GET_STATUS, UT_READ_DEVICE): 3464 len = 2; 3465 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3466 break; 3467 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3468 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3469 len = 2; 3470 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3471 break; 3472 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3473 if (value >= XHCI_MAX_DEVICES) { 3474 err = USB_ERR_IOERROR; 3475 goto done; 3476 } 3477 break; 3478 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3479 if (value != 0 && value != 1) { 3480 err = USB_ERR_IOERROR; 3481 goto done; 3482 } 3483 sc->sc_conf = value; 3484 break; 3485 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3486 break; 3487 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3488 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3489 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3490 err = USB_ERR_IOERROR; 3491 goto done; 3492 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3493 break; 3494 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3495 break; 3496 /* Hub requests */ 3497 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3498 break; 3499 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3500 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3501 3502 if ((index < 1) || 3503 (index > sc->sc_noport)) { 3504 err = USB_ERR_IOERROR; 3505 goto done; 3506 } 3507 port = XHCI_PORTSC(index); 3508 3509 v = XREAD4(sc, oper, port); 3510 i = XHCI_PS_PLS_GET(v); 3511 v &= ~XHCI_PS_CLEAR; 3512 3513 switch (value) { 3514 case UHF_C_BH_PORT_RESET: 3515 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3516 break; 3517 case UHF_C_PORT_CONFIG_ERROR: 3518 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3519 break; 3520 case UHF_C_PORT_SUSPEND: 3521 case UHF_C_PORT_LINK_STATE: 3522 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3523 break; 3524 case UHF_C_PORT_CONNECTION: 3525 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3526 break; 3527 case UHF_C_PORT_ENABLE: 3528 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3529 break; 3530 case UHF_C_PORT_OVER_CURRENT: 3531 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3532 break; 3533 case UHF_C_PORT_RESET: 3534 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3535 break; 3536 case UHF_PORT_ENABLE: 3537 if ((sc->sc_quirks & XHCI_QUIRK_DISABLE_PORT_PED) == 0) 3538 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3539 break; 3540 case UHF_PORT_POWER: 3541 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3542 break; 3543 case UHF_PORT_INDICATOR: 3544 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3545 break; 3546 case UHF_PORT_SUSPEND: 3547 3548 /* U3 -> U15 */ 3549 if (i == 3) { 3550 XWRITE4(sc, oper, port, v | 3551 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3552 } 3553 3554 /* wait 20ms for resume sequence to complete */ 3555 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3556 3557 /* U0 */ 3558 XWRITE4(sc, oper, port, v | 3559 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3560 break; 3561 default: 3562 err = USB_ERR_IOERROR; 3563 goto done; 3564 } 3565 break; 3566 3567 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3568 if ((value & 0xff) != 0) { 3569 err = USB_ERR_IOERROR; 3570 goto done; 3571 } 3572 3573 v = XREAD4(sc, capa, XHCI_HCCPARAMS1); 3574 3575 sc->sc_hub_desc.hubd = xhci_hubd; 3576 3577 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3578 3579 if (XHCI_HCS0_PPC(v)) 3580 i = UHD_PWR_INDIVIDUAL; 3581 else 3582 i = UHD_PWR_GANGED; 3583 3584 if (XHCI_HCS0_PIND(v)) 3585 i |= UHD_PORT_IND; 3586 3587 i |= UHD_OC_INDIVIDUAL; 3588 3589 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3590 3591 /* see XHCI section 5.4.9: */ 3592 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3593 3594 for (j = 1; j <= sc->sc_noport; j++) { 3595 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3596 if (v & XHCI_PS_DR) { 3597 sc->sc_hub_desc.hubd. 3598 DeviceRemovable[j / 8] |= 1U << (j % 8); 3599 } 3600 } 3601 len = sc->sc_hub_desc.hubd.bLength; 3602 break; 3603 3604 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3605 len = 16; 3606 memset(sc->sc_hub_desc.temp, 0, 16); 3607 break; 3608 3609 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3610 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3611 3612 if ((index < 1) || 3613 (index > sc->sc_noport)) { 3614 err = USB_ERR_IOERROR; 3615 goto done; 3616 } 3617 3618 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3619 3620 DPRINTFN(9, "port status=0x%08x\n", v); 3621 3622 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3623 3624 switch (XHCI_PS_SPEED_GET(v)) { 3625 case XHCI_PS_SPEED_HIGH: 3626 i |= UPS_HIGH_SPEED; 3627 break; 3628 case XHCI_PS_SPEED_LOW: 3629 i |= UPS_LOW_SPEED; 3630 break; 3631 case XHCI_PS_SPEED_FULL: 3632 /* FULL speed */ 3633 break; 3634 default: 3635 i |= UPS_OTHER_SPEED; 3636 break; 3637 } 3638 3639 if (v & XHCI_PS_CCS) 3640 i |= UPS_CURRENT_CONNECT_STATUS; 3641 if (v & XHCI_PS_PED) 3642 i |= UPS_PORT_ENABLED; 3643 if (v & XHCI_PS_OCA) 3644 i |= UPS_OVERCURRENT_INDICATOR; 3645 if (v & XHCI_PS_PR) 3646 i |= UPS_RESET; 3647 #if 0 3648 if (v & XHCI_PS_PP) 3649 /* XXX undefined */ 3650 #endif 3651 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3652 3653 i = 0; 3654 if (v & XHCI_PS_CSC) 3655 i |= UPS_C_CONNECT_STATUS; 3656 if (v & XHCI_PS_PEC) 3657 i |= UPS_C_PORT_ENABLED; 3658 if (v & XHCI_PS_OCC) 3659 i |= UPS_C_OVERCURRENT_INDICATOR; 3660 if (v & XHCI_PS_WRC) 3661 i |= UPS_C_BH_PORT_RESET; 3662 if (v & XHCI_PS_PRC) 3663 i |= UPS_C_PORT_RESET; 3664 if (v & XHCI_PS_PLC) 3665 i |= UPS_C_PORT_LINK_STATE; 3666 if (v & XHCI_PS_CEC) 3667 i |= UPS_C_PORT_CONFIG_ERROR; 3668 3669 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3670 len = sizeof(sc->sc_hub_desc.ps); 3671 break; 3672 3673 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3674 err = USB_ERR_IOERROR; 3675 goto done; 3676 3677 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3678 break; 3679 3680 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3681 3682 i = index >> 8; 3683 index &= 0x00FF; 3684 3685 if ((index < 1) || 3686 (index > sc->sc_noport)) { 3687 err = USB_ERR_IOERROR; 3688 goto done; 3689 } 3690 3691 port = XHCI_PORTSC(index); 3692 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3693 3694 switch (value) { 3695 case UHF_PORT_U1_TIMEOUT: 3696 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3697 err = USB_ERR_IOERROR; 3698 goto done; 3699 } 3700 port = XHCI_PORTPMSC(index); 3701 v = XREAD4(sc, oper, port); 3702 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3703 v |= XHCI_PM3_U1TO_SET(i); 3704 XWRITE4(sc, oper, port, v); 3705 break; 3706 case UHF_PORT_U2_TIMEOUT: 3707 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3708 err = USB_ERR_IOERROR; 3709 goto done; 3710 } 3711 port = XHCI_PORTPMSC(index); 3712 v = XREAD4(sc, oper, port); 3713 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3714 v |= XHCI_PM3_U2TO_SET(i); 3715 XWRITE4(sc, oper, port, v); 3716 break; 3717 case UHF_BH_PORT_RESET: 3718 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3719 break; 3720 case UHF_PORT_LINK_STATE: 3721 XWRITE4(sc, oper, port, v | 3722 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3723 /* 4ms settle time */ 3724 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3725 break; 3726 case UHF_PORT_ENABLE: 3727 DPRINTFN(3, "set port enable %d\n", index); 3728 break; 3729 case UHF_PORT_SUSPEND: 3730 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3731 j = XHCI_PS_SPEED_GET(v); 3732 if (j == 0 || j >= XHCI_PS_SPEED_SS) { 3733 /* non-supported speed */ 3734 err = USB_ERR_IOERROR; 3735 goto done; 3736 } 3737 XWRITE4(sc, oper, port, v | 3738 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3739 break; 3740 case UHF_PORT_RESET: 3741 DPRINTFN(6, "reset port %d\n", index); 3742 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3743 break; 3744 case UHF_PORT_POWER: 3745 DPRINTFN(3, "set port power %d\n", index); 3746 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3747 break; 3748 case UHF_PORT_TEST: 3749 DPRINTFN(3, "set port test %d\n", index); 3750 break; 3751 case UHF_PORT_INDICATOR: 3752 DPRINTFN(3, "set port indicator %d\n", index); 3753 3754 v &= ~XHCI_PS_PIC_SET(3); 3755 v |= XHCI_PS_PIC_SET(1); 3756 3757 XWRITE4(sc, oper, port, v); 3758 break; 3759 default: 3760 err = USB_ERR_IOERROR; 3761 goto done; 3762 } 3763 break; 3764 3765 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3766 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3767 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3768 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3769 break; 3770 default: 3771 err = USB_ERR_IOERROR; 3772 goto done; 3773 } 3774 done: 3775 *plength = len; 3776 *pptr = ptr; 3777 return (err); 3778 } 3779 3780 static void 3781 xhci_xfer_setup(struct usb_setup_params *parm) 3782 { 3783 struct usb_page_search page_info; 3784 struct usb_page_cache *pc; 3785 struct usb_xfer *xfer; 3786 void *last_obj; 3787 uint32_t ntd; 3788 uint32_t n; 3789 3790 xfer = parm->curr_xfer; 3791 3792 /* 3793 * The proof for the "ntd" formula is illustrated like this: 3794 * 3795 * +------------------------------------+ 3796 * | | 3797 * | |remainder -> | 3798 * | +-----+---+ | 3799 * | | xxx | x | frm 0 | 3800 * | +-----+---++ | 3801 * | | xxx | xx | frm 1 | 3802 * | +-----+----+ | 3803 * | ... | 3804 * +------------------------------------+ 3805 * 3806 * "xxx" means a completely full USB transfer descriptor 3807 * 3808 * "x" and "xx" means a short USB packet 3809 * 3810 * For the remainder of an USB transfer modulo 3811 * "max_data_length" we need two USB transfer descriptors. 3812 * One to transfer the remaining data and one to finalise with 3813 * a zero length packet in case the "force_short_xfer" flag is 3814 * set. We only need two USB transfer descriptors in the case 3815 * where the transfer length of the first one is a factor of 3816 * "max_frame_size". The rest of the needed USB transfer 3817 * descriptors is given by the buffer size divided by the 3818 * maximum data payload. 3819 */ 3820 parm->hc_max_packet_size = 0x400; 3821 parm->hc_max_packet_count = 16 * 3; 3822 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3823 3824 xfer->flags_int.bdma_enable = 1; 3825 3826 usbd_transfer_setup_sub(parm); 3827 3828 if (xfer->flags_int.isochronous_xfr) { 3829 ntd = ((1 * xfer->nframes) 3830 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3831 } else if (xfer->flags_int.control_xfr) { 3832 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3833 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3834 } else { 3835 ntd = ((2 * xfer->nframes) 3836 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3837 } 3838 3839 alloc_dma_set: 3840 3841 if (parm->err) 3842 return; 3843 3844 /* 3845 * Allocate queue heads and transfer descriptors 3846 */ 3847 last_obj = NULL; 3848 3849 if (usbd_transfer_setup_sub_malloc( 3850 parm, &pc, sizeof(struct xhci_td), 3851 XHCI_TD_ALIGN, ntd)) { 3852 parm->err = USB_ERR_NOMEM; 3853 return; 3854 } 3855 if (parm->buf) { 3856 for (n = 0; n != ntd; n++) { 3857 struct xhci_td *td; 3858 3859 usbd_get_page(pc + n, 0, &page_info); 3860 3861 td = page_info.buffer; 3862 3863 /* init TD */ 3864 td->td_self = page_info.physaddr; 3865 td->obj_next = last_obj; 3866 td->page_cache = pc + n; 3867 3868 last_obj = td; 3869 3870 usb_pc_cpu_flush(pc + n); 3871 } 3872 } 3873 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3874 3875 if (!xfer->flags_int.curr_dma_set) { 3876 xfer->flags_int.curr_dma_set = 1; 3877 goto alloc_dma_set; 3878 } 3879 } 3880 3881 static uint8_t 3882 xhci_get_endpoint_state(struct usb_device *udev, uint8_t epno) 3883 { 3884 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3885 struct usb_page_search buf_dev; 3886 struct xhci_hw_dev *hdev; 3887 struct xhci_endp_ctx *endp; 3888 uint32_t temp; 3889 3890 MPASS(epno != 0); 3891 3892 hdev = &sc->sc_hw.devs[udev->controller_slot_id]; 3893 3894 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 3895 endp = XHCI_GET_CTX(sc, xhci_dev_ctx, ctx_ep[epno - 1], 3896 buf_dev.buffer); 3897 usb_pc_cpu_invalidate(&hdev->device_pc); 3898 3899 temp = le32toh(endp->dwEpCtx0); 3900 3901 return (XHCI_EPCTX_0_EPSTATE_GET(temp)); 3902 } 3903 3904 static usb_error_t 3905 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3906 { 3907 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3908 struct usb_page_search buf_inp; 3909 struct usb_device *udev; 3910 struct xhci_endpoint_ext *pepext; 3911 struct usb_endpoint_descriptor *edesc; 3912 struct usb_page_cache *pcinp; 3913 usb_error_t err; 3914 usb_stream_t stream_id; 3915 uint32_t mask; 3916 uint8_t index; 3917 uint8_t epno; 3918 uint8_t drop; 3919 3920 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3921 xfer->endpoint->edesc); 3922 3923 udev = xfer->xroot->udev; 3924 index = udev->controller_slot_id; 3925 3926 pcinp = &sc->sc_hw.devs[index].input_pc; 3927 3928 usbd_get_page(pcinp, 0, &buf_inp); 3929 3930 edesc = xfer->endpoint->edesc; 3931 3932 epno = edesc->bEndpointAddress; 3933 stream_id = xfer->stream_id; 3934 3935 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3936 epno |= UE_DIR_IN; 3937 3938 epno = XHCI_EPNO2EPID(epno); 3939 3940 if (epno == 0) 3941 return (USB_ERR_NO_PIPE); /* invalid */ 3942 3943 XHCI_CMD_LOCK(sc); 3944 3945 /* configure endpoint */ 3946 3947 err = xhci_configure_endpoint_by_xfer(xfer); 3948 3949 if (err != 0) { 3950 XHCI_CMD_UNLOCK(sc); 3951 return (err); 3952 } 3953 3954 /* 3955 * Get the endpoint into the stopped state according to the 3956 * endpoint context state diagram in the XHCI specification: 3957 */ 3958 switch (xhci_get_endpoint_state(udev, epno)) { 3959 case XHCI_EPCTX_0_EPSTATE_DISABLED: 3960 case XHCI_EPCTX_0_EPSTATE_STOPPED: 3961 drop = 0; 3962 break; 3963 case XHCI_EPCTX_0_EPSTATE_HALTED: 3964 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3965 drop = (err != 0); 3966 if (drop) 3967 DPRINTF("Could not reset endpoint %u\n", epno); 3968 break; 3969 default: 3970 /* 3971 * xHCI spec 4.6.8: 3972 * The Drop and Add operation resets the toggle bit, which can 3973 * cause a toggle mismatch between the device and host. As a 3974 * result, xHCI may refuse to receive or process the packet. 3975 */ 3976 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3977 drop = (err != 0); 3978 if (drop) 3979 DPRINTF("Could not stop endpoint %u\n", epno); 3980 break; 3981 } 3982 3983 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3984 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3985 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3986 stream_id, epno, index); 3987 3988 if (err != 0) 3989 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3990 3991 /* 3992 * Get the endpoint into the running state according to the 3993 * endpoint context state diagram in the XHCI specification: 3994 */ 3995 3996 mask = (1U << epno); 3997 3998 /* 3999 * So-called control and isochronous transfer types have 4000 * predefined data toggles (USB 2.0) or sequence numbers (USB 4001 * 3.0) and does not need to be dropped. 4002 */ 4003 if (drop != 0 && 4004 (edesc->bmAttributes & UE_XFERTYPE) != UE_CONTROL && 4005 (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) { 4006 /* drop endpoint context to reset data toggle value, if any. */ 4007 xhci_configure_mask(udev, mask, 1); 4008 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 4009 if (err != 0) { 4010 DPRINTF("Could not drop " 4011 "endpoint %u at slot %u.\n", epno, index); 4012 } else { 4013 sc->sc_hw.devs[index].ep_configured &= ~mask; 4014 } 4015 } 4016 4017 /* 4018 * Always need to evaluate the slot context, because the maximum 4019 * number of endpoint contexts is stored there. 4020 */ 4021 xhci_configure_mask(udev, mask | 1U, 0); 4022 4023 if (!(sc->sc_hw.devs[index].ep_configured & mask)) { 4024 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 4025 if (err == 0) 4026 sc->sc_hw.devs[index].ep_configured |= mask; 4027 } else { 4028 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4029 } 4030 4031 if (err != 0) { 4032 DPRINTF("Could not configure " 4033 "endpoint %u at slot %u.\n", epno, index); 4034 } 4035 XHCI_CMD_UNLOCK(sc); 4036 4037 return (0); 4038 } 4039 4040 static void 4041 xhci_xfer_unsetup(struct usb_xfer *xfer) 4042 { 4043 return; 4044 } 4045 4046 static void 4047 xhci_start_dma_delay(struct usb_xfer *xfer) 4048 { 4049 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 4050 4051 /* put transfer on interrupt queue (again) */ 4052 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 4053 4054 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 4055 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 4056 } 4057 4058 static void 4059 xhci_configure_msg(struct usb_proc_msg *pm) 4060 { 4061 struct xhci_softc *sc; 4062 struct xhci_endpoint_ext *pepext; 4063 struct usb_xfer *xfer; 4064 4065 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 4066 4067 restart: 4068 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4069 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 4070 xfer->endpoint->edesc); 4071 4072 if ((pepext->trb_halted != 0) || 4073 (pepext->trb_running == 0)) { 4074 uint16_t i; 4075 4076 /* clear halted and running */ 4077 pepext->trb_halted = 0; 4078 pepext->trb_running = 0; 4079 4080 /* nuke remaining buffered transfers */ 4081 4082 for (i = 0; i != (XHCI_MAX_TRANSFERS * 4083 XHCI_MAX_STREAMS); i++) { 4084 /* 4085 * NOTE: We need to use the timeout 4086 * error code here else existing 4087 * isochronous clients can get 4088 * confused: 4089 */ 4090 if (pepext->xfer[i] != NULL) { 4091 xhci_device_done(pepext->xfer[i], 4092 USB_ERR_TIMEOUT); 4093 } 4094 } 4095 4096 /* 4097 * NOTE: The USB transfer cannot vanish in 4098 * this state! 4099 */ 4100 4101 USB_BUS_UNLOCK(&sc->sc_bus); 4102 4103 xhci_configure_reset_endpoint(xfer); 4104 4105 USB_BUS_LOCK(&sc->sc_bus); 4106 4107 /* check if halted is still cleared */ 4108 if (pepext->trb_halted == 0) { 4109 pepext->trb_running = 1; 4110 memset(pepext->trb_index, 0, 4111 sizeof(pepext->trb_index)); 4112 } 4113 goto restart; 4114 } 4115 4116 if (xfer->flags_int.did_dma_delay) { 4117 /* remove transfer from interrupt queue (again) */ 4118 usbd_transfer_dequeue(xfer); 4119 4120 /* we are finally done */ 4121 usb_dma_delay_done_cb(xfer); 4122 4123 /* queue changed - restart */ 4124 goto restart; 4125 } 4126 } 4127 4128 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4129 /* try to insert xfer on HW queue */ 4130 xhci_transfer_insert(xfer); 4131 4132 /* try to multi buffer */ 4133 xhci_device_generic_multi_enter(xfer->endpoint, 4134 xfer->stream_id, NULL); 4135 } 4136 } 4137 4138 static void 4139 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4140 struct usb_endpoint *ep) 4141 { 4142 struct xhci_endpoint_ext *pepext; 4143 struct xhci_softc *sc; 4144 uint8_t index; 4145 uint8_t epno; 4146 4147 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 4148 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 4149 4150 if (udev->parent_hub == NULL) { 4151 /* root HUB has special endpoint handling */ 4152 return; 4153 } 4154 4155 ep->methods = &xhci_device_generic_methods; 4156 4157 pepext = xhci_get_endpoint_ext(udev, edesc); 4158 4159 USB_BUS_LOCK(udev->bus); 4160 pepext->trb_halted = 1; 4161 pepext->trb_running = 0; 4162 4163 /* 4164 * When doing an alternate setting, except for control 4165 * endpoints, we need to re-configure the XHCI endpoint 4166 * context: 4167 */ 4168 if ((edesc->bEndpointAddress & UE_ADDR) != 0) { 4169 sc = XHCI_BUS2SC(udev->bus); 4170 index = udev->controller_slot_id; 4171 epno = XHCI_EPNO2EPID(edesc->bEndpointAddress); 4172 sc->sc_hw.devs[index].ep_configured &= ~(1U << epno); 4173 } 4174 USB_BUS_UNLOCK(udev->bus); 4175 } 4176 4177 static void 4178 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 4179 { 4180 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4181 const struct usb_endpoint_descriptor *edesc = ep->edesc; 4182 struct usb_page_search buf_inp; 4183 struct usb_page_cache *pcinp; 4184 uint32_t mask; 4185 uint8_t index; 4186 uint8_t epno; 4187 usb_error_t err; 4188 4189 if (udev->parent_hub == NULL) { 4190 /* root HUB has special endpoint handling */ 4191 return; 4192 } 4193 4194 if ((edesc->bEndpointAddress & UE_ADDR) == 0) { 4195 /* control endpoint is never unconfigured */ 4196 return; 4197 } 4198 4199 XHCI_CMD_LOCK(sc); 4200 index = udev->controller_slot_id; 4201 epno = XHCI_EPNO2EPID(edesc->bEndpointAddress); 4202 mask = 1U << epno; 4203 4204 if (sc->sc_hw.devs[index].ep_configured & mask) { 4205 USB_BUS_LOCK(udev->bus); 4206 xhci_configure_mask(udev, mask, 1); 4207 USB_BUS_UNLOCK(udev->bus); 4208 4209 pcinp = &sc->sc_hw.devs[index].input_pc; 4210 usbd_get_page(pcinp, 0, &buf_inp); 4211 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 4212 if (err) { 4213 DPRINTF("Unconfiguring endpoint failed: %d\n", err); 4214 } else { 4215 USB_BUS_LOCK(udev->bus); 4216 sc->sc_hw.devs[index].ep_configured &= ~mask; 4217 USB_BUS_UNLOCK(udev->bus); 4218 } 4219 } 4220 XHCI_CMD_UNLOCK(sc); 4221 } 4222 4223 static void 4224 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 4225 { 4226 struct xhci_endpoint_ext *pepext; 4227 4228 DPRINTF("\n"); 4229 4230 if (udev->flags.usb_mode != USB_MODE_HOST) { 4231 /* not supported */ 4232 return; 4233 } 4234 if (udev->parent_hub == NULL) { 4235 /* root HUB has special endpoint handling */ 4236 return; 4237 } 4238 4239 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 4240 4241 USB_BUS_LOCK(udev->bus); 4242 pepext->trb_halted = 1; 4243 pepext->trb_running = 0; 4244 USB_BUS_UNLOCK(udev->bus); 4245 } 4246 4247 static usb_error_t 4248 xhci_device_init(struct usb_device *udev) 4249 { 4250 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4251 usb_error_t err; 4252 uint8_t temp; 4253 4254 /* no init for root HUB */ 4255 if (udev->parent_hub == NULL) 4256 return (0); 4257 4258 XHCI_CMD_LOCK(sc); 4259 4260 /* set invalid default */ 4261 4262 udev->controller_slot_id = sc->sc_noslot + 1; 4263 4264 /* try to get a new slot ID from the XHCI */ 4265 4266 err = xhci_cmd_enable_slot(sc, &temp); 4267 4268 if (err) { 4269 XHCI_CMD_UNLOCK(sc); 4270 return (err); 4271 } 4272 4273 if (temp > sc->sc_noslot) { 4274 XHCI_CMD_UNLOCK(sc); 4275 return (USB_ERR_BAD_ADDRESS); 4276 } 4277 4278 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4279 DPRINTF("slot %u already allocated.\n", temp); 4280 XHCI_CMD_UNLOCK(sc); 4281 return (USB_ERR_BAD_ADDRESS); 4282 } 4283 4284 /* store slot ID for later reference */ 4285 4286 udev->controller_slot_id = temp; 4287 4288 /* reset data structure */ 4289 4290 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4291 4292 /* set mark slot allocated */ 4293 4294 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4295 4296 err = xhci_alloc_device_ext(udev); 4297 4298 XHCI_CMD_UNLOCK(sc); 4299 4300 /* get device into default state */ 4301 4302 if (err == 0) 4303 err = xhci_set_address(udev, NULL, 0); 4304 4305 return (err); 4306 } 4307 4308 static void 4309 xhci_device_uninit(struct usb_device *udev) 4310 { 4311 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4312 uint8_t index; 4313 4314 /* no init for root HUB */ 4315 if (udev->parent_hub == NULL) 4316 return; 4317 4318 XHCI_CMD_LOCK(sc); 4319 4320 index = udev->controller_slot_id; 4321 4322 if (index <= sc->sc_noslot) { 4323 xhci_cmd_disable_slot(sc, index); 4324 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4325 4326 /* free device extension */ 4327 xhci_free_device_ext(udev); 4328 } 4329 4330 XHCI_CMD_UNLOCK(sc); 4331 } 4332 4333 static void 4334 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4335 { 4336 /* 4337 * Wait until the hardware has finished any possible use of 4338 * the transfer descriptor(s) 4339 */ 4340 *pus = 2048; /* microseconds */ 4341 } 4342 4343 static void 4344 xhci_device_resume(struct usb_device *udev) 4345 { 4346 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4347 uint8_t index; 4348 uint8_t n; 4349 uint8_t p; 4350 4351 DPRINTF("\n"); 4352 4353 /* check for root HUB */ 4354 if (udev->parent_hub == NULL) 4355 return; 4356 4357 index = udev->controller_slot_id; 4358 4359 XHCI_CMD_LOCK(sc); 4360 4361 /* blindly resume all endpoints */ 4362 4363 USB_BUS_LOCK(udev->bus); 4364 4365 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4366 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4367 XWRITE4(sc, door, XHCI_DOORBELL(index), 4368 n | XHCI_DB_SID_SET(p)); 4369 } 4370 } 4371 4372 USB_BUS_UNLOCK(udev->bus); 4373 4374 XHCI_CMD_UNLOCK(sc); 4375 } 4376 4377 static void 4378 xhci_device_suspend(struct usb_device *udev) 4379 { 4380 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4381 uint8_t index; 4382 uint8_t n; 4383 usb_error_t err; 4384 4385 DPRINTF("\n"); 4386 4387 /* check for root HUB */ 4388 if (udev->parent_hub == NULL) 4389 return; 4390 4391 index = udev->controller_slot_id; 4392 4393 XHCI_CMD_LOCK(sc); 4394 4395 /* blindly suspend all endpoints */ 4396 4397 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4398 err = xhci_cmd_stop_ep(sc, 1, n, index); 4399 if (err != 0) { 4400 DPRINTF("Failed to suspend endpoint " 4401 "%u on slot %u (ignored).\n", n, index); 4402 } 4403 } 4404 4405 XHCI_CMD_UNLOCK(sc); 4406 } 4407 4408 static void 4409 xhci_set_hw_power(struct usb_bus *bus) 4410 { 4411 DPRINTF("\n"); 4412 } 4413 4414 static void 4415 xhci_device_state_change(struct usb_device *udev) 4416 { 4417 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4418 struct usb_page_search buf_inp; 4419 usb_error_t err; 4420 uint8_t index; 4421 4422 /* check for root HUB */ 4423 if (udev->parent_hub == NULL) 4424 return; 4425 4426 index = udev->controller_slot_id; 4427 4428 DPRINTF("\n"); 4429 4430 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4431 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4432 &sc->sc_hw.devs[index].tt); 4433 if (err != 0) 4434 sc->sc_hw.devs[index].nports = 0; 4435 } 4436 4437 XHCI_CMD_LOCK(sc); 4438 4439 switch (usb_get_device_state(udev)) { 4440 case USB_STATE_POWERED: 4441 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4442 break; 4443 4444 /* set default state */ 4445 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4446 sc->sc_hw.devs[index].ep_configured = 3U; 4447 4448 /* reset number of contexts */ 4449 sc->sc_hw.devs[index].context_num = 0; 4450 4451 err = xhci_cmd_reset_dev(sc, index); 4452 4453 if (err != 0) { 4454 DPRINTF("Device reset failed " 4455 "for slot %u.\n", index); 4456 } 4457 break; 4458 4459 case USB_STATE_ADDRESSED: 4460 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4461 break; 4462 4463 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4464 sc->sc_hw.devs[index].ep_configured = 3U; 4465 4466 /* set configure mask to slot only */ 4467 xhci_configure_mask(udev, 1, 0); 4468 4469 /* deconfigure all endpoints, except EP0 */ 4470 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4471 4472 if (err) { 4473 DPRINTF("Failed to deconfigure " 4474 "slot %u.\n", index); 4475 } 4476 break; 4477 4478 case USB_STATE_CONFIGURED: 4479 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) { 4480 /* deconfigure all endpoints, except EP0 */ 4481 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4482 4483 if (err) { 4484 DPRINTF("Failed to deconfigure " 4485 "slot %u.\n", index); 4486 } 4487 } 4488 4489 /* set configured state */ 4490 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4491 sc->sc_hw.devs[index].ep_configured = 3U; 4492 4493 /* reset number of contexts */ 4494 sc->sc_hw.devs[index].context_num = 0; 4495 4496 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4497 4498 xhci_configure_mask(udev, 3, 0); 4499 4500 err = xhci_configure_device(udev); 4501 if (err != 0) { 4502 DPRINTF("Could not configure device " 4503 "at slot %u.\n", index); 4504 } 4505 4506 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4507 if (err != 0) { 4508 DPRINTF("Could not evaluate device " 4509 "context at slot %u.\n", index); 4510 } 4511 break; 4512 4513 default: 4514 break; 4515 } 4516 XHCI_CMD_UNLOCK(sc); 4517 } 4518 4519 static usb_error_t 4520 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4521 uint8_t ep_mode) 4522 { 4523 switch (ep_mode) { 4524 case USB_EP_MODE_DEFAULT: 4525 return (0); 4526 case USB_EP_MODE_STREAMS: 4527 if (xhcistreams == 0 || 4528 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4529 udev->speed != USB_SPEED_SUPER) 4530 return (USB_ERR_INVAL); 4531 return (0); 4532 default: 4533 return (USB_ERR_INVAL); 4534 } 4535 } 4536 4537 static const struct usb_bus_methods xhci_bus_methods = { 4538 .endpoint_init = xhci_ep_init, 4539 .endpoint_uninit = xhci_ep_uninit, 4540 .xfer_setup = xhci_xfer_setup, 4541 .xfer_unsetup = xhci_xfer_unsetup, 4542 .get_dma_delay = xhci_get_dma_delay, 4543 .device_init = xhci_device_init, 4544 .device_uninit = xhci_device_uninit, 4545 .device_resume = xhci_device_resume, 4546 .device_suspend = xhci_device_suspend, 4547 .set_hw_power = xhci_set_hw_power, 4548 .roothub_exec = xhci_roothub_exec, 4549 .xfer_poll = xhci_do_poll, 4550 .start_dma_delay = xhci_start_dma_delay, 4551 .set_address = xhci_set_address, 4552 .clear_stall = xhci_ep_clear_stall, 4553 .device_state_change = xhci_device_state_change, 4554 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4555 .set_endpoint_mode = xhci_set_endpoint_mode, 4556 }; 4557 4558 MODULE_VERSION(xhci, 1); 4559