1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36 /* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43 #ifdef USB_GLOBAL_INCLUDE_FILE 44 #include USB_GLOBAL_INCLUDE_FILE 45 #else 46 #include <sys/stdint.h> 47 #include <sys/stddef.h> 48 #include <sys/param.h> 49 #include <sys/queue.h> 50 #include <sys/types.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/bus.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/condvar.h> 58 #include <sys/sysctl.h> 59 #include <sys/sx.h> 60 #include <sys/unistd.h> 61 #include <sys/callout.h> 62 #include <sys/malloc.h> 63 #include <sys/priv.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 68 #define USB_DEBUG_VAR xhcidebug 69 70 #include <dev/usb/usb_core.h> 71 #include <dev/usb/usb_debug.h> 72 #include <dev/usb/usb_busdma.h> 73 #include <dev/usb/usb_process.h> 74 #include <dev/usb/usb_transfer.h> 75 #include <dev/usb/usb_device.h> 76 #include <dev/usb/usb_hub.h> 77 #include <dev/usb/usb_util.h> 78 79 #include <dev/usb/usb_controller.h> 80 #include <dev/usb/usb_bus.h> 81 #endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83 #include <dev/usb/controller/xhci.h> 84 #include <dev/usb/controller/xhcireg.h> 85 86 #define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 92 static int xhcistreams; 93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN, 94 &xhcistreams, 0, "Set to enable streams mode support"); 95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams); 96 97 #ifdef USB_DEBUG 98 static int xhcidebug; 99 static int xhciroute; 100 static int xhcipolling; 101 102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 103 &xhcidebug, 0, "Debug level"); 104 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN, 106 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 107 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN, 109 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller"); 110 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling); 111 #else 112 #define xhciroute 0 113 #endif 114 115 #define XHCI_INTR_ENDPT 1 116 117 struct xhci_std_temp { 118 struct xhci_softc *sc; 119 struct usb_page_cache *pc; 120 struct xhci_td *td; 121 struct xhci_td *td_next; 122 uint32_t len; 123 uint32_t offset; 124 uint32_t max_packet_size; 125 uint32_t average; 126 uint16_t isoc_delta; 127 uint16_t isoc_frame; 128 uint8_t shortpkt; 129 uint8_t multishort; 130 uint8_t last_frame; 131 uint8_t trb_type; 132 uint8_t direction; 133 uint8_t tbc; 134 uint8_t tlbpc; 135 uint8_t step_td; 136 uint8_t do_isoc_sync; 137 }; 138 139 static void xhci_do_poll(struct usb_bus *); 140 static void xhci_device_done(struct usb_xfer *, usb_error_t); 141 static void xhci_root_intr(struct xhci_softc *); 142 static void xhci_free_device_ext(struct usb_device *); 143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 144 struct usb_endpoint_descriptor *); 145 static usb_proc_callback_t xhci_configure_msg; 146 static usb_error_t xhci_configure_device(struct usb_device *); 147 static usb_error_t xhci_configure_endpoint(struct usb_device *, 148 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 149 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 150 uint8_t); 151 static usb_error_t xhci_configure_mask(struct usb_device *, 152 uint32_t, uint8_t); 153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 154 uint64_t, uint8_t); 155 static void xhci_endpoint_doorbell(struct usb_xfer *); 156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 159 #ifdef USB_DEBUG 160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 161 #endif 162 163 static const struct usb_bus_methods xhci_bus_methods; 164 165 #ifdef USB_DEBUG 166 static void 167 xhci_dump_trb(struct xhci_trb *trb) 168 { 169 DPRINTFN(5, "trb = %p\n", trb); 170 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 171 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 172 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 173 } 174 175 static void 176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 177 { 178 DPRINTFN(5, "pep = %p\n", pep); 179 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 180 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 181 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 182 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 183 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 184 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 185 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 186 } 187 188 static void 189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 190 { 191 DPRINTFN(5, "psl = %p\n", psl); 192 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 193 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 194 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 195 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 196 } 197 #endif 198 199 uint8_t 200 xhci_use_polling(void) 201 { 202 #ifdef USB_DEBUG 203 return (xhcipolling != 0); 204 #else 205 return (0); 206 #endif 207 } 208 209 static void 210 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 211 { 212 struct xhci_softc *sc = XHCI_BUS2SC(bus); 213 uint8_t i; 214 215 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 216 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 217 218 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 219 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 220 221 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 222 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 223 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 224 } 225 } 226 227 static void 228 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 229 { 230 if (sc->sc_ctx_is_64_byte) { 231 uint32_t offset; 232 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 233 /* all contexts are initially 32-bytes */ 234 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 235 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 236 } 237 *ptr = htole32(val); 238 } 239 240 static uint32_t 241 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 242 { 243 if (sc->sc_ctx_is_64_byte) { 244 uint32_t offset; 245 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 246 /* all contexts are initially 32-bytes */ 247 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 248 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 249 } 250 return (le32toh(*ptr)); 251 } 252 253 static void 254 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 255 { 256 if (sc->sc_ctx_is_64_byte) { 257 uint32_t offset; 258 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 259 /* all contexts are initially 32-bytes */ 260 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 261 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 262 } 263 *ptr = htole64(val); 264 } 265 266 #ifdef USB_DEBUG 267 static uint64_t 268 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 269 { 270 if (sc->sc_ctx_is_64_byte) { 271 uint32_t offset; 272 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 273 /* all contexts are initially 32-bytes */ 274 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 275 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 276 } 277 return (le64toh(*ptr)); 278 } 279 #endif 280 281 static int 282 xhci_reset_command_queue_locked(struct xhci_softc *sc) 283 { 284 struct usb_page_search buf_res; 285 struct xhci_hw_root *phwr; 286 uint64_t addr; 287 uint32_t temp; 288 289 DPRINTF("\n"); 290 291 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 292 if (temp & XHCI_CRCR_LO_CRR) { 293 DPRINTF("Command ring running\n"); 294 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 295 296 /* 297 * Try to abort the last command as per section 298 * 4.6.1.2 "Aborting a Command" of the XHCI 299 * specification: 300 */ 301 302 /* stop and cancel */ 303 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 304 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 305 306 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 307 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 308 309 /* wait 250ms */ 310 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 311 312 /* check if command ring is still running */ 313 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 314 if (temp & XHCI_CRCR_LO_CRR) { 315 DPRINTF("Comand ring still running\n"); 316 return (USB_ERR_IOERROR); 317 } 318 } 319 320 /* reset command ring */ 321 sc->sc_command_ccs = 1; 322 sc->sc_command_idx = 0; 323 324 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 325 326 /* setup command ring control base address */ 327 addr = buf_res.physaddr; 328 phwr = buf_res.buffer; 329 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 330 331 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 332 333 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 334 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 335 336 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 337 338 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 339 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 340 341 return (0); 342 } 343 344 usb_error_t 345 xhci_start_controller(struct xhci_softc *sc) 346 { 347 struct usb_page_search buf_res; 348 struct xhci_hw_root *phwr; 349 struct xhci_dev_ctx_addr *pdctxa; 350 uint64_t addr; 351 uint32_t temp; 352 uint16_t i; 353 354 DPRINTF("\n"); 355 356 sc->sc_capa_off = 0; 357 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 358 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 359 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 360 361 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 362 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 363 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 364 365 sc->sc_event_ccs = 1; 366 sc->sc_event_idx = 0; 367 sc->sc_command_ccs = 1; 368 sc->sc_command_idx = 0; 369 370 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 371 372 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 373 374 DPRINTF("HCS0 = 0x%08x\n", temp); 375 376 if (XHCI_HCS0_CSZ(temp)) { 377 sc->sc_ctx_is_64_byte = 1; 378 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 379 } else { 380 sc->sc_ctx_is_64_byte = 0; 381 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 382 } 383 384 /* Reset controller */ 385 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 386 387 for (i = 0; i != 100; i++) { 388 usb_pause_mtx(NULL, hz / 100); 389 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 390 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 391 if (!temp) 392 break; 393 } 394 395 if (temp) { 396 device_printf(sc->sc_bus.parent, "Controller " 397 "reset timeout.\n"); 398 return (USB_ERR_IOERROR); 399 } 400 401 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 402 device_printf(sc->sc_bus.parent, "Controller does " 403 "not support 4K page size.\n"); 404 return (USB_ERR_IOERROR); 405 } 406 407 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 408 409 i = XHCI_HCS1_N_PORTS(temp); 410 411 if (i == 0) { 412 device_printf(sc->sc_bus.parent, "Invalid number " 413 "of ports: %u\n", i); 414 return (USB_ERR_IOERROR); 415 } 416 417 sc->sc_noport = i; 418 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 419 420 if (sc->sc_noslot > XHCI_MAX_DEVICES) 421 sc->sc_noslot = XHCI_MAX_DEVICES; 422 423 /* setup number of device slots */ 424 425 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 426 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 427 428 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 429 430 DPRINTF("Max slots: %u\n", sc->sc_noslot); 431 432 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 433 434 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 435 436 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 437 device_printf(sc->sc_bus.parent, "XHCI request " 438 "too many scratchpads\n"); 439 return (USB_ERR_NOMEM); 440 } 441 442 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 443 444 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 445 446 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 447 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 448 449 temp = XREAD4(sc, oper, XHCI_USBSTS); 450 451 /* clear interrupts */ 452 XWRITE4(sc, oper, XHCI_USBSTS, temp); 453 /* disable all device notifications */ 454 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 455 456 /* setup device context base address */ 457 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 458 pdctxa = buf_res.buffer; 459 memset(pdctxa, 0, sizeof(*pdctxa)); 460 461 addr = buf_res.physaddr; 462 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 463 464 /* slot 0 points to the table of scratchpad pointers */ 465 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 466 467 for (i = 0; i != sc->sc_noscratch; i++) { 468 struct usb_page_search buf_scp; 469 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 470 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 471 } 472 473 addr = buf_res.physaddr; 474 475 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 476 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 477 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 478 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 479 480 /* Setup event table size */ 481 482 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 483 484 DPRINTF("HCS2=0x%08x\n", temp); 485 486 temp = XHCI_HCS2_ERST_MAX(temp); 487 temp = 1U << temp; 488 if (temp > XHCI_MAX_RSEG) 489 temp = XHCI_MAX_RSEG; 490 491 sc->sc_erst_max = temp; 492 493 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 494 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 495 496 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 497 498 /* Setup interrupt rate */ 499 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 500 501 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 502 503 phwr = buf_res.buffer; 504 addr = buf_res.physaddr; 505 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 506 507 /* reset hardware root structure */ 508 memset(phwr, 0, sizeof(*phwr)); 509 510 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 511 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 512 513 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 514 515 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 516 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 517 518 addr = (uint64_t)buf_res.physaddr; 519 520 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 521 522 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 523 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 524 525 /* Setup interrupter registers */ 526 527 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 528 temp |= XHCI_IMAN_INTR_ENA; 529 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 530 531 /* setup command ring control base address */ 532 addr = buf_res.physaddr; 533 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 534 535 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 536 537 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 538 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 539 540 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 541 542 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 543 544 /* Go! */ 545 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 546 XHCI_CMD_INTE | XHCI_CMD_HSEE); 547 548 for (i = 0; i != 100; i++) { 549 usb_pause_mtx(NULL, hz / 100); 550 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 551 if (!temp) 552 break; 553 } 554 if (temp) { 555 XWRITE4(sc, oper, XHCI_USBCMD, 0); 556 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 557 return (USB_ERR_IOERROR); 558 } 559 560 /* catch any lost interrupts */ 561 xhci_do_poll(&sc->sc_bus); 562 563 if (sc->sc_port_route != NULL) { 564 /* Route all ports to the XHCI by default */ 565 sc->sc_port_route(sc->sc_bus.parent, 566 ~xhciroute, xhciroute); 567 } 568 return (0); 569 } 570 571 usb_error_t 572 xhci_halt_controller(struct xhci_softc *sc) 573 { 574 uint32_t temp; 575 uint16_t i; 576 577 DPRINTF("\n"); 578 579 sc->sc_capa_off = 0; 580 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 581 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 582 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 583 584 /* Halt controller */ 585 XWRITE4(sc, oper, XHCI_USBCMD, 0); 586 587 for (i = 0; i != 100; i++) { 588 usb_pause_mtx(NULL, hz / 100); 589 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 590 if (temp) 591 break; 592 } 593 594 if (!temp) { 595 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 596 return (USB_ERR_IOERROR); 597 } 598 return (0); 599 } 600 601 usb_error_t 602 xhci_init(struct xhci_softc *sc, device_t self) 603 { 604 /* initialise some bus fields */ 605 sc->sc_bus.parent = self; 606 607 /* set the bus revision */ 608 sc->sc_bus.usbrev = USB_REV_3_0; 609 610 /* set up the bus struct */ 611 sc->sc_bus.methods = &xhci_bus_methods; 612 613 /* setup devices array */ 614 sc->sc_bus.devices = sc->sc_devices; 615 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 616 617 /* setup command queue mutex and condition varible */ 618 cv_init(&sc->sc_cmd_cv, "CMDQ"); 619 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 620 621 /* get all DMA memory */ 622 if (usb_bus_mem_alloc_all(&sc->sc_bus, 623 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 624 return (ENOMEM); 625 } 626 627 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 628 sc->sc_config_msg[0].bus = &sc->sc_bus; 629 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 630 sc->sc_config_msg[1].bus = &sc->sc_bus; 631 632 return (0); 633 } 634 635 void 636 xhci_uninit(struct xhci_softc *sc) 637 { 638 /* 639 * NOTE: At this point the control transfer process is gone 640 * and "xhci_configure_msg" is no longer called. Consequently 641 * waiting for the configuration messages to complete is not 642 * needed. 643 */ 644 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 645 646 cv_destroy(&sc->sc_cmd_cv); 647 sx_destroy(&sc->sc_cmd_sx); 648 } 649 650 static void 651 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 652 { 653 struct xhci_softc *sc = XHCI_BUS2SC(bus); 654 655 switch (state) { 656 case USB_HW_POWER_SUSPEND: 657 DPRINTF("Stopping the XHCI\n"); 658 xhci_halt_controller(sc); 659 break; 660 case USB_HW_POWER_SHUTDOWN: 661 DPRINTF("Stopping the XHCI\n"); 662 xhci_halt_controller(sc); 663 break; 664 case USB_HW_POWER_RESUME: 665 DPRINTF("Starting the XHCI\n"); 666 xhci_start_controller(sc); 667 break; 668 default: 669 break; 670 } 671 } 672 673 static usb_error_t 674 xhci_generic_done_sub(struct usb_xfer *xfer) 675 { 676 struct xhci_td *td; 677 struct xhci_td *td_alt_next; 678 uint32_t len; 679 uint8_t status; 680 681 td = xfer->td_transfer_cache; 682 td_alt_next = td->alt_next; 683 684 if (xfer->aframes != xfer->nframes) 685 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 686 687 while (1) { 688 689 usb_pc_cpu_invalidate(td->page_cache); 690 691 status = td->status; 692 len = td->remainder; 693 694 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 695 xfer, (unsigned int)xfer->aframes, 696 (unsigned int)xfer->nframes, 697 (unsigned int)len, (unsigned int)td->len, 698 (unsigned int)status); 699 700 /* 701 * Verify the status length and 702 * add the length to "frlengths[]": 703 */ 704 if (len > td->len) { 705 /* should not happen */ 706 DPRINTF("Invalid status length, " 707 "0x%04x/0x%04x bytes\n", len, td->len); 708 status = XHCI_TRB_ERROR_LENGTH; 709 } else if (xfer->aframes != xfer->nframes) { 710 xfer->frlengths[xfer->aframes] += td->len - len; 711 } 712 /* Check for last transfer */ 713 if (((void *)td) == xfer->td_transfer_last) { 714 td = NULL; 715 break; 716 } 717 /* Check for transfer error */ 718 if (status != XHCI_TRB_ERROR_SHORT_PKT && 719 status != XHCI_TRB_ERROR_SUCCESS) { 720 /* the transfer is finished */ 721 td = NULL; 722 break; 723 } 724 /* Check for short transfer */ 725 if (len > 0) { 726 if (xfer->flags_int.short_frames_ok || 727 xfer->flags_int.isochronous_xfr || 728 xfer->flags_int.control_xfr) { 729 /* follow alt next */ 730 td = td->alt_next; 731 } else { 732 /* the transfer is finished */ 733 td = NULL; 734 } 735 break; 736 } 737 td = td->obj_next; 738 739 if (td->alt_next != td_alt_next) { 740 /* this USB frame is complete */ 741 break; 742 } 743 } 744 745 /* update transfer cache */ 746 747 xfer->td_transfer_cache = td; 748 749 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 750 (status != XHCI_TRB_ERROR_SHORT_PKT && 751 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 752 USB_ERR_NORMAL_COMPLETION); 753 } 754 755 static void 756 xhci_generic_done(struct usb_xfer *xfer) 757 { 758 usb_error_t err = 0; 759 760 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 761 xfer, xfer->endpoint); 762 763 /* reset scanner */ 764 765 xfer->td_transfer_cache = xfer->td_transfer_first; 766 767 if (xfer->flags_int.control_xfr) { 768 769 if (xfer->flags_int.control_hdr) 770 err = xhci_generic_done_sub(xfer); 771 772 xfer->aframes = 1; 773 774 if (xfer->td_transfer_cache == NULL) 775 goto done; 776 } 777 778 while (xfer->aframes != xfer->nframes) { 779 780 err = xhci_generic_done_sub(xfer); 781 xfer->aframes++; 782 783 if (xfer->td_transfer_cache == NULL) 784 goto done; 785 } 786 787 if (xfer->flags_int.control_xfr && 788 !xfer->flags_int.control_act) 789 err = xhci_generic_done_sub(xfer); 790 done: 791 /* transfer is complete */ 792 xhci_device_done(xfer, err); 793 } 794 795 static void 796 xhci_activate_transfer(struct usb_xfer *xfer) 797 { 798 struct xhci_td *td; 799 800 td = xfer->td_transfer_cache; 801 802 usb_pc_cpu_invalidate(td->page_cache); 803 804 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 805 806 /* activate the transfer */ 807 808 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 809 usb_pc_cpu_flush(td->page_cache); 810 811 xhci_endpoint_doorbell(xfer); 812 } 813 } 814 815 static void 816 xhci_skip_transfer(struct usb_xfer *xfer) 817 { 818 struct xhci_td *td; 819 struct xhci_td *td_last; 820 821 td = xfer->td_transfer_cache; 822 td_last = xfer->td_transfer_last; 823 824 td = td->alt_next; 825 826 usb_pc_cpu_invalidate(td->page_cache); 827 828 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 829 830 usb_pc_cpu_invalidate(td_last->page_cache); 831 832 /* copy LINK TRB to current waiting location */ 833 834 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 835 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 836 usb_pc_cpu_flush(td->page_cache); 837 838 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 839 usb_pc_cpu_flush(td->page_cache); 840 841 xhci_endpoint_doorbell(xfer); 842 } 843 } 844 845 /*------------------------------------------------------------------------* 846 * xhci_check_transfer 847 *------------------------------------------------------------------------*/ 848 static void 849 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 850 { 851 struct xhci_endpoint_ext *pepext; 852 int64_t offset; 853 uint64_t td_event; 854 uint32_t temp; 855 uint32_t remainder; 856 uint16_t stream_id; 857 uint16_t i; 858 uint8_t status; 859 uint8_t halted; 860 uint8_t epno; 861 uint8_t index; 862 863 /* decode TRB */ 864 td_event = le64toh(trb->qwTrb0); 865 temp = le32toh(trb->dwTrb2); 866 867 remainder = XHCI_TRB_2_REM_GET(temp); 868 status = XHCI_TRB_2_ERROR_GET(temp); 869 stream_id = XHCI_TRB_2_STREAM_GET(temp); 870 871 temp = le32toh(trb->dwTrb3); 872 epno = XHCI_TRB_3_EP_GET(temp); 873 index = XHCI_TRB_3_SLOT_GET(temp); 874 875 /* check if error means halted */ 876 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 877 status != XHCI_TRB_ERROR_SUCCESS); 878 879 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 880 index, epno, stream_id, remainder, status); 881 882 if (index > sc->sc_noslot) { 883 DPRINTF("Invalid slot.\n"); 884 return; 885 } 886 887 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 888 DPRINTF("Invalid endpoint.\n"); 889 return; 890 } 891 892 pepext = &sc->sc_hw.devs[index].endp[epno]; 893 894 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 895 stream_id = 0; 896 DPRINTF("stream_id=0\n"); 897 } else if (stream_id >= XHCI_MAX_STREAMS) { 898 DPRINTF("Invalid stream ID.\n"); 899 return; 900 } 901 902 /* try to find the USB transfer that generated the event */ 903 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 904 struct usb_xfer *xfer; 905 struct xhci_td *td; 906 907 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 908 if (xfer == NULL) 909 continue; 910 911 td = xfer->td_transfer_cache; 912 913 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 914 (long long)td_event, 915 (long long)td->td_self, 916 (long long)td->td_self + sizeof(td->td_trb)); 917 918 /* 919 * NOTE: Some XHCI implementations might not trigger 920 * an event on the last LINK TRB so we need to 921 * consider both the last and second last event 922 * address as conditions for a successful transfer. 923 * 924 * NOTE: We assume that the XHCI will only trigger one 925 * event per chain of TRBs. 926 */ 927 928 offset = td_event - td->td_self; 929 930 if (offset >= 0 && 931 offset < (int64_t)sizeof(td->td_trb)) { 932 933 usb_pc_cpu_invalidate(td->page_cache); 934 935 /* compute rest of remainder, if any */ 936 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 937 temp = le32toh(td->td_trb[i].dwTrb2); 938 remainder += XHCI_TRB_2_BYTES_GET(temp); 939 } 940 941 DPRINTFN(5, "New remainder: %u\n", remainder); 942 943 /* clear isochronous transfer errors */ 944 if (xfer->flags_int.isochronous_xfr) { 945 if (halted) { 946 halted = 0; 947 status = XHCI_TRB_ERROR_SUCCESS; 948 remainder = td->len; 949 } 950 } 951 952 /* "td->remainder" is verified later */ 953 td->remainder = remainder; 954 td->status = status; 955 956 usb_pc_cpu_flush(td->page_cache); 957 958 /* 959 * 1) Last transfer descriptor makes the 960 * transfer done 961 */ 962 if (((void *)td) == xfer->td_transfer_last) { 963 DPRINTF("TD is last\n"); 964 xhci_generic_done(xfer); 965 break; 966 } 967 968 /* 969 * 2) Any kind of error makes the transfer 970 * done 971 */ 972 if (halted) { 973 DPRINTF("TD has I/O error\n"); 974 xhci_generic_done(xfer); 975 break; 976 } 977 978 /* 979 * 3) If there is no alternate next transfer, 980 * a short packet also makes the transfer done 981 */ 982 if (td->remainder > 0) { 983 if (td->alt_next == NULL) { 984 DPRINTF( 985 "short TD has no alternate next\n"); 986 xhci_generic_done(xfer); 987 break; 988 } 989 DPRINTF("TD has short pkt\n"); 990 if (xfer->flags_int.short_frames_ok || 991 xfer->flags_int.isochronous_xfr || 992 xfer->flags_int.control_xfr) { 993 /* follow the alt next */ 994 xfer->td_transfer_cache = td->alt_next; 995 xhci_activate_transfer(xfer); 996 break; 997 } 998 xhci_skip_transfer(xfer); 999 xhci_generic_done(xfer); 1000 break; 1001 } 1002 1003 /* 1004 * 4) Transfer complete - go to next TD 1005 */ 1006 DPRINTF("Following next TD\n"); 1007 xfer->td_transfer_cache = td->obj_next; 1008 xhci_activate_transfer(xfer); 1009 break; /* there should only be one match */ 1010 } 1011 } 1012 } 1013 1014 static int 1015 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1016 { 1017 if (sc->sc_cmd_addr == trb->qwTrb0) { 1018 DPRINTF("Received command event\n"); 1019 sc->sc_cmd_result[0] = trb->dwTrb2; 1020 sc->sc_cmd_result[1] = trb->dwTrb3; 1021 cv_signal(&sc->sc_cmd_cv); 1022 return (1); /* command match */ 1023 } 1024 return (0); 1025 } 1026 1027 static int 1028 xhci_interrupt_poll(struct xhci_softc *sc) 1029 { 1030 struct usb_page_search buf_res; 1031 struct xhci_hw_root *phwr; 1032 uint64_t addr; 1033 uint32_t temp; 1034 int retval = 0; 1035 uint16_t i; 1036 uint8_t event; 1037 uint8_t j; 1038 uint8_t k; 1039 uint8_t t; 1040 1041 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1042 1043 phwr = buf_res.buffer; 1044 1045 /* Receive any events */ 1046 1047 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1048 1049 i = sc->sc_event_idx; 1050 j = sc->sc_event_ccs; 1051 t = 2; 1052 1053 while (1) { 1054 1055 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1056 1057 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1058 1059 if (j != k) 1060 break; 1061 1062 event = XHCI_TRB_3_TYPE_GET(temp); 1063 1064 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1065 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1066 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1067 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1068 1069 switch (event) { 1070 case XHCI_TRB_EVENT_TRANSFER: 1071 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1072 break; 1073 case XHCI_TRB_EVENT_CMD_COMPLETE: 1074 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1075 break; 1076 default: 1077 DPRINTF("Unhandled event = %u\n", event); 1078 break; 1079 } 1080 1081 i++; 1082 1083 if (i == XHCI_MAX_EVENTS) { 1084 i = 0; 1085 j ^= 1; 1086 1087 /* check for timeout */ 1088 if (!--t) 1089 break; 1090 } 1091 } 1092 1093 sc->sc_event_idx = i; 1094 sc->sc_event_ccs = j; 1095 1096 /* 1097 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1098 * latched. That means to activate the register we need to 1099 * write both the low and high double word of the 64-bit 1100 * register. 1101 */ 1102 1103 addr = (uint32_t)buf_res.physaddr; 1104 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1105 1106 /* try to clear busy bit */ 1107 addr |= XHCI_ERDP_LO_BUSY; 1108 1109 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1110 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1111 1112 return (retval); 1113 } 1114 1115 static usb_error_t 1116 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1117 uint16_t timeout_ms) 1118 { 1119 struct usb_page_search buf_res; 1120 struct xhci_hw_root *phwr; 1121 uint64_t addr; 1122 uint32_t temp; 1123 uint8_t i; 1124 uint8_t j; 1125 uint8_t timeout = 0; 1126 int err; 1127 1128 XHCI_CMD_ASSERT_LOCKED(sc); 1129 1130 /* get hardware root structure */ 1131 1132 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1133 1134 phwr = buf_res.buffer; 1135 1136 /* Queue command */ 1137 1138 USB_BUS_LOCK(&sc->sc_bus); 1139 retry: 1140 i = sc->sc_command_idx; 1141 j = sc->sc_command_ccs; 1142 1143 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1144 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1145 (long long)le64toh(trb->qwTrb0), 1146 (long)le32toh(trb->dwTrb2), 1147 (long)le32toh(trb->dwTrb3)); 1148 1149 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1150 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1151 1152 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1153 1154 temp = trb->dwTrb3; 1155 1156 if (j) 1157 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1158 else 1159 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1160 1161 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1162 1163 phwr->hwr_commands[i].dwTrb3 = temp; 1164 1165 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1166 1167 addr = buf_res.physaddr; 1168 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1169 1170 sc->sc_cmd_addr = htole64(addr); 1171 1172 i++; 1173 1174 if (i == (XHCI_MAX_COMMANDS - 1)) { 1175 1176 if (j) { 1177 temp = htole32(XHCI_TRB_3_TC_BIT | 1178 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1179 XHCI_TRB_3_CYCLE_BIT); 1180 } else { 1181 temp = htole32(XHCI_TRB_3_TC_BIT | 1182 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1183 } 1184 1185 phwr->hwr_commands[i].dwTrb3 = temp; 1186 1187 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1188 1189 i = 0; 1190 j ^= 1; 1191 } 1192 1193 sc->sc_command_idx = i; 1194 sc->sc_command_ccs = j; 1195 1196 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1197 1198 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1199 USB_MS_TO_TICKS(timeout_ms)); 1200 1201 /* 1202 * In some error cases event interrupts are not generated. 1203 * Poll one time to see if the command has completed. 1204 */ 1205 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1206 DPRINTF("Command was completed when polling\n"); 1207 err = 0; 1208 } 1209 if (err != 0) { 1210 DPRINTF("Command timeout!\n"); 1211 /* 1212 * After some weeks of continuous operation, it has 1213 * been observed that the ASMedia Technology, ASM1042 1214 * SuperSpeed USB Host Controller can suddenly stop 1215 * accepting commands via the command queue. Try to 1216 * first reset the command queue. If that fails do a 1217 * host controller reset. 1218 */ 1219 if (timeout == 0 && 1220 xhci_reset_command_queue_locked(sc) == 0) { 1221 timeout = 1; 1222 goto retry; 1223 } else { 1224 DPRINTF("Controller reset!\n"); 1225 usb_bus_reset_async_locked(&sc->sc_bus); 1226 } 1227 err = USB_ERR_TIMEOUT; 1228 trb->dwTrb2 = 0; 1229 trb->dwTrb3 = 0; 1230 } else { 1231 temp = le32toh(sc->sc_cmd_result[0]); 1232 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1233 err = USB_ERR_IOERROR; 1234 1235 trb->dwTrb2 = sc->sc_cmd_result[0]; 1236 trb->dwTrb3 = sc->sc_cmd_result[1]; 1237 } 1238 1239 USB_BUS_UNLOCK(&sc->sc_bus); 1240 1241 return (err); 1242 } 1243 1244 #if 0 1245 static usb_error_t 1246 xhci_cmd_nop(struct xhci_softc *sc) 1247 { 1248 struct xhci_trb trb; 1249 uint32_t temp; 1250 1251 DPRINTF("\n"); 1252 1253 trb.qwTrb0 = 0; 1254 trb.dwTrb2 = 0; 1255 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1256 1257 trb.dwTrb3 = htole32(temp); 1258 1259 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1260 } 1261 #endif 1262 1263 static usb_error_t 1264 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1265 { 1266 struct xhci_trb trb; 1267 uint32_t temp; 1268 usb_error_t err; 1269 1270 DPRINTF("\n"); 1271 1272 trb.qwTrb0 = 0; 1273 trb.dwTrb2 = 0; 1274 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1275 1276 err = xhci_do_command(sc, &trb, 100 /* ms */); 1277 if (err) 1278 goto done; 1279 1280 temp = le32toh(trb.dwTrb3); 1281 1282 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1283 1284 done: 1285 return (err); 1286 } 1287 1288 static usb_error_t 1289 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1290 { 1291 struct xhci_trb trb; 1292 uint32_t temp; 1293 1294 DPRINTF("\n"); 1295 1296 trb.qwTrb0 = 0; 1297 trb.dwTrb2 = 0; 1298 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1299 XHCI_TRB_3_SLOT_SET(slot_id); 1300 1301 trb.dwTrb3 = htole32(temp); 1302 1303 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1304 } 1305 1306 static usb_error_t 1307 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1308 uint8_t bsr, uint8_t slot_id) 1309 { 1310 struct xhci_trb trb; 1311 uint32_t temp; 1312 1313 DPRINTF("\n"); 1314 1315 trb.qwTrb0 = htole64(input_ctx); 1316 trb.dwTrb2 = 0; 1317 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1318 XHCI_TRB_3_SLOT_SET(slot_id); 1319 1320 if (bsr) 1321 temp |= XHCI_TRB_3_BSR_BIT; 1322 1323 trb.dwTrb3 = htole32(temp); 1324 1325 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1326 } 1327 1328 static usb_error_t 1329 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1330 { 1331 struct usb_page_search buf_inp; 1332 struct usb_page_search buf_dev; 1333 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1334 struct xhci_hw_dev *hdev; 1335 struct xhci_dev_ctx *pdev; 1336 struct xhci_endpoint_ext *pepext; 1337 uint32_t temp; 1338 uint16_t mps; 1339 usb_error_t err; 1340 uint8_t index; 1341 1342 /* the root HUB case is not handled here */ 1343 if (udev->parent_hub == NULL) 1344 return (USB_ERR_INVAL); 1345 1346 index = udev->controller_slot_id; 1347 1348 hdev = &sc->sc_hw.devs[index]; 1349 1350 if (mtx != NULL) 1351 mtx_unlock(mtx); 1352 1353 XHCI_CMD_LOCK(sc); 1354 1355 switch (hdev->state) { 1356 case XHCI_ST_DEFAULT: 1357 case XHCI_ST_ENABLED: 1358 1359 hdev->state = XHCI_ST_ENABLED; 1360 1361 /* set configure mask to slot and EP0 */ 1362 xhci_configure_mask(udev, 3, 0); 1363 1364 /* configure input slot context structure */ 1365 err = xhci_configure_device(udev); 1366 1367 if (err != 0) { 1368 DPRINTF("Could not configure device\n"); 1369 break; 1370 } 1371 1372 /* configure input endpoint context structure */ 1373 switch (udev->speed) { 1374 case USB_SPEED_LOW: 1375 case USB_SPEED_FULL: 1376 mps = 8; 1377 break; 1378 case USB_SPEED_HIGH: 1379 mps = 64; 1380 break; 1381 default: 1382 mps = 512; 1383 break; 1384 } 1385 1386 pepext = xhci_get_endpoint_ext(udev, 1387 &udev->ctrl_ep_desc); 1388 err = xhci_configure_endpoint(udev, 1389 &udev->ctrl_ep_desc, pepext, 1390 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1391 1392 if (err != 0) { 1393 DPRINTF("Could not configure default endpoint\n"); 1394 break; 1395 } 1396 1397 /* execute set address command */ 1398 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1399 1400 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1401 (address == 0), index); 1402 1403 if (err != 0) { 1404 temp = le32toh(sc->sc_cmd_result[0]); 1405 if (address == 0 && sc->sc_port_route != NULL && 1406 XHCI_TRB_2_ERROR_GET(temp) == 1407 XHCI_TRB_ERROR_PARAMETER) { 1408 /* LynxPoint XHCI - ports are not switchable */ 1409 /* Un-route all ports from the XHCI */ 1410 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1411 } 1412 DPRINTF("Could not set address " 1413 "for slot %u.\n", index); 1414 if (address != 0) 1415 break; 1416 } 1417 1418 /* update device address to new value */ 1419 1420 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1421 pdev = buf_dev.buffer; 1422 usb_pc_cpu_invalidate(&hdev->device_pc); 1423 1424 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1425 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1426 1427 /* update device state to new value */ 1428 1429 if (address != 0) 1430 hdev->state = XHCI_ST_ADDRESSED; 1431 else 1432 hdev->state = XHCI_ST_DEFAULT; 1433 break; 1434 1435 default: 1436 DPRINTF("Wrong state for set address.\n"); 1437 err = USB_ERR_IOERROR; 1438 break; 1439 } 1440 XHCI_CMD_UNLOCK(sc); 1441 1442 if (mtx != NULL) 1443 mtx_lock(mtx); 1444 1445 return (err); 1446 } 1447 1448 static usb_error_t 1449 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1450 uint8_t deconfigure, uint8_t slot_id) 1451 { 1452 struct xhci_trb trb; 1453 uint32_t temp; 1454 1455 DPRINTF("\n"); 1456 1457 trb.qwTrb0 = htole64(input_ctx); 1458 trb.dwTrb2 = 0; 1459 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1460 XHCI_TRB_3_SLOT_SET(slot_id); 1461 1462 if (deconfigure) 1463 temp |= XHCI_TRB_3_DCEP_BIT; 1464 1465 trb.dwTrb3 = htole32(temp); 1466 1467 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1468 } 1469 1470 static usb_error_t 1471 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1472 uint8_t slot_id) 1473 { 1474 struct xhci_trb trb; 1475 uint32_t temp; 1476 1477 DPRINTF("\n"); 1478 1479 trb.qwTrb0 = htole64(input_ctx); 1480 trb.dwTrb2 = 0; 1481 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1482 XHCI_TRB_3_SLOT_SET(slot_id); 1483 trb.dwTrb3 = htole32(temp); 1484 1485 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1486 } 1487 1488 static usb_error_t 1489 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1490 uint8_t ep_id, uint8_t slot_id) 1491 { 1492 struct xhci_trb trb; 1493 uint32_t temp; 1494 1495 DPRINTF("\n"); 1496 1497 trb.qwTrb0 = 0; 1498 trb.dwTrb2 = 0; 1499 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1500 XHCI_TRB_3_SLOT_SET(slot_id) | 1501 XHCI_TRB_3_EP_SET(ep_id); 1502 1503 if (preserve) 1504 temp |= XHCI_TRB_3_PRSV_BIT; 1505 1506 trb.dwTrb3 = htole32(temp); 1507 1508 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1509 } 1510 1511 static usb_error_t 1512 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1513 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1514 { 1515 struct xhci_trb trb; 1516 uint32_t temp; 1517 1518 DPRINTF("\n"); 1519 1520 trb.qwTrb0 = htole64(dequeue_ptr); 1521 1522 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1523 trb.dwTrb2 = htole32(temp); 1524 1525 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1526 XHCI_TRB_3_SLOT_SET(slot_id) | 1527 XHCI_TRB_3_EP_SET(ep_id); 1528 trb.dwTrb3 = htole32(temp); 1529 1530 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1531 } 1532 1533 static usb_error_t 1534 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1535 uint8_t ep_id, uint8_t slot_id) 1536 { 1537 struct xhci_trb trb; 1538 uint32_t temp; 1539 1540 DPRINTF("\n"); 1541 1542 trb.qwTrb0 = 0; 1543 trb.dwTrb2 = 0; 1544 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1545 XHCI_TRB_3_SLOT_SET(slot_id) | 1546 XHCI_TRB_3_EP_SET(ep_id); 1547 1548 if (suspend) 1549 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1550 1551 trb.dwTrb3 = htole32(temp); 1552 1553 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1554 } 1555 1556 static usb_error_t 1557 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1558 { 1559 struct xhci_trb trb; 1560 uint32_t temp; 1561 1562 DPRINTF("\n"); 1563 1564 trb.qwTrb0 = 0; 1565 trb.dwTrb2 = 0; 1566 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1567 XHCI_TRB_3_SLOT_SET(slot_id); 1568 1569 trb.dwTrb3 = htole32(temp); 1570 1571 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1572 } 1573 1574 /*------------------------------------------------------------------------* 1575 * xhci_interrupt - XHCI interrupt handler 1576 *------------------------------------------------------------------------*/ 1577 void 1578 xhci_interrupt(struct xhci_softc *sc) 1579 { 1580 uint32_t status; 1581 uint32_t temp; 1582 1583 USB_BUS_LOCK(&sc->sc_bus); 1584 1585 status = XREAD4(sc, oper, XHCI_USBSTS); 1586 1587 /* acknowledge interrupts, if any */ 1588 if (status != 0) { 1589 XWRITE4(sc, oper, XHCI_USBSTS, status); 1590 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1591 } 1592 1593 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1594 1595 /* force clearing of pending interrupts */ 1596 if (temp & XHCI_IMAN_INTR_PEND) 1597 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1598 1599 /* check for event(s) */ 1600 xhci_interrupt_poll(sc); 1601 1602 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1603 XHCI_STS_HSE | XHCI_STS_HCE)) { 1604 1605 if (status & XHCI_STS_PCD) { 1606 xhci_root_intr(sc); 1607 } 1608 1609 if (status & XHCI_STS_HCH) { 1610 printf("%s: host controller halted\n", 1611 __FUNCTION__); 1612 } 1613 1614 if (status & XHCI_STS_HSE) { 1615 printf("%s: host system error\n", 1616 __FUNCTION__); 1617 } 1618 1619 if (status & XHCI_STS_HCE) { 1620 printf("%s: host controller error\n", 1621 __FUNCTION__); 1622 } 1623 } 1624 USB_BUS_UNLOCK(&sc->sc_bus); 1625 } 1626 1627 /*------------------------------------------------------------------------* 1628 * xhci_timeout - XHCI timeout handler 1629 *------------------------------------------------------------------------*/ 1630 static void 1631 xhci_timeout(void *arg) 1632 { 1633 struct usb_xfer *xfer = arg; 1634 1635 DPRINTF("xfer=%p\n", xfer); 1636 1637 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1638 1639 /* transfer is transferred */ 1640 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1641 } 1642 1643 static void 1644 xhci_do_poll(struct usb_bus *bus) 1645 { 1646 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1647 1648 USB_BUS_LOCK(&sc->sc_bus); 1649 xhci_interrupt_poll(sc); 1650 USB_BUS_UNLOCK(&sc->sc_bus); 1651 } 1652 1653 static void 1654 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1655 { 1656 struct usb_page_search buf_res; 1657 struct xhci_td *td; 1658 struct xhci_td *td_next; 1659 struct xhci_td *td_alt_next; 1660 struct xhci_td *td_first; 1661 uint32_t buf_offset; 1662 uint32_t average; 1663 uint32_t len_old; 1664 uint32_t npkt_off; 1665 uint32_t dword; 1666 uint8_t shortpkt_old; 1667 uint8_t precompute; 1668 uint8_t x; 1669 1670 td_alt_next = NULL; 1671 buf_offset = 0; 1672 shortpkt_old = temp->shortpkt; 1673 len_old = temp->len; 1674 npkt_off = 0; 1675 precompute = 1; 1676 1677 restart: 1678 1679 td = temp->td; 1680 td_next = td_first = temp->td_next; 1681 1682 while (1) { 1683 1684 if (temp->len == 0) { 1685 1686 if (temp->shortpkt) 1687 break; 1688 1689 /* send a Zero Length Packet, ZLP, last */ 1690 1691 temp->shortpkt = 1; 1692 average = 0; 1693 1694 } else { 1695 1696 average = temp->average; 1697 1698 if (temp->len < average) { 1699 if (temp->len % temp->max_packet_size) { 1700 temp->shortpkt = 1; 1701 } 1702 average = temp->len; 1703 } 1704 } 1705 1706 if (td_next == NULL) 1707 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1708 1709 /* get next TD */ 1710 1711 td = td_next; 1712 td_next = td->obj_next; 1713 1714 /* check if we are pre-computing */ 1715 1716 if (precompute) { 1717 1718 /* update remaining length */ 1719 1720 temp->len -= average; 1721 1722 continue; 1723 } 1724 /* fill out current TD */ 1725 1726 td->len = average; 1727 td->remainder = 0; 1728 td->status = 0; 1729 1730 /* update remaining length */ 1731 1732 temp->len -= average; 1733 1734 /* reset TRB index */ 1735 1736 x = 0; 1737 1738 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1739 /* immediate data */ 1740 1741 if (average > 8) 1742 average = 8; 1743 1744 td->td_trb[0].qwTrb0 = 0; 1745 1746 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1747 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1748 average); 1749 1750 dword = XHCI_TRB_2_BYTES_SET(8) | 1751 XHCI_TRB_2_TDSZ_SET(0) | 1752 XHCI_TRB_2_IRQ_SET(0); 1753 1754 td->td_trb[0].dwTrb2 = htole32(dword); 1755 1756 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1757 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1758 1759 /* check wLength */ 1760 if (td->td_trb[0].qwTrb0 & 1761 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1762 if (td->td_trb[0].qwTrb0 & 1763 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1764 dword |= XHCI_TRB_3_TRT_IN; 1765 else 1766 dword |= XHCI_TRB_3_TRT_OUT; 1767 } 1768 1769 td->td_trb[0].dwTrb3 = htole32(dword); 1770 #ifdef USB_DEBUG 1771 xhci_dump_trb(&td->td_trb[x]); 1772 #endif 1773 x++; 1774 1775 } else do { 1776 1777 uint32_t npkt; 1778 1779 /* fill out buffer pointers */ 1780 1781 if (average == 0) { 1782 memset(&buf_res, 0, sizeof(buf_res)); 1783 } else { 1784 usbd_get_page(temp->pc, temp->offset + 1785 buf_offset, &buf_res); 1786 1787 /* get length to end of page */ 1788 if (buf_res.length > average) 1789 buf_res.length = average; 1790 1791 /* check for maximum length */ 1792 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1793 buf_res.length = XHCI_TD_PAGE_SIZE; 1794 1795 npkt_off += buf_res.length; 1796 } 1797 1798 /* setup npkt */ 1799 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1800 temp->max_packet_size; 1801 1802 if (npkt == 0) 1803 npkt = 1; 1804 else if (npkt > 31) 1805 npkt = 31; 1806 1807 /* fill out TRB's */ 1808 td->td_trb[x].qwTrb0 = 1809 htole64((uint64_t)buf_res.physaddr); 1810 1811 dword = 1812 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1813 XHCI_TRB_2_TDSZ_SET(npkt) | 1814 XHCI_TRB_2_IRQ_SET(0); 1815 1816 td->td_trb[x].dwTrb2 = htole32(dword); 1817 1818 switch (temp->trb_type) { 1819 case XHCI_TRB_TYPE_ISOCH: 1820 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1821 XHCI_TRB_3_TBC_SET(temp->tbc) | 1822 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1823 if (td != td_first) { 1824 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1825 } else if (temp->do_isoc_sync != 0) { 1826 temp->do_isoc_sync = 0; 1827 /* wait until "isoc_frame" */ 1828 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1829 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1830 } else { 1831 /* start data transfer at next interval */ 1832 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1833 XHCI_TRB_3_ISO_SIA_BIT; 1834 } 1835 if (temp->direction == UE_DIR_IN) 1836 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1837 break; 1838 case XHCI_TRB_TYPE_DATA_STAGE: 1839 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1840 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 1841 XHCI_TRB_3_TBC_SET(temp->tbc) | 1842 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1843 if (temp->direction == UE_DIR_IN) 1844 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1845 break; 1846 case XHCI_TRB_TYPE_STATUS_STAGE: 1847 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1848 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 1849 XHCI_TRB_3_TBC_SET(temp->tbc) | 1850 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1851 if (temp->direction == UE_DIR_IN) 1852 dword |= XHCI_TRB_3_DIR_IN; 1853 break; 1854 default: /* XHCI_TRB_TYPE_NORMAL */ 1855 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1856 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 1857 XHCI_TRB_3_TBC_SET(temp->tbc) | 1858 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1859 if (temp->direction == UE_DIR_IN) 1860 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1861 break; 1862 } 1863 td->td_trb[x].dwTrb3 = htole32(dword); 1864 1865 average -= buf_res.length; 1866 buf_offset += buf_res.length; 1867 #ifdef USB_DEBUG 1868 xhci_dump_trb(&td->td_trb[x]); 1869 #endif 1870 x++; 1871 1872 } while (average != 0); 1873 1874 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1875 1876 /* store number of data TRB's */ 1877 1878 td->ntrb = x; 1879 1880 DPRINTF("NTRB=%u\n", x); 1881 1882 /* fill out link TRB */ 1883 1884 if (td_next != NULL) { 1885 /* link the current TD with the next one */ 1886 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1887 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1888 } else { 1889 /* this field will get updated later */ 1890 DPRINTF("NOLINK\n"); 1891 } 1892 1893 dword = XHCI_TRB_2_IRQ_SET(0); 1894 1895 td->td_trb[x].dwTrb2 = htole32(dword); 1896 1897 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1898 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1899 /* 1900 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1901 * frame only receives a single short packet event 1902 * by setting the CHAIN bit in the LINK field. In 1903 * addition some XHCI controllers have problems 1904 * sending a ZLP unless the CHAIN-BIT is set in 1905 * the LINK TRB. 1906 */ 1907 XHCI_TRB_3_CHAIN_BIT; 1908 1909 td->td_trb[x].dwTrb3 = htole32(dword); 1910 1911 td->alt_next = td_alt_next; 1912 #ifdef USB_DEBUG 1913 xhci_dump_trb(&td->td_trb[x]); 1914 #endif 1915 usb_pc_cpu_flush(td->page_cache); 1916 } 1917 1918 if (precompute) { 1919 precompute = 0; 1920 1921 /* setup alt next pointer, if any */ 1922 if (temp->last_frame) { 1923 td_alt_next = NULL; 1924 } else { 1925 /* we use this field internally */ 1926 td_alt_next = td_next; 1927 } 1928 1929 /* restore */ 1930 temp->shortpkt = shortpkt_old; 1931 temp->len = len_old; 1932 goto restart; 1933 } 1934 1935 /* 1936 * Remove cycle bit from the first TRB if we are 1937 * stepping them: 1938 */ 1939 if (temp->step_td != 0) { 1940 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1941 usb_pc_cpu_flush(td_first->page_cache); 1942 } 1943 1944 /* clear TD SIZE to zero, hence this is the last TRB */ 1945 /* remove chain bit because this is the last data TRB in the chain */ 1946 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1947 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1948 /* remove CHAIN-BIT from last LINK TRB */ 1949 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1950 1951 usb_pc_cpu_flush(td->page_cache); 1952 1953 temp->td = td; 1954 temp->td_next = td_next; 1955 } 1956 1957 static void 1958 xhci_setup_generic_chain(struct usb_xfer *xfer) 1959 { 1960 struct xhci_std_temp temp; 1961 struct xhci_td *td; 1962 uint32_t x; 1963 uint32_t y; 1964 uint8_t mult; 1965 1966 temp.do_isoc_sync = 0; 1967 temp.step_td = 0; 1968 temp.tbc = 0; 1969 temp.tlbpc = 0; 1970 temp.average = xfer->max_hc_frame_size; 1971 temp.max_packet_size = xfer->max_packet_size; 1972 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1973 temp.pc = NULL; 1974 temp.last_frame = 0; 1975 temp.offset = 0; 1976 temp.multishort = xfer->flags_int.isochronous_xfr || 1977 xfer->flags_int.control_xfr || 1978 xfer->flags_int.short_frames_ok; 1979 1980 /* toggle the DMA set we are using */ 1981 xfer->flags_int.curr_dma_set ^= 1; 1982 1983 /* get next DMA set */ 1984 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1985 1986 temp.td = NULL; 1987 temp.td_next = td; 1988 1989 xfer->td_transfer_first = td; 1990 xfer->td_transfer_cache = td; 1991 1992 if (xfer->flags_int.isochronous_xfr) { 1993 uint8_t shift; 1994 1995 /* compute multiplier for ISOCHRONOUS transfers */ 1996 mult = xfer->endpoint->ecomp ? 1997 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 1998 : 0; 1999 /* check for USB 2.0 multiplier */ 2000 if (mult == 0) { 2001 mult = (xfer->endpoint->edesc-> 2002 wMaxPacketSize[1] >> 3) & 3; 2003 } 2004 /* range check */ 2005 if (mult > 2) 2006 mult = 3; 2007 else 2008 mult++; 2009 2010 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2011 2012 DPRINTF("MFINDEX=0x%08x\n", x); 2013 2014 switch (usbd_get_speed(xfer->xroot->udev)) { 2015 case USB_SPEED_FULL: 2016 shift = 3; 2017 temp.isoc_delta = 8; /* 1ms */ 2018 x += temp.isoc_delta - 1; 2019 x &= ~(temp.isoc_delta - 1); 2020 break; 2021 default: 2022 shift = usbd_xfer_get_fps_shift(xfer); 2023 temp.isoc_delta = 1U << shift; 2024 x += temp.isoc_delta - 1; 2025 x &= ~(temp.isoc_delta - 1); 2026 /* simple frame load balancing */ 2027 x += xfer->endpoint->usb_uframe; 2028 break; 2029 } 2030 2031 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2032 2033 if ((xfer->endpoint->is_synced == 0) || 2034 (y < (xfer->nframes << shift)) || 2035 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2036 /* 2037 * If there is data underflow or the pipe 2038 * queue is empty we schedule the transfer a 2039 * few frames ahead of the current frame 2040 * position. Else two isochronous transfers 2041 * might overlap. 2042 */ 2043 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2044 xfer->endpoint->is_synced = 1; 2045 temp.do_isoc_sync = 1; 2046 2047 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2048 } 2049 2050 /* compute isochronous completion time */ 2051 2052 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2053 2054 xfer->isoc_time_complete = 2055 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2056 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2057 2058 x = 0; 2059 temp.isoc_frame = xfer->endpoint->isoc_next; 2060 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2061 2062 xfer->endpoint->isoc_next += xfer->nframes << shift; 2063 2064 } else if (xfer->flags_int.control_xfr) { 2065 2066 /* check if we should prepend a setup message */ 2067 2068 if (xfer->flags_int.control_hdr) { 2069 2070 temp.len = xfer->frlengths[0]; 2071 temp.pc = xfer->frbuffers + 0; 2072 temp.shortpkt = temp.len ? 1 : 0; 2073 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2074 temp.direction = 0; 2075 2076 /* check for last frame */ 2077 if (xfer->nframes == 1) { 2078 /* no STATUS stage yet, SETUP is last */ 2079 if (xfer->flags_int.control_act) 2080 temp.last_frame = 1; 2081 } 2082 2083 xhci_setup_generic_chain_sub(&temp); 2084 } 2085 x = 1; 2086 mult = 1; 2087 temp.isoc_delta = 0; 2088 temp.isoc_frame = 0; 2089 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 2090 } else { 2091 x = 0; 2092 mult = 1; 2093 temp.isoc_delta = 0; 2094 temp.isoc_frame = 0; 2095 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2096 } 2097 2098 if (x != xfer->nframes) { 2099 /* setup page_cache pointer */ 2100 temp.pc = xfer->frbuffers + x; 2101 /* set endpoint direction */ 2102 temp.direction = UE_GET_DIR(xfer->endpointno); 2103 } 2104 2105 while (x != xfer->nframes) { 2106 2107 /* DATA0 / DATA1 message */ 2108 2109 temp.len = xfer->frlengths[x]; 2110 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2111 x != 0 && temp.multishort == 0); 2112 2113 x++; 2114 2115 if (x == xfer->nframes) { 2116 if (xfer->flags_int.control_xfr) { 2117 /* no STATUS stage yet, DATA is last */ 2118 if (xfer->flags_int.control_act) 2119 temp.last_frame = 1; 2120 } else { 2121 temp.last_frame = 1; 2122 } 2123 } 2124 if (temp.len == 0) { 2125 2126 /* make sure that we send an USB packet */ 2127 2128 temp.shortpkt = 0; 2129 2130 temp.tbc = 0; 2131 temp.tlbpc = mult - 1; 2132 2133 } else if (xfer->flags_int.isochronous_xfr) { 2134 2135 uint8_t tdpc; 2136 2137 /* 2138 * Isochronous transfers don't have short 2139 * packet termination: 2140 */ 2141 2142 temp.shortpkt = 1; 2143 2144 /* isochronous transfers have a transfer limit */ 2145 2146 if (temp.len > xfer->max_frame_size) 2147 temp.len = xfer->max_frame_size; 2148 2149 /* compute TD packet count */ 2150 tdpc = (temp.len + xfer->max_packet_size - 1) / 2151 xfer->max_packet_size; 2152 2153 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2154 temp.tlbpc = (tdpc % mult); 2155 2156 if (temp.tlbpc == 0) 2157 temp.tlbpc = mult - 1; 2158 else 2159 temp.tlbpc--; 2160 } else { 2161 2162 /* regular data transfer */ 2163 2164 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2165 } 2166 2167 xhci_setup_generic_chain_sub(&temp); 2168 2169 if (xfer->flags_int.isochronous_xfr) { 2170 temp.offset += xfer->frlengths[x - 1]; 2171 temp.isoc_frame += temp.isoc_delta; 2172 } else { 2173 /* get next Page Cache pointer */ 2174 temp.pc = xfer->frbuffers + x; 2175 } 2176 } 2177 2178 /* check if we should append a status stage */ 2179 2180 if (xfer->flags_int.control_xfr && 2181 !xfer->flags_int.control_act) { 2182 2183 /* 2184 * Send a DATA1 message and invert the current 2185 * endpoint direction. 2186 */ 2187 temp.step_td = (xfer->nframes != 0); 2188 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2189 temp.len = 0; 2190 temp.pc = NULL; 2191 temp.shortpkt = 0; 2192 temp.last_frame = 1; 2193 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2194 2195 xhci_setup_generic_chain_sub(&temp); 2196 } 2197 2198 td = temp.td; 2199 2200 /* must have at least one frame! */ 2201 2202 xfer->td_transfer_last = td; 2203 2204 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2205 } 2206 2207 static void 2208 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2209 { 2210 struct usb_page_search buf_res; 2211 struct xhci_dev_ctx_addr *pdctxa; 2212 2213 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2214 2215 pdctxa = buf_res.buffer; 2216 2217 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2218 2219 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2220 2221 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2222 } 2223 2224 static usb_error_t 2225 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2226 { 2227 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2228 struct usb_page_search buf_inp; 2229 struct xhci_input_dev_ctx *pinp; 2230 uint32_t temp; 2231 uint8_t index; 2232 uint8_t x; 2233 2234 index = udev->controller_slot_id; 2235 2236 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2237 2238 pinp = buf_inp.buffer; 2239 2240 if (drop) { 2241 mask &= XHCI_INCTX_NON_CTRL_MASK; 2242 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2243 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2244 } else { 2245 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2246 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2247 2248 /* find most significant set bit */ 2249 for (x = 31; x != 1; x--) { 2250 if (mask & (1 << x)) 2251 break; 2252 } 2253 2254 /* adjust */ 2255 x--; 2256 2257 /* figure out maximum */ 2258 if (x > sc->sc_hw.devs[index].context_num) { 2259 sc->sc_hw.devs[index].context_num = x; 2260 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2261 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2262 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2263 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2264 } 2265 } 2266 return (0); 2267 } 2268 2269 static usb_error_t 2270 xhci_configure_endpoint(struct usb_device *udev, 2271 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2272 uint16_t interval, uint8_t max_packet_count, 2273 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2274 uint16_t max_frame_size, uint8_t ep_mode) 2275 { 2276 struct usb_page_search buf_inp; 2277 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2278 struct xhci_input_dev_ctx *pinp; 2279 uint64_t ring_addr = pepext->physaddr; 2280 uint32_t temp; 2281 uint8_t index; 2282 uint8_t epno; 2283 uint8_t type; 2284 2285 index = udev->controller_slot_id; 2286 2287 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2288 2289 pinp = buf_inp.buffer; 2290 2291 epno = edesc->bEndpointAddress; 2292 type = edesc->bmAttributes & UE_XFERTYPE; 2293 2294 if (type == UE_CONTROL) 2295 epno |= UE_DIR_IN; 2296 2297 epno = XHCI_EPNO2EPID(epno); 2298 2299 if (epno == 0) 2300 return (USB_ERR_NO_PIPE); /* invalid */ 2301 2302 if (max_packet_count == 0) 2303 return (USB_ERR_BAD_BUFSIZE); 2304 2305 max_packet_count--; 2306 2307 if (mult == 0) 2308 return (USB_ERR_BAD_BUFSIZE); 2309 2310 /* store endpoint mode */ 2311 pepext->trb_ep_mode = ep_mode; 2312 usb_pc_cpu_flush(pepext->page_cache); 2313 2314 if (ep_mode == USB_EP_MODE_STREAMS) { 2315 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2316 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2317 XHCI_EPCTX_0_LSA_SET(1); 2318 2319 ring_addr += sizeof(struct xhci_trb) * 2320 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2321 } else { 2322 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2323 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2324 XHCI_EPCTX_0_LSA_SET(0); 2325 2326 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2327 } 2328 2329 switch (udev->speed) { 2330 case USB_SPEED_FULL: 2331 case USB_SPEED_LOW: 2332 /* 1ms -> 125us */ 2333 fps_shift += 3; 2334 break; 2335 default: 2336 break; 2337 } 2338 2339 switch (type) { 2340 case UE_INTERRUPT: 2341 if (fps_shift > 3) 2342 fps_shift--; 2343 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2344 break; 2345 case UE_ISOCHRONOUS: 2346 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2347 2348 switch (udev->speed) { 2349 case USB_SPEED_SUPER: 2350 if (mult > 3) 2351 mult = 3; 2352 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2353 max_packet_count /= mult; 2354 break; 2355 default: 2356 break; 2357 } 2358 break; 2359 default: 2360 break; 2361 } 2362 2363 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2364 2365 temp = 2366 XHCI_EPCTX_1_HID_SET(0) | 2367 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2368 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2369 2370 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2371 if (type != UE_ISOCHRONOUS) 2372 temp |= XHCI_EPCTX_1_CERR_SET(3); 2373 } 2374 2375 switch (type) { 2376 case UE_CONTROL: 2377 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2378 break; 2379 case UE_ISOCHRONOUS: 2380 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2381 break; 2382 case UE_BULK: 2383 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2384 break; 2385 default: 2386 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2387 break; 2388 } 2389 2390 /* check for IN direction */ 2391 if (epno & 1) 2392 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2393 2394 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2395 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2396 2397 switch (edesc->bmAttributes & UE_XFERTYPE) { 2398 case UE_INTERRUPT: 2399 case UE_ISOCHRONOUS: 2400 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2401 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2402 max_frame_size)); 2403 break; 2404 case UE_CONTROL: 2405 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2406 break; 2407 default: 2408 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2409 break; 2410 } 2411 2412 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2413 2414 #ifdef USB_DEBUG 2415 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2416 #endif 2417 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2418 2419 return (0); /* success */ 2420 } 2421 2422 static usb_error_t 2423 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2424 { 2425 struct xhci_endpoint_ext *pepext; 2426 struct usb_endpoint_ss_comp_descriptor *ecomp; 2427 usb_stream_t x; 2428 2429 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2430 xfer->endpoint->edesc); 2431 2432 ecomp = xfer->endpoint->ecomp; 2433 2434 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2435 uint64_t temp; 2436 2437 /* halt any transfers */ 2438 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2439 2440 /* compute start of TRB ring for stream "x" */ 2441 temp = pepext->physaddr + 2442 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2443 XHCI_SCTX_0_SCT_SEC_TR_RING; 2444 2445 /* make tree structure */ 2446 pepext->trb[(XHCI_MAX_TRANSFERS * 2447 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2448 2449 /* reserved fields */ 2450 pepext->trb[(XHCI_MAX_TRANSFERS * 2451 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2452 pepext->trb[(XHCI_MAX_TRANSFERS * 2453 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2454 } 2455 usb_pc_cpu_flush(pepext->page_cache); 2456 2457 return (xhci_configure_endpoint(xfer->xroot->udev, 2458 xfer->endpoint->edesc, pepext, 2459 xfer->interval, xfer->max_packet_count, 2460 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2461 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2462 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2463 } 2464 2465 static usb_error_t 2466 xhci_configure_device(struct usb_device *udev) 2467 { 2468 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2469 struct usb_page_search buf_inp; 2470 struct usb_page_cache *pcinp; 2471 struct xhci_input_dev_ctx *pinp; 2472 struct usb_device *hubdev; 2473 uint32_t temp; 2474 uint32_t route; 2475 uint32_t rh_port; 2476 uint8_t is_hub; 2477 uint8_t index; 2478 uint8_t depth; 2479 2480 index = udev->controller_slot_id; 2481 2482 DPRINTF("index=%u\n", index); 2483 2484 pcinp = &sc->sc_hw.devs[index].input_pc; 2485 2486 usbd_get_page(pcinp, 0, &buf_inp); 2487 2488 pinp = buf_inp.buffer; 2489 2490 rh_port = 0; 2491 route = 0; 2492 2493 /* figure out route string and root HUB port number */ 2494 2495 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2496 2497 if (hubdev->parent_hub == NULL) 2498 break; 2499 2500 depth = hubdev->parent_hub->depth; 2501 2502 /* 2503 * NOTE: HS/FS/LS devices and the SS root HUB can have 2504 * more than 15 ports 2505 */ 2506 2507 rh_port = hubdev->port_no; 2508 2509 if (depth == 0) 2510 break; 2511 2512 if (rh_port > 15) 2513 rh_port = 15; 2514 2515 if (depth < 6) 2516 route |= rh_port << (4 * (depth - 1)); 2517 } 2518 2519 DPRINTF("Route=0x%08x\n", route); 2520 2521 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2522 XHCI_SCTX_0_CTX_NUM_SET( 2523 sc->sc_hw.devs[index].context_num + 1); 2524 2525 switch (udev->speed) { 2526 case USB_SPEED_LOW: 2527 temp |= XHCI_SCTX_0_SPEED_SET(2); 2528 if (udev->parent_hs_hub != NULL && 2529 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2530 UDPROTO_HSHUBMTT) { 2531 DPRINTF("Device inherits MTT\n"); 2532 temp |= XHCI_SCTX_0_MTT_SET(1); 2533 } 2534 break; 2535 case USB_SPEED_HIGH: 2536 temp |= XHCI_SCTX_0_SPEED_SET(3); 2537 if (sc->sc_hw.devs[index].nports != 0 && 2538 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2539 DPRINTF("HUB supports MTT\n"); 2540 temp |= XHCI_SCTX_0_MTT_SET(1); 2541 } 2542 break; 2543 case USB_SPEED_FULL: 2544 temp |= XHCI_SCTX_0_SPEED_SET(1); 2545 if (udev->parent_hs_hub != NULL && 2546 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2547 UDPROTO_HSHUBMTT) { 2548 DPRINTF("Device inherits MTT\n"); 2549 temp |= XHCI_SCTX_0_MTT_SET(1); 2550 } 2551 break; 2552 default: 2553 temp |= XHCI_SCTX_0_SPEED_SET(4); 2554 break; 2555 } 2556 2557 is_hub = sc->sc_hw.devs[index].nports != 0 && 2558 (udev->speed == USB_SPEED_SUPER || 2559 udev->speed == USB_SPEED_HIGH); 2560 2561 if (is_hub) 2562 temp |= XHCI_SCTX_0_HUB_SET(1); 2563 2564 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2565 2566 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2567 2568 if (is_hub) { 2569 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2570 sc->sc_hw.devs[index].nports); 2571 } 2572 2573 switch (udev->speed) { 2574 case USB_SPEED_SUPER: 2575 switch (sc->sc_hw.devs[index].state) { 2576 case XHCI_ST_ADDRESSED: 2577 case XHCI_ST_CONFIGURED: 2578 /* enable power save */ 2579 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2580 break; 2581 default: 2582 /* disable power save */ 2583 break; 2584 } 2585 break; 2586 default: 2587 break; 2588 } 2589 2590 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2591 2592 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2593 2594 if (is_hub) { 2595 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2596 sc->sc_hw.devs[index].tt); 2597 } 2598 2599 hubdev = udev->parent_hs_hub; 2600 2601 /* check if we should activate the transaction translator */ 2602 switch (udev->speed) { 2603 case USB_SPEED_FULL: 2604 case USB_SPEED_LOW: 2605 if (hubdev != NULL) { 2606 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2607 hubdev->controller_slot_id); 2608 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2609 udev->hs_port_no); 2610 } 2611 break; 2612 default: 2613 break; 2614 } 2615 2616 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2617 2618 /* 2619 * These fields should be initialized to zero, according to 2620 * XHCI section 6.2.2 - slot context: 2621 */ 2622 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2623 XHCI_SCTX_3_SLOT_STATE_SET(0); 2624 2625 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2626 2627 #ifdef USB_DEBUG 2628 xhci_dump_device(sc, &pinp->ctx_slot); 2629 #endif 2630 usb_pc_cpu_flush(pcinp); 2631 2632 return (0); /* success */ 2633 } 2634 2635 static usb_error_t 2636 xhci_alloc_device_ext(struct usb_device *udev) 2637 { 2638 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2639 struct usb_page_search buf_dev; 2640 struct usb_page_search buf_ep; 2641 struct xhci_trb *trb; 2642 struct usb_page_cache *pc; 2643 struct usb_page *pg; 2644 uint64_t addr; 2645 uint8_t index; 2646 uint8_t i; 2647 2648 index = udev->controller_slot_id; 2649 2650 pc = &sc->sc_hw.devs[index].device_pc; 2651 pg = &sc->sc_hw.devs[index].device_pg; 2652 2653 /* need to initialize the page cache */ 2654 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2655 2656 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2657 (2 * sizeof(struct xhci_dev_ctx)) : 2658 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2659 goto error; 2660 2661 usbd_get_page(pc, 0, &buf_dev); 2662 2663 pc = &sc->sc_hw.devs[index].input_pc; 2664 pg = &sc->sc_hw.devs[index].input_pg; 2665 2666 /* need to initialize the page cache */ 2667 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2668 2669 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2670 (2 * sizeof(struct xhci_input_dev_ctx)) : 2671 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2672 goto error; 2673 } 2674 2675 pc = &sc->sc_hw.devs[index].endpoint_pc; 2676 pg = &sc->sc_hw.devs[index].endpoint_pg; 2677 2678 /* need to initialize the page cache */ 2679 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2680 2681 if (usb_pc_alloc_mem(pc, pg, 2682 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) { 2683 goto error; 2684 } 2685 2686 /* initialise all endpoint LINK TRBs */ 2687 2688 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2689 2690 /* lookup endpoint TRB ring */ 2691 usbd_get_page(pc, (uintptr_t)& 2692 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2693 2694 /* get TRB pointer */ 2695 trb = buf_ep.buffer; 2696 trb += XHCI_MAX_TRANSFERS - 1; 2697 2698 /* get TRB start address */ 2699 addr = buf_ep.physaddr; 2700 2701 /* create LINK TRB */ 2702 trb->qwTrb0 = htole64(addr); 2703 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2704 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2705 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2706 } 2707 2708 usb_pc_cpu_flush(pc); 2709 2710 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2711 2712 return (0); 2713 2714 error: 2715 xhci_free_device_ext(udev); 2716 2717 return (USB_ERR_NOMEM); 2718 } 2719 2720 static void 2721 xhci_free_device_ext(struct usb_device *udev) 2722 { 2723 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2724 uint8_t index; 2725 2726 index = udev->controller_slot_id; 2727 xhci_set_slot_pointer(sc, index, 0); 2728 2729 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2730 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2731 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2732 } 2733 2734 static struct xhci_endpoint_ext * 2735 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2736 { 2737 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2738 struct xhci_endpoint_ext *pepext; 2739 struct usb_page_cache *pc; 2740 struct usb_page_search buf_ep; 2741 uint8_t epno; 2742 uint8_t index; 2743 2744 epno = edesc->bEndpointAddress; 2745 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2746 epno |= UE_DIR_IN; 2747 2748 epno = XHCI_EPNO2EPID(epno); 2749 2750 index = udev->controller_slot_id; 2751 2752 pc = &sc->sc_hw.devs[index].endpoint_pc; 2753 2754 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2755 trb[epno][0], &buf_ep); 2756 2757 pepext = &sc->sc_hw.devs[index].endp[epno]; 2758 pepext->page_cache = pc; 2759 pepext->trb = buf_ep.buffer; 2760 pepext->physaddr = buf_ep.physaddr; 2761 2762 return (pepext); 2763 } 2764 2765 static void 2766 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2767 { 2768 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2769 uint8_t epno; 2770 uint8_t index; 2771 2772 epno = xfer->endpointno; 2773 if (xfer->flags_int.control_xfr) 2774 epno |= UE_DIR_IN; 2775 2776 epno = XHCI_EPNO2EPID(epno); 2777 index = xfer->xroot->udev->controller_slot_id; 2778 2779 if (xfer->xroot->udev->flags.self_suspended == 0) { 2780 XWRITE4(sc, door, XHCI_DOORBELL(index), 2781 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2782 } 2783 } 2784 2785 static void 2786 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2787 { 2788 struct xhci_endpoint_ext *pepext; 2789 2790 if (xfer->flags_int.bandwidth_reclaimed) { 2791 xfer->flags_int.bandwidth_reclaimed = 0; 2792 2793 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2794 xfer->endpoint->edesc); 2795 2796 pepext->trb_used[xfer->stream_id]--; 2797 2798 pepext->xfer[xfer->qh_pos] = NULL; 2799 2800 if (error && pepext->trb_running != 0) { 2801 pepext->trb_halted = 1; 2802 pepext->trb_running = 0; 2803 } 2804 } 2805 } 2806 2807 static usb_error_t 2808 xhci_transfer_insert(struct usb_xfer *xfer) 2809 { 2810 struct xhci_td *td_first; 2811 struct xhci_td *td_last; 2812 struct xhci_trb *trb_link; 2813 struct xhci_endpoint_ext *pepext; 2814 uint64_t addr; 2815 usb_stream_t id; 2816 uint8_t i; 2817 uint8_t inext; 2818 uint8_t trb_limit; 2819 2820 DPRINTFN(8, "\n"); 2821 2822 id = xfer->stream_id; 2823 2824 /* check if already inserted */ 2825 if (xfer->flags_int.bandwidth_reclaimed) { 2826 DPRINTFN(8, "Already in schedule\n"); 2827 return (0); 2828 } 2829 2830 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2831 xfer->endpoint->edesc); 2832 2833 td_first = xfer->td_transfer_first; 2834 td_last = xfer->td_transfer_last; 2835 addr = pepext->physaddr; 2836 2837 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2838 case UE_CONTROL: 2839 case UE_INTERRUPT: 2840 /* single buffered */ 2841 trb_limit = 1; 2842 break; 2843 default: 2844 /* multi buffered */ 2845 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2846 break; 2847 } 2848 2849 if (pepext->trb_used[id] >= trb_limit) { 2850 DPRINTFN(8, "Too many TDs queued.\n"); 2851 return (USB_ERR_NOMEM); 2852 } 2853 2854 /* check for stopped condition, after putting transfer on interrupt queue */ 2855 if (pepext->trb_running == 0) { 2856 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2857 2858 DPRINTFN(8, "Not running\n"); 2859 2860 /* start configuration */ 2861 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2862 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2863 return (0); 2864 } 2865 2866 pepext->trb_used[id]++; 2867 2868 /* get current TRB index */ 2869 i = pepext->trb_index[id]; 2870 2871 /* get next TRB index */ 2872 inext = (i + 1); 2873 2874 /* the last entry of the ring is a hardcoded link TRB */ 2875 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2876 inext = 0; 2877 2878 /* store next TRB index, before stream ID offset is added */ 2879 pepext->trb_index[id] = inext; 2880 2881 /* offset for stream */ 2882 i += id * XHCI_MAX_TRANSFERS; 2883 inext += id * XHCI_MAX_TRANSFERS; 2884 2885 /* compute terminating return address */ 2886 addr += (inext * sizeof(struct xhci_trb)); 2887 2888 /* compute link TRB pointer */ 2889 trb_link = td_last->td_trb + td_last->ntrb; 2890 2891 /* update next pointer of last link TRB */ 2892 trb_link->qwTrb0 = htole64(addr); 2893 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2894 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2895 XHCI_TRB_3_CYCLE_BIT | 2896 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2897 2898 #ifdef USB_DEBUG 2899 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2900 #endif 2901 usb_pc_cpu_flush(td_last->page_cache); 2902 2903 /* write ahead chain end marker */ 2904 2905 pepext->trb[inext].qwTrb0 = 0; 2906 pepext->trb[inext].dwTrb2 = 0; 2907 pepext->trb[inext].dwTrb3 = 0; 2908 2909 /* update next pointer of link TRB */ 2910 2911 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2912 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2913 2914 #ifdef USB_DEBUG 2915 xhci_dump_trb(&pepext->trb[i]); 2916 #endif 2917 usb_pc_cpu_flush(pepext->page_cache); 2918 2919 /* toggle cycle bit which activates the transfer chain */ 2920 2921 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2922 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2923 2924 usb_pc_cpu_flush(pepext->page_cache); 2925 2926 DPRINTF("qh_pos = %u\n", i); 2927 2928 pepext->xfer[i] = xfer; 2929 2930 xfer->qh_pos = i; 2931 2932 xfer->flags_int.bandwidth_reclaimed = 1; 2933 2934 xhci_endpoint_doorbell(xfer); 2935 2936 return (0); 2937 } 2938 2939 static void 2940 xhci_root_intr(struct xhci_softc *sc) 2941 { 2942 uint16_t i; 2943 2944 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2945 2946 /* clear any old interrupt data */ 2947 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2948 2949 for (i = 1; i <= sc->sc_noport; i++) { 2950 /* pick out CHANGE bits from the status register */ 2951 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2952 XHCI_PS_CSC | XHCI_PS_PEC | 2953 XHCI_PS_OCC | XHCI_PS_WRC | 2954 XHCI_PS_PRC | XHCI_PS_PLC | 2955 XHCI_PS_CEC)) { 2956 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2957 DPRINTF("port %d changed\n", i); 2958 } 2959 } 2960 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2961 sizeof(sc->sc_hub_idata)); 2962 } 2963 2964 /*------------------------------------------------------------------------* 2965 * xhci_device_done - XHCI done handler 2966 * 2967 * NOTE: This function can be called two times in a row on 2968 * the same USB transfer. From close and from interrupt. 2969 *------------------------------------------------------------------------*/ 2970 static void 2971 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2972 { 2973 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2974 xfer, xfer->endpoint, error); 2975 2976 /* remove transfer from HW queue */ 2977 xhci_transfer_remove(xfer, error); 2978 2979 /* dequeue transfer and start next transfer */ 2980 usbd_transfer_done(xfer, error); 2981 } 2982 2983 /*------------------------------------------------------------------------* 2984 * XHCI data transfer support (generic type) 2985 *------------------------------------------------------------------------*/ 2986 static void 2987 xhci_device_generic_open(struct usb_xfer *xfer) 2988 { 2989 if (xfer->flags_int.isochronous_xfr) { 2990 switch (xfer->xroot->udev->speed) { 2991 case USB_SPEED_FULL: 2992 break; 2993 default: 2994 usb_hs_bandwidth_alloc(xfer); 2995 break; 2996 } 2997 } 2998 } 2999 3000 static void 3001 xhci_device_generic_close(struct usb_xfer *xfer) 3002 { 3003 DPRINTF("\n"); 3004 3005 xhci_device_done(xfer, USB_ERR_CANCELLED); 3006 3007 if (xfer->flags_int.isochronous_xfr) { 3008 switch (xfer->xroot->udev->speed) { 3009 case USB_SPEED_FULL: 3010 break; 3011 default: 3012 usb_hs_bandwidth_free(xfer); 3013 break; 3014 } 3015 } 3016 } 3017 3018 static void 3019 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3020 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3021 { 3022 struct usb_xfer *xfer; 3023 3024 /* check if there is a current transfer */ 3025 xfer = ep->endpoint_q[stream_id].curr; 3026 if (xfer == NULL) 3027 return; 3028 3029 /* 3030 * Check if the current transfer is started and then pickup 3031 * the next one, if any. Else wait for next start event due to 3032 * block on failure feature. 3033 */ 3034 if (!xfer->flags_int.bandwidth_reclaimed) 3035 return; 3036 3037 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3038 if (xfer == NULL) { 3039 /* 3040 * In case of enter we have to consider that the 3041 * transfer is queued by the USB core after the enter 3042 * method is called. 3043 */ 3044 xfer = enter_xfer; 3045 3046 if (xfer == NULL) 3047 return; 3048 } 3049 3050 /* try to multi buffer */ 3051 xhci_transfer_insert(xfer); 3052 } 3053 3054 static void 3055 xhci_device_generic_enter(struct usb_xfer *xfer) 3056 { 3057 DPRINTF("\n"); 3058 3059 /* setup TD's and QH */ 3060 xhci_setup_generic_chain(xfer); 3061 3062 xhci_device_generic_multi_enter(xfer->endpoint, 3063 xfer->stream_id, xfer); 3064 } 3065 3066 static void 3067 xhci_device_generic_start(struct usb_xfer *xfer) 3068 { 3069 DPRINTF("\n"); 3070 3071 /* try to insert xfer on HW queue */ 3072 xhci_transfer_insert(xfer); 3073 3074 /* try to multi buffer */ 3075 xhci_device_generic_multi_enter(xfer->endpoint, 3076 xfer->stream_id, NULL); 3077 3078 /* add transfer last on interrupt queue */ 3079 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3080 3081 /* start timeout, if any */ 3082 if (xfer->timeout != 0) 3083 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3084 } 3085 3086 static const struct usb_pipe_methods xhci_device_generic_methods = 3087 { 3088 .open = xhci_device_generic_open, 3089 .close = xhci_device_generic_close, 3090 .enter = xhci_device_generic_enter, 3091 .start = xhci_device_generic_start, 3092 }; 3093 3094 /*------------------------------------------------------------------------* 3095 * xhci root HUB support 3096 *------------------------------------------------------------------------* 3097 * Simulate a hardware HUB by handling all the necessary requests. 3098 *------------------------------------------------------------------------*/ 3099 3100 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3101 3102 static const 3103 struct usb_device_descriptor xhci_devd = 3104 { 3105 .bLength = sizeof(xhci_devd), 3106 .bDescriptorType = UDESC_DEVICE, /* type */ 3107 HSETW(.bcdUSB, 0x0300), /* USB version */ 3108 .bDeviceClass = UDCLASS_HUB, /* class */ 3109 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3110 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3111 .bMaxPacketSize = 9, /* max packet size */ 3112 HSETW(.idVendor, 0x0000), /* vendor */ 3113 HSETW(.idProduct, 0x0000), /* product */ 3114 HSETW(.bcdDevice, 0x0100), /* device version */ 3115 .iManufacturer = 1, 3116 .iProduct = 2, 3117 .iSerialNumber = 0, 3118 .bNumConfigurations = 1, /* # of configurations */ 3119 }; 3120 3121 static const 3122 struct xhci_bos_desc xhci_bosd = { 3123 .bosd = { 3124 .bLength = sizeof(xhci_bosd.bosd), 3125 .bDescriptorType = UDESC_BOS, 3126 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3127 .bNumDeviceCaps = 3, 3128 }, 3129 .usb2extd = { 3130 .bLength = sizeof(xhci_bosd.usb2extd), 3131 .bDescriptorType = 1, 3132 .bDevCapabilityType = 2, 3133 .bmAttributes[0] = 2, 3134 }, 3135 .usbdcd = { 3136 .bLength = sizeof(xhci_bosd.usbdcd), 3137 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3138 .bDevCapabilityType = 3, 3139 .bmAttributes = 0, /* XXX */ 3140 HSETW(.wSpeedsSupported, 0x000C), 3141 .bFunctionalitySupport = 8, 3142 .bU1DevExitLat = 255, /* dummy - not used */ 3143 .wU2DevExitLat = { 0x00, 0x08 }, 3144 }, 3145 .cidd = { 3146 .bLength = sizeof(xhci_bosd.cidd), 3147 .bDescriptorType = 1, 3148 .bDevCapabilityType = 4, 3149 .bReserved = 0, 3150 .bContainerID = 0, /* XXX */ 3151 }, 3152 }; 3153 3154 static const 3155 struct xhci_config_desc xhci_confd = { 3156 .confd = { 3157 .bLength = sizeof(xhci_confd.confd), 3158 .bDescriptorType = UDESC_CONFIG, 3159 .wTotalLength[0] = sizeof(xhci_confd), 3160 .bNumInterface = 1, 3161 .bConfigurationValue = 1, 3162 .iConfiguration = 0, 3163 .bmAttributes = UC_SELF_POWERED, 3164 .bMaxPower = 0 /* max power */ 3165 }, 3166 .ifcd = { 3167 .bLength = sizeof(xhci_confd.ifcd), 3168 .bDescriptorType = UDESC_INTERFACE, 3169 .bNumEndpoints = 1, 3170 .bInterfaceClass = UICLASS_HUB, 3171 .bInterfaceSubClass = UISUBCLASS_HUB, 3172 .bInterfaceProtocol = 0, 3173 }, 3174 .endpd = { 3175 .bLength = sizeof(xhci_confd.endpd), 3176 .bDescriptorType = UDESC_ENDPOINT, 3177 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3178 .bmAttributes = UE_INTERRUPT, 3179 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3180 .bInterval = 255, 3181 }, 3182 .endpcd = { 3183 .bLength = sizeof(xhci_confd.endpcd), 3184 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3185 .bMaxBurst = 0, 3186 .bmAttributes = 0, 3187 }, 3188 }; 3189 3190 static const 3191 struct usb_hub_ss_descriptor xhci_hubd = { 3192 .bLength = sizeof(xhci_hubd), 3193 .bDescriptorType = UDESC_SS_HUB, 3194 }; 3195 3196 static usb_error_t 3197 xhci_roothub_exec(struct usb_device *udev, 3198 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3199 { 3200 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3201 const char *str_ptr; 3202 const void *ptr; 3203 uint32_t port; 3204 uint32_t v; 3205 uint16_t len; 3206 uint16_t i; 3207 uint16_t value; 3208 uint16_t index; 3209 uint8_t j; 3210 usb_error_t err; 3211 3212 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3213 3214 /* buffer reset */ 3215 ptr = (const void *)&sc->sc_hub_desc; 3216 len = 0; 3217 err = 0; 3218 3219 value = UGETW(req->wValue); 3220 index = UGETW(req->wIndex); 3221 3222 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3223 "wValue=0x%04x wIndex=0x%04x\n", 3224 req->bmRequestType, req->bRequest, 3225 UGETW(req->wLength), value, index); 3226 3227 #define C(x,y) ((x) | ((y) << 8)) 3228 switch (C(req->bRequest, req->bmRequestType)) { 3229 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3230 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3231 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3232 /* 3233 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3234 * for the integrated root hub. 3235 */ 3236 break; 3237 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3238 len = 1; 3239 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3240 break; 3241 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3242 switch (value >> 8) { 3243 case UDESC_DEVICE: 3244 if ((value & 0xff) != 0) { 3245 err = USB_ERR_IOERROR; 3246 goto done; 3247 } 3248 len = sizeof(xhci_devd); 3249 ptr = (const void *)&xhci_devd; 3250 break; 3251 3252 case UDESC_BOS: 3253 if ((value & 0xff) != 0) { 3254 err = USB_ERR_IOERROR; 3255 goto done; 3256 } 3257 len = sizeof(xhci_bosd); 3258 ptr = (const void *)&xhci_bosd; 3259 break; 3260 3261 case UDESC_CONFIG: 3262 if ((value & 0xff) != 0) { 3263 err = USB_ERR_IOERROR; 3264 goto done; 3265 } 3266 len = sizeof(xhci_confd); 3267 ptr = (const void *)&xhci_confd; 3268 break; 3269 3270 case UDESC_STRING: 3271 switch (value & 0xff) { 3272 case 0: /* Language table */ 3273 str_ptr = "\001"; 3274 break; 3275 3276 case 1: /* Vendor */ 3277 str_ptr = sc->sc_vendor; 3278 break; 3279 3280 case 2: /* Product */ 3281 str_ptr = "XHCI root HUB"; 3282 break; 3283 3284 default: 3285 str_ptr = ""; 3286 break; 3287 } 3288 3289 len = usb_make_str_desc( 3290 sc->sc_hub_desc.temp, 3291 sizeof(sc->sc_hub_desc.temp), 3292 str_ptr); 3293 break; 3294 3295 default: 3296 err = USB_ERR_IOERROR; 3297 goto done; 3298 } 3299 break; 3300 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3301 len = 1; 3302 sc->sc_hub_desc.temp[0] = 0; 3303 break; 3304 case C(UR_GET_STATUS, UT_READ_DEVICE): 3305 len = 2; 3306 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3307 break; 3308 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3309 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3310 len = 2; 3311 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3312 break; 3313 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3314 if (value >= XHCI_MAX_DEVICES) { 3315 err = USB_ERR_IOERROR; 3316 goto done; 3317 } 3318 break; 3319 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3320 if (value != 0 && value != 1) { 3321 err = USB_ERR_IOERROR; 3322 goto done; 3323 } 3324 sc->sc_conf = value; 3325 break; 3326 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3327 break; 3328 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3329 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3330 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3331 err = USB_ERR_IOERROR; 3332 goto done; 3333 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3334 break; 3335 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3336 break; 3337 /* Hub requests */ 3338 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3339 break; 3340 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3341 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3342 3343 if ((index < 1) || 3344 (index > sc->sc_noport)) { 3345 err = USB_ERR_IOERROR; 3346 goto done; 3347 } 3348 port = XHCI_PORTSC(index); 3349 3350 v = XREAD4(sc, oper, port); 3351 i = XHCI_PS_PLS_GET(v); 3352 v &= ~XHCI_PS_CLEAR; 3353 3354 switch (value) { 3355 case UHF_C_BH_PORT_RESET: 3356 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3357 break; 3358 case UHF_C_PORT_CONFIG_ERROR: 3359 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3360 break; 3361 case UHF_C_PORT_SUSPEND: 3362 case UHF_C_PORT_LINK_STATE: 3363 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3364 break; 3365 case UHF_C_PORT_CONNECTION: 3366 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3367 break; 3368 case UHF_C_PORT_ENABLE: 3369 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3370 break; 3371 case UHF_C_PORT_OVER_CURRENT: 3372 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3373 break; 3374 case UHF_C_PORT_RESET: 3375 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3376 break; 3377 case UHF_PORT_ENABLE: 3378 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3379 break; 3380 case UHF_PORT_POWER: 3381 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3382 break; 3383 case UHF_PORT_INDICATOR: 3384 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3385 break; 3386 case UHF_PORT_SUSPEND: 3387 3388 /* U3 -> U15 */ 3389 if (i == 3) { 3390 XWRITE4(sc, oper, port, v | 3391 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3392 } 3393 3394 /* wait 20ms for resume sequence to complete */ 3395 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3396 3397 /* U0 */ 3398 XWRITE4(sc, oper, port, v | 3399 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3400 break; 3401 default: 3402 err = USB_ERR_IOERROR; 3403 goto done; 3404 } 3405 break; 3406 3407 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3408 if ((value & 0xff) != 0) { 3409 err = USB_ERR_IOERROR; 3410 goto done; 3411 } 3412 3413 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3414 3415 sc->sc_hub_desc.hubd = xhci_hubd; 3416 3417 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3418 3419 if (XHCI_HCS0_PPC(v)) 3420 i = UHD_PWR_INDIVIDUAL; 3421 else 3422 i = UHD_PWR_GANGED; 3423 3424 if (XHCI_HCS0_PIND(v)) 3425 i |= UHD_PORT_IND; 3426 3427 i |= UHD_OC_INDIVIDUAL; 3428 3429 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3430 3431 /* see XHCI section 5.4.9: */ 3432 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3433 3434 for (j = 1; j <= sc->sc_noport; j++) { 3435 3436 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3437 if (v & XHCI_PS_DR) { 3438 sc->sc_hub_desc.hubd. 3439 DeviceRemovable[j / 8] |= 1U << (j % 8); 3440 } 3441 } 3442 len = sc->sc_hub_desc.hubd.bLength; 3443 break; 3444 3445 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3446 len = 16; 3447 memset(sc->sc_hub_desc.temp, 0, 16); 3448 break; 3449 3450 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3451 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3452 3453 if ((index < 1) || 3454 (index > sc->sc_noport)) { 3455 err = USB_ERR_IOERROR; 3456 goto done; 3457 } 3458 3459 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3460 3461 DPRINTFN(9, "port status=0x%08x\n", v); 3462 3463 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3464 3465 switch (XHCI_PS_SPEED_GET(v)) { 3466 case 3: 3467 i |= UPS_HIGH_SPEED; 3468 break; 3469 case 2: 3470 i |= UPS_LOW_SPEED; 3471 break; 3472 case 1: 3473 /* FULL speed */ 3474 break; 3475 default: 3476 i |= UPS_OTHER_SPEED; 3477 break; 3478 } 3479 3480 if (v & XHCI_PS_CCS) 3481 i |= UPS_CURRENT_CONNECT_STATUS; 3482 if (v & XHCI_PS_PED) 3483 i |= UPS_PORT_ENABLED; 3484 if (v & XHCI_PS_OCA) 3485 i |= UPS_OVERCURRENT_INDICATOR; 3486 if (v & XHCI_PS_PR) 3487 i |= UPS_RESET; 3488 if (v & XHCI_PS_PP) { 3489 /* 3490 * The USB 3.0 RH is using the 3491 * USB 2.0's power bit 3492 */ 3493 i |= UPS_PORT_POWER; 3494 } 3495 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3496 3497 i = 0; 3498 if (v & XHCI_PS_CSC) 3499 i |= UPS_C_CONNECT_STATUS; 3500 if (v & XHCI_PS_PEC) 3501 i |= UPS_C_PORT_ENABLED; 3502 if (v & XHCI_PS_OCC) 3503 i |= UPS_C_OVERCURRENT_INDICATOR; 3504 if (v & XHCI_PS_WRC) 3505 i |= UPS_C_BH_PORT_RESET; 3506 if (v & XHCI_PS_PRC) 3507 i |= UPS_C_PORT_RESET; 3508 if (v & XHCI_PS_PLC) 3509 i |= UPS_C_PORT_LINK_STATE; 3510 if (v & XHCI_PS_CEC) 3511 i |= UPS_C_PORT_CONFIG_ERROR; 3512 3513 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3514 len = sizeof(sc->sc_hub_desc.ps); 3515 break; 3516 3517 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3518 err = USB_ERR_IOERROR; 3519 goto done; 3520 3521 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3522 break; 3523 3524 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3525 3526 i = index >> 8; 3527 index &= 0x00FF; 3528 3529 if ((index < 1) || 3530 (index > sc->sc_noport)) { 3531 err = USB_ERR_IOERROR; 3532 goto done; 3533 } 3534 3535 port = XHCI_PORTSC(index); 3536 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3537 3538 switch (value) { 3539 case UHF_PORT_U1_TIMEOUT: 3540 if (XHCI_PS_SPEED_GET(v) != 4) { 3541 err = USB_ERR_IOERROR; 3542 goto done; 3543 } 3544 port = XHCI_PORTPMSC(index); 3545 v = XREAD4(sc, oper, port); 3546 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3547 v |= XHCI_PM3_U1TO_SET(i); 3548 XWRITE4(sc, oper, port, v); 3549 break; 3550 case UHF_PORT_U2_TIMEOUT: 3551 if (XHCI_PS_SPEED_GET(v) != 4) { 3552 err = USB_ERR_IOERROR; 3553 goto done; 3554 } 3555 port = XHCI_PORTPMSC(index); 3556 v = XREAD4(sc, oper, port); 3557 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3558 v |= XHCI_PM3_U2TO_SET(i); 3559 XWRITE4(sc, oper, port, v); 3560 break; 3561 case UHF_BH_PORT_RESET: 3562 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3563 break; 3564 case UHF_PORT_LINK_STATE: 3565 XWRITE4(sc, oper, port, v | 3566 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3567 /* 4ms settle time */ 3568 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3569 break; 3570 case UHF_PORT_ENABLE: 3571 DPRINTFN(3, "set port enable %d\n", index); 3572 break; 3573 case UHF_PORT_SUSPEND: 3574 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3575 j = XHCI_PS_SPEED_GET(v); 3576 if ((j < 1) || (j > 3)) { 3577 /* non-supported speed */ 3578 err = USB_ERR_IOERROR; 3579 goto done; 3580 } 3581 XWRITE4(sc, oper, port, v | 3582 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3583 break; 3584 case UHF_PORT_RESET: 3585 DPRINTFN(6, "reset port %d\n", index); 3586 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3587 break; 3588 case UHF_PORT_POWER: 3589 DPRINTFN(3, "set port power %d\n", index); 3590 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3591 break; 3592 case UHF_PORT_TEST: 3593 DPRINTFN(3, "set port test %d\n", index); 3594 break; 3595 case UHF_PORT_INDICATOR: 3596 DPRINTFN(3, "set port indicator %d\n", index); 3597 3598 v &= ~XHCI_PS_PIC_SET(3); 3599 v |= XHCI_PS_PIC_SET(1); 3600 3601 XWRITE4(sc, oper, port, v); 3602 break; 3603 default: 3604 err = USB_ERR_IOERROR; 3605 goto done; 3606 } 3607 break; 3608 3609 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3610 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3611 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3612 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3613 break; 3614 default: 3615 err = USB_ERR_IOERROR; 3616 goto done; 3617 } 3618 done: 3619 *plength = len; 3620 *pptr = ptr; 3621 return (err); 3622 } 3623 3624 static void 3625 xhci_xfer_setup(struct usb_setup_params *parm) 3626 { 3627 struct usb_page_search page_info; 3628 struct usb_page_cache *pc; 3629 struct xhci_softc *sc; 3630 struct usb_xfer *xfer; 3631 void *last_obj; 3632 uint32_t ntd; 3633 uint32_t n; 3634 3635 sc = XHCI_BUS2SC(parm->udev->bus); 3636 xfer = parm->curr_xfer; 3637 3638 /* 3639 * The proof for the "ntd" formula is illustrated like this: 3640 * 3641 * +------------------------------------+ 3642 * | | 3643 * | |remainder -> | 3644 * | +-----+---+ | 3645 * | | xxx | x | frm 0 | 3646 * | +-----+---++ | 3647 * | | xxx | xx | frm 1 | 3648 * | +-----+----+ | 3649 * | ... | 3650 * +------------------------------------+ 3651 * 3652 * "xxx" means a completely full USB transfer descriptor 3653 * 3654 * "x" and "xx" means a short USB packet 3655 * 3656 * For the remainder of an USB transfer modulo 3657 * "max_data_length" we need two USB transfer descriptors. 3658 * One to transfer the remaining data and one to finalise with 3659 * a zero length packet in case the "force_short_xfer" flag is 3660 * set. We only need two USB transfer descriptors in the case 3661 * where the transfer length of the first one is a factor of 3662 * "max_frame_size". The rest of the needed USB transfer 3663 * descriptors is given by the buffer size divided by the 3664 * maximum data payload. 3665 */ 3666 parm->hc_max_packet_size = 0x400; 3667 parm->hc_max_packet_count = 16 * 3; 3668 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3669 3670 xfer->flags_int.bdma_enable = 1; 3671 3672 usbd_transfer_setup_sub(parm); 3673 3674 if (xfer->flags_int.isochronous_xfr) { 3675 ntd = ((1 * xfer->nframes) 3676 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3677 } else if (xfer->flags_int.control_xfr) { 3678 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3679 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3680 } else { 3681 ntd = ((2 * xfer->nframes) 3682 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3683 } 3684 3685 alloc_dma_set: 3686 3687 if (parm->err) 3688 return; 3689 3690 /* 3691 * Allocate queue heads and transfer descriptors 3692 */ 3693 last_obj = NULL; 3694 3695 if (usbd_transfer_setup_sub_malloc( 3696 parm, &pc, sizeof(struct xhci_td), 3697 XHCI_TD_ALIGN, ntd)) { 3698 parm->err = USB_ERR_NOMEM; 3699 return; 3700 } 3701 if (parm->buf) { 3702 for (n = 0; n != ntd; n++) { 3703 struct xhci_td *td; 3704 3705 usbd_get_page(pc + n, 0, &page_info); 3706 3707 td = page_info.buffer; 3708 3709 /* init TD */ 3710 td->td_self = page_info.physaddr; 3711 td->obj_next = last_obj; 3712 td->page_cache = pc + n; 3713 3714 last_obj = td; 3715 3716 usb_pc_cpu_flush(pc + n); 3717 } 3718 } 3719 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3720 3721 if (!xfer->flags_int.curr_dma_set) { 3722 xfer->flags_int.curr_dma_set = 1; 3723 goto alloc_dma_set; 3724 } 3725 } 3726 3727 static usb_error_t 3728 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3729 { 3730 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3731 struct usb_page_search buf_inp; 3732 struct usb_device *udev; 3733 struct xhci_endpoint_ext *pepext; 3734 struct usb_endpoint_descriptor *edesc; 3735 struct usb_page_cache *pcinp; 3736 usb_error_t err; 3737 usb_stream_t stream_id; 3738 uint8_t index; 3739 uint8_t epno; 3740 3741 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3742 xfer->endpoint->edesc); 3743 3744 udev = xfer->xroot->udev; 3745 index = udev->controller_slot_id; 3746 3747 pcinp = &sc->sc_hw.devs[index].input_pc; 3748 3749 usbd_get_page(pcinp, 0, &buf_inp); 3750 3751 edesc = xfer->endpoint->edesc; 3752 3753 epno = edesc->bEndpointAddress; 3754 stream_id = xfer->stream_id; 3755 3756 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3757 epno |= UE_DIR_IN; 3758 3759 epno = XHCI_EPNO2EPID(epno); 3760 3761 if (epno == 0) 3762 return (USB_ERR_NO_PIPE); /* invalid */ 3763 3764 XHCI_CMD_LOCK(sc); 3765 3766 /* configure endpoint */ 3767 3768 err = xhci_configure_endpoint_by_xfer(xfer); 3769 3770 if (err != 0) { 3771 XHCI_CMD_UNLOCK(sc); 3772 return (err); 3773 } 3774 3775 /* 3776 * Get the endpoint into the stopped state according to the 3777 * endpoint context state diagram in the XHCI specification: 3778 */ 3779 3780 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3781 3782 if (err != 0) 3783 DPRINTF("Could not stop endpoint %u\n", epno); 3784 3785 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3786 3787 if (err != 0) 3788 DPRINTF("Could not reset endpoint %u\n", epno); 3789 3790 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3791 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3792 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3793 stream_id, epno, index); 3794 3795 if (err != 0) 3796 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3797 3798 /* 3799 * Get the endpoint into the running state according to the 3800 * endpoint context state diagram in the XHCI specification: 3801 */ 3802 3803 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3804 3805 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3806 3807 if (err != 0) 3808 DPRINTF("Could not configure endpoint %u\n", epno); 3809 3810 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3811 3812 if (err != 0) 3813 DPRINTF("Could not configure endpoint %u\n", epno); 3814 3815 XHCI_CMD_UNLOCK(sc); 3816 3817 return (0); 3818 } 3819 3820 static void 3821 xhci_xfer_unsetup(struct usb_xfer *xfer) 3822 { 3823 return; 3824 } 3825 3826 static void 3827 xhci_start_dma_delay(struct usb_xfer *xfer) 3828 { 3829 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3830 3831 /* put transfer on interrupt queue (again) */ 3832 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3833 3834 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3835 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3836 } 3837 3838 static void 3839 xhci_configure_msg(struct usb_proc_msg *pm) 3840 { 3841 struct xhci_softc *sc; 3842 struct xhci_endpoint_ext *pepext; 3843 struct usb_xfer *xfer; 3844 3845 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3846 3847 restart: 3848 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3849 3850 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3851 xfer->endpoint->edesc); 3852 3853 if ((pepext->trb_halted != 0) || 3854 (pepext->trb_running == 0)) { 3855 3856 uint16_t i; 3857 3858 /* clear halted and running */ 3859 pepext->trb_halted = 0; 3860 pepext->trb_running = 0; 3861 3862 /* nuke remaining buffered transfers */ 3863 3864 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3865 XHCI_MAX_STREAMS); i++) { 3866 /* 3867 * NOTE: We need to use the timeout 3868 * error code here else existing 3869 * isochronous clients can get 3870 * confused: 3871 */ 3872 if (pepext->xfer[i] != NULL) { 3873 xhci_device_done(pepext->xfer[i], 3874 USB_ERR_TIMEOUT); 3875 } 3876 } 3877 3878 /* 3879 * NOTE: The USB transfer cannot vanish in 3880 * this state! 3881 */ 3882 3883 USB_BUS_UNLOCK(&sc->sc_bus); 3884 3885 xhci_configure_reset_endpoint(xfer); 3886 3887 USB_BUS_LOCK(&sc->sc_bus); 3888 3889 /* check if halted is still cleared */ 3890 if (pepext->trb_halted == 0) { 3891 pepext->trb_running = 1; 3892 memset(pepext->trb_index, 0, 3893 sizeof(pepext->trb_index)); 3894 } 3895 goto restart; 3896 } 3897 3898 if (xfer->flags_int.did_dma_delay) { 3899 3900 /* remove transfer from interrupt queue (again) */ 3901 usbd_transfer_dequeue(xfer); 3902 3903 /* we are finally done */ 3904 usb_dma_delay_done_cb(xfer); 3905 3906 /* queue changed - restart */ 3907 goto restart; 3908 } 3909 } 3910 3911 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3912 3913 /* try to insert xfer on HW queue */ 3914 xhci_transfer_insert(xfer); 3915 3916 /* try to multi buffer */ 3917 xhci_device_generic_multi_enter(xfer->endpoint, 3918 xfer->stream_id, NULL); 3919 } 3920 } 3921 3922 static void 3923 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3924 struct usb_endpoint *ep) 3925 { 3926 struct xhci_endpoint_ext *pepext; 3927 3928 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3929 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3930 3931 if (udev->parent_hub == NULL) { 3932 /* root HUB has special endpoint handling */ 3933 return; 3934 } 3935 3936 ep->methods = &xhci_device_generic_methods; 3937 3938 pepext = xhci_get_endpoint_ext(udev, edesc); 3939 3940 USB_BUS_LOCK(udev->bus); 3941 pepext->trb_halted = 1; 3942 pepext->trb_running = 0; 3943 USB_BUS_UNLOCK(udev->bus); 3944 } 3945 3946 static void 3947 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3948 { 3949 3950 } 3951 3952 static void 3953 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3954 { 3955 struct xhci_endpoint_ext *pepext; 3956 3957 DPRINTF("\n"); 3958 3959 if (udev->flags.usb_mode != USB_MODE_HOST) { 3960 /* not supported */ 3961 return; 3962 } 3963 if (udev->parent_hub == NULL) { 3964 /* root HUB has special endpoint handling */ 3965 return; 3966 } 3967 3968 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3969 3970 USB_BUS_LOCK(udev->bus); 3971 pepext->trb_halted = 1; 3972 pepext->trb_running = 0; 3973 USB_BUS_UNLOCK(udev->bus); 3974 } 3975 3976 static usb_error_t 3977 xhci_device_init(struct usb_device *udev) 3978 { 3979 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3980 usb_error_t err; 3981 uint8_t temp; 3982 3983 /* no init for root HUB */ 3984 if (udev->parent_hub == NULL) 3985 return (0); 3986 3987 XHCI_CMD_LOCK(sc); 3988 3989 /* set invalid default */ 3990 3991 udev->controller_slot_id = sc->sc_noslot + 1; 3992 3993 /* try to get a new slot ID from the XHCI */ 3994 3995 err = xhci_cmd_enable_slot(sc, &temp); 3996 3997 if (err) { 3998 XHCI_CMD_UNLOCK(sc); 3999 return (err); 4000 } 4001 4002 if (temp > sc->sc_noslot) { 4003 XHCI_CMD_UNLOCK(sc); 4004 return (USB_ERR_BAD_ADDRESS); 4005 } 4006 4007 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4008 DPRINTF("slot %u already allocated.\n", temp); 4009 XHCI_CMD_UNLOCK(sc); 4010 return (USB_ERR_BAD_ADDRESS); 4011 } 4012 4013 /* store slot ID for later reference */ 4014 4015 udev->controller_slot_id = temp; 4016 4017 /* reset data structure */ 4018 4019 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4020 4021 /* set mark slot allocated */ 4022 4023 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4024 4025 err = xhci_alloc_device_ext(udev); 4026 4027 XHCI_CMD_UNLOCK(sc); 4028 4029 /* get device into default state */ 4030 4031 if (err == 0) 4032 err = xhci_set_address(udev, NULL, 0); 4033 4034 return (err); 4035 } 4036 4037 static void 4038 xhci_device_uninit(struct usb_device *udev) 4039 { 4040 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4041 uint8_t index; 4042 4043 /* no init for root HUB */ 4044 if (udev->parent_hub == NULL) 4045 return; 4046 4047 XHCI_CMD_LOCK(sc); 4048 4049 index = udev->controller_slot_id; 4050 4051 if (index <= sc->sc_noslot) { 4052 xhci_cmd_disable_slot(sc, index); 4053 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4054 4055 /* free device extension */ 4056 xhci_free_device_ext(udev); 4057 } 4058 4059 XHCI_CMD_UNLOCK(sc); 4060 } 4061 4062 static void 4063 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4064 { 4065 /* 4066 * Wait until the hardware has finished any possible use of 4067 * the transfer descriptor(s) 4068 */ 4069 *pus = 2048; /* microseconds */ 4070 } 4071 4072 static void 4073 xhci_device_resume(struct usb_device *udev) 4074 { 4075 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4076 uint8_t index; 4077 uint8_t n; 4078 uint8_t p; 4079 4080 DPRINTF("\n"); 4081 4082 /* check for root HUB */ 4083 if (udev->parent_hub == NULL) 4084 return; 4085 4086 index = udev->controller_slot_id; 4087 4088 XHCI_CMD_LOCK(sc); 4089 4090 /* blindly resume all endpoints */ 4091 4092 USB_BUS_LOCK(udev->bus); 4093 4094 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4095 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4096 XWRITE4(sc, door, XHCI_DOORBELL(index), 4097 n | XHCI_DB_SID_SET(p)); 4098 } 4099 } 4100 4101 USB_BUS_UNLOCK(udev->bus); 4102 4103 XHCI_CMD_UNLOCK(sc); 4104 } 4105 4106 static void 4107 xhci_device_suspend(struct usb_device *udev) 4108 { 4109 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4110 uint8_t index; 4111 uint8_t n; 4112 usb_error_t err; 4113 4114 DPRINTF("\n"); 4115 4116 /* check for root HUB */ 4117 if (udev->parent_hub == NULL) 4118 return; 4119 4120 index = udev->controller_slot_id; 4121 4122 XHCI_CMD_LOCK(sc); 4123 4124 /* blindly suspend all endpoints */ 4125 4126 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4127 err = xhci_cmd_stop_ep(sc, 1, n, index); 4128 if (err != 0) { 4129 DPRINTF("Failed to suspend endpoint " 4130 "%u on slot %u (ignored).\n", n, index); 4131 } 4132 } 4133 4134 XHCI_CMD_UNLOCK(sc); 4135 } 4136 4137 static void 4138 xhci_set_hw_power(struct usb_bus *bus) 4139 { 4140 DPRINTF("\n"); 4141 } 4142 4143 static void 4144 xhci_device_state_change(struct usb_device *udev) 4145 { 4146 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4147 struct usb_page_search buf_inp; 4148 usb_error_t err; 4149 uint8_t index; 4150 4151 /* check for root HUB */ 4152 if (udev->parent_hub == NULL) 4153 return; 4154 4155 index = udev->controller_slot_id; 4156 4157 DPRINTF("\n"); 4158 4159 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4160 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4161 &sc->sc_hw.devs[index].tt); 4162 if (err != 0) 4163 sc->sc_hw.devs[index].nports = 0; 4164 } 4165 4166 XHCI_CMD_LOCK(sc); 4167 4168 switch (usb_get_device_state(udev)) { 4169 case USB_STATE_POWERED: 4170 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4171 break; 4172 4173 /* set default state */ 4174 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4175 4176 /* reset number of contexts */ 4177 sc->sc_hw.devs[index].context_num = 0; 4178 4179 err = xhci_cmd_reset_dev(sc, index); 4180 4181 if (err != 0) { 4182 DPRINTF("Device reset failed " 4183 "for slot %u.\n", index); 4184 } 4185 break; 4186 4187 case USB_STATE_ADDRESSED: 4188 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4189 break; 4190 4191 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4192 4193 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4194 4195 if (err) { 4196 DPRINTF("Failed to deconfigure " 4197 "slot %u.\n", index); 4198 } 4199 break; 4200 4201 case USB_STATE_CONFIGURED: 4202 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4203 break; 4204 4205 /* set configured state */ 4206 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4207 4208 /* reset number of contexts */ 4209 sc->sc_hw.devs[index].context_num = 0; 4210 4211 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4212 4213 xhci_configure_mask(udev, 3, 0); 4214 4215 err = xhci_configure_device(udev); 4216 if (err != 0) { 4217 DPRINTF("Could not configure device " 4218 "at slot %u.\n", index); 4219 } 4220 4221 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4222 if (err != 0) { 4223 DPRINTF("Could not evaluate device " 4224 "context at slot %u.\n", index); 4225 } 4226 break; 4227 4228 default: 4229 break; 4230 } 4231 XHCI_CMD_UNLOCK(sc); 4232 } 4233 4234 static usb_error_t 4235 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4236 uint8_t ep_mode) 4237 { 4238 switch (ep_mode) { 4239 case USB_EP_MODE_DEFAULT: 4240 return (0); 4241 case USB_EP_MODE_STREAMS: 4242 if (xhcistreams == 0 || 4243 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4244 udev->speed != USB_SPEED_SUPER) 4245 return (USB_ERR_INVAL); 4246 return (0); 4247 default: 4248 return (USB_ERR_INVAL); 4249 } 4250 } 4251 4252 static const struct usb_bus_methods xhci_bus_methods = { 4253 .endpoint_init = xhci_ep_init, 4254 .endpoint_uninit = xhci_ep_uninit, 4255 .xfer_setup = xhci_xfer_setup, 4256 .xfer_unsetup = xhci_xfer_unsetup, 4257 .get_dma_delay = xhci_get_dma_delay, 4258 .device_init = xhci_device_init, 4259 .device_uninit = xhci_device_uninit, 4260 .device_resume = xhci_device_resume, 4261 .device_suspend = xhci_device_suspend, 4262 .set_hw_power = xhci_set_hw_power, 4263 .roothub_exec = xhci_roothub_exec, 4264 .xfer_poll = xhci_do_poll, 4265 .start_dma_delay = xhci_start_dma_delay, 4266 .set_address = xhci_set_address, 4267 .clear_stall = xhci_ep_clear_stall, 4268 .device_state_change = xhci_device_state_change, 4269 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4270 .set_endpoint_mode = xhci_set_endpoint_mode, 4271 }; 4272