1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 28 * 29 * The XHCI 1.0 spec can be found at 30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 31 * and the USB 3.0 spec at 32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 33 */ 34 35 /* 36 * A few words about the design implementation: This driver emulates 37 * the concept about TDs which is found in EHCI specification. This 38 * way we avoid too much diveration among USB drivers. 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/stdint.h> 45 #include <sys/stddef.h> 46 #include <sys/param.h> 47 #include <sys/queue.h> 48 #include <sys/types.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/bus.h> 52 #include <sys/module.h> 53 #include <sys/lock.h> 54 #include <sys/mutex.h> 55 #include <sys/condvar.h> 56 #include <sys/sysctl.h> 57 #include <sys/sx.h> 58 #include <sys/unistd.h> 59 #include <sys/callout.h> 60 #include <sys/malloc.h> 61 #include <sys/priv.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 66 #define USB_DEBUG_VAR xhcidebug 67 68 #include <dev/usb/usb_core.h> 69 #include <dev/usb/usb_debug.h> 70 #include <dev/usb/usb_busdma.h> 71 #include <dev/usb/usb_process.h> 72 #include <dev/usb/usb_transfer.h> 73 #include <dev/usb/usb_device.h> 74 #include <dev/usb/usb_hub.h> 75 #include <dev/usb/usb_util.h> 76 77 #include <dev/usb/usb_controller.h> 78 #include <dev/usb/usb_bus.h> 79 #include <dev/usb/controller/xhci.h> 80 #include <dev/usb/controller/xhcireg.h> 81 82 #define XHCI_BUS2SC(bus) \ 83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 85 86 #ifdef USB_DEBUG 87 static int xhcidebug; 88 static int xhciroute; 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW, 92 &xhcidebug, 0, "Debug level"); 93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW, 94 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 95 96 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 97 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 98 #endif 99 100 #define XHCI_INTR_ENDPT 1 101 102 struct xhci_std_temp { 103 struct xhci_softc *sc; 104 struct usb_page_cache *pc; 105 struct xhci_td *td; 106 struct xhci_td *td_next; 107 uint32_t len; 108 uint32_t offset; 109 uint32_t max_packet_size; 110 uint32_t average; 111 uint16_t isoc_delta; 112 uint16_t isoc_frame; 113 uint8_t shortpkt; 114 uint8_t multishort; 115 uint8_t last_frame; 116 uint8_t trb_type; 117 uint8_t direction; 118 uint8_t tbc; 119 uint8_t tlbpc; 120 uint8_t step_td; 121 uint8_t do_isoc_sync; 122 }; 123 124 static void xhci_do_poll(struct usb_bus *); 125 static void xhci_device_done(struct usb_xfer *, usb_error_t); 126 static void xhci_root_intr(struct xhci_softc *); 127 static void xhci_free_device_ext(struct usb_device *); 128 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 129 struct usb_endpoint_descriptor *); 130 static usb_proc_callback_t xhci_configure_msg; 131 static usb_error_t xhci_configure_device(struct usb_device *); 132 static usb_error_t xhci_configure_endpoint(struct usb_device *, 133 struct usb_endpoint_descriptor *, uint64_t, uint16_t, 134 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, uint8_t); 135 static usb_error_t xhci_configure_mask(struct usb_device *, 136 uint32_t, uint8_t); 137 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 138 uint64_t, uint8_t); 139 static void xhci_endpoint_doorbell(struct usb_xfer *); 140 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 141 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 142 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 143 #ifdef USB_DEBUG 144 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 145 #endif 146 147 extern struct usb_bus_methods xhci_bus_methods; 148 149 #ifdef USB_DEBUG 150 static void 151 xhci_dump_trb(struct xhci_trb *trb) 152 { 153 DPRINTFN(5, "trb = %p\n", trb); 154 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 155 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 156 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 157 } 158 159 static void 160 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 161 { 162 DPRINTFN(5, "pep = %p\n", pep); 163 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 164 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 165 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 166 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 167 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 168 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 169 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 170 } 171 172 static void 173 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 174 { 175 DPRINTFN(5, "psl = %p\n", psl); 176 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 177 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 178 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 179 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 180 } 181 #endif 182 183 uint32_t 184 xhci_get_port_route(void) 185 { 186 #ifdef USB_DEBUG 187 return (0xFFFFFFFFU ^ ((uint32_t)xhciroute)); 188 #else 189 return (0xFFFFFFFFU); 190 #endif 191 } 192 193 static void 194 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 195 { 196 struct xhci_softc *sc = XHCI_BUS2SC(bus); 197 uint8_t i; 198 199 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 200 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 201 202 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 203 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 204 205 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 206 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 207 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 208 } 209 } 210 211 static void 212 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 213 { 214 if (sc->sc_ctx_is_64_byte) { 215 uint32_t offset; 216 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 217 /* all contexts are initially 32-bytes */ 218 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 219 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 220 } 221 *ptr = htole32(val); 222 } 223 224 static uint32_t 225 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 226 { 227 if (sc->sc_ctx_is_64_byte) { 228 uint32_t offset; 229 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 230 /* all contexts are initially 32-bytes */ 231 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 232 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 233 } 234 return (le32toh(*ptr)); 235 } 236 237 static void 238 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 239 { 240 if (sc->sc_ctx_is_64_byte) { 241 uint32_t offset; 242 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 243 /* all contexts are initially 32-bytes */ 244 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 245 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 246 } 247 *ptr = htole64(val); 248 } 249 250 #ifdef USB_DEBUG 251 static uint64_t 252 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 253 { 254 if (sc->sc_ctx_is_64_byte) { 255 uint32_t offset; 256 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 257 /* all contexts are initially 32-bytes */ 258 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 259 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 260 } 261 return (le64toh(*ptr)); 262 } 263 #endif 264 265 usb_error_t 266 xhci_start_controller(struct xhci_softc *sc) 267 { 268 struct usb_page_search buf_res; 269 struct xhci_hw_root *phwr; 270 struct xhci_dev_ctx_addr *pdctxa; 271 uint64_t addr; 272 uint32_t temp; 273 uint16_t i; 274 275 DPRINTF("\n"); 276 277 sc->sc_capa_off = 0; 278 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 279 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 280 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 281 282 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 283 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 284 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 285 286 sc->sc_event_ccs = 1; 287 sc->sc_event_idx = 0; 288 sc->sc_command_ccs = 1; 289 sc->sc_command_idx = 0; 290 291 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 292 293 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 294 295 DPRINTF("HCS0 = 0x%08x\n", temp); 296 297 if (XHCI_HCS0_CSZ(temp)) { 298 sc->sc_ctx_is_64_byte = 1; 299 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 300 } else { 301 sc->sc_ctx_is_64_byte = 0; 302 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 303 } 304 305 /* Reset controller */ 306 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 307 308 for (i = 0; i != 100; i++) { 309 usb_pause_mtx(NULL, hz / 100); 310 temp = XREAD4(sc, oper, XHCI_USBCMD) & 311 (XHCI_CMD_HCRST | XHCI_STS_CNR); 312 if (!temp) 313 break; 314 } 315 316 if (temp) { 317 device_printf(sc->sc_bus.parent, "Controller " 318 "reset timeout.\n"); 319 return (USB_ERR_IOERROR); 320 } 321 322 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 323 device_printf(sc->sc_bus.parent, "Controller does " 324 "not support 4K page size.\n"); 325 return (USB_ERR_IOERROR); 326 } 327 328 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 329 330 i = XHCI_HCS1_N_PORTS(temp); 331 332 if (i == 0) { 333 device_printf(sc->sc_bus.parent, "Invalid number " 334 "of ports: %u\n", i); 335 return (USB_ERR_IOERROR); 336 } 337 338 sc->sc_noport = i; 339 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 340 341 if (sc->sc_noslot > XHCI_MAX_DEVICES) 342 sc->sc_noslot = XHCI_MAX_DEVICES; 343 344 /* setup number of device slots */ 345 346 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 347 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 348 349 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 350 351 DPRINTF("Max slots: %u\n", sc->sc_noslot); 352 353 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 354 355 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 356 357 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 358 device_printf(sc->sc_bus.parent, "XHCI request " 359 "too many scratchpads\n"); 360 return (USB_ERR_NOMEM); 361 } 362 363 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 364 365 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 366 367 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 368 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 369 370 temp = XREAD4(sc, oper, XHCI_USBSTS); 371 372 /* clear interrupts */ 373 XWRITE4(sc, oper, XHCI_USBSTS, temp); 374 /* disable all device notifications */ 375 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 376 377 /* setup device context base address */ 378 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 379 pdctxa = buf_res.buffer; 380 memset(pdctxa, 0, sizeof(*pdctxa)); 381 382 addr = buf_res.physaddr; 383 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 384 385 /* slot 0 points to the table of scratchpad pointers */ 386 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 387 388 for (i = 0; i != sc->sc_noscratch; i++) { 389 struct usb_page_search buf_scp; 390 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 391 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 392 } 393 394 addr = buf_res.physaddr; 395 396 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 397 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 398 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 399 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 400 401 /* Setup event table size */ 402 403 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 404 405 DPRINTF("HCS2=0x%08x\n", temp); 406 407 temp = XHCI_HCS2_ERST_MAX(temp); 408 temp = 1U << temp; 409 if (temp > XHCI_MAX_RSEG) 410 temp = XHCI_MAX_RSEG; 411 412 sc->sc_erst_max = temp; 413 414 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 415 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 416 417 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 418 419 /* Setup interrupt rate */ 420 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 421 422 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 423 424 phwr = buf_res.buffer; 425 addr = buf_res.physaddr; 426 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 427 428 /* reset hardware root structure */ 429 memset(phwr, 0, sizeof(*phwr)); 430 431 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 432 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 433 434 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 435 436 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 437 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 438 439 addr = (uint64_t)buf_res.physaddr; 440 441 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 442 443 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 444 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 445 446 /* Setup interrupter registers */ 447 448 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 449 temp |= XHCI_IMAN_INTR_ENA; 450 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 451 452 /* setup command ring control base address */ 453 addr = buf_res.physaddr; 454 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 455 456 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 457 458 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 459 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 460 461 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 462 463 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 464 465 /* Go! */ 466 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 467 XHCI_CMD_INTE | XHCI_CMD_HSEE); 468 469 for (i = 0; i != 100; i++) { 470 usb_pause_mtx(NULL, hz / 100); 471 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 472 if (!temp) 473 break; 474 } 475 if (temp) { 476 XWRITE4(sc, oper, XHCI_USBCMD, 0); 477 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 478 return (USB_ERR_IOERROR); 479 } 480 481 /* catch any lost interrupts */ 482 xhci_do_poll(&sc->sc_bus); 483 484 return (0); 485 } 486 487 usb_error_t 488 xhci_halt_controller(struct xhci_softc *sc) 489 { 490 uint32_t temp; 491 uint16_t i; 492 493 DPRINTF("\n"); 494 495 sc->sc_capa_off = 0; 496 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 497 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 498 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 499 500 /* Halt controller */ 501 XWRITE4(sc, oper, XHCI_USBCMD, 0); 502 503 for (i = 0; i != 100; i++) { 504 usb_pause_mtx(NULL, hz / 100); 505 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 506 if (temp) 507 break; 508 } 509 510 if (!temp) { 511 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 512 return (USB_ERR_IOERROR); 513 } 514 return (0); 515 } 516 517 usb_error_t 518 xhci_init(struct xhci_softc *sc, device_t self) 519 { 520 /* initialise some bus fields */ 521 sc->sc_bus.parent = self; 522 523 /* set the bus revision */ 524 sc->sc_bus.usbrev = USB_REV_3_0; 525 526 /* set up the bus struct */ 527 sc->sc_bus.methods = &xhci_bus_methods; 528 529 /* setup devices array */ 530 sc->sc_bus.devices = sc->sc_devices; 531 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 532 533 /* setup command queue mutex and condition varible */ 534 cv_init(&sc->sc_cmd_cv, "CMDQ"); 535 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 536 537 /* get all DMA memory */ 538 if (usb_bus_mem_alloc_all(&sc->sc_bus, 539 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 540 return (ENOMEM); 541 } 542 543 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 544 sc->sc_config_msg[0].bus = &sc->sc_bus; 545 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 546 sc->sc_config_msg[1].bus = &sc->sc_bus; 547 548 if (usb_proc_create(&sc->sc_config_proc, 549 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) { 550 printf("WARNING: Creation of XHCI configure " 551 "callback process failed.\n"); 552 } 553 return (0); 554 } 555 556 void 557 xhci_uninit(struct xhci_softc *sc) 558 { 559 usb_proc_free(&sc->sc_config_proc); 560 561 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 562 563 cv_destroy(&sc->sc_cmd_cv); 564 sx_destroy(&sc->sc_cmd_sx); 565 } 566 567 static void 568 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 569 { 570 struct xhci_softc *sc = XHCI_BUS2SC(bus); 571 572 switch (state) { 573 case USB_HW_POWER_SUSPEND: 574 DPRINTF("Stopping the XHCI\n"); 575 xhci_halt_controller(sc); 576 break; 577 case USB_HW_POWER_SHUTDOWN: 578 DPRINTF("Stopping the XHCI\n"); 579 xhci_halt_controller(sc); 580 break; 581 case USB_HW_POWER_RESUME: 582 DPRINTF("Starting the XHCI\n"); 583 xhci_start_controller(sc); 584 break; 585 default: 586 break; 587 } 588 } 589 590 static usb_error_t 591 xhci_generic_done_sub(struct usb_xfer *xfer) 592 { 593 struct xhci_td *td; 594 struct xhci_td *td_alt_next; 595 uint32_t len; 596 uint8_t status; 597 598 td = xfer->td_transfer_cache; 599 td_alt_next = td->alt_next; 600 601 if (xfer->aframes != xfer->nframes) 602 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 603 604 while (1) { 605 606 usb_pc_cpu_invalidate(td->page_cache); 607 608 status = td->status; 609 len = td->remainder; 610 611 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 612 xfer, (unsigned int)xfer->aframes, 613 (unsigned int)xfer->nframes, 614 (unsigned int)len, (unsigned int)td->len, 615 (unsigned int)status); 616 617 /* 618 * Verify the status length and 619 * add the length to "frlengths[]": 620 */ 621 if (len > td->len) { 622 /* should not happen */ 623 DPRINTF("Invalid status length, " 624 "0x%04x/0x%04x bytes\n", len, td->len); 625 status = XHCI_TRB_ERROR_LENGTH; 626 } else if (xfer->aframes != xfer->nframes) { 627 xfer->frlengths[xfer->aframes] += td->len - len; 628 } 629 /* Check for last transfer */ 630 if (((void *)td) == xfer->td_transfer_last) { 631 td = NULL; 632 break; 633 } 634 /* Check for transfer error */ 635 if (status != XHCI_TRB_ERROR_SHORT_PKT && 636 status != XHCI_TRB_ERROR_SUCCESS) { 637 /* the transfer is finished */ 638 td = NULL; 639 break; 640 } 641 /* Check for short transfer */ 642 if (len > 0) { 643 if (xfer->flags_int.short_frames_ok || 644 xfer->flags_int.isochronous_xfr || 645 xfer->flags_int.control_xfr) { 646 /* follow alt next */ 647 td = td->alt_next; 648 } else { 649 /* the transfer is finished */ 650 td = NULL; 651 } 652 break; 653 } 654 td = td->obj_next; 655 656 if (td->alt_next != td_alt_next) { 657 /* this USB frame is complete */ 658 break; 659 } 660 } 661 662 /* update transfer cache */ 663 664 xfer->td_transfer_cache = td; 665 666 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 667 (status != XHCI_TRB_ERROR_SHORT_PKT && 668 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 669 USB_ERR_NORMAL_COMPLETION); 670 } 671 672 static void 673 xhci_generic_done(struct usb_xfer *xfer) 674 { 675 usb_error_t err = 0; 676 677 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 678 xfer, xfer->endpoint); 679 680 /* reset scanner */ 681 682 xfer->td_transfer_cache = xfer->td_transfer_first; 683 684 if (xfer->flags_int.control_xfr) { 685 686 if (xfer->flags_int.control_hdr) 687 err = xhci_generic_done_sub(xfer); 688 689 xfer->aframes = 1; 690 691 if (xfer->td_transfer_cache == NULL) 692 goto done; 693 } 694 695 while (xfer->aframes != xfer->nframes) { 696 697 err = xhci_generic_done_sub(xfer); 698 xfer->aframes++; 699 700 if (xfer->td_transfer_cache == NULL) 701 goto done; 702 } 703 704 if (xfer->flags_int.control_xfr && 705 !xfer->flags_int.control_act) 706 err = xhci_generic_done_sub(xfer); 707 done: 708 /* transfer is complete */ 709 xhci_device_done(xfer, err); 710 } 711 712 static void 713 xhci_activate_transfer(struct usb_xfer *xfer) 714 { 715 struct xhci_td *td; 716 717 td = xfer->td_transfer_cache; 718 719 usb_pc_cpu_invalidate(td->page_cache); 720 721 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 722 723 /* activate the transfer */ 724 725 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 726 usb_pc_cpu_flush(td->page_cache); 727 728 xhci_endpoint_doorbell(xfer); 729 } 730 } 731 732 static void 733 xhci_skip_transfer(struct usb_xfer *xfer) 734 { 735 struct xhci_td *td; 736 struct xhci_td *td_last; 737 738 td = xfer->td_transfer_cache; 739 td_last = xfer->td_transfer_last; 740 741 td = td->alt_next; 742 743 usb_pc_cpu_invalidate(td->page_cache); 744 745 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 746 747 usb_pc_cpu_invalidate(td_last->page_cache); 748 749 /* copy LINK TRB to current waiting location */ 750 751 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 752 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 753 usb_pc_cpu_flush(td->page_cache); 754 755 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 756 usb_pc_cpu_flush(td->page_cache); 757 758 xhci_endpoint_doorbell(xfer); 759 } 760 } 761 762 /*------------------------------------------------------------------------* 763 * xhci_check_transfer 764 *------------------------------------------------------------------------*/ 765 static void 766 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 767 { 768 int64_t offset; 769 uint64_t td_event; 770 uint32_t temp; 771 uint32_t remainder; 772 uint8_t status; 773 uint8_t halted; 774 uint8_t epno; 775 uint8_t index; 776 uint8_t i; 777 778 /* decode TRB */ 779 td_event = le64toh(trb->qwTrb0); 780 temp = le32toh(trb->dwTrb2); 781 782 remainder = XHCI_TRB_2_REM_GET(temp); 783 status = XHCI_TRB_2_ERROR_GET(temp); 784 785 temp = le32toh(trb->dwTrb3); 786 epno = XHCI_TRB_3_EP_GET(temp); 787 index = XHCI_TRB_3_SLOT_GET(temp); 788 789 /* check if error means halted */ 790 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 791 status != XHCI_TRB_ERROR_SUCCESS); 792 793 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 794 index, epno, remainder, status); 795 796 if (index > sc->sc_noslot) { 797 DPRINTF("Invalid slot.\n"); 798 return; 799 } 800 801 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 802 DPRINTF("Invalid endpoint.\n"); 803 return; 804 } 805 806 /* try to find the USB transfer that generated the event */ 807 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 808 struct usb_xfer *xfer; 809 struct xhci_td *td; 810 struct xhci_endpoint_ext *pepext; 811 812 pepext = &sc->sc_hw.devs[index].endp[epno]; 813 814 xfer = pepext->xfer[i]; 815 if (xfer == NULL) 816 continue; 817 818 td = xfer->td_transfer_cache; 819 820 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 821 (long long)td_event, 822 (long long)td->td_self, 823 (long long)td->td_self + sizeof(td->td_trb)); 824 825 /* 826 * NOTE: Some XHCI implementations might not trigger 827 * an event on the last LINK TRB so we need to 828 * consider both the last and second last event 829 * address as conditions for a successful transfer. 830 * 831 * NOTE: We assume that the XHCI will only trigger one 832 * event per chain of TRBs. 833 */ 834 835 offset = td_event - td->td_self; 836 837 if (offset >= 0 && 838 offset < (int64_t)sizeof(td->td_trb)) { 839 840 usb_pc_cpu_invalidate(td->page_cache); 841 842 /* compute rest of remainder, if any */ 843 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 844 temp = le32toh(td->td_trb[i].dwTrb2); 845 remainder += XHCI_TRB_2_BYTES_GET(temp); 846 } 847 848 DPRINTFN(5, "New remainder: %u\n", remainder); 849 850 /* clear isochronous transfer errors */ 851 if (xfer->flags_int.isochronous_xfr) { 852 if (halted) { 853 halted = 0; 854 status = XHCI_TRB_ERROR_SUCCESS; 855 remainder = td->len; 856 } 857 } 858 859 /* "td->remainder" is verified later */ 860 td->remainder = remainder; 861 td->status = status; 862 863 usb_pc_cpu_flush(td->page_cache); 864 865 /* 866 * 1) Last transfer descriptor makes the 867 * transfer done 868 */ 869 if (((void *)td) == xfer->td_transfer_last) { 870 DPRINTF("TD is last\n"); 871 xhci_generic_done(xfer); 872 break; 873 } 874 875 /* 876 * 2) Any kind of error makes the transfer 877 * done 878 */ 879 if (halted) { 880 DPRINTF("TD has I/O error\n"); 881 xhci_generic_done(xfer); 882 break; 883 } 884 885 /* 886 * 3) If there is no alternate next transfer, 887 * a short packet also makes the transfer done 888 */ 889 if (td->remainder > 0) { 890 DPRINTF("TD has short pkt\n"); 891 if (xfer->flags_int.short_frames_ok || 892 xfer->flags_int.isochronous_xfr || 893 xfer->flags_int.control_xfr) { 894 /* follow the alt next */ 895 xfer->td_transfer_cache = td->alt_next; 896 xhci_activate_transfer(xfer); 897 break; 898 } 899 xhci_skip_transfer(xfer); 900 xhci_generic_done(xfer); 901 break; 902 } 903 904 /* 905 * 4) Transfer complete - go to next TD 906 */ 907 DPRINTF("Following next TD\n"); 908 xfer->td_transfer_cache = td->obj_next; 909 xhci_activate_transfer(xfer); 910 break; /* there should only be one match */ 911 } 912 } 913 } 914 915 static void 916 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 917 { 918 if (sc->sc_cmd_addr == trb->qwTrb0) { 919 DPRINTF("Received command event\n"); 920 sc->sc_cmd_result[0] = trb->dwTrb2; 921 sc->sc_cmd_result[1] = trb->dwTrb3; 922 cv_signal(&sc->sc_cmd_cv); 923 } 924 } 925 926 static void 927 xhci_interrupt_poll(struct xhci_softc *sc) 928 { 929 struct usb_page_search buf_res; 930 struct xhci_hw_root *phwr; 931 uint64_t addr; 932 uint32_t temp; 933 uint16_t i; 934 uint8_t event; 935 uint8_t j; 936 uint8_t k; 937 uint8_t t; 938 939 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 940 941 phwr = buf_res.buffer; 942 943 /* Receive any events */ 944 945 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 946 947 i = sc->sc_event_idx; 948 j = sc->sc_event_ccs; 949 t = 2; 950 951 while (1) { 952 953 temp = le32toh(phwr->hwr_events[i].dwTrb3); 954 955 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 956 957 if (j != k) 958 break; 959 960 event = XHCI_TRB_3_TYPE_GET(temp); 961 962 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 963 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 964 (long)le32toh(phwr->hwr_events[i].dwTrb2), 965 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 966 967 switch (event) { 968 case XHCI_TRB_EVENT_TRANSFER: 969 xhci_check_transfer(sc, &phwr->hwr_events[i]); 970 break; 971 case XHCI_TRB_EVENT_CMD_COMPLETE: 972 xhci_check_command(sc, &phwr->hwr_events[i]); 973 break; 974 default: 975 DPRINTF("Unhandled event = %u\n", event); 976 break; 977 } 978 979 i++; 980 981 if (i == XHCI_MAX_EVENTS) { 982 i = 0; 983 j ^= 1; 984 985 /* check for timeout */ 986 if (!--t) 987 break; 988 } 989 } 990 991 sc->sc_event_idx = i; 992 sc->sc_event_ccs = j; 993 994 /* 995 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 996 * latched. That means to activate the register we need to 997 * write both the low and high double word of the 64-bit 998 * register. 999 */ 1000 1001 addr = (uint32_t)buf_res.physaddr; 1002 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1003 1004 /* try to clear busy bit */ 1005 addr |= XHCI_ERDP_LO_BUSY; 1006 1007 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1008 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1009 } 1010 1011 static usb_error_t 1012 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1013 uint16_t timeout_ms) 1014 { 1015 struct usb_page_search buf_res; 1016 struct xhci_hw_root *phwr; 1017 uint64_t addr; 1018 uint32_t temp; 1019 uint8_t i; 1020 uint8_t j; 1021 int err; 1022 1023 XHCI_CMD_ASSERT_LOCKED(sc); 1024 1025 /* get hardware root structure */ 1026 1027 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1028 1029 phwr = buf_res.buffer; 1030 1031 /* Queue command */ 1032 1033 USB_BUS_LOCK(&sc->sc_bus); 1034 1035 i = sc->sc_command_idx; 1036 j = sc->sc_command_ccs; 1037 1038 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1039 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1040 (long long)le64toh(trb->qwTrb0), 1041 (long)le32toh(trb->dwTrb2), 1042 (long)le32toh(trb->dwTrb3)); 1043 1044 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1045 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1046 1047 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1048 1049 temp = trb->dwTrb3; 1050 1051 if (j) 1052 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1053 else 1054 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1055 1056 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1057 1058 phwr->hwr_commands[i].dwTrb3 = temp; 1059 1060 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1061 1062 addr = buf_res.physaddr; 1063 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1064 1065 sc->sc_cmd_addr = htole64(addr); 1066 1067 i++; 1068 1069 if (i == (XHCI_MAX_COMMANDS - 1)) { 1070 1071 if (j) { 1072 temp = htole32(XHCI_TRB_3_TC_BIT | 1073 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1074 XHCI_TRB_3_CYCLE_BIT); 1075 } else { 1076 temp = htole32(XHCI_TRB_3_TC_BIT | 1077 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1078 } 1079 1080 phwr->hwr_commands[i].dwTrb3 = temp; 1081 1082 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1083 1084 i = 0; 1085 j ^= 1; 1086 } 1087 1088 sc->sc_command_idx = i; 1089 sc->sc_command_ccs = j; 1090 1091 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1092 1093 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1094 USB_MS_TO_TICKS(timeout_ms)); 1095 1096 if (err) { 1097 DPRINTFN(0, "Command timeout!\n"); 1098 err = USB_ERR_TIMEOUT; 1099 trb->dwTrb2 = 0; 1100 trb->dwTrb3 = 0; 1101 } else { 1102 temp = le32toh(sc->sc_cmd_result[0]); 1103 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1104 err = USB_ERR_IOERROR; 1105 1106 trb->dwTrb2 = sc->sc_cmd_result[0]; 1107 trb->dwTrb3 = sc->sc_cmd_result[1]; 1108 } 1109 1110 USB_BUS_UNLOCK(&sc->sc_bus); 1111 1112 return (err); 1113 } 1114 1115 #if 0 1116 static usb_error_t 1117 xhci_cmd_nop(struct xhci_softc *sc) 1118 { 1119 struct xhci_trb trb; 1120 uint32_t temp; 1121 1122 DPRINTF("\n"); 1123 1124 trb.qwTrb0 = 0; 1125 trb.dwTrb2 = 0; 1126 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1127 1128 trb.dwTrb3 = htole32(temp); 1129 1130 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1131 } 1132 #endif 1133 1134 static usb_error_t 1135 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1136 { 1137 struct xhci_trb trb; 1138 uint32_t temp; 1139 usb_error_t err; 1140 1141 DPRINTF("\n"); 1142 1143 trb.qwTrb0 = 0; 1144 trb.dwTrb2 = 0; 1145 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1146 1147 err = xhci_do_command(sc, &trb, 100 /* ms */); 1148 if (err) 1149 goto done; 1150 1151 temp = le32toh(trb.dwTrb3); 1152 1153 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1154 1155 done: 1156 return (err); 1157 } 1158 1159 static usb_error_t 1160 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1161 { 1162 struct xhci_trb trb; 1163 uint32_t temp; 1164 1165 DPRINTF("\n"); 1166 1167 trb.qwTrb0 = 0; 1168 trb.dwTrb2 = 0; 1169 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1170 XHCI_TRB_3_SLOT_SET(slot_id); 1171 1172 trb.dwTrb3 = htole32(temp); 1173 1174 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1175 } 1176 1177 static usb_error_t 1178 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1179 uint8_t bsr, uint8_t slot_id) 1180 { 1181 struct xhci_trb trb; 1182 uint32_t temp; 1183 1184 DPRINTF("\n"); 1185 1186 trb.qwTrb0 = htole64(input_ctx); 1187 trb.dwTrb2 = 0; 1188 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1189 XHCI_TRB_3_SLOT_SET(slot_id); 1190 1191 if (bsr) 1192 temp |= XHCI_TRB_3_BSR_BIT; 1193 1194 trb.dwTrb3 = htole32(temp); 1195 1196 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1197 } 1198 1199 static usb_error_t 1200 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1201 { 1202 struct usb_page_search buf_inp; 1203 struct usb_page_search buf_dev; 1204 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1205 struct xhci_hw_dev *hdev; 1206 struct xhci_dev_ctx *pdev; 1207 struct xhci_endpoint_ext *pepext; 1208 uint32_t temp; 1209 uint16_t mps; 1210 usb_error_t err; 1211 uint8_t index; 1212 1213 /* the root HUB case is not handled here */ 1214 if (udev->parent_hub == NULL) 1215 return (USB_ERR_INVAL); 1216 1217 index = udev->controller_slot_id; 1218 1219 hdev = &sc->sc_hw.devs[index]; 1220 1221 if (mtx != NULL) 1222 mtx_unlock(mtx); 1223 1224 XHCI_CMD_LOCK(sc); 1225 1226 switch (hdev->state) { 1227 case XHCI_ST_DEFAULT: 1228 case XHCI_ST_ENABLED: 1229 1230 hdev->state = XHCI_ST_ENABLED; 1231 1232 /* set configure mask to slot and EP0 */ 1233 xhci_configure_mask(udev, 3, 0); 1234 1235 /* configure input slot context structure */ 1236 err = xhci_configure_device(udev); 1237 1238 if (err != 0) { 1239 DPRINTF("Could not configure device\n"); 1240 break; 1241 } 1242 1243 /* configure input endpoint context structure */ 1244 switch (udev->speed) { 1245 case USB_SPEED_LOW: 1246 case USB_SPEED_FULL: 1247 mps = 8; 1248 break; 1249 case USB_SPEED_HIGH: 1250 mps = 64; 1251 break; 1252 default: 1253 mps = 512; 1254 break; 1255 } 1256 1257 pepext = xhci_get_endpoint_ext(udev, 1258 &udev->ctrl_ep_desc); 1259 err = xhci_configure_endpoint(udev, 1260 &udev->ctrl_ep_desc, pepext->physaddr, 1261 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1262 1263 if (err != 0) { 1264 DPRINTF("Could not configure default endpoint\n"); 1265 break; 1266 } 1267 1268 /* execute set address command */ 1269 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1270 1271 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1272 (address == 0), index); 1273 1274 if (err != 0) { 1275 DPRINTF("Could not set address " 1276 "for slot %u.\n", index); 1277 if (address != 0) 1278 break; 1279 } 1280 1281 /* update device address to new value */ 1282 1283 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1284 pdev = buf_dev.buffer; 1285 usb_pc_cpu_invalidate(&hdev->device_pc); 1286 1287 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1288 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1289 1290 /* update device state to new value */ 1291 1292 if (address != 0) 1293 hdev->state = XHCI_ST_ADDRESSED; 1294 else 1295 hdev->state = XHCI_ST_DEFAULT; 1296 break; 1297 1298 default: 1299 DPRINTF("Wrong state for set address.\n"); 1300 err = USB_ERR_IOERROR; 1301 break; 1302 } 1303 XHCI_CMD_UNLOCK(sc); 1304 1305 if (mtx != NULL) 1306 mtx_lock(mtx); 1307 1308 return (err); 1309 } 1310 1311 static usb_error_t 1312 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1313 uint8_t deconfigure, uint8_t slot_id) 1314 { 1315 struct xhci_trb trb; 1316 uint32_t temp; 1317 1318 DPRINTF("\n"); 1319 1320 trb.qwTrb0 = htole64(input_ctx); 1321 trb.dwTrb2 = 0; 1322 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1323 XHCI_TRB_3_SLOT_SET(slot_id); 1324 1325 if (deconfigure) 1326 temp |= XHCI_TRB_3_DCEP_BIT; 1327 1328 trb.dwTrb3 = htole32(temp); 1329 1330 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1331 } 1332 1333 static usb_error_t 1334 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1335 uint8_t slot_id) 1336 { 1337 struct xhci_trb trb; 1338 uint32_t temp; 1339 1340 DPRINTF("\n"); 1341 1342 trb.qwTrb0 = htole64(input_ctx); 1343 trb.dwTrb2 = 0; 1344 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1345 XHCI_TRB_3_SLOT_SET(slot_id); 1346 trb.dwTrb3 = htole32(temp); 1347 1348 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1349 } 1350 1351 static usb_error_t 1352 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1353 uint8_t ep_id, uint8_t slot_id) 1354 { 1355 struct xhci_trb trb; 1356 uint32_t temp; 1357 1358 DPRINTF("\n"); 1359 1360 trb.qwTrb0 = 0; 1361 trb.dwTrb2 = 0; 1362 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1363 XHCI_TRB_3_SLOT_SET(slot_id) | 1364 XHCI_TRB_3_EP_SET(ep_id); 1365 1366 if (preserve) 1367 temp |= XHCI_TRB_3_PRSV_BIT; 1368 1369 trb.dwTrb3 = htole32(temp); 1370 1371 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1372 } 1373 1374 static usb_error_t 1375 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1376 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1377 { 1378 struct xhci_trb trb; 1379 uint32_t temp; 1380 1381 DPRINTF("\n"); 1382 1383 trb.qwTrb0 = htole64(dequeue_ptr); 1384 1385 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1386 trb.dwTrb2 = htole32(temp); 1387 1388 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1389 XHCI_TRB_3_SLOT_SET(slot_id) | 1390 XHCI_TRB_3_EP_SET(ep_id); 1391 trb.dwTrb3 = htole32(temp); 1392 1393 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1394 } 1395 1396 static usb_error_t 1397 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1398 uint8_t ep_id, uint8_t slot_id) 1399 { 1400 struct xhci_trb trb; 1401 uint32_t temp; 1402 1403 DPRINTF("\n"); 1404 1405 trb.qwTrb0 = 0; 1406 trb.dwTrb2 = 0; 1407 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1408 XHCI_TRB_3_SLOT_SET(slot_id) | 1409 XHCI_TRB_3_EP_SET(ep_id); 1410 1411 if (suspend) 1412 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1413 1414 trb.dwTrb3 = htole32(temp); 1415 1416 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1417 } 1418 1419 static usb_error_t 1420 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1421 { 1422 struct xhci_trb trb; 1423 uint32_t temp; 1424 1425 DPRINTF("\n"); 1426 1427 trb.qwTrb0 = 0; 1428 trb.dwTrb2 = 0; 1429 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1430 XHCI_TRB_3_SLOT_SET(slot_id); 1431 1432 trb.dwTrb3 = htole32(temp); 1433 1434 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1435 } 1436 1437 /*------------------------------------------------------------------------* 1438 * xhci_interrupt - XHCI interrupt handler 1439 *------------------------------------------------------------------------*/ 1440 void 1441 xhci_interrupt(struct xhci_softc *sc) 1442 { 1443 uint32_t status; 1444 uint32_t temp; 1445 1446 USB_BUS_LOCK(&sc->sc_bus); 1447 1448 status = XREAD4(sc, oper, XHCI_USBSTS); 1449 1450 /* acknowledge interrupts */ 1451 1452 XWRITE4(sc, oper, XHCI_USBSTS, status); 1453 1454 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1455 1456 /* acknowledge pending event */ 1457 1458 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1459 1460 DPRINTFN(16, "real interrupt (sts=0x%08x, " 1461 "iman=0x%08x)\n", status, temp); 1462 1463 if (status != 0) { 1464 if (status & XHCI_STS_PCD) { 1465 xhci_root_intr(sc); 1466 } 1467 1468 if (status & XHCI_STS_HCH) { 1469 printf("%s: host controller halted\n", 1470 __FUNCTION__); 1471 } 1472 1473 if (status & XHCI_STS_HSE) { 1474 printf("%s: host system error\n", 1475 __FUNCTION__); 1476 } 1477 1478 if (status & XHCI_STS_HCE) { 1479 printf("%s: host controller error\n", 1480 __FUNCTION__); 1481 } 1482 } 1483 1484 xhci_interrupt_poll(sc); 1485 1486 USB_BUS_UNLOCK(&sc->sc_bus); 1487 } 1488 1489 /*------------------------------------------------------------------------* 1490 * xhci_timeout - XHCI timeout handler 1491 *------------------------------------------------------------------------*/ 1492 static void 1493 xhci_timeout(void *arg) 1494 { 1495 struct usb_xfer *xfer = arg; 1496 1497 DPRINTF("xfer=%p\n", xfer); 1498 1499 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1500 1501 /* transfer is transferred */ 1502 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1503 } 1504 1505 static void 1506 xhci_do_poll(struct usb_bus *bus) 1507 { 1508 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1509 1510 USB_BUS_LOCK(&sc->sc_bus); 1511 xhci_interrupt_poll(sc); 1512 USB_BUS_UNLOCK(&sc->sc_bus); 1513 } 1514 1515 static void 1516 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1517 { 1518 struct usb_page_search buf_res; 1519 struct xhci_td *td; 1520 struct xhci_td *td_next; 1521 struct xhci_td *td_alt_next; 1522 uint32_t buf_offset; 1523 uint32_t average; 1524 uint32_t len_old; 1525 uint32_t dword; 1526 uint8_t shortpkt_old; 1527 uint8_t precompute; 1528 uint8_t x; 1529 1530 td_alt_next = NULL; 1531 buf_offset = 0; 1532 shortpkt_old = temp->shortpkt; 1533 len_old = temp->len; 1534 precompute = 1; 1535 1536 restart: 1537 1538 td = temp->td; 1539 td_next = temp->td_next; 1540 1541 while (1) { 1542 1543 if (temp->len == 0) { 1544 1545 if (temp->shortpkt) 1546 break; 1547 1548 /* send a Zero Length Packet, ZLP, last */ 1549 1550 temp->shortpkt = 1; 1551 average = 0; 1552 1553 } else { 1554 1555 average = temp->average; 1556 1557 if (temp->len < average) { 1558 if (temp->len % temp->max_packet_size) { 1559 temp->shortpkt = 1; 1560 } 1561 average = temp->len; 1562 } 1563 } 1564 1565 if (td_next == NULL) 1566 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1567 1568 /* get next TD */ 1569 1570 td = td_next; 1571 td_next = td->obj_next; 1572 1573 /* check if we are pre-computing */ 1574 1575 if (precompute) { 1576 1577 /* update remaining length */ 1578 1579 temp->len -= average; 1580 1581 continue; 1582 } 1583 /* fill out current TD */ 1584 1585 td->len = average; 1586 td->remainder = 0; 1587 td->status = 0; 1588 1589 /* update remaining length */ 1590 1591 temp->len -= average; 1592 1593 /* reset TRB index */ 1594 1595 x = 0; 1596 1597 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1598 /* immediate data */ 1599 1600 if (average > 8) 1601 average = 8; 1602 1603 td->td_trb[0].qwTrb0 = 0; 1604 1605 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1606 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1607 average); 1608 1609 dword = XHCI_TRB_2_BYTES_SET(8) | 1610 XHCI_TRB_2_TDSZ_SET(0) | 1611 XHCI_TRB_2_IRQ_SET(0); 1612 1613 td->td_trb[0].dwTrb2 = htole32(dword); 1614 1615 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1616 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1617 1618 /* check wLength */ 1619 if (td->td_trb[0].qwTrb0 & 1620 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1621 if (td->td_trb[0].qwTrb0 & htole64(1)) 1622 dword |= XHCI_TRB_3_TRT_IN; 1623 else 1624 dword |= XHCI_TRB_3_TRT_OUT; 1625 } 1626 1627 td->td_trb[0].dwTrb3 = htole32(dword); 1628 #ifdef USB_DEBUG 1629 xhci_dump_trb(&td->td_trb[x]); 1630 #endif 1631 x++; 1632 1633 } else do { 1634 1635 uint32_t npkt; 1636 1637 /* fill out buffer pointers */ 1638 1639 if (average == 0) { 1640 npkt = 1; 1641 memset(&buf_res, 0, sizeof(buf_res)); 1642 } else { 1643 usbd_get_page(temp->pc, temp->offset + 1644 buf_offset, &buf_res); 1645 1646 /* get length to end of page */ 1647 if (buf_res.length > average) 1648 buf_res.length = average; 1649 1650 /* check for maximum length */ 1651 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1652 buf_res.length = XHCI_TD_PAGE_SIZE; 1653 1654 /* setup npkt */ 1655 npkt = (average + temp->max_packet_size - 1) / 1656 temp->max_packet_size; 1657 1658 if (npkt > 31) 1659 npkt = 31; 1660 } 1661 1662 /* fill out TRB's */ 1663 td->td_trb[x].qwTrb0 = 1664 htole64((uint64_t)buf_res.physaddr); 1665 1666 dword = 1667 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1668 XHCI_TRB_2_TDSZ_SET(npkt) | 1669 XHCI_TRB_2_IRQ_SET(0); 1670 1671 td->td_trb[x].dwTrb2 = htole32(dword); 1672 1673 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1674 XHCI_TRB_3_TYPE_SET(temp->trb_type) | 1675 (temp->do_isoc_sync ? 1676 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) : 1677 XHCI_TRB_3_ISO_SIA_BIT) | 1678 XHCI_TRB_3_TBC_SET(temp->tbc) | 1679 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1680 1681 temp->do_isoc_sync = 0; 1682 1683 if (temp->direction == UE_DIR_IN) { 1684 dword |= XHCI_TRB_3_DIR_IN; 1685 1686 /* 1687 * NOTE: Only the SETUP stage should 1688 * use the IDT bit. Else transactions 1689 * can be sent using the wrong data 1690 * toggle value. 1691 */ 1692 if (temp->trb_type != 1693 XHCI_TRB_TYPE_SETUP_STAGE && 1694 temp->trb_type != 1695 XHCI_TRB_TYPE_STATUS_STAGE) 1696 dword |= XHCI_TRB_3_ISP_BIT; 1697 } 1698 1699 td->td_trb[x].dwTrb3 = htole32(dword); 1700 1701 average -= buf_res.length; 1702 buf_offset += buf_res.length; 1703 #ifdef USB_DEBUG 1704 xhci_dump_trb(&td->td_trb[x]); 1705 #endif 1706 x++; 1707 1708 } while (average != 0); 1709 1710 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1711 1712 /* store number of data TRB's */ 1713 1714 td->ntrb = x; 1715 1716 DPRINTF("NTRB=%u\n", x); 1717 1718 /* fill out link TRB */ 1719 1720 if (td_next != NULL) { 1721 /* link the current TD with the next one */ 1722 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1723 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1724 } else { 1725 /* this field will get updated later */ 1726 DPRINTF("NOLINK\n"); 1727 } 1728 1729 dword = XHCI_TRB_2_IRQ_SET(0); 1730 1731 td->td_trb[x].dwTrb2 = htole32(dword); 1732 1733 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1734 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT; 1735 1736 td->td_trb[x].dwTrb3 = htole32(dword); 1737 1738 td->alt_next = td_alt_next; 1739 #ifdef USB_DEBUG 1740 xhci_dump_trb(&td->td_trb[x]); 1741 #endif 1742 usb_pc_cpu_flush(td->page_cache); 1743 } 1744 1745 if (precompute) { 1746 precompute = 0; 1747 1748 /* setup alt next pointer, if any */ 1749 if (temp->last_frame) { 1750 td_alt_next = NULL; 1751 } else { 1752 /* we use this field internally */ 1753 td_alt_next = td_next; 1754 } 1755 1756 /* restore */ 1757 temp->shortpkt = shortpkt_old; 1758 temp->len = len_old; 1759 goto restart; 1760 } 1761 1762 /* remove cycle bit from first if we are stepping the TRBs */ 1763 if (temp->step_td) 1764 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1765 1766 /* remove chain bit because this is the last TRB in the chain */ 1767 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1768 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1769 1770 usb_pc_cpu_flush(td->page_cache); 1771 1772 temp->td = td; 1773 temp->td_next = td_next; 1774 } 1775 1776 static void 1777 xhci_setup_generic_chain(struct usb_xfer *xfer) 1778 { 1779 struct xhci_std_temp temp; 1780 struct xhci_td *td; 1781 uint32_t x; 1782 uint32_t y; 1783 uint8_t mult; 1784 1785 temp.do_isoc_sync = 0; 1786 temp.step_td = 0; 1787 temp.tbc = 0; 1788 temp.tlbpc = 0; 1789 temp.average = xfer->max_hc_frame_size; 1790 temp.max_packet_size = xfer->max_packet_size; 1791 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1792 temp.pc = NULL; 1793 temp.last_frame = 0; 1794 temp.offset = 0; 1795 temp.multishort = xfer->flags_int.isochronous_xfr || 1796 xfer->flags_int.control_xfr || 1797 xfer->flags_int.short_frames_ok; 1798 1799 /* toggle the DMA set we are using */ 1800 xfer->flags_int.curr_dma_set ^= 1; 1801 1802 /* get next DMA set */ 1803 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1804 1805 temp.td = NULL; 1806 temp.td_next = td; 1807 1808 xfer->td_transfer_first = td; 1809 xfer->td_transfer_cache = td; 1810 1811 if (xfer->flags_int.isochronous_xfr) { 1812 uint8_t shift; 1813 1814 /* compute multiplier for ISOCHRONOUS transfers */ 1815 mult = xfer->endpoint->ecomp ? 1816 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 1817 : 0; 1818 /* check for USB 2.0 multiplier */ 1819 if (mult == 0) { 1820 mult = (xfer->endpoint->edesc-> 1821 wMaxPacketSize[1] >> 3) & 3; 1822 } 1823 /* range check */ 1824 if (mult > 2) 1825 mult = 3; 1826 else 1827 mult++; 1828 1829 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 1830 1831 DPRINTF("MFINDEX=0x%08x\n", x); 1832 1833 switch (usbd_get_speed(xfer->xroot->udev)) { 1834 case USB_SPEED_FULL: 1835 shift = 3; 1836 temp.isoc_delta = 8; /* 1ms */ 1837 x += temp.isoc_delta - 1; 1838 x &= ~(temp.isoc_delta - 1); 1839 break; 1840 default: 1841 shift = usbd_xfer_get_fps_shift(xfer); 1842 temp.isoc_delta = 1U << shift; 1843 x += temp.isoc_delta - 1; 1844 x &= ~(temp.isoc_delta - 1); 1845 /* simple frame load balancing */ 1846 x += xfer->endpoint->usb_uframe; 1847 break; 1848 } 1849 1850 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 1851 1852 if ((xfer->endpoint->is_synced == 0) || 1853 (y < (xfer->nframes << shift)) || 1854 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 1855 /* 1856 * If there is data underflow or the pipe 1857 * queue is empty we schedule the transfer a 1858 * few frames ahead of the current frame 1859 * position. Else two isochronous transfers 1860 * might overlap. 1861 */ 1862 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 1863 xfer->endpoint->is_synced = 1; 1864 temp.do_isoc_sync = 1; 1865 1866 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1867 } 1868 1869 /* compute isochronous completion time */ 1870 1871 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 1872 1873 xfer->isoc_time_complete = 1874 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 1875 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 1876 1877 x = 0; 1878 temp.isoc_frame = xfer->endpoint->isoc_next; 1879 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 1880 1881 xfer->endpoint->isoc_next += xfer->nframes << shift; 1882 1883 } else if (xfer->flags_int.control_xfr) { 1884 1885 /* check if we should prepend a setup message */ 1886 1887 if (xfer->flags_int.control_hdr) { 1888 1889 temp.len = xfer->frlengths[0]; 1890 temp.pc = xfer->frbuffers + 0; 1891 temp.shortpkt = temp.len ? 1 : 0; 1892 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 1893 temp.direction = 0; 1894 1895 /* check for last frame */ 1896 if (xfer->nframes == 1) { 1897 /* no STATUS stage yet, SETUP is last */ 1898 if (xfer->flags_int.control_act) 1899 temp.last_frame = 1; 1900 } 1901 1902 xhci_setup_generic_chain_sub(&temp); 1903 } 1904 x = 1; 1905 mult = 1; 1906 temp.isoc_delta = 0; 1907 temp.isoc_frame = 0; 1908 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 1909 } else { 1910 x = 0; 1911 mult = 1; 1912 temp.isoc_delta = 0; 1913 temp.isoc_frame = 0; 1914 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 1915 } 1916 1917 if (x != xfer->nframes) { 1918 /* setup page_cache pointer */ 1919 temp.pc = xfer->frbuffers + x; 1920 /* set endpoint direction */ 1921 temp.direction = UE_GET_DIR(xfer->endpointno); 1922 } 1923 1924 while (x != xfer->nframes) { 1925 1926 /* DATA0 / DATA1 message */ 1927 1928 temp.len = xfer->frlengths[x]; 1929 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 1930 x != 0 && temp.multishort == 0); 1931 1932 x++; 1933 1934 if (x == xfer->nframes) { 1935 if (xfer->flags_int.control_xfr) { 1936 /* no STATUS stage yet, DATA is last */ 1937 if (xfer->flags_int.control_act) 1938 temp.last_frame = 1; 1939 } else { 1940 temp.last_frame = 1; 1941 } 1942 } 1943 if (temp.len == 0) { 1944 1945 /* make sure that we send an USB packet */ 1946 1947 temp.shortpkt = 0; 1948 1949 temp.tbc = 0; 1950 temp.tlbpc = mult - 1; 1951 1952 } else if (xfer->flags_int.isochronous_xfr) { 1953 1954 uint8_t tdpc; 1955 1956 /* 1957 * Isochronous transfers don't have short 1958 * packet termination: 1959 */ 1960 1961 temp.shortpkt = 1; 1962 1963 /* isochronous transfers have a transfer limit */ 1964 1965 if (temp.len > xfer->max_frame_size) 1966 temp.len = xfer->max_frame_size; 1967 1968 /* compute TD packet count */ 1969 tdpc = (temp.len + xfer->max_packet_size - 1) / 1970 xfer->max_packet_size; 1971 1972 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 1973 temp.tlbpc = (tdpc % mult); 1974 1975 if (temp.tlbpc == 0) 1976 temp.tlbpc = mult - 1; 1977 else 1978 temp.tlbpc--; 1979 } else { 1980 1981 /* regular data transfer */ 1982 1983 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 1984 } 1985 1986 xhci_setup_generic_chain_sub(&temp); 1987 1988 if (xfer->flags_int.isochronous_xfr) { 1989 temp.offset += xfer->frlengths[x - 1]; 1990 temp.isoc_frame += temp.isoc_delta; 1991 } else { 1992 /* get next Page Cache pointer */ 1993 temp.pc = xfer->frbuffers + x; 1994 } 1995 } 1996 1997 /* check if we should append a status stage */ 1998 1999 if (xfer->flags_int.control_xfr && 2000 !xfer->flags_int.control_act) { 2001 2002 /* 2003 * Send a DATA1 message and invert the current 2004 * endpoint direction. 2005 */ 2006 temp.step_td = (xfer->nframes != 0); 2007 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2008 temp.len = 0; 2009 temp.pc = NULL; 2010 temp.shortpkt = 0; 2011 temp.last_frame = 1; 2012 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2013 2014 xhci_setup_generic_chain_sub(&temp); 2015 } 2016 2017 td = temp.td; 2018 2019 /* must have at least one frame! */ 2020 2021 xfer->td_transfer_last = td; 2022 2023 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2024 } 2025 2026 static void 2027 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2028 { 2029 struct usb_page_search buf_res; 2030 struct xhci_dev_ctx_addr *pdctxa; 2031 2032 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2033 2034 pdctxa = buf_res.buffer; 2035 2036 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2037 2038 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2039 2040 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2041 } 2042 2043 static usb_error_t 2044 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2045 { 2046 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2047 struct usb_page_search buf_inp; 2048 struct xhci_input_dev_ctx *pinp; 2049 uint8_t index; 2050 2051 index = udev->controller_slot_id; 2052 2053 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2054 2055 pinp = buf_inp.buffer; 2056 2057 if (drop) { 2058 mask &= XHCI_INCTX_NON_CTRL_MASK; 2059 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2060 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2061 } else { 2062 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2063 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2064 } 2065 return (0); 2066 } 2067 2068 static usb_error_t 2069 xhci_configure_endpoint(struct usb_device *udev, 2070 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr, 2071 uint16_t interval, uint8_t max_packet_count, uint8_t mult, 2072 uint8_t fps_shift, uint16_t max_packet_size, 2073 uint16_t max_frame_size, uint8_t ep_mode) 2074 { 2075 struct usb_page_search buf_inp; 2076 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2077 struct xhci_input_dev_ctx *pinp; 2078 uint32_t temp; 2079 uint8_t index; 2080 uint8_t epno; 2081 uint8_t type; 2082 2083 index = udev->controller_slot_id; 2084 2085 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2086 2087 pinp = buf_inp.buffer; 2088 2089 epno = edesc->bEndpointAddress; 2090 type = edesc->bmAttributes & UE_XFERTYPE; 2091 2092 if (type == UE_CONTROL) 2093 epno |= UE_DIR_IN; 2094 2095 epno = XHCI_EPNO2EPID(epno); 2096 2097 if (epno == 0) 2098 return (USB_ERR_NO_PIPE); /* invalid */ 2099 2100 if (max_packet_count == 0) 2101 return (USB_ERR_BAD_BUFSIZE); 2102 2103 max_packet_count--; 2104 2105 if (mult == 0) 2106 return (USB_ERR_BAD_BUFSIZE); 2107 2108 if (ep_mode == USB_EP_MODE_STREAMS) { 2109 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2110 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2111 XHCI_EPCTX_0_LSA_SET(1); 2112 2113 ring_addr += sizeof(struct xhci_trb) * 2114 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2115 } else { 2116 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2117 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2118 XHCI_EPCTX_0_LSA_SET(0); 2119 2120 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2121 } 2122 2123 switch (udev->speed) { 2124 case USB_SPEED_FULL: 2125 case USB_SPEED_LOW: 2126 /* 1ms -> 125us */ 2127 fps_shift += 3; 2128 break; 2129 default: 2130 break; 2131 } 2132 2133 switch (type) { 2134 case UE_INTERRUPT: 2135 if (fps_shift > 3) 2136 fps_shift--; 2137 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2138 break; 2139 case UE_ISOCHRONOUS: 2140 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2141 2142 switch (udev->speed) { 2143 case USB_SPEED_SUPER: 2144 if (mult > 3) 2145 mult = 3; 2146 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2147 max_packet_count /= mult; 2148 break; 2149 default: 2150 break; 2151 } 2152 break; 2153 default: 2154 break; 2155 } 2156 2157 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2158 2159 temp = 2160 XHCI_EPCTX_1_HID_SET(0) | 2161 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2162 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2163 2164 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2165 if (type != UE_ISOCHRONOUS) 2166 temp |= XHCI_EPCTX_1_CERR_SET(3); 2167 } 2168 2169 switch (type) { 2170 case UE_CONTROL: 2171 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2172 break; 2173 case UE_ISOCHRONOUS: 2174 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2175 break; 2176 case UE_BULK: 2177 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2178 break; 2179 default: 2180 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2181 break; 2182 } 2183 2184 /* check for IN direction */ 2185 if (epno & 1) 2186 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2187 2188 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2189 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2190 2191 switch (edesc->bmAttributes & UE_XFERTYPE) { 2192 case UE_INTERRUPT: 2193 case UE_ISOCHRONOUS: 2194 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2195 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2196 max_frame_size)); 2197 break; 2198 case UE_CONTROL: 2199 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2200 break; 2201 default: 2202 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2203 break; 2204 } 2205 2206 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2207 2208 #ifdef USB_DEBUG 2209 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2210 #endif 2211 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2212 2213 return (0); /* success */ 2214 } 2215 2216 static usb_error_t 2217 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2218 { 2219 struct xhci_endpoint_ext *pepext; 2220 struct usb_endpoint_ss_comp_descriptor *ecomp; 2221 usb_stream_t x; 2222 2223 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2224 xfer->endpoint->edesc); 2225 2226 ecomp = xfer->endpoint->ecomp; 2227 2228 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2229 uint64_t temp; 2230 2231 /* halt any transfers */ 2232 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2233 2234 /* compute start of TRB ring for stream "x" */ 2235 temp = pepext->physaddr + 2236 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2237 XHCI_SCTX_0_SCT_SEC_TR_RING; 2238 2239 /* make tree structure */ 2240 pepext->trb[(XHCI_MAX_TRANSFERS * 2241 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2242 2243 /* reserved fields */ 2244 pepext->trb[(XHCI_MAX_TRANSFERS * 2245 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2246 pepext->trb[(XHCI_MAX_TRANSFERS * 2247 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2248 } 2249 usb_pc_cpu_flush(pepext->page_cache); 2250 2251 return (xhci_configure_endpoint(xfer->xroot->udev, 2252 xfer->endpoint->edesc, pepext->physaddr, 2253 xfer->interval, xfer->max_packet_count, 2254 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2255 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2256 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2257 } 2258 2259 static usb_error_t 2260 xhci_configure_device(struct usb_device *udev) 2261 { 2262 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2263 struct usb_page_search buf_inp; 2264 struct usb_page_cache *pcinp; 2265 struct xhci_input_dev_ctx *pinp; 2266 struct usb_device *hubdev; 2267 uint32_t temp; 2268 uint32_t route; 2269 uint32_t rh_port; 2270 uint8_t is_hub; 2271 uint8_t index; 2272 uint8_t depth; 2273 2274 index = udev->controller_slot_id; 2275 2276 DPRINTF("index=%u\n", index); 2277 2278 pcinp = &sc->sc_hw.devs[index].input_pc; 2279 2280 usbd_get_page(pcinp, 0, &buf_inp); 2281 2282 pinp = buf_inp.buffer; 2283 2284 rh_port = 0; 2285 route = 0; 2286 2287 /* figure out route string and root HUB port number */ 2288 2289 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2290 2291 if (hubdev->parent_hub == NULL) 2292 break; 2293 2294 depth = hubdev->parent_hub->depth; 2295 2296 /* 2297 * NOTE: HS/FS/LS devices and the SS root HUB can have 2298 * more than 15 ports 2299 */ 2300 2301 rh_port = hubdev->port_no; 2302 2303 if (depth == 0) 2304 break; 2305 2306 if (rh_port > 15) 2307 rh_port = 15; 2308 2309 if (depth < 6) 2310 route |= rh_port << (4 * (depth - 1)); 2311 } 2312 2313 DPRINTF("Route=0x%08x\n", route); 2314 2315 temp = XHCI_SCTX_0_ROUTE_SET(route); 2316 2317 switch (sc->sc_hw.devs[index].state) { 2318 case XHCI_ST_CONFIGURED: 2319 temp |= XHCI_SCTX_0_CTX_NUM_SET(XHCI_MAX_ENDPOINTS - 1); 2320 break; 2321 default: 2322 temp |= XHCI_SCTX_0_CTX_NUM_SET(1); 2323 break; 2324 } 2325 2326 switch (udev->speed) { 2327 case USB_SPEED_LOW: 2328 temp |= XHCI_SCTX_0_SPEED_SET(2); 2329 if (udev->parent_hs_hub != NULL && 2330 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2331 UDPROTO_HSHUBMTT) { 2332 DPRINTF("Device inherits MTT\n"); 2333 temp |= XHCI_SCTX_0_MTT_SET(1); 2334 } 2335 break; 2336 case USB_SPEED_HIGH: 2337 temp |= XHCI_SCTX_0_SPEED_SET(3); 2338 if (sc->sc_hw.devs[index].nports != 0 && 2339 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2340 DPRINTF("HUB supports MTT\n"); 2341 temp |= XHCI_SCTX_0_MTT_SET(1); 2342 } 2343 break; 2344 case USB_SPEED_FULL: 2345 temp |= XHCI_SCTX_0_SPEED_SET(1); 2346 if (udev->parent_hs_hub != NULL && 2347 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2348 UDPROTO_HSHUBMTT) { 2349 DPRINTF("Device inherits MTT\n"); 2350 temp |= XHCI_SCTX_0_MTT_SET(1); 2351 } 2352 break; 2353 default: 2354 temp |= XHCI_SCTX_0_SPEED_SET(4); 2355 break; 2356 } 2357 2358 is_hub = sc->sc_hw.devs[index].nports != 0 && 2359 (udev->speed == USB_SPEED_SUPER || 2360 udev->speed == USB_SPEED_HIGH); 2361 2362 if (is_hub) 2363 temp |= XHCI_SCTX_0_HUB_SET(1); 2364 2365 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2366 2367 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2368 2369 if (is_hub) { 2370 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2371 sc->sc_hw.devs[index].nports); 2372 } 2373 2374 switch (udev->speed) { 2375 case USB_SPEED_SUPER: 2376 switch (sc->sc_hw.devs[index].state) { 2377 case XHCI_ST_ADDRESSED: 2378 case XHCI_ST_CONFIGURED: 2379 /* enable power save */ 2380 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2381 break; 2382 default: 2383 /* disable power save */ 2384 break; 2385 } 2386 break; 2387 default: 2388 break; 2389 } 2390 2391 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2392 2393 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2394 2395 if (is_hub) { 2396 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2397 sc->sc_hw.devs[index].tt); 2398 } 2399 2400 hubdev = udev->parent_hs_hub; 2401 2402 /* check if we should activate the transaction translator */ 2403 switch (udev->speed) { 2404 case USB_SPEED_FULL: 2405 case USB_SPEED_LOW: 2406 if (hubdev != NULL) { 2407 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2408 hubdev->controller_slot_id); 2409 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2410 udev->hs_port_no); 2411 } 2412 break; 2413 default: 2414 break; 2415 } 2416 2417 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2418 2419 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) | 2420 XHCI_SCTX_3_SLOT_STATE_SET(0); 2421 2422 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2423 2424 #ifdef USB_DEBUG 2425 xhci_dump_device(sc, &pinp->ctx_slot); 2426 #endif 2427 usb_pc_cpu_flush(pcinp); 2428 2429 return (0); /* success */ 2430 } 2431 2432 static usb_error_t 2433 xhci_alloc_device_ext(struct usb_device *udev) 2434 { 2435 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2436 struct usb_page_search buf_dev; 2437 struct usb_page_search buf_ep; 2438 struct xhci_trb *trb; 2439 struct usb_page_cache *pc; 2440 struct usb_page *pg; 2441 uint64_t addr; 2442 uint8_t index; 2443 uint8_t i; 2444 2445 index = udev->controller_slot_id; 2446 2447 pc = &sc->sc_hw.devs[index].device_pc; 2448 pg = &sc->sc_hw.devs[index].device_pg; 2449 2450 /* need to initialize the page cache */ 2451 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2452 2453 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2454 (2 * sizeof(struct xhci_dev_ctx)) : 2455 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2456 goto error; 2457 2458 usbd_get_page(pc, 0, &buf_dev); 2459 2460 pc = &sc->sc_hw.devs[index].input_pc; 2461 pg = &sc->sc_hw.devs[index].input_pg; 2462 2463 /* need to initialize the page cache */ 2464 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2465 2466 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2467 (2 * sizeof(struct xhci_input_dev_ctx)) : 2468 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) 2469 goto error; 2470 2471 pc = &sc->sc_hw.devs[index].endpoint_pc; 2472 pg = &sc->sc_hw.devs[index].endpoint_pg; 2473 2474 /* need to initialize the page cache */ 2475 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2476 2477 if (usb_pc_alloc_mem(pc, pg, sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) 2478 goto error; 2479 2480 /* initialise all endpoint LINK TRBs */ 2481 2482 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2483 2484 /* lookup endpoint TRB ring */ 2485 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2486 2487 /* get TRB pointer */ 2488 trb = buf_ep.buffer; 2489 trb += XHCI_MAX_TRANSFERS - 1; 2490 2491 /* get TRB start address */ 2492 addr = buf_ep.physaddr; 2493 2494 /* create LINK TRB */ 2495 trb->qwTrb0 = htole64(addr); 2496 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2497 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2498 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2499 } 2500 2501 usb_pc_cpu_flush(pc); 2502 2503 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2504 2505 return (0); 2506 2507 error: 2508 xhci_free_device_ext(udev); 2509 2510 return (USB_ERR_NOMEM); 2511 } 2512 2513 static void 2514 xhci_free_device_ext(struct usb_device *udev) 2515 { 2516 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2517 uint8_t index; 2518 2519 index = udev->controller_slot_id; 2520 xhci_set_slot_pointer(sc, index, 0); 2521 2522 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2523 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2524 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2525 } 2526 2527 static struct xhci_endpoint_ext * 2528 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2529 { 2530 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2531 struct xhci_endpoint_ext *pepext; 2532 struct usb_page_cache *pc; 2533 struct usb_page_search buf_ep; 2534 uint8_t epno; 2535 uint8_t index; 2536 2537 epno = edesc->bEndpointAddress; 2538 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2539 epno |= UE_DIR_IN; 2540 2541 epno = XHCI_EPNO2EPID(epno); 2542 2543 index = udev->controller_slot_id; 2544 2545 pc = &sc->sc_hw.devs[index].endpoint_pc; 2546 2547 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2548 trb[epno][0], &buf_ep); 2549 2550 pepext = &sc->sc_hw.devs[index].endp[epno]; 2551 pepext->page_cache = pc; 2552 pepext->trb = buf_ep.buffer; 2553 pepext->physaddr = buf_ep.physaddr; 2554 2555 return (pepext); 2556 } 2557 2558 static void 2559 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2560 { 2561 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2562 uint8_t epno; 2563 uint8_t index; 2564 2565 epno = xfer->endpointno; 2566 if (xfer->flags_int.control_xfr) 2567 epno |= UE_DIR_IN; 2568 2569 epno = XHCI_EPNO2EPID(epno); 2570 index = xfer->xroot->udev->controller_slot_id; 2571 2572 if (xfer->xroot->udev->flags.self_suspended == 0) 2573 XWRITE4(sc, door, XHCI_DOORBELL(index), epno | XHCI_DB_SID_SET(0)); 2574 } 2575 2576 static void 2577 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2578 { 2579 struct xhci_endpoint_ext *pepext; 2580 2581 if (xfer->flags_int.bandwidth_reclaimed) { 2582 xfer->flags_int.bandwidth_reclaimed = 0; 2583 2584 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2585 xfer->endpoint->edesc); 2586 2587 pepext->trb_used[xfer->stream_id]--; 2588 2589 pepext->xfer[xfer->qh_pos] = NULL; 2590 2591 if (error && pepext->trb_running != 0) { 2592 pepext->trb_halted = 1; 2593 pepext->trb_running = 0; 2594 } 2595 } 2596 } 2597 2598 static usb_error_t 2599 xhci_transfer_insert(struct usb_xfer *xfer) 2600 { 2601 struct xhci_td *td_first; 2602 struct xhci_td *td_last; 2603 struct xhci_endpoint_ext *pepext; 2604 uint64_t addr; 2605 usb_stream_t id; 2606 uint8_t i; 2607 uint8_t inext; 2608 uint8_t trb_limit; 2609 2610 DPRINTFN(8, "\n"); 2611 2612 id = xfer->stream_id; 2613 2614 /* check if already inserted */ 2615 if (xfer->flags_int.bandwidth_reclaimed) { 2616 DPRINTFN(8, "Already in schedule\n"); 2617 return (0); 2618 } 2619 2620 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2621 xfer->endpoint->edesc); 2622 2623 td_first = xfer->td_transfer_first; 2624 td_last = xfer->td_transfer_last; 2625 addr = pepext->physaddr; 2626 2627 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2628 case UE_CONTROL: 2629 case UE_INTERRUPT: 2630 /* single buffered */ 2631 trb_limit = 1; 2632 break; 2633 default: 2634 /* multi buffered */ 2635 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2636 break; 2637 } 2638 2639 if (pepext->trb_used[id] >= trb_limit) { 2640 DPRINTFN(8, "Too many TDs queued.\n"); 2641 return (USB_ERR_NOMEM); 2642 } 2643 2644 /* check for stopped condition, after putting transfer on interrupt queue */ 2645 if (pepext->trb_running == 0) { 2646 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2647 2648 DPRINTFN(8, "Not running\n"); 2649 2650 /* start configuration */ 2651 (void)usb_proc_msignal(&sc->sc_config_proc, 2652 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2653 return (0); 2654 } 2655 2656 pepext->trb_used[id]++; 2657 2658 /* get current TRB index */ 2659 i = pepext->trb_index[id]; 2660 2661 /* get next TRB index */ 2662 inext = (i + 1); 2663 2664 /* the last entry of the ring is a hardcoded link TRB */ 2665 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2666 inext = 0; 2667 2668 /* offset for stream */ 2669 i += id * XHCI_MAX_TRANSFERS; 2670 inext += id * XHCI_MAX_TRANSFERS; 2671 2672 /* compute terminating return address */ 2673 addr += (inext * sizeof(struct xhci_trb)); 2674 2675 /* update next pointer of last link TRB */ 2676 td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr); 2677 td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2678 td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2679 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2680 2681 #ifdef USB_DEBUG 2682 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2683 #endif 2684 usb_pc_cpu_flush(td_last->page_cache); 2685 2686 /* write ahead chain end marker */ 2687 2688 pepext->trb[inext].qwTrb0 = 0; 2689 pepext->trb[inext].dwTrb2 = 0; 2690 pepext->trb[inext].dwTrb3 = 0; 2691 2692 /* update next pointer of link TRB */ 2693 2694 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2695 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2696 2697 #ifdef USB_DEBUG 2698 xhci_dump_trb(&pepext->trb[i]); 2699 #endif 2700 usb_pc_cpu_flush(pepext->page_cache); 2701 2702 /* toggle cycle bit which activates the transfer chain */ 2703 2704 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2705 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2706 2707 usb_pc_cpu_flush(pepext->page_cache); 2708 2709 DPRINTF("qh_pos = %u\n", i); 2710 2711 pepext->xfer[i] = xfer; 2712 2713 xfer->qh_pos = i; 2714 2715 xfer->flags_int.bandwidth_reclaimed = 1; 2716 2717 pepext->trb_index[id] = inext; 2718 2719 xhci_endpoint_doorbell(xfer); 2720 2721 return (0); 2722 } 2723 2724 static void 2725 xhci_root_intr(struct xhci_softc *sc) 2726 { 2727 uint16_t i; 2728 2729 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2730 2731 /* clear any old interrupt data */ 2732 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2733 2734 for (i = 1; i <= sc->sc_noport; i++) { 2735 /* pick out CHANGE bits from the status register */ 2736 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2737 XHCI_PS_CSC | XHCI_PS_PEC | 2738 XHCI_PS_OCC | XHCI_PS_WRC | 2739 XHCI_PS_PRC | XHCI_PS_PLC | 2740 XHCI_PS_CEC)) { 2741 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2742 DPRINTF("port %d changed\n", i); 2743 } 2744 } 2745 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2746 sizeof(sc->sc_hub_idata)); 2747 } 2748 2749 /*------------------------------------------------------------------------* 2750 * xhci_device_done - XHCI done handler 2751 * 2752 * NOTE: This function can be called two times in a row on 2753 * the same USB transfer. From close and from interrupt. 2754 *------------------------------------------------------------------------*/ 2755 static void 2756 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2757 { 2758 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2759 xfer, xfer->endpoint, error); 2760 2761 /* remove transfer from HW queue */ 2762 xhci_transfer_remove(xfer, error); 2763 2764 /* dequeue transfer and start next transfer */ 2765 usbd_transfer_done(xfer, error); 2766 } 2767 2768 /*------------------------------------------------------------------------* 2769 * XHCI data transfer support (generic type) 2770 *------------------------------------------------------------------------*/ 2771 static void 2772 xhci_device_generic_open(struct usb_xfer *xfer) 2773 { 2774 if (xfer->flags_int.isochronous_xfr) { 2775 switch (xfer->xroot->udev->speed) { 2776 case USB_SPEED_FULL: 2777 break; 2778 default: 2779 usb_hs_bandwidth_alloc(xfer); 2780 break; 2781 } 2782 } 2783 } 2784 2785 static void 2786 xhci_device_generic_close(struct usb_xfer *xfer) 2787 { 2788 DPRINTF("\n"); 2789 2790 xhci_device_done(xfer, USB_ERR_CANCELLED); 2791 2792 if (xfer->flags_int.isochronous_xfr) { 2793 switch (xfer->xroot->udev->speed) { 2794 case USB_SPEED_FULL: 2795 break; 2796 default: 2797 usb_hs_bandwidth_free(xfer); 2798 break; 2799 } 2800 } 2801 } 2802 2803 static void 2804 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 2805 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 2806 { 2807 struct usb_xfer *xfer; 2808 2809 /* check if there is a current transfer */ 2810 xfer = ep->endpoint_q[stream_id].curr; 2811 if (xfer == NULL) 2812 return; 2813 2814 /* 2815 * Check if the current transfer is started and then pickup 2816 * the next one, if any. Else wait for next start event due to 2817 * block on failure feature. 2818 */ 2819 if (!xfer->flags_int.bandwidth_reclaimed) 2820 return; 2821 2822 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 2823 if (xfer == NULL) { 2824 /* 2825 * In case of enter we have to consider that the 2826 * transfer is queued by the USB core after the enter 2827 * method is called. 2828 */ 2829 xfer = enter_xfer; 2830 2831 if (xfer == NULL) 2832 return; 2833 } 2834 2835 /* try to multi buffer */ 2836 xhci_transfer_insert(xfer); 2837 } 2838 2839 static void 2840 xhci_device_generic_enter(struct usb_xfer *xfer) 2841 { 2842 DPRINTF("\n"); 2843 2844 /* setup TD's and QH */ 2845 xhci_setup_generic_chain(xfer); 2846 2847 xhci_device_generic_multi_enter(xfer->endpoint, 2848 xfer->stream_id, xfer); 2849 } 2850 2851 static void 2852 xhci_device_generic_start(struct usb_xfer *xfer) 2853 { 2854 DPRINTF("\n"); 2855 2856 /* try to insert xfer on HW queue */ 2857 xhci_transfer_insert(xfer); 2858 2859 /* try to multi buffer */ 2860 xhci_device_generic_multi_enter(xfer->endpoint, 2861 xfer->stream_id, NULL); 2862 2863 /* add transfer last on interrupt queue */ 2864 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2865 2866 /* start timeout, if any */ 2867 if (xfer->timeout != 0) 2868 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 2869 } 2870 2871 struct usb_pipe_methods xhci_device_generic_methods = 2872 { 2873 .open = xhci_device_generic_open, 2874 .close = xhci_device_generic_close, 2875 .enter = xhci_device_generic_enter, 2876 .start = xhci_device_generic_start, 2877 }; 2878 2879 /*------------------------------------------------------------------------* 2880 * xhci root HUB support 2881 *------------------------------------------------------------------------* 2882 * Simulate a hardware HUB by handling all the necessary requests. 2883 *------------------------------------------------------------------------*/ 2884 2885 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 2886 2887 static const 2888 struct usb_device_descriptor xhci_devd = 2889 { 2890 .bLength = sizeof(xhci_devd), 2891 .bDescriptorType = UDESC_DEVICE, /* type */ 2892 HSETW(.bcdUSB, 0x0300), /* USB version */ 2893 .bDeviceClass = UDCLASS_HUB, /* class */ 2894 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 2895 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 2896 .bMaxPacketSize = 9, /* max packet size */ 2897 HSETW(.idVendor, 0x0000), /* vendor */ 2898 HSETW(.idProduct, 0x0000), /* product */ 2899 HSETW(.bcdDevice, 0x0100), /* device version */ 2900 .iManufacturer = 1, 2901 .iProduct = 2, 2902 .iSerialNumber = 0, 2903 .bNumConfigurations = 1, /* # of configurations */ 2904 }; 2905 2906 static const 2907 struct xhci_bos_desc xhci_bosd = { 2908 .bosd = { 2909 .bLength = sizeof(xhci_bosd.bosd), 2910 .bDescriptorType = UDESC_BOS, 2911 HSETW(.wTotalLength, sizeof(xhci_bosd)), 2912 .bNumDeviceCaps = 3, 2913 }, 2914 .usb2extd = { 2915 .bLength = sizeof(xhci_bosd.usb2extd), 2916 .bDescriptorType = 1, 2917 .bDevCapabilityType = 2, 2918 .bmAttributes[0] = 2, 2919 }, 2920 .usbdcd = { 2921 .bLength = sizeof(xhci_bosd.usbdcd), 2922 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 2923 .bDevCapabilityType = 3, 2924 .bmAttributes = 0, /* XXX */ 2925 HSETW(.wSpeedsSupported, 0x000C), 2926 .bFunctionalitySupport = 8, 2927 .bU1DevExitLat = 255, /* dummy - not used */ 2928 .wU2DevExitLat = { 0x00, 0x08 }, 2929 }, 2930 .cidd = { 2931 .bLength = sizeof(xhci_bosd.cidd), 2932 .bDescriptorType = 1, 2933 .bDevCapabilityType = 4, 2934 .bReserved = 0, 2935 .bContainerID = 0, /* XXX */ 2936 }, 2937 }; 2938 2939 static const 2940 struct xhci_config_desc xhci_confd = { 2941 .confd = { 2942 .bLength = sizeof(xhci_confd.confd), 2943 .bDescriptorType = UDESC_CONFIG, 2944 .wTotalLength[0] = sizeof(xhci_confd), 2945 .bNumInterface = 1, 2946 .bConfigurationValue = 1, 2947 .iConfiguration = 0, 2948 .bmAttributes = UC_SELF_POWERED, 2949 .bMaxPower = 0 /* max power */ 2950 }, 2951 .ifcd = { 2952 .bLength = sizeof(xhci_confd.ifcd), 2953 .bDescriptorType = UDESC_INTERFACE, 2954 .bNumEndpoints = 1, 2955 .bInterfaceClass = UICLASS_HUB, 2956 .bInterfaceSubClass = UISUBCLASS_HUB, 2957 .bInterfaceProtocol = 0, 2958 }, 2959 .endpd = { 2960 .bLength = sizeof(xhci_confd.endpd), 2961 .bDescriptorType = UDESC_ENDPOINT, 2962 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 2963 .bmAttributes = UE_INTERRUPT, 2964 .wMaxPacketSize[0] = 2, /* max 15 ports */ 2965 .bInterval = 255, 2966 }, 2967 .endpcd = { 2968 .bLength = sizeof(xhci_confd.endpcd), 2969 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 2970 .bMaxBurst = 0, 2971 .bmAttributes = 0, 2972 }, 2973 }; 2974 2975 static const 2976 struct usb_hub_ss_descriptor xhci_hubd = { 2977 .bLength = sizeof(xhci_hubd), 2978 .bDescriptorType = UDESC_SS_HUB, 2979 }; 2980 2981 static usb_error_t 2982 xhci_roothub_exec(struct usb_device *udev, 2983 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2984 { 2985 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2986 const char *str_ptr; 2987 const void *ptr; 2988 uint32_t port; 2989 uint32_t v; 2990 uint16_t len; 2991 uint16_t i; 2992 uint16_t value; 2993 uint16_t index; 2994 uint8_t j; 2995 usb_error_t err; 2996 2997 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2998 2999 /* buffer reset */ 3000 ptr = (const void *)&sc->sc_hub_desc; 3001 len = 0; 3002 err = 0; 3003 3004 value = UGETW(req->wValue); 3005 index = UGETW(req->wIndex); 3006 3007 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3008 "wValue=0x%04x wIndex=0x%04x\n", 3009 req->bmRequestType, req->bRequest, 3010 UGETW(req->wLength), value, index); 3011 3012 #define C(x,y) ((x) | ((y) << 8)) 3013 switch (C(req->bRequest, req->bmRequestType)) { 3014 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3015 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3016 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3017 /* 3018 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3019 * for the integrated root hub. 3020 */ 3021 break; 3022 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3023 len = 1; 3024 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3025 break; 3026 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3027 switch (value >> 8) { 3028 case UDESC_DEVICE: 3029 if ((value & 0xff) != 0) { 3030 err = USB_ERR_IOERROR; 3031 goto done; 3032 } 3033 len = sizeof(xhci_devd); 3034 ptr = (const void *)&xhci_devd; 3035 break; 3036 3037 case UDESC_BOS: 3038 if ((value & 0xff) != 0) { 3039 err = USB_ERR_IOERROR; 3040 goto done; 3041 } 3042 len = sizeof(xhci_bosd); 3043 ptr = (const void *)&xhci_bosd; 3044 break; 3045 3046 case UDESC_CONFIG: 3047 if ((value & 0xff) != 0) { 3048 err = USB_ERR_IOERROR; 3049 goto done; 3050 } 3051 len = sizeof(xhci_confd); 3052 ptr = (const void *)&xhci_confd; 3053 break; 3054 3055 case UDESC_STRING: 3056 switch (value & 0xff) { 3057 case 0: /* Language table */ 3058 str_ptr = "\001"; 3059 break; 3060 3061 case 1: /* Vendor */ 3062 str_ptr = sc->sc_vendor; 3063 break; 3064 3065 case 2: /* Product */ 3066 str_ptr = "XHCI root HUB"; 3067 break; 3068 3069 default: 3070 str_ptr = ""; 3071 break; 3072 } 3073 3074 len = usb_make_str_desc( 3075 sc->sc_hub_desc.temp, 3076 sizeof(sc->sc_hub_desc.temp), 3077 str_ptr); 3078 break; 3079 3080 default: 3081 err = USB_ERR_IOERROR; 3082 goto done; 3083 } 3084 break; 3085 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3086 len = 1; 3087 sc->sc_hub_desc.temp[0] = 0; 3088 break; 3089 case C(UR_GET_STATUS, UT_READ_DEVICE): 3090 len = 2; 3091 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3092 break; 3093 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3094 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3095 len = 2; 3096 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3097 break; 3098 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3099 if (value >= XHCI_MAX_DEVICES) { 3100 err = USB_ERR_IOERROR; 3101 goto done; 3102 } 3103 break; 3104 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3105 if (value != 0 && value != 1) { 3106 err = USB_ERR_IOERROR; 3107 goto done; 3108 } 3109 sc->sc_conf = value; 3110 break; 3111 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3112 break; 3113 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3114 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3115 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3116 err = USB_ERR_IOERROR; 3117 goto done; 3118 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3119 break; 3120 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3121 break; 3122 /* Hub requests */ 3123 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3124 break; 3125 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3126 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3127 3128 if ((index < 1) || 3129 (index > sc->sc_noport)) { 3130 err = USB_ERR_IOERROR; 3131 goto done; 3132 } 3133 port = XHCI_PORTSC(index); 3134 3135 v = XREAD4(sc, oper, port); 3136 i = XHCI_PS_PLS_GET(v); 3137 v &= ~XHCI_PS_CLEAR; 3138 3139 switch (value) { 3140 case UHF_C_BH_PORT_RESET: 3141 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3142 break; 3143 case UHF_C_PORT_CONFIG_ERROR: 3144 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3145 break; 3146 case UHF_C_PORT_SUSPEND: 3147 case UHF_C_PORT_LINK_STATE: 3148 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3149 break; 3150 case UHF_C_PORT_CONNECTION: 3151 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3152 break; 3153 case UHF_C_PORT_ENABLE: 3154 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3155 break; 3156 case UHF_C_PORT_OVER_CURRENT: 3157 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3158 break; 3159 case UHF_C_PORT_RESET: 3160 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3161 break; 3162 case UHF_PORT_ENABLE: 3163 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3164 break; 3165 case UHF_PORT_POWER: 3166 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3167 break; 3168 case UHF_PORT_INDICATOR: 3169 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3170 break; 3171 case UHF_PORT_SUSPEND: 3172 3173 /* U3 -> U15 */ 3174 if (i == 3) { 3175 XWRITE4(sc, oper, port, v | 3176 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3177 } 3178 3179 /* wait 20ms for resume sequence to complete */ 3180 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3181 3182 /* U0 */ 3183 XWRITE4(sc, oper, port, v | 3184 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3185 break; 3186 default: 3187 err = USB_ERR_IOERROR; 3188 goto done; 3189 } 3190 break; 3191 3192 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3193 if ((value & 0xff) != 0) { 3194 err = USB_ERR_IOERROR; 3195 goto done; 3196 } 3197 3198 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3199 3200 sc->sc_hub_desc.hubd = xhci_hubd; 3201 3202 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3203 3204 if (XHCI_HCS0_PPC(v)) 3205 i = UHD_PWR_INDIVIDUAL; 3206 else 3207 i = UHD_PWR_GANGED; 3208 3209 if (XHCI_HCS0_PIND(v)) 3210 i |= UHD_PORT_IND; 3211 3212 i |= UHD_OC_INDIVIDUAL; 3213 3214 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3215 3216 /* see XHCI section 5.4.9: */ 3217 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3218 3219 for (j = 1; j <= sc->sc_noport; j++) { 3220 3221 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3222 if (v & XHCI_PS_DR) { 3223 sc->sc_hub_desc.hubd. 3224 DeviceRemovable[j / 8] |= 1U << (j % 8); 3225 } 3226 } 3227 len = sc->sc_hub_desc.hubd.bLength; 3228 break; 3229 3230 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3231 len = 16; 3232 memset(sc->sc_hub_desc.temp, 0, 16); 3233 break; 3234 3235 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3236 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3237 3238 if ((index < 1) || 3239 (index > sc->sc_noport)) { 3240 err = USB_ERR_IOERROR; 3241 goto done; 3242 } 3243 3244 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3245 3246 DPRINTFN(9, "port status=0x%08x\n", v); 3247 3248 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3249 3250 switch (XHCI_PS_SPEED_GET(v)) { 3251 case 3: 3252 i |= UPS_HIGH_SPEED; 3253 break; 3254 case 2: 3255 i |= UPS_LOW_SPEED; 3256 break; 3257 case 1: 3258 /* FULL speed */ 3259 break; 3260 default: 3261 i |= UPS_OTHER_SPEED; 3262 break; 3263 } 3264 3265 if (v & XHCI_PS_CCS) 3266 i |= UPS_CURRENT_CONNECT_STATUS; 3267 if (v & XHCI_PS_PED) 3268 i |= UPS_PORT_ENABLED; 3269 if (v & XHCI_PS_OCA) 3270 i |= UPS_OVERCURRENT_INDICATOR; 3271 if (v & XHCI_PS_PR) 3272 i |= UPS_RESET; 3273 if (v & XHCI_PS_PP) { 3274 /* 3275 * The USB 3.0 RH is using the 3276 * USB 2.0's power bit 3277 */ 3278 i |= UPS_PORT_POWER; 3279 } 3280 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3281 3282 i = 0; 3283 if (v & XHCI_PS_CSC) 3284 i |= UPS_C_CONNECT_STATUS; 3285 if (v & XHCI_PS_PEC) 3286 i |= UPS_C_PORT_ENABLED; 3287 if (v & XHCI_PS_OCC) 3288 i |= UPS_C_OVERCURRENT_INDICATOR; 3289 if (v & XHCI_PS_WRC) 3290 i |= UPS_C_BH_PORT_RESET; 3291 if (v & XHCI_PS_PRC) 3292 i |= UPS_C_PORT_RESET; 3293 if (v & XHCI_PS_PLC) 3294 i |= UPS_C_PORT_LINK_STATE; 3295 if (v & XHCI_PS_CEC) 3296 i |= UPS_C_PORT_CONFIG_ERROR; 3297 3298 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3299 len = sizeof(sc->sc_hub_desc.ps); 3300 break; 3301 3302 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3303 err = USB_ERR_IOERROR; 3304 goto done; 3305 3306 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3307 break; 3308 3309 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3310 3311 i = index >> 8; 3312 index &= 0x00FF; 3313 3314 if ((index < 1) || 3315 (index > sc->sc_noport)) { 3316 err = USB_ERR_IOERROR; 3317 goto done; 3318 } 3319 3320 port = XHCI_PORTSC(index); 3321 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3322 3323 switch (value) { 3324 case UHF_PORT_U1_TIMEOUT: 3325 if (XHCI_PS_SPEED_GET(v) != 4) { 3326 err = USB_ERR_IOERROR; 3327 goto done; 3328 } 3329 port = XHCI_PORTPMSC(index); 3330 v = XREAD4(sc, oper, port); 3331 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3332 v |= XHCI_PM3_U1TO_SET(i); 3333 XWRITE4(sc, oper, port, v); 3334 break; 3335 case UHF_PORT_U2_TIMEOUT: 3336 if (XHCI_PS_SPEED_GET(v) != 4) { 3337 err = USB_ERR_IOERROR; 3338 goto done; 3339 } 3340 port = XHCI_PORTPMSC(index); 3341 v = XREAD4(sc, oper, port); 3342 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3343 v |= XHCI_PM3_U2TO_SET(i); 3344 XWRITE4(sc, oper, port, v); 3345 break; 3346 case UHF_BH_PORT_RESET: 3347 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3348 break; 3349 case UHF_PORT_LINK_STATE: 3350 XWRITE4(sc, oper, port, v | 3351 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3352 /* 4ms settle time */ 3353 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3354 break; 3355 case UHF_PORT_ENABLE: 3356 DPRINTFN(3, "set port enable %d\n", index); 3357 break; 3358 case UHF_PORT_SUSPEND: 3359 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3360 j = XHCI_PS_SPEED_GET(v); 3361 if ((j < 1) || (j > 3)) { 3362 /* non-supported speed */ 3363 err = USB_ERR_IOERROR; 3364 goto done; 3365 } 3366 XWRITE4(sc, oper, port, v | 3367 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3368 break; 3369 case UHF_PORT_RESET: 3370 DPRINTFN(6, "reset port %d\n", index); 3371 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3372 break; 3373 case UHF_PORT_POWER: 3374 DPRINTFN(3, "set port power %d\n", index); 3375 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3376 break; 3377 case UHF_PORT_TEST: 3378 DPRINTFN(3, "set port test %d\n", index); 3379 break; 3380 case UHF_PORT_INDICATOR: 3381 DPRINTFN(3, "set port indicator %d\n", index); 3382 3383 v &= ~XHCI_PS_PIC_SET(3); 3384 v |= XHCI_PS_PIC_SET(1); 3385 3386 XWRITE4(sc, oper, port, v); 3387 break; 3388 default: 3389 err = USB_ERR_IOERROR; 3390 goto done; 3391 } 3392 break; 3393 3394 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3395 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3396 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3397 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3398 break; 3399 default: 3400 err = USB_ERR_IOERROR; 3401 goto done; 3402 } 3403 done: 3404 *plength = len; 3405 *pptr = ptr; 3406 return (err); 3407 } 3408 3409 static void 3410 xhci_xfer_setup(struct usb_setup_params *parm) 3411 { 3412 struct usb_page_search page_info; 3413 struct usb_page_cache *pc; 3414 struct xhci_softc *sc; 3415 struct usb_xfer *xfer; 3416 void *last_obj; 3417 uint32_t ntd; 3418 uint32_t n; 3419 3420 sc = XHCI_BUS2SC(parm->udev->bus); 3421 xfer = parm->curr_xfer; 3422 3423 /* 3424 * The proof for the "ntd" formula is illustrated like this: 3425 * 3426 * +------------------------------------+ 3427 * | | 3428 * | |remainder -> | 3429 * | +-----+---+ | 3430 * | | xxx | x | frm 0 | 3431 * | +-----+---++ | 3432 * | | xxx | xx | frm 1 | 3433 * | +-----+----+ | 3434 * | ... | 3435 * +------------------------------------+ 3436 * 3437 * "xxx" means a completely full USB transfer descriptor 3438 * 3439 * "x" and "xx" means a short USB packet 3440 * 3441 * For the remainder of an USB transfer modulo 3442 * "max_data_length" we need two USB transfer descriptors. 3443 * One to transfer the remaining data and one to finalise with 3444 * a zero length packet in case the "force_short_xfer" flag is 3445 * set. We only need two USB transfer descriptors in the case 3446 * where the transfer length of the first one is a factor of 3447 * "max_frame_size". The rest of the needed USB transfer 3448 * descriptors is given by the buffer size divided by the 3449 * maximum data payload. 3450 */ 3451 parm->hc_max_packet_size = 0x400; 3452 parm->hc_max_packet_count = 16 * 3; 3453 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3454 3455 xfer->flags_int.bdma_enable = 1; 3456 3457 usbd_transfer_setup_sub(parm); 3458 3459 if (xfer->flags_int.isochronous_xfr) { 3460 ntd = ((1 * xfer->nframes) 3461 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3462 } else if (xfer->flags_int.control_xfr) { 3463 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3464 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3465 } else { 3466 ntd = ((2 * xfer->nframes) 3467 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3468 } 3469 3470 alloc_dma_set: 3471 3472 if (parm->err) 3473 return; 3474 3475 /* 3476 * Allocate queue heads and transfer descriptors 3477 */ 3478 last_obj = NULL; 3479 3480 if (usbd_transfer_setup_sub_malloc( 3481 parm, &pc, sizeof(struct xhci_td), 3482 XHCI_TD_ALIGN, ntd)) { 3483 parm->err = USB_ERR_NOMEM; 3484 return; 3485 } 3486 if (parm->buf) { 3487 for (n = 0; n != ntd; n++) { 3488 struct xhci_td *td; 3489 3490 usbd_get_page(pc + n, 0, &page_info); 3491 3492 td = page_info.buffer; 3493 3494 /* init TD */ 3495 td->td_self = page_info.physaddr; 3496 td->obj_next = last_obj; 3497 td->page_cache = pc + n; 3498 3499 last_obj = td; 3500 3501 usb_pc_cpu_flush(pc + n); 3502 } 3503 } 3504 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3505 3506 if (!xfer->flags_int.curr_dma_set) { 3507 xfer->flags_int.curr_dma_set = 1; 3508 goto alloc_dma_set; 3509 } 3510 } 3511 3512 static usb_error_t 3513 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3514 { 3515 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3516 struct usb_page_search buf_inp; 3517 struct usb_device *udev; 3518 struct xhci_endpoint_ext *pepext; 3519 struct usb_endpoint_descriptor *edesc; 3520 struct usb_page_cache *pcinp; 3521 usb_error_t err; 3522 usb_stream_t stream_id; 3523 uint8_t index; 3524 uint8_t epno; 3525 3526 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3527 xfer->endpoint->edesc); 3528 3529 udev = xfer->xroot->udev; 3530 index = udev->controller_slot_id; 3531 3532 pcinp = &sc->sc_hw.devs[index].input_pc; 3533 3534 usbd_get_page(pcinp, 0, &buf_inp); 3535 3536 edesc = xfer->endpoint->edesc; 3537 3538 epno = edesc->bEndpointAddress; 3539 stream_id = xfer->stream_id; 3540 3541 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3542 epno |= UE_DIR_IN; 3543 3544 epno = XHCI_EPNO2EPID(epno); 3545 3546 if (epno == 0) 3547 return (USB_ERR_NO_PIPE); /* invalid */ 3548 3549 XHCI_CMD_LOCK(sc); 3550 3551 /* configure endpoint */ 3552 3553 err = xhci_configure_endpoint_by_xfer(xfer); 3554 3555 if (err != 0) { 3556 XHCI_CMD_UNLOCK(sc); 3557 return (err); 3558 } 3559 3560 /* 3561 * Get the endpoint into the stopped state according to the 3562 * endpoint context state diagram in the XHCI specification: 3563 */ 3564 3565 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3566 3567 if (err != 0) 3568 DPRINTF("Could not stop endpoint %u\n", epno); 3569 3570 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3571 3572 if (err != 0) 3573 DPRINTF("Could not reset endpoint %u\n", epno); 3574 3575 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3576 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3577 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3578 stream_id, epno, index); 3579 3580 if (err != 0) 3581 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3582 3583 /* 3584 * Get the endpoint into the running state according to the 3585 * endpoint context state diagram in the XHCI specification: 3586 */ 3587 3588 xhci_configure_mask(udev, 1U << epno, 0); 3589 3590 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3591 3592 if (err != 0) 3593 DPRINTF("Could not configure endpoint %u\n", epno); 3594 3595 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3596 3597 if (err != 0) 3598 DPRINTF("Could not configure endpoint %u\n", epno); 3599 3600 XHCI_CMD_UNLOCK(sc); 3601 3602 return (0); 3603 } 3604 3605 static void 3606 xhci_xfer_unsetup(struct usb_xfer *xfer) 3607 { 3608 return; 3609 } 3610 3611 static void 3612 xhci_start_dma_delay(struct usb_xfer *xfer) 3613 { 3614 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3615 3616 /* put transfer on interrupt queue (again) */ 3617 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3618 3619 (void)usb_proc_msignal(&sc->sc_config_proc, 3620 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3621 } 3622 3623 static void 3624 xhci_configure_msg(struct usb_proc_msg *pm) 3625 { 3626 struct xhci_softc *sc; 3627 struct xhci_endpoint_ext *pepext; 3628 struct usb_xfer *xfer; 3629 3630 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3631 3632 restart: 3633 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3634 3635 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3636 xfer->endpoint->edesc); 3637 3638 if ((pepext->trb_halted != 0) || 3639 (pepext->trb_running == 0)) { 3640 3641 uint8_t i; 3642 3643 /* clear halted and running */ 3644 pepext->trb_halted = 0; 3645 pepext->trb_running = 0; 3646 3647 /* nuke remaining buffered transfers */ 3648 3649 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 3650 /* 3651 * NOTE: We need to use the timeout 3652 * error code here else existing 3653 * isochronous clients can get 3654 * confused: 3655 */ 3656 if (pepext->xfer[i] != NULL) { 3657 xhci_device_done(pepext->xfer[i], 3658 USB_ERR_TIMEOUT); 3659 } 3660 } 3661 3662 /* 3663 * NOTE: The USB transfer cannot vanish in 3664 * this state! 3665 */ 3666 3667 USB_BUS_UNLOCK(&sc->sc_bus); 3668 3669 xhci_configure_reset_endpoint(xfer); 3670 3671 USB_BUS_LOCK(&sc->sc_bus); 3672 3673 /* check if halted is still cleared */ 3674 if (pepext->trb_halted == 0) { 3675 pepext->trb_running = 1; 3676 memset(pepext->trb_index, 0, 3677 sizeof(pepext->trb_index)); 3678 } 3679 goto restart; 3680 } 3681 3682 if (xfer->flags_int.did_dma_delay) { 3683 3684 /* remove transfer from interrupt queue (again) */ 3685 usbd_transfer_dequeue(xfer); 3686 3687 /* we are finally done */ 3688 usb_dma_delay_done_cb(xfer); 3689 3690 /* queue changed - restart */ 3691 goto restart; 3692 } 3693 } 3694 3695 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3696 3697 /* try to insert xfer on HW queue */ 3698 xhci_transfer_insert(xfer); 3699 3700 /* try to multi buffer */ 3701 xhci_device_generic_multi_enter(xfer->endpoint, 3702 xfer->stream_id, NULL); 3703 } 3704 } 3705 3706 static void 3707 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3708 struct usb_endpoint *ep) 3709 { 3710 struct xhci_endpoint_ext *pepext; 3711 3712 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3713 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3714 3715 if (udev->parent_hub == NULL) { 3716 /* root HUB has special endpoint handling */ 3717 return; 3718 } 3719 3720 ep->methods = &xhci_device_generic_methods; 3721 3722 pepext = xhci_get_endpoint_ext(udev, edesc); 3723 3724 USB_BUS_LOCK(udev->bus); 3725 pepext->trb_halted = 1; 3726 pepext->trb_running = 0; 3727 USB_BUS_UNLOCK(udev->bus); 3728 } 3729 3730 static void 3731 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3732 { 3733 3734 } 3735 3736 static void 3737 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3738 { 3739 struct xhci_endpoint_ext *pepext; 3740 3741 DPRINTF("\n"); 3742 3743 if (udev->flags.usb_mode != USB_MODE_HOST) { 3744 /* not supported */ 3745 return; 3746 } 3747 if (udev->parent_hub == NULL) { 3748 /* root HUB has special endpoint handling */ 3749 return; 3750 } 3751 3752 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3753 3754 USB_BUS_LOCK(udev->bus); 3755 pepext->trb_halted = 1; 3756 pepext->trb_running = 0; 3757 USB_BUS_UNLOCK(udev->bus); 3758 } 3759 3760 static usb_error_t 3761 xhci_device_init(struct usb_device *udev) 3762 { 3763 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3764 usb_error_t err; 3765 uint8_t temp; 3766 3767 /* no init for root HUB */ 3768 if (udev->parent_hub == NULL) 3769 return (0); 3770 3771 XHCI_CMD_LOCK(sc); 3772 3773 /* set invalid default */ 3774 3775 udev->controller_slot_id = sc->sc_noslot + 1; 3776 3777 /* try to get a new slot ID from the XHCI */ 3778 3779 err = xhci_cmd_enable_slot(sc, &temp); 3780 3781 if (err) { 3782 XHCI_CMD_UNLOCK(sc); 3783 return (err); 3784 } 3785 3786 if (temp > sc->sc_noslot) { 3787 XHCI_CMD_UNLOCK(sc); 3788 return (USB_ERR_BAD_ADDRESS); 3789 } 3790 3791 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 3792 DPRINTF("slot %u already allocated.\n", temp); 3793 XHCI_CMD_UNLOCK(sc); 3794 return (USB_ERR_BAD_ADDRESS); 3795 } 3796 3797 /* store slot ID for later reference */ 3798 3799 udev->controller_slot_id = temp; 3800 3801 /* reset data structure */ 3802 3803 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 3804 3805 /* set mark slot allocated */ 3806 3807 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 3808 3809 err = xhci_alloc_device_ext(udev); 3810 3811 XHCI_CMD_UNLOCK(sc); 3812 3813 /* get device into default state */ 3814 3815 if (err == 0) 3816 err = xhci_set_address(udev, NULL, 0); 3817 3818 return (err); 3819 } 3820 3821 static void 3822 xhci_device_uninit(struct usb_device *udev) 3823 { 3824 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3825 uint8_t index; 3826 3827 /* no init for root HUB */ 3828 if (udev->parent_hub == NULL) 3829 return; 3830 3831 XHCI_CMD_LOCK(sc); 3832 3833 index = udev->controller_slot_id; 3834 3835 if (index <= sc->sc_noslot) { 3836 xhci_cmd_disable_slot(sc, index); 3837 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 3838 3839 /* free device extension */ 3840 xhci_free_device_ext(udev); 3841 } 3842 3843 XHCI_CMD_UNLOCK(sc); 3844 } 3845 3846 static void 3847 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3848 { 3849 /* 3850 * Wait until the hardware has finished any possible use of 3851 * the transfer descriptor(s) 3852 */ 3853 *pus = 2048; /* microseconds */ 3854 } 3855 3856 static void 3857 xhci_device_resume(struct usb_device *udev) 3858 { 3859 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3860 uint8_t index; 3861 uint8_t n; 3862 3863 DPRINTF("\n"); 3864 3865 /* check for root HUB */ 3866 if (udev->parent_hub == NULL) 3867 return; 3868 3869 index = udev->controller_slot_id; 3870 3871 XHCI_CMD_LOCK(sc); 3872 3873 /* blindly resume all endpoints */ 3874 3875 USB_BUS_LOCK(udev->bus); 3876 3877 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) 3878 XWRITE4(sc, door, XHCI_DOORBELL(index), n | XHCI_DB_SID_SET(0)); 3879 3880 USB_BUS_UNLOCK(udev->bus); 3881 3882 XHCI_CMD_UNLOCK(sc); 3883 } 3884 3885 static void 3886 xhci_device_suspend(struct usb_device *udev) 3887 { 3888 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3889 uint8_t index; 3890 uint8_t n; 3891 usb_error_t err; 3892 3893 DPRINTF("\n"); 3894 3895 /* check for root HUB */ 3896 if (udev->parent_hub == NULL) 3897 return; 3898 3899 index = udev->controller_slot_id; 3900 3901 XHCI_CMD_LOCK(sc); 3902 3903 /* blindly suspend all endpoints */ 3904 3905 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3906 err = xhci_cmd_stop_ep(sc, 1, n, index); 3907 if (err != 0) { 3908 DPRINTF("Failed to suspend endpoint " 3909 "%u on slot %u (ignored).\n", n, index); 3910 } 3911 } 3912 3913 XHCI_CMD_UNLOCK(sc); 3914 } 3915 3916 static void 3917 xhci_set_hw_power(struct usb_bus *bus) 3918 { 3919 DPRINTF("\n"); 3920 } 3921 3922 static void 3923 xhci_device_state_change(struct usb_device *udev) 3924 { 3925 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3926 struct usb_page_search buf_inp; 3927 usb_error_t err; 3928 uint8_t index; 3929 3930 /* check for root HUB */ 3931 if (udev->parent_hub == NULL) 3932 return; 3933 3934 index = udev->controller_slot_id; 3935 3936 DPRINTF("\n"); 3937 3938 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 3939 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 3940 &sc->sc_hw.devs[index].tt); 3941 if (err != 0) 3942 sc->sc_hw.devs[index].nports = 0; 3943 } 3944 3945 XHCI_CMD_LOCK(sc); 3946 3947 switch (usb_get_device_state(udev)) { 3948 case USB_STATE_POWERED: 3949 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 3950 break; 3951 3952 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 3953 3954 err = xhci_cmd_reset_dev(sc, index); 3955 3956 if (err != 0) { 3957 DPRINTF("Device reset failed " 3958 "for slot %u.\n", index); 3959 } 3960 break; 3961 3962 case USB_STATE_ADDRESSED: 3963 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 3964 break; 3965 3966 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 3967 3968 err = xhci_cmd_configure_ep(sc, 0, 1, index); 3969 3970 if (err) { 3971 DPRINTF("Failed to deconfigure " 3972 "slot %u.\n", index); 3973 } 3974 break; 3975 3976 case USB_STATE_CONFIGURED: 3977 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 3978 break; 3979 3980 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 3981 3982 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 3983 3984 xhci_configure_mask(udev, 1, 0); 3985 3986 err = xhci_configure_device(udev); 3987 if (err != 0) { 3988 DPRINTF("Could not configure device " 3989 "at slot %u.\n", index); 3990 } 3991 3992 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3993 if (err != 0) { 3994 DPRINTF("Could not evaluate device " 3995 "context at slot %u.\n", index); 3996 } 3997 break; 3998 3999 default: 4000 break; 4001 } 4002 XHCI_CMD_UNLOCK(sc); 4003 } 4004 4005 static usb_error_t 4006 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4007 uint8_t ep_mode) 4008 { 4009 switch (ep_mode) { 4010 case USB_EP_MODE_DEFAULT: 4011 return (0); 4012 case USB_EP_MODE_STREAMS: 4013 if ((ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4014 udev->speed != USB_SPEED_SUPER) 4015 return (USB_ERR_INVAL); 4016 return (0); 4017 default: 4018 return (USB_ERR_INVAL); 4019 } 4020 } 4021 4022 struct usb_bus_methods xhci_bus_methods = { 4023 .endpoint_init = xhci_ep_init, 4024 .endpoint_uninit = xhci_ep_uninit, 4025 .xfer_setup = xhci_xfer_setup, 4026 .xfer_unsetup = xhci_xfer_unsetup, 4027 .get_dma_delay = xhci_get_dma_delay, 4028 .device_init = xhci_device_init, 4029 .device_uninit = xhci_device_uninit, 4030 .device_resume = xhci_device_resume, 4031 .device_suspend = xhci_device_suspend, 4032 .set_hw_power = xhci_set_hw_power, 4033 .roothub_exec = xhci_roothub_exec, 4034 .xfer_poll = xhci_do_poll, 4035 .start_dma_delay = xhci_start_dma_delay, 4036 .set_address = xhci_set_address, 4037 .clear_stall = xhci_ep_clear_stall, 4038 .device_state_change = xhci_device_state_change, 4039 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4040 .set_endpoint_mode = xhci_set_endpoint_mode, 4041 }; 4042