1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36 /* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43 #ifdef USB_GLOBAL_INCLUDE_FILE 44 #include USB_GLOBAL_INCLUDE_FILE 45 #else 46 #include <sys/stdint.h> 47 #include <sys/stddef.h> 48 #include <sys/param.h> 49 #include <sys/queue.h> 50 #include <sys/types.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/bus.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/condvar.h> 58 #include <sys/sysctl.h> 59 #include <sys/sx.h> 60 #include <sys/unistd.h> 61 #include <sys/callout.h> 62 #include <sys/malloc.h> 63 #include <sys/priv.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 68 #define USB_DEBUG_VAR xhcidebug 69 70 #include <dev/usb/usb_core.h> 71 #include <dev/usb/usb_debug.h> 72 #include <dev/usb/usb_busdma.h> 73 #include <dev/usb/usb_process.h> 74 #include <dev/usb/usb_transfer.h> 75 #include <dev/usb/usb_device.h> 76 #include <dev/usb/usb_hub.h> 77 #include <dev/usb/usb_util.h> 78 79 #include <dev/usb/usb_controller.h> 80 #include <dev/usb/usb_bus.h> 81 #endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83 #include <dev/usb/controller/xhci.h> 84 #include <dev/usb/controller/xhcireg.h> 85 86 #define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 92 static int xhcistreams; 93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN, 94 &xhcistreams, 0, "Set to enable streams mode support"); 95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams); 96 97 #ifdef USB_DEBUG 98 static int xhcidebug; 99 static int xhciroute; 100 static int xhcipolling; 101 102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 103 &xhcidebug, 0, "Debug level"); 104 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN, 106 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 107 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN, 109 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller"); 110 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling); 111 #else 112 #define xhciroute 0 113 #endif 114 115 #define XHCI_INTR_ENDPT 1 116 117 struct xhci_std_temp { 118 struct xhci_softc *sc; 119 struct usb_page_cache *pc; 120 struct xhci_td *td; 121 struct xhci_td *td_next; 122 uint32_t len; 123 uint32_t offset; 124 uint32_t max_packet_size; 125 uint32_t average; 126 uint16_t isoc_delta; 127 uint16_t isoc_frame; 128 uint8_t shortpkt; 129 uint8_t multishort; 130 uint8_t last_frame; 131 uint8_t trb_type; 132 uint8_t direction; 133 uint8_t tbc; 134 uint8_t tlbpc; 135 uint8_t step_td; 136 uint8_t do_isoc_sync; 137 }; 138 139 static void xhci_do_poll(struct usb_bus *); 140 static void xhci_device_done(struct usb_xfer *, usb_error_t); 141 static void xhci_root_intr(struct xhci_softc *); 142 static void xhci_free_device_ext(struct usb_device *); 143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 144 struct usb_endpoint_descriptor *); 145 static usb_proc_callback_t xhci_configure_msg; 146 static usb_error_t xhci_configure_device(struct usb_device *); 147 static usb_error_t xhci_configure_endpoint(struct usb_device *, 148 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 149 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 150 uint8_t); 151 static usb_error_t xhci_configure_mask(struct usb_device *, 152 uint32_t, uint8_t); 153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 154 uint64_t, uint8_t); 155 static void xhci_endpoint_doorbell(struct usb_xfer *); 156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 159 #ifdef USB_DEBUG 160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 161 #endif 162 163 static const struct usb_bus_methods xhci_bus_methods; 164 165 #ifdef USB_DEBUG 166 static void 167 xhci_dump_trb(struct xhci_trb *trb) 168 { 169 DPRINTFN(5, "trb = %p\n", trb); 170 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 171 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 172 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 173 } 174 175 static void 176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 177 { 178 DPRINTFN(5, "pep = %p\n", pep); 179 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 180 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 181 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 182 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 183 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 184 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 185 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 186 } 187 188 static void 189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 190 { 191 DPRINTFN(5, "psl = %p\n", psl); 192 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 193 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 194 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 195 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 196 } 197 #endif 198 199 uint8_t 200 xhci_use_polling(void) 201 { 202 #ifdef USB_DEBUG 203 return (xhcipolling != 0); 204 #else 205 return (0); 206 #endif 207 } 208 209 static void 210 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 211 { 212 struct xhci_softc *sc = XHCI_BUS2SC(bus); 213 uint8_t i; 214 215 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 216 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 217 218 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 219 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 220 221 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 222 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 223 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 224 } 225 } 226 227 static void 228 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 229 { 230 if (sc->sc_ctx_is_64_byte) { 231 uint32_t offset; 232 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 233 /* all contexts are initially 32-bytes */ 234 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 235 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 236 } 237 *ptr = htole32(val); 238 } 239 240 static uint32_t 241 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 242 { 243 if (sc->sc_ctx_is_64_byte) { 244 uint32_t offset; 245 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 246 /* all contexts are initially 32-bytes */ 247 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 248 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 249 } 250 return (le32toh(*ptr)); 251 } 252 253 static void 254 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 255 { 256 if (sc->sc_ctx_is_64_byte) { 257 uint32_t offset; 258 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 259 /* all contexts are initially 32-bytes */ 260 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 261 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 262 } 263 *ptr = htole64(val); 264 } 265 266 #ifdef USB_DEBUG 267 static uint64_t 268 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 269 { 270 if (sc->sc_ctx_is_64_byte) { 271 uint32_t offset; 272 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 273 /* all contexts are initially 32-bytes */ 274 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 275 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 276 } 277 return (le64toh(*ptr)); 278 } 279 #endif 280 281 static int 282 xhci_reset_command_queue_locked(struct xhci_softc *sc) 283 { 284 struct usb_page_search buf_res; 285 struct xhci_hw_root *phwr; 286 uint64_t addr; 287 uint32_t temp; 288 289 DPRINTF("\n"); 290 291 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 292 if (temp & XHCI_CRCR_LO_CRR) { 293 DPRINTF("Command ring running\n"); 294 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 295 296 /* 297 * Try to abort the last command as per section 298 * 4.6.1.2 "Aborting a Command" of the XHCI 299 * specification: 300 */ 301 302 /* stop and cancel */ 303 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 304 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 305 306 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 307 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 308 309 /* wait 250ms */ 310 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 311 312 /* check if command ring is still running */ 313 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 314 if (temp & XHCI_CRCR_LO_CRR) { 315 DPRINTF("Comand ring still running\n"); 316 return (USB_ERR_IOERROR); 317 } 318 } 319 320 /* reset command ring */ 321 sc->sc_command_ccs = 1; 322 sc->sc_command_idx = 0; 323 324 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 325 326 /* setup command ring control base address */ 327 addr = buf_res.physaddr; 328 phwr = buf_res.buffer; 329 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 330 331 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 332 333 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 334 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 335 336 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 337 338 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 339 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 340 341 return (0); 342 } 343 344 usb_error_t 345 xhci_start_controller(struct xhci_softc *sc) 346 { 347 struct usb_page_search buf_res; 348 struct xhci_hw_root *phwr; 349 struct xhci_dev_ctx_addr *pdctxa; 350 uint64_t addr; 351 uint32_t temp; 352 uint16_t i; 353 354 DPRINTF("\n"); 355 356 sc->sc_capa_off = 0; 357 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 358 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 359 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 360 361 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 362 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 363 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 364 365 sc->sc_event_ccs = 1; 366 sc->sc_event_idx = 0; 367 sc->sc_command_ccs = 1; 368 sc->sc_command_idx = 0; 369 370 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 371 372 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 373 374 DPRINTF("HCS0 = 0x%08x\n", temp); 375 376 if (XHCI_HCS0_CSZ(temp)) { 377 sc->sc_ctx_is_64_byte = 1; 378 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 379 } else { 380 sc->sc_ctx_is_64_byte = 0; 381 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 382 } 383 384 /* Reset controller */ 385 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 386 387 for (i = 0; i != 100; i++) { 388 usb_pause_mtx(NULL, hz / 100); 389 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 390 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 391 if (!temp) 392 break; 393 } 394 395 if (temp) { 396 device_printf(sc->sc_bus.parent, "Controller " 397 "reset timeout.\n"); 398 return (USB_ERR_IOERROR); 399 } 400 401 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 402 device_printf(sc->sc_bus.parent, "Controller does " 403 "not support 4K page size.\n"); 404 return (USB_ERR_IOERROR); 405 } 406 407 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 408 409 i = XHCI_HCS1_N_PORTS(temp); 410 411 if (i == 0) { 412 device_printf(sc->sc_bus.parent, "Invalid number " 413 "of ports: %u\n", i); 414 return (USB_ERR_IOERROR); 415 } 416 417 sc->sc_noport = i; 418 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 419 420 if (sc->sc_noslot > XHCI_MAX_DEVICES) 421 sc->sc_noslot = XHCI_MAX_DEVICES; 422 423 /* setup number of device slots */ 424 425 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 426 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 427 428 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 429 430 DPRINTF("Max slots: %u\n", sc->sc_noslot); 431 432 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 433 434 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 435 436 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 437 device_printf(sc->sc_bus.parent, "XHCI request " 438 "too many scratchpads\n"); 439 return (USB_ERR_NOMEM); 440 } 441 442 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 443 444 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 445 446 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 447 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 448 449 temp = XREAD4(sc, oper, XHCI_USBSTS); 450 451 /* clear interrupts */ 452 XWRITE4(sc, oper, XHCI_USBSTS, temp); 453 /* disable all device notifications */ 454 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 455 456 /* setup device context base address */ 457 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 458 pdctxa = buf_res.buffer; 459 memset(pdctxa, 0, sizeof(*pdctxa)); 460 461 addr = buf_res.physaddr; 462 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 463 464 /* slot 0 points to the table of scratchpad pointers */ 465 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 466 467 for (i = 0; i != sc->sc_noscratch; i++) { 468 struct usb_page_search buf_scp; 469 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 470 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 471 } 472 473 addr = buf_res.physaddr; 474 475 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 476 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 477 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 478 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 479 480 /* Setup event table size */ 481 482 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 483 484 DPRINTF("HCS2=0x%08x\n", temp); 485 486 temp = XHCI_HCS2_ERST_MAX(temp); 487 temp = 1U << temp; 488 if (temp > XHCI_MAX_RSEG) 489 temp = XHCI_MAX_RSEG; 490 491 sc->sc_erst_max = temp; 492 493 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 494 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 495 496 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 497 498 /* Check if we should use the default IMOD value */ 499 if (sc->sc_imod_default == 0) 500 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 501 502 /* Setup interrupt rate */ 503 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 504 505 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 506 507 phwr = buf_res.buffer; 508 addr = buf_res.physaddr; 509 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 510 511 /* reset hardware root structure */ 512 memset(phwr, 0, sizeof(*phwr)); 513 514 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 515 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 516 517 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 518 519 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 520 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 521 522 addr = (uint64_t)buf_res.physaddr; 523 524 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 525 526 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 527 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 528 529 /* Setup interrupter registers */ 530 531 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 532 temp |= XHCI_IMAN_INTR_ENA; 533 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 534 535 /* setup command ring control base address */ 536 addr = buf_res.physaddr; 537 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 538 539 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 540 541 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 542 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 543 544 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 545 546 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 547 548 /* Go! */ 549 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 550 XHCI_CMD_INTE | XHCI_CMD_HSEE); 551 552 for (i = 0; i != 100; i++) { 553 usb_pause_mtx(NULL, hz / 100); 554 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 555 if (!temp) 556 break; 557 } 558 if (temp) { 559 XWRITE4(sc, oper, XHCI_USBCMD, 0); 560 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 561 return (USB_ERR_IOERROR); 562 } 563 564 /* catch any lost interrupts */ 565 xhci_do_poll(&sc->sc_bus); 566 567 if (sc->sc_port_route != NULL) { 568 /* Route all ports to the XHCI by default */ 569 sc->sc_port_route(sc->sc_bus.parent, 570 ~xhciroute, xhciroute); 571 } 572 return (0); 573 } 574 575 usb_error_t 576 xhci_halt_controller(struct xhci_softc *sc) 577 { 578 uint32_t temp; 579 uint16_t i; 580 581 DPRINTF("\n"); 582 583 sc->sc_capa_off = 0; 584 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 585 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 586 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 587 588 /* Halt controller */ 589 XWRITE4(sc, oper, XHCI_USBCMD, 0); 590 591 for (i = 0; i != 100; i++) { 592 usb_pause_mtx(NULL, hz / 100); 593 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 594 if (temp) 595 break; 596 } 597 598 if (!temp) { 599 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 600 return (USB_ERR_IOERROR); 601 } 602 return (0); 603 } 604 605 usb_error_t 606 xhci_init(struct xhci_softc *sc, device_t self) 607 { 608 /* initialise some bus fields */ 609 sc->sc_bus.parent = self; 610 611 /* set the bus revision */ 612 sc->sc_bus.usbrev = USB_REV_3_0; 613 614 /* set up the bus struct */ 615 sc->sc_bus.methods = &xhci_bus_methods; 616 617 /* setup devices array */ 618 sc->sc_bus.devices = sc->sc_devices; 619 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 620 621 /* setup command queue mutex and condition varible */ 622 cv_init(&sc->sc_cmd_cv, "CMDQ"); 623 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 624 625 /* get all DMA memory */ 626 if (usb_bus_mem_alloc_all(&sc->sc_bus, 627 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 628 return (ENOMEM); 629 } 630 631 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 632 sc->sc_config_msg[0].bus = &sc->sc_bus; 633 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 634 sc->sc_config_msg[1].bus = &sc->sc_bus; 635 636 return (0); 637 } 638 639 void 640 xhci_uninit(struct xhci_softc *sc) 641 { 642 /* 643 * NOTE: At this point the control transfer process is gone 644 * and "xhci_configure_msg" is no longer called. Consequently 645 * waiting for the configuration messages to complete is not 646 * needed. 647 */ 648 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 649 650 cv_destroy(&sc->sc_cmd_cv); 651 sx_destroy(&sc->sc_cmd_sx); 652 } 653 654 static void 655 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 656 { 657 struct xhci_softc *sc = XHCI_BUS2SC(bus); 658 659 switch (state) { 660 case USB_HW_POWER_SUSPEND: 661 DPRINTF("Stopping the XHCI\n"); 662 xhci_halt_controller(sc); 663 break; 664 case USB_HW_POWER_SHUTDOWN: 665 DPRINTF("Stopping the XHCI\n"); 666 xhci_halt_controller(sc); 667 break; 668 case USB_HW_POWER_RESUME: 669 DPRINTF("Starting the XHCI\n"); 670 xhci_start_controller(sc); 671 break; 672 default: 673 break; 674 } 675 } 676 677 static usb_error_t 678 xhci_generic_done_sub(struct usb_xfer *xfer) 679 { 680 struct xhci_td *td; 681 struct xhci_td *td_alt_next; 682 uint32_t len; 683 uint8_t status; 684 685 td = xfer->td_transfer_cache; 686 td_alt_next = td->alt_next; 687 688 if (xfer->aframes != xfer->nframes) 689 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 690 691 while (1) { 692 693 usb_pc_cpu_invalidate(td->page_cache); 694 695 status = td->status; 696 len = td->remainder; 697 698 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 699 xfer, (unsigned int)xfer->aframes, 700 (unsigned int)xfer->nframes, 701 (unsigned int)len, (unsigned int)td->len, 702 (unsigned int)status); 703 704 /* 705 * Verify the status length and 706 * add the length to "frlengths[]": 707 */ 708 if (len > td->len) { 709 /* should not happen */ 710 DPRINTF("Invalid status length, " 711 "0x%04x/0x%04x bytes\n", len, td->len); 712 status = XHCI_TRB_ERROR_LENGTH; 713 } else if (xfer->aframes != xfer->nframes) { 714 xfer->frlengths[xfer->aframes] += td->len - len; 715 } 716 /* Check for last transfer */ 717 if (((void *)td) == xfer->td_transfer_last) { 718 td = NULL; 719 break; 720 } 721 /* Check for transfer error */ 722 if (status != XHCI_TRB_ERROR_SHORT_PKT && 723 status != XHCI_TRB_ERROR_SUCCESS) { 724 /* the transfer is finished */ 725 td = NULL; 726 break; 727 } 728 /* Check for short transfer */ 729 if (len > 0) { 730 if (xfer->flags_int.short_frames_ok || 731 xfer->flags_int.isochronous_xfr || 732 xfer->flags_int.control_xfr) { 733 /* follow alt next */ 734 td = td->alt_next; 735 } else { 736 /* the transfer is finished */ 737 td = NULL; 738 } 739 break; 740 } 741 td = td->obj_next; 742 743 if (td->alt_next != td_alt_next) { 744 /* this USB frame is complete */ 745 break; 746 } 747 } 748 749 /* update transfer cache */ 750 751 xfer->td_transfer_cache = td; 752 753 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 754 (status != XHCI_TRB_ERROR_SHORT_PKT && 755 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 756 USB_ERR_NORMAL_COMPLETION); 757 } 758 759 static void 760 xhci_generic_done(struct usb_xfer *xfer) 761 { 762 usb_error_t err = 0; 763 764 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 765 xfer, xfer->endpoint); 766 767 /* reset scanner */ 768 769 xfer->td_transfer_cache = xfer->td_transfer_first; 770 771 if (xfer->flags_int.control_xfr) { 772 773 if (xfer->flags_int.control_hdr) 774 err = xhci_generic_done_sub(xfer); 775 776 xfer->aframes = 1; 777 778 if (xfer->td_transfer_cache == NULL) 779 goto done; 780 } 781 782 while (xfer->aframes != xfer->nframes) { 783 784 err = xhci_generic_done_sub(xfer); 785 xfer->aframes++; 786 787 if (xfer->td_transfer_cache == NULL) 788 goto done; 789 } 790 791 if (xfer->flags_int.control_xfr && 792 !xfer->flags_int.control_act) 793 err = xhci_generic_done_sub(xfer); 794 done: 795 /* transfer is complete */ 796 xhci_device_done(xfer, err); 797 } 798 799 static void 800 xhci_activate_transfer(struct usb_xfer *xfer) 801 { 802 struct xhci_td *td; 803 804 td = xfer->td_transfer_cache; 805 806 usb_pc_cpu_invalidate(td->page_cache); 807 808 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 809 810 /* activate the transfer */ 811 812 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 813 usb_pc_cpu_flush(td->page_cache); 814 815 xhci_endpoint_doorbell(xfer); 816 } 817 } 818 819 static void 820 xhci_skip_transfer(struct usb_xfer *xfer) 821 { 822 struct xhci_td *td; 823 struct xhci_td *td_last; 824 825 td = xfer->td_transfer_cache; 826 td_last = xfer->td_transfer_last; 827 828 td = td->alt_next; 829 830 usb_pc_cpu_invalidate(td->page_cache); 831 832 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 833 834 usb_pc_cpu_invalidate(td_last->page_cache); 835 836 /* copy LINK TRB to current waiting location */ 837 838 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 839 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 840 usb_pc_cpu_flush(td->page_cache); 841 842 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 843 usb_pc_cpu_flush(td->page_cache); 844 845 xhci_endpoint_doorbell(xfer); 846 } 847 } 848 849 /*------------------------------------------------------------------------* 850 * xhci_check_transfer 851 *------------------------------------------------------------------------*/ 852 static void 853 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 854 { 855 struct xhci_endpoint_ext *pepext; 856 int64_t offset; 857 uint64_t td_event; 858 uint32_t temp; 859 uint32_t remainder; 860 uint16_t stream_id; 861 uint16_t i; 862 uint8_t status; 863 uint8_t halted; 864 uint8_t epno; 865 uint8_t index; 866 867 /* decode TRB */ 868 td_event = le64toh(trb->qwTrb0); 869 temp = le32toh(trb->dwTrb2); 870 871 remainder = XHCI_TRB_2_REM_GET(temp); 872 status = XHCI_TRB_2_ERROR_GET(temp); 873 stream_id = XHCI_TRB_2_STREAM_GET(temp); 874 875 temp = le32toh(trb->dwTrb3); 876 epno = XHCI_TRB_3_EP_GET(temp); 877 index = XHCI_TRB_3_SLOT_GET(temp); 878 879 /* check if error means halted */ 880 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 881 status != XHCI_TRB_ERROR_SUCCESS); 882 883 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 884 index, epno, stream_id, remainder, status); 885 886 if (index > sc->sc_noslot) { 887 DPRINTF("Invalid slot.\n"); 888 return; 889 } 890 891 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 892 DPRINTF("Invalid endpoint.\n"); 893 return; 894 } 895 896 pepext = &sc->sc_hw.devs[index].endp[epno]; 897 898 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 899 stream_id = 0; 900 DPRINTF("stream_id=0\n"); 901 } else if (stream_id >= XHCI_MAX_STREAMS) { 902 DPRINTF("Invalid stream ID.\n"); 903 return; 904 } 905 906 /* try to find the USB transfer that generated the event */ 907 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 908 struct usb_xfer *xfer; 909 struct xhci_td *td; 910 911 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 912 if (xfer == NULL) 913 continue; 914 915 td = xfer->td_transfer_cache; 916 917 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 918 (long long)td_event, 919 (long long)td->td_self, 920 (long long)td->td_self + sizeof(td->td_trb)); 921 922 /* 923 * NOTE: Some XHCI implementations might not trigger 924 * an event on the last LINK TRB so we need to 925 * consider both the last and second last event 926 * address as conditions for a successful transfer. 927 * 928 * NOTE: We assume that the XHCI will only trigger one 929 * event per chain of TRBs. 930 */ 931 932 offset = td_event - td->td_self; 933 934 if (offset >= 0 && 935 offset < (int64_t)sizeof(td->td_trb)) { 936 937 usb_pc_cpu_invalidate(td->page_cache); 938 939 /* compute rest of remainder, if any */ 940 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 941 temp = le32toh(td->td_trb[i].dwTrb2); 942 remainder += XHCI_TRB_2_BYTES_GET(temp); 943 } 944 945 DPRINTFN(5, "New remainder: %u\n", remainder); 946 947 /* clear isochronous transfer errors */ 948 if (xfer->flags_int.isochronous_xfr) { 949 if (halted) { 950 halted = 0; 951 status = XHCI_TRB_ERROR_SUCCESS; 952 remainder = td->len; 953 } 954 } 955 956 /* "td->remainder" is verified later */ 957 td->remainder = remainder; 958 td->status = status; 959 960 usb_pc_cpu_flush(td->page_cache); 961 962 /* 963 * 1) Last transfer descriptor makes the 964 * transfer done 965 */ 966 if (((void *)td) == xfer->td_transfer_last) { 967 DPRINTF("TD is last\n"); 968 xhci_generic_done(xfer); 969 break; 970 } 971 972 /* 973 * 2) Any kind of error makes the transfer 974 * done 975 */ 976 if (halted) { 977 DPRINTF("TD has I/O error\n"); 978 xhci_generic_done(xfer); 979 break; 980 } 981 982 /* 983 * 3) If there is no alternate next transfer, 984 * a short packet also makes the transfer done 985 */ 986 if (td->remainder > 0) { 987 if (td->alt_next == NULL) { 988 DPRINTF( 989 "short TD has no alternate next\n"); 990 xhci_generic_done(xfer); 991 break; 992 } 993 DPRINTF("TD has short pkt\n"); 994 if (xfer->flags_int.short_frames_ok || 995 xfer->flags_int.isochronous_xfr || 996 xfer->flags_int.control_xfr) { 997 /* follow the alt next */ 998 xfer->td_transfer_cache = td->alt_next; 999 xhci_activate_transfer(xfer); 1000 break; 1001 } 1002 xhci_skip_transfer(xfer); 1003 xhci_generic_done(xfer); 1004 break; 1005 } 1006 1007 /* 1008 * 4) Transfer complete - go to next TD 1009 */ 1010 DPRINTF("Following next TD\n"); 1011 xfer->td_transfer_cache = td->obj_next; 1012 xhci_activate_transfer(xfer); 1013 break; /* there should only be one match */ 1014 } 1015 } 1016 } 1017 1018 static int 1019 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1020 { 1021 if (sc->sc_cmd_addr == trb->qwTrb0) { 1022 DPRINTF("Received command event\n"); 1023 sc->sc_cmd_result[0] = trb->dwTrb2; 1024 sc->sc_cmd_result[1] = trb->dwTrb3; 1025 cv_signal(&sc->sc_cmd_cv); 1026 return (1); /* command match */ 1027 } 1028 return (0); 1029 } 1030 1031 static int 1032 xhci_interrupt_poll(struct xhci_softc *sc) 1033 { 1034 struct usb_page_search buf_res; 1035 struct xhci_hw_root *phwr; 1036 uint64_t addr; 1037 uint32_t temp; 1038 int retval = 0; 1039 uint16_t i; 1040 uint8_t event; 1041 uint8_t j; 1042 uint8_t k; 1043 uint8_t t; 1044 1045 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1046 1047 phwr = buf_res.buffer; 1048 1049 /* Receive any events */ 1050 1051 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1052 1053 i = sc->sc_event_idx; 1054 j = sc->sc_event_ccs; 1055 t = 2; 1056 1057 while (1) { 1058 1059 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1060 1061 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1062 1063 if (j != k) 1064 break; 1065 1066 event = XHCI_TRB_3_TYPE_GET(temp); 1067 1068 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1069 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1070 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1071 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1072 1073 switch (event) { 1074 case XHCI_TRB_EVENT_TRANSFER: 1075 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1076 break; 1077 case XHCI_TRB_EVENT_CMD_COMPLETE: 1078 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1079 break; 1080 default: 1081 DPRINTF("Unhandled event = %u\n", event); 1082 break; 1083 } 1084 1085 i++; 1086 1087 if (i == XHCI_MAX_EVENTS) { 1088 i = 0; 1089 j ^= 1; 1090 1091 /* check for timeout */ 1092 if (!--t) 1093 break; 1094 } 1095 } 1096 1097 sc->sc_event_idx = i; 1098 sc->sc_event_ccs = j; 1099 1100 /* 1101 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1102 * latched. That means to activate the register we need to 1103 * write both the low and high double word of the 64-bit 1104 * register. 1105 */ 1106 1107 addr = (uint32_t)buf_res.physaddr; 1108 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1109 1110 /* try to clear busy bit */ 1111 addr |= XHCI_ERDP_LO_BUSY; 1112 1113 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1114 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1115 1116 return (retval); 1117 } 1118 1119 static usb_error_t 1120 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1121 uint16_t timeout_ms) 1122 { 1123 struct usb_page_search buf_res; 1124 struct xhci_hw_root *phwr; 1125 uint64_t addr; 1126 uint32_t temp; 1127 uint8_t i; 1128 uint8_t j; 1129 uint8_t timeout = 0; 1130 int err; 1131 1132 XHCI_CMD_ASSERT_LOCKED(sc); 1133 1134 /* get hardware root structure */ 1135 1136 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1137 1138 phwr = buf_res.buffer; 1139 1140 /* Queue command */ 1141 1142 USB_BUS_LOCK(&sc->sc_bus); 1143 retry: 1144 i = sc->sc_command_idx; 1145 j = sc->sc_command_ccs; 1146 1147 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1148 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1149 (long long)le64toh(trb->qwTrb0), 1150 (long)le32toh(trb->dwTrb2), 1151 (long)le32toh(trb->dwTrb3)); 1152 1153 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1154 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1155 1156 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1157 1158 temp = trb->dwTrb3; 1159 1160 if (j) 1161 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1162 else 1163 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1164 1165 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1166 1167 phwr->hwr_commands[i].dwTrb3 = temp; 1168 1169 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1170 1171 addr = buf_res.physaddr; 1172 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1173 1174 sc->sc_cmd_addr = htole64(addr); 1175 1176 i++; 1177 1178 if (i == (XHCI_MAX_COMMANDS - 1)) { 1179 1180 if (j) { 1181 temp = htole32(XHCI_TRB_3_TC_BIT | 1182 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1183 XHCI_TRB_3_CYCLE_BIT); 1184 } else { 1185 temp = htole32(XHCI_TRB_3_TC_BIT | 1186 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1187 } 1188 1189 phwr->hwr_commands[i].dwTrb3 = temp; 1190 1191 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1192 1193 i = 0; 1194 j ^= 1; 1195 } 1196 1197 sc->sc_command_idx = i; 1198 sc->sc_command_ccs = j; 1199 1200 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1201 1202 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1203 USB_MS_TO_TICKS(timeout_ms)); 1204 1205 /* 1206 * In some error cases event interrupts are not generated. 1207 * Poll one time to see if the command has completed. 1208 */ 1209 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1210 DPRINTF("Command was completed when polling\n"); 1211 err = 0; 1212 } 1213 if (err != 0) { 1214 DPRINTF("Command timeout!\n"); 1215 /* 1216 * After some weeks of continuous operation, it has 1217 * been observed that the ASMedia Technology, ASM1042 1218 * SuperSpeed USB Host Controller can suddenly stop 1219 * accepting commands via the command queue. Try to 1220 * first reset the command queue. If that fails do a 1221 * host controller reset. 1222 */ 1223 if (timeout == 0 && 1224 xhci_reset_command_queue_locked(sc) == 0) { 1225 temp = le32toh(trb->dwTrb3); 1226 1227 /* 1228 * Avoid infinite XHCI reset loops if the set 1229 * address command fails to respond due to a 1230 * non-enumerating device: 1231 */ 1232 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1233 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1234 DPRINTF("Set address timeout\n"); 1235 } else { 1236 timeout = 1; 1237 goto retry; 1238 } 1239 } else { 1240 DPRINTF("Controller reset!\n"); 1241 usb_bus_reset_async_locked(&sc->sc_bus); 1242 } 1243 err = USB_ERR_TIMEOUT; 1244 trb->dwTrb2 = 0; 1245 trb->dwTrb3 = 0; 1246 } else { 1247 temp = le32toh(sc->sc_cmd_result[0]); 1248 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1249 err = USB_ERR_IOERROR; 1250 1251 trb->dwTrb2 = sc->sc_cmd_result[0]; 1252 trb->dwTrb3 = sc->sc_cmd_result[1]; 1253 } 1254 1255 USB_BUS_UNLOCK(&sc->sc_bus); 1256 1257 return (err); 1258 } 1259 1260 #if 0 1261 static usb_error_t 1262 xhci_cmd_nop(struct xhci_softc *sc) 1263 { 1264 struct xhci_trb trb; 1265 uint32_t temp; 1266 1267 DPRINTF("\n"); 1268 1269 trb.qwTrb0 = 0; 1270 trb.dwTrb2 = 0; 1271 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1272 1273 trb.dwTrb3 = htole32(temp); 1274 1275 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1276 } 1277 #endif 1278 1279 static usb_error_t 1280 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1281 { 1282 struct xhci_trb trb; 1283 uint32_t temp; 1284 usb_error_t err; 1285 1286 DPRINTF("\n"); 1287 1288 trb.qwTrb0 = 0; 1289 trb.dwTrb2 = 0; 1290 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1291 1292 err = xhci_do_command(sc, &trb, 100 /* ms */); 1293 if (err) 1294 goto done; 1295 1296 temp = le32toh(trb.dwTrb3); 1297 1298 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1299 1300 done: 1301 return (err); 1302 } 1303 1304 static usb_error_t 1305 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1306 { 1307 struct xhci_trb trb; 1308 uint32_t temp; 1309 1310 DPRINTF("\n"); 1311 1312 trb.qwTrb0 = 0; 1313 trb.dwTrb2 = 0; 1314 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1315 XHCI_TRB_3_SLOT_SET(slot_id); 1316 1317 trb.dwTrb3 = htole32(temp); 1318 1319 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1320 } 1321 1322 static usb_error_t 1323 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1324 uint8_t bsr, uint8_t slot_id) 1325 { 1326 struct xhci_trb trb; 1327 uint32_t temp; 1328 1329 DPRINTF("\n"); 1330 1331 trb.qwTrb0 = htole64(input_ctx); 1332 trb.dwTrb2 = 0; 1333 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1334 XHCI_TRB_3_SLOT_SET(slot_id); 1335 1336 if (bsr) 1337 temp |= XHCI_TRB_3_BSR_BIT; 1338 1339 trb.dwTrb3 = htole32(temp); 1340 1341 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1342 } 1343 1344 static usb_error_t 1345 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1346 { 1347 struct usb_page_search buf_inp; 1348 struct usb_page_search buf_dev; 1349 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1350 struct xhci_hw_dev *hdev; 1351 struct xhci_dev_ctx *pdev; 1352 struct xhci_endpoint_ext *pepext; 1353 uint32_t temp; 1354 uint16_t mps; 1355 usb_error_t err; 1356 uint8_t index; 1357 1358 /* the root HUB case is not handled here */ 1359 if (udev->parent_hub == NULL) 1360 return (USB_ERR_INVAL); 1361 1362 index = udev->controller_slot_id; 1363 1364 hdev = &sc->sc_hw.devs[index]; 1365 1366 if (mtx != NULL) 1367 mtx_unlock(mtx); 1368 1369 XHCI_CMD_LOCK(sc); 1370 1371 switch (hdev->state) { 1372 case XHCI_ST_DEFAULT: 1373 case XHCI_ST_ENABLED: 1374 1375 hdev->state = XHCI_ST_ENABLED; 1376 1377 /* set configure mask to slot and EP0 */ 1378 xhci_configure_mask(udev, 3, 0); 1379 1380 /* configure input slot context structure */ 1381 err = xhci_configure_device(udev); 1382 1383 if (err != 0) { 1384 DPRINTF("Could not configure device\n"); 1385 break; 1386 } 1387 1388 /* configure input endpoint context structure */ 1389 switch (udev->speed) { 1390 case USB_SPEED_LOW: 1391 case USB_SPEED_FULL: 1392 mps = 8; 1393 break; 1394 case USB_SPEED_HIGH: 1395 mps = 64; 1396 break; 1397 default: 1398 mps = 512; 1399 break; 1400 } 1401 1402 pepext = xhci_get_endpoint_ext(udev, 1403 &udev->ctrl_ep_desc); 1404 err = xhci_configure_endpoint(udev, 1405 &udev->ctrl_ep_desc, pepext, 1406 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1407 1408 if (err != 0) { 1409 DPRINTF("Could not configure default endpoint\n"); 1410 break; 1411 } 1412 1413 /* execute set address command */ 1414 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1415 1416 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1417 (address == 0), index); 1418 1419 if (err != 0) { 1420 temp = le32toh(sc->sc_cmd_result[0]); 1421 if (address == 0 && sc->sc_port_route != NULL && 1422 XHCI_TRB_2_ERROR_GET(temp) == 1423 XHCI_TRB_ERROR_PARAMETER) { 1424 /* LynxPoint XHCI - ports are not switchable */ 1425 /* Un-route all ports from the XHCI */ 1426 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1427 } 1428 DPRINTF("Could not set address " 1429 "for slot %u.\n", index); 1430 if (address != 0) 1431 break; 1432 } 1433 1434 /* update device address to new value */ 1435 1436 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1437 pdev = buf_dev.buffer; 1438 usb_pc_cpu_invalidate(&hdev->device_pc); 1439 1440 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1441 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1442 1443 /* update device state to new value */ 1444 1445 if (address != 0) 1446 hdev->state = XHCI_ST_ADDRESSED; 1447 else 1448 hdev->state = XHCI_ST_DEFAULT; 1449 break; 1450 1451 default: 1452 DPRINTF("Wrong state for set address.\n"); 1453 err = USB_ERR_IOERROR; 1454 break; 1455 } 1456 XHCI_CMD_UNLOCK(sc); 1457 1458 if (mtx != NULL) 1459 mtx_lock(mtx); 1460 1461 return (err); 1462 } 1463 1464 static usb_error_t 1465 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1466 uint8_t deconfigure, uint8_t slot_id) 1467 { 1468 struct xhci_trb trb; 1469 uint32_t temp; 1470 1471 DPRINTF("\n"); 1472 1473 trb.qwTrb0 = htole64(input_ctx); 1474 trb.dwTrb2 = 0; 1475 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1476 XHCI_TRB_3_SLOT_SET(slot_id); 1477 1478 if (deconfigure) 1479 temp |= XHCI_TRB_3_DCEP_BIT; 1480 1481 trb.dwTrb3 = htole32(temp); 1482 1483 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1484 } 1485 1486 static usb_error_t 1487 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1488 uint8_t slot_id) 1489 { 1490 struct xhci_trb trb; 1491 uint32_t temp; 1492 1493 DPRINTF("\n"); 1494 1495 trb.qwTrb0 = htole64(input_ctx); 1496 trb.dwTrb2 = 0; 1497 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1498 XHCI_TRB_3_SLOT_SET(slot_id); 1499 trb.dwTrb3 = htole32(temp); 1500 1501 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1502 } 1503 1504 static usb_error_t 1505 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1506 uint8_t ep_id, uint8_t slot_id) 1507 { 1508 struct xhci_trb trb; 1509 uint32_t temp; 1510 1511 DPRINTF("\n"); 1512 1513 trb.qwTrb0 = 0; 1514 trb.dwTrb2 = 0; 1515 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1516 XHCI_TRB_3_SLOT_SET(slot_id) | 1517 XHCI_TRB_3_EP_SET(ep_id); 1518 1519 if (preserve) 1520 temp |= XHCI_TRB_3_PRSV_BIT; 1521 1522 trb.dwTrb3 = htole32(temp); 1523 1524 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1525 } 1526 1527 static usb_error_t 1528 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1529 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1530 { 1531 struct xhci_trb trb; 1532 uint32_t temp; 1533 1534 DPRINTF("\n"); 1535 1536 trb.qwTrb0 = htole64(dequeue_ptr); 1537 1538 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1539 trb.dwTrb2 = htole32(temp); 1540 1541 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1542 XHCI_TRB_3_SLOT_SET(slot_id) | 1543 XHCI_TRB_3_EP_SET(ep_id); 1544 trb.dwTrb3 = htole32(temp); 1545 1546 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1547 } 1548 1549 static usb_error_t 1550 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1551 uint8_t ep_id, uint8_t slot_id) 1552 { 1553 struct xhci_trb trb; 1554 uint32_t temp; 1555 1556 DPRINTF("\n"); 1557 1558 trb.qwTrb0 = 0; 1559 trb.dwTrb2 = 0; 1560 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1561 XHCI_TRB_3_SLOT_SET(slot_id) | 1562 XHCI_TRB_3_EP_SET(ep_id); 1563 1564 if (suspend) 1565 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1566 1567 trb.dwTrb3 = htole32(temp); 1568 1569 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1570 } 1571 1572 static usb_error_t 1573 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1574 { 1575 struct xhci_trb trb; 1576 uint32_t temp; 1577 1578 DPRINTF("\n"); 1579 1580 trb.qwTrb0 = 0; 1581 trb.dwTrb2 = 0; 1582 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1583 XHCI_TRB_3_SLOT_SET(slot_id); 1584 1585 trb.dwTrb3 = htole32(temp); 1586 1587 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1588 } 1589 1590 /*------------------------------------------------------------------------* 1591 * xhci_interrupt - XHCI interrupt handler 1592 *------------------------------------------------------------------------*/ 1593 void 1594 xhci_interrupt(struct xhci_softc *sc) 1595 { 1596 uint32_t status; 1597 uint32_t temp; 1598 1599 USB_BUS_LOCK(&sc->sc_bus); 1600 1601 status = XREAD4(sc, oper, XHCI_USBSTS); 1602 1603 /* acknowledge interrupts, if any */ 1604 if (status != 0) { 1605 XWRITE4(sc, oper, XHCI_USBSTS, status); 1606 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1607 } 1608 1609 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1610 1611 /* force clearing of pending interrupts */ 1612 if (temp & XHCI_IMAN_INTR_PEND) 1613 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1614 1615 /* check for event(s) */ 1616 xhci_interrupt_poll(sc); 1617 1618 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1619 XHCI_STS_HSE | XHCI_STS_HCE)) { 1620 1621 if (status & XHCI_STS_PCD) { 1622 xhci_root_intr(sc); 1623 } 1624 1625 if (status & XHCI_STS_HCH) { 1626 printf("%s: host controller halted\n", 1627 __FUNCTION__); 1628 } 1629 1630 if (status & XHCI_STS_HSE) { 1631 printf("%s: host system error\n", 1632 __FUNCTION__); 1633 } 1634 1635 if (status & XHCI_STS_HCE) { 1636 printf("%s: host controller error\n", 1637 __FUNCTION__); 1638 } 1639 } 1640 USB_BUS_UNLOCK(&sc->sc_bus); 1641 } 1642 1643 /*------------------------------------------------------------------------* 1644 * xhci_timeout - XHCI timeout handler 1645 *------------------------------------------------------------------------*/ 1646 static void 1647 xhci_timeout(void *arg) 1648 { 1649 struct usb_xfer *xfer = arg; 1650 1651 DPRINTF("xfer=%p\n", xfer); 1652 1653 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1654 1655 /* transfer is transferred */ 1656 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1657 } 1658 1659 static void 1660 xhci_do_poll(struct usb_bus *bus) 1661 { 1662 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1663 1664 USB_BUS_LOCK(&sc->sc_bus); 1665 xhci_interrupt_poll(sc); 1666 USB_BUS_UNLOCK(&sc->sc_bus); 1667 } 1668 1669 static void 1670 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1671 { 1672 struct usb_page_search buf_res; 1673 struct xhci_td *td; 1674 struct xhci_td *td_next; 1675 struct xhci_td *td_alt_next; 1676 struct xhci_td *td_first; 1677 uint32_t buf_offset; 1678 uint32_t average; 1679 uint32_t len_old; 1680 uint32_t npkt_off; 1681 uint32_t dword; 1682 uint8_t shortpkt_old; 1683 uint8_t precompute; 1684 uint8_t x; 1685 1686 td_alt_next = NULL; 1687 buf_offset = 0; 1688 shortpkt_old = temp->shortpkt; 1689 len_old = temp->len; 1690 npkt_off = 0; 1691 precompute = 1; 1692 1693 restart: 1694 1695 td = temp->td; 1696 td_next = td_first = temp->td_next; 1697 1698 while (1) { 1699 1700 if (temp->len == 0) { 1701 1702 if (temp->shortpkt) 1703 break; 1704 1705 /* send a Zero Length Packet, ZLP, last */ 1706 1707 temp->shortpkt = 1; 1708 average = 0; 1709 1710 } else { 1711 1712 average = temp->average; 1713 1714 if (temp->len < average) { 1715 if (temp->len % temp->max_packet_size) { 1716 temp->shortpkt = 1; 1717 } 1718 average = temp->len; 1719 } 1720 } 1721 1722 if (td_next == NULL) 1723 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1724 1725 /* get next TD */ 1726 1727 td = td_next; 1728 td_next = td->obj_next; 1729 1730 /* check if we are pre-computing */ 1731 1732 if (precompute) { 1733 1734 /* update remaining length */ 1735 1736 temp->len -= average; 1737 1738 continue; 1739 } 1740 /* fill out current TD */ 1741 1742 td->len = average; 1743 td->remainder = 0; 1744 td->status = 0; 1745 1746 /* update remaining length */ 1747 1748 temp->len -= average; 1749 1750 /* reset TRB index */ 1751 1752 x = 0; 1753 1754 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1755 /* immediate data */ 1756 1757 if (average > 8) 1758 average = 8; 1759 1760 td->td_trb[0].qwTrb0 = 0; 1761 1762 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1763 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1764 average); 1765 1766 dword = XHCI_TRB_2_BYTES_SET(8) | 1767 XHCI_TRB_2_TDSZ_SET(0) | 1768 XHCI_TRB_2_IRQ_SET(0); 1769 1770 td->td_trb[0].dwTrb2 = htole32(dword); 1771 1772 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1773 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1774 1775 /* check wLength */ 1776 if (td->td_trb[0].qwTrb0 & 1777 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1778 if (td->td_trb[0].qwTrb0 & 1779 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1780 dword |= XHCI_TRB_3_TRT_IN; 1781 else 1782 dword |= XHCI_TRB_3_TRT_OUT; 1783 } 1784 1785 td->td_trb[0].dwTrb3 = htole32(dword); 1786 #ifdef USB_DEBUG 1787 xhci_dump_trb(&td->td_trb[x]); 1788 #endif 1789 x++; 1790 1791 } else do { 1792 1793 uint32_t npkt; 1794 1795 /* fill out buffer pointers */ 1796 1797 if (average == 0) { 1798 memset(&buf_res, 0, sizeof(buf_res)); 1799 } else { 1800 usbd_get_page(temp->pc, temp->offset + 1801 buf_offset, &buf_res); 1802 1803 /* get length to end of page */ 1804 if (buf_res.length > average) 1805 buf_res.length = average; 1806 1807 /* check for maximum length */ 1808 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1809 buf_res.length = XHCI_TD_PAGE_SIZE; 1810 1811 npkt_off += buf_res.length; 1812 } 1813 1814 /* setup npkt */ 1815 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1816 temp->max_packet_size; 1817 1818 if (npkt == 0) 1819 npkt = 1; 1820 else if (npkt > 31) 1821 npkt = 31; 1822 1823 /* fill out TRB's */ 1824 td->td_trb[x].qwTrb0 = 1825 htole64((uint64_t)buf_res.physaddr); 1826 1827 dword = 1828 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1829 XHCI_TRB_2_TDSZ_SET(npkt) | 1830 XHCI_TRB_2_IRQ_SET(0); 1831 1832 td->td_trb[x].dwTrb2 = htole32(dword); 1833 1834 switch (temp->trb_type) { 1835 case XHCI_TRB_TYPE_ISOCH: 1836 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1837 XHCI_TRB_3_TBC_SET(temp->tbc) | 1838 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1839 if (td != td_first) { 1840 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1841 } else if (temp->do_isoc_sync != 0) { 1842 temp->do_isoc_sync = 0; 1843 /* wait until "isoc_frame" */ 1844 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1845 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1846 } else { 1847 /* start data transfer at next interval */ 1848 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1849 XHCI_TRB_3_ISO_SIA_BIT; 1850 } 1851 if (temp->direction == UE_DIR_IN) 1852 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1853 break; 1854 case XHCI_TRB_TYPE_DATA_STAGE: 1855 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1856 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 1857 XHCI_TRB_3_TBC_SET(temp->tbc) | 1858 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1859 if (temp->direction == UE_DIR_IN) 1860 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1861 break; 1862 case XHCI_TRB_TYPE_STATUS_STAGE: 1863 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1864 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 1865 XHCI_TRB_3_TBC_SET(temp->tbc) | 1866 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1867 if (temp->direction == UE_DIR_IN) 1868 dword |= XHCI_TRB_3_DIR_IN; 1869 break; 1870 default: /* XHCI_TRB_TYPE_NORMAL */ 1871 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1872 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 1873 XHCI_TRB_3_TBC_SET(temp->tbc) | 1874 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1875 if (temp->direction == UE_DIR_IN) 1876 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1877 break; 1878 } 1879 td->td_trb[x].dwTrb3 = htole32(dword); 1880 1881 average -= buf_res.length; 1882 buf_offset += buf_res.length; 1883 #ifdef USB_DEBUG 1884 xhci_dump_trb(&td->td_trb[x]); 1885 #endif 1886 x++; 1887 1888 } while (average != 0); 1889 1890 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1891 1892 /* store number of data TRB's */ 1893 1894 td->ntrb = x; 1895 1896 DPRINTF("NTRB=%u\n", x); 1897 1898 /* fill out link TRB */ 1899 1900 if (td_next != NULL) { 1901 /* link the current TD with the next one */ 1902 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1903 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1904 } else { 1905 /* this field will get updated later */ 1906 DPRINTF("NOLINK\n"); 1907 } 1908 1909 dword = XHCI_TRB_2_IRQ_SET(0); 1910 1911 td->td_trb[x].dwTrb2 = htole32(dword); 1912 1913 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1914 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1915 /* 1916 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1917 * frame only receives a single short packet event 1918 * by setting the CHAIN bit in the LINK field. In 1919 * addition some XHCI controllers have problems 1920 * sending a ZLP unless the CHAIN-BIT is set in 1921 * the LINK TRB. 1922 */ 1923 XHCI_TRB_3_CHAIN_BIT; 1924 1925 td->td_trb[x].dwTrb3 = htole32(dword); 1926 1927 td->alt_next = td_alt_next; 1928 #ifdef USB_DEBUG 1929 xhci_dump_trb(&td->td_trb[x]); 1930 #endif 1931 usb_pc_cpu_flush(td->page_cache); 1932 } 1933 1934 if (precompute) { 1935 precompute = 0; 1936 1937 /* setup alt next pointer, if any */ 1938 if (temp->last_frame) { 1939 td_alt_next = NULL; 1940 } else { 1941 /* we use this field internally */ 1942 td_alt_next = td_next; 1943 } 1944 1945 /* restore */ 1946 temp->shortpkt = shortpkt_old; 1947 temp->len = len_old; 1948 goto restart; 1949 } 1950 1951 /* 1952 * Remove cycle bit from the first TRB if we are 1953 * stepping them: 1954 */ 1955 if (temp->step_td != 0) { 1956 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1957 usb_pc_cpu_flush(td_first->page_cache); 1958 } 1959 1960 /* clear TD SIZE to zero, hence this is the last TRB */ 1961 /* remove chain bit because this is the last data TRB in the chain */ 1962 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1963 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1964 /* remove CHAIN-BIT from last LINK TRB */ 1965 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1966 1967 usb_pc_cpu_flush(td->page_cache); 1968 1969 temp->td = td; 1970 temp->td_next = td_next; 1971 } 1972 1973 static void 1974 xhci_setup_generic_chain(struct usb_xfer *xfer) 1975 { 1976 struct xhci_std_temp temp; 1977 struct xhci_td *td; 1978 uint32_t x; 1979 uint32_t y; 1980 uint8_t mult; 1981 1982 temp.do_isoc_sync = 0; 1983 temp.step_td = 0; 1984 temp.tbc = 0; 1985 temp.tlbpc = 0; 1986 temp.average = xfer->max_hc_frame_size; 1987 temp.max_packet_size = xfer->max_packet_size; 1988 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1989 temp.pc = NULL; 1990 temp.last_frame = 0; 1991 temp.offset = 0; 1992 temp.multishort = xfer->flags_int.isochronous_xfr || 1993 xfer->flags_int.control_xfr || 1994 xfer->flags_int.short_frames_ok; 1995 1996 /* toggle the DMA set we are using */ 1997 xfer->flags_int.curr_dma_set ^= 1; 1998 1999 /* get next DMA set */ 2000 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2001 2002 temp.td = NULL; 2003 temp.td_next = td; 2004 2005 xfer->td_transfer_first = td; 2006 xfer->td_transfer_cache = td; 2007 2008 if (xfer->flags_int.isochronous_xfr) { 2009 uint8_t shift; 2010 2011 /* compute multiplier for ISOCHRONOUS transfers */ 2012 mult = xfer->endpoint->ecomp ? 2013 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2014 : 0; 2015 /* check for USB 2.0 multiplier */ 2016 if (mult == 0) { 2017 mult = (xfer->endpoint->edesc-> 2018 wMaxPacketSize[1] >> 3) & 3; 2019 } 2020 /* range check */ 2021 if (mult > 2) 2022 mult = 3; 2023 else 2024 mult++; 2025 2026 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2027 2028 DPRINTF("MFINDEX=0x%08x\n", x); 2029 2030 switch (usbd_get_speed(xfer->xroot->udev)) { 2031 case USB_SPEED_FULL: 2032 shift = 3; 2033 temp.isoc_delta = 8; /* 1ms */ 2034 x += temp.isoc_delta - 1; 2035 x &= ~(temp.isoc_delta - 1); 2036 break; 2037 default: 2038 shift = usbd_xfer_get_fps_shift(xfer); 2039 temp.isoc_delta = 1U << shift; 2040 x += temp.isoc_delta - 1; 2041 x &= ~(temp.isoc_delta - 1); 2042 /* simple frame load balancing */ 2043 x += xfer->endpoint->usb_uframe; 2044 break; 2045 } 2046 2047 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2048 2049 if ((xfer->endpoint->is_synced == 0) || 2050 (y < (xfer->nframes << shift)) || 2051 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2052 /* 2053 * If there is data underflow or the pipe 2054 * queue is empty we schedule the transfer a 2055 * few frames ahead of the current frame 2056 * position. Else two isochronous transfers 2057 * might overlap. 2058 */ 2059 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2060 xfer->endpoint->is_synced = 1; 2061 temp.do_isoc_sync = 1; 2062 2063 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2064 } 2065 2066 /* compute isochronous completion time */ 2067 2068 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2069 2070 xfer->isoc_time_complete = 2071 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2072 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2073 2074 x = 0; 2075 temp.isoc_frame = xfer->endpoint->isoc_next; 2076 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2077 2078 xfer->endpoint->isoc_next += xfer->nframes << shift; 2079 2080 } else if (xfer->flags_int.control_xfr) { 2081 2082 /* check if we should prepend a setup message */ 2083 2084 if (xfer->flags_int.control_hdr) { 2085 2086 temp.len = xfer->frlengths[0]; 2087 temp.pc = xfer->frbuffers + 0; 2088 temp.shortpkt = temp.len ? 1 : 0; 2089 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2090 temp.direction = 0; 2091 2092 /* check for last frame */ 2093 if (xfer->nframes == 1) { 2094 /* no STATUS stage yet, SETUP is last */ 2095 if (xfer->flags_int.control_act) 2096 temp.last_frame = 1; 2097 } 2098 2099 xhci_setup_generic_chain_sub(&temp); 2100 } 2101 x = 1; 2102 mult = 1; 2103 temp.isoc_delta = 0; 2104 temp.isoc_frame = 0; 2105 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 2106 } else { 2107 x = 0; 2108 mult = 1; 2109 temp.isoc_delta = 0; 2110 temp.isoc_frame = 0; 2111 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2112 } 2113 2114 if (x != xfer->nframes) { 2115 /* setup page_cache pointer */ 2116 temp.pc = xfer->frbuffers + x; 2117 /* set endpoint direction */ 2118 temp.direction = UE_GET_DIR(xfer->endpointno); 2119 } 2120 2121 while (x != xfer->nframes) { 2122 2123 /* DATA0 / DATA1 message */ 2124 2125 temp.len = xfer->frlengths[x]; 2126 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2127 x != 0 && temp.multishort == 0); 2128 2129 x++; 2130 2131 if (x == xfer->nframes) { 2132 if (xfer->flags_int.control_xfr) { 2133 /* no STATUS stage yet, DATA is last */ 2134 if (xfer->flags_int.control_act) 2135 temp.last_frame = 1; 2136 } else { 2137 temp.last_frame = 1; 2138 } 2139 } 2140 if (temp.len == 0) { 2141 2142 /* make sure that we send an USB packet */ 2143 2144 temp.shortpkt = 0; 2145 2146 temp.tbc = 0; 2147 temp.tlbpc = mult - 1; 2148 2149 } else if (xfer->flags_int.isochronous_xfr) { 2150 2151 uint8_t tdpc; 2152 2153 /* 2154 * Isochronous transfers don't have short 2155 * packet termination: 2156 */ 2157 2158 temp.shortpkt = 1; 2159 2160 /* isochronous transfers have a transfer limit */ 2161 2162 if (temp.len > xfer->max_frame_size) 2163 temp.len = xfer->max_frame_size; 2164 2165 /* compute TD packet count */ 2166 tdpc = (temp.len + xfer->max_packet_size - 1) / 2167 xfer->max_packet_size; 2168 2169 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2170 temp.tlbpc = (tdpc % mult); 2171 2172 if (temp.tlbpc == 0) 2173 temp.tlbpc = mult - 1; 2174 else 2175 temp.tlbpc--; 2176 } else { 2177 2178 /* regular data transfer */ 2179 2180 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2181 } 2182 2183 xhci_setup_generic_chain_sub(&temp); 2184 2185 if (xfer->flags_int.isochronous_xfr) { 2186 temp.offset += xfer->frlengths[x - 1]; 2187 temp.isoc_frame += temp.isoc_delta; 2188 } else { 2189 /* get next Page Cache pointer */ 2190 temp.pc = xfer->frbuffers + x; 2191 } 2192 } 2193 2194 /* check if we should append a status stage */ 2195 2196 if (xfer->flags_int.control_xfr && 2197 !xfer->flags_int.control_act) { 2198 2199 /* 2200 * Send a DATA1 message and invert the current 2201 * endpoint direction. 2202 */ 2203 temp.step_td = (xfer->nframes != 0); 2204 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2205 temp.len = 0; 2206 temp.pc = NULL; 2207 temp.shortpkt = 0; 2208 temp.last_frame = 1; 2209 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2210 2211 xhci_setup_generic_chain_sub(&temp); 2212 } 2213 2214 td = temp.td; 2215 2216 /* must have at least one frame! */ 2217 2218 xfer->td_transfer_last = td; 2219 2220 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2221 } 2222 2223 static void 2224 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2225 { 2226 struct usb_page_search buf_res; 2227 struct xhci_dev_ctx_addr *pdctxa; 2228 2229 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2230 2231 pdctxa = buf_res.buffer; 2232 2233 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2234 2235 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2236 2237 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2238 } 2239 2240 static usb_error_t 2241 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2242 { 2243 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2244 struct usb_page_search buf_inp; 2245 struct xhci_input_dev_ctx *pinp; 2246 uint32_t temp; 2247 uint8_t index; 2248 uint8_t x; 2249 2250 index = udev->controller_slot_id; 2251 2252 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2253 2254 pinp = buf_inp.buffer; 2255 2256 if (drop) { 2257 mask &= XHCI_INCTX_NON_CTRL_MASK; 2258 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2259 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2260 } else { 2261 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2262 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2263 2264 /* find most significant set bit */ 2265 for (x = 31; x != 1; x--) { 2266 if (mask & (1 << x)) 2267 break; 2268 } 2269 2270 /* adjust */ 2271 x--; 2272 2273 /* figure out maximum */ 2274 if (x > sc->sc_hw.devs[index].context_num) { 2275 sc->sc_hw.devs[index].context_num = x; 2276 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2277 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2278 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2279 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2280 } 2281 } 2282 return (0); 2283 } 2284 2285 static usb_error_t 2286 xhci_configure_endpoint(struct usb_device *udev, 2287 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2288 uint16_t interval, uint8_t max_packet_count, 2289 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2290 uint16_t max_frame_size, uint8_t ep_mode) 2291 { 2292 struct usb_page_search buf_inp; 2293 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2294 struct xhci_input_dev_ctx *pinp; 2295 uint64_t ring_addr = pepext->physaddr; 2296 uint32_t temp; 2297 uint8_t index; 2298 uint8_t epno; 2299 uint8_t type; 2300 2301 index = udev->controller_slot_id; 2302 2303 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2304 2305 pinp = buf_inp.buffer; 2306 2307 epno = edesc->bEndpointAddress; 2308 type = edesc->bmAttributes & UE_XFERTYPE; 2309 2310 if (type == UE_CONTROL) 2311 epno |= UE_DIR_IN; 2312 2313 epno = XHCI_EPNO2EPID(epno); 2314 2315 if (epno == 0) 2316 return (USB_ERR_NO_PIPE); /* invalid */ 2317 2318 if (max_packet_count == 0) 2319 return (USB_ERR_BAD_BUFSIZE); 2320 2321 max_packet_count--; 2322 2323 if (mult == 0) 2324 return (USB_ERR_BAD_BUFSIZE); 2325 2326 /* store endpoint mode */ 2327 pepext->trb_ep_mode = ep_mode; 2328 usb_pc_cpu_flush(pepext->page_cache); 2329 2330 if (ep_mode == USB_EP_MODE_STREAMS) { 2331 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2332 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2333 XHCI_EPCTX_0_LSA_SET(1); 2334 2335 ring_addr += sizeof(struct xhci_trb) * 2336 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2337 } else { 2338 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2339 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2340 XHCI_EPCTX_0_LSA_SET(0); 2341 2342 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2343 } 2344 2345 switch (udev->speed) { 2346 case USB_SPEED_FULL: 2347 case USB_SPEED_LOW: 2348 /* 1ms -> 125us */ 2349 fps_shift += 3; 2350 break; 2351 default: 2352 break; 2353 } 2354 2355 switch (type) { 2356 case UE_INTERRUPT: 2357 if (fps_shift > 3) 2358 fps_shift--; 2359 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2360 break; 2361 case UE_ISOCHRONOUS: 2362 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2363 2364 switch (udev->speed) { 2365 case USB_SPEED_SUPER: 2366 if (mult > 3) 2367 mult = 3; 2368 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2369 max_packet_count /= mult; 2370 break; 2371 default: 2372 break; 2373 } 2374 break; 2375 default: 2376 break; 2377 } 2378 2379 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2380 2381 temp = 2382 XHCI_EPCTX_1_HID_SET(0) | 2383 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2384 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2385 2386 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2387 if (type != UE_ISOCHRONOUS) 2388 temp |= XHCI_EPCTX_1_CERR_SET(3); 2389 } 2390 2391 switch (type) { 2392 case UE_CONTROL: 2393 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2394 break; 2395 case UE_ISOCHRONOUS: 2396 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2397 break; 2398 case UE_BULK: 2399 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2400 break; 2401 default: 2402 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2403 break; 2404 } 2405 2406 /* check for IN direction */ 2407 if (epno & 1) 2408 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2409 2410 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2411 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2412 2413 switch (edesc->bmAttributes & UE_XFERTYPE) { 2414 case UE_INTERRUPT: 2415 case UE_ISOCHRONOUS: 2416 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2417 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2418 max_frame_size)); 2419 break; 2420 case UE_CONTROL: 2421 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2422 break; 2423 default: 2424 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2425 break; 2426 } 2427 2428 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2429 2430 #ifdef USB_DEBUG 2431 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2432 #endif 2433 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2434 2435 return (0); /* success */ 2436 } 2437 2438 static usb_error_t 2439 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2440 { 2441 struct xhci_endpoint_ext *pepext; 2442 struct usb_endpoint_ss_comp_descriptor *ecomp; 2443 usb_stream_t x; 2444 2445 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2446 xfer->endpoint->edesc); 2447 2448 ecomp = xfer->endpoint->ecomp; 2449 2450 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2451 uint64_t temp; 2452 2453 /* halt any transfers */ 2454 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2455 2456 /* compute start of TRB ring for stream "x" */ 2457 temp = pepext->physaddr + 2458 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2459 XHCI_SCTX_0_SCT_SEC_TR_RING; 2460 2461 /* make tree structure */ 2462 pepext->trb[(XHCI_MAX_TRANSFERS * 2463 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2464 2465 /* reserved fields */ 2466 pepext->trb[(XHCI_MAX_TRANSFERS * 2467 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2468 pepext->trb[(XHCI_MAX_TRANSFERS * 2469 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2470 } 2471 usb_pc_cpu_flush(pepext->page_cache); 2472 2473 return (xhci_configure_endpoint(xfer->xroot->udev, 2474 xfer->endpoint->edesc, pepext, 2475 xfer->interval, xfer->max_packet_count, 2476 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2477 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2478 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2479 } 2480 2481 static usb_error_t 2482 xhci_configure_device(struct usb_device *udev) 2483 { 2484 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2485 struct usb_page_search buf_inp; 2486 struct usb_page_cache *pcinp; 2487 struct xhci_input_dev_ctx *pinp; 2488 struct usb_device *hubdev; 2489 uint32_t temp; 2490 uint32_t route; 2491 uint32_t rh_port; 2492 uint8_t is_hub; 2493 uint8_t index; 2494 uint8_t depth; 2495 2496 index = udev->controller_slot_id; 2497 2498 DPRINTF("index=%u\n", index); 2499 2500 pcinp = &sc->sc_hw.devs[index].input_pc; 2501 2502 usbd_get_page(pcinp, 0, &buf_inp); 2503 2504 pinp = buf_inp.buffer; 2505 2506 rh_port = 0; 2507 route = 0; 2508 2509 /* figure out route string and root HUB port number */ 2510 2511 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2512 2513 if (hubdev->parent_hub == NULL) 2514 break; 2515 2516 depth = hubdev->parent_hub->depth; 2517 2518 /* 2519 * NOTE: HS/FS/LS devices and the SS root HUB can have 2520 * more than 15 ports 2521 */ 2522 2523 rh_port = hubdev->port_no; 2524 2525 if (depth == 0) 2526 break; 2527 2528 if (rh_port > 15) 2529 rh_port = 15; 2530 2531 if (depth < 6) 2532 route |= rh_port << (4 * (depth - 1)); 2533 } 2534 2535 DPRINTF("Route=0x%08x\n", route); 2536 2537 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2538 XHCI_SCTX_0_CTX_NUM_SET( 2539 sc->sc_hw.devs[index].context_num + 1); 2540 2541 switch (udev->speed) { 2542 case USB_SPEED_LOW: 2543 temp |= XHCI_SCTX_0_SPEED_SET(2); 2544 if (udev->parent_hs_hub != NULL && 2545 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2546 UDPROTO_HSHUBMTT) { 2547 DPRINTF("Device inherits MTT\n"); 2548 temp |= XHCI_SCTX_0_MTT_SET(1); 2549 } 2550 break; 2551 case USB_SPEED_HIGH: 2552 temp |= XHCI_SCTX_0_SPEED_SET(3); 2553 if (sc->sc_hw.devs[index].nports != 0 && 2554 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2555 DPRINTF("HUB supports MTT\n"); 2556 temp |= XHCI_SCTX_0_MTT_SET(1); 2557 } 2558 break; 2559 case USB_SPEED_FULL: 2560 temp |= XHCI_SCTX_0_SPEED_SET(1); 2561 if (udev->parent_hs_hub != NULL && 2562 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2563 UDPROTO_HSHUBMTT) { 2564 DPRINTF("Device inherits MTT\n"); 2565 temp |= XHCI_SCTX_0_MTT_SET(1); 2566 } 2567 break; 2568 default: 2569 temp |= XHCI_SCTX_0_SPEED_SET(4); 2570 break; 2571 } 2572 2573 is_hub = sc->sc_hw.devs[index].nports != 0 && 2574 (udev->speed == USB_SPEED_SUPER || 2575 udev->speed == USB_SPEED_HIGH); 2576 2577 if (is_hub) 2578 temp |= XHCI_SCTX_0_HUB_SET(1); 2579 2580 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2581 2582 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2583 2584 if (is_hub) { 2585 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2586 sc->sc_hw.devs[index].nports); 2587 } 2588 2589 switch (udev->speed) { 2590 case USB_SPEED_SUPER: 2591 switch (sc->sc_hw.devs[index].state) { 2592 case XHCI_ST_ADDRESSED: 2593 case XHCI_ST_CONFIGURED: 2594 /* enable power save */ 2595 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2596 break; 2597 default: 2598 /* disable power save */ 2599 break; 2600 } 2601 break; 2602 default: 2603 break; 2604 } 2605 2606 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2607 2608 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2609 2610 if (is_hub) { 2611 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2612 sc->sc_hw.devs[index].tt); 2613 } 2614 2615 hubdev = udev->parent_hs_hub; 2616 2617 /* check if we should activate the transaction translator */ 2618 switch (udev->speed) { 2619 case USB_SPEED_FULL: 2620 case USB_SPEED_LOW: 2621 if (hubdev != NULL) { 2622 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2623 hubdev->controller_slot_id); 2624 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2625 udev->hs_port_no); 2626 } 2627 break; 2628 default: 2629 break; 2630 } 2631 2632 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2633 2634 /* 2635 * These fields should be initialized to zero, according to 2636 * XHCI section 6.2.2 - slot context: 2637 */ 2638 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2639 XHCI_SCTX_3_SLOT_STATE_SET(0); 2640 2641 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2642 2643 #ifdef USB_DEBUG 2644 xhci_dump_device(sc, &pinp->ctx_slot); 2645 #endif 2646 usb_pc_cpu_flush(pcinp); 2647 2648 return (0); /* success */ 2649 } 2650 2651 static usb_error_t 2652 xhci_alloc_device_ext(struct usb_device *udev) 2653 { 2654 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2655 struct usb_page_search buf_dev; 2656 struct usb_page_search buf_ep; 2657 struct xhci_trb *trb; 2658 struct usb_page_cache *pc; 2659 struct usb_page *pg; 2660 uint64_t addr; 2661 uint8_t index; 2662 uint8_t i; 2663 2664 index = udev->controller_slot_id; 2665 2666 pc = &sc->sc_hw.devs[index].device_pc; 2667 pg = &sc->sc_hw.devs[index].device_pg; 2668 2669 /* need to initialize the page cache */ 2670 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2671 2672 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2673 (2 * sizeof(struct xhci_dev_ctx)) : 2674 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2675 goto error; 2676 2677 usbd_get_page(pc, 0, &buf_dev); 2678 2679 pc = &sc->sc_hw.devs[index].input_pc; 2680 pg = &sc->sc_hw.devs[index].input_pg; 2681 2682 /* need to initialize the page cache */ 2683 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2684 2685 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2686 (2 * sizeof(struct xhci_input_dev_ctx)) : 2687 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2688 goto error; 2689 } 2690 2691 pc = &sc->sc_hw.devs[index].endpoint_pc; 2692 pg = &sc->sc_hw.devs[index].endpoint_pg; 2693 2694 /* need to initialize the page cache */ 2695 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2696 2697 if (usb_pc_alloc_mem(pc, pg, 2698 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) { 2699 goto error; 2700 } 2701 2702 /* initialise all endpoint LINK TRBs */ 2703 2704 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2705 2706 /* lookup endpoint TRB ring */ 2707 usbd_get_page(pc, (uintptr_t)& 2708 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2709 2710 /* get TRB pointer */ 2711 trb = buf_ep.buffer; 2712 trb += XHCI_MAX_TRANSFERS - 1; 2713 2714 /* get TRB start address */ 2715 addr = buf_ep.physaddr; 2716 2717 /* create LINK TRB */ 2718 trb->qwTrb0 = htole64(addr); 2719 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2720 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2721 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2722 } 2723 2724 usb_pc_cpu_flush(pc); 2725 2726 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2727 2728 return (0); 2729 2730 error: 2731 xhci_free_device_ext(udev); 2732 2733 return (USB_ERR_NOMEM); 2734 } 2735 2736 static void 2737 xhci_free_device_ext(struct usb_device *udev) 2738 { 2739 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2740 uint8_t index; 2741 2742 index = udev->controller_slot_id; 2743 xhci_set_slot_pointer(sc, index, 0); 2744 2745 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2746 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2747 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2748 } 2749 2750 static struct xhci_endpoint_ext * 2751 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2752 { 2753 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2754 struct xhci_endpoint_ext *pepext; 2755 struct usb_page_cache *pc; 2756 struct usb_page_search buf_ep; 2757 uint8_t epno; 2758 uint8_t index; 2759 2760 epno = edesc->bEndpointAddress; 2761 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2762 epno |= UE_DIR_IN; 2763 2764 epno = XHCI_EPNO2EPID(epno); 2765 2766 index = udev->controller_slot_id; 2767 2768 pc = &sc->sc_hw.devs[index].endpoint_pc; 2769 2770 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2771 trb[epno][0], &buf_ep); 2772 2773 pepext = &sc->sc_hw.devs[index].endp[epno]; 2774 pepext->page_cache = pc; 2775 pepext->trb = buf_ep.buffer; 2776 pepext->physaddr = buf_ep.physaddr; 2777 2778 return (pepext); 2779 } 2780 2781 static void 2782 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2783 { 2784 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2785 uint8_t epno; 2786 uint8_t index; 2787 2788 epno = xfer->endpointno; 2789 if (xfer->flags_int.control_xfr) 2790 epno |= UE_DIR_IN; 2791 2792 epno = XHCI_EPNO2EPID(epno); 2793 index = xfer->xroot->udev->controller_slot_id; 2794 2795 if (xfer->xroot->udev->flags.self_suspended == 0) { 2796 XWRITE4(sc, door, XHCI_DOORBELL(index), 2797 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2798 } 2799 } 2800 2801 static void 2802 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2803 { 2804 struct xhci_endpoint_ext *pepext; 2805 2806 if (xfer->flags_int.bandwidth_reclaimed) { 2807 xfer->flags_int.bandwidth_reclaimed = 0; 2808 2809 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2810 xfer->endpoint->edesc); 2811 2812 pepext->trb_used[xfer->stream_id]--; 2813 2814 pepext->xfer[xfer->qh_pos] = NULL; 2815 2816 if (error && pepext->trb_running != 0) { 2817 pepext->trb_halted = 1; 2818 pepext->trb_running = 0; 2819 } 2820 } 2821 } 2822 2823 static usb_error_t 2824 xhci_transfer_insert(struct usb_xfer *xfer) 2825 { 2826 struct xhci_td *td_first; 2827 struct xhci_td *td_last; 2828 struct xhci_trb *trb_link; 2829 struct xhci_endpoint_ext *pepext; 2830 uint64_t addr; 2831 usb_stream_t id; 2832 uint8_t i; 2833 uint8_t inext; 2834 uint8_t trb_limit; 2835 2836 DPRINTFN(8, "\n"); 2837 2838 id = xfer->stream_id; 2839 2840 /* check if already inserted */ 2841 if (xfer->flags_int.bandwidth_reclaimed) { 2842 DPRINTFN(8, "Already in schedule\n"); 2843 return (0); 2844 } 2845 2846 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2847 xfer->endpoint->edesc); 2848 2849 td_first = xfer->td_transfer_first; 2850 td_last = xfer->td_transfer_last; 2851 addr = pepext->physaddr; 2852 2853 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2854 case UE_CONTROL: 2855 case UE_INTERRUPT: 2856 /* single buffered */ 2857 trb_limit = 1; 2858 break; 2859 default: 2860 /* multi buffered */ 2861 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2862 break; 2863 } 2864 2865 if (pepext->trb_used[id] >= trb_limit) { 2866 DPRINTFN(8, "Too many TDs queued.\n"); 2867 return (USB_ERR_NOMEM); 2868 } 2869 2870 /* check for stopped condition, after putting transfer on interrupt queue */ 2871 if (pepext->trb_running == 0) { 2872 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2873 2874 DPRINTFN(8, "Not running\n"); 2875 2876 /* start configuration */ 2877 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2878 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2879 return (0); 2880 } 2881 2882 pepext->trb_used[id]++; 2883 2884 /* get current TRB index */ 2885 i = pepext->trb_index[id]; 2886 2887 /* get next TRB index */ 2888 inext = (i + 1); 2889 2890 /* the last entry of the ring is a hardcoded link TRB */ 2891 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2892 inext = 0; 2893 2894 /* store next TRB index, before stream ID offset is added */ 2895 pepext->trb_index[id] = inext; 2896 2897 /* offset for stream */ 2898 i += id * XHCI_MAX_TRANSFERS; 2899 inext += id * XHCI_MAX_TRANSFERS; 2900 2901 /* compute terminating return address */ 2902 addr += (inext * sizeof(struct xhci_trb)); 2903 2904 /* compute link TRB pointer */ 2905 trb_link = td_last->td_trb + td_last->ntrb; 2906 2907 /* update next pointer of last link TRB */ 2908 trb_link->qwTrb0 = htole64(addr); 2909 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2910 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2911 XHCI_TRB_3_CYCLE_BIT | 2912 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2913 2914 #ifdef USB_DEBUG 2915 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2916 #endif 2917 usb_pc_cpu_flush(td_last->page_cache); 2918 2919 /* write ahead chain end marker */ 2920 2921 pepext->trb[inext].qwTrb0 = 0; 2922 pepext->trb[inext].dwTrb2 = 0; 2923 pepext->trb[inext].dwTrb3 = 0; 2924 2925 /* update next pointer of link TRB */ 2926 2927 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2928 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2929 2930 #ifdef USB_DEBUG 2931 xhci_dump_trb(&pepext->trb[i]); 2932 #endif 2933 usb_pc_cpu_flush(pepext->page_cache); 2934 2935 /* toggle cycle bit which activates the transfer chain */ 2936 2937 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2938 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2939 2940 usb_pc_cpu_flush(pepext->page_cache); 2941 2942 DPRINTF("qh_pos = %u\n", i); 2943 2944 pepext->xfer[i] = xfer; 2945 2946 xfer->qh_pos = i; 2947 2948 xfer->flags_int.bandwidth_reclaimed = 1; 2949 2950 xhci_endpoint_doorbell(xfer); 2951 2952 return (0); 2953 } 2954 2955 static void 2956 xhci_root_intr(struct xhci_softc *sc) 2957 { 2958 uint16_t i; 2959 2960 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2961 2962 /* clear any old interrupt data */ 2963 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2964 2965 for (i = 1; i <= sc->sc_noport; i++) { 2966 /* pick out CHANGE bits from the status register */ 2967 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2968 XHCI_PS_CSC | XHCI_PS_PEC | 2969 XHCI_PS_OCC | XHCI_PS_WRC | 2970 XHCI_PS_PRC | XHCI_PS_PLC | 2971 XHCI_PS_CEC)) { 2972 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2973 DPRINTF("port %d changed\n", i); 2974 } 2975 } 2976 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2977 sizeof(sc->sc_hub_idata)); 2978 } 2979 2980 /*------------------------------------------------------------------------* 2981 * xhci_device_done - XHCI done handler 2982 * 2983 * NOTE: This function can be called two times in a row on 2984 * the same USB transfer. From close and from interrupt. 2985 *------------------------------------------------------------------------*/ 2986 static void 2987 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2988 { 2989 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2990 xfer, xfer->endpoint, error); 2991 2992 /* remove transfer from HW queue */ 2993 xhci_transfer_remove(xfer, error); 2994 2995 /* dequeue transfer and start next transfer */ 2996 usbd_transfer_done(xfer, error); 2997 } 2998 2999 /*------------------------------------------------------------------------* 3000 * XHCI data transfer support (generic type) 3001 *------------------------------------------------------------------------*/ 3002 static void 3003 xhci_device_generic_open(struct usb_xfer *xfer) 3004 { 3005 if (xfer->flags_int.isochronous_xfr) { 3006 switch (xfer->xroot->udev->speed) { 3007 case USB_SPEED_FULL: 3008 break; 3009 default: 3010 usb_hs_bandwidth_alloc(xfer); 3011 break; 3012 } 3013 } 3014 } 3015 3016 static void 3017 xhci_device_generic_close(struct usb_xfer *xfer) 3018 { 3019 DPRINTF("\n"); 3020 3021 xhci_device_done(xfer, USB_ERR_CANCELLED); 3022 3023 if (xfer->flags_int.isochronous_xfr) { 3024 switch (xfer->xroot->udev->speed) { 3025 case USB_SPEED_FULL: 3026 break; 3027 default: 3028 usb_hs_bandwidth_free(xfer); 3029 break; 3030 } 3031 } 3032 } 3033 3034 static void 3035 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3036 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3037 { 3038 struct usb_xfer *xfer; 3039 3040 /* check if there is a current transfer */ 3041 xfer = ep->endpoint_q[stream_id].curr; 3042 if (xfer == NULL) 3043 return; 3044 3045 /* 3046 * Check if the current transfer is started and then pickup 3047 * the next one, if any. Else wait for next start event due to 3048 * block on failure feature. 3049 */ 3050 if (!xfer->flags_int.bandwidth_reclaimed) 3051 return; 3052 3053 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3054 if (xfer == NULL) { 3055 /* 3056 * In case of enter we have to consider that the 3057 * transfer is queued by the USB core after the enter 3058 * method is called. 3059 */ 3060 xfer = enter_xfer; 3061 3062 if (xfer == NULL) 3063 return; 3064 } 3065 3066 /* try to multi buffer */ 3067 xhci_transfer_insert(xfer); 3068 } 3069 3070 static void 3071 xhci_device_generic_enter(struct usb_xfer *xfer) 3072 { 3073 DPRINTF("\n"); 3074 3075 /* setup TD's and QH */ 3076 xhci_setup_generic_chain(xfer); 3077 3078 xhci_device_generic_multi_enter(xfer->endpoint, 3079 xfer->stream_id, xfer); 3080 } 3081 3082 static void 3083 xhci_device_generic_start(struct usb_xfer *xfer) 3084 { 3085 DPRINTF("\n"); 3086 3087 /* try to insert xfer on HW queue */ 3088 xhci_transfer_insert(xfer); 3089 3090 /* try to multi buffer */ 3091 xhci_device_generic_multi_enter(xfer->endpoint, 3092 xfer->stream_id, NULL); 3093 3094 /* add transfer last on interrupt queue */ 3095 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3096 3097 /* start timeout, if any */ 3098 if (xfer->timeout != 0) 3099 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3100 } 3101 3102 static const struct usb_pipe_methods xhci_device_generic_methods = 3103 { 3104 .open = xhci_device_generic_open, 3105 .close = xhci_device_generic_close, 3106 .enter = xhci_device_generic_enter, 3107 .start = xhci_device_generic_start, 3108 }; 3109 3110 /*------------------------------------------------------------------------* 3111 * xhci root HUB support 3112 *------------------------------------------------------------------------* 3113 * Simulate a hardware HUB by handling all the necessary requests. 3114 *------------------------------------------------------------------------*/ 3115 3116 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3117 3118 static const 3119 struct usb_device_descriptor xhci_devd = 3120 { 3121 .bLength = sizeof(xhci_devd), 3122 .bDescriptorType = UDESC_DEVICE, /* type */ 3123 HSETW(.bcdUSB, 0x0300), /* USB version */ 3124 .bDeviceClass = UDCLASS_HUB, /* class */ 3125 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3126 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3127 .bMaxPacketSize = 9, /* max packet size */ 3128 HSETW(.idVendor, 0x0000), /* vendor */ 3129 HSETW(.idProduct, 0x0000), /* product */ 3130 HSETW(.bcdDevice, 0x0100), /* device version */ 3131 .iManufacturer = 1, 3132 .iProduct = 2, 3133 .iSerialNumber = 0, 3134 .bNumConfigurations = 1, /* # of configurations */ 3135 }; 3136 3137 static const 3138 struct xhci_bos_desc xhci_bosd = { 3139 .bosd = { 3140 .bLength = sizeof(xhci_bosd.bosd), 3141 .bDescriptorType = UDESC_BOS, 3142 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3143 .bNumDeviceCaps = 3, 3144 }, 3145 .usb2extd = { 3146 .bLength = sizeof(xhci_bosd.usb2extd), 3147 .bDescriptorType = 1, 3148 .bDevCapabilityType = 2, 3149 .bmAttributes[0] = 2, 3150 }, 3151 .usbdcd = { 3152 .bLength = sizeof(xhci_bosd.usbdcd), 3153 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3154 .bDevCapabilityType = 3, 3155 .bmAttributes = 0, /* XXX */ 3156 HSETW(.wSpeedsSupported, 0x000C), 3157 .bFunctionalitySupport = 8, 3158 .bU1DevExitLat = 255, /* dummy - not used */ 3159 .wU2DevExitLat = { 0x00, 0x08 }, 3160 }, 3161 .cidd = { 3162 .bLength = sizeof(xhci_bosd.cidd), 3163 .bDescriptorType = 1, 3164 .bDevCapabilityType = 4, 3165 .bReserved = 0, 3166 .bContainerID = 0, /* XXX */ 3167 }, 3168 }; 3169 3170 static const 3171 struct xhci_config_desc xhci_confd = { 3172 .confd = { 3173 .bLength = sizeof(xhci_confd.confd), 3174 .bDescriptorType = UDESC_CONFIG, 3175 .wTotalLength[0] = sizeof(xhci_confd), 3176 .bNumInterface = 1, 3177 .bConfigurationValue = 1, 3178 .iConfiguration = 0, 3179 .bmAttributes = UC_SELF_POWERED, 3180 .bMaxPower = 0 /* max power */ 3181 }, 3182 .ifcd = { 3183 .bLength = sizeof(xhci_confd.ifcd), 3184 .bDescriptorType = UDESC_INTERFACE, 3185 .bNumEndpoints = 1, 3186 .bInterfaceClass = UICLASS_HUB, 3187 .bInterfaceSubClass = UISUBCLASS_HUB, 3188 .bInterfaceProtocol = 0, 3189 }, 3190 .endpd = { 3191 .bLength = sizeof(xhci_confd.endpd), 3192 .bDescriptorType = UDESC_ENDPOINT, 3193 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3194 .bmAttributes = UE_INTERRUPT, 3195 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3196 .bInterval = 255, 3197 }, 3198 .endpcd = { 3199 .bLength = sizeof(xhci_confd.endpcd), 3200 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3201 .bMaxBurst = 0, 3202 .bmAttributes = 0, 3203 }, 3204 }; 3205 3206 static const 3207 struct usb_hub_ss_descriptor xhci_hubd = { 3208 .bLength = sizeof(xhci_hubd), 3209 .bDescriptorType = UDESC_SS_HUB, 3210 }; 3211 3212 static usb_error_t 3213 xhci_roothub_exec(struct usb_device *udev, 3214 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3215 { 3216 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3217 const char *str_ptr; 3218 const void *ptr; 3219 uint32_t port; 3220 uint32_t v; 3221 uint16_t len; 3222 uint16_t i; 3223 uint16_t value; 3224 uint16_t index; 3225 uint8_t j; 3226 usb_error_t err; 3227 3228 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3229 3230 /* buffer reset */ 3231 ptr = (const void *)&sc->sc_hub_desc; 3232 len = 0; 3233 err = 0; 3234 3235 value = UGETW(req->wValue); 3236 index = UGETW(req->wIndex); 3237 3238 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3239 "wValue=0x%04x wIndex=0x%04x\n", 3240 req->bmRequestType, req->bRequest, 3241 UGETW(req->wLength), value, index); 3242 3243 #define C(x,y) ((x) | ((y) << 8)) 3244 switch (C(req->bRequest, req->bmRequestType)) { 3245 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3246 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3247 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3248 /* 3249 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3250 * for the integrated root hub. 3251 */ 3252 break; 3253 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3254 len = 1; 3255 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3256 break; 3257 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3258 switch (value >> 8) { 3259 case UDESC_DEVICE: 3260 if ((value & 0xff) != 0) { 3261 err = USB_ERR_IOERROR; 3262 goto done; 3263 } 3264 len = sizeof(xhci_devd); 3265 ptr = (const void *)&xhci_devd; 3266 break; 3267 3268 case UDESC_BOS: 3269 if ((value & 0xff) != 0) { 3270 err = USB_ERR_IOERROR; 3271 goto done; 3272 } 3273 len = sizeof(xhci_bosd); 3274 ptr = (const void *)&xhci_bosd; 3275 break; 3276 3277 case UDESC_CONFIG: 3278 if ((value & 0xff) != 0) { 3279 err = USB_ERR_IOERROR; 3280 goto done; 3281 } 3282 len = sizeof(xhci_confd); 3283 ptr = (const void *)&xhci_confd; 3284 break; 3285 3286 case UDESC_STRING: 3287 switch (value & 0xff) { 3288 case 0: /* Language table */ 3289 str_ptr = "\001"; 3290 break; 3291 3292 case 1: /* Vendor */ 3293 str_ptr = sc->sc_vendor; 3294 break; 3295 3296 case 2: /* Product */ 3297 str_ptr = "XHCI root HUB"; 3298 break; 3299 3300 default: 3301 str_ptr = ""; 3302 break; 3303 } 3304 3305 len = usb_make_str_desc( 3306 sc->sc_hub_desc.temp, 3307 sizeof(sc->sc_hub_desc.temp), 3308 str_ptr); 3309 break; 3310 3311 default: 3312 err = USB_ERR_IOERROR; 3313 goto done; 3314 } 3315 break; 3316 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3317 len = 1; 3318 sc->sc_hub_desc.temp[0] = 0; 3319 break; 3320 case C(UR_GET_STATUS, UT_READ_DEVICE): 3321 len = 2; 3322 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3323 break; 3324 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3325 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3326 len = 2; 3327 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3328 break; 3329 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3330 if (value >= XHCI_MAX_DEVICES) { 3331 err = USB_ERR_IOERROR; 3332 goto done; 3333 } 3334 break; 3335 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3336 if (value != 0 && value != 1) { 3337 err = USB_ERR_IOERROR; 3338 goto done; 3339 } 3340 sc->sc_conf = value; 3341 break; 3342 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3343 break; 3344 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3345 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3346 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3347 err = USB_ERR_IOERROR; 3348 goto done; 3349 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3350 break; 3351 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3352 break; 3353 /* Hub requests */ 3354 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3355 break; 3356 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3357 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3358 3359 if ((index < 1) || 3360 (index > sc->sc_noport)) { 3361 err = USB_ERR_IOERROR; 3362 goto done; 3363 } 3364 port = XHCI_PORTSC(index); 3365 3366 v = XREAD4(sc, oper, port); 3367 i = XHCI_PS_PLS_GET(v); 3368 v &= ~XHCI_PS_CLEAR; 3369 3370 switch (value) { 3371 case UHF_C_BH_PORT_RESET: 3372 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3373 break; 3374 case UHF_C_PORT_CONFIG_ERROR: 3375 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3376 break; 3377 case UHF_C_PORT_SUSPEND: 3378 case UHF_C_PORT_LINK_STATE: 3379 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3380 break; 3381 case UHF_C_PORT_CONNECTION: 3382 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3383 break; 3384 case UHF_C_PORT_ENABLE: 3385 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3386 break; 3387 case UHF_C_PORT_OVER_CURRENT: 3388 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3389 break; 3390 case UHF_C_PORT_RESET: 3391 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3392 break; 3393 case UHF_PORT_ENABLE: 3394 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3395 break; 3396 case UHF_PORT_POWER: 3397 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3398 break; 3399 case UHF_PORT_INDICATOR: 3400 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3401 break; 3402 case UHF_PORT_SUSPEND: 3403 3404 /* U3 -> U15 */ 3405 if (i == 3) { 3406 XWRITE4(sc, oper, port, v | 3407 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3408 } 3409 3410 /* wait 20ms for resume sequence to complete */ 3411 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3412 3413 /* U0 */ 3414 XWRITE4(sc, oper, port, v | 3415 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3416 break; 3417 default: 3418 err = USB_ERR_IOERROR; 3419 goto done; 3420 } 3421 break; 3422 3423 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3424 if ((value & 0xff) != 0) { 3425 err = USB_ERR_IOERROR; 3426 goto done; 3427 } 3428 3429 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3430 3431 sc->sc_hub_desc.hubd = xhci_hubd; 3432 3433 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3434 3435 if (XHCI_HCS0_PPC(v)) 3436 i = UHD_PWR_INDIVIDUAL; 3437 else 3438 i = UHD_PWR_GANGED; 3439 3440 if (XHCI_HCS0_PIND(v)) 3441 i |= UHD_PORT_IND; 3442 3443 i |= UHD_OC_INDIVIDUAL; 3444 3445 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3446 3447 /* see XHCI section 5.4.9: */ 3448 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3449 3450 for (j = 1; j <= sc->sc_noport; j++) { 3451 3452 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3453 if (v & XHCI_PS_DR) { 3454 sc->sc_hub_desc.hubd. 3455 DeviceRemovable[j / 8] |= 1U << (j % 8); 3456 } 3457 } 3458 len = sc->sc_hub_desc.hubd.bLength; 3459 break; 3460 3461 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3462 len = 16; 3463 memset(sc->sc_hub_desc.temp, 0, 16); 3464 break; 3465 3466 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3467 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3468 3469 if ((index < 1) || 3470 (index > sc->sc_noport)) { 3471 err = USB_ERR_IOERROR; 3472 goto done; 3473 } 3474 3475 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3476 3477 DPRINTFN(9, "port status=0x%08x\n", v); 3478 3479 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3480 3481 switch (XHCI_PS_SPEED_GET(v)) { 3482 case 3: 3483 i |= UPS_HIGH_SPEED; 3484 break; 3485 case 2: 3486 i |= UPS_LOW_SPEED; 3487 break; 3488 case 1: 3489 /* FULL speed */ 3490 break; 3491 default: 3492 i |= UPS_OTHER_SPEED; 3493 break; 3494 } 3495 3496 if (v & XHCI_PS_CCS) 3497 i |= UPS_CURRENT_CONNECT_STATUS; 3498 if (v & XHCI_PS_PED) 3499 i |= UPS_PORT_ENABLED; 3500 if (v & XHCI_PS_OCA) 3501 i |= UPS_OVERCURRENT_INDICATOR; 3502 if (v & XHCI_PS_PR) 3503 i |= UPS_RESET; 3504 if (v & XHCI_PS_PP) { 3505 /* 3506 * The USB 3.0 RH is using the 3507 * USB 2.0's power bit 3508 */ 3509 i |= UPS_PORT_POWER; 3510 } 3511 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3512 3513 i = 0; 3514 if (v & XHCI_PS_CSC) 3515 i |= UPS_C_CONNECT_STATUS; 3516 if (v & XHCI_PS_PEC) 3517 i |= UPS_C_PORT_ENABLED; 3518 if (v & XHCI_PS_OCC) 3519 i |= UPS_C_OVERCURRENT_INDICATOR; 3520 if (v & XHCI_PS_WRC) 3521 i |= UPS_C_BH_PORT_RESET; 3522 if (v & XHCI_PS_PRC) 3523 i |= UPS_C_PORT_RESET; 3524 if (v & XHCI_PS_PLC) 3525 i |= UPS_C_PORT_LINK_STATE; 3526 if (v & XHCI_PS_CEC) 3527 i |= UPS_C_PORT_CONFIG_ERROR; 3528 3529 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3530 len = sizeof(sc->sc_hub_desc.ps); 3531 break; 3532 3533 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3534 err = USB_ERR_IOERROR; 3535 goto done; 3536 3537 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3538 break; 3539 3540 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3541 3542 i = index >> 8; 3543 index &= 0x00FF; 3544 3545 if ((index < 1) || 3546 (index > sc->sc_noport)) { 3547 err = USB_ERR_IOERROR; 3548 goto done; 3549 } 3550 3551 port = XHCI_PORTSC(index); 3552 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3553 3554 switch (value) { 3555 case UHF_PORT_U1_TIMEOUT: 3556 if (XHCI_PS_SPEED_GET(v) != 4) { 3557 err = USB_ERR_IOERROR; 3558 goto done; 3559 } 3560 port = XHCI_PORTPMSC(index); 3561 v = XREAD4(sc, oper, port); 3562 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3563 v |= XHCI_PM3_U1TO_SET(i); 3564 XWRITE4(sc, oper, port, v); 3565 break; 3566 case UHF_PORT_U2_TIMEOUT: 3567 if (XHCI_PS_SPEED_GET(v) != 4) { 3568 err = USB_ERR_IOERROR; 3569 goto done; 3570 } 3571 port = XHCI_PORTPMSC(index); 3572 v = XREAD4(sc, oper, port); 3573 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3574 v |= XHCI_PM3_U2TO_SET(i); 3575 XWRITE4(sc, oper, port, v); 3576 break; 3577 case UHF_BH_PORT_RESET: 3578 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3579 break; 3580 case UHF_PORT_LINK_STATE: 3581 XWRITE4(sc, oper, port, v | 3582 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3583 /* 4ms settle time */ 3584 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3585 break; 3586 case UHF_PORT_ENABLE: 3587 DPRINTFN(3, "set port enable %d\n", index); 3588 break; 3589 case UHF_PORT_SUSPEND: 3590 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3591 j = XHCI_PS_SPEED_GET(v); 3592 if ((j < 1) || (j > 3)) { 3593 /* non-supported speed */ 3594 err = USB_ERR_IOERROR; 3595 goto done; 3596 } 3597 XWRITE4(sc, oper, port, v | 3598 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3599 break; 3600 case UHF_PORT_RESET: 3601 DPRINTFN(6, "reset port %d\n", index); 3602 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3603 break; 3604 case UHF_PORT_POWER: 3605 DPRINTFN(3, "set port power %d\n", index); 3606 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3607 break; 3608 case UHF_PORT_TEST: 3609 DPRINTFN(3, "set port test %d\n", index); 3610 break; 3611 case UHF_PORT_INDICATOR: 3612 DPRINTFN(3, "set port indicator %d\n", index); 3613 3614 v &= ~XHCI_PS_PIC_SET(3); 3615 v |= XHCI_PS_PIC_SET(1); 3616 3617 XWRITE4(sc, oper, port, v); 3618 break; 3619 default: 3620 err = USB_ERR_IOERROR; 3621 goto done; 3622 } 3623 break; 3624 3625 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3626 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3627 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3628 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3629 break; 3630 default: 3631 err = USB_ERR_IOERROR; 3632 goto done; 3633 } 3634 done: 3635 *plength = len; 3636 *pptr = ptr; 3637 return (err); 3638 } 3639 3640 static void 3641 xhci_xfer_setup(struct usb_setup_params *parm) 3642 { 3643 struct usb_page_search page_info; 3644 struct usb_page_cache *pc; 3645 struct xhci_softc *sc; 3646 struct usb_xfer *xfer; 3647 void *last_obj; 3648 uint32_t ntd; 3649 uint32_t n; 3650 3651 sc = XHCI_BUS2SC(parm->udev->bus); 3652 xfer = parm->curr_xfer; 3653 3654 /* 3655 * The proof for the "ntd" formula is illustrated like this: 3656 * 3657 * +------------------------------------+ 3658 * | | 3659 * | |remainder -> | 3660 * | +-----+---+ | 3661 * | | xxx | x | frm 0 | 3662 * | +-----+---++ | 3663 * | | xxx | xx | frm 1 | 3664 * | +-----+----+ | 3665 * | ... | 3666 * +------------------------------------+ 3667 * 3668 * "xxx" means a completely full USB transfer descriptor 3669 * 3670 * "x" and "xx" means a short USB packet 3671 * 3672 * For the remainder of an USB transfer modulo 3673 * "max_data_length" we need two USB transfer descriptors. 3674 * One to transfer the remaining data and one to finalise with 3675 * a zero length packet in case the "force_short_xfer" flag is 3676 * set. We only need two USB transfer descriptors in the case 3677 * where the transfer length of the first one is a factor of 3678 * "max_frame_size". The rest of the needed USB transfer 3679 * descriptors is given by the buffer size divided by the 3680 * maximum data payload. 3681 */ 3682 parm->hc_max_packet_size = 0x400; 3683 parm->hc_max_packet_count = 16 * 3; 3684 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3685 3686 xfer->flags_int.bdma_enable = 1; 3687 3688 usbd_transfer_setup_sub(parm); 3689 3690 if (xfer->flags_int.isochronous_xfr) { 3691 ntd = ((1 * xfer->nframes) 3692 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3693 } else if (xfer->flags_int.control_xfr) { 3694 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3695 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3696 } else { 3697 ntd = ((2 * xfer->nframes) 3698 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3699 } 3700 3701 alloc_dma_set: 3702 3703 if (parm->err) 3704 return; 3705 3706 /* 3707 * Allocate queue heads and transfer descriptors 3708 */ 3709 last_obj = NULL; 3710 3711 if (usbd_transfer_setup_sub_malloc( 3712 parm, &pc, sizeof(struct xhci_td), 3713 XHCI_TD_ALIGN, ntd)) { 3714 parm->err = USB_ERR_NOMEM; 3715 return; 3716 } 3717 if (parm->buf) { 3718 for (n = 0; n != ntd; n++) { 3719 struct xhci_td *td; 3720 3721 usbd_get_page(pc + n, 0, &page_info); 3722 3723 td = page_info.buffer; 3724 3725 /* init TD */ 3726 td->td_self = page_info.physaddr; 3727 td->obj_next = last_obj; 3728 td->page_cache = pc + n; 3729 3730 last_obj = td; 3731 3732 usb_pc_cpu_flush(pc + n); 3733 } 3734 } 3735 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3736 3737 if (!xfer->flags_int.curr_dma_set) { 3738 xfer->flags_int.curr_dma_set = 1; 3739 goto alloc_dma_set; 3740 } 3741 } 3742 3743 static usb_error_t 3744 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3745 { 3746 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3747 struct usb_page_search buf_inp; 3748 struct usb_device *udev; 3749 struct xhci_endpoint_ext *pepext; 3750 struct usb_endpoint_descriptor *edesc; 3751 struct usb_page_cache *pcinp; 3752 usb_error_t err; 3753 usb_stream_t stream_id; 3754 uint8_t index; 3755 uint8_t epno; 3756 3757 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3758 xfer->endpoint->edesc); 3759 3760 udev = xfer->xroot->udev; 3761 index = udev->controller_slot_id; 3762 3763 pcinp = &sc->sc_hw.devs[index].input_pc; 3764 3765 usbd_get_page(pcinp, 0, &buf_inp); 3766 3767 edesc = xfer->endpoint->edesc; 3768 3769 epno = edesc->bEndpointAddress; 3770 stream_id = xfer->stream_id; 3771 3772 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3773 epno |= UE_DIR_IN; 3774 3775 epno = XHCI_EPNO2EPID(epno); 3776 3777 if (epno == 0) 3778 return (USB_ERR_NO_PIPE); /* invalid */ 3779 3780 XHCI_CMD_LOCK(sc); 3781 3782 /* configure endpoint */ 3783 3784 err = xhci_configure_endpoint_by_xfer(xfer); 3785 3786 if (err != 0) { 3787 XHCI_CMD_UNLOCK(sc); 3788 return (err); 3789 } 3790 3791 /* 3792 * Get the endpoint into the stopped state according to the 3793 * endpoint context state diagram in the XHCI specification: 3794 */ 3795 3796 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3797 3798 if (err != 0) 3799 DPRINTF("Could not stop endpoint %u\n", epno); 3800 3801 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3802 3803 if (err != 0) 3804 DPRINTF("Could not reset endpoint %u\n", epno); 3805 3806 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3807 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3808 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3809 stream_id, epno, index); 3810 3811 if (err != 0) 3812 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3813 3814 /* 3815 * Get the endpoint into the running state according to the 3816 * endpoint context state diagram in the XHCI specification: 3817 */ 3818 3819 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3820 3821 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3822 3823 if (err != 0) 3824 DPRINTF("Could not configure endpoint %u\n", epno); 3825 3826 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3827 3828 if (err != 0) 3829 DPRINTF("Could not configure endpoint %u\n", epno); 3830 3831 XHCI_CMD_UNLOCK(sc); 3832 3833 return (0); 3834 } 3835 3836 static void 3837 xhci_xfer_unsetup(struct usb_xfer *xfer) 3838 { 3839 return; 3840 } 3841 3842 static void 3843 xhci_start_dma_delay(struct usb_xfer *xfer) 3844 { 3845 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3846 3847 /* put transfer on interrupt queue (again) */ 3848 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3849 3850 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3851 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3852 } 3853 3854 static void 3855 xhci_configure_msg(struct usb_proc_msg *pm) 3856 { 3857 struct xhci_softc *sc; 3858 struct xhci_endpoint_ext *pepext; 3859 struct usb_xfer *xfer; 3860 3861 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3862 3863 restart: 3864 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3865 3866 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3867 xfer->endpoint->edesc); 3868 3869 if ((pepext->trb_halted != 0) || 3870 (pepext->trb_running == 0)) { 3871 3872 uint16_t i; 3873 3874 /* clear halted and running */ 3875 pepext->trb_halted = 0; 3876 pepext->trb_running = 0; 3877 3878 /* nuke remaining buffered transfers */ 3879 3880 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3881 XHCI_MAX_STREAMS); i++) { 3882 /* 3883 * NOTE: We need to use the timeout 3884 * error code here else existing 3885 * isochronous clients can get 3886 * confused: 3887 */ 3888 if (pepext->xfer[i] != NULL) { 3889 xhci_device_done(pepext->xfer[i], 3890 USB_ERR_TIMEOUT); 3891 } 3892 } 3893 3894 /* 3895 * NOTE: The USB transfer cannot vanish in 3896 * this state! 3897 */ 3898 3899 USB_BUS_UNLOCK(&sc->sc_bus); 3900 3901 xhci_configure_reset_endpoint(xfer); 3902 3903 USB_BUS_LOCK(&sc->sc_bus); 3904 3905 /* check if halted is still cleared */ 3906 if (pepext->trb_halted == 0) { 3907 pepext->trb_running = 1; 3908 memset(pepext->trb_index, 0, 3909 sizeof(pepext->trb_index)); 3910 } 3911 goto restart; 3912 } 3913 3914 if (xfer->flags_int.did_dma_delay) { 3915 3916 /* remove transfer from interrupt queue (again) */ 3917 usbd_transfer_dequeue(xfer); 3918 3919 /* we are finally done */ 3920 usb_dma_delay_done_cb(xfer); 3921 3922 /* queue changed - restart */ 3923 goto restart; 3924 } 3925 } 3926 3927 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3928 3929 /* try to insert xfer on HW queue */ 3930 xhci_transfer_insert(xfer); 3931 3932 /* try to multi buffer */ 3933 xhci_device_generic_multi_enter(xfer->endpoint, 3934 xfer->stream_id, NULL); 3935 } 3936 } 3937 3938 static void 3939 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3940 struct usb_endpoint *ep) 3941 { 3942 struct xhci_endpoint_ext *pepext; 3943 3944 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3945 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3946 3947 if (udev->parent_hub == NULL) { 3948 /* root HUB has special endpoint handling */ 3949 return; 3950 } 3951 3952 ep->methods = &xhci_device_generic_methods; 3953 3954 pepext = xhci_get_endpoint_ext(udev, edesc); 3955 3956 USB_BUS_LOCK(udev->bus); 3957 pepext->trb_halted = 1; 3958 pepext->trb_running = 0; 3959 USB_BUS_UNLOCK(udev->bus); 3960 } 3961 3962 static void 3963 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3964 { 3965 3966 } 3967 3968 static void 3969 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3970 { 3971 struct xhci_endpoint_ext *pepext; 3972 3973 DPRINTF("\n"); 3974 3975 if (udev->flags.usb_mode != USB_MODE_HOST) { 3976 /* not supported */ 3977 return; 3978 } 3979 if (udev->parent_hub == NULL) { 3980 /* root HUB has special endpoint handling */ 3981 return; 3982 } 3983 3984 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3985 3986 USB_BUS_LOCK(udev->bus); 3987 pepext->trb_halted = 1; 3988 pepext->trb_running = 0; 3989 USB_BUS_UNLOCK(udev->bus); 3990 } 3991 3992 static usb_error_t 3993 xhci_device_init(struct usb_device *udev) 3994 { 3995 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3996 usb_error_t err; 3997 uint8_t temp; 3998 3999 /* no init for root HUB */ 4000 if (udev->parent_hub == NULL) 4001 return (0); 4002 4003 XHCI_CMD_LOCK(sc); 4004 4005 /* set invalid default */ 4006 4007 udev->controller_slot_id = sc->sc_noslot + 1; 4008 4009 /* try to get a new slot ID from the XHCI */ 4010 4011 err = xhci_cmd_enable_slot(sc, &temp); 4012 4013 if (err) { 4014 XHCI_CMD_UNLOCK(sc); 4015 return (err); 4016 } 4017 4018 if (temp > sc->sc_noslot) { 4019 XHCI_CMD_UNLOCK(sc); 4020 return (USB_ERR_BAD_ADDRESS); 4021 } 4022 4023 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4024 DPRINTF("slot %u already allocated.\n", temp); 4025 XHCI_CMD_UNLOCK(sc); 4026 return (USB_ERR_BAD_ADDRESS); 4027 } 4028 4029 /* store slot ID for later reference */ 4030 4031 udev->controller_slot_id = temp; 4032 4033 /* reset data structure */ 4034 4035 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4036 4037 /* set mark slot allocated */ 4038 4039 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4040 4041 err = xhci_alloc_device_ext(udev); 4042 4043 XHCI_CMD_UNLOCK(sc); 4044 4045 /* get device into default state */ 4046 4047 if (err == 0) 4048 err = xhci_set_address(udev, NULL, 0); 4049 4050 return (err); 4051 } 4052 4053 static void 4054 xhci_device_uninit(struct usb_device *udev) 4055 { 4056 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4057 uint8_t index; 4058 4059 /* no init for root HUB */ 4060 if (udev->parent_hub == NULL) 4061 return; 4062 4063 XHCI_CMD_LOCK(sc); 4064 4065 index = udev->controller_slot_id; 4066 4067 if (index <= sc->sc_noslot) { 4068 xhci_cmd_disable_slot(sc, index); 4069 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4070 4071 /* free device extension */ 4072 xhci_free_device_ext(udev); 4073 } 4074 4075 XHCI_CMD_UNLOCK(sc); 4076 } 4077 4078 static void 4079 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4080 { 4081 /* 4082 * Wait until the hardware has finished any possible use of 4083 * the transfer descriptor(s) 4084 */ 4085 *pus = 2048; /* microseconds */ 4086 } 4087 4088 static void 4089 xhci_device_resume(struct usb_device *udev) 4090 { 4091 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4092 uint8_t index; 4093 uint8_t n; 4094 uint8_t p; 4095 4096 DPRINTF("\n"); 4097 4098 /* check for root HUB */ 4099 if (udev->parent_hub == NULL) 4100 return; 4101 4102 index = udev->controller_slot_id; 4103 4104 XHCI_CMD_LOCK(sc); 4105 4106 /* blindly resume all endpoints */ 4107 4108 USB_BUS_LOCK(udev->bus); 4109 4110 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4111 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4112 XWRITE4(sc, door, XHCI_DOORBELL(index), 4113 n | XHCI_DB_SID_SET(p)); 4114 } 4115 } 4116 4117 USB_BUS_UNLOCK(udev->bus); 4118 4119 XHCI_CMD_UNLOCK(sc); 4120 } 4121 4122 static void 4123 xhci_device_suspend(struct usb_device *udev) 4124 { 4125 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4126 uint8_t index; 4127 uint8_t n; 4128 usb_error_t err; 4129 4130 DPRINTF("\n"); 4131 4132 /* check for root HUB */ 4133 if (udev->parent_hub == NULL) 4134 return; 4135 4136 index = udev->controller_slot_id; 4137 4138 XHCI_CMD_LOCK(sc); 4139 4140 /* blindly suspend all endpoints */ 4141 4142 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4143 err = xhci_cmd_stop_ep(sc, 1, n, index); 4144 if (err != 0) { 4145 DPRINTF("Failed to suspend endpoint " 4146 "%u on slot %u (ignored).\n", n, index); 4147 } 4148 } 4149 4150 XHCI_CMD_UNLOCK(sc); 4151 } 4152 4153 static void 4154 xhci_set_hw_power(struct usb_bus *bus) 4155 { 4156 DPRINTF("\n"); 4157 } 4158 4159 static void 4160 xhci_device_state_change(struct usb_device *udev) 4161 { 4162 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4163 struct usb_page_search buf_inp; 4164 usb_error_t err; 4165 uint8_t index; 4166 4167 /* check for root HUB */ 4168 if (udev->parent_hub == NULL) 4169 return; 4170 4171 index = udev->controller_slot_id; 4172 4173 DPRINTF("\n"); 4174 4175 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4176 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4177 &sc->sc_hw.devs[index].tt); 4178 if (err != 0) 4179 sc->sc_hw.devs[index].nports = 0; 4180 } 4181 4182 XHCI_CMD_LOCK(sc); 4183 4184 switch (usb_get_device_state(udev)) { 4185 case USB_STATE_POWERED: 4186 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4187 break; 4188 4189 /* set default state */ 4190 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4191 4192 /* reset number of contexts */ 4193 sc->sc_hw.devs[index].context_num = 0; 4194 4195 err = xhci_cmd_reset_dev(sc, index); 4196 4197 if (err != 0) { 4198 DPRINTF("Device reset failed " 4199 "for slot %u.\n", index); 4200 } 4201 break; 4202 4203 case USB_STATE_ADDRESSED: 4204 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4205 break; 4206 4207 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4208 4209 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4210 4211 if (err) { 4212 DPRINTF("Failed to deconfigure " 4213 "slot %u.\n", index); 4214 } 4215 break; 4216 4217 case USB_STATE_CONFIGURED: 4218 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4219 break; 4220 4221 /* set configured state */ 4222 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4223 4224 /* reset number of contexts */ 4225 sc->sc_hw.devs[index].context_num = 0; 4226 4227 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4228 4229 xhci_configure_mask(udev, 3, 0); 4230 4231 err = xhci_configure_device(udev); 4232 if (err != 0) { 4233 DPRINTF("Could not configure device " 4234 "at slot %u.\n", index); 4235 } 4236 4237 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4238 if (err != 0) { 4239 DPRINTF("Could not evaluate device " 4240 "context at slot %u.\n", index); 4241 } 4242 break; 4243 4244 default: 4245 break; 4246 } 4247 XHCI_CMD_UNLOCK(sc); 4248 } 4249 4250 static usb_error_t 4251 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4252 uint8_t ep_mode) 4253 { 4254 switch (ep_mode) { 4255 case USB_EP_MODE_DEFAULT: 4256 return (0); 4257 case USB_EP_MODE_STREAMS: 4258 if (xhcistreams == 0 || 4259 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4260 udev->speed != USB_SPEED_SUPER) 4261 return (USB_ERR_INVAL); 4262 return (0); 4263 default: 4264 return (USB_ERR_INVAL); 4265 } 4266 } 4267 4268 static const struct usb_bus_methods xhci_bus_methods = { 4269 .endpoint_init = xhci_ep_init, 4270 .endpoint_uninit = xhci_ep_uninit, 4271 .xfer_setup = xhci_xfer_setup, 4272 .xfer_unsetup = xhci_xfer_unsetup, 4273 .get_dma_delay = xhci_get_dma_delay, 4274 .device_init = xhci_device_init, 4275 .device_uninit = xhci_device_uninit, 4276 .device_resume = xhci_device_resume, 4277 .device_suspend = xhci_device_suspend, 4278 .set_hw_power = xhci_set_hw_power, 4279 .roothub_exec = xhci_roothub_exec, 4280 .xfer_poll = xhci_do_poll, 4281 .start_dma_delay = xhci_start_dma_delay, 4282 .set_address = xhci_set_address, 4283 .clear_stall = xhci_ep_clear_stall, 4284 .device_state_change = xhci_device_state_change, 4285 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4286 .set_endpoint_mode = xhci_set_endpoint_mode, 4287 }; 4288