xref: /freebsd/sys/dev/usb/controller/uss820dci.h (revision 195ebc7e9e4b129de810833791a19dfb4349d6a9)
1 /* $FreeBSD$ */
2 /*-
3  * Copyright (c) 2007 Hans Petter Selasky <hselasky@FreeBSD.org>
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #ifndef _USS820_DCI_H_
29 #define	_USS820_DCI_H_
30 
31 #define	USS820_MAX_DEVICES (USB_MIN_DEVICES + 1)
32 
33 #define	USS820_EP_MAX 8			/* maximum number of endpoints */
34 
35 #define	USS820_TXDAT 0x00		/* Transmit FIFO data */
36 
37 #define	USS820_TXCNTL 0x01		/* Transmit FIFO byte count low */
38 #define	USS820_TXCNTL_MASK 0xFF
39 
40 #define	USS820_TXCNTH 0x02		/* Transmit FIFO byte count high */
41 #define	USS820_TXCNTH_MASK 0x03
42 #define	USS820_TXCNTH_UNUSED 0xFC
43 
44 #define	USS820_TXCON 0x03		/* USB transmit FIFO control */
45 #define	USS820_TXCON_REVRP 0x01
46 #define	USS820_TXCON_ADVRM 0x02
47 #define	USS820_TXCON_ATM 0x04		/* Automatic Transmit Management */
48 #define	USS820_TXCON_TXISO 0x08		/* Transmit Isochronous Data */
49 #define	USS820_TXCON_UNUSED 0x10
50 #define	USS820_TXCON_FFSZ_16_64 0x00
51 #define	USS820_TXCON_FFSZ_64_256 0x20
52 #define	USS820_TXCON_FFSZ_8_512 0x40
53 #define	USS820_TXCON_FFSZ_32_1024 0x60
54 #define	USS820_TXCON_FFSZ_MASK 0x60
55 #define	USS820_TXCON_TXCLR 0x80		/* Transmit FIFO clear */
56 
57 #define	USS820_TXFLG 0x04		/* Transmit FIFO flag (Read Only) */
58 #define	USS820_TXFLG_TXOVF 0x01		/* TX overrun */
59 #define	USS820_TXFLG_TXURF 0x02		/* TX underrun */
60 #define	USS820_TXFLG_TXFULL 0x04	/* TX full */
61 #define	USS820_TXFLG_TXEMP 0x08		/* TX empty */
62 #define	USS820_TXFLG_UNUSED 0x30
63 #define	USS820_TXFLG_TXFIF0 0x40
64 #define	USS820_TXFLG_TXFIF1 0x80
65 
66 #define	USS820_RXDAT 0x05		/* Receive FIFO data */
67 
68 #define	USS820_RXCNTL 0x06		/* Receive FIFO byte count low */
69 #define	USS820_RXCNTL_MASK 0xFF
70 
71 #define	USS820_RXCNTH 0x07		/* Receive FIFO byte count high */
72 #define	USS820_RXCNTH_MASK 0x03
73 #define	USS820_RXCNTH_UNUSED 0xFC
74 
75 #define	USS820_RXCON 0x08		/* Receive FIFO control */
76 #define	USS820_RXCON_REVWP 0x01
77 #define	USS820_RXCON_ADVWM 0x02
78 #define	USS820_RXCON_ARM 0x04		/* Auto Receive Management */
79 #define	USS820_RXCON_RXISO 0x08		/* Receive Isochronous Data */
80 #define	USS820_RXCON_RXFFRC 0x10	/* FIFO Read Complete */
81 #define	USS820_RXCON_FFSZ_16_64 0x00
82 #define	USS820_RXCON_FFSZ_64_256 0x20
83 #define	USS820_RXCON_FFSZ_8_512 0x40
84 #define	USS820_RXCON_FFSZ_32_1024 0x60
85 #define	USS820_RXCON_RXCLR 0x80		/* Receive FIFO clear */
86 
87 #define	USS820_RXFLG 0x09		/* Receive FIFO flag (Read Only) */
88 #define	USS820_RXFLG_RXOVF 0x01		/* RX overflow */
89 #define	USS820_RXFLG_RXURF 0x02		/* RX underflow */
90 #define	USS820_RXFLG_RXFULL 0x04	/* RX full */
91 #define	USS820_RXFLG_RXEMP 0x08		/* RX empty */
92 #define	USS820_RXFLG_RXFLUSH 0x10	/* RX flush */
93 #define	USS820_RXFLG_UNUSED 0x20
94 #define	USS820_RXFLG_RXFIF0 0x40
95 #define	USS820_RXFLG_RXFIF1 0x80
96 
97 #define	USS820_EPINDEX 0x0a		/* Endpoint index selection */
98 #define	USS820_EPINDEX_MASK 0x07
99 #define	USS820_EPINDEX_UNUSED 0xF8
100 
101 #define	USS820_EPCON 0x0b		/* Endpoint control */
102 #define	USS820_EPCON_TXEPEN 0x01	/* Transmit Endpoint Enable */
103 #define	USS820_EPCON_TXOE 0x02		/* Transmit Output Enable */
104 #define	USS820_EPCON_RXEPEN 0x04	/* Receive Endpoint Enable */
105 #define	USS820_EPCON_RXIE 0x08		/* Receive Input Enable */
106 #define	USS820_EPCON_RXSPM 0x10		/* Receive Single-Packet Mode */
107 #define	USS820_EPCON_CTLEP 0x20		/* Control Endpoint */
108 #define	USS820_EPCON_TXSTL 0x40		/* Stall Transmit Endpoint */
109 #define	USS820_EPCON_RXSTL 0x80		/* Stall Receive Endpoint */
110 
111 #define	USS820_TXSTAT 0x0c		/* Transmit status */
112 #define	USS820_TXSTAT_TXACK 0x01	/* Transmit Acknowledge */
113 #define	USS820_TXSTAT_TXERR 0x02	/* Transmit Error */
114 #define	USS820_TXSTAT_TXVOID 0x04	/* Transmit Void */
115 #define	USS820_TXSTAT_TXSOVW 0x08	/* Transmit Data Sequence Overwrite
116 					 * Bit */
117 #define	USS820_TXSTAT_TXFLUSH 0x10	/* Transmit FIFO Packet Flushed */
118 #define	USS820_TXSTAT_TXNAKE 0x20	/* Transmit NAK Mode Enable */
119 #define	USS820_TXSTAT_TXDSAM 0x40	/* Transmit Data-Set-Available Mode */
120 #define	USS820_TXSTAT_TXSEQ 0x80	/* Transmitter Current Sequence Bit */
121 
122 #define	USS820_RXSTAT 0x0d		/* Receive status */
123 #define	USS820_RXSTAT_RXACK 0x01	/* Receive Acknowledge */
124 #define	USS820_RXSTAT_RXERR 0x02	/* Receive Error */
125 #define	USS820_RXSTAT_RXVOID 0x04	/* Receive Void */
126 #define	USS820_RXSTAT_RXSOVW 0x08	/* Receive Data Sequence Overwrite Bit */
127 #define	USS820_RXSTAT_EDOVW 0x10	/* End Overwrite Flag */
128 #define	USS820_RXSTAT_STOVW 0x20	/* Start Overwrite Flag */
129 #define	USS820_RXSTAT_RXSETUP 0x40	/* Received SETUP token */
130 #define	USS820_RXSTAT_RXSEQ 0x80	/* Receiver Endpoint Sequence Bit */
131 
132 #define	USS820_SOFL 0x0e		/* Start Of Frame counter low */
133 #define	USS820_SOFL_MASK 0xFF
134 
135 #define	USS820_SOFH 0x0f		/* Start Of Frame counter high */
136 #define	USS820_SOFH_MASK 0x07
137 #define	USS820_SOFH_SOFDIS 0x08		/* SOF Pin Output Disable */
138 #define	USS820_SOFH_FTLOCK 0x10		/* Frame Timer Lock */
139 #define	USS820_SOFH_SOFIE 0x20		/* SOF Interrupt Enable */
140 #define	USS820_SOFH_ASOF 0x40		/* Any Start of Frame */
141 #define	USS820_SOFH_SOFACK 0x80		/* SOF Token Received Without Error */
142 
143 #define	USS820_FADDR 0x10		/* Function Address */
144 #define	USS820_FADDR_MASK 0x7F
145 #define	USS820_FADDR_UNUSED 0x80
146 
147 #define	USS820_SCR 0x11			/* System Control */
148 #define	USS820_SCR_UNUSED 0x01
149 #define	USS820_SCR_T_IRQ 0x02		/* Global Interrupt Enable */
150 #define	USS820_SCR_IRQLVL 0x04		/* Interrupt Mode */
151 #define	USS820_SCR_SRESET 0x08		/* Software reset */
152 #define	USS820_SCR_IE_RESET 0x10	/* Enable Reset Interrupt */
153 #define	USS820_SCR_IE_SUSP 0x20		/* Enable Suspend Interrupt */
154 #define	USS820_SCR_RWUPE 0x40		/* Enable Remote Wake-Up Feature */
155 #define	USS820_SCR_IRQPOL 0x80		/* IRQ polarity */
156 
157 #define	USS820_SSR 0x12			/* System Status */
158 #define	USS820_SSR_RESET 0x01		/* Reset Condition Detected on USB
159 					 * cable */
160 #define	USS820_SSR_SUSPEND 0x02		/* Suspend Detected */
161 #define	USS820_SSR_RESUME 0x04		/* Resume Detected */
162 #define	USS820_SSR_SUSPDIS 0x08		/* Suspend Disable */
163 #define	USS820_SSR_SUSPPO 0x10		/* Suspend Power Off */
164 #define	USS820_SSR_UNUSED 0xE0
165 
166 #define	USS820_UNK0 0x13		/* Unknown */
167 #define	USS820_UNK0_UNUSED 0xFF
168 
169 #define	USS820_SBI 0x14			/* Serial bus interrupt low */
170 #define	USS820_SBI_FTXD0 0x01		/* Function Transmit Done, EP 0 */
171 #define	USS820_SBI_FRXD0 0x02		/* Function Receive Done, EP 0 */
172 #define	USS820_SBI_FTXD1 0x04
173 #define	USS820_SBI_FRXD1 0x08
174 #define	USS820_SBI_FTXD2 0x10
175 #define	USS820_SBI_FRXD2 0x20
176 #define	USS820_SBI_FTXD3 0x40
177 #define	USS820_SBI_FRXD3 0x80
178 
179 #define	USS820_SBI1 0x15		/* Serial bus interrupt high */
180 #define	USS820_SBI1_FTXD4 0x01
181 #define	USS820_SBI1_FRXD4 0x02
182 #define	USS820_SBI1_FTXD5 0x04
183 #define	USS820_SBI1_FRXD5 0x08
184 #define	USS820_SBI1_FTXD6 0x10
185 #define	USS820_SBI1_FRXD6 0x20
186 #define	USS820_SBI1_FTXD7 0x40
187 #define	USS820_SBI1_FRXD7 0x80
188 
189 #define	USS820_SBIE 0x16		/* Serial bus interrupt enable low */
190 #define	USS820_SBIE_FTXIE0 0x01
191 #define	USS820_SBIE_FRXIE0 0x02
192 #define	USS820_SBIE_FTXIE1 0x04
193 #define	USS820_SBIE_FRXIE1 0x08
194 #define	USS820_SBIE_FTXIE2 0x10
195 #define	USS820_SBIE_FRXIE2 0x20
196 #define	USS820_SBIE_FTXIE3 0x40
197 #define	USS820_SBIE_FRXIE3 0x80
198 
199 #define	USS820_SBIE1 0x17		/* Serial bus interrupt enable high */
200 #define	USS820_SBIE1_FTXIE4 0x01
201 #define	USS820_SBIE1_FRXIE4 0x02
202 #define	USS820_SBIE1_FTXIE5 0x04
203 #define	USS820_SBIE1_FRXIE5 0x08
204 #define	USS820_SBIE1_FTXIE6 0x10
205 #define	USS820_SBIE1_FRXIE6 0x20
206 #define	USS820_SBIE1_FTXIE7 0x40
207 #define	USS820_SBIE1_FRXIE7 0x80
208 
209 #define	USS820_REV 0x18			/* Hardware revision */
210 #define	USS820_REV_MIN 0x0F
211 #define	USS820_REV_MAJ 0xF0
212 
213 #define	USS820_LOCK 0x19		/* Suspend power-off locking */
214 #define	USS820_LOCK_UNLOCKED 0x01
215 #define	USS820_LOCK_UNUSED 0xFE
216 
217 #define	USS820_PEND 0x1a		/* Pend hardware status update */
218 #define	USS820_PEND_PEND 0x01
219 #define	USS820_PEND_UNUSED 0xFE
220 
221 #define	USS820_SCRATCH 0x1b		/* Scratch firmware information */
222 #define	USS820_SCRATCH_MASK 0x7F
223 #define	USS820_SCRATCH_IE_RESUME 0x80	/* Enable Resume Interrupt */
224 
225 #define	USS820_MCSR 0x1c		/* Miscellaneous control and status */
226 #define	USS820_MCSR_DPEN 0x01		/* DPLS Pull-Up Enable */
227 #define	USS820_MCSR_SUSPLOE 0x02	/* Suspend Lock Out Enable */
228 #define	USS820_MCSR_BDFEAT 0x04		/* Board Feature Enable */
229 #define	USS820_MCSR_FEAT 0x08		/* Feature Enable */
230 #define	USS820_MCSR_PKGID 0x10		/* Package Identification */
231 #define	USS820_MCSR_SUSPS 0x20		/* Suspend Status */
232 #define	USS820_MCSR_INIT 0x40		/* Device Initialized */
233 #define	USS820_MCSR_RWUPR 0x80		/* Remote Wakeup-Up Remember */
234 
235 #define	USS820_DSAV 0x1d		/* Data set available low (Read Only) */
236 #define	USS820_DSAV_TXAV0 0x01
237 #define	USS820_DSAV_RXAV0 0x02
238 #define	USS820_DSAV_TXAV1 0x04
239 #define	USS820_DSAV_RXAV1 0x08
240 #define	USS820_DSAV_TXAV2 0x10
241 #define	USS820_DSAV_RXAV2 0x20
242 #define	USS820_DSAV_TXAV3 0x40
243 #define	USS820_DSAV_RXAV3 0x80
244 
245 #define	USS820_DSAV1 0x1e		/* Data set available high */
246 #define	USS820_DSAV1_TXAV4 0x01
247 #define	USS820_DSAV1_RXAV4 0x02
248 #define	USS820_DSAV1_TXAV5 0x04
249 #define	USS820_DSAV1_RXAV5 0x08
250 #define	USS820_DSAV1_TXAV6 0x10
251 #define	USS820_DSAV1_RXAV6 0x20
252 #define	USS820_DSAV1_TXAV7 0x40
253 #define	USS820_DSAV1_RXAV7 0x80
254 
255 #define	USS820_UNK1 0x1f		/* Unknown */
256 #define	USS820_UNK1_UNKNOWN 0xFF
257 
258 #define	USS820_READ_1(sc, reg) \
259   bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
260 
261 #define	USS820_WRITE_1(sc, reg, data)	\
262   bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
263 
264 struct uss820dci_td;
265 
266 typedef uint8_t (uss820dci_cmd_t)(struct uss820dci_td *td);
267 
268 struct uss820dci_td {
269 	bus_space_tag_t io_tag;
270 	bus_space_handle_t io_hdl;
271 	struct uss820dci_td *obj_next;
272 	uss820dci_cmd_t *func;
273 	struct usb_page_cache *pc;
274 	uint32_t offset;
275 	uint32_t remainder;
276 	uint16_t max_packet_size;
277 	uint8_t	ep_index;
278 	uint8_t	error:1;
279 	uint8_t	alt_next:1;
280 	uint8_t	short_pkt:1;
281 	uint8_t	support_multi_buffer:1;
282 	uint8_t	did_stall:1;
283 	uint8_t	did_enable:1;
284 };
285 
286 struct uss820_std_temp {
287 	uss820dci_cmd_t *func;
288 	struct usb_page_cache *pc;
289 	struct uss820dci_td *td;
290 	struct uss820dci_td *td_next;
291 	uint32_t len;
292 	uint32_t offset;
293 	uint16_t max_frame_size;
294 	uint8_t	short_pkt;
295 	/*
296          * short_pkt = 0: transfer should be short terminated
297          * short_pkt = 1: transfer should not be short terminated
298          */
299 	uint8_t	setup_alt_next;
300 	uint8_t did_stall;
301 };
302 
303 struct uss820dci_config_desc {
304 	struct usb_config_descriptor confd;
305 	struct usb_interface_descriptor ifcd;
306 	struct usb_endpoint_descriptor endpd;
307 } __packed;
308 
309 union uss820_hub_temp {
310 	uWord	wValue;
311 	struct usb_port_status ps;
312 };
313 
314 struct uss820_flags {
315 	uint8_t	change_connect:1;
316 	uint8_t	change_suspend:1;
317 	uint8_t	status_suspend:1;	/* set if suspended */
318 	uint8_t	status_vbus:1;		/* set if present */
319 	uint8_t	status_bus_reset:1;	/* set if reset complete */
320 	uint8_t	clocks_off:1;
321 	uint8_t	port_powered:1;
322 	uint8_t	port_enabled:1;
323 	uint8_t	d_pulled_up:1;
324 	uint8_t	mcsr_feat:1;
325 };
326 
327 struct uss820dci_softc {
328 	struct usb_bus sc_bus;
329 	union uss820_hub_temp sc_hub_temp;
330 
331 	struct usb_device *sc_devices[USS820_MAX_DEVICES];
332 	struct resource *sc_io_res;
333 	struct resource *sc_irq_res;
334 	void   *sc_intr_hdl;
335 	bus_size_t sc_io_size;
336 	bus_space_tag_t sc_io_tag;
337 	bus_space_handle_t sc_io_hdl;
338 
339 	uint8_t	sc_rt_addr;		/* root HUB address */
340 	uint8_t	sc_dv_addr;		/* device address */
341 	uint8_t	sc_conf;		/* root HUB config */
342 
343 	uint8_t	sc_hub_idata[1];
344 
345 	struct uss820_flags sc_flags;
346 };
347 
348 /* prototypes */
349 
350 usb_error_t uss820dci_init(struct uss820dci_softc *sc);
351 void	uss820dci_uninit(struct uss820dci_softc *sc);
352 void	uss820dci_suspend(struct uss820dci_softc *sc);
353 void	uss820dci_resume(struct uss820dci_softc *sc);
354 void	uss820dci_interrupt(struct uss820dci_softc *sc);
355 
356 #endif					/* _USS820_DCI_H_ */
357