1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2008 Hans Petter Selasky <hselasky@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * This file contains the driver for the USS820 series USB Device 30 * Controller 31 * 32 * NOTE: The datasheet does not document everything. 33 */ 34 35 #ifdef USB_GLOBAL_INCLUDE_FILE 36 #include USB_GLOBAL_INCLUDE_FILE 37 #else 38 #include <sys/stdint.h> 39 #include <sys/stddef.h> 40 #include <sys/param.h> 41 #include <sys/queue.h> 42 #include <sys/types.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/bus.h> 46 #include <sys/module.h> 47 #include <sys/lock.h> 48 #include <sys/mutex.h> 49 #include <sys/condvar.h> 50 #include <sys/sysctl.h> 51 #include <sys/sx.h> 52 #include <sys/unistd.h> 53 #include <sys/callout.h> 54 #include <sys/malloc.h> 55 #include <sys/priv.h> 56 57 #include <dev/usb/usb.h> 58 #include <dev/usb/usbdi.h> 59 60 #define USB_DEBUG_VAR uss820dcidebug 61 62 #include <dev/usb/usb_core.h> 63 #include <dev/usb/usb_debug.h> 64 #include <dev/usb/usb_busdma.h> 65 #include <dev/usb/usb_process.h> 66 #include <dev/usb/usb_transfer.h> 67 #include <dev/usb/usb_device.h> 68 #include <dev/usb/usb_hub.h> 69 #include <dev/usb/usb_util.h> 70 71 #include <dev/usb/usb_controller.h> 72 #include <dev/usb/usb_bus.h> 73 #endif /* USB_GLOBAL_INCLUDE_FILE */ 74 75 #include <dev/usb/controller/uss820dci.h> 76 77 #define USS820_DCI_BUS2SC(bus) \ 78 ((struct uss820dci_softc *)(((uint8_t *)(bus)) - \ 79 ((uint8_t *)&(((struct uss820dci_softc *)0)->sc_bus)))) 80 81 #define USS820_DCI_PC2SC(pc) \ 82 USS820_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 83 84 #define USS820_DCI_THREAD_IRQ \ 85 (USS820_SSR_SUSPEND | USS820_SSR_RESUME | USS820_SSR_RESET) 86 87 #ifdef USB_DEBUG 88 static int uss820dcidebug = 0; 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, uss820dci, CTLFLAG_RW, 0, 91 "USB uss820dci"); 92 SYSCTL_INT(_hw_usb_uss820dci, OID_AUTO, debug, CTLFLAG_RW, 93 &uss820dcidebug, 0, "uss820dci debug level"); 94 #endif 95 96 #define USS820_DCI_INTR_ENDPT 1 97 98 /* prototypes */ 99 100 static const struct usb_bus_methods uss820dci_bus_methods; 101 static const struct usb_pipe_methods uss820dci_device_bulk_methods; 102 static const struct usb_pipe_methods uss820dci_device_ctrl_methods; 103 static const struct usb_pipe_methods uss820dci_device_intr_methods; 104 static const struct usb_pipe_methods uss820dci_device_isoc_fs_methods; 105 106 static uss820dci_cmd_t uss820dci_setup_rx; 107 static uss820dci_cmd_t uss820dci_data_rx; 108 static uss820dci_cmd_t uss820dci_data_tx; 109 static uss820dci_cmd_t uss820dci_data_tx_sync; 110 static void uss820dci_device_done(struct usb_xfer *, usb_error_t); 111 static void uss820dci_do_poll(struct usb_bus *); 112 static void uss820dci_standard_done(struct usb_xfer *); 113 static void uss820dci_intr_set(struct usb_xfer *, uint8_t); 114 static void uss820dci_update_shared_1(struct uss820dci_softc *, uint8_t, 115 uint8_t, uint8_t); 116 static void uss820dci_root_intr(struct uss820dci_softc *); 117 118 /* 119 * Here is a list of what the USS820D chip can support. The main 120 * limitation is that the sum of the buffer sizes must be less than 121 * 1120 bytes. 122 */ 123 static const struct usb_hw_ep_profile 124 uss820dci_ep_profile[] = { 125 126 [0] = { 127 .max_in_frame_size = 32, 128 .max_out_frame_size = 32, 129 .is_simplex = 0, 130 .support_control = 1, 131 }, 132 [1] = { 133 .max_in_frame_size = 64, 134 .max_out_frame_size = 64, 135 .is_simplex = 0, 136 .support_multi_buffer = 1, 137 .support_bulk = 1, 138 .support_interrupt = 1, 139 .support_in = 1, 140 .support_out = 1, 141 }, 142 [2] = { 143 .max_in_frame_size = 8, 144 .max_out_frame_size = 8, 145 .is_simplex = 0, 146 .support_multi_buffer = 1, 147 .support_bulk = 1, 148 .support_interrupt = 1, 149 .support_in = 1, 150 .support_out = 1, 151 }, 152 [3] = { 153 .max_in_frame_size = 256, 154 .max_out_frame_size = 256, 155 .is_simplex = 0, 156 .support_multi_buffer = 1, 157 .support_isochronous = 1, 158 .support_in = 1, 159 .support_out = 1, 160 }, 161 }; 162 163 static void 164 uss820dci_update_shared_1(struct uss820dci_softc *sc, uint8_t reg, 165 uint8_t keep_mask, uint8_t set_mask) 166 { 167 uint8_t temp; 168 169 USS820_WRITE_1(sc, USS820_PEND, 1); 170 temp = USS820_READ_1(sc, reg); 171 temp &= (keep_mask); 172 temp |= (set_mask); 173 USS820_WRITE_1(sc, reg, temp); 174 USS820_WRITE_1(sc, USS820_PEND, 0); 175 } 176 177 static void 178 uss820dci_get_hw_ep_profile(struct usb_device *udev, 179 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 180 { 181 if (ep_addr == 0) { 182 *ppf = uss820dci_ep_profile + 0; 183 } else if (ep_addr < 5) { 184 *ppf = uss820dci_ep_profile + 1; 185 } else if (ep_addr < 7) { 186 *ppf = uss820dci_ep_profile + 2; 187 } else if (ep_addr == 7) { 188 *ppf = uss820dci_ep_profile + 3; 189 } else { 190 *ppf = NULL; 191 } 192 } 193 194 static void 195 uss820dci_pull_up(struct uss820dci_softc *sc) 196 { 197 uint8_t temp; 198 199 /* pullup D+, if possible */ 200 201 if (!sc->sc_flags.d_pulled_up && 202 sc->sc_flags.port_powered) { 203 sc->sc_flags.d_pulled_up = 1; 204 205 DPRINTF("\n"); 206 207 temp = USS820_READ_1(sc, USS820_MCSR); 208 temp |= USS820_MCSR_DPEN; 209 USS820_WRITE_1(sc, USS820_MCSR, temp); 210 } 211 } 212 213 static void 214 uss820dci_pull_down(struct uss820dci_softc *sc) 215 { 216 uint8_t temp; 217 218 /* pulldown D+, if possible */ 219 220 if (sc->sc_flags.d_pulled_up) { 221 sc->sc_flags.d_pulled_up = 0; 222 223 DPRINTF("\n"); 224 225 temp = USS820_READ_1(sc, USS820_MCSR); 226 temp &= ~USS820_MCSR_DPEN; 227 USS820_WRITE_1(sc, USS820_MCSR, temp); 228 } 229 } 230 231 static void 232 uss820dci_wakeup_peer(struct uss820dci_softc *sc) 233 { 234 if (!(sc->sc_flags.status_suspend)) { 235 return; 236 } 237 DPRINTFN(0, "not supported\n"); 238 } 239 240 static void 241 uss820dci_set_address(struct uss820dci_softc *sc, uint8_t addr) 242 { 243 DPRINTFN(5, "addr=%d\n", addr); 244 245 USS820_WRITE_1(sc, USS820_FADDR, addr); 246 } 247 248 static uint8_t 249 uss820dci_setup_rx(struct uss820dci_softc *sc, struct uss820dci_td *td) 250 { 251 struct usb_device_request req; 252 uint16_t count; 253 uint8_t rx_stat; 254 uint8_t temp; 255 256 /* select the correct endpoint */ 257 USS820_WRITE_1(sc, USS820_EPINDEX, td->ep_index); 258 259 /* read out FIFO status */ 260 rx_stat = USS820_READ_1(sc, USS820_RXSTAT); 261 262 DPRINTFN(5, "rx_stat=0x%02x rem=%u\n", rx_stat, td->remainder); 263 264 if (!(rx_stat & USS820_RXSTAT_RXSETUP)) { 265 goto not_complete; 266 } 267 /* clear did stall */ 268 td->did_stall = 0; 269 270 /* clear stall and all I/O */ 271 uss820dci_update_shared_1(sc, USS820_EPCON, 272 0xFF ^ (USS820_EPCON_TXSTL | 273 USS820_EPCON_RXSTL | 274 USS820_EPCON_RXIE | 275 USS820_EPCON_TXOE), 0); 276 277 /* clear end overwrite flag */ 278 uss820dci_update_shared_1(sc, USS820_RXSTAT, 279 0xFF ^ USS820_RXSTAT_EDOVW, 0); 280 281 /* get the packet byte count */ 282 count = USS820_READ_1(sc, USS820_RXCNTL); 283 count |= (USS820_READ_1(sc, USS820_RXCNTH) << 8); 284 count &= 0x3FF; 285 286 /* verify data length */ 287 if (count != td->remainder) { 288 DPRINTFN(0, "Invalid SETUP packet " 289 "length, %d bytes\n", count); 290 goto setup_not_complete; 291 } 292 if (count != sizeof(req)) { 293 DPRINTFN(0, "Unsupported SETUP packet " 294 "length, %d bytes\n", count); 295 goto setup_not_complete; 296 } 297 /* receive data */ 298 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 299 USS820_RXDAT * USS820_REG_STRIDE, (void *)&req, sizeof(req)); 300 301 /* read out FIFO status */ 302 rx_stat = USS820_READ_1(sc, USS820_RXSTAT); 303 304 if (rx_stat & (USS820_RXSTAT_EDOVW | 305 USS820_RXSTAT_STOVW)) { 306 DPRINTF("new SETUP packet received\n"); 307 return (1); /* not complete */ 308 } 309 /* clear receive setup bit */ 310 uss820dci_update_shared_1(sc, USS820_RXSTAT, 311 0xFF ^ (USS820_RXSTAT_RXSETUP | 312 USS820_RXSTAT_EDOVW | 313 USS820_RXSTAT_STOVW), 0); 314 315 /* set RXFFRC bit */ 316 temp = USS820_READ_1(sc, USS820_RXCON); 317 temp |= USS820_RXCON_RXFFRC; 318 USS820_WRITE_1(sc, USS820_RXCON, temp); 319 320 /* copy data into real buffer */ 321 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 322 323 td->offset = sizeof(req); 324 td->remainder = 0; 325 326 /* sneak peek the set address */ 327 if ((req.bmRequestType == UT_WRITE_DEVICE) && 328 (req.bRequest == UR_SET_ADDRESS)) { 329 sc->sc_dv_addr = req.wValue[0] & 0x7F; 330 } else { 331 sc->sc_dv_addr = 0xFF; 332 } 333 334 /* reset TX FIFO */ 335 temp = USS820_READ_1(sc, USS820_TXCON); 336 temp |= USS820_TXCON_TXCLR; 337 USS820_WRITE_1(sc, USS820_TXCON, temp); 338 temp &= ~USS820_TXCON_TXCLR; 339 USS820_WRITE_1(sc, USS820_TXCON, temp); 340 341 return (0); /* complete */ 342 343 setup_not_complete: 344 345 /* set RXFFRC bit */ 346 temp = USS820_READ_1(sc, USS820_RXCON); 347 temp |= USS820_RXCON_RXFFRC; 348 USS820_WRITE_1(sc, USS820_RXCON, temp); 349 350 /* FALLTHROUGH */ 351 352 not_complete: 353 /* abort any ongoing transfer */ 354 if (!td->did_stall) { 355 DPRINTFN(5, "stalling\n"); 356 /* set stall */ 357 uss820dci_update_shared_1(sc, USS820_EPCON, 0xFF, 358 (USS820_EPCON_TXSTL | USS820_EPCON_RXSTL)); 359 360 td->did_stall = 1; 361 } 362 363 /* clear end overwrite flag, if any */ 364 if (rx_stat & USS820_RXSTAT_RXSETUP) { 365 uss820dci_update_shared_1(sc, USS820_RXSTAT, 366 0xFF ^ (USS820_RXSTAT_EDOVW | 367 USS820_RXSTAT_STOVW | 368 USS820_RXSTAT_RXSETUP), 0); 369 } 370 return (1); /* not complete */ 371 } 372 373 static uint8_t 374 uss820dci_data_rx(struct uss820dci_softc *sc, struct uss820dci_td *td) 375 { 376 struct usb_page_search buf_res; 377 uint16_t count; 378 uint8_t rx_flag; 379 uint8_t rx_stat; 380 uint8_t rx_cntl; 381 uint8_t to; 382 uint8_t got_short; 383 384 to = 2; /* don't loop forever! */ 385 got_short = 0; 386 387 /* select the correct endpoint */ 388 USS820_WRITE_1(sc, USS820_EPINDEX, td->ep_index); 389 390 /* check if any of the FIFO banks have data */ 391 repeat: 392 /* read out FIFO flag */ 393 rx_flag = USS820_READ_1(sc, USS820_RXFLG); 394 /* read out FIFO status */ 395 rx_stat = USS820_READ_1(sc, USS820_RXSTAT); 396 397 DPRINTFN(5, "rx_stat=0x%02x rx_flag=0x%02x rem=%u\n", 398 rx_stat, rx_flag, td->remainder); 399 400 if (rx_stat & (USS820_RXSTAT_RXSETUP | 401 USS820_RXSTAT_RXSOVW | 402 USS820_RXSTAT_EDOVW)) { 403 if (td->remainder == 0) { 404 /* 405 * We are actually complete and have 406 * received the next SETUP 407 */ 408 DPRINTFN(5, "faking complete\n"); 409 return (0); /* complete */ 410 } 411 /* 412 * USB Host Aborted the transfer. 413 */ 414 td->error = 1; 415 return (0); /* complete */ 416 } 417 /* check for errors */ 418 if (rx_flag & (USS820_RXFLG_RXOVF | 419 USS820_RXFLG_RXURF)) { 420 DPRINTFN(5, "overflow or underflow\n"); 421 /* should not happen */ 422 td->error = 1; 423 return (0); /* complete */ 424 } 425 /* check status */ 426 if (!(rx_flag & (USS820_RXFLG_RXFIF0 | 427 USS820_RXFLG_RXFIF1))) { 428 429 /* read out EPCON register */ 430 /* enable RX input */ 431 if (!td->did_enable) { 432 uss820dci_update_shared_1(USS820_DCI_PC2SC(td->pc), 433 USS820_EPCON, 0xFF, USS820_EPCON_RXIE); 434 td->did_enable = 1; 435 } 436 return (1); /* not complete */ 437 } 438 /* get the packet byte count */ 439 count = USS820_READ_1(sc, USS820_RXCNTL); 440 count |= (USS820_READ_1(sc, USS820_RXCNTH) << 8); 441 count &= 0x3FF; 442 443 DPRINTFN(5, "count=0x%04x\n", count); 444 445 /* verify the packet byte count */ 446 if (count != td->max_packet_size) { 447 if (count < td->max_packet_size) { 448 /* we have a short packet */ 449 td->short_pkt = 1; 450 got_short = 1; 451 } else { 452 /* invalid USB packet */ 453 td->error = 1; 454 return (0); /* we are complete */ 455 } 456 } 457 /* verify the packet byte count */ 458 if (count > td->remainder) { 459 /* invalid USB packet */ 460 td->error = 1; 461 return (0); /* we are complete */ 462 } 463 while (count > 0) { 464 usbd_get_page(td->pc, td->offset, &buf_res); 465 466 /* get correct length */ 467 if (buf_res.length > count) { 468 buf_res.length = count; 469 } 470 /* receive data */ 471 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 472 USS820_RXDAT * USS820_REG_STRIDE, buf_res.buffer, buf_res.length); 473 474 /* update counters */ 475 count -= buf_res.length; 476 td->offset += buf_res.length; 477 td->remainder -= buf_res.length; 478 } 479 480 /* set RXFFRC bit */ 481 rx_cntl = USS820_READ_1(sc, USS820_RXCON); 482 rx_cntl |= USS820_RXCON_RXFFRC; 483 USS820_WRITE_1(sc, USS820_RXCON, rx_cntl); 484 485 /* check if we are complete */ 486 if ((td->remainder == 0) || got_short) { 487 if (td->short_pkt) { 488 /* we are complete */ 489 return (0); 490 } 491 /* else need to receive a zero length packet */ 492 } 493 if (--to) { 494 goto repeat; 495 } 496 return (1); /* not complete */ 497 } 498 499 static uint8_t 500 uss820dci_data_tx(struct uss820dci_softc *sc, struct uss820dci_td *td) 501 { 502 struct usb_page_search buf_res; 503 uint16_t count; 504 uint16_t count_copy; 505 uint8_t rx_stat; 506 uint8_t tx_flag; 507 uint8_t to; 508 509 /* select the correct endpoint */ 510 USS820_WRITE_1(sc, USS820_EPINDEX, td->ep_index); 511 512 to = 2; /* don't loop forever! */ 513 514 repeat: 515 /* read out TX FIFO flags */ 516 tx_flag = USS820_READ_1(sc, USS820_TXFLG); 517 518 /* read out RX FIFO status last */ 519 rx_stat = USS820_READ_1(sc, USS820_RXSTAT); 520 521 DPRINTFN(5, "rx_stat=0x%02x tx_flag=0x%02x rem=%u\n", 522 rx_stat, tx_flag, td->remainder); 523 524 if (rx_stat & (USS820_RXSTAT_RXSETUP | 525 USS820_RXSTAT_RXSOVW | 526 USS820_RXSTAT_EDOVW)) { 527 /* 528 * The current transfer was aborted 529 * by the USB Host 530 */ 531 td->error = 1; 532 return (0); /* complete */ 533 } 534 if (tx_flag & (USS820_TXFLG_TXOVF | 535 USS820_TXFLG_TXURF)) { 536 td->error = 1; 537 return (0); /* complete */ 538 } 539 if (tx_flag & USS820_TXFLG_TXFIF0) { 540 if (tx_flag & USS820_TXFLG_TXFIF1) { 541 return (1); /* not complete */ 542 } 543 } 544 if ((!td->support_multi_buffer) && 545 (tx_flag & (USS820_TXFLG_TXFIF0 | 546 USS820_TXFLG_TXFIF1))) { 547 return (1); /* not complete */ 548 } 549 count = td->max_packet_size; 550 if (td->remainder < count) { 551 /* we have a short packet */ 552 td->short_pkt = 1; 553 count = td->remainder; 554 } 555 count_copy = count; 556 while (count > 0) { 557 558 usbd_get_page(td->pc, td->offset, &buf_res); 559 560 /* get correct length */ 561 if (buf_res.length > count) { 562 buf_res.length = count; 563 } 564 /* transmit data */ 565 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 566 USS820_TXDAT * USS820_REG_STRIDE, buf_res.buffer, buf_res.length); 567 568 /* update counters */ 569 count -= buf_res.length; 570 td->offset += buf_res.length; 571 td->remainder -= buf_res.length; 572 } 573 574 /* post-write high packet byte count first */ 575 USS820_WRITE_1(sc, USS820_TXCNTH, count_copy >> 8); 576 577 /* post-write low packet byte count last */ 578 USS820_WRITE_1(sc, USS820_TXCNTL, count_copy); 579 580 /* 581 * Enable TX output, which must happen after that we have written 582 * data into the FIFO. This is undocumented. 583 */ 584 if (!td->did_enable) { 585 uss820dci_update_shared_1(USS820_DCI_PC2SC(td->pc), 586 USS820_EPCON, 0xFF, USS820_EPCON_TXOE); 587 td->did_enable = 1; 588 } 589 /* check remainder */ 590 if (td->remainder == 0) { 591 if (td->short_pkt) { 592 return (0); /* complete */ 593 } 594 /* else we need to transmit a short packet */ 595 } 596 if (--to) { 597 goto repeat; 598 } 599 return (1); /* not complete */ 600 } 601 602 static uint8_t 603 uss820dci_data_tx_sync(struct uss820dci_softc *sc, struct uss820dci_td *td) 604 { 605 uint8_t rx_stat; 606 uint8_t tx_flag; 607 608 /* select the correct endpoint */ 609 USS820_WRITE_1(sc, USS820_EPINDEX, td->ep_index); 610 611 /* read out TX FIFO flag */ 612 tx_flag = USS820_READ_1(sc, USS820_TXFLG); 613 614 /* read out RX FIFO status last */ 615 rx_stat = USS820_READ_1(sc, USS820_RXSTAT); 616 617 DPRINTFN(5, "rx_stat=0x%02x rem=%u\n", rx_stat, td->remainder); 618 619 if (rx_stat & (USS820_RXSTAT_RXSETUP | 620 USS820_RXSTAT_RXSOVW | 621 USS820_RXSTAT_EDOVW)) { 622 DPRINTFN(5, "faking complete\n"); 623 /* Race condition */ 624 return (0); /* complete */ 625 } 626 DPRINTFN(5, "tx_flag=0x%02x rem=%u\n", 627 tx_flag, td->remainder); 628 629 if (tx_flag & (USS820_TXFLG_TXOVF | 630 USS820_TXFLG_TXURF)) { 631 td->error = 1; 632 return (0); /* complete */ 633 } 634 if (tx_flag & (USS820_TXFLG_TXFIF0 | 635 USS820_TXFLG_TXFIF1)) { 636 return (1); /* not complete */ 637 } 638 if (sc->sc_dv_addr != 0xFF) { 639 /* write function address */ 640 uss820dci_set_address(sc, sc->sc_dv_addr); 641 } 642 return (0); /* complete */ 643 } 644 645 static void 646 uss820dci_xfer_do_fifo(struct usb_xfer *xfer) 647 { 648 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(xfer->xroot->bus); 649 struct uss820dci_td *td; 650 651 DPRINTFN(9, "\n"); 652 653 td = xfer->td_transfer_cache; 654 if (td == NULL) 655 return; 656 657 while (1) { 658 if ((td->func) (sc, td)) { 659 /* operation in progress */ 660 break; 661 } 662 if (((void *)td) == xfer->td_transfer_last) { 663 goto done; 664 } 665 if (td->error) { 666 goto done; 667 } else if (td->remainder > 0) { 668 /* 669 * We had a short transfer. If there is no alternate 670 * next, stop processing ! 671 */ 672 if (!td->alt_next) { 673 goto done; 674 } 675 } 676 /* 677 * Fetch the next transfer descriptor. 678 */ 679 td = td->obj_next; 680 xfer->td_transfer_cache = td; 681 } 682 return; 683 684 done: 685 /* compute all actual lengths */ 686 xfer->td_transfer_cache = NULL; 687 sc->sc_xfer_complete = 1; 688 } 689 690 static uint8_t 691 uss820dci_xfer_do_complete(struct usb_xfer *xfer) 692 { 693 struct uss820dci_td *td; 694 695 DPRINTFN(9, "\n"); 696 697 td = xfer->td_transfer_cache; 698 if (td == NULL) { 699 /* compute all actual lengths */ 700 uss820dci_standard_done(xfer); 701 return(1); 702 } 703 return (0); 704 } 705 706 static void 707 uss820dci_interrupt_poll_locked(struct uss820dci_softc *sc) 708 { 709 struct usb_xfer *xfer; 710 711 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 712 uss820dci_xfer_do_fifo(xfer); 713 } 714 715 static void 716 uss820dci_interrupt_complete_locked(struct uss820dci_softc *sc) 717 { 718 struct usb_xfer *xfer; 719 repeat: 720 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 721 if (uss820dci_xfer_do_complete(xfer)) 722 goto repeat; 723 } 724 } 725 726 static void 727 uss820dci_wait_suspend(struct uss820dci_softc *sc, uint8_t on) 728 { 729 uint8_t scr; 730 uint8_t scratch; 731 732 scr = USS820_READ_1(sc, USS820_SCR); 733 scratch = USS820_READ_1(sc, USS820_SCRATCH); 734 735 if (on) { 736 scr |= USS820_SCR_IE_SUSP; 737 scratch &= ~USS820_SCRATCH_IE_RESUME; 738 } else { 739 scr &= ~USS820_SCR_IE_SUSP; 740 scratch |= USS820_SCRATCH_IE_RESUME; 741 } 742 743 USS820_WRITE_1(sc, USS820_SCR, scr); 744 USS820_WRITE_1(sc, USS820_SCRATCH, scratch); 745 } 746 747 int 748 uss820dci_filter_interrupt(void *arg) 749 { 750 struct uss820dci_softc *sc = arg; 751 int retval = FILTER_HANDLED; 752 uint8_t ssr; 753 754 USB_BUS_SPIN_LOCK(&sc->sc_bus); 755 756 ssr = USS820_READ_1(sc, USS820_SSR); 757 uss820dci_update_shared_1(sc, USS820_SSR, USS820_DCI_THREAD_IRQ, 0); 758 759 if (ssr & USS820_DCI_THREAD_IRQ) 760 retval = FILTER_SCHEDULE_THREAD; 761 762 /* poll FIFOs, if any */ 763 uss820dci_interrupt_poll_locked(sc); 764 765 if (sc->sc_xfer_complete != 0) 766 retval = FILTER_SCHEDULE_THREAD; 767 768 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 769 770 return (retval); 771 } 772 773 void 774 uss820dci_interrupt(void *arg) 775 { 776 struct uss820dci_softc *sc = arg; 777 uint8_t ssr; 778 uint8_t event; 779 780 USB_BUS_LOCK(&sc->sc_bus); 781 USB_BUS_SPIN_LOCK(&sc->sc_bus); 782 783 ssr = USS820_READ_1(sc, USS820_SSR); 784 785 /* acknowledge all interrupts */ 786 787 uss820dci_update_shared_1(sc, USS820_SSR, ~USS820_DCI_THREAD_IRQ, 0); 788 789 /* check for any bus state change interrupts */ 790 791 if (ssr & USS820_DCI_THREAD_IRQ) { 792 793 event = 0; 794 795 if (ssr & USS820_SSR_RESET) { 796 sc->sc_flags.status_bus_reset = 1; 797 sc->sc_flags.status_suspend = 0; 798 sc->sc_flags.change_suspend = 0; 799 sc->sc_flags.change_connect = 1; 800 801 /* disable resume interrupt */ 802 uss820dci_wait_suspend(sc, 1); 803 804 event = 1; 805 } 806 /* 807 * If "RESUME" and "SUSPEND" is set at the same time 808 * we interpret that like "RESUME". Resume is set when 809 * there is at least 3 milliseconds of inactivity on 810 * the USB BUS. 811 */ 812 if (ssr & USS820_SSR_RESUME) { 813 if (sc->sc_flags.status_suspend) { 814 sc->sc_flags.status_suspend = 0; 815 sc->sc_flags.change_suspend = 1; 816 /* disable resume interrupt */ 817 uss820dci_wait_suspend(sc, 1); 818 event = 1; 819 } 820 } else if (ssr & USS820_SSR_SUSPEND) { 821 if (!sc->sc_flags.status_suspend) { 822 sc->sc_flags.status_suspend = 1; 823 sc->sc_flags.change_suspend = 1; 824 /* enable resume interrupt */ 825 uss820dci_wait_suspend(sc, 0); 826 event = 1; 827 } 828 } 829 if (event) { 830 831 DPRINTF("real bus interrupt 0x%02x\n", ssr); 832 833 /* complete root HUB interrupt endpoint */ 834 uss820dci_root_intr(sc); 835 } 836 } 837 /* acknowledge all SBI interrupts */ 838 uss820dci_update_shared_1(sc, USS820_SBI, 0, 0); 839 840 /* acknowledge all SBI1 interrupts */ 841 uss820dci_update_shared_1(sc, USS820_SBI1, 0, 0); 842 843 if (sc->sc_xfer_complete != 0) { 844 sc->sc_xfer_complete = 0; 845 846 /* complete FIFOs, if any */ 847 uss820dci_interrupt_complete_locked(sc); 848 } 849 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 850 USB_BUS_UNLOCK(&sc->sc_bus); 851 } 852 853 static void 854 uss820dci_setup_standard_chain_sub(struct uss820_std_temp *temp) 855 { 856 struct uss820dci_td *td; 857 858 /* get current Transfer Descriptor */ 859 td = temp->td_next; 860 temp->td = td; 861 862 /* prepare for next TD */ 863 temp->td_next = td->obj_next; 864 865 /* fill out the Transfer Descriptor */ 866 td->func = temp->func; 867 td->pc = temp->pc; 868 td->offset = temp->offset; 869 td->remainder = temp->len; 870 td->error = 0; 871 td->did_enable = 0; 872 td->did_stall = temp->did_stall; 873 td->short_pkt = temp->short_pkt; 874 td->alt_next = temp->setup_alt_next; 875 } 876 877 static void 878 uss820dci_setup_standard_chain(struct usb_xfer *xfer) 879 { 880 struct uss820_std_temp temp; 881 struct uss820dci_softc *sc; 882 struct uss820dci_td *td; 883 uint32_t x; 884 uint8_t ep_no; 885 886 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 887 xfer->address, UE_GET_ADDR(xfer->endpointno), 888 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 889 890 temp.max_frame_size = xfer->max_frame_size; 891 892 td = xfer->td_start[0]; 893 xfer->td_transfer_first = td; 894 xfer->td_transfer_cache = td; 895 896 /* setup temp */ 897 898 temp.pc = NULL; 899 temp.td = NULL; 900 temp.td_next = xfer->td_start[0]; 901 temp.offset = 0; 902 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 903 xfer->flags_int.isochronous_xfr; 904 temp.did_stall = !xfer->flags_int.control_stall; 905 906 sc = USS820_DCI_BUS2SC(xfer->xroot->bus); 907 ep_no = (xfer->endpointno & UE_ADDR); 908 909 /* check if we should prepend a setup message */ 910 911 if (xfer->flags_int.control_xfr) { 912 if (xfer->flags_int.control_hdr) { 913 914 temp.func = &uss820dci_setup_rx; 915 temp.len = xfer->frlengths[0]; 916 temp.pc = xfer->frbuffers + 0; 917 temp.short_pkt = temp.len ? 1 : 0; 918 /* check for last frame */ 919 if (xfer->nframes == 1) { 920 /* no STATUS stage yet, SETUP is last */ 921 if (xfer->flags_int.control_act) 922 temp.setup_alt_next = 0; 923 } 924 925 uss820dci_setup_standard_chain_sub(&temp); 926 } 927 x = 1; 928 } else { 929 x = 0; 930 } 931 932 if (x != xfer->nframes) { 933 if (xfer->endpointno & UE_DIR_IN) { 934 temp.func = &uss820dci_data_tx; 935 } else { 936 temp.func = &uss820dci_data_rx; 937 } 938 939 /* setup "pc" pointer */ 940 temp.pc = xfer->frbuffers + x; 941 } 942 while (x != xfer->nframes) { 943 944 /* DATA0 / DATA1 message */ 945 946 temp.len = xfer->frlengths[x]; 947 948 x++; 949 950 if (x == xfer->nframes) { 951 if (xfer->flags_int.control_xfr) { 952 if (xfer->flags_int.control_act) { 953 temp.setup_alt_next = 0; 954 } 955 } else { 956 temp.setup_alt_next = 0; 957 } 958 } 959 if (temp.len == 0) { 960 961 /* make sure that we send an USB packet */ 962 963 temp.short_pkt = 0; 964 965 } else { 966 967 /* regular data transfer */ 968 969 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 970 } 971 972 uss820dci_setup_standard_chain_sub(&temp); 973 974 if (xfer->flags_int.isochronous_xfr) { 975 temp.offset += temp.len; 976 } else { 977 /* get next Page Cache pointer */ 978 temp.pc = xfer->frbuffers + x; 979 } 980 } 981 982 /* check for control transfer */ 983 if (xfer->flags_int.control_xfr) { 984 uint8_t need_sync; 985 986 /* always setup a valid "pc" pointer for status and sync */ 987 temp.pc = xfer->frbuffers + 0; 988 temp.len = 0; 989 temp.short_pkt = 0; 990 temp.setup_alt_next = 0; 991 992 /* check if we should append a status stage */ 993 if (!xfer->flags_int.control_act) { 994 995 /* 996 * Send a DATA1 message and invert the current 997 * endpoint direction. 998 */ 999 if (xfer->endpointno & UE_DIR_IN) { 1000 temp.func = &uss820dci_data_rx; 1001 need_sync = 0; 1002 } else { 1003 temp.func = &uss820dci_data_tx; 1004 need_sync = 1; 1005 } 1006 temp.len = 0; 1007 temp.short_pkt = 0; 1008 1009 uss820dci_setup_standard_chain_sub(&temp); 1010 if (need_sync) { 1011 /* we need a SYNC point after TX */ 1012 temp.func = &uss820dci_data_tx_sync; 1013 uss820dci_setup_standard_chain_sub(&temp); 1014 } 1015 } 1016 } 1017 /* must have at least one frame! */ 1018 td = temp.td; 1019 xfer->td_transfer_last = td; 1020 } 1021 1022 static void 1023 uss820dci_timeout(void *arg) 1024 { 1025 struct usb_xfer *xfer = arg; 1026 1027 DPRINTF("xfer=%p\n", xfer); 1028 1029 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1030 1031 /* transfer is transferred */ 1032 uss820dci_device_done(xfer, USB_ERR_TIMEOUT); 1033 } 1034 1035 static void 1036 uss820dci_intr_set(struct usb_xfer *xfer, uint8_t set) 1037 { 1038 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(xfer->xroot->bus); 1039 uint8_t ep_no = (xfer->endpointno & UE_ADDR); 1040 uint8_t ep_reg; 1041 uint8_t temp; 1042 1043 DPRINTFN(15, "endpoint 0x%02x\n", xfer->endpointno); 1044 1045 if (ep_no > 3) { 1046 ep_reg = USS820_SBIE1; 1047 } else { 1048 ep_reg = USS820_SBIE; 1049 } 1050 1051 ep_no &= 3; 1052 ep_no = 1 << (2 * ep_no); 1053 1054 if (xfer->flags_int.control_xfr) { 1055 if (xfer->flags_int.control_hdr) { 1056 ep_no <<= 1; /* RX interrupt only */ 1057 } else { 1058 ep_no |= (ep_no << 1); /* RX and TX interrupt */ 1059 } 1060 } else { 1061 if (!(xfer->endpointno & UE_DIR_IN)) { 1062 ep_no <<= 1; 1063 } 1064 } 1065 temp = USS820_READ_1(sc, ep_reg); 1066 if (set) { 1067 temp |= ep_no; 1068 } else { 1069 temp &= ~ep_no; 1070 } 1071 USS820_WRITE_1(sc, ep_reg, temp); 1072 } 1073 1074 static void 1075 uss820dci_start_standard_chain(struct usb_xfer *xfer) 1076 { 1077 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(xfer->xroot->bus); 1078 1079 DPRINTFN(9, "\n"); 1080 1081 USB_BUS_SPIN_LOCK(&sc->sc_bus); 1082 1083 /* poll one time */ 1084 uss820dci_xfer_do_fifo(xfer); 1085 1086 if (uss820dci_xfer_do_complete(xfer) == 0) { 1087 /* 1088 * Only enable the endpoint interrupt when we are 1089 * actually waiting for data, hence we are dealing 1090 * with level triggered interrupts ! 1091 */ 1092 uss820dci_intr_set(xfer, 1); 1093 1094 /* put transfer on interrupt queue */ 1095 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1096 1097 /* start timeout, if any */ 1098 if (xfer->timeout != 0) { 1099 usbd_transfer_timeout_ms(xfer, 1100 &uss820dci_timeout, xfer->timeout); 1101 } 1102 } 1103 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 1104 } 1105 1106 static void 1107 uss820dci_root_intr(struct uss820dci_softc *sc) 1108 { 1109 DPRINTFN(9, "\n"); 1110 1111 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1112 1113 /* set port bit */ 1114 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1115 1116 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1117 sizeof(sc->sc_hub_idata)); 1118 } 1119 1120 static usb_error_t 1121 uss820dci_standard_done_sub(struct usb_xfer *xfer) 1122 { 1123 struct uss820dci_td *td; 1124 uint32_t len; 1125 uint8_t error; 1126 1127 DPRINTFN(9, "\n"); 1128 1129 td = xfer->td_transfer_cache; 1130 1131 do { 1132 len = td->remainder; 1133 1134 if (xfer->aframes != xfer->nframes) { 1135 /* 1136 * Verify the length and subtract 1137 * the remainder from "frlengths[]": 1138 */ 1139 if (len > xfer->frlengths[xfer->aframes]) { 1140 td->error = 1; 1141 } else { 1142 xfer->frlengths[xfer->aframes] -= len; 1143 } 1144 } 1145 /* Check for transfer error */ 1146 if (td->error) { 1147 /* the transfer is finished */ 1148 error = 1; 1149 td = NULL; 1150 break; 1151 } 1152 /* Check for short transfer */ 1153 if (len > 0) { 1154 if (xfer->flags_int.short_frames_ok || 1155 xfer->flags_int.isochronous_xfr) { 1156 /* follow alt next */ 1157 if (td->alt_next) { 1158 td = td->obj_next; 1159 } else { 1160 td = NULL; 1161 } 1162 } else { 1163 /* the transfer is finished */ 1164 td = NULL; 1165 } 1166 error = 0; 1167 break; 1168 } 1169 td = td->obj_next; 1170 1171 /* this USB frame is complete */ 1172 error = 0; 1173 break; 1174 1175 } while (0); 1176 1177 /* update transfer cache */ 1178 1179 xfer->td_transfer_cache = td; 1180 1181 return (error ? 1182 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1183 } 1184 1185 static void 1186 uss820dci_standard_done(struct usb_xfer *xfer) 1187 { 1188 usb_error_t err = 0; 1189 1190 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1191 xfer, xfer->endpoint); 1192 1193 /* reset scanner */ 1194 1195 xfer->td_transfer_cache = xfer->td_transfer_first; 1196 1197 if (xfer->flags_int.control_xfr) { 1198 1199 if (xfer->flags_int.control_hdr) { 1200 1201 err = uss820dci_standard_done_sub(xfer); 1202 } 1203 xfer->aframes = 1; 1204 1205 if (xfer->td_transfer_cache == NULL) { 1206 goto done; 1207 } 1208 } 1209 while (xfer->aframes != xfer->nframes) { 1210 1211 err = uss820dci_standard_done_sub(xfer); 1212 xfer->aframes++; 1213 1214 if (xfer->td_transfer_cache == NULL) { 1215 goto done; 1216 } 1217 } 1218 1219 if (xfer->flags_int.control_xfr && 1220 !xfer->flags_int.control_act) { 1221 1222 err = uss820dci_standard_done_sub(xfer); 1223 } 1224 done: 1225 uss820dci_device_done(xfer, err); 1226 } 1227 1228 /*------------------------------------------------------------------------* 1229 * uss820dci_device_done 1230 * 1231 * NOTE: this function can be called more than one time on the 1232 * same USB transfer! 1233 *------------------------------------------------------------------------*/ 1234 static void 1235 uss820dci_device_done(struct usb_xfer *xfer, usb_error_t error) 1236 { 1237 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(xfer->xroot->bus); 1238 1239 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1240 1241 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1242 xfer, xfer->endpoint, error); 1243 1244 USB_BUS_SPIN_LOCK(&sc->sc_bus); 1245 1246 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1247 uss820dci_intr_set(xfer, 0); 1248 } 1249 /* dequeue transfer and start next transfer */ 1250 usbd_transfer_done(xfer, error); 1251 1252 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 1253 } 1254 1255 static void 1256 uss820dci_xfer_stall(struct usb_xfer *xfer) 1257 { 1258 uss820dci_device_done(xfer, USB_ERR_STALLED); 1259 } 1260 1261 static void 1262 uss820dci_set_stall(struct usb_device *udev, 1263 struct usb_endpoint *ep, uint8_t *did_stall) 1264 { 1265 struct uss820dci_softc *sc; 1266 uint8_t ep_no; 1267 uint8_t ep_type; 1268 uint8_t ep_dir; 1269 uint8_t temp; 1270 1271 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1272 1273 DPRINTFN(5, "endpoint=%p\n", ep); 1274 1275 /* set FORCESTALL */ 1276 sc = USS820_DCI_BUS2SC(udev->bus); 1277 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 1278 ep_dir = (ep->edesc->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)); 1279 ep_type = (ep->edesc->bmAttributes & UE_XFERTYPE); 1280 1281 if (ep_type == UE_CONTROL) { 1282 /* should not happen */ 1283 return; 1284 } 1285 USB_BUS_SPIN_LOCK(&sc->sc_bus); 1286 USS820_WRITE_1(sc, USS820_EPINDEX, ep_no); 1287 1288 if (ep_dir == UE_DIR_IN) { 1289 temp = USS820_EPCON_TXSTL; 1290 } else { 1291 temp = USS820_EPCON_RXSTL; 1292 } 1293 uss820dci_update_shared_1(sc, USS820_EPCON, 0xFF, temp); 1294 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 1295 } 1296 1297 static void 1298 uss820dci_clear_stall_sub(struct uss820dci_softc *sc, 1299 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1300 { 1301 uint8_t temp; 1302 1303 if (ep_type == UE_CONTROL) { 1304 /* clearing stall is not needed */ 1305 return; 1306 } 1307 USB_BUS_SPIN_LOCK(&sc->sc_bus); 1308 1309 /* select endpoint index */ 1310 USS820_WRITE_1(sc, USS820_EPINDEX, ep_no); 1311 1312 /* clear stall and disable I/O transfers */ 1313 if (ep_dir == UE_DIR_IN) { 1314 temp = 0xFF ^ (USS820_EPCON_TXOE | 1315 USS820_EPCON_TXSTL); 1316 } else { 1317 temp = 0xFF ^ (USS820_EPCON_RXIE | 1318 USS820_EPCON_RXSTL); 1319 } 1320 uss820dci_update_shared_1(sc, USS820_EPCON, temp, 0); 1321 1322 if (ep_dir == UE_DIR_IN) { 1323 /* reset data toggle */ 1324 USS820_WRITE_1(sc, USS820_TXSTAT, 1325 USS820_TXSTAT_TXSOVW); 1326 1327 /* reset FIFO */ 1328 temp = USS820_READ_1(sc, USS820_TXCON); 1329 temp |= USS820_TXCON_TXCLR; 1330 USS820_WRITE_1(sc, USS820_TXCON, temp); 1331 temp &= ~USS820_TXCON_TXCLR; 1332 USS820_WRITE_1(sc, USS820_TXCON, temp); 1333 } else { 1334 1335 /* reset data toggle */ 1336 uss820dci_update_shared_1(sc, USS820_RXSTAT, 1337 0, USS820_RXSTAT_RXSOVW); 1338 1339 /* reset FIFO */ 1340 temp = USS820_READ_1(sc, USS820_RXCON); 1341 temp |= USS820_RXCON_RXCLR; 1342 temp &= ~USS820_RXCON_RXFFRC; 1343 USS820_WRITE_1(sc, USS820_RXCON, temp); 1344 temp &= ~USS820_RXCON_RXCLR; 1345 USS820_WRITE_1(sc, USS820_RXCON, temp); 1346 } 1347 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 1348 } 1349 1350 static void 1351 uss820dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1352 { 1353 struct uss820dci_softc *sc; 1354 struct usb_endpoint_descriptor *ed; 1355 1356 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1357 1358 DPRINTFN(5, "endpoint=%p\n", ep); 1359 1360 /* check mode */ 1361 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1362 /* not supported */ 1363 return; 1364 } 1365 /* get softc */ 1366 sc = USS820_DCI_BUS2SC(udev->bus); 1367 1368 /* get endpoint descriptor */ 1369 ed = ep->edesc; 1370 1371 /* reset endpoint */ 1372 uss820dci_clear_stall_sub(sc, 1373 (ed->bEndpointAddress & UE_ADDR), 1374 (ed->bmAttributes & UE_XFERTYPE), 1375 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1376 } 1377 1378 usb_error_t 1379 uss820dci_init(struct uss820dci_softc *sc) 1380 { 1381 const struct usb_hw_ep_profile *pf; 1382 uint8_t n; 1383 uint8_t temp; 1384 1385 DPRINTF("start\n"); 1386 1387 /* set up the bus structure */ 1388 sc->sc_bus.usbrev = USB_REV_1_1; 1389 sc->sc_bus.methods = &uss820dci_bus_methods; 1390 1391 USB_BUS_LOCK(&sc->sc_bus); 1392 1393 /* we always have VBUS */ 1394 sc->sc_flags.status_vbus = 1; 1395 1396 /* reset the chip */ 1397 USS820_WRITE_1(sc, USS820_SCR, USS820_SCR_SRESET); 1398 DELAY(100); 1399 USS820_WRITE_1(sc, USS820_SCR, 0); 1400 1401 /* wait for reset to complete */ 1402 for (n = 0;; n++) { 1403 1404 temp = USS820_READ_1(sc, USS820_MCSR); 1405 1406 if (temp & USS820_MCSR_INIT) { 1407 break; 1408 } 1409 if (n == 100) { 1410 USB_BUS_UNLOCK(&sc->sc_bus); 1411 return (USB_ERR_INVAL); 1412 } 1413 /* wait a little for things to stabilise */ 1414 DELAY(100); 1415 } 1416 1417 /* do a pulldown */ 1418 uss820dci_pull_down(sc); 1419 1420 /* wait 10ms for pulldown to stabilise */ 1421 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1422 1423 /* check hardware revision */ 1424 temp = USS820_READ_1(sc, USS820_REV); 1425 1426 if (temp < 0x13) { 1427 USB_BUS_UNLOCK(&sc->sc_bus); 1428 return (USB_ERR_INVAL); 1429 } 1430 /* enable interrupts */ 1431 USS820_WRITE_1(sc, USS820_SCR, 1432 USS820_SCR_T_IRQ | 1433 USS820_SCR_IE_RESET | 1434 /* USS820_SCR_RWUPE | */ 1435 USS820_SCR_IE_SUSP | 1436 USS820_SCR_IRQPOL); 1437 1438 /* enable interrupts */ 1439 USS820_WRITE_1(sc, USS820_SCRATCH, 1440 USS820_SCRATCH_IE_RESUME); 1441 1442 /* enable features */ 1443 USS820_WRITE_1(sc, USS820_MCSR, 1444 USS820_MCSR_BDFEAT | 1445 USS820_MCSR_FEAT); 1446 1447 sc->sc_flags.mcsr_feat = 1; 1448 1449 /* disable interrupts */ 1450 USS820_WRITE_1(sc, USS820_SBIE, 0); 1451 1452 /* disable interrupts */ 1453 USS820_WRITE_1(sc, USS820_SBIE1, 0); 1454 1455 /* disable all endpoints */ 1456 for (n = 0; n != USS820_EP_MAX; n++) { 1457 1458 /* select endpoint */ 1459 USS820_WRITE_1(sc, USS820_EPINDEX, n); 1460 1461 /* disable endpoint */ 1462 uss820dci_update_shared_1(sc, USS820_EPCON, 0, 0); 1463 } 1464 1465 /* 1466 * Initialise default values for some registers that cannot be 1467 * changed during operation! 1468 */ 1469 for (n = 0; n != USS820_EP_MAX; n++) { 1470 1471 uss820dci_get_hw_ep_profile(NULL, &pf, n); 1472 1473 /* the maximum frame sizes should be the same */ 1474 if (pf->max_in_frame_size != pf->max_out_frame_size) { 1475 DPRINTF("Max frame size mismatch %u != %u\n", 1476 pf->max_in_frame_size, pf->max_out_frame_size); 1477 } 1478 if (pf->support_isochronous) { 1479 if (pf->max_in_frame_size <= 64) { 1480 temp = (USS820_TXCON_FFSZ_16_64 | 1481 USS820_TXCON_TXISO | 1482 USS820_TXCON_ATM); 1483 } else if (pf->max_in_frame_size <= 256) { 1484 temp = (USS820_TXCON_FFSZ_64_256 | 1485 USS820_TXCON_TXISO | 1486 USS820_TXCON_ATM); 1487 } else if (pf->max_in_frame_size <= 512) { 1488 temp = (USS820_TXCON_FFSZ_8_512 | 1489 USS820_TXCON_TXISO | 1490 USS820_TXCON_ATM); 1491 } else { /* 1024 bytes */ 1492 temp = (USS820_TXCON_FFSZ_32_1024 | 1493 USS820_TXCON_TXISO | 1494 USS820_TXCON_ATM); 1495 } 1496 } else { 1497 if ((pf->max_in_frame_size <= 8) && 1498 (sc->sc_flags.mcsr_feat)) { 1499 temp = (USS820_TXCON_FFSZ_8_512 | 1500 USS820_TXCON_ATM); 1501 } else if (pf->max_in_frame_size <= 16) { 1502 temp = (USS820_TXCON_FFSZ_16_64 | 1503 USS820_TXCON_ATM); 1504 } else if ((pf->max_in_frame_size <= 32) && 1505 (sc->sc_flags.mcsr_feat)) { 1506 temp = (USS820_TXCON_FFSZ_32_1024 | 1507 USS820_TXCON_ATM); 1508 } else { /* 64 bytes */ 1509 temp = (USS820_TXCON_FFSZ_64_256 | 1510 USS820_TXCON_ATM); 1511 } 1512 } 1513 1514 /* need to configure the chip early */ 1515 1516 USS820_WRITE_1(sc, USS820_EPINDEX, n); 1517 USS820_WRITE_1(sc, USS820_TXCON, temp); 1518 USS820_WRITE_1(sc, USS820_RXCON, temp); 1519 1520 if (pf->support_control) { 1521 temp = USS820_EPCON_CTLEP | 1522 USS820_EPCON_RXSPM | 1523 USS820_EPCON_RXIE | 1524 USS820_EPCON_RXEPEN | 1525 USS820_EPCON_TXOE | 1526 USS820_EPCON_TXEPEN; 1527 } else { 1528 temp = USS820_EPCON_RXEPEN | USS820_EPCON_TXEPEN; 1529 } 1530 1531 uss820dci_update_shared_1(sc, USS820_EPCON, 0xFF, temp); 1532 } 1533 1534 USB_BUS_UNLOCK(&sc->sc_bus); 1535 1536 /* catch any lost interrupts */ 1537 1538 uss820dci_do_poll(&sc->sc_bus); 1539 1540 return (0); /* success */ 1541 } 1542 1543 void 1544 uss820dci_uninit(struct uss820dci_softc *sc) 1545 { 1546 uint8_t temp; 1547 1548 USB_BUS_LOCK(&sc->sc_bus); 1549 1550 /* disable all interrupts */ 1551 temp = USS820_READ_1(sc, USS820_SCR); 1552 temp &= ~USS820_SCR_T_IRQ; 1553 USS820_WRITE_1(sc, USS820_SCR, temp); 1554 1555 sc->sc_flags.port_powered = 0; 1556 sc->sc_flags.status_vbus = 0; 1557 sc->sc_flags.status_bus_reset = 0; 1558 sc->sc_flags.status_suspend = 0; 1559 sc->sc_flags.change_suspend = 0; 1560 sc->sc_flags.change_connect = 1; 1561 1562 uss820dci_pull_down(sc); 1563 USB_BUS_UNLOCK(&sc->sc_bus); 1564 } 1565 1566 static void 1567 uss820dci_suspend(struct uss820dci_softc *sc) 1568 { 1569 /* TODO */ 1570 } 1571 1572 static void 1573 uss820dci_resume(struct uss820dci_softc *sc) 1574 { 1575 /* TODO */ 1576 } 1577 1578 static void 1579 uss820dci_do_poll(struct usb_bus *bus) 1580 { 1581 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(bus); 1582 1583 USB_BUS_LOCK(&sc->sc_bus); 1584 USB_BUS_SPIN_LOCK(&sc->sc_bus); 1585 uss820dci_interrupt_poll_locked(sc); 1586 uss820dci_interrupt_complete_locked(sc); 1587 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 1588 USB_BUS_UNLOCK(&sc->sc_bus); 1589 } 1590 1591 /*------------------------------------------------------------------------* 1592 * uss820dci bulk support 1593 *------------------------------------------------------------------------*/ 1594 static void 1595 uss820dci_device_bulk_open(struct usb_xfer *xfer) 1596 { 1597 return; 1598 } 1599 1600 static void 1601 uss820dci_device_bulk_close(struct usb_xfer *xfer) 1602 { 1603 uss820dci_device_done(xfer, USB_ERR_CANCELLED); 1604 } 1605 1606 static void 1607 uss820dci_device_bulk_enter(struct usb_xfer *xfer) 1608 { 1609 return; 1610 } 1611 1612 static void 1613 uss820dci_device_bulk_start(struct usb_xfer *xfer) 1614 { 1615 /* setup TDs */ 1616 uss820dci_setup_standard_chain(xfer); 1617 uss820dci_start_standard_chain(xfer); 1618 } 1619 1620 static const struct usb_pipe_methods uss820dci_device_bulk_methods = 1621 { 1622 .open = uss820dci_device_bulk_open, 1623 .close = uss820dci_device_bulk_close, 1624 .enter = uss820dci_device_bulk_enter, 1625 .start = uss820dci_device_bulk_start, 1626 }; 1627 1628 /*------------------------------------------------------------------------* 1629 * uss820dci control support 1630 *------------------------------------------------------------------------*/ 1631 static void 1632 uss820dci_device_ctrl_open(struct usb_xfer *xfer) 1633 { 1634 return; 1635 } 1636 1637 static void 1638 uss820dci_device_ctrl_close(struct usb_xfer *xfer) 1639 { 1640 uss820dci_device_done(xfer, USB_ERR_CANCELLED); 1641 } 1642 1643 static void 1644 uss820dci_device_ctrl_enter(struct usb_xfer *xfer) 1645 { 1646 return; 1647 } 1648 1649 static void 1650 uss820dci_device_ctrl_start(struct usb_xfer *xfer) 1651 { 1652 /* setup TDs */ 1653 uss820dci_setup_standard_chain(xfer); 1654 uss820dci_start_standard_chain(xfer); 1655 } 1656 1657 static const struct usb_pipe_methods uss820dci_device_ctrl_methods = 1658 { 1659 .open = uss820dci_device_ctrl_open, 1660 .close = uss820dci_device_ctrl_close, 1661 .enter = uss820dci_device_ctrl_enter, 1662 .start = uss820dci_device_ctrl_start, 1663 }; 1664 1665 /*------------------------------------------------------------------------* 1666 * uss820dci interrupt support 1667 *------------------------------------------------------------------------*/ 1668 static void 1669 uss820dci_device_intr_open(struct usb_xfer *xfer) 1670 { 1671 return; 1672 } 1673 1674 static void 1675 uss820dci_device_intr_close(struct usb_xfer *xfer) 1676 { 1677 uss820dci_device_done(xfer, USB_ERR_CANCELLED); 1678 } 1679 1680 static void 1681 uss820dci_device_intr_enter(struct usb_xfer *xfer) 1682 { 1683 return; 1684 } 1685 1686 static void 1687 uss820dci_device_intr_start(struct usb_xfer *xfer) 1688 { 1689 /* setup TDs */ 1690 uss820dci_setup_standard_chain(xfer); 1691 uss820dci_start_standard_chain(xfer); 1692 } 1693 1694 static const struct usb_pipe_methods uss820dci_device_intr_methods = 1695 { 1696 .open = uss820dci_device_intr_open, 1697 .close = uss820dci_device_intr_close, 1698 .enter = uss820dci_device_intr_enter, 1699 .start = uss820dci_device_intr_start, 1700 }; 1701 1702 /*------------------------------------------------------------------------* 1703 * uss820dci full speed isochronous support 1704 *------------------------------------------------------------------------*/ 1705 static void 1706 uss820dci_device_isoc_fs_open(struct usb_xfer *xfer) 1707 { 1708 return; 1709 } 1710 1711 static void 1712 uss820dci_device_isoc_fs_close(struct usb_xfer *xfer) 1713 { 1714 uss820dci_device_done(xfer, USB_ERR_CANCELLED); 1715 } 1716 1717 static void 1718 uss820dci_device_isoc_fs_enter(struct usb_xfer *xfer) 1719 { 1720 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(xfer->xroot->bus); 1721 uint32_t temp; 1722 uint32_t nframes; 1723 1724 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1725 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1726 1727 /* get the current frame index - we don't need the high bits */ 1728 1729 nframes = USS820_READ_1(sc, USS820_SOFL); 1730 1731 /* 1732 * check if the frame index is within the window where the 1733 * frames will be inserted 1734 */ 1735 temp = (nframes - xfer->endpoint->isoc_next) & USS820_SOFL_MASK; 1736 1737 if ((xfer->endpoint->is_synced == 0) || 1738 (temp < xfer->nframes)) { 1739 /* 1740 * If there is data underflow or the pipe queue is 1741 * empty we schedule the transfer a few frames ahead 1742 * of the current frame position. Else two isochronous 1743 * transfers might overlap. 1744 */ 1745 xfer->endpoint->isoc_next = (nframes + 3) & USS820_SOFL_MASK; 1746 xfer->endpoint->is_synced = 1; 1747 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1748 } 1749 /* 1750 * compute how many milliseconds the insertion is ahead of the 1751 * current frame position: 1752 */ 1753 temp = (xfer->endpoint->isoc_next - nframes) & USS820_SOFL_MASK; 1754 1755 /* 1756 * pre-compute when the isochronous transfer will be finished: 1757 */ 1758 xfer->isoc_time_complete = 1759 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1760 xfer->nframes; 1761 1762 /* compute frame number for next insertion */ 1763 xfer->endpoint->isoc_next += xfer->nframes; 1764 1765 /* setup TDs */ 1766 uss820dci_setup_standard_chain(xfer); 1767 } 1768 1769 static void 1770 uss820dci_device_isoc_fs_start(struct usb_xfer *xfer) 1771 { 1772 /* start TD chain */ 1773 uss820dci_start_standard_chain(xfer); 1774 } 1775 1776 static const struct usb_pipe_methods uss820dci_device_isoc_fs_methods = 1777 { 1778 .open = uss820dci_device_isoc_fs_open, 1779 .close = uss820dci_device_isoc_fs_close, 1780 .enter = uss820dci_device_isoc_fs_enter, 1781 .start = uss820dci_device_isoc_fs_start, 1782 }; 1783 1784 /*------------------------------------------------------------------------* 1785 * uss820dci root control support 1786 *------------------------------------------------------------------------* 1787 * Simulate a hardware HUB by handling all the necessary requests. 1788 *------------------------------------------------------------------------*/ 1789 1790 static const struct usb_device_descriptor uss820dci_devd = { 1791 .bLength = sizeof(struct usb_device_descriptor), 1792 .bDescriptorType = UDESC_DEVICE, 1793 .bcdUSB = {0x00, 0x02}, 1794 .bDeviceClass = UDCLASS_HUB, 1795 .bDeviceSubClass = UDSUBCLASS_HUB, 1796 .bDeviceProtocol = UDPROTO_FSHUB, 1797 .bMaxPacketSize = 64, 1798 .bcdDevice = {0x00, 0x01}, 1799 .iManufacturer = 1, 1800 .iProduct = 2, 1801 .bNumConfigurations = 1, 1802 }; 1803 1804 static const struct usb_device_qualifier uss820dci_odevd = { 1805 .bLength = sizeof(struct usb_device_qualifier), 1806 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1807 .bcdUSB = {0x00, 0x02}, 1808 .bDeviceClass = UDCLASS_HUB, 1809 .bDeviceSubClass = UDSUBCLASS_HUB, 1810 .bDeviceProtocol = UDPROTO_FSHUB, 1811 .bMaxPacketSize0 = 0, 1812 .bNumConfigurations = 0, 1813 }; 1814 1815 static const struct uss820dci_config_desc uss820dci_confd = { 1816 .confd = { 1817 .bLength = sizeof(struct usb_config_descriptor), 1818 .bDescriptorType = UDESC_CONFIG, 1819 .wTotalLength[0] = sizeof(uss820dci_confd), 1820 .bNumInterface = 1, 1821 .bConfigurationValue = 1, 1822 .iConfiguration = 0, 1823 .bmAttributes = UC_SELF_POWERED, 1824 .bMaxPower = 0, 1825 }, 1826 .ifcd = { 1827 .bLength = sizeof(struct usb_interface_descriptor), 1828 .bDescriptorType = UDESC_INTERFACE, 1829 .bNumEndpoints = 1, 1830 .bInterfaceClass = UICLASS_HUB, 1831 .bInterfaceSubClass = UISUBCLASS_HUB, 1832 .bInterfaceProtocol = 0, 1833 }, 1834 1835 .endpd = { 1836 .bLength = sizeof(struct usb_endpoint_descriptor), 1837 .bDescriptorType = UDESC_ENDPOINT, 1838 .bEndpointAddress = (UE_DIR_IN | USS820_DCI_INTR_ENDPT), 1839 .bmAttributes = UE_INTERRUPT, 1840 .wMaxPacketSize[0] = 8, 1841 .bInterval = 255, 1842 }, 1843 }; 1844 1845 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1846 1847 static const struct usb_hub_descriptor_min uss820dci_hubd = { 1848 .bDescLength = sizeof(uss820dci_hubd), 1849 .bDescriptorType = UDESC_HUB, 1850 .bNbrPorts = 1, 1851 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1852 .bPwrOn2PwrGood = 50, 1853 .bHubContrCurrent = 0, 1854 .DeviceRemovable = {0}, /* port is removable */ 1855 }; 1856 1857 #define STRING_VENDOR \ 1858 "A\0G\0E\0R\0E" 1859 1860 #define STRING_PRODUCT \ 1861 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1862 1863 USB_MAKE_STRING_DESC(STRING_VENDOR, uss820dci_vendor); 1864 USB_MAKE_STRING_DESC(STRING_PRODUCT, uss820dci_product); 1865 1866 static usb_error_t 1867 uss820dci_roothub_exec(struct usb_device *udev, 1868 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1869 { 1870 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(udev->bus); 1871 const void *ptr; 1872 uint16_t len; 1873 uint16_t value; 1874 uint16_t index; 1875 usb_error_t err; 1876 1877 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1878 1879 /* buffer reset */ 1880 ptr = (const void *)&sc->sc_hub_temp; 1881 len = 0; 1882 err = 0; 1883 1884 value = UGETW(req->wValue); 1885 index = UGETW(req->wIndex); 1886 1887 /* demultiplex the control request */ 1888 1889 switch (req->bmRequestType) { 1890 case UT_READ_DEVICE: 1891 switch (req->bRequest) { 1892 case UR_GET_DESCRIPTOR: 1893 goto tr_handle_get_descriptor; 1894 case UR_GET_CONFIG: 1895 goto tr_handle_get_config; 1896 case UR_GET_STATUS: 1897 goto tr_handle_get_status; 1898 default: 1899 goto tr_stalled; 1900 } 1901 break; 1902 1903 case UT_WRITE_DEVICE: 1904 switch (req->bRequest) { 1905 case UR_SET_ADDRESS: 1906 goto tr_handle_set_address; 1907 case UR_SET_CONFIG: 1908 goto tr_handle_set_config; 1909 case UR_CLEAR_FEATURE: 1910 goto tr_valid; /* nop */ 1911 case UR_SET_DESCRIPTOR: 1912 goto tr_valid; /* nop */ 1913 case UR_SET_FEATURE: 1914 default: 1915 goto tr_stalled; 1916 } 1917 break; 1918 1919 case UT_WRITE_ENDPOINT: 1920 switch (req->bRequest) { 1921 case UR_CLEAR_FEATURE: 1922 switch (UGETW(req->wValue)) { 1923 case UF_ENDPOINT_HALT: 1924 goto tr_handle_clear_halt; 1925 case UF_DEVICE_REMOTE_WAKEUP: 1926 goto tr_handle_clear_wakeup; 1927 default: 1928 goto tr_stalled; 1929 } 1930 break; 1931 case UR_SET_FEATURE: 1932 switch (UGETW(req->wValue)) { 1933 case UF_ENDPOINT_HALT: 1934 goto tr_handle_set_halt; 1935 case UF_DEVICE_REMOTE_WAKEUP: 1936 goto tr_handle_set_wakeup; 1937 default: 1938 goto tr_stalled; 1939 } 1940 break; 1941 case UR_SYNCH_FRAME: 1942 goto tr_valid; /* nop */ 1943 default: 1944 goto tr_stalled; 1945 } 1946 break; 1947 1948 case UT_READ_ENDPOINT: 1949 switch (req->bRequest) { 1950 case UR_GET_STATUS: 1951 goto tr_handle_get_ep_status; 1952 default: 1953 goto tr_stalled; 1954 } 1955 break; 1956 1957 case UT_WRITE_INTERFACE: 1958 switch (req->bRequest) { 1959 case UR_SET_INTERFACE: 1960 goto tr_handle_set_interface; 1961 case UR_CLEAR_FEATURE: 1962 goto tr_valid; /* nop */ 1963 case UR_SET_FEATURE: 1964 default: 1965 goto tr_stalled; 1966 } 1967 break; 1968 1969 case UT_READ_INTERFACE: 1970 switch (req->bRequest) { 1971 case UR_GET_INTERFACE: 1972 goto tr_handle_get_interface; 1973 case UR_GET_STATUS: 1974 goto tr_handle_get_iface_status; 1975 default: 1976 goto tr_stalled; 1977 } 1978 break; 1979 1980 case UT_WRITE_CLASS_INTERFACE: 1981 case UT_WRITE_VENDOR_INTERFACE: 1982 /* XXX forward */ 1983 break; 1984 1985 case UT_READ_CLASS_INTERFACE: 1986 case UT_READ_VENDOR_INTERFACE: 1987 /* XXX forward */ 1988 break; 1989 1990 case UT_WRITE_CLASS_DEVICE: 1991 switch (req->bRequest) { 1992 case UR_CLEAR_FEATURE: 1993 goto tr_valid; 1994 case UR_SET_DESCRIPTOR: 1995 case UR_SET_FEATURE: 1996 break; 1997 default: 1998 goto tr_stalled; 1999 } 2000 break; 2001 2002 case UT_WRITE_CLASS_OTHER: 2003 switch (req->bRequest) { 2004 case UR_CLEAR_FEATURE: 2005 goto tr_handle_clear_port_feature; 2006 case UR_SET_FEATURE: 2007 goto tr_handle_set_port_feature; 2008 case UR_CLEAR_TT_BUFFER: 2009 case UR_RESET_TT: 2010 case UR_STOP_TT: 2011 goto tr_valid; 2012 2013 default: 2014 goto tr_stalled; 2015 } 2016 break; 2017 2018 case UT_READ_CLASS_OTHER: 2019 switch (req->bRequest) { 2020 case UR_GET_TT_STATE: 2021 goto tr_handle_get_tt_state; 2022 case UR_GET_STATUS: 2023 goto tr_handle_get_port_status; 2024 default: 2025 goto tr_stalled; 2026 } 2027 break; 2028 2029 case UT_READ_CLASS_DEVICE: 2030 switch (req->bRequest) { 2031 case UR_GET_DESCRIPTOR: 2032 goto tr_handle_get_class_descriptor; 2033 case UR_GET_STATUS: 2034 goto tr_handle_get_class_status; 2035 2036 default: 2037 goto tr_stalled; 2038 } 2039 break; 2040 default: 2041 goto tr_stalled; 2042 } 2043 goto tr_valid; 2044 2045 tr_handle_get_descriptor: 2046 switch (value >> 8) { 2047 case UDESC_DEVICE: 2048 if (value & 0xff) { 2049 goto tr_stalled; 2050 } 2051 len = sizeof(uss820dci_devd); 2052 ptr = (const void *)&uss820dci_devd; 2053 goto tr_valid; 2054 case UDESC_DEVICE_QUALIFIER: 2055 if (value & 0xff) { 2056 goto tr_stalled; 2057 } 2058 len = sizeof(uss820dci_odevd); 2059 ptr = (const void *)&uss820dci_odevd; 2060 goto tr_valid; 2061 case UDESC_CONFIG: 2062 if (value & 0xff) { 2063 goto tr_stalled; 2064 } 2065 len = sizeof(uss820dci_confd); 2066 ptr = (const void *)&uss820dci_confd; 2067 goto tr_valid; 2068 case UDESC_STRING: 2069 switch (value & 0xff) { 2070 case 0: /* Language table */ 2071 len = sizeof(usb_string_lang_en); 2072 ptr = (const void *)&usb_string_lang_en; 2073 goto tr_valid; 2074 2075 case 1: /* Vendor */ 2076 len = sizeof(uss820dci_vendor); 2077 ptr = (const void *)&uss820dci_vendor; 2078 goto tr_valid; 2079 2080 case 2: /* Product */ 2081 len = sizeof(uss820dci_product); 2082 ptr = (const void *)&uss820dci_product; 2083 goto tr_valid; 2084 default: 2085 break; 2086 } 2087 break; 2088 default: 2089 goto tr_stalled; 2090 } 2091 goto tr_stalled; 2092 2093 tr_handle_get_config: 2094 len = 1; 2095 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2096 goto tr_valid; 2097 2098 tr_handle_get_status: 2099 len = 2; 2100 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2101 goto tr_valid; 2102 2103 tr_handle_set_address: 2104 if (value & 0xFF00) { 2105 goto tr_stalled; 2106 } 2107 sc->sc_rt_addr = value; 2108 goto tr_valid; 2109 2110 tr_handle_set_config: 2111 if (value >= 2) { 2112 goto tr_stalled; 2113 } 2114 sc->sc_conf = value; 2115 goto tr_valid; 2116 2117 tr_handle_get_interface: 2118 len = 1; 2119 sc->sc_hub_temp.wValue[0] = 0; 2120 goto tr_valid; 2121 2122 tr_handle_get_tt_state: 2123 tr_handle_get_class_status: 2124 tr_handle_get_iface_status: 2125 tr_handle_get_ep_status: 2126 len = 2; 2127 USETW(sc->sc_hub_temp.wValue, 0); 2128 goto tr_valid; 2129 2130 tr_handle_set_halt: 2131 tr_handle_set_interface: 2132 tr_handle_set_wakeup: 2133 tr_handle_clear_wakeup: 2134 tr_handle_clear_halt: 2135 goto tr_valid; 2136 2137 tr_handle_clear_port_feature: 2138 if (index != 1) { 2139 goto tr_stalled; 2140 } 2141 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2142 2143 switch (value) { 2144 case UHF_PORT_SUSPEND: 2145 uss820dci_wakeup_peer(sc); 2146 break; 2147 2148 case UHF_PORT_ENABLE: 2149 sc->sc_flags.port_enabled = 0; 2150 break; 2151 2152 case UHF_PORT_TEST: 2153 case UHF_PORT_INDICATOR: 2154 case UHF_C_PORT_ENABLE: 2155 case UHF_C_PORT_OVER_CURRENT: 2156 case UHF_C_PORT_RESET: 2157 /* nops */ 2158 break; 2159 case UHF_PORT_POWER: 2160 sc->sc_flags.port_powered = 0; 2161 uss820dci_pull_down(sc); 2162 break; 2163 case UHF_C_PORT_CONNECTION: 2164 sc->sc_flags.change_connect = 0; 2165 break; 2166 case UHF_C_PORT_SUSPEND: 2167 sc->sc_flags.change_suspend = 0; 2168 break; 2169 default: 2170 err = USB_ERR_IOERROR; 2171 goto done; 2172 } 2173 goto tr_valid; 2174 2175 tr_handle_set_port_feature: 2176 if (index != 1) { 2177 goto tr_stalled; 2178 } 2179 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2180 2181 switch (value) { 2182 case UHF_PORT_ENABLE: 2183 sc->sc_flags.port_enabled = 1; 2184 break; 2185 case UHF_PORT_SUSPEND: 2186 case UHF_PORT_RESET: 2187 case UHF_PORT_TEST: 2188 case UHF_PORT_INDICATOR: 2189 /* nops */ 2190 break; 2191 case UHF_PORT_POWER: 2192 sc->sc_flags.port_powered = 1; 2193 break; 2194 default: 2195 err = USB_ERR_IOERROR; 2196 goto done; 2197 } 2198 goto tr_valid; 2199 2200 tr_handle_get_port_status: 2201 2202 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2203 2204 if (index != 1) { 2205 goto tr_stalled; 2206 } 2207 if (sc->sc_flags.status_vbus) { 2208 uss820dci_pull_up(sc); 2209 } else { 2210 uss820dci_pull_down(sc); 2211 } 2212 2213 /* Select FULL-speed and Device Side Mode */ 2214 2215 value = UPS_PORT_MODE_DEVICE; 2216 2217 if (sc->sc_flags.port_powered) { 2218 value |= UPS_PORT_POWER; 2219 } 2220 if (sc->sc_flags.port_enabled) { 2221 value |= UPS_PORT_ENABLED; 2222 } 2223 if (sc->sc_flags.status_vbus && 2224 sc->sc_flags.status_bus_reset) { 2225 value |= UPS_CURRENT_CONNECT_STATUS; 2226 } 2227 if (sc->sc_flags.status_suspend) { 2228 value |= UPS_SUSPEND; 2229 } 2230 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2231 2232 value = 0; 2233 2234 if (sc->sc_flags.change_connect) { 2235 value |= UPS_C_CONNECT_STATUS; 2236 } 2237 if (sc->sc_flags.change_suspend) { 2238 value |= UPS_C_SUSPEND; 2239 } 2240 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2241 len = sizeof(sc->sc_hub_temp.ps); 2242 goto tr_valid; 2243 2244 tr_handle_get_class_descriptor: 2245 if (value & 0xFF) { 2246 goto tr_stalled; 2247 } 2248 ptr = (const void *)&uss820dci_hubd; 2249 len = sizeof(uss820dci_hubd); 2250 goto tr_valid; 2251 2252 tr_stalled: 2253 err = USB_ERR_STALLED; 2254 tr_valid: 2255 done: 2256 *plength = len; 2257 *pptr = ptr; 2258 return (err); 2259 } 2260 2261 static void 2262 uss820dci_xfer_setup(struct usb_setup_params *parm) 2263 { 2264 const struct usb_hw_ep_profile *pf; 2265 struct uss820dci_softc *sc; 2266 struct usb_xfer *xfer; 2267 void *last_obj; 2268 uint32_t ntd; 2269 uint32_t n; 2270 uint8_t ep_no; 2271 2272 sc = USS820_DCI_BUS2SC(parm->udev->bus); 2273 xfer = parm->curr_xfer; 2274 2275 /* 2276 * NOTE: This driver does not use any of the parameters that 2277 * are computed from the following values. Just set some 2278 * reasonable dummies: 2279 */ 2280 parm->hc_max_packet_size = 0x500; 2281 parm->hc_max_packet_count = 1; 2282 parm->hc_max_frame_size = 0x500; 2283 2284 usbd_transfer_setup_sub(parm); 2285 2286 /* 2287 * compute maximum number of TDs 2288 */ 2289 if (parm->methods == &uss820dci_device_ctrl_methods) { 2290 2291 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 2292 2293 } else if (parm->methods == &uss820dci_device_bulk_methods) { 2294 2295 ntd = xfer->nframes + 1 /* SYNC */ ; 2296 2297 } else if (parm->methods == &uss820dci_device_intr_methods) { 2298 2299 ntd = xfer->nframes + 1 /* SYNC */ ; 2300 2301 } else if (parm->methods == &uss820dci_device_isoc_fs_methods) { 2302 2303 ntd = xfer->nframes + 1 /* SYNC */ ; 2304 2305 } else { 2306 2307 ntd = 0; 2308 } 2309 2310 /* 2311 * check if "usbd_transfer_setup_sub" set an error 2312 */ 2313 if (parm->err) { 2314 return; 2315 } 2316 /* 2317 * allocate transfer descriptors 2318 */ 2319 last_obj = NULL; 2320 2321 /* 2322 * get profile stuff 2323 */ 2324 if (ntd) { 2325 2326 ep_no = xfer->endpointno & UE_ADDR; 2327 uss820dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2328 2329 if (pf == NULL) { 2330 /* should not happen */ 2331 parm->err = USB_ERR_INVAL; 2332 return; 2333 } 2334 } else { 2335 ep_no = 0; 2336 pf = NULL; 2337 } 2338 2339 /* align data */ 2340 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2341 2342 for (n = 0; n != ntd; n++) { 2343 2344 struct uss820dci_td *td; 2345 2346 if (parm->buf) { 2347 2348 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2349 2350 /* init TD */ 2351 td->max_packet_size = xfer->max_packet_size; 2352 td->ep_index = ep_no; 2353 if (pf->support_multi_buffer && 2354 (parm->methods != &uss820dci_device_ctrl_methods)) { 2355 td->support_multi_buffer = 1; 2356 } 2357 td->obj_next = last_obj; 2358 2359 last_obj = td; 2360 } 2361 parm->size[0] += sizeof(*td); 2362 } 2363 2364 xfer->td_start[0] = last_obj; 2365 } 2366 2367 static void 2368 uss820dci_xfer_unsetup(struct usb_xfer *xfer) 2369 { 2370 return; 2371 } 2372 2373 static void 2374 uss820dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2375 struct usb_endpoint *ep) 2376 { 2377 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(udev->bus); 2378 2379 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2380 ep, udev->address, 2381 edesc->bEndpointAddress, udev->flags.usb_mode, 2382 sc->sc_rt_addr); 2383 2384 if (udev->device_index != sc->sc_rt_addr) { 2385 2386 if (udev->speed != USB_SPEED_FULL) { 2387 /* not supported */ 2388 return; 2389 } 2390 switch (edesc->bmAttributes & UE_XFERTYPE) { 2391 case UE_CONTROL: 2392 ep->methods = &uss820dci_device_ctrl_methods; 2393 break; 2394 case UE_INTERRUPT: 2395 ep->methods = &uss820dci_device_intr_methods; 2396 break; 2397 case UE_ISOCHRONOUS: 2398 ep->methods = &uss820dci_device_isoc_fs_methods; 2399 break; 2400 case UE_BULK: 2401 ep->methods = &uss820dci_device_bulk_methods; 2402 break; 2403 default: 2404 /* do nothing */ 2405 break; 2406 } 2407 } 2408 } 2409 2410 static void 2411 uss820dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2412 { 2413 struct uss820dci_softc *sc = USS820_DCI_BUS2SC(bus); 2414 2415 switch (state) { 2416 case USB_HW_POWER_SUSPEND: 2417 uss820dci_suspend(sc); 2418 break; 2419 case USB_HW_POWER_SHUTDOWN: 2420 uss820dci_uninit(sc); 2421 break; 2422 case USB_HW_POWER_RESUME: 2423 uss820dci_resume(sc); 2424 break; 2425 default: 2426 break; 2427 } 2428 } 2429 2430 static const struct usb_bus_methods uss820dci_bus_methods = 2431 { 2432 .endpoint_init = &uss820dci_ep_init, 2433 .xfer_setup = &uss820dci_xfer_setup, 2434 .xfer_unsetup = &uss820dci_xfer_unsetup, 2435 .get_hw_ep_profile = &uss820dci_get_hw_ep_profile, 2436 .xfer_stall = &uss820dci_xfer_stall, 2437 .set_stall = &uss820dci_set_stall, 2438 .clear_stall = &uss820dci_clear_stall, 2439 .roothub_exec = &uss820dci_roothub_exec, 2440 .xfer_poll = &uss820dci_do_poll, 2441 .set_hw_power_sleep = uss820dci_set_hw_power_sleep, 2442 }; 2443