1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 7 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * USB Universal Host Controller driver. 33 * Handles e.g. PIIX3 and PIIX4. 34 * 35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 38 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 39 */ 40 41 #ifdef USB_GLOBAL_INCLUDE_FILE 42 #include USB_GLOBAL_INCLUDE_FILE 43 #else 44 #include <sys/stdint.h> 45 #include <sys/stddef.h> 46 #include <sys/param.h> 47 #include <sys/queue.h> 48 #include <sys/types.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/bus.h> 52 #include <sys/module.h> 53 #include <sys/lock.h> 54 #include <sys/mutex.h> 55 #include <sys/condvar.h> 56 #include <sys/sysctl.h> 57 #include <sys/sx.h> 58 #include <sys/unistd.h> 59 #include <sys/callout.h> 60 #include <sys/malloc.h> 61 #include <sys/priv.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 66 #define USB_DEBUG_VAR uhcidebug 67 68 #include <dev/usb/usb_core.h> 69 #include <dev/usb/usb_debug.h> 70 #include <dev/usb/usb_busdma.h> 71 #include <dev/usb/usb_process.h> 72 #include <dev/usb/usb_transfer.h> 73 #include <dev/usb/usb_device.h> 74 #include <dev/usb/usb_hub.h> 75 #include <dev/usb/usb_util.h> 76 77 #include <dev/usb/usb_controller.h> 78 #include <dev/usb/usb_bus.h> 79 #endif /* USB_GLOBAL_INCLUDE_FILE */ 80 81 #include <dev/usb/controller/uhci.h> 82 #include <dev/usb/controller/uhcireg.h> 83 84 #define alt_next next 85 #define UHCI_BUS2SC(bus) \ 86 ((uhci_softc_t *)(((uint8_t *)(bus)) - \ 87 ((uint8_t *)&(((uhci_softc_t *)0)->sc_bus)))) 88 89 #ifdef USB_DEBUG 90 static int uhcidebug = 0; 91 static int uhcinoloop = 0; 92 93 static SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW, 0, "USB uhci"); 94 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RWTUN, 95 &uhcidebug, 0, "uhci debug level"); 96 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RWTUN, 97 &uhcinoloop, 0, "uhci noloop"); 98 99 static void uhci_dumpregs(uhci_softc_t *sc); 100 static void uhci_dump_tds(uhci_td_t *td); 101 102 #endif 103 104 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 105 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 106 #define UWRITE1(sc, r, x) \ 107 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 108 } while (/*CONSTCOND*/0) 109 #define UWRITE2(sc, r, x) \ 110 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 111 } while (/*CONSTCOND*/0) 112 #define UWRITE4(sc, r, x) \ 113 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 114 } while (/*CONSTCOND*/0) 115 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 116 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 117 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 118 119 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 120 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 121 122 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 123 124 #define UHCI_INTR_ENDPT 1 125 126 struct uhci_mem_layout { 127 128 struct usb_page_search buf_res; 129 struct usb_page_search fix_res; 130 131 struct usb_page_cache *buf_pc; 132 struct usb_page_cache *fix_pc; 133 134 uint32_t buf_offset; 135 136 uint16_t max_frame_size; 137 }; 138 139 struct uhci_std_temp { 140 141 struct uhci_mem_layout ml; 142 uhci_td_t *td; 143 uhci_td_t *td_next; 144 uint32_t average; 145 uint32_t td_status; 146 uint32_t td_token; 147 uint32_t len; 148 uint16_t max_frame_size; 149 uint8_t shortpkt; 150 uint8_t setup_alt_next; 151 uint8_t last_frame; 152 }; 153 154 static const struct usb_bus_methods uhci_bus_methods; 155 static const struct usb_pipe_methods uhci_device_bulk_methods; 156 static const struct usb_pipe_methods uhci_device_ctrl_methods; 157 static const struct usb_pipe_methods uhci_device_intr_methods; 158 static const struct usb_pipe_methods uhci_device_isoc_methods; 159 160 static uint8_t uhci_restart(uhci_softc_t *sc); 161 static void uhci_do_poll(struct usb_bus *); 162 static void uhci_device_done(struct usb_xfer *, usb_error_t); 163 static void uhci_transfer_intr_enqueue(struct usb_xfer *); 164 static void uhci_timeout(void *); 165 static uint8_t uhci_check_transfer(struct usb_xfer *); 166 static void uhci_root_intr(uhci_softc_t *sc); 167 168 void 169 uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 170 { 171 struct uhci_softc *sc = UHCI_BUS2SC(bus); 172 uint32_t i; 173 174 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 175 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN); 176 177 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg, 178 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 179 180 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg, 181 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 182 183 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 184 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 185 186 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg, 187 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 188 189 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg, 190 sizeof(uhci_td_t), UHCI_TD_ALIGN); 191 192 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) { 193 cb(bus, sc->sc_hw.isoc_start_pc + i, 194 sc->sc_hw.isoc_start_pg + i, 195 sizeof(uhci_td_t), UHCI_TD_ALIGN); 196 } 197 198 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) { 199 cb(bus, sc->sc_hw.intr_start_pc + i, 200 sc->sc_hw.intr_start_pg + i, 201 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 202 } 203 } 204 205 static void 206 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer) 207 { 208 ml->buf_pc = xfer->frbuffers + 0; 209 ml->fix_pc = xfer->buf_fixup; 210 211 ml->buf_offset = 0; 212 213 ml->max_frame_size = xfer->max_frame_size; 214 } 215 216 static void 217 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td) 218 { 219 usbd_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res); 220 221 if (ml->buf_res.length < td->len) { 222 223 /* need to do a fixup */ 224 225 usbd_get_page(ml->fix_pc, 0, &ml->fix_res); 226 227 td->td_buffer = htole32(ml->fix_res.physaddr); 228 229 /* 230 * The UHCI driver cannot handle 231 * page crossings, so a fixup is 232 * needed: 233 * 234 * +----+----+ - - - 235 * | YYY|Y | 236 * +----+----+ - - - 237 * \ \ 238 * \ \ 239 * +----+ 240 * |YYYY| (fixup) 241 * +----+ 242 */ 243 244 if ((td->td_token & htole32(UHCI_TD_PID)) == 245 htole32(UHCI_TD_PID_IN)) { 246 td->fix_pc = ml->fix_pc; 247 usb_pc_cpu_invalidate(ml->fix_pc); 248 249 } else { 250 td->fix_pc = NULL; 251 252 /* copy data to fixup location */ 253 254 usbd_copy_out(ml->buf_pc, ml->buf_offset, 255 ml->fix_res.buffer, td->len); 256 257 usb_pc_cpu_flush(ml->fix_pc); 258 } 259 260 /* prepare next fixup */ 261 262 ml->fix_pc++; 263 264 } else { 265 266 td->td_buffer = htole32(ml->buf_res.physaddr); 267 td->fix_pc = NULL; 268 } 269 270 /* prepare next data location */ 271 272 ml->buf_offset += td->len; 273 } 274 275 /* 276 * Return values: 277 * 0: Success 278 * Else: Failure 279 */ 280 static uint8_t 281 uhci_restart(uhci_softc_t *sc) 282 { 283 struct usb_page_search buf_res; 284 285 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 286 287 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) { 288 DPRINTFN(2, "Already started\n"); 289 return (0); 290 } 291 292 DPRINTFN(2, "Restarting\n"); 293 294 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 295 296 /* Reload fresh base address */ 297 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr); 298 299 /* 300 * Assume 64 byte packets at frame end and start HC controller: 301 */ 302 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 303 304 /* wait 10 milliseconds */ 305 306 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 307 308 /* check that controller has started */ 309 310 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 311 DPRINTFN(2, "Failed\n"); 312 return (1); 313 } 314 return (0); 315 } 316 317 void 318 uhci_reset(uhci_softc_t *sc) 319 { 320 uint16_t n; 321 322 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 323 324 DPRINTF("resetting the HC\n"); 325 326 /* disable interrupts */ 327 328 UWRITE2(sc, UHCI_INTR, 0); 329 330 /* global reset */ 331 332 UHCICMD(sc, UHCI_CMD_GRESET); 333 334 /* wait */ 335 336 usb_pause_mtx(&sc->sc_bus.bus_mtx, 337 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 338 339 /* terminate all transfers */ 340 341 UHCICMD(sc, UHCI_CMD_HCRESET); 342 343 /* the reset bit goes low when the controller is done */ 344 345 n = UHCI_RESET_TIMEOUT; 346 while (n--) { 347 /* wait one millisecond */ 348 349 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 350 351 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) { 352 goto done_1; 353 } 354 } 355 356 device_printf(sc->sc_bus.bdev, 357 "controller did not reset\n"); 358 359 done_1: 360 361 n = 10; 362 while (n--) { 363 /* wait one millisecond */ 364 365 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 366 367 /* check if HC is stopped */ 368 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 369 goto done_2; 370 } 371 } 372 373 device_printf(sc->sc_bus.bdev, 374 "controller did not stop\n"); 375 376 done_2: 377 378 /* reset frame number */ 379 UWRITE2(sc, UHCI_FRNUM, 0); 380 /* set default SOF value */ 381 UWRITE1(sc, UHCI_SOF, 0x40); 382 383 USB_BUS_UNLOCK(&sc->sc_bus); 384 385 /* stop root interrupt */ 386 usb_callout_drain(&sc->sc_root_intr); 387 388 USB_BUS_LOCK(&sc->sc_bus); 389 } 390 391 static void 392 uhci_start(uhci_softc_t *sc) 393 { 394 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 395 396 DPRINTFN(2, "enabling\n"); 397 398 /* enable interrupts */ 399 400 UWRITE2(sc, UHCI_INTR, 401 (UHCI_INTR_TOCRCIE | 402 UHCI_INTR_RIE | 403 UHCI_INTR_IOCE | 404 UHCI_INTR_SPIE)); 405 406 if (uhci_restart(sc)) { 407 device_printf(sc->sc_bus.bdev, 408 "cannot start HC controller\n"); 409 } 410 411 /* start root interrupt */ 412 uhci_root_intr(sc); 413 } 414 415 static struct uhci_qh * 416 uhci_init_qh(struct usb_page_cache *pc) 417 { 418 struct usb_page_search buf_res; 419 struct uhci_qh *qh; 420 421 usbd_get_page(pc, 0, &buf_res); 422 423 qh = buf_res.buffer; 424 425 qh->qh_self = 426 htole32(buf_res.physaddr) | 427 htole32(UHCI_PTR_QH); 428 429 qh->page_cache = pc; 430 431 return (qh); 432 } 433 434 static struct uhci_td * 435 uhci_init_td(struct usb_page_cache *pc) 436 { 437 struct usb_page_search buf_res; 438 struct uhci_td *td; 439 440 usbd_get_page(pc, 0, &buf_res); 441 442 td = buf_res.buffer; 443 444 td->td_self = 445 htole32(buf_res.physaddr) | 446 htole32(UHCI_PTR_TD); 447 448 td->page_cache = pc; 449 450 return (td); 451 } 452 453 usb_error_t 454 uhci_init(uhci_softc_t *sc) 455 { 456 uint16_t bit; 457 uint16_t x; 458 uint16_t y; 459 460 DPRINTF("start\n"); 461 462 usb_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_mtx, 0); 463 464 #ifdef USB_DEBUG 465 if (uhcidebug > 2) { 466 uhci_dumpregs(sc); 467 } 468 #endif 469 /* 470 * Setup QH's 471 */ 472 sc->sc_ls_ctl_p_last = 473 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc); 474 475 sc->sc_fs_ctl_p_last = 476 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc); 477 478 sc->sc_bulk_p_last = 479 uhci_init_qh(&sc->sc_hw.bulk_start_pc); 480 #if 0 481 sc->sc_reclaim_qh_p = 482 sc->sc_fs_ctl_p_last; 483 #else 484 /* setup reclaim looping point */ 485 sc->sc_reclaim_qh_p = 486 sc->sc_bulk_p_last; 487 #endif 488 489 sc->sc_last_qh_p = 490 uhci_init_qh(&sc->sc_hw.last_qh_pc); 491 492 sc->sc_last_td_p = 493 uhci_init_td(&sc->sc_hw.last_td_pc); 494 495 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 496 sc->sc_isoc_p_last[x] = 497 uhci_init_td(sc->sc_hw.isoc_start_pc + x); 498 } 499 500 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) { 501 sc->sc_intr_p_last[x] = 502 uhci_init_qh(sc->sc_hw.intr_start_pc + x); 503 } 504 505 /* 506 * the QHs are arranged to give poll intervals that are 507 * powers of 2 times 1ms 508 */ 509 bit = UHCI_IFRAMELIST_COUNT / 2; 510 while (bit) { 511 x = bit; 512 while (x & bit) { 513 uhci_qh_t *qh_x; 514 uhci_qh_t *qh_y; 515 516 y = (x ^ bit) | (bit / 2); 517 518 /* 519 * the next QH has half the poll interval 520 */ 521 qh_x = sc->sc_intr_p_last[x]; 522 qh_y = sc->sc_intr_p_last[y]; 523 524 qh_x->h_next = NULL; 525 qh_x->qh_h_next = qh_y->qh_self; 526 qh_x->e_next = NULL; 527 qh_x->qh_e_next = htole32(UHCI_PTR_T); 528 x++; 529 } 530 bit >>= 1; 531 } 532 533 if (1) { 534 uhci_qh_t *qh_ls; 535 uhci_qh_t *qh_intr; 536 537 qh_ls = sc->sc_ls_ctl_p_last; 538 qh_intr = sc->sc_intr_p_last[0]; 539 540 /* start QH for interrupt traffic */ 541 qh_intr->h_next = qh_ls; 542 qh_intr->qh_h_next = qh_ls->qh_self; 543 qh_intr->e_next = 0; 544 qh_intr->qh_e_next = htole32(UHCI_PTR_T); 545 } 546 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 547 548 uhci_td_t *td_x; 549 uhci_qh_t *qh_intr; 550 551 td_x = sc->sc_isoc_p_last[x]; 552 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)]; 553 554 /* start TD for isochronous traffic */ 555 td_x->next = NULL; 556 td_x->td_next = qh_intr->qh_self; 557 td_x->td_status = htole32(UHCI_TD_IOS); 558 td_x->td_token = htole32(0); 559 td_x->td_buffer = htole32(0); 560 } 561 562 if (1) { 563 uhci_qh_t *qh_ls; 564 uhci_qh_t *qh_fs; 565 566 qh_ls = sc->sc_ls_ctl_p_last; 567 qh_fs = sc->sc_fs_ctl_p_last; 568 569 /* start QH where low speed control traffic will be queued */ 570 qh_ls->h_next = qh_fs; 571 qh_ls->qh_h_next = qh_fs->qh_self; 572 qh_ls->e_next = 0; 573 qh_ls->qh_e_next = htole32(UHCI_PTR_T); 574 } 575 if (1) { 576 uhci_qh_t *qh_ctl; 577 uhci_qh_t *qh_blk; 578 uhci_qh_t *qh_lst; 579 uhci_td_t *td_lst; 580 581 qh_ctl = sc->sc_fs_ctl_p_last; 582 qh_blk = sc->sc_bulk_p_last; 583 584 /* start QH where full speed control traffic will be queued */ 585 qh_ctl->h_next = qh_blk; 586 qh_ctl->qh_h_next = qh_blk->qh_self; 587 qh_ctl->e_next = 0; 588 qh_ctl->qh_e_next = htole32(UHCI_PTR_T); 589 590 qh_lst = sc->sc_last_qh_p; 591 592 /* start QH where bulk traffic will be queued */ 593 qh_blk->h_next = qh_lst; 594 qh_blk->qh_h_next = qh_lst->qh_self; 595 qh_blk->e_next = 0; 596 qh_blk->qh_e_next = htole32(UHCI_PTR_T); 597 598 td_lst = sc->sc_last_td_p; 599 600 /* end QH which is used for looping the QHs */ 601 qh_lst->h_next = 0; 602 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */ 603 qh_lst->e_next = td_lst; 604 qh_lst->qh_e_next = td_lst->td_self; 605 606 /* 607 * end TD which hangs from the last QH, to avoid a bug in the PIIX 608 * that makes it run berserk otherwise 609 */ 610 td_lst->next = 0; 611 td_lst->td_next = htole32(UHCI_PTR_T); 612 td_lst->td_status = htole32(0); /* inactive */ 613 td_lst->td_token = htole32(0); 614 td_lst->td_buffer = htole32(0); 615 } 616 if (1) { 617 struct usb_page_search buf_res; 618 uint32_t *pframes; 619 620 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 621 622 pframes = buf_res.buffer; 623 624 625 /* 626 * Setup UHCI framelist 627 * 628 * Execution order: 629 * 630 * pframes -> full speed isochronous -> interrupt QH's -> low 631 * speed control -> full speed control -> bulk transfers 632 * 633 */ 634 635 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) { 636 pframes[x] = 637 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self; 638 } 639 } 640 /* flush all cache into memory */ 641 642 usb_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc); 643 644 /* set up the bus struct */ 645 sc->sc_bus.methods = &uhci_bus_methods; 646 647 USB_BUS_LOCK(&sc->sc_bus); 648 /* reset the controller */ 649 uhci_reset(sc); 650 651 /* start the controller */ 652 uhci_start(sc); 653 USB_BUS_UNLOCK(&sc->sc_bus); 654 655 /* catch lost interrupts */ 656 uhci_do_poll(&sc->sc_bus); 657 658 return (0); 659 } 660 661 static void 662 uhci_suspend(uhci_softc_t *sc) 663 { 664 #ifdef USB_DEBUG 665 if (uhcidebug > 2) { 666 uhci_dumpregs(sc); 667 } 668 #endif 669 670 USB_BUS_LOCK(&sc->sc_bus); 671 672 /* stop the controller */ 673 674 uhci_reset(sc); 675 676 /* enter global suspend */ 677 678 UHCICMD(sc, UHCI_CMD_EGSM); 679 680 USB_BUS_UNLOCK(&sc->sc_bus); 681 } 682 683 static void 684 uhci_resume(uhci_softc_t *sc) 685 { 686 USB_BUS_LOCK(&sc->sc_bus); 687 688 /* reset the controller */ 689 690 uhci_reset(sc); 691 692 /* force global resume */ 693 694 UHCICMD(sc, UHCI_CMD_FGR); 695 696 /* and start traffic again */ 697 698 uhci_start(sc); 699 700 USB_BUS_UNLOCK(&sc->sc_bus); 701 702 #ifdef USB_DEBUG 703 if (uhcidebug > 2) 704 uhci_dumpregs(sc); 705 #endif 706 707 /* catch lost interrupts */ 708 uhci_do_poll(&sc->sc_bus); 709 } 710 711 #ifdef USB_DEBUG 712 static void 713 uhci_dumpregs(uhci_softc_t *sc) 714 { 715 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 716 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 717 device_get_nameunit(sc->sc_bus.bdev), 718 UREAD2(sc, UHCI_CMD), 719 UREAD2(sc, UHCI_STS), 720 UREAD2(sc, UHCI_INTR), 721 UREAD2(sc, UHCI_FRNUM), 722 UREAD4(sc, UHCI_FLBASEADDR), 723 UREAD1(sc, UHCI_SOF), 724 UREAD2(sc, UHCI_PORTSC1), 725 UREAD2(sc, UHCI_PORTSC2)); 726 } 727 728 static uint8_t 729 uhci_dump_td(uhci_td_t *p) 730 { 731 uint32_t td_next; 732 uint32_t td_status; 733 uint32_t td_token; 734 uint8_t temp; 735 736 usb_pc_cpu_invalidate(p->page_cache); 737 738 td_next = le32toh(p->td_next); 739 td_status = le32toh(p->td_status); 740 td_token = le32toh(p->td_token); 741 742 /* 743 * Check whether the link pointer in this TD marks the link pointer 744 * as end of queue: 745 */ 746 temp = ((td_next & UHCI_PTR_T) || (td_next == 0)); 747 748 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x " 749 "token=0x%08x buffer=0x%08x\n", 750 p, 751 le32toh(p->td_self), 752 td_next, 753 td_status, 754 td_token, 755 le32toh(p->td_buffer)); 756 757 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x," 758 "addr=%d,endpt=%d,D=%d,maxlen=%d\n", 759 p, 760 (td_next & 1) ? "-T" : "", 761 (td_next & 2) ? "-Q" : "", 762 (td_next & 4) ? "-VF" : "", 763 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "", 764 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "", 765 (td_status & UHCI_TD_NAK) ? "-NAK" : "", 766 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "", 767 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "", 768 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "", 769 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "", 770 (td_status & UHCI_TD_IOC) ? "-IOC" : "", 771 (td_status & UHCI_TD_IOS) ? "-IOS" : "", 772 (td_status & UHCI_TD_LS) ? "-LS" : "", 773 (td_status & UHCI_TD_SPD) ? "-SPD" : "", 774 UHCI_TD_GET_ERRCNT(td_status), 775 UHCI_TD_GET_ACTLEN(td_status), 776 UHCI_TD_GET_PID(td_token), 777 UHCI_TD_GET_DEVADDR(td_token), 778 UHCI_TD_GET_ENDPT(td_token), 779 UHCI_TD_GET_DT(td_token), 780 UHCI_TD_GET_MAXLEN(td_token)); 781 782 return (temp); 783 } 784 785 static uint8_t 786 uhci_dump_qh(uhci_qh_t *sqh) 787 { 788 uint8_t temp; 789 uint32_t qh_h_next; 790 uint32_t qh_e_next; 791 792 usb_pc_cpu_invalidate(sqh->page_cache); 793 794 qh_h_next = le32toh(sqh->qh_h_next); 795 qh_e_next = le32toh(sqh->qh_e_next); 796 797 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh, 798 le32toh(sqh->qh_self), qh_h_next, qh_e_next); 799 800 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) | 801 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0)); 802 803 return (temp); 804 } 805 806 static void 807 uhci_dump_all(uhci_softc_t *sc) 808 { 809 uhci_dumpregs(sc); 810 uhci_dump_qh(sc->sc_ls_ctl_p_last); 811 uhci_dump_qh(sc->sc_fs_ctl_p_last); 812 uhci_dump_qh(sc->sc_bulk_p_last); 813 uhci_dump_qh(sc->sc_last_qh_p); 814 } 815 816 static void 817 uhci_dump_tds(uhci_td_t *td) 818 { 819 for (; 820 td != NULL; 821 td = td->obj_next) { 822 if (uhci_dump_td(td)) { 823 break; 824 } 825 } 826 } 827 828 #endif 829 830 /* 831 * Let the last QH loop back to the full speed control transfer QH. 832 * This is what intel calls "bandwidth reclamation" and improves 833 * USB performance a lot for some devices. 834 * If we are already looping, just count it. 835 */ 836 static void 837 uhci_add_loop(uhci_softc_t *sc) 838 { 839 struct uhci_qh *qh_lst; 840 struct uhci_qh *qh_rec; 841 842 #ifdef USB_DEBUG 843 if (uhcinoloop) { 844 return; 845 } 846 #endif 847 if (++(sc->sc_loops) == 1) { 848 DPRINTFN(6, "add\n"); 849 850 qh_lst = sc->sc_last_qh_p; 851 qh_rec = sc->sc_reclaim_qh_p; 852 853 /* NOTE: we don't loop back the soft pointer */ 854 855 qh_lst->qh_h_next = qh_rec->qh_self; 856 usb_pc_cpu_flush(qh_lst->page_cache); 857 } 858 } 859 860 static void 861 uhci_rem_loop(uhci_softc_t *sc) 862 { 863 struct uhci_qh *qh_lst; 864 865 #ifdef USB_DEBUG 866 if (uhcinoloop) { 867 return; 868 } 869 #endif 870 if (--(sc->sc_loops) == 0) { 871 DPRINTFN(6, "remove\n"); 872 873 qh_lst = sc->sc_last_qh_p; 874 qh_lst->qh_h_next = htole32(UHCI_PTR_T); 875 usb_pc_cpu_flush(qh_lst->page_cache); 876 } 877 } 878 879 static void 880 uhci_transfer_intr_enqueue(struct usb_xfer *xfer) 881 { 882 /* check for early completion */ 883 if (uhci_check_transfer(xfer)) { 884 return; 885 } 886 /* put transfer on interrupt queue */ 887 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 888 889 /* start timeout, if any */ 890 if (xfer->timeout != 0) { 891 usbd_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout); 892 } 893 } 894 895 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last) 896 static uhci_td_t * 897 _uhci_append_td(uhci_td_t *std, uhci_td_t *last) 898 { 899 DPRINTFN(11, "%p to %p\n", std, last); 900 901 /* (sc->sc_bus.mtx) must be locked */ 902 903 std->next = last->next; 904 std->td_next = last->td_next; 905 906 std->prev = last; 907 908 usb_pc_cpu_flush(std->page_cache); 909 910 /* 911 * the last->next->prev is never followed: std->next->prev = std; 912 */ 913 last->next = std; 914 last->td_next = std->td_self; 915 916 usb_pc_cpu_flush(last->page_cache); 917 918 return (std); 919 } 920 921 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last) 922 static uhci_qh_t * 923 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last) 924 { 925 DPRINTFN(11, "%p to %p\n", sqh, last); 926 927 if (sqh->h_prev != NULL) { 928 /* should not happen */ 929 DPRINTFN(0, "QH already linked!\n"); 930 return (last); 931 } 932 /* (sc->sc_bus.mtx) must be locked */ 933 934 sqh->h_next = last->h_next; 935 sqh->qh_h_next = last->qh_h_next; 936 937 sqh->h_prev = last; 938 939 usb_pc_cpu_flush(sqh->page_cache); 940 941 /* 942 * The "last->h_next->h_prev" is never followed: 943 * 944 * "sqh->h_next->h_prev" = sqh; 945 */ 946 947 last->h_next = sqh; 948 last->qh_h_next = sqh->qh_self; 949 950 usb_pc_cpu_flush(last->page_cache); 951 952 return (sqh); 953 } 954 955 /**/ 956 957 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last) 958 static uhci_td_t * 959 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last) 960 { 961 DPRINTFN(11, "%p from %p\n", std, last); 962 963 /* (sc->sc_bus.mtx) must be locked */ 964 965 std->prev->next = std->next; 966 std->prev->td_next = std->td_next; 967 968 usb_pc_cpu_flush(std->prev->page_cache); 969 970 if (std->next) { 971 std->next->prev = std->prev; 972 usb_pc_cpu_flush(std->next->page_cache); 973 } 974 return ((last == std) ? std->prev : last); 975 } 976 977 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last) 978 static uhci_qh_t * 979 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last) 980 { 981 DPRINTFN(11, "%p from %p\n", sqh, last); 982 983 /* (sc->sc_bus.mtx) must be locked */ 984 985 /* only remove if not removed from a queue */ 986 if (sqh->h_prev) { 987 988 sqh->h_prev->h_next = sqh->h_next; 989 sqh->h_prev->qh_h_next = sqh->qh_h_next; 990 991 usb_pc_cpu_flush(sqh->h_prev->page_cache); 992 993 if (sqh->h_next) { 994 sqh->h_next->h_prev = sqh->h_prev; 995 usb_pc_cpu_flush(sqh->h_next->page_cache); 996 } 997 last = ((last == sqh) ? sqh->h_prev : last); 998 999 sqh->h_prev = 0; 1000 1001 usb_pc_cpu_flush(sqh->page_cache); 1002 } 1003 return (last); 1004 } 1005 1006 static void 1007 uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer) 1008 { 1009 struct usb_page_search res; 1010 uint32_t nframes = xfer->nframes; 1011 uint32_t status; 1012 uint32_t offset = 0; 1013 uint32_t *plen = xfer->frlengths; 1014 uint16_t len = 0; 1015 uhci_td_t *td = xfer->td_transfer_first; 1016 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos]; 1017 1018 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1019 xfer, xfer->endpoint); 1020 1021 /* sync any DMA memory before doing fixups */ 1022 1023 usb_bdma_post_sync(xfer); 1024 1025 while (nframes--) { 1026 if (td == NULL) { 1027 panic("%s:%d: out of TD's\n", 1028 __FUNCTION__, __LINE__); 1029 } 1030 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 1031 pp_last = &sc->sc_isoc_p_last[0]; 1032 } 1033 #ifdef USB_DEBUG 1034 if (uhcidebug > 5) { 1035 DPRINTF("isoc TD\n"); 1036 uhci_dump_td(td); 1037 } 1038 #endif 1039 usb_pc_cpu_invalidate(td->page_cache); 1040 status = le32toh(td->td_status); 1041 1042 len = UHCI_TD_GET_ACTLEN(status); 1043 1044 if (len > *plen) { 1045 len = *plen; 1046 } 1047 if (td->fix_pc) { 1048 1049 usbd_get_page(td->fix_pc, 0, &res); 1050 1051 /* copy data from fixup location to real location */ 1052 1053 usb_pc_cpu_invalidate(td->fix_pc); 1054 1055 usbd_copy_in(xfer->frbuffers, offset, 1056 res.buffer, len); 1057 } 1058 offset += *plen; 1059 1060 *plen = len; 1061 1062 /* remove TD from schedule */ 1063 UHCI_REMOVE_TD(td, *pp_last); 1064 1065 pp_last++; 1066 plen++; 1067 td = td->obj_next; 1068 } 1069 1070 xfer->aframes = xfer->nframes; 1071 } 1072 1073 static usb_error_t 1074 uhci_non_isoc_done_sub(struct usb_xfer *xfer) 1075 { 1076 struct usb_page_search res; 1077 uhci_td_t *td; 1078 uhci_td_t *td_alt_next; 1079 uint32_t status; 1080 uint32_t token; 1081 uint16_t len; 1082 1083 td = xfer->td_transfer_cache; 1084 td_alt_next = td->alt_next; 1085 1086 if (xfer->aframes != xfer->nframes) { 1087 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1088 } 1089 while (1) { 1090 1091 usb_pc_cpu_invalidate(td->page_cache); 1092 status = le32toh(td->td_status); 1093 token = le32toh(td->td_token); 1094 1095 /* 1096 * Verify the status and add 1097 * up the actual length: 1098 */ 1099 1100 len = UHCI_TD_GET_ACTLEN(status); 1101 if (len > td->len) { 1102 /* should not happen */ 1103 DPRINTF("Invalid status length, " 1104 "0x%04x/0x%04x bytes\n", len, td->len); 1105 status |= UHCI_TD_STALLED; 1106 1107 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) { 1108 1109 if (td->fix_pc) { 1110 1111 usbd_get_page(td->fix_pc, 0, &res); 1112 1113 /* 1114 * copy data from fixup location to real 1115 * location 1116 */ 1117 1118 usb_pc_cpu_invalidate(td->fix_pc); 1119 1120 usbd_copy_in(xfer->frbuffers + xfer->aframes, 1121 xfer->frlengths[xfer->aframes], res.buffer, len); 1122 } 1123 /* update actual length */ 1124 1125 xfer->frlengths[xfer->aframes] += len; 1126 } 1127 /* Check for last transfer */ 1128 if (((void *)td) == xfer->td_transfer_last) { 1129 td = NULL; 1130 break; 1131 } 1132 if (status & UHCI_TD_STALLED) { 1133 /* the transfer is finished */ 1134 td = NULL; 1135 break; 1136 } 1137 /* Check for short transfer */ 1138 if (len != td->len) { 1139 if (xfer->flags_int.short_frames_ok) { 1140 /* follow alt next */ 1141 td = td->alt_next; 1142 } else { 1143 /* the transfer is finished */ 1144 td = NULL; 1145 } 1146 break; 1147 } 1148 td = td->obj_next; 1149 1150 if (td->alt_next != td_alt_next) { 1151 /* this USB frame is complete */ 1152 break; 1153 } 1154 } 1155 1156 /* update transfer cache */ 1157 1158 xfer->td_transfer_cache = td; 1159 1160 /* update data toggle */ 1161 1162 xfer->endpoint->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1; 1163 1164 #ifdef USB_DEBUG 1165 if (status & UHCI_TD_ERROR) { 1166 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x " 1167 "status=%s%s%s%s%s%s%s%s%s%s%s\n", 1168 xfer->address, xfer->endpointno, xfer->aframes, 1169 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "", 1170 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "", 1171 (status & UHCI_TD_NAK) ? "[NAK]" : "", 1172 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "", 1173 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "", 1174 (status & UHCI_TD_STALLED) ? "[STALLED]" : "", 1175 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1176 (status & UHCI_TD_IOC) ? "[IOC]" : "", 1177 (status & UHCI_TD_IOS) ? "[IOS]" : "", 1178 (status & UHCI_TD_LS) ? "[LS]" : "", 1179 (status & UHCI_TD_SPD) ? "[SPD]" : ""); 1180 } 1181 #endif 1182 if (status & UHCI_TD_STALLED) { 1183 /* try to separate I/O errors from STALL */ 1184 if (UHCI_TD_GET_ERRCNT(status) == 0) 1185 return (USB_ERR_IOERROR); 1186 return (USB_ERR_STALLED); 1187 } 1188 return (USB_ERR_NORMAL_COMPLETION); 1189 } 1190 1191 static void 1192 uhci_non_isoc_done(struct usb_xfer *xfer) 1193 { 1194 usb_error_t err = 0; 1195 1196 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1197 xfer, xfer->endpoint); 1198 1199 #ifdef USB_DEBUG 1200 if (uhcidebug > 10) { 1201 uhci_dump_tds(xfer->td_transfer_first); 1202 } 1203 #endif 1204 1205 /* sync any DMA memory before doing fixups */ 1206 1207 usb_bdma_post_sync(xfer); 1208 1209 /* reset scanner */ 1210 1211 xfer->td_transfer_cache = xfer->td_transfer_first; 1212 1213 if (xfer->flags_int.control_xfr) { 1214 if (xfer->flags_int.control_hdr) { 1215 1216 err = uhci_non_isoc_done_sub(xfer); 1217 } 1218 xfer->aframes = 1; 1219 1220 if (xfer->td_transfer_cache == NULL) { 1221 goto done; 1222 } 1223 } 1224 while (xfer->aframes != xfer->nframes) { 1225 1226 err = uhci_non_isoc_done_sub(xfer); 1227 xfer->aframes++; 1228 1229 if (xfer->td_transfer_cache == NULL) { 1230 goto done; 1231 } 1232 } 1233 1234 if (xfer->flags_int.control_xfr && 1235 !xfer->flags_int.control_act) { 1236 1237 err = uhci_non_isoc_done_sub(xfer); 1238 } 1239 done: 1240 uhci_device_done(xfer, err); 1241 } 1242 1243 /*------------------------------------------------------------------------* 1244 * uhci_check_transfer_sub 1245 * 1246 * The main purpose of this function is to update the data-toggle 1247 * in case it is wrong. 1248 *------------------------------------------------------------------------*/ 1249 static void 1250 uhci_check_transfer_sub(struct usb_xfer *xfer) 1251 { 1252 uhci_qh_t *qh; 1253 uhci_td_t *td; 1254 uhci_td_t *td_alt_next; 1255 1256 uint32_t td_token; 1257 uint32_t td_self; 1258 1259 td = xfer->td_transfer_cache; 1260 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1261 1262 td_token = td->obj_next->td_token; 1263 td = td->alt_next; 1264 xfer->td_transfer_cache = td; 1265 td_self = td->td_self; 1266 td_alt_next = td->alt_next; 1267 1268 if (xfer->flags_int.control_xfr) 1269 goto skip; /* don't touch the DT value! */ 1270 1271 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1)))) 1272 goto skip; /* data toggle has correct value */ 1273 1274 /* 1275 * The data toggle is wrong and we need to toggle it ! 1276 */ 1277 while (1) { 1278 1279 td->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1280 usb_pc_cpu_flush(td->page_cache); 1281 1282 if (td == xfer->td_transfer_last) { 1283 /* last transfer */ 1284 break; 1285 } 1286 td = td->obj_next; 1287 1288 if (td->alt_next != td_alt_next) { 1289 /* next frame */ 1290 break; 1291 } 1292 } 1293 skip: 1294 1295 /* update the QH */ 1296 qh->qh_e_next = td_self; 1297 usb_pc_cpu_flush(qh->page_cache); 1298 1299 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1300 } 1301 1302 /*------------------------------------------------------------------------* 1303 * uhci_check_transfer 1304 * 1305 * Return values: 1306 * 0: USB transfer is not finished 1307 * Else: USB transfer is finished 1308 *------------------------------------------------------------------------*/ 1309 static uint8_t 1310 uhci_check_transfer(struct usb_xfer *xfer) 1311 { 1312 uint32_t status; 1313 uint32_t token; 1314 uhci_td_t *td; 1315 1316 DPRINTFN(16, "xfer=%p checking transfer\n", xfer); 1317 1318 if (xfer->endpoint->methods == &uhci_device_isoc_methods) { 1319 /* isochronous transfer */ 1320 1321 td = xfer->td_transfer_last; 1322 1323 usb_pc_cpu_invalidate(td->page_cache); 1324 status = le32toh(td->td_status); 1325 1326 /* check also if the first is complete */ 1327 1328 td = xfer->td_transfer_first; 1329 1330 usb_pc_cpu_invalidate(td->page_cache); 1331 status |= le32toh(td->td_status); 1332 1333 if (!(status & UHCI_TD_ACTIVE)) { 1334 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1335 goto transferred; 1336 } 1337 } else { 1338 /* non-isochronous transfer */ 1339 1340 /* 1341 * check whether there is an error somewhere 1342 * in the middle, or whether there was a short 1343 * packet (SPD and not ACTIVE) 1344 */ 1345 td = xfer->td_transfer_cache; 1346 1347 while (1) { 1348 usb_pc_cpu_invalidate(td->page_cache); 1349 status = le32toh(td->td_status); 1350 token = le32toh(td->td_token); 1351 1352 /* 1353 * if there is an active TD the transfer isn't done 1354 */ 1355 if (status & UHCI_TD_ACTIVE) { 1356 /* update cache */ 1357 xfer->td_transfer_cache = td; 1358 goto done; 1359 } 1360 /* 1361 * last transfer descriptor makes the transfer done 1362 */ 1363 if (((void *)td) == xfer->td_transfer_last) { 1364 break; 1365 } 1366 /* 1367 * any kind of error makes the transfer done 1368 */ 1369 if (status & UHCI_TD_STALLED) { 1370 break; 1371 } 1372 /* 1373 * check if we reached the last packet 1374 * or if there is a short packet: 1375 */ 1376 if ((td->td_next == htole32(UHCI_PTR_T)) || 1377 (UHCI_TD_GET_ACTLEN(status) < td->len)) { 1378 1379 if (xfer->flags_int.short_frames_ok) { 1380 /* follow alt next */ 1381 if (td->alt_next) { 1382 /* update cache */ 1383 xfer->td_transfer_cache = td; 1384 uhci_check_transfer_sub(xfer); 1385 goto done; 1386 } 1387 } 1388 /* transfer is done */ 1389 break; 1390 } 1391 td = td->obj_next; 1392 } 1393 uhci_non_isoc_done(xfer); 1394 goto transferred; 1395 } 1396 1397 done: 1398 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1399 return (0); 1400 1401 transferred: 1402 return (1); 1403 } 1404 1405 static void 1406 uhci_interrupt_poll(uhci_softc_t *sc) 1407 { 1408 struct usb_xfer *xfer; 1409 1410 repeat: 1411 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1412 /* 1413 * check if transfer is transferred 1414 */ 1415 if (uhci_check_transfer(xfer)) { 1416 /* queue has been modified */ 1417 goto repeat; 1418 } 1419 } 1420 } 1421 1422 /*------------------------------------------------------------------------* 1423 * uhci_interrupt - UHCI interrupt handler 1424 * 1425 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1426 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1427 * is present ! 1428 *------------------------------------------------------------------------*/ 1429 void 1430 uhci_interrupt(uhci_softc_t *sc) 1431 { 1432 uint32_t status; 1433 1434 USB_BUS_LOCK(&sc->sc_bus); 1435 1436 DPRINTFN(16, "real interrupt\n"); 1437 1438 #ifdef USB_DEBUG 1439 if (uhcidebug > 15) { 1440 uhci_dumpregs(sc); 1441 } 1442 #endif 1443 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1444 if (status == 0) { 1445 /* the interrupt was not for us */ 1446 goto done; 1447 } 1448 if (status & (UHCI_STS_RD | UHCI_STS_HSE | 1449 UHCI_STS_HCPE | UHCI_STS_HCH)) { 1450 1451 if (status & UHCI_STS_RD) { 1452 #ifdef USB_DEBUG 1453 printf("%s: resume detect\n", 1454 __FUNCTION__); 1455 #endif 1456 } 1457 if (status & UHCI_STS_HSE) { 1458 printf("%s: host system error\n", 1459 __FUNCTION__); 1460 } 1461 if (status & UHCI_STS_HCPE) { 1462 printf("%s: host controller process error\n", 1463 __FUNCTION__); 1464 } 1465 if (status & UHCI_STS_HCH) { 1466 /* no acknowledge needed */ 1467 DPRINTF("%s: host controller halted\n", 1468 __FUNCTION__); 1469 #ifdef USB_DEBUG 1470 if (uhcidebug > 0) { 1471 uhci_dump_all(sc); 1472 } 1473 #endif 1474 } 1475 } 1476 /* get acknowledge bits */ 1477 status &= (UHCI_STS_USBINT | 1478 UHCI_STS_USBEI | 1479 UHCI_STS_RD | 1480 UHCI_STS_HSE | 1481 UHCI_STS_HCPE | 1482 UHCI_STS_HCH); 1483 1484 if (status == 0) { 1485 /* nothing to acknowledge */ 1486 goto done; 1487 } 1488 /* acknowledge interrupts */ 1489 UWRITE2(sc, UHCI_STS, status); 1490 1491 /* poll all the USB transfers */ 1492 uhci_interrupt_poll(sc); 1493 1494 done: 1495 USB_BUS_UNLOCK(&sc->sc_bus); 1496 } 1497 1498 /* 1499 * called when a request does not complete 1500 */ 1501 static void 1502 uhci_timeout(void *arg) 1503 { 1504 struct usb_xfer *xfer = arg; 1505 1506 DPRINTF("xfer=%p\n", xfer); 1507 1508 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1509 1510 /* transfer is transferred */ 1511 uhci_device_done(xfer, USB_ERR_TIMEOUT); 1512 } 1513 1514 static void 1515 uhci_do_poll(struct usb_bus *bus) 1516 { 1517 struct uhci_softc *sc = UHCI_BUS2SC(bus); 1518 1519 USB_BUS_LOCK(&sc->sc_bus); 1520 uhci_interrupt_poll(sc); 1521 USB_BUS_UNLOCK(&sc->sc_bus); 1522 } 1523 1524 static void 1525 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp) 1526 { 1527 uhci_td_t *td; 1528 uhci_td_t *td_next; 1529 uhci_td_t *td_alt_next; 1530 uint32_t average; 1531 uint32_t len_old; 1532 uint8_t shortpkt_old; 1533 uint8_t precompute; 1534 1535 td_alt_next = NULL; 1536 shortpkt_old = temp->shortpkt; 1537 len_old = temp->len; 1538 precompute = 1; 1539 1540 /* software is used to detect short incoming transfers */ 1541 1542 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) { 1543 temp->td_status |= htole32(UHCI_TD_SPD); 1544 } else { 1545 temp->td_status &= ~htole32(UHCI_TD_SPD); 1546 } 1547 1548 temp->ml.buf_offset = 0; 1549 1550 restart: 1551 1552 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1553 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average)); 1554 1555 td = temp->td; 1556 td_next = temp->td_next; 1557 1558 while (1) { 1559 1560 if (temp->len == 0) { 1561 1562 if (temp->shortpkt) { 1563 break; 1564 } 1565 /* send a Zero Length Packet, ZLP, last */ 1566 1567 temp->shortpkt = 1; 1568 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0)); 1569 average = 0; 1570 1571 } else { 1572 1573 average = temp->average; 1574 1575 if (temp->len < average) { 1576 temp->shortpkt = 1; 1577 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1578 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len)); 1579 average = temp->len; 1580 } 1581 } 1582 1583 if (td_next == NULL) { 1584 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__); 1585 } 1586 /* get next TD */ 1587 1588 td = td_next; 1589 td_next = td->obj_next; 1590 1591 /* check if we are pre-computing */ 1592 1593 if (precompute) { 1594 1595 /* update remaining length */ 1596 1597 temp->len -= average; 1598 1599 continue; 1600 } 1601 /* fill out current TD */ 1602 1603 td->td_status = temp->td_status; 1604 td->td_token = temp->td_token; 1605 1606 /* update data toggle */ 1607 1608 temp->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1609 1610 if (average == 0) { 1611 1612 td->len = 0; 1613 td->td_buffer = 0; 1614 td->fix_pc = NULL; 1615 1616 } else { 1617 1618 /* update remaining length */ 1619 1620 temp->len -= average; 1621 1622 td->len = average; 1623 1624 /* fill out buffer pointer and do fixup, if any */ 1625 1626 uhci_mem_layout_fixup(&temp->ml, td); 1627 } 1628 1629 td->alt_next = td_alt_next; 1630 1631 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1632 /* we need to receive these frames one by one ! */ 1633 td->td_status |= htole32(UHCI_TD_IOC); 1634 td->td_next = htole32(UHCI_PTR_T); 1635 } else { 1636 if (td_next) { 1637 /* link the current TD with the next one */ 1638 td->td_next = td_next->td_self; 1639 } 1640 } 1641 1642 usb_pc_cpu_flush(td->page_cache); 1643 } 1644 1645 if (precompute) { 1646 precompute = 0; 1647 1648 /* setup alt next pointer, if any */ 1649 if (temp->last_frame) { 1650 td_alt_next = NULL; 1651 } else { 1652 /* we use this field internally */ 1653 td_alt_next = td_next; 1654 } 1655 1656 /* restore */ 1657 temp->shortpkt = shortpkt_old; 1658 temp->len = len_old; 1659 goto restart; 1660 } 1661 temp->td = td; 1662 temp->td_next = td_next; 1663 } 1664 1665 static uhci_td_t * 1666 uhci_setup_standard_chain(struct usb_xfer *xfer) 1667 { 1668 struct uhci_std_temp temp; 1669 uhci_td_t *td; 1670 uint32_t x; 1671 1672 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1673 xfer->address, UE_GET_ADDR(xfer->endpointno), 1674 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1675 1676 temp.average = xfer->max_frame_size; 1677 temp.max_frame_size = xfer->max_frame_size; 1678 1679 /* toggle the DMA set we are using */ 1680 xfer->flags_int.curr_dma_set ^= 1; 1681 1682 /* get next DMA set */ 1683 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1684 xfer->td_transfer_first = td; 1685 xfer->td_transfer_cache = td; 1686 1687 temp.td = NULL; 1688 temp.td_next = td; 1689 temp.last_frame = 0; 1690 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1691 1692 uhci_mem_layout_init(&temp.ml, xfer); 1693 1694 temp.td_status = 1695 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | 1696 UHCI_TD_ACTIVE)); 1697 1698 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1699 temp.td_status |= htole32(UHCI_TD_LS); 1700 } 1701 temp.td_token = 1702 htole32(UHCI_TD_SET_ENDPT(xfer->endpointno) | 1703 UHCI_TD_SET_DEVADDR(xfer->address)); 1704 1705 if (xfer->endpoint->toggle_next) { 1706 /* DATA1 is next */ 1707 temp.td_token |= htole32(UHCI_TD_SET_DT(1)); 1708 } 1709 /* check if we should prepend a setup message */ 1710 1711 if (xfer->flags_int.control_xfr) { 1712 1713 if (xfer->flags_int.control_hdr) { 1714 1715 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1716 UHCI_TD_SET_ENDPT(0xF)); 1717 temp.td_token |= htole32(UHCI_TD_PID_SETUP | 1718 UHCI_TD_SET_DT(0)); 1719 1720 temp.len = xfer->frlengths[0]; 1721 temp.ml.buf_pc = xfer->frbuffers + 0; 1722 temp.shortpkt = temp.len ? 1 : 0; 1723 /* check for last frame */ 1724 if (xfer->nframes == 1) { 1725 /* no STATUS stage yet, SETUP is last */ 1726 if (xfer->flags_int.control_act) { 1727 temp.last_frame = 1; 1728 temp.setup_alt_next = 0; 1729 } 1730 } 1731 uhci_setup_standard_chain_sub(&temp); 1732 } 1733 x = 1; 1734 } else { 1735 x = 0; 1736 } 1737 1738 while (x != xfer->nframes) { 1739 1740 /* DATA0 / DATA1 message */ 1741 1742 temp.len = xfer->frlengths[x]; 1743 temp.ml.buf_pc = xfer->frbuffers + x; 1744 1745 x++; 1746 1747 if (x == xfer->nframes) { 1748 if (xfer->flags_int.control_xfr) { 1749 /* no STATUS stage yet, DATA is last */ 1750 if (xfer->flags_int.control_act) { 1751 temp.last_frame = 1; 1752 temp.setup_alt_next = 0; 1753 } 1754 } else { 1755 temp.last_frame = 1; 1756 temp.setup_alt_next = 0; 1757 } 1758 } 1759 /* 1760 * Keep previous data toggle, 1761 * device address and endpoint number: 1762 */ 1763 1764 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1765 UHCI_TD_SET_ENDPT(0xF) | 1766 UHCI_TD_SET_DT(1)); 1767 1768 if (temp.len == 0) { 1769 1770 /* make sure that we send an USB packet */ 1771 1772 temp.shortpkt = 0; 1773 1774 } else { 1775 1776 /* regular data transfer */ 1777 1778 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1779 } 1780 1781 /* set endpoint direction */ 1782 1783 temp.td_token |= 1784 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1785 htole32(UHCI_TD_PID_IN) : 1786 htole32(UHCI_TD_PID_OUT); 1787 1788 uhci_setup_standard_chain_sub(&temp); 1789 } 1790 1791 /* check if we should append a status stage */ 1792 1793 if (xfer->flags_int.control_xfr && 1794 !xfer->flags_int.control_act) { 1795 1796 /* 1797 * send a DATA1 message and reverse the current endpoint 1798 * direction 1799 */ 1800 1801 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1802 UHCI_TD_SET_ENDPT(0xF) | 1803 UHCI_TD_SET_DT(1)); 1804 temp.td_token |= 1805 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1806 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) : 1807 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1)); 1808 1809 temp.len = 0; 1810 temp.ml.buf_pc = NULL; 1811 temp.shortpkt = 0; 1812 temp.last_frame = 1; 1813 temp.setup_alt_next = 0; 1814 1815 uhci_setup_standard_chain_sub(&temp); 1816 } 1817 td = temp.td; 1818 1819 /* Ensure that last TD is terminating: */ 1820 td->td_next = htole32(UHCI_PTR_T); 1821 1822 /* set interrupt bit */ 1823 1824 td->td_status |= htole32(UHCI_TD_IOC); 1825 1826 usb_pc_cpu_flush(td->page_cache); 1827 1828 /* must have at least one frame! */ 1829 1830 xfer->td_transfer_last = td; 1831 1832 #ifdef USB_DEBUG 1833 if (uhcidebug > 8) { 1834 DPRINTF("nexttog=%d; data before transfer:\n", 1835 xfer->endpoint->toggle_next); 1836 uhci_dump_tds(xfer->td_transfer_first); 1837 } 1838 #endif 1839 return (xfer->td_transfer_first); 1840 } 1841 1842 /* NOTE: "done" can be run two times in a row, 1843 * from close and from interrupt 1844 */ 1845 1846 static void 1847 uhci_device_done(struct usb_xfer *xfer, usb_error_t error) 1848 { 1849 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1850 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1851 uhci_qh_t *qh; 1852 1853 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1854 1855 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1856 xfer, xfer->endpoint, error); 1857 1858 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1859 if (qh) { 1860 usb_pc_cpu_invalidate(qh->page_cache); 1861 } 1862 if (xfer->flags_int.bandwidth_reclaimed) { 1863 xfer->flags_int.bandwidth_reclaimed = 0; 1864 uhci_rem_loop(sc); 1865 } 1866 if (methods == &uhci_device_bulk_methods) { 1867 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 1868 } 1869 if (methods == &uhci_device_ctrl_methods) { 1870 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1871 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 1872 } else { 1873 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 1874 } 1875 } 1876 if (methods == &uhci_device_intr_methods) { 1877 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 1878 } 1879 /* 1880 * Only finish isochronous transfers once 1881 * which will update "xfer->frlengths". 1882 */ 1883 if (xfer->td_transfer_first && 1884 xfer->td_transfer_last) { 1885 if (methods == &uhci_device_isoc_methods) { 1886 uhci_isoc_done(sc, xfer); 1887 } 1888 xfer->td_transfer_first = NULL; 1889 xfer->td_transfer_last = NULL; 1890 } 1891 /* dequeue transfer and start next transfer */ 1892 usbd_transfer_done(xfer, error); 1893 } 1894 1895 /*------------------------------------------------------------------------* 1896 * uhci bulk support 1897 *------------------------------------------------------------------------*/ 1898 static void 1899 uhci_device_bulk_open(struct usb_xfer *xfer) 1900 { 1901 return; 1902 } 1903 1904 static void 1905 uhci_device_bulk_close(struct usb_xfer *xfer) 1906 { 1907 uhci_device_done(xfer, USB_ERR_CANCELLED); 1908 } 1909 1910 static void 1911 uhci_device_bulk_enter(struct usb_xfer *xfer) 1912 { 1913 return; 1914 } 1915 1916 static void 1917 uhci_device_bulk_start(struct usb_xfer *xfer) 1918 { 1919 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1920 uhci_td_t *td; 1921 uhci_qh_t *qh; 1922 1923 /* setup TD's */ 1924 td = uhci_setup_standard_chain(xfer); 1925 1926 /* setup QH */ 1927 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1928 1929 qh->e_next = td; 1930 qh->qh_e_next = td->td_self; 1931 1932 if (xfer->xroot->udev->flags.self_suspended == 0) { 1933 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 1934 uhci_add_loop(sc); 1935 xfer->flags_int.bandwidth_reclaimed = 1; 1936 } else { 1937 usb_pc_cpu_flush(qh->page_cache); 1938 } 1939 1940 /* put transfer on interrupt queue */ 1941 uhci_transfer_intr_enqueue(xfer); 1942 } 1943 1944 static const struct usb_pipe_methods uhci_device_bulk_methods = 1945 { 1946 .open = uhci_device_bulk_open, 1947 .close = uhci_device_bulk_close, 1948 .enter = uhci_device_bulk_enter, 1949 .start = uhci_device_bulk_start, 1950 }; 1951 1952 /*------------------------------------------------------------------------* 1953 * uhci control support 1954 *------------------------------------------------------------------------*/ 1955 static void 1956 uhci_device_ctrl_open(struct usb_xfer *xfer) 1957 { 1958 return; 1959 } 1960 1961 static void 1962 uhci_device_ctrl_close(struct usb_xfer *xfer) 1963 { 1964 uhci_device_done(xfer, USB_ERR_CANCELLED); 1965 } 1966 1967 static void 1968 uhci_device_ctrl_enter(struct usb_xfer *xfer) 1969 { 1970 return; 1971 } 1972 1973 static void 1974 uhci_device_ctrl_start(struct usb_xfer *xfer) 1975 { 1976 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1977 uhci_qh_t *qh; 1978 uhci_td_t *td; 1979 1980 /* setup TD's */ 1981 td = uhci_setup_standard_chain(xfer); 1982 1983 /* setup QH */ 1984 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1985 1986 qh->e_next = td; 1987 qh->qh_e_next = td->td_self; 1988 1989 /* 1990 * NOTE: some devices choke on bandwidth- reclamation for control 1991 * transfers 1992 */ 1993 if (xfer->xroot->udev->flags.self_suspended == 0) { 1994 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1995 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 1996 } else { 1997 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 1998 } 1999 } else { 2000 usb_pc_cpu_flush(qh->page_cache); 2001 } 2002 /* put transfer on interrupt queue */ 2003 uhci_transfer_intr_enqueue(xfer); 2004 } 2005 2006 static const struct usb_pipe_methods uhci_device_ctrl_methods = 2007 { 2008 .open = uhci_device_ctrl_open, 2009 .close = uhci_device_ctrl_close, 2010 .enter = uhci_device_ctrl_enter, 2011 .start = uhci_device_ctrl_start, 2012 }; 2013 2014 /*------------------------------------------------------------------------* 2015 * uhci interrupt support 2016 *------------------------------------------------------------------------*/ 2017 static void 2018 uhci_device_intr_open(struct usb_xfer *xfer) 2019 { 2020 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2021 uint16_t best; 2022 uint16_t bit; 2023 uint16_t x; 2024 2025 best = 0; 2026 bit = UHCI_IFRAMELIST_COUNT / 2; 2027 while (bit) { 2028 if (xfer->interval >= bit) { 2029 x = bit; 2030 best = bit; 2031 while (x & bit) { 2032 if (sc->sc_intr_stat[x] < 2033 sc->sc_intr_stat[best]) { 2034 best = x; 2035 } 2036 x++; 2037 } 2038 break; 2039 } 2040 bit >>= 1; 2041 } 2042 2043 sc->sc_intr_stat[best]++; 2044 xfer->qh_pos = best; 2045 2046 DPRINTFN(3, "best=%d interval=%d\n", 2047 best, xfer->interval); 2048 } 2049 2050 static void 2051 uhci_device_intr_close(struct usb_xfer *xfer) 2052 { 2053 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2054 2055 sc->sc_intr_stat[xfer->qh_pos]--; 2056 2057 uhci_device_done(xfer, USB_ERR_CANCELLED); 2058 } 2059 2060 static void 2061 uhci_device_intr_enter(struct usb_xfer *xfer) 2062 { 2063 return; 2064 } 2065 2066 static void 2067 uhci_device_intr_start(struct usb_xfer *xfer) 2068 { 2069 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2070 uhci_qh_t *qh; 2071 uhci_td_t *td; 2072 2073 /* setup TD's */ 2074 td = uhci_setup_standard_chain(xfer); 2075 2076 /* setup QH */ 2077 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2078 2079 qh->e_next = td; 2080 qh->qh_e_next = td->td_self; 2081 2082 if (xfer->xroot->udev->flags.self_suspended == 0) { 2083 /* enter QHs into the controller data structures */ 2084 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 2085 } else { 2086 usb_pc_cpu_flush(qh->page_cache); 2087 } 2088 2089 /* put transfer on interrupt queue */ 2090 uhci_transfer_intr_enqueue(xfer); 2091 } 2092 2093 static const struct usb_pipe_methods uhci_device_intr_methods = 2094 { 2095 .open = uhci_device_intr_open, 2096 .close = uhci_device_intr_close, 2097 .enter = uhci_device_intr_enter, 2098 .start = uhci_device_intr_start, 2099 }; 2100 2101 /*------------------------------------------------------------------------* 2102 * uhci isochronous support 2103 *------------------------------------------------------------------------*/ 2104 static void 2105 uhci_device_isoc_open(struct usb_xfer *xfer) 2106 { 2107 uhci_td_t *td; 2108 uint32_t td_token; 2109 uint8_t ds; 2110 2111 td_token = 2112 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 2113 UHCI_TD_IN(0, xfer->endpointno, xfer->address, 0) : 2114 UHCI_TD_OUT(0, xfer->endpointno, xfer->address, 0); 2115 2116 td_token = htole32(td_token); 2117 2118 /* initialize all TD's */ 2119 2120 for (ds = 0; ds != 2; ds++) { 2121 2122 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2123 2124 /* mark TD as inactive */ 2125 td->td_status = htole32(UHCI_TD_IOS); 2126 td->td_token = td_token; 2127 2128 usb_pc_cpu_flush(td->page_cache); 2129 } 2130 } 2131 } 2132 2133 static void 2134 uhci_device_isoc_close(struct usb_xfer *xfer) 2135 { 2136 uhci_device_done(xfer, USB_ERR_CANCELLED); 2137 } 2138 2139 static void 2140 uhci_device_isoc_enter(struct usb_xfer *xfer) 2141 { 2142 struct uhci_mem_layout ml; 2143 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2144 uint32_t nframes; 2145 uint32_t temp; 2146 uint32_t *plen; 2147 2148 #ifdef USB_DEBUG 2149 uint8_t once = 1; 2150 2151 #endif 2152 uhci_td_t *td; 2153 uhci_td_t *td_last = NULL; 2154 uhci_td_t **pp_last; 2155 2156 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2157 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2158 2159 nframes = UREAD2(sc, UHCI_FRNUM); 2160 2161 temp = (nframes - xfer->endpoint->isoc_next) & 2162 (UHCI_VFRAMELIST_COUNT - 1); 2163 2164 if ((xfer->endpoint->is_synced == 0) || 2165 (temp < xfer->nframes)) { 2166 /* 2167 * If there is data underflow or the pipe queue is empty we 2168 * schedule the transfer a few frames ahead of the current 2169 * frame position. Else two isochronous transfers might 2170 * overlap. 2171 */ 2172 xfer->endpoint->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1); 2173 xfer->endpoint->is_synced = 1; 2174 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2175 } 2176 /* 2177 * compute how many milliseconds the insertion is ahead of the 2178 * current frame position: 2179 */ 2180 temp = (xfer->endpoint->isoc_next - nframes) & 2181 (UHCI_VFRAMELIST_COUNT - 1); 2182 2183 /* 2184 * pre-compute when the isochronous transfer will be finished: 2185 */ 2186 xfer->isoc_time_complete = 2187 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2188 xfer->nframes; 2189 2190 /* get the real number of frames */ 2191 2192 nframes = xfer->nframes; 2193 2194 uhci_mem_layout_init(&ml, xfer); 2195 2196 plen = xfer->frlengths; 2197 2198 /* toggle the DMA set we are using */ 2199 xfer->flags_int.curr_dma_set ^= 1; 2200 2201 /* get next DMA set */ 2202 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2203 xfer->td_transfer_first = td; 2204 2205 pp_last = &sc->sc_isoc_p_last[xfer->endpoint->isoc_next]; 2206 2207 /* store starting position */ 2208 2209 xfer->qh_pos = xfer->endpoint->isoc_next; 2210 2211 while (nframes--) { 2212 if (td == NULL) { 2213 panic("%s:%d: out of TD's\n", 2214 __FUNCTION__, __LINE__); 2215 } 2216 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 2217 pp_last = &sc->sc_isoc_p_last[0]; 2218 } 2219 if (*plen > xfer->max_frame_size) { 2220 #ifdef USB_DEBUG 2221 if (once) { 2222 once = 0; 2223 printf("%s: frame length(%d) exceeds %d " 2224 "bytes (frame truncated)\n", 2225 __FUNCTION__, *plen, 2226 xfer->max_frame_size); 2227 } 2228 #endif 2229 *plen = xfer->max_frame_size; 2230 } 2231 /* reuse td_token from last transfer */ 2232 2233 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2234 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen)); 2235 2236 td->len = *plen; 2237 2238 if (td->len == 0) { 2239 /* 2240 * Do not call "uhci_mem_layout_fixup()" when the 2241 * length is zero! 2242 */ 2243 td->td_buffer = 0; 2244 td->fix_pc = NULL; 2245 2246 } else { 2247 2248 /* fill out buffer pointer and do fixup, if any */ 2249 2250 uhci_mem_layout_fixup(&ml, td); 2251 2252 } 2253 2254 /* update status */ 2255 if (nframes == 0) { 2256 td->td_status = htole32 2257 (UHCI_TD_ZERO_ACTLEN 2258 (UHCI_TD_SET_ERRCNT(0) | 2259 UHCI_TD_ACTIVE | 2260 UHCI_TD_IOS | 2261 UHCI_TD_IOC)); 2262 } else { 2263 td->td_status = htole32 2264 (UHCI_TD_ZERO_ACTLEN 2265 (UHCI_TD_SET_ERRCNT(0) | 2266 UHCI_TD_ACTIVE | 2267 UHCI_TD_IOS)); 2268 } 2269 2270 usb_pc_cpu_flush(td->page_cache); 2271 2272 #ifdef USB_DEBUG 2273 if (uhcidebug > 5) { 2274 DPRINTF("TD %d\n", nframes); 2275 uhci_dump_td(td); 2276 } 2277 #endif 2278 /* insert TD into schedule */ 2279 UHCI_APPEND_TD(td, *pp_last); 2280 pp_last++; 2281 2282 plen++; 2283 td_last = td; 2284 td = td->obj_next; 2285 } 2286 2287 xfer->td_transfer_last = td_last; 2288 2289 /* update isoc_next */ 2290 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) & 2291 (UHCI_VFRAMELIST_COUNT - 1); 2292 } 2293 2294 static void 2295 uhci_device_isoc_start(struct usb_xfer *xfer) 2296 { 2297 /* put transfer on interrupt queue */ 2298 uhci_transfer_intr_enqueue(xfer); 2299 } 2300 2301 static const struct usb_pipe_methods uhci_device_isoc_methods = 2302 { 2303 .open = uhci_device_isoc_open, 2304 .close = uhci_device_isoc_close, 2305 .enter = uhci_device_isoc_enter, 2306 .start = uhci_device_isoc_start, 2307 }; 2308 2309 /*------------------------------------------------------------------------* 2310 * uhci root control support 2311 *------------------------------------------------------------------------* 2312 * Simulate a hardware hub by handling all the necessary requests. 2313 *------------------------------------------------------------------------*/ 2314 2315 static const 2316 struct usb_device_descriptor uhci_devd = 2317 { 2318 sizeof(struct usb_device_descriptor), 2319 UDESC_DEVICE, /* type */ 2320 {0x00, 0x01}, /* USB version */ 2321 UDCLASS_HUB, /* class */ 2322 UDSUBCLASS_HUB, /* subclass */ 2323 UDPROTO_FSHUB, /* protocol */ 2324 64, /* max packet */ 2325 {0}, {0}, {0x00, 0x01}, /* device id */ 2326 1, 2, 0, /* string indexes */ 2327 1 /* # of configurations */ 2328 }; 2329 2330 static const struct uhci_config_desc uhci_confd = { 2331 .confd = { 2332 .bLength = sizeof(struct usb_config_descriptor), 2333 .bDescriptorType = UDESC_CONFIG, 2334 .wTotalLength[0] = sizeof(uhci_confd), 2335 .bNumInterface = 1, 2336 .bConfigurationValue = 1, 2337 .iConfiguration = 0, 2338 .bmAttributes = UC_SELF_POWERED, 2339 .bMaxPower = 0 /* max power */ 2340 }, 2341 .ifcd = { 2342 .bLength = sizeof(struct usb_interface_descriptor), 2343 .bDescriptorType = UDESC_INTERFACE, 2344 .bNumEndpoints = 1, 2345 .bInterfaceClass = UICLASS_HUB, 2346 .bInterfaceSubClass = UISUBCLASS_HUB, 2347 .bInterfaceProtocol = UIPROTO_FSHUB, 2348 }, 2349 .endpd = { 2350 .bLength = sizeof(struct usb_endpoint_descriptor), 2351 .bDescriptorType = UDESC_ENDPOINT, 2352 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 2353 .bmAttributes = UE_INTERRUPT, 2354 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2355 .bInterval = 255, 2356 }, 2357 }; 2358 2359 static const 2360 struct usb_hub_descriptor_min uhci_hubd_piix = 2361 { 2362 .bDescLength = sizeof(uhci_hubd_piix), 2363 .bDescriptorType = UDESC_HUB, 2364 .bNbrPorts = 2, 2365 .wHubCharacteristics = {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0}, 2366 .bPwrOn2PwrGood = 50, 2367 }; 2368 2369 /* 2370 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 2371 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 2372 * should not be used by the USB subsystem. As we cannot issue a 2373 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 2374 * will be enabled as part of the reset. 2375 * 2376 * On the VT83C572, the port cannot be successfully enabled until the 2377 * outstanding "port enable change" and "connection status change" 2378 * events have been reset. 2379 */ 2380 static usb_error_t 2381 uhci_portreset(uhci_softc_t *sc, uint16_t index) 2382 { 2383 uint16_t port; 2384 uint16_t x; 2385 uint8_t lim; 2386 2387 if (index == 1) 2388 port = UHCI_PORTSC1; 2389 else if (index == 2) 2390 port = UHCI_PORTSC2; 2391 else 2392 return (USB_ERR_IOERROR); 2393 2394 /* 2395 * Before we do anything, turn on SOF messages on the USB 2396 * BUS. Some USB devices do not cope without them! 2397 */ 2398 uhci_restart(sc); 2399 2400 x = URWMASK(UREAD2(sc, port)); 2401 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2402 2403 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2404 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 2405 2406 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n", 2407 index, UREAD2(sc, port)); 2408 2409 x = URWMASK(UREAD2(sc, port)); 2410 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2411 2412 2413 mtx_unlock(&sc->sc_bus.bus_mtx); 2414 2415 /* 2416 * This delay needs to be exactly 100us, else some USB devices 2417 * fail to attach! 2418 */ 2419 DELAY(100); 2420 2421 mtx_lock(&sc->sc_bus.bus_mtx); 2422 2423 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n", 2424 index, UREAD2(sc, port)); 2425 2426 x = URWMASK(UREAD2(sc, port)); 2427 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2428 2429 for (lim = 0; lim < 12; lim++) { 2430 2431 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2432 USB_MS_TO_TICKS(usb_port_reset_delay)); 2433 2434 x = UREAD2(sc, port); 2435 2436 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n", 2437 index, lim, x); 2438 2439 if (!(x & UHCI_PORTSC_CCS)) { 2440 /* 2441 * No device is connected (or was disconnected 2442 * during reset). Consider the port reset. 2443 * The delay must be long enough to ensure on 2444 * the initial iteration that the device 2445 * connection will have been registered. 50ms 2446 * appears to be sufficient, but 20ms is not. 2447 */ 2448 DPRINTFN(4, "uhci port %d loop %u, device detached\n", 2449 index, lim); 2450 goto done; 2451 } 2452 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 2453 /* 2454 * Port enabled changed and/or connection 2455 * status changed were set. Reset either or 2456 * both raised flags (by writing a 1 to that 2457 * bit), and wait again for state to settle. 2458 */ 2459 UWRITE2(sc, port, URWMASK(x) | 2460 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 2461 continue; 2462 } 2463 if (x & UHCI_PORTSC_PE) { 2464 /* port is enabled */ 2465 goto done; 2466 } 2467 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 2468 } 2469 2470 DPRINTFN(2, "uhci port %d reset timed out\n", index); 2471 return (USB_ERR_TIMEOUT); 2472 2473 done: 2474 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n", 2475 index, UREAD2(sc, port)); 2476 2477 sc->sc_isreset = 1; 2478 return (USB_ERR_NORMAL_COMPLETION); 2479 } 2480 2481 static usb_error_t 2482 uhci_roothub_exec(struct usb_device *udev, 2483 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2484 { 2485 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 2486 const void *ptr; 2487 const char *str_ptr; 2488 uint16_t x; 2489 uint16_t port; 2490 uint16_t value; 2491 uint16_t index; 2492 uint16_t status; 2493 uint16_t change; 2494 uint16_t len; 2495 usb_error_t err; 2496 2497 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2498 2499 /* buffer reset */ 2500 ptr = (const void *)&sc->sc_hub_desc.temp; 2501 len = 0; 2502 err = 0; 2503 2504 value = UGETW(req->wValue); 2505 index = UGETW(req->wIndex); 2506 2507 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2508 "wValue=0x%04x wIndex=0x%04x\n", 2509 req->bmRequestType, req->bRequest, 2510 UGETW(req->wLength), value, index); 2511 2512 #define C(x,y) ((x) | ((y) << 8)) 2513 switch (C(req->bRequest, req->bmRequestType)) { 2514 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2515 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2516 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2517 /* 2518 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2519 * for the integrated root hub. 2520 */ 2521 break; 2522 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2523 len = 1; 2524 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2525 break; 2526 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2527 switch (value >> 8) { 2528 case UDESC_DEVICE: 2529 if ((value & 0xff) != 0) { 2530 err = USB_ERR_IOERROR; 2531 goto done; 2532 } 2533 len = sizeof(uhci_devd); 2534 ptr = (const void *)&uhci_devd; 2535 break; 2536 2537 case UDESC_CONFIG: 2538 if ((value & 0xff) != 0) { 2539 err = USB_ERR_IOERROR; 2540 goto done; 2541 } 2542 len = sizeof(uhci_confd); 2543 ptr = (const void *)&uhci_confd; 2544 break; 2545 2546 case UDESC_STRING: 2547 switch (value & 0xff) { 2548 case 0: /* Language table */ 2549 str_ptr = "\001"; 2550 break; 2551 2552 case 1: /* Vendor */ 2553 str_ptr = sc->sc_vendor; 2554 break; 2555 2556 case 2: /* Product */ 2557 str_ptr = "UHCI root HUB"; 2558 break; 2559 2560 default: 2561 str_ptr = ""; 2562 break; 2563 } 2564 2565 len = usb_make_str_desc 2566 (sc->sc_hub_desc.temp, 2567 sizeof(sc->sc_hub_desc.temp), 2568 str_ptr); 2569 break; 2570 2571 default: 2572 err = USB_ERR_IOERROR; 2573 goto done; 2574 } 2575 break; 2576 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2577 len = 1; 2578 sc->sc_hub_desc.temp[0] = 0; 2579 break; 2580 case C(UR_GET_STATUS, UT_READ_DEVICE): 2581 len = 2; 2582 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2583 break; 2584 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2585 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2586 len = 2; 2587 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2588 break; 2589 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2590 if (value >= UHCI_MAX_DEVICES) { 2591 err = USB_ERR_IOERROR; 2592 goto done; 2593 } 2594 sc->sc_addr = value; 2595 break; 2596 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2597 if ((value != 0) && (value != 1)) { 2598 err = USB_ERR_IOERROR; 2599 goto done; 2600 } 2601 sc->sc_conf = value; 2602 break; 2603 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2604 break; 2605 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2606 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2607 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2608 err = USB_ERR_IOERROR; 2609 goto done; 2610 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2611 break; 2612 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2613 break; 2614 /* Hub requests */ 2615 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2616 break; 2617 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2618 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE " 2619 "port=%d feature=%d\n", 2620 index, value); 2621 if (index == 1) 2622 port = UHCI_PORTSC1; 2623 else if (index == 2) 2624 port = UHCI_PORTSC2; 2625 else { 2626 err = USB_ERR_IOERROR; 2627 goto done; 2628 } 2629 switch (value) { 2630 case UHF_PORT_ENABLE: 2631 x = URWMASK(UREAD2(sc, port)); 2632 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2633 break; 2634 case UHF_PORT_SUSPEND: 2635 x = URWMASK(UREAD2(sc, port)); 2636 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP)); 2637 break; 2638 case UHF_PORT_RESET: 2639 x = URWMASK(UREAD2(sc, port)); 2640 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2641 break; 2642 case UHF_C_PORT_CONNECTION: 2643 x = URWMASK(UREAD2(sc, port)); 2644 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2645 break; 2646 case UHF_C_PORT_ENABLE: 2647 x = URWMASK(UREAD2(sc, port)); 2648 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2649 break; 2650 case UHF_C_PORT_OVER_CURRENT: 2651 x = URWMASK(UREAD2(sc, port)); 2652 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2653 break; 2654 case UHF_C_PORT_RESET: 2655 sc->sc_isreset = 0; 2656 err = USB_ERR_NORMAL_COMPLETION; 2657 goto done; 2658 case UHF_C_PORT_SUSPEND: 2659 sc->sc_isresumed &= ~(1 << index); 2660 break; 2661 case UHF_PORT_CONNECTION: 2662 case UHF_PORT_OVER_CURRENT: 2663 case UHF_PORT_POWER: 2664 case UHF_PORT_LOW_SPEED: 2665 default: 2666 err = USB_ERR_IOERROR; 2667 goto done; 2668 } 2669 break; 2670 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2671 if (index == 1) 2672 port = UHCI_PORTSC1; 2673 else if (index == 2) 2674 port = UHCI_PORTSC2; 2675 else { 2676 err = USB_ERR_IOERROR; 2677 goto done; 2678 } 2679 len = 1; 2680 sc->sc_hub_desc.temp[0] = 2681 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2682 UHCI_PORTSC_LS_SHIFT); 2683 break; 2684 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2685 if ((value & 0xff) != 0) { 2686 err = USB_ERR_IOERROR; 2687 goto done; 2688 } 2689 len = sizeof(uhci_hubd_piix); 2690 ptr = (const void *)&uhci_hubd_piix; 2691 break; 2692 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2693 len = 16; 2694 memset(sc->sc_hub_desc.temp, 0, 16); 2695 break; 2696 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2697 if (index == 1) 2698 port = UHCI_PORTSC1; 2699 else if (index == 2) 2700 port = UHCI_PORTSC2; 2701 else { 2702 err = USB_ERR_IOERROR; 2703 goto done; 2704 } 2705 x = UREAD2(sc, port); 2706 status = change = 0; 2707 if (x & UHCI_PORTSC_CCS) 2708 status |= UPS_CURRENT_CONNECT_STATUS; 2709 if (x & UHCI_PORTSC_CSC) 2710 change |= UPS_C_CONNECT_STATUS; 2711 if (x & UHCI_PORTSC_PE) 2712 status |= UPS_PORT_ENABLED; 2713 if (x & UHCI_PORTSC_POEDC) 2714 change |= UPS_C_PORT_ENABLED; 2715 if (x & UHCI_PORTSC_OCI) 2716 status |= UPS_OVERCURRENT_INDICATOR; 2717 if (x & UHCI_PORTSC_OCIC) 2718 change |= UPS_C_OVERCURRENT_INDICATOR; 2719 if (x & UHCI_PORTSC_LSDA) 2720 status |= UPS_LOW_SPEED; 2721 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) { 2722 /* need to do a write back */ 2723 UWRITE2(sc, port, URWMASK(x)); 2724 2725 /* wait 20ms for resume sequence to complete */ 2726 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 2727 2728 /* clear suspend and resume detect */ 2729 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD | 2730 UHCI_PORTSC_SUSP)); 2731 2732 /* wait a little bit */ 2733 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500); 2734 2735 sc->sc_isresumed |= (1 << index); 2736 2737 } else if (x & UHCI_PORTSC_SUSP) { 2738 status |= UPS_SUSPEND; 2739 } 2740 status |= UPS_PORT_POWER; 2741 if (sc->sc_isresumed & (1 << index)) 2742 change |= UPS_C_SUSPEND; 2743 if (sc->sc_isreset) 2744 change |= UPS_C_PORT_RESET; 2745 USETW(sc->sc_hub_desc.ps.wPortStatus, status); 2746 USETW(sc->sc_hub_desc.ps.wPortChange, change); 2747 len = sizeof(sc->sc_hub_desc.ps); 2748 break; 2749 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2750 err = USB_ERR_IOERROR; 2751 goto done; 2752 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2753 break; 2754 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2755 if (index == 1) 2756 port = UHCI_PORTSC1; 2757 else if (index == 2) 2758 port = UHCI_PORTSC2; 2759 else { 2760 err = USB_ERR_IOERROR; 2761 goto done; 2762 } 2763 switch (value) { 2764 case UHF_PORT_ENABLE: 2765 x = URWMASK(UREAD2(sc, port)); 2766 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2767 break; 2768 case UHF_PORT_SUSPEND: 2769 x = URWMASK(UREAD2(sc, port)); 2770 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2771 break; 2772 case UHF_PORT_RESET: 2773 err = uhci_portreset(sc, index); 2774 goto done; 2775 case UHF_PORT_POWER: 2776 /* pretend we turned on power */ 2777 err = USB_ERR_NORMAL_COMPLETION; 2778 goto done; 2779 case UHF_C_PORT_CONNECTION: 2780 case UHF_C_PORT_ENABLE: 2781 case UHF_C_PORT_OVER_CURRENT: 2782 case UHF_PORT_CONNECTION: 2783 case UHF_PORT_OVER_CURRENT: 2784 case UHF_PORT_LOW_SPEED: 2785 case UHF_C_PORT_SUSPEND: 2786 case UHF_C_PORT_RESET: 2787 default: 2788 err = USB_ERR_IOERROR; 2789 goto done; 2790 } 2791 break; 2792 default: 2793 err = USB_ERR_IOERROR; 2794 goto done; 2795 } 2796 done: 2797 *plength = len; 2798 *pptr = ptr; 2799 return (err); 2800 } 2801 2802 /* 2803 * This routine is executed periodically and simulates interrupts from 2804 * the root controller interrupt pipe for port status change: 2805 */ 2806 static void 2807 uhci_root_intr(uhci_softc_t *sc) 2808 { 2809 DPRINTFN(21, "\n"); 2810 2811 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2812 2813 sc->sc_hub_idata[0] = 0; 2814 2815 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | 2816 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2817 sc->sc_hub_idata[0] |= 1 << 1; 2818 } 2819 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | 2820 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2821 sc->sc_hub_idata[0] |= 1 << 2; 2822 } 2823 2824 /* restart timer */ 2825 usb_callout_reset(&sc->sc_root_intr, hz, 2826 (void *)&uhci_root_intr, sc); 2827 2828 if (sc->sc_hub_idata[0] != 0) { 2829 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2830 sizeof(sc->sc_hub_idata)); 2831 } 2832 } 2833 2834 static void 2835 uhci_xfer_setup(struct usb_setup_params *parm) 2836 { 2837 struct usb_page_search page_info; 2838 struct usb_page_cache *pc; 2839 uhci_softc_t *sc; 2840 struct usb_xfer *xfer; 2841 void *last_obj; 2842 uint32_t ntd; 2843 uint32_t nqh; 2844 uint32_t nfixup; 2845 uint32_t n; 2846 uint16_t align; 2847 2848 sc = UHCI_BUS2SC(parm->udev->bus); 2849 xfer = parm->curr_xfer; 2850 2851 parm->hc_max_packet_size = 0x500; 2852 parm->hc_max_packet_count = 1; 2853 parm->hc_max_frame_size = 0x500; 2854 2855 /* 2856 * compute ntd and nqh 2857 */ 2858 if (parm->methods == &uhci_device_ctrl_methods) { 2859 xfer->flags_int.bdma_enable = 1; 2860 xfer->flags_int.bdma_no_post_sync = 1; 2861 2862 usbd_transfer_setup_sub(parm); 2863 2864 /* see EHCI HC driver for proof of "ntd" formula */ 2865 2866 nqh = 1; 2867 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2868 + (xfer->max_data_length / xfer->max_frame_size)); 2869 2870 } else if (parm->methods == &uhci_device_bulk_methods) { 2871 xfer->flags_int.bdma_enable = 1; 2872 xfer->flags_int.bdma_no_post_sync = 1; 2873 2874 usbd_transfer_setup_sub(parm); 2875 2876 nqh = 1; 2877 ntd = ((2 * xfer->nframes) 2878 + (xfer->max_data_length / xfer->max_frame_size)); 2879 2880 } else if (parm->methods == &uhci_device_intr_methods) { 2881 xfer->flags_int.bdma_enable = 1; 2882 xfer->flags_int.bdma_no_post_sync = 1; 2883 2884 usbd_transfer_setup_sub(parm); 2885 2886 nqh = 1; 2887 ntd = ((2 * xfer->nframes) 2888 + (xfer->max_data_length / xfer->max_frame_size)); 2889 2890 } else if (parm->methods == &uhci_device_isoc_methods) { 2891 xfer->flags_int.bdma_enable = 1; 2892 xfer->flags_int.bdma_no_post_sync = 1; 2893 2894 usbd_transfer_setup_sub(parm); 2895 2896 nqh = 0; 2897 ntd = xfer->nframes; 2898 2899 } else { 2900 2901 usbd_transfer_setup_sub(parm); 2902 2903 nqh = 0; 2904 ntd = 0; 2905 } 2906 2907 if (parm->err) { 2908 return; 2909 } 2910 /* 2911 * NOTE: the UHCI controller requires that 2912 * every packet must be contiguous on 2913 * the same USB memory page ! 2914 */ 2915 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1; 2916 2917 /* 2918 * Compute a suitable power of two alignment 2919 * for our "max_frame_size" fixup buffer(s): 2920 */ 2921 align = xfer->max_frame_size; 2922 n = 0; 2923 while (align) { 2924 align >>= 1; 2925 n++; 2926 } 2927 2928 /* check for power of two */ 2929 if (!(xfer->max_frame_size & 2930 (xfer->max_frame_size - 1))) { 2931 n--; 2932 } 2933 /* 2934 * We don't allow alignments of 2935 * less than 8 bytes: 2936 * 2937 * NOTE: Allocating using an aligment 2938 * of 1 byte has special meaning! 2939 */ 2940 if (n < 3) { 2941 n = 3; 2942 } 2943 align = (1 << n); 2944 2945 if (usbd_transfer_setup_sub_malloc( 2946 parm, &pc, xfer->max_frame_size, 2947 align, nfixup)) { 2948 parm->err = USB_ERR_NOMEM; 2949 return; 2950 } 2951 xfer->buf_fixup = pc; 2952 2953 alloc_dma_set: 2954 2955 if (parm->err) { 2956 return; 2957 } 2958 last_obj = NULL; 2959 2960 if (usbd_transfer_setup_sub_malloc( 2961 parm, &pc, sizeof(uhci_td_t), 2962 UHCI_TD_ALIGN, ntd)) { 2963 parm->err = USB_ERR_NOMEM; 2964 return; 2965 } 2966 if (parm->buf) { 2967 for (n = 0; n != ntd; n++) { 2968 uhci_td_t *td; 2969 2970 usbd_get_page(pc + n, 0, &page_info); 2971 2972 td = page_info.buffer; 2973 2974 /* init TD */ 2975 if ((parm->methods == &uhci_device_bulk_methods) || 2976 (parm->methods == &uhci_device_ctrl_methods) || 2977 (parm->methods == &uhci_device_intr_methods)) { 2978 /* set depth first bit */ 2979 td->td_self = htole32(page_info.physaddr | 2980 UHCI_PTR_TD | UHCI_PTR_VF); 2981 } else { 2982 td->td_self = htole32(page_info.physaddr | 2983 UHCI_PTR_TD); 2984 } 2985 2986 td->obj_next = last_obj; 2987 td->page_cache = pc + n; 2988 2989 last_obj = td; 2990 2991 usb_pc_cpu_flush(pc + n); 2992 } 2993 } 2994 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2995 2996 last_obj = NULL; 2997 2998 if (usbd_transfer_setup_sub_malloc( 2999 parm, &pc, sizeof(uhci_qh_t), 3000 UHCI_QH_ALIGN, nqh)) { 3001 parm->err = USB_ERR_NOMEM; 3002 return; 3003 } 3004 if (parm->buf) { 3005 for (n = 0; n != nqh; n++) { 3006 uhci_qh_t *qh; 3007 3008 usbd_get_page(pc + n, 0, &page_info); 3009 3010 qh = page_info.buffer; 3011 3012 /* init QH */ 3013 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH); 3014 qh->obj_next = last_obj; 3015 qh->page_cache = pc + n; 3016 3017 last_obj = qh; 3018 3019 usb_pc_cpu_flush(pc + n); 3020 } 3021 } 3022 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3023 3024 if (!xfer->flags_int.curr_dma_set) { 3025 xfer->flags_int.curr_dma_set = 1; 3026 goto alloc_dma_set; 3027 } 3028 } 3029 3030 static void 3031 uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3032 struct usb_endpoint *ep) 3033 { 3034 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 3035 3036 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3037 ep, udev->address, 3038 edesc->bEndpointAddress, udev->flags.usb_mode, 3039 sc->sc_addr); 3040 3041 if (udev->device_index != sc->sc_addr) { 3042 switch (edesc->bmAttributes & UE_XFERTYPE) { 3043 case UE_CONTROL: 3044 ep->methods = &uhci_device_ctrl_methods; 3045 break; 3046 case UE_INTERRUPT: 3047 ep->methods = &uhci_device_intr_methods; 3048 break; 3049 case UE_ISOCHRONOUS: 3050 if (udev->speed == USB_SPEED_FULL) { 3051 ep->methods = &uhci_device_isoc_methods; 3052 } 3053 break; 3054 case UE_BULK: 3055 ep->methods = &uhci_device_bulk_methods; 3056 break; 3057 default: 3058 /* do nothing */ 3059 break; 3060 } 3061 } 3062 } 3063 3064 static void 3065 uhci_xfer_unsetup(struct usb_xfer *xfer) 3066 { 3067 return; 3068 } 3069 3070 static void 3071 uhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3072 { 3073 /* 3074 * Wait until hardware has finished any possible use of the 3075 * transfer descriptor(s) and QH 3076 */ 3077 *pus = (1125); /* microseconds */ 3078 } 3079 3080 static void 3081 uhci_device_resume(struct usb_device *udev) 3082 { 3083 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3084 struct usb_xfer *xfer; 3085 const struct usb_pipe_methods *methods; 3086 uhci_qh_t *qh; 3087 3088 DPRINTF("\n"); 3089 3090 USB_BUS_LOCK(udev->bus); 3091 3092 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3093 3094 if (xfer->xroot->udev == udev) { 3095 3096 methods = xfer->endpoint->methods; 3097 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3098 3099 if (methods == &uhci_device_bulk_methods) { 3100 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 3101 uhci_add_loop(sc); 3102 xfer->flags_int.bandwidth_reclaimed = 1; 3103 } 3104 if (methods == &uhci_device_ctrl_methods) { 3105 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3106 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 3107 } else { 3108 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 3109 } 3110 } 3111 if (methods == &uhci_device_intr_methods) { 3112 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3113 } 3114 } 3115 } 3116 3117 USB_BUS_UNLOCK(udev->bus); 3118 3119 return; 3120 } 3121 3122 static void 3123 uhci_device_suspend(struct usb_device *udev) 3124 { 3125 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3126 struct usb_xfer *xfer; 3127 const struct usb_pipe_methods *methods; 3128 uhci_qh_t *qh; 3129 3130 DPRINTF("\n"); 3131 3132 USB_BUS_LOCK(udev->bus); 3133 3134 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3135 3136 if (xfer->xroot->udev == udev) { 3137 3138 methods = xfer->endpoint->methods; 3139 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3140 3141 if (xfer->flags_int.bandwidth_reclaimed) { 3142 xfer->flags_int.bandwidth_reclaimed = 0; 3143 uhci_rem_loop(sc); 3144 } 3145 if (methods == &uhci_device_bulk_methods) { 3146 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 3147 } 3148 if (methods == &uhci_device_ctrl_methods) { 3149 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3150 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 3151 } else { 3152 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 3153 } 3154 } 3155 if (methods == &uhci_device_intr_methods) { 3156 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3157 } 3158 } 3159 } 3160 3161 USB_BUS_UNLOCK(udev->bus); 3162 3163 return; 3164 } 3165 3166 static void 3167 uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3168 { 3169 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3170 3171 switch (state) { 3172 case USB_HW_POWER_SUSPEND: 3173 case USB_HW_POWER_SHUTDOWN: 3174 uhci_suspend(sc); 3175 break; 3176 case USB_HW_POWER_RESUME: 3177 uhci_resume(sc); 3178 break; 3179 default: 3180 break; 3181 } 3182 } 3183 3184 static void 3185 uhci_set_hw_power(struct usb_bus *bus) 3186 { 3187 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3188 uint32_t flags; 3189 3190 DPRINTF("\n"); 3191 3192 USB_BUS_LOCK(bus); 3193 3194 flags = bus->hw_power_state; 3195 3196 /* 3197 * WARNING: Some FULL speed USB devices require periodic SOF 3198 * messages! If any USB devices are connected through the 3199 * UHCI, power save will be disabled! 3200 */ 3201 if (flags & (USB_HW_POWER_CONTROL | 3202 USB_HW_POWER_NON_ROOT_HUB | 3203 USB_HW_POWER_BULK | 3204 USB_HW_POWER_INTERRUPT | 3205 USB_HW_POWER_ISOC)) { 3206 DPRINTF("Some USB transfer is " 3207 "active on unit %u.\n", 3208 device_get_unit(sc->sc_bus.bdev)); 3209 uhci_restart(sc); 3210 } else { 3211 DPRINTF("Power save on unit %u.\n", 3212 device_get_unit(sc->sc_bus.bdev)); 3213 UHCICMD(sc, UHCI_CMD_MAXP); 3214 } 3215 3216 USB_BUS_UNLOCK(bus); 3217 3218 return; 3219 } 3220 3221 3222 static const struct usb_bus_methods uhci_bus_methods = 3223 { 3224 .endpoint_init = uhci_ep_init, 3225 .xfer_setup = uhci_xfer_setup, 3226 .xfer_unsetup = uhci_xfer_unsetup, 3227 .get_dma_delay = uhci_get_dma_delay, 3228 .device_resume = uhci_device_resume, 3229 .device_suspend = uhci_device_suspend, 3230 .set_hw_power = uhci_set_hw_power, 3231 .set_hw_power_sleep = uhci_set_hw_power_sleep, 3232 .roothub_exec = uhci_roothub_exec, 3233 .xfer_poll = uhci_do_poll, 3234 }; 3235