1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 6 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * USB Universal Host Controller driver. 32 * Handles e.g. PIIX3 and PIIX4. 33 * 34 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 35 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 36 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 37 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 38 */ 39 40 #ifdef USB_GLOBAL_INCLUDE_FILE 41 #include USB_GLOBAL_INCLUDE_FILE 42 #else 43 #include <sys/stdint.h> 44 #include <sys/stddef.h> 45 #include <sys/param.h> 46 #include <sys/queue.h> 47 #include <sys/types.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/bus.h> 51 #include <sys/module.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/condvar.h> 55 #include <sys/sysctl.h> 56 #include <sys/sx.h> 57 #include <sys/unistd.h> 58 #include <sys/callout.h> 59 #include <sys/malloc.h> 60 #include <sys/priv.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 65 #define USB_DEBUG_VAR uhcidebug 66 67 #include <dev/usb/usb_core.h> 68 #include <dev/usb/usb_debug.h> 69 #include <dev/usb/usb_busdma.h> 70 #include <dev/usb/usb_process.h> 71 #include <dev/usb/usb_transfer.h> 72 #include <dev/usb/usb_device.h> 73 #include <dev/usb/usb_hub.h> 74 #include <dev/usb/usb_util.h> 75 76 #include <dev/usb/usb_controller.h> 77 #include <dev/usb/usb_bus.h> 78 #endif /* USB_GLOBAL_INCLUDE_FILE */ 79 80 #include <dev/usb/controller/uhci.h> 81 #include <dev/usb/controller/uhcireg.h> 82 83 #define alt_next next 84 #define UHCI_BUS2SC(bus) \ 85 __containerof(bus, uhci_softc_t, sc_bus) 86 87 #ifdef USB_DEBUG 88 static int uhcidebug = 0; 89 static int uhcinoloop = 0; 90 91 static SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 92 "USB uhci"); 93 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RWTUN, 94 &uhcidebug, 0, "uhci debug level"); 95 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RWTUN, 96 &uhcinoloop, 0, "uhci noloop"); 97 98 static void uhci_dumpregs(uhci_softc_t *sc); 99 static void uhci_dump_tds(uhci_td_t *td); 100 101 #endif 102 103 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 104 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 105 #define UWRITE1(sc, r, x) \ 106 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 107 } while (/*CONSTCOND*/0) 108 #define UWRITE2(sc, r, x) \ 109 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 110 } while (/*CONSTCOND*/0) 111 #define UWRITE4(sc, r, x) \ 112 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 113 } while (/*CONSTCOND*/0) 114 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 115 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 116 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 117 118 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 119 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 120 121 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 122 123 #define UHCI_INTR_ENDPT 1 124 125 struct uhci_mem_layout { 126 struct usb_page_search buf_res; 127 struct usb_page_search fix_res; 128 129 struct usb_page_cache *buf_pc; 130 struct usb_page_cache *fix_pc; 131 132 uint32_t buf_offset; 133 134 uint16_t max_frame_size; 135 }; 136 137 struct uhci_std_temp { 138 struct uhci_mem_layout ml; 139 uhci_td_t *td; 140 uhci_td_t *td_next; 141 uint32_t average; 142 uint32_t td_status; 143 uint32_t td_token; 144 uint32_t len; 145 uint16_t max_frame_size; 146 uint8_t shortpkt; 147 uint8_t setup_alt_next; 148 uint8_t last_frame; 149 }; 150 151 static const struct usb_bus_methods uhci_bus_methods; 152 static const struct usb_pipe_methods uhci_device_bulk_methods; 153 static const struct usb_pipe_methods uhci_device_ctrl_methods; 154 static const struct usb_pipe_methods uhci_device_intr_methods; 155 static const struct usb_pipe_methods uhci_device_isoc_methods; 156 157 static uint8_t uhci_restart(uhci_softc_t *sc); 158 static void uhci_do_poll(struct usb_bus *); 159 static void uhci_device_done(struct usb_xfer *, usb_error_t); 160 static void uhci_transfer_intr_enqueue(struct usb_xfer *); 161 static void uhci_timeout(void *); 162 static uint8_t uhci_check_transfer(struct usb_xfer *); 163 static void uhci_root_intr(uhci_softc_t *sc); 164 165 void 166 uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 167 { 168 struct uhci_softc *sc = UHCI_BUS2SC(bus); 169 uint32_t i; 170 171 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 172 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN); 173 174 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg, 175 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 176 177 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg, 178 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 179 180 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 181 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 182 183 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg, 184 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 185 186 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg, 187 sizeof(uhci_td_t), UHCI_TD_ALIGN); 188 189 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) { 190 cb(bus, sc->sc_hw.isoc_start_pc + i, 191 sc->sc_hw.isoc_start_pg + i, 192 sizeof(uhci_td_t), UHCI_TD_ALIGN); 193 } 194 195 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) { 196 cb(bus, sc->sc_hw.intr_start_pc + i, 197 sc->sc_hw.intr_start_pg + i, 198 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 199 } 200 } 201 202 static void 203 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer) 204 { 205 ml->buf_pc = xfer->frbuffers + 0; 206 ml->fix_pc = xfer->buf_fixup; 207 208 ml->buf_offset = 0; 209 210 ml->max_frame_size = xfer->max_frame_size; 211 } 212 213 static void 214 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td) 215 { 216 usbd_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res); 217 218 if (ml->buf_res.length < td->len) { 219 /* need to do a fixup */ 220 221 usbd_get_page(ml->fix_pc, 0, &ml->fix_res); 222 223 td->td_buffer = htole32(ml->fix_res.physaddr); 224 225 /* 226 * The UHCI driver cannot handle 227 * page crossings, so a fixup is 228 * needed: 229 * 230 * +----+----+ - - - 231 * | YYY|Y | 232 * +----+----+ - - - 233 * \ \ 234 * \ \ 235 * +----+ 236 * |YYYY| (fixup) 237 * +----+ 238 */ 239 240 if ((td->td_token & htole32(UHCI_TD_PID)) == 241 htole32(UHCI_TD_PID_IN)) { 242 td->fix_pc = ml->fix_pc; 243 usb_pc_cpu_invalidate(ml->fix_pc); 244 245 } else { 246 td->fix_pc = NULL; 247 248 /* copy data to fixup location */ 249 250 usbd_copy_out(ml->buf_pc, ml->buf_offset, 251 ml->fix_res.buffer, td->len); 252 253 usb_pc_cpu_flush(ml->fix_pc); 254 } 255 256 /* prepare next fixup */ 257 258 ml->fix_pc++; 259 260 } else { 261 td->td_buffer = htole32(ml->buf_res.physaddr); 262 td->fix_pc = NULL; 263 } 264 265 /* prepare next data location */ 266 267 ml->buf_offset += td->len; 268 } 269 270 /* 271 * Return values: 272 * 0: Success 273 * Else: Failure 274 */ 275 static uint8_t 276 uhci_restart(uhci_softc_t *sc) 277 { 278 struct usb_page_search buf_res; 279 280 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 281 282 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) { 283 DPRINTFN(2, "Already started\n"); 284 return (0); 285 } 286 287 DPRINTFN(2, "Restarting\n"); 288 289 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 290 291 /* Reload fresh base address */ 292 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr); 293 294 /* 295 * Assume 64 byte packets at frame end and start HC controller: 296 */ 297 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 298 299 /* wait 10 milliseconds */ 300 301 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 302 303 /* check that controller has started */ 304 305 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 306 DPRINTFN(2, "Failed\n"); 307 return (1); 308 } 309 return (0); 310 } 311 312 void 313 uhci_reset(uhci_softc_t *sc) 314 { 315 uint16_t n; 316 317 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 318 319 DPRINTF("resetting the HC\n"); 320 321 /* disable interrupts */ 322 323 UWRITE2(sc, UHCI_INTR, 0); 324 325 /* global reset */ 326 327 UHCICMD(sc, UHCI_CMD_GRESET); 328 329 /* wait */ 330 331 usb_pause_mtx(&sc->sc_bus.bus_mtx, 332 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 333 334 /* terminate all transfers */ 335 336 UHCICMD(sc, UHCI_CMD_HCRESET); 337 338 /* the reset bit goes low when the controller is done */ 339 340 n = UHCI_RESET_TIMEOUT; 341 while (n--) { 342 /* wait one millisecond */ 343 344 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 345 346 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) { 347 goto done_1; 348 } 349 } 350 351 device_printf(sc->sc_bus.bdev, 352 "controller did not reset\n"); 353 354 done_1: 355 356 n = 10; 357 while (n--) { 358 /* wait one millisecond */ 359 360 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 361 362 /* check if HC is stopped */ 363 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 364 goto done_2; 365 } 366 } 367 368 device_printf(sc->sc_bus.bdev, 369 "controller did not stop\n"); 370 371 done_2: 372 373 /* reset frame number */ 374 UWRITE2(sc, UHCI_FRNUM, 0); 375 /* set default SOF value */ 376 UWRITE1(sc, UHCI_SOF, 0x40); 377 378 USB_BUS_UNLOCK(&sc->sc_bus); 379 380 /* stop root interrupt */ 381 usb_callout_drain(&sc->sc_root_intr); 382 383 USB_BUS_LOCK(&sc->sc_bus); 384 } 385 386 static void 387 uhci_start(uhci_softc_t *sc) 388 { 389 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 390 391 DPRINTFN(2, "enabling\n"); 392 393 /* enable interrupts */ 394 395 UWRITE2(sc, UHCI_INTR, 396 (UHCI_INTR_TOCRCIE | 397 UHCI_INTR_RIE | 398 UHCI_INTR_IOCE | 399 UHCI_INTR_SPIE)); 400 401 if (uhci_restart(sc)) { 402 device_printf(sc->sc_bus.bdev, 403 "cannot start HC controller\n"); 404 } 405 406 /* start root interrupt */ 407 uhci_root_intr(sc); 408 } 409 410 static struct uhci_qh * 411 uhci_init_qh(struct usb_page_cache *pc) 412 { 413 struct usb_page_search buf_res; 414 struct uhci_qh *qh; 415 416 usbd_get_page(pc, 0, &buf_res); 417 418 qh = buf_res.buffer; 419 420 qh->qh_self = 421 htole32(buf_res.physaddr) | 422 htole32(UHCI_PTR_QH); 423 424 qh->page_cache = pc; 425 426 return (qh); 427 } 428 429 static struct uhci_td * 430 uhci_init_td(struct usb_page_cache *pc) 431 { 432 struct usb_page_search buf_res; 433 struct uhci_td *td; 434 435 usbd_get_page(pc, 0, &buf_res); 436 437 td = buf_res.buffer; 438 439 td->td_self = 440 htole32(buf_res.physaddr) | 441 htole32(UHCI_PTR_TD); 442 443 td->page_cache = pc; 444 445 return (td); 446 } 447 448 usb_error_t 449 uhci_init(uhci_softc_t *sc) 450 { 451 uint16_t bit; 452 uint16_t x; 453 uint16_t y; 454 455 DPRINTF("start\n"); 456 457 usb_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_mtx, 0); 458 459 #ifdef USB_DEBUG 460 if (uhcidebug > 2) { 461 uhci_dumpregs(sc); 462 } 463 #endif 464 /* 465 * Setup QH's 466 */ 467 sc->sc_ls_ctl_p_last = 468 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc); 469 470 sc->sc_fs_ctl_p_last = 471 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc); 472 473 sc->sc_bulk_p_last = 474 uhci_init_qh(&sc->sc_hw.bulk_start_pc); 475 #if 0 476 sc->sc_reclaim_qh_p = 477 sc->sc_fs_ctl_p_last; 478 #else 479 /* setup reclaim looping point */ 480 sc->sc_reclaim_qh_p = 481 sc->sc_bulk_p_last; 482 #endif 483 484 sc->sc_last_qh_p = 485 uhci_init_qh(&sc->sc_hw.last_qh_pc); 486 487 sc->sc_last_td_p = 488 uhci_init_td(&sc->sc_hw.last_td_pc); 489 490 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 491 sc->sc_isoc_p_last[x] = 492 uhci_init_td(sc->sc_hw.isoc_start_pc + x); 493 } 494 495 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) { 496 sc->sc_intr_p_last[x] = 497 uhci_init_qh(sc->sc_hw.intr_start_pc + x); 498 } 499 500 /* 501 * the QHs are arranged to give poll intervals that are 502 * powers of 2 times 1ms 503 */ 504 bit = UHCI_IFRAMELIST_COUNT / 2; 505 while (bit) { 506 x = bit; 507 while (x & bit) { 508 uhci_qh_t *qh_x; 509 uhci_qh_t *qh_y; 510 511 y = (x ^ bit) | (bit / 2); 512 513 /* 514 * the next QH has half the poll interval 515 */ 516 qh_x = sc->sc_intr_p_last[x]; 517 qh_y = sc->sc_intr_p_last[y]; 518 519 qh_x->h_next = NULL; 520 qh_x->qh_h_next = qh_y->qh_self; 521 qh_x->e_next = NULL; 522 qh_x->qh_e_next = htole32(UHCI_PTR_T); 523 x++; 524 } 525 bit >>= 1; 526 } 527 528 if (1) { 529 uhci_qh_t *qh_ls; 530 uhci_qh_t *qh_intr; 531 532 qh_ls = sc->sc_ls_ctl_p_last; 533 qh_intr = sc->sc_intr_p_last[0]; 534 535 /* start QH for interrupt traffic */ 536 qh_intr->h_next = qh_ls; 537 qh_intr->qh_h_next = qh_ls->qh_self; 538 qh_intr->e_next = 0; 539 qh_intr->qh_e_next = htole32(UHCI_PTR_T); 540 } 541 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 542 uhci_td_t *td_x; 543 uhci_qh_t *qh_intr; 544 545 td_x = sc->sc_isoc_p_last[x]; 546 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)]; 547 548 /* start TD for isochronous traffic */ 549 td_x->next = NULL; 550 td_x->td_next = qh_intr->qh_self; 551 td_x->td_status = htole32(UHCI_TD_IOS); 552 td_x->td_token = htole32(0); 553 td_x->td_buffer = htole32(0); 554 } 555 556 if (1) { 557 uhci_qh_t *qh_ls; 558 uhci_qh_t *qh_fs; 559 560 qh_ls = sc->sc_ls_ctl_p_last; 561 qh_fs = sc->sc_fs_ctl_p_last; 562 563 /* start QH where low speed control traffic will be queued */ 564 qh_ls->h_next = qh_fs; 565 qh_ls->qh_h_next = qh_fs->qh_self; 566 qh_ls->e_next = 0; 567 qh_ls->qh_e_next = htole32(UHCI_PTR_T); 568 } 569 if (1) { 570 uhci_qh_t *qh_ctl; 571 uhci_qh_t *qh_blk; 572 uhci_qh_t *qh_lst; 573 uhci_td_t *td_lst; 574 575 qh_ctl = sc->sc_fs_ctl_p_last; 576 qh_blk = sc->sc_bulk_p_last; 577 578 /* start QH where full speed control traffic will be queued */ 579 qh_ctl->h_next = qh_blk; 580 qh_ctl->qh_h_next = qh_blk->qh_self; 581 qh_ctl->e_next = 0; 582 qh_ctl->qh_e_next = htole32(UHCI_PTR_T); 583 584 qh_lst = sc->sc_last_qh_p; 585 586 /* start QH where bulk traffic will be queued */ 587 qh_blk->h_next = qh_lst; 588 qh_blk->qh_h_next = qh_lst->qh_self; 589 qh_blk->e_next = 0; 590 qh_blk->qh_e_next = htole32(UHCI_PTR_T); 591 592 td_lst = sc->sc_last_td_p; 593 594 /* end QH which is used for looping the QHs */ 595 qh_lst->h_next = 0; 596 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */ 597 qh_lst->e_next = td_lst; 598 qh_lst->qh_e_next = td_lst->td_self; 599 600 /* 601 * end TD which hangs from the last QH, to avoid a bug in the PIIX 602 * that makes it run berserk otherwise 603 */ 604 td_lst->next = 0; 605 td_lst->td_next = htole32(UHCI_PTR_T); 606 td_lst->td_status = htole32(0); /* inactive */ 607 td_lst->td_token = htole32(0); 608 td_lst->td_buffer = htole32(0); 609 } 610 if (1) { 611 struct usb_page_search buf_res; 612 uint32_t *pframes; 613 614 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 615 616 pframes = buf_res.buffer; 617 618 /* 619 * Setup UHCI framelist 620 * 621 * Execution order: 622 * 623 * pframes -> full speed isochronous -> interrupt QH's -> low 624 * speed control -> full speed control -> bulk transfers 625 * 626 */ 627 628 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) { 629 pframes[x] = 630 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self; 631 } 632 } 633 /* flush all cache into memory */ 634 635 usb_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc); 636 637 /* set up the bus struct */ 638 sc->sc_bus.methods = &uhci_bus_methods; 639 640 USB_BUS_LOCK(&sc->sc_bus); 641 /* reset the controller */ 642 uhci_reset(sc); 643 644 /* start the controller */ 645 uhci_start(sc); 646 USB_BUS_UNLOCK(&sc->sc_bus); 647 648 /* catch lost interrupts */ 649 uhci_do_poll(&sc->sc_bus); 650 651 return (0); 652 } 653 654 static void 655 uhci_suspend(uhci_softc_t *sc) 656 { 657 #ifdef USB_DEBUG 658 if (uhcidebug > 2) { 659 uhci_dumpregs(sc); 660 } 661 #endif 662 663 USB_BUS_LOCK(&sc->sc_bus); 664 665 /* stop the controller */ 666 667 uhci_reset(sc); 668 669 /* enter global suspend */ 670 671 UHCICMD(sc, UHCI_CMD_EGSM); 672 673 USB_BUS_UNLOCK(&sc->sc_bus); 674 } 675 676 static void 677 uhci_resume(uhci_softc_t *sc) 678 { 679 USB_BUS_LOCK(&sc->sc_bus); 680 681 /* reset the controller */ 682 683 uhci_reset(sc); 684 685 /* force global resume */ 686 687 UHCICMD(sc, UHCI_CMD_FGR); 688 689 /* and start traffic again */ 690 691 uhci_start(sc); 692 693 USB_BUS_UNLOCK(&sc->sc_bus); 694 695 #ifdef USB_DEBUG 696 if (uhcidebug > 2) 697 uhci_dumpregs(sc); 698 #endif 699 700 /* catch lost interrupts */ 701 uhci_do_poll(&sc->sc_bus); 702 } 703 704 #ifdef USB_DEBUG 705 static void 706 uhci_dumpregs(uhci_softc_t *sc) 707 { 708 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 709 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 710 device_get_nameunit(sc->sc_bus.bdev), 711 UREAD2(sc, UHCI_CMD), 712 UREAD2(sc, UHCI_STS), 713 UREAD2(sc, UHCI_INTR), 714 UREAD2(sc, UHCI_FRNUM), 715 UREAD4(sc, UHCI_FLBASEADDR), 716 UREAD1(sc, UHCI_SOF), 717 UREAD2(sc, UHCI_PORTSC1), 718 UREAD2(sc, UHCI_PORTSC2)); 719 } 720 721 static uint8_t 722 uhci_dump_td(uhci_td_t *p) 723 { 724 uint32_t td_next; 725 uint32_t td_status; 726 uint32_t td_token; 727 uint8_t temp; 728 729 usb_pc_cpu_invalidate(p->page_cache); 730 731 td_next = le32toh(p->td_next); 732 td_status = le32toh(p->td_status); 733 td_token = le32toh(p->td_token); 734 735 /* 736 * Check whether the link pointer in this TD marks the link pointer 737 * as end of queue: 738 */ 739 temp = ((td_next & UHCI_PTR_T) || (td_next == 0)); 740 741 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x " 742 "token=0x%08x buffer=0x%08x\n", 743 p, 744 le32toh(p->td_self), 745 td_next, 746 td_status, 747 td_token, 748 le32toh(p->td_buffer)); 749 750 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x," 751 "addr=%d,endpt=%d,D=%d,maxlen=%d\n", 752 p, 753 (td_next & 1) ? "-T" : "", 754 (td_next & 2) ? "-Q" : "", 755 (td_next & 4) ? "-VF" : "", 756 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "", 757 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "", 758 (td_status & UHCI_TD_NAK) ? "-NAK" : "", 759 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "", 760 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "", 761 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "", 762 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "", 763 (td_status & UHCI_TD_IOC) ? "-IOC" : "", 764 (td_status & UHCI_TD_IOS) ? "-IOS" : "", 765 (td_status & UHCI_TD_LS) ? "-LS" : "", 766 (td_status & UHCI_TD_SPD) ? "-SPD" : "", 767 UHCI_TD_GET_ERRCNT(td_status), 768 UHCI_TD_GET_ACTLEN(td_status), 769 UHCI_TD_GET_PID(td_token), 770 UHCI_TD_GET_DEVADDR(td_token), 771 UHCI_TD_GET_ENDPT(td_token), 772 UHCI_TD_GET_DT(td_token), 773 UHCI_TD_GET_MAXLEN(td_token)); 774 775 return (temp); 776 } 777 778 static uint8_t 779 uhci_dump_qh(uhci_qh_t *sqh) 780 { 781 uint8_t temp; 782 uint32_t qh_h_next; 783 uint32_t qh_e_next; 784 785 usb_pc_cpu_invalidate(sqh->page_cache); 786 787 qh_h_next = le32toh(sqh->qh_h_next); 788 qh_e_next = le32toh(sqh->qh_e_next); 789 790 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh, 791 le32toh(sqh->qh_self), qh_h_next, qh_e_next); 792 793 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) | 794 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0)); 795 796 return (temp); 797 } 798 799 static void 800 uhci_dump_all(uhci_softc_t *sc) 801 { 802 uhci_dumpregs(sc); 803 uhci_dump_qh(sc->sc_ls_ctl_p_last); 804 uhci_dump_qh(sc->sc_fs_ctl_p_last); 805 uhci_dump_qh(sc->sc_bulk_p_last); 806 uhci_dump_qh(sc->sc_last_qh_p); 807 } 808 809 static void 810 uhci_dump_tds(uhci_td_t *td) 811 { 812 for (; 813 td != NULL; 814 td = td->obj_next) { 815 if (uhci_dump_td(td)) { 816 break; 817 } 818 } 819 } 820 821 #endif 822 823 /* 824 * Let the last QH loop back to the full speed control transfer QH. 825 * This is what intel calls "bandwidth reclamation" and improves 826 * USB performance a lot for some devices. 827 * If we are already looping, just count it. 828 */ 829 static void 830 uhci_add_loop(uhci_softc_t *sc) 831 { 832 struct uhci_qh *qh_lst; 833 struct uhci_qh *qh_rec; 834 835 #ifdef USB_DEBUG 836 if (uhcinoloop) { 837 return; 838 } 839 #endif 840 if (++(sc->sc_loops) == 1) { 841 DPRINTFN(6, "add\n"); 842 843 qh_lst = sc->sc_last_qh_p; 844 qh_rec = sc->sc_reclaim_qh_p; 845 846 /* NOTE: we don't loop back the soft pointer */ 847 848 qh_lst->qh_h_next = qh_rec->qh_self; 849 usb_pc_cpu_flush(qh_lst->page_cache); 850 } 851 } 852 853 static void 854 uhci_rem_loop(uhci_softc_t *sc) 855 { 856 struct uhci_qh *qh_lst; 857 858 #ifdef USB_DEBUG 859 if (uhcinoloop) { 860 return; 861 } 862 #endif 863 if (--(sc->sc_loops) == 0) { 864 DPRINTFN(6, "remove\n"); 865 866 qh_lst = sc->sc_last_qh_p; 867 qh_lst->qh_h_next = htole32(UHCI_PTR_T); 868 usb_pc_cpu_flush(qh_lst->page_cache); 869 } 870 } 871 872 static void 873 uhci_transfer_intr_enqueue(struct usb_xfer *xfer) 874 { 875 /* check for early completion */ 876 if (uhci_check_transfer(xfer)) { 877 return; 878 } 879 /* put transfer on interrupt queue */ 880 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 881 882 /* start timeout, if any */ 883 if (xfer->timeout != 0) { 884 usbd_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout); 885 } 886 } 887 888 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last) 889 static uhci_td_t * 890 _uhci_append_td(uhci_td_t *std, uhci_td_t *last) 891 { 892 DPRINTFN(11, "%p to %p\n", std, last); 893 894 /* (sc->sc_bus.mtx) must be locked */ 895 896 std->next = last->next; 897 std->td_next = last->td_next; 898 899 std->prev = last; 900 901 usb_pc_cpu_flush(std->page_cache); 902 903 /* 904 * the last->next->prev is never followed: std->next->prev = std; 905 */ 906 last->next = std; 907 last->td_next = std->td_self; 908 909 usb_pc_cpu_flush(last->page_cache); 910 911 return (std); 912 } 913 914 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last) 915 static uhci_qh_t * 916 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last) 917 { 918 DPRINTFN(11, "%p to %p\n", sqh, last); 919 920 if (sqh->h_prev != NULL) { 921 /* should not happen */ 922 DPRINTFN(0, "QH already linked!\n"); 923 return (last); 924 } 925 /* (sc->sc_bus.mtx) must be locked */ 926 927 sqh->h_next = last->h_next; 928 sqh->qh_h_next = last->qh_h_next; 929 930 sqh->h_prev = last; 931 932 usb_pc_cpu_flush(sqh->page_cache); 933 934 /* 935 * The "last->h_next->h_prev" is never followed: 936 * 937 * "sqh->h_next->h_prev" = sqh; 938 */ 939 940 last->h_next = sqh; 941 last->qh_h_next = sqh->qh_self; 942 943 usb_pc_cpu_flush(last->page_cache); 944 945 return (sqh); 946 } 947 948 /**/ 949 950 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last) 951 static uhci_td_t * 952 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last) 953 { 954 DPRINTFN(11, "%p from %p\n", std, last); 955 956 /* (sc->sc_bus.mtx) must be locked */ 957 958 std->prev->next = std->next; 959 std->prev->td_next = std->td_next; 960 961 usb_pc_cpu_flush(std->prev->page_cache); 962 963 if (std->next) { 964 std->next->prev = std->prev; 965 usb_pc_cpu_flush(std->next->page_cache); 966 } 967 return ((last == std) ? std->prev : last); 968 } 969 970 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last) 971 static uhci_qh_t * 972 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last) 973 { 974 DPRINTFN(11, "%p from %p\n", sqh, last); 975 976 /* (sc->sc_bus.mtx) must be locked */ 977 978 /* only remove if not removed from a queue */ 979 if (sqh->h_prev) { 980 sqh->h_prev->h_next = sqh->h_next; 981 sqh->h_prev->qh_h_next = sqh->qh_h_next; 982 983 usb_pc_cpu_flush(sqh->h_prev->page_cache); 984 985 if (sqh->h_next) { 986 sqh->h_next->h_prev = sqh->h_prev; 987 usb_pc_cpu_flush(sqh->h_next->page_cache); 988 } 989 last = ((last == sqh) ? sqh->h_prev : last); 990 991 sqh->h_prev = 0; 992 993 usb_pc_cpu_flush(sqh->page_cache); 994 } 995 return (last); 996 } 997 998 static void 999 uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer) 1000 { 1001 struct usb_page_search res; 1002 uint32_t nframes = xfer->nframes; 1003 uint32_t status; 1004 uint32_t offset = 0; 1005 uint32_t *plen = xfer->frlengths; 1006 uint16_t len = 0; 1007 uhci_td_t *td = xfer->td_transfer_first; 1008 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos]; 1009 1010 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1011 xfer, xfer->endpoint); 1012 1013 /* sync any DMA memory before doing fixups */ 1014 1015 usb_bdma_post_sync(xfer); 1016 1017 while (nframes--) { 1018 if (td == NULL) { 1019 panic("%s:%d: out of TD's\n", 1020 __FUNCTION__, __LINE__); 1021 } 1022 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 1023 pp_last = &sc->sc_isoc_p_last[0]; 1024 } 1025 #ifdef USB_DEBUG 1026 if (uhcidebug > 5) { 1027 DPRINTF("isoc TD\n"); 1028 uhci_dump_td(td); 1029 } 1030 #endif 1031 usb_pc_cpu_invalidate(td->page_cache); 1032 status = le32toh(td->td_status); 1033 1034 len = UHCI_TD_GET_ACTLEN(status); 1035 1036 if (len > *plen) { 1037 len = *plen; 1038 } 1039 if (td->fix_pc) { 1040 usbd_get_page(td->fix_pc, 0, &res); 1041 1042 /* copy data from fixup location to real location */ 1043 1044 usb_pc_cpu_invalidate(td->fix_pc); 1045 1046 usbd_copy_in(xfer->frbuffers, offset, 1047 res.buffer, len); 1048 } 1049 offset += *plen; 1050 1051 *plen = len; 1052 1053 /* remove TD from schedule */ 1054 UHCI_REMOVE_TD(td, *pp_last); 1055 1056 pp_last++; 1057 plen++; 1058 td = td->obj_next; 1059 } 1060 1061 xfer->aframes = xfer->nframes; 1062 } 1063 1064 static usb_error_t 1065 uhci_non_isoc_done_sub(struct usb_xfer *xfer) 1066 { 1067 struct usb_page_search res; 1068 uhci_td_t *td; 1069 uhci_td_t *td_alt_next; 1070 uint32_t status; 1071 uint32_t token; 1072 uint16_t len; 1073 1074 td = xfer->td_transfer_cache; 1075 td_alt_next = td->alt_next; 1076 1077 if (xfer->aframes != xfer->nframes) { 1078 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1079 } 1080 while (1) { 1081 usb_pc_cpu_invalidate(td->page_cache); 1082 status = le32toh(td->td_status); 1083 token = le32toh(td->td_token); 1084 1085 /* 1086 * Verify the status and add 1087 * up the actual length: 1088 */ 1089 1090 len = UHCI_TD_GET_ACTLEN(status); 1091 if (len > td->len) { 1092 /* should not happen */ 1093 DPRINTF("Invalid status length, " 1094 "0x%04x/0x%04x bytes\n", len, td->len); 1095 status |= UHCI_TD_STALLED; 1096 1097 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) { 1098 if (td->fix_pc) { 1099 usbd_get_page(td->fix_pc, 0, &res); 1100 1101 /* 1102 * copy data from fixup location to real 1103 * location 1104 */ 1105 1106 usb_pc_cpu_invalidate(td->fix_pc); 1107 1108 usbd_copy_in(xfer->frbuffers + xfer->aframes, 1109 xfer->frlengths[xfer->aframes], res.buffer, len); 1110 } 1111 /* update actual length */ 1112 1113 xfer->frlengths[xfer->aframes] += len; 1114 } 1115 /* Check for last transfer */ 1116 if (((void *)td) == xfer->td_transfer_last) { 1117 td = NULL; 1118 break; 1119 } 1120 if (status & UHCI_TD_STALLED) { 1121 /* the transfer is finished */ 1122 td = NULL; 1123 break; 1124 } 1125 /* Check for short transfer */ 1126 if (len != td->len) { 1127 if (xfer->flags_int.short_frames_ok) { 1128 /* follow alt next */ 1129 td = td->alt_next; 1130 } else { 1131 /* the transfer is finished */ 1132 td = NULL; 1133 } 1134 break; 1135 } 1136 td = td->obj_next; 1137 1138 if (td->alt_next != td_alt_next) { 1139 /* this USB frame is complete */ 1140 break; 1141 } 1142 } 1143 1144 /* update transfer cache */ 1145 1146 xfer->td_transfer_cache = td; 1147 1148 /* update data toggle */ 1149 1150 xfer->endpoint->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1; 1151 1152 #ifdef USB_DEBUG 1153 if (status & UHCI_TD_ERROR) { 1154 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x " 1155 "status=%s%s%s%s%s%s%s%s%s%s%s\n", 1156 xfer->address, xfer->endpointno, xfer->aframes, 1157 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "", 1158 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "", 1159 (status & UHCI_TD_NAK) ? "[NAK]" : "", 1160 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "", 1161 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "", 1162 (status & UHCI_TD_STALLED) ? "[STALLED]" : "", 1163 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1164 (status & UHCI_TD_IOC) ? "[IOC]" : "", 1165 (status & UHCI_TD_IOS) ? "[IOS]" : "", 1166 (status & UHCI_TD_LS) ? "[LS]" : "", 1167 (status & UHCI_TD_SPD) ? "[SPD]" : ""); 1168 } 1169 #endif 1170 if (status & UHCI_TD_STALLED) { 1171 /* try to separate I/O errors from STALL */ 1172 if (UHCI_TD_GET_ERRCNT(status) == 0) 1173 return (USB_ERR_IOERROR); 1174 return (USB_ERR_STALLED); 1175 } 1176 return (USB_ERR_NORMAL_COMPLETION); 1177 } 1178 1179 static void 1180 uhci_non_isoc_done(struct usb_xfer *xfer) 1181 { 1182 usb_error_t err = 0; 1183 1184 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1185 xfer, xfer->endpoint); 1186 1187 #ifdef USB_DEBUG 1188 if (uhcidebug > 10) { 1189 uhci_dump_tds(xfer->td_transfer_first); 1190 } 1191 #endif 1192 1193 /* sync any DMA memory before doing fixups */ 1194 1195 usb_bdma_post_sync(xfer); 1196 1197 /* reset scanner */ 1198 1199 xfer->td_transfer_cache = xfer->td_transfer_first; 1200 1201 if (xfer->flags_int.control_xfr) { 1202 if (xfer->flags_int.control_hdr) { 1203 err = uhci_non_isoc_done_sub(xfer); 1204 } 1205 xfer->aframes = 1; 1206 1207 if (xfer->td_transfer_cache == NULL) { 1208 goto done; 1209 } 1210 } 1211 while (xfer->aframes != xfer->nframes) { 1212 err = uhci_non_isoc_done_sub(xfer); 1213 xfer->aframes++; 1214 1215 if (xfer->td_transfer_cache == NULL) { 1216 goto done; 1217 } 1218 } 1219 1220 if (xfer->flags_int.control_xfr && 1221 !xfer->flags_int.control_act) { 1222 err = uhci_non_isoc_done_sub(xfer); 1223 } 1224 done: 1225 uhci_device_done(xfer, err); 1226 } 1227 1228 /*------------------------------------------------------------------------* 1229 * uhci_check_transfer_sub 1230 * 1231 * The main purpose of this function is to update the data-toggle 1232 * in case it is wrong. 1233 *------------------------------------------------------------------------*/ 1234 static void 1235 uhci_check_transfer_sub(struct usb_xfer *xfer) 1236 { 1237 uhci_qh_t *qh; 1238 uhci_td_t *td; 1239 uhci_td_t *td_alt_next; 1240 1241 uint32_t td_token; 1242 uint32_t td_self; 1243 1244 td = xfer->td_transfer_cache; 1245 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1246 1247 td_token = td->obj_next->td_token; 1248 td = td->alt_next; 1249 xfer->td_transfer_cache = td; 1250 td_self = td->td_self; 1251 td_alt_next = td->alt_next; 1252 1253 if (xfer->flags_int.control_xfr) 1254 goto skip; /* don't touch the DT value! */ 1255 1256 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1)))) 1257 goto skip; /* data toggle has correct value */ 1258 1259 /* 1260 * The data toggle is wrong and we need to toggle it ! 1261 */ 1262 while (1) { 1263 td->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1264 usb_pc_cpu_flush(td->page_cache); 1265 1266 if (td == xfer->td_transfer_last) { 1267 /* last transfer */ 1268 break; 1269 } 1270 td = td->obj_next; 1271 1272 if (td->alt_next != td_alt_next) { 1273 /* next frame */ 1274 break; 1275 } 1276 } 1277 skip: 1278 1279 /* update the QH */ 1280 qh->qh_e_next = td_self; 1281 usb_pc_cpu_flush(qh->page_cache); 1282 1283 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1284 } 1285 1286 /*------------------------------------------------------------------------* 1287 * uhci_check_transfer 1288 * 1289 * Return values: 1290 * 0: USB transfer is not finished 1291 * Else: USB transfer is finished 1292 *------------------------------------------------------------------------*/ 1293 static uint8_t 1294 uhci_check_transfer(struct usb_xfer *xfer) 1295 { 1296 uint32_t status; 1297 uhci_td_t *td; 1298 1299 DPRINTFN(16, "xfer=%p checking transfer\n", xfer); 1300 1301 if (xfer->endpoint->methods == &uhci_device_isoc_methods) { 1302 /* isochronous transfer */ 1303 1304 td = xfer->td_transfer_last; 1305 1306 usb_pc_cpu_invalidate(td->page_cache); 1307 status = le32toh(td->td_status); 1308 1309 /* check also if the first is complete */ 1310 1311 td = xfer->td_transfer_first; 1312 1313 usb_pc_cpu_invalidate(td->page_cache); 1314 status |= le32toh(td->td_status); 1315 1316 if (!(status & UHCI_TD_ACTIVE)) { 1317 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1318 goto transferred; 1319 } 1320 } else { 1321 /* non-isochronous transfer */ 1322 1323 /* 1324 * check whether there is an error somewhere 1325 * in the middle, or whether there was a short 1326 * packet (SPD and not ACTIVE) 1327 */ 1328 td = xfer->td_transfer_cache; 1329 1330 while (1) { 1331 usb_pc_cpu_invalidate(td->page_cache); 1332 status = le32toh(td->td_status); 1333 1334 /* 1335 * if there is an active TD the transfer isn't done 1336 */ 1337 if (status & UHCI_TD_ACTIVE) { 1338 /* update cache */ 1339 xfer->td_transfer_cache = td; 1340 goto done; 1341 } 1342 /* 1343 * last transfer descriptor makes the transfer done 1344 */ 1345 if (((void *)td) == xfer->td_transfer_last) { 1346 break; 1347 } 1348 /* 1349 * any kind of error makes the transfer done 1350 */ 1351 if (status & UHCI_TD_STALLED) { 1352 break; 1353 } 1354 /* 1355 * check if we reached the last packet 1356 * or if there is a short packet: 1357 */ 1358 if ((td->td_next == htole32(UHCI_PTR_T)) || 1359 (UHCI_TD_GET_ACTLEN(status) < td->len)) { 1360 if (xfer->flags_int.short_frames_ok) { 1361 /* follow alt next */ 1362 if (td->alt_next) { 1363 /* update cache */ 1364 xfer->td_transfer_cache = td; 1365 uhci_check_transfer_sub(xfer); 1366 goto done; 1367 } 1368 } 1369 /* transfer is done */ 1370 break; 1371 } 1372 td = td->obj_next; 1373 } 1374 uhci_non_isoc_done(xfer); 1375 goto transferred; 1376 } 1377 1378 done: 1379 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1380 return (0); 1381 1382 transferred: 1383 return (1); 1384 } 1385 1386 static void 1387 uhci_interrupt_poll(uhci_softc_t *sc) 1388 { 1389 struct usb_xfer *xfer; 1390 1391 repeat: 1392 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1393 /* 1394 * check if transfer is transferred 1395 */ 1396 if (uhci_check_transfer(xfer)) { 1397 /* queue has been modified */ 1398 goto repeat; 1399 } 1400 } 1401 } 1402 1403 /*------------------------------------------------------------------------* 1404 * uhci_interrupt - UHCI interrupt handler 1405 * 1406 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1407 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1408 * is present ! 1409 *------------------------------------------------------------------------*/ 1410 void 1411 uhci_interrupt(uhci_softc_t *sc) 1412 { 1413 uint32_t status; 1414 1415 USB_BUS_LOCK(&sc->sc_bus); 1416 1417 DPRINTFN(16, "real interrupt\n"); 1418 1419 #ifdef USB_DEBUG 1420 if (uhcidebug > 15) { 1421 uhci_dumpregs(sc); 1422 } 1423 #endif 1424 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1425 if (status == 0) { 1426 /* the interrupt was not for us */ 1427 goto done; 1428 } 1429 if (status & (UHCI_STS_RD | UHCI_STS_HSE | 1430 UHCI_STS_HCPE | UHCI_STS_HCH)) { 1431 if (status & UHCI_STS_RD) { 1432 #ifdef USB_DEBUG 1433 printf("%s: resume detect\n", 1434 __FUNCTION__); 1435 #endif 1436 } 1437 if (status & UHCI_STS_HSE) { 1438 printf("%s: host system error\n", 1439 __FUNCTION__); 1440 } 1441 if (status & UHCI_STS_HCPE) { 1442 printf("%s: host controller process error\n", 1443 __FUNCTION__); 1444 } 1445 if (status & UHCI_STS_HCH) { 1446 /* no acknowledge needed */ 1447 DPRINTF("%s: host controller halted\n", 1448 __FUNCTION__); 1449 #ifdef USB_DEBUG 1450 if (uhcidebug > 0) { 1451 uhci_dump_all(sc); 1452 } 1453 #endif 1454 } 1455 } 1456 /* get acknowledge bits */ 1457 status &= (UHCI_STS_USBINT | 1458 UHCI_STS_USBEI | 1459 UHCI_STS_RD | 1460 UHCI_STS_HSE | 1461 UHCI_STS_HCPE | 1462 UHCI_STS_HCH); 1463 1464 if (status == 0) { 1465 /* nothing to acknowledge */ 1466 goto done; 1467 } 1468 /* acknowledge interrupts */ 1469 UWRITE2(sc, UHCI_STS, status); 1470 1471 /* poll all the USB transfers */ 1472 uhci_interrupt_poll(sc); 1473 1474 done: 1475 USB_BUS_UNLOCK(&sc->sc_bus); 1476 } 1477 1478 /* 1479 * called when a request does not complete 1480 */ 1481 static void 1482 uhci_timeout(void *arg) 1483 { 1484 struct usb_xfer *xfer = arg; 1485 1486 DPRINTF("xfer=%p\n", xfer); 1487 1488 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1489 1490 /* transfer is transferred */ 1491 uhci_device_done(xfer, USB_ERR_TIMEOUT); 1492 } 1493 1494 static void 1495 uhci_do_poll(struct usb_bus *bus) 1496 { 1497 struct uhci_softc *sc = UHCI_BUS2SC(bus); 1498 1499 USB_BUS_LOCK(&sc->sc_bus); 1500 uhci_interrupt_poll(sc); 1501 USB_BUS_UNLOCK(&sc->sc_bus); 1502 } 1503 1504 static void 1505 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp) 1506 { 1507 uhci_td_t *td; 1508 uhci_td_t *td_next; 1509 uhci_td_t *td_alt_next; 1510 uint32_t average; 1511 uint32_t len_old; 1512 uint8_t shortpkt_old; 1513 uint8_t precompute; 1514 1515 td_alt_next = NULL; 1516 shortpkt_old = temp->shortpkt; 1517 len_old = temp->len; 1518 precompute = 1; 1519 1520 /* software is used to detect short incoming transfers */ 1521 1522 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) { 1523 temp->td_status |= htole32(UHCI_TD_SPD); 1524 } else { 1525 temp->td_status &= ~htole32(UHCI_TD_SPD); 1526 } 1527 1528 temp->ml.buf_offset = 0; 1529 1530 restart: 1531 1532 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1533 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average)); 1534 1535 td = temp->td; 1536 td_next = temp->td_next; 1537 1538 while (1) { 1539 if (temp->len == 0) { 1540 if (temp->shortpkt) { 1541 break; 1542 } 1543 /* send a Zero Length Packet, ZLP, last */ 1544 1545 temp->shortpkt = 1; 1546 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0)); 1547 average = 0; 1548 1549 } else { 1550 average = temp->average; 1551 1552 if (temp->len < average) { 1553 temp->shortpkt = 1; 1554 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1555 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len)); 1556 average = temp->len; 1557 } 1558 } 1559 1560 if (td_next == NULL) { 1561 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__); 1562 } 1563 /* get next TD */ 1564 1565 td = td_next; 1566 td_next = td->obj_next; 1567 1568 /* check if we are pre-computing */ 1569 1570 if (precompute) { 1571 /* update remaining length */ 1572 1573 temp->len -= average; 1574 1575 continue; 1576 } 1577 /* fill out current TD */ 1578 1579 td->td_status = temp->td_status; 1580 td->td_token = temp->td_token; 1581 1582 /* update data toggle */ 1583 1584 temp->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1585 1586 if (average == 0) { 1587 td->len = 0; 1588 td->td_buffer = 0; 1589 td->fix_pc = NULL; 1590 1591 } else { 1592 /* update remaining length */ 1593 1594 temp->len -= average; 1595 1596 td->len = average; 1597 1598 /* fill out buffer pointer and do fixup, if any */ 1599 1600 uhci_mem_layout_fixup(&temp->ml, td); 1601 } 1602 1603 td->alt_next = td_alt_next; 1604 1605 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1606 /* we need to receive these frames one by one ! */ 1607 td->td_status |= htole32(UHCI_TD_IOC); 1608 td->td_next = htole32(UHCI_PTR_T); 1609 } else { 1610 if (td_next) { 1611 /* link the current TD with the next one */ 1612 td->td_next = td_next->td_self; 1613 } 1614 } 1615 1616 usb_pc_cpu_flush(td->page_cache); 1617 } 1618 1619 if (precompute) { 1620 precompute = 0; 1621 1622 /* setup alt next pointer, if any */ 1623 if (temp->last_frame) { 1624 td_alt_next = NULL; 1625 } else { 1626 /* we use this field internally */ 1627 td_alt_next = td_next; 1628 } 1629 1630 /* restore */ 1631 temp->shortpkt = shortpkt_old; 1632 temp->len = len_old; 1633 goto restart; 1634 } 1635 temp->td = td; 1636 temp->td_next = td_next; 1637 } 1638 1639 static uhci_td_t * 1640 uhci_setup_standard_chain(struct usb_xfer *xfer) 1641 { 1642 struct uhci_std_temp temp; 1643 uhci_td_t *td; 1644 uint32_t x; 1645 1646 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1647 xfer->address, UE_GET_ADDR(xfer->endpointno), 1648 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1649 1650 temp.average = xfer->max_frame_size; 1651 temp.max_frame_size = xfer->max_frame_size; 1652 1653 /* toggle the DMA set we are using */ 1654 xfer->flags_int.curr_dma_set ^= 1; 1655 1656 /* get next DMA set */ 1657 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1658 xfer->td_transfer_first = td; 1659 xfer->td_transfer_cache = td; 1660 1661 temp.td = NULL; 1662 temp.td_next = td; 1663 temp.last_frame = 0; 1664 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1665 1666 uhci_mem_layout_init(&temp.ml, xfer); 1667 1668 temp.td_status = 1669 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | 1670 UHCI_TD_ACTIVE)); 1671 1672 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1673 temp.td_status |= htole32(UHCI_TD_LS); 1674 } 1675 temp.td_token = 1676 htole32(UHCI_TD_SET_ENDPT(xfer->endpointno) | 1677 UHCI_TD_SET_DEVADDR(xfer->address)); 1678 1679 if (xfer->endpoint->toggle_next) { 1680 /* DATA1 is next */ 1681 temp.td_token |= htole32(UHCI_TD_SET_DT(1)); 1682 } 1683 /* check if we should prepend a setup message */ 1684 1685 if (xfer->flags_int.control_xfr) { 1686 if (xfer->flags_int.control_hdr) { 1687 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1688 UHCI_TD_SET_ENDPT(0xF)); 1689 temp.td_token |= htole32(UHCI_TD_PID_SETUP | 1690 UHCI_TD_SET_DT(0)); 1691 1692 temp.len = xfer->frlengths[0]; 1693 temp.ml.buf_pc = xfer->frbuffers + 0; 1694 temp.shortpkt = temp.len ? 1 : 0; 1695 /* check for last frame */ 1696 if (xfer->nframes == 1) { 1697 /* no STATUS stage yet, SETUP is last */ 1698 if (xfer->flags_int.control_act) { 1699 temp.last_frame = 1; 1700 temp.setup_alt_next = 0; 1701 } 1702 } 1703 uhci_setup_standard_chain_sub(&temp); 1704 } 1705 x = 1; 1706 } else { 1707 x = 0; 1708 } 1709 1710 while (x != xfer->nframes) { 1711 /* DATA0 / DATA1 message */ 1712 1713 temp.len = xfer->frlengths[x]; 1714 temp.ml.buf_pc = xfer->frbuffers + x; 1715 1716 x++; 1717 1718 if (x == xfer->nframes) { 1719 if (xfer->flags_int.control_xfr) { 1720 /* no STATUS stage yet, DATA is last */ 1721 if (xfer->flags_int.control_act) { 1722 temp.last_frame = 1; 1723 temp.setup_alt_next = 0; 1724 } 1725 } else { 1726 temp.last_frame = 1; 1727 temp.setup_alt_next = 0; 1728 } 1729 } 1730 /* 1731 * Keep previous data toggle, 1732 * device address and endpoint number: 1733 */ 1734 1735 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1736 UHCI_TD_SET_ENDPT(0xF) | 1737 UHCI_TD_SET_DT(1)); 1738 1739 if (temp.len == 0) { 1740 /* make sure that we send an USB packet */ 1741 1742 temp.shortpkt = 0; 1743 1744 } else { 1745 /* regular data transfer */ 1746 1747 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1748 } 1749 1750 /* set endpoint direction */ 1751 1752 temp.td_token |= 1753 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1754 htole32(UHCI_TD_PID_IN) : 1755 htole32(UHCI_TD_PID_OUT); 1756 1757 uhci_setup_standard_chain_sub(&temp); 1758 } 1759 1760 /* check if we should append a status stage */ 1761 1762 if (xfer->flags_int.control_xfr && 1763 !xfer->flags_int.control_act) { 1764 /* 1765 * send a DATA1 message and reverse the current endpoint 1766 * direction 1767 */ 1768 1769 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1770 UHCI_TD_SET_ENDPT(0xF) | 1771 UHCI_TD_SET_DT(1)); 1772 temp.td_token |= 1773 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1774 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) : 1775 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1)); 1776 1777 temp.len = 0; 1778 temp.ml.buf_pc = NULL; 1779 temp.shortpkt = 0; 1780 temp.last_frame = 1; 1781 temp.setup_alt_next = 0; 1782 1783 uhci_setup_standard_chain_sub(&temp); 1784 } 1785 td = temp.td; 1786 1787 /* Ensure that last TD is terminating: */ 1788 td->td_next = htole32(UHCI_PTR_T); 1789 1790 /* set interrupt bit */ 1791 1792 td->td_status |= htole32(UHCI_TD_IOC); 1793 1794 usb_pc_cpu_flush(td->page_cache); 1795 1796 /* must have at least one frame! */ 1797 1798 xfer->td_transfer_last = td; 1799 1800 #ifdef USB_DEBUG 1801 if (uhcidebug > 8) { 1802 DPRINTF("nexttog=%d; data before transfer:\n", 1803 xfer->endpoint->toggle_next); 1804 uhci_dump_tds(xfer->td_transfer_first); 1805 } 1806 #endif 1807 return (xfer->td_transfer_first); 1808 } 1809 1810 /* NOTE: "done" can be run two times in a row, 1811 * from close and from interrupt 1812 */ 1813 1814 static void 1815 uhci_device_done(struct usb_xfer *xfer, usb_error_t error) 1816 { 1817 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1818 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1819 uhci_qh_t *qh; 1820 1821 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1822 1823 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1824 xfer, xfer->endpoint, error); 1825 1826 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1827 if (qh) { 1828 usb_pc_cpu_invalidate(qh->page_cache); 1829 } 1830 if (xfer->flags_int.bandwidth_reclaimed) { 1831 xfer->flags_int.bandwidth_reclaimed = 0; 1832 uhci_rem_loop(sc); 1833 } 1834 if (methods == &uhci_device_bulk_methods) { 1835 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 1836 } 1837 if (methods == &uhci_device_ctrl_methods) { 1838 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1839 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 1840 } else { 1841 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 1842 } 1843 } 1844 if (methods == &uhci_device_intr_methods) { 1845 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 1846 } 1847 /* 1848 * Only finish isochronous transfers once 1849 * which will update "xfer->frlengths". 1850 */ 1851 if (xfer->td_transfer_first && 1852 xfer->td_transfer_last) { 1853 if (methods == &uhci_device_isoc_methods) { 1854 uhci_isoc_done(sc, xfer); 1855 } 1856 xfer->td_transfer_first = NULL; 1857 xfer->td_transfer_last = NULL; 1858 } 1859 /* dequeue transfer and start next transfer */ 1860 usbd_transfer_done(xfer, error); 1861 } 1862 1863 /*------------------------------------------------------------------------* 1864 * uhci bulk support 1865 *------------------------------------------------------------------------*/ 1866 static void 1867 uhci_device_bulk_open(struct usb_xfer *xfer) 1868 { 1869 return; 1870 } 1871 1872 static void 1873 uhci_device_bulk_close(struct usb_xfer *xfer) 1874 { 1875 uhci_device_done(xfer, USB_ERR_CANCELLED); 1876 } 1877 1878 static void 1879 uhci_device_bulk_enter(struct usb_xfer *xfer) 1880 { 1881 return; 1882 } 1883 1884 static void 1885 uhci_device_bulk_start(struct usb_xfer *xfer) 1886 { 1887 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1888 uhci_td_t *td; 1889 uhci_qh_t *qh; 1890 1891 /* setup TD's */ 1892 td = uhci_setup_standard_chain(xfer); 1893 1894 /* setup QH */ 1895 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1896 1897 qh->e_next = td; 1898 qh->qh_e_next = td->td_self; 1899 1900 if (xfer->xroot->udev->flags.self_suspended == 0) { 1901 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 1902 uhci_add_loop(sc); 1903 xfer->flags_int.bandwidth_reclaimed = 1; 1904 } else { 1905 usb_pc_cpu_flush(qh->page_cache); 1906 } 1907 1908 /* put transfer on interrupt queue */ 1909 uhci_transfer_intr_enqueue(xfer); 1910 } 1911 1912 static const struct usb_pipe_methods uhci_device_bulk_methods = 1913 { 1914 .open = uhci_device_bulk_open, 1915 .close = uhci_device_bulk_close, 1916 .enter = uhci_device_bulk_enter, 1917 .start = uhci_device_bulk_start, 1918 }; 1919 1920 /*------------------------------------------------------------------------* 1921 * uhci control support 1922 *------------------------------------------------------------------------*/ 1923 static void 1924 uhci_device_ctrl_open(struct usb_xfer *xfer) 1925 { 1926 return; 1927 } 1928 1929 static void 1930 uhci_device_ctrl_close(struct usb_xfer *xfer) 1931 { 1932 uhci_device_done(xfer, USB_ERR_CANCELLED); 1933 } 1934 1935 static void 1936 uhci_device_ctrl_enter(struct usb_xfer *xfer) 1937 { 1938 return; 1939 } 1940 1941 static void 1942 uhci_device_ctrl_start(struct usb_xfer *xfer) 1943 { 1944 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1945 uhci_qh_t *qh; 1946 uhci_td_t *td; 1947 1948 /* setup TD's */ 1949 td = uhci_setup_standard_chain(xfer); 1950 1951 /* setup QH */ 1952 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1953 1954 qh->e_next = td; 1955 qh->qh_e_next = td->td_self; 1956 1957 /* 1958 * NOTE: some devices choke on bandwidth- reclamation for control 1959 * transfers 1960 */ 1961 if (xfer->xroot->udev->flags.self_suspended == 0) { 1962 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1963 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 1964 } else { 1965 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 1966 } 1967 } else { 1968 usb_pc_cpu_flush(qh->page_cache); 1969 } 1970 /* put transfer on interrupt queue */ 1971 uhci_transfer_intr_enqueue(xfer); 1972 } 1973 1974 static const struct usb_pipe_methods uhci_device_ctrl_methods = 1975 { 1976 .open = uhci_device_ctrl_open, 1977 .close = uhci_device_ctrl_close, 1978 .enter = uhci_device_ctrl_enter, 1979 .start = uhci_device_ctrl_start, 1980 }; 1981 1982 /*------------------------------------------------------------------------* 1983 * uhci interrupt support 1984 *------------------------------------------------------------------------*/ 1985 static void 1986 uhci_device_intr_open(struct usb_xfer *xfer) 1987 { 1988 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1989 uint16_t best; 1990 uint16_t bit; 1991 uint16_t x; 1992 1993 best = 0; 1994 bit = UHCI_IFRAMELIST_COUNT / 2; 1995 while (bit) { 1996 if (xfer->interval >= bit) { 1997 x = bit; 1998 best = bit; 1999 while (x & bit) { 2000 if (sc->sc_intr_stat[x] < 2001 sc->sc_intr_stat[best]) { 2002 best = x; 2003 } 2004 x++; 2005 } 2006 break; 2007 } 2008 bit >>= 1; 2009 } 2010 2011 sc->sc_intr_stat[best]++; 2012 xfer->qh_pos = best; 2013 2014 DPRINTFN(3, "best=%d interval=%d\n", 2015 best, xfer->interval); 2016 } 2017 2018 static void 2019 uhci_device_intr_close(struct usb_xfer *xfer) 2020 { 2021 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2022 2023 sc->sc_intr_stat[xfer->qh_pos]--; 2024 2025 uhci_device_done(xfer, USB_ERR_CANCELLED); 2026 } 2027 2028 static void 2029 uhci_device_intr_enter(struct usb_xfer *xfer) 2030 { 2031 return; 2032 } 2033 2034 static void 2035 uhci_device_intr_start(struct usb_xfer *xfer) 2036 { 2037 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2038 uhci_qh_t *qh; 2039 uhci_td_t *td; 2040 2041 /* setup TD's */ 2042 td = uhci_setup_standard_chain(xfer); 2043 2044 /* setup QH */ 2045 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2046 2047 qh->e_next = td; 2048 qh->qh_e_next = td->td_self; 2049 2050 if (xfer->xroot->udev->flags.self_suspended == 0) { 2051 /* enter QHs into the controller data structures */ 2052 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 2053 } else { 2054 usb_pc_cpu_flush(qh->page_cache); 2055 } 2056 2057 /* put transfer on interrupt queue */ 2058 uhci_transfer_intr_enqueue(xfer); 2059 } 2060 2061 static const struct usb_pipe_methods uhci_device_intr_methods = 2062 { 2063 .open = uhci_device_intr_open, 2064 .close = uhci_device_intr_close, 2065 .enter = uhci_device_intr_enter, 2066 .start = uhci_device_intr_start, 2067 }; 2068 2069 /*------------------------------------------------------------------------* 2070 * uhci isochronous support 2071 *------------------------------------------------------------------------*/ 2072 static void 2073 uhci_device_isoc_open(struct usb_xfer *xfer) 2074 { 2075 uhci_td_t *td; 2076 uint32_t td_token; 2077 uint8_t ds; 2078 2079 td_token = 2080 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 2081 UHCI_TD_IN(0, xfer->endpointno, xfer->address, 0) : 2082 UHCI_TD_OUT(0, xfer->endpointno, xfer->address, 0); 2083 2084 td_token = htole32(td_token); 2085 2086 /* initialize all TD's */ 2087 2088 for (ds = 0; ds != 2; ds++) { 2089 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2090 /* mark TD as inactive */ 2091 td->td_status = htole32(UHCI_TD_IOS); 2092 td->td_token = td_token; 2093 2094 usb_pc_cpu_flush(td->page_cache); 2095 } 2096 } 2097 } 2098 2099 static void 2100 uhci_device_isoc_close(struct usb_xfer *xfer) 2101 { 2102 uhci_device_done(xfer, USB_ERR_CANCELLED); 2103 } 2104 2105 static void 2106 uhci_device_isoc_enter(struct usb_xfer *xfer) 2107 { 2108 struct uhci_mem_layout ml; 2109 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2110 uint32_t nframes; 2111 uint32_t startframe; 2112 uint32_t *plen; 2113 2114 #ifdef USB_DEBUG 2115 uint8_t once = 1; 2116 2117 #endif 2118 uhci_td_t *td; 2119 uhci_td_t *td_last = NULL; 2120 uhci_td_t **pp_last; 2121 2122 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2123 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2124 2125 nframes = UREAD2(sc, UHCI_FRNUM); 2126 2127 if (usbd_xfer_get_isochronous_start_frame( 2128 xfer, nframes, 0, 1, UHCI_VFRAMELIST_COUNT - 1, &startframe)) 2129 DPRINTFN(3, "start next=%d\n", startframe); 2130 2131 /* get the real number of frames */ 2132 2133 nframes = xfer->nframes; 2134 2135 uhci_mem_layout_init(&ml, xfer); 2136 2137 plen = xfer->frlengths; 2138 2139 /* toggle the DMA set we are using */ 2140 xfer->flags_int.curr_dma_set ^= 1; 2141 2142 /* get next DMA set */ 2143 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2144 xfer->td_transfer_first = td; 2145 2146 pp_last = &sc->sc_isoc_p_last[startframe]; 2147 2148 /* store starting position */ 2149 2150 xfer->qh_pos = startframe; 2151 2152 while (nframes--) { 2153 if (td == NULL) { 2154 panic("%s:%d: out of TD's\n", 2155 __FUNCTION__, __LINE__); 2156 } 2157 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 2158 pp_last = &sc->sc_isoc_p_last[0]; 2159 } 2160 if (*plen > xfer->max_frame_size) { 2161 #ifdef USB_DEBUG 2162 if (once) { 2163 once = 0; 2164 printf("%s: frame length(%d) exceeds %d " 2165 "bytes (frame truncated)\n", 2166 __FUNCTION__, *plen, 2167 xfer->max_frame_size); 2168 } 2169 #endif 2170 *plen = xfer->max_frame_size; 2171 } 2172 /* reuse td_token from last transfer */ 2173 2174 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2175 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen)); 2176 2177 td->len = *plen; 2178 2179 if (td->len == 0) { 2180 /* 2181 * Do not call "uhci_mem_layout_fixup()" when the 2182 * length is zero! 2183 */ 2184 td->td_buffer = 0; 2185 td->fix_pc = NULL; 2186 2187 } else { 2188 /* fill out buffer pointer and do fixup, if any */ 2189 2190 uhci_mem_layout_fixup(&ml, td); 2191 } 2192 2193 /* update status */ 2194 if (nframes == 0) { 2195 td->td_status = htole32 2196 (UHCI_TD_ZERO_ACTLEN 2197 (UHCI_TD_SET_ERRCNT(0) | 2198 UHCI_TD_ACTIVE | 2199 UHCI_TD_IOS | 2200 UHCI_TD_IOC)); 2201 } else { 2202 td->td_status = htole32 2203 (UHCI_TD_ZERO_ACTLEN 2204 (UHCI_TD_SET_ERRCNT(0) | 2205 UHCI_TD_ACTIVE | 2206 UHCI_TD_IOS)); 2207 } 2208 2209 usb_pc_cpu_flush(td->page_cache); 2210 2211 #ifdef USB_DEBUG 2212 if (uhcidebug > 5) { 2213 DPRINTF("TD %d\n", nframes); 2214 uhci_dump_td(td); 2215 } 2216 #endif 2217 /* insert TD into schedule */ 2218 UHCI_APPEND_TD(td, *pp_last); 2219 pp_last++; 2220 2221 plen++; 2222 td_last = td; 2223 td = td->obj_next; 2224 } 2225 2226 xfer->td_transfer_last = td_last; 2227 } 2228 2229 static void 2230 uhci_device_isoc_start(struct usb_xfer *xfer) 2231 { 2232 /* put transfer on interrupt queue */ 2233 uhci_transfer_intr_enqueue(xfer); 2234 } 2235 2236 static const struct usb_pipe_methods uhci_device_isoc_methods = 2237 { 2238 .open = uhci_device_isoc_open, 2239 .close = uhci_device_isoc_close, 2240 .enter = uhci_device_isoc_enter, 2241 .start = uhci_device_isoc_start, 2242 }; 2243 2244 /*------------------------------------------------------------------------* 2245 * uhci root control support 2246 *------------------------------------------------------------------------* 2247 * Simulate a hardware hub by handling all the necessary requests. 2248 *------------------------------------------------------------------------*/ 2249 2250 static const 2251 struct usb_device_descriptor uhci_devd = 2252 { 2253 sizeof(struct usb_device_descriptor), 2254 UDESC_DEVICE, /* type */ 2255 {0x00, 0x01}, /* USB version */ 2256 UDCLASS_HUB, /* class */ 2257 UDSUBCLASS_HUB, /* subclass */ 2258 UDPROTO_FSHUB, /* protocol */ 2259 64, /* max packet */ 2260 {0}, {0}, {0x00, 0x01}, /* device id */ 2261 1, 2, 0, /* string indexes */ 2262 1 /* # of configurations */ 2263 }; 2264 2265 static const struct uhci_config_desc uhci_confd = { 2266 .confd = { 2267 .bLength = sizeof(struct usb_config_descriptor), 2268 .bDescriptorType = UDESC_CONFIG, 2269 .wTotalLength[0] = sizeof(uhci_confd), 2270 .bNumInterface = 1, 2271 .bConfigurationValue = 1, 2272 .iConfiguration = 0, 2273 .bmAttributes = UC_SELF_POWERED, 2274 .bMaxPower = 0 /* max power */ 2275 }, 2276 .ifcd = { 2277 .bLength = sizeof(struct usb_interface_descriptor), 2278 .bDescriptorType = UDESC_INTERFACE, 2279 .bNumEndpoints = 1, 2280 .bInterfaceClass = UICLASS_HUB, 2281 .bInterfaceSubClass = UISUBCLASS_HUB, 2282 .bInterfaceProtocol = UIPROTO_FSHUB, 2283 }, 2284 .endpd = { 2285 .bLength = sizeof(struct usb_endpoint_descriptor), 2286 .bDescriptorType = UDESC_ENDPOINT, 2287 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 2288 .bmAttributes = UE_INTERRUPT, 2289 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2290 .bInterval = 255, 2291 }, 2292 }; 2293 2294 static const 2295 struct usb_hub_descriptor_min uhci_hubd_piix = 2296 { 2297 .bDescLength = sizeof(uhci_hubd_piix), 2298 .bDescriptorType = UDESC_HUB, 2299 .bNbrPorts = 2, 2300 .wHubCharacteristics = {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0}, 2301 .bPwrOn2PwrGood = 50, 2302 }; 2303 2304 /* 2305 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 2306 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 2307 * should not be used by the USB subsystem. As we cannot issue a 2308 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 2309 * will be enabled as part of the reset. 2310 * 2311 * On the VT83C572, the port cannot be successfully enabled until the 2312 * outstanding "port enable change" and "connection status change" 2313 * events have been reset. 2314 */ 2315 static usb_error_t 2316 uhci_portreset(uhci_softc_t *sc, uint16_t index) 2317 { 2318 uint16_t port; 2319 uint16_t x; 2320 uint8_t lim; 2321 2322 if (index == 1) 2323 port = UHCI_PORTSC1; 2324 else if (index == 2) 2325 port = UHCI_PORTSC2; 2326 else 2327 return (USB_ERR_IOERROR); 2328 2329 /* 2330 * Before we do anything, turn on SOF messages on the USB 2331 * BUS. Some USB devices do not cope without them! 2332 */ 2333 uhci_restart(sc); 2334 2335 x = URWMASK(UREAD2(sc, port)); 2336 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2337 2338 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2339 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 2340 2341 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n", 2342 index, UREAD2(sc, port)); 2343 2344 x = URWMASK(UREAD2(sc, port)); 2345 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2346 2347 mtx_unlock(&sc->sc_bus.bus_mtx); 2348 2349 /* 2350 * This delay needs to be exactly 100us, else some USB devices 2351 * fail to attach! 2352 */ 2353 DELAY(100); 2354 2355 mtx_lock(&sc->sc_bus.bus_mtx); 2356 2357 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n", 2358 index, UREAD2(sc, port)); 2359 2360 x = URWMASK(UREAD2(sc, port)); 2361 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2362 2363 for (lim = 0; lim < 12; lim++) { 2364 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2365 USB_MS_TO_TICKS(usb_port_reset_delay)); 2366 2367 x = UREAD2(sc, port); 2368 2369 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n", 2370 index, lim, x); 2371 2372 if (!(x & UHCI_PORTSC_CCS)) { 2373 /* 2374 * No device is connected (or was disconnected 2375 * during reset). Consider the port reset. 2376 * The delay must be long enough to ensure on 2377 * the initial iteration that the device 2378 * connection will have been registered. 50ms 2379 * appears to be sufficient, but 20ms is not. 2380 */ 2381 DPRINTFN(4, "uhci port %d loop %u, device detached\n", 2382 index, lim); 2383 goto done; 2384 } 2385 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 2386 /* 2387 * Port enabled changed and/or connection 2388 * status changed were set. Reset either or 2389 * both raised flags (by writing a 1 to that 2390 * bit), and wait again for state to settle. 2391 */ 2392 UWRITE2(sc, port, URWMASK(x) | 2393 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 2394 continue; 2395 } 2396 if (x & UHCI_PORTSC_PE) { 2397 /* port is enabled */ 2398 goto done; 2399 } 2400 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 2401 } 2402 2403 DPRINTFN(2, "uhci port %d reset timed out\n", index); 2404 return (USB_ERR_TIMEOUT); 2405 2406 done: 2407 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n", 2408 index, UREAD2(sc, port)); 2409 2410 sc->sc_isreset = 1; 2411 return (USB_ERR_NORMAL_COMPLETION); 2412 } 2413 2414 static usb_error_t 2415 uhci_roothub_exec(struct usb_device *udev, 2416 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2417 { 2418 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 2419 const void *ptr; 2420 const char *str_ptr; 2421 uint16_t x; 2422 uint16_t port; 2423 uint16_t value; 2424 uint16_t index; 2425 uint16_t status; 2426 uint16_t change; 2427 uint16_t len; 2428 usb_error_t err; 2429 2430 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2431 2432 /* buffer reset */ 2433 ptr = (const void *)&sc->sc_hub_desc.temp; 2434 len = 0; 2435 err = 0; 2436 2437 value = UGETW(req->wValue); 2438 index = UGETW(req->wIndex); 2439 2440 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2441 "wValue=0x%04x wIndex=0x%04x\n", 2442 req->bmRequestType, req->bRequest, 2443 UGETW(req->wLength), value, index); 2444 2445 #define C(x,y) ((x) | ((y) << 8)) 2446 switch (C(req->bRequest, req->bmRequestType)) { 2447 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2448 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2449 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2450 /* 2451 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2452 * for the integrated root hub. 2453 */ 2454 break; 2455 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2456 len = 1; 2457 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2458 break; 2459 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2460 switch (value >> 8) { 2461 case UDESC_DEVICE: 2462 if ((value & 0xff) != 0) { 2463 err = USB_ERR_IOERROR; 2464 goto done; 2465 } 2466 len = sizeof(uhci_devd); 2467 ptr = (const void *)&uhci_devd; 2468 break; 2469 2470 case UDESC_CONFIG: 2471 if ((value & 0xff) != 0) { 2472 err = USB_ERR_IOERROR; 2473 goto done; 2474 } 2475 len = sizeof(uhci_confd); 2476 ptr = (const void *)&uhci_confd; 2477 break; 2478 2479 case UDESC_STRING: 2480 switch (value & 0xff) { 2481 case 0: /* Language table */ 2482 str_ptr = "\001"; 2483 break; 2484 2485 case 1: /* Vendor */ 2486 str_ptr = sc->sc_vendor; 2487 break; 2488 2489 case 2: /* Product */ 2490 str_ptr = "UHCI root HUB"; 2491 break; 2492 2493 default: 2494 str_ptr = ""; 2495 break; 2496 } 2497 2498 len = usb_make_str_desc 2499 (sc->sc_hub_desc.temp, 2500 sizeof(sc->sc_hub_desc.temp), 2501 str_ptr); 2502 break; 2503 2504 default: 2505 err = USB_ERR_IOERROR; 2506 goto done; 2507 } 2508 break; 2509 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2510 len = 1; 2511 sc->sc_hub_desc.temp[0] = 0; 2512 break; 2513 case C(UR_GET_STATUS, UT_READ_DEVICE): 2514 len = 2; 2515 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2516 break; 2517 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2518 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2519 len = 2; 2520 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2521 break; 2522 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2523 if (value >= UHCI_MAX_DEVICES) { 2524 err = USB_ERR_IOERROR; 2525 goto done; 2526 } 2527 sc->sc_addr = value; 2528 break; 2529 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2530 if ((value != 0) && (value != 1)) { 2531 err = USB_ERR_IOERROR; 2532 goto done; 2533 } 2534 sc->sc_conf = value; 2535 break; 2536 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2537 break; 2538 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2539 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2540 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2541 err = USB_ERR_IOERROR; 2542 goto done; 2543 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2544 break; 2545 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2546 break; 2547 /* Hub requests */ 2548 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2549 break; 2550 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2551 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE " 2552 "port=%d feature=%d\n", 2553 index, value); 2554 if (index == 1) 2555 port = UHCI_PORTSC1; 2556 else if (index == 2) 2557 port = UHCI_PORTSC2; 2558 else { 2559 err = USB_ERR_IOERROR; 2560 goto done; 2561 } 2562 switch (value) { 2563 case UHF_PORT_ENABLE: 2564 x = URWMASK(UREAD2(sc, port)); 2565 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2566 break; 2567 case UHF_PORT_SUSPEND: 2568 x = URWMASK(UREAD2(sc, port)); 2569 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP)); 2570 break; 2571 case UHF_PORT_RESET: 2572 x = URWMASK(UREAD2(sc, port)); 2573 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2574 break; 2575 case UHF_C_PORT_CONNECTION: 2576 x = URWMASK(UREAD2(sc, port)); 2577 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2578 break; 2579 case UHF_C_PORT_ENABLE: 2580 x = URWMASK(UREAD2(sc, port)); 2581 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2582 break; 2583 case UHF_C_PORT_OVER_CURRENT: 2584 x = URWMASK(UREAD2(sc, port)); 2585 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2586 break; 2587 case UHF_C_PORT_RESET: 2588 sc->sc_isreset = 0; 2589 err = USB_ERR_NORMAL_COMPLETION; 2590 goto done; 2591 case UHF_C_PORT_SUSPEND: 2592 sc->sc_isresumed &= ~(1 << index); 2593 break; 2594 case UHF_PORT_CONNECTION: 2595 case UHF_PORT_OVER_CURRENT: 2596 case UHF_PORT_POWER: 2597 case UHF_PORT_LOW_SPEED: 2598 default: 2599 err = USB_ERR_IOERROR; 2600 goto done; 2601 } 2602 break; 2603 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2604 if (index == 1) 2605 port = UHCI_PORTSC1; 2606 else if (index == 2) 2607 port = UHCI_PORTSC2; 2608 else { 2609 err = USB_ERR_IOERROR; 2610 goto done; 2611 } 2612 len = 1; 2613 sc->sc_hub_desc.temp[0] = 2614 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2615 UHCI_PORTSC_LS_SHIFT); 2616 break; 2617 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2618 if ((value & 0xff) != 0) { 2619 err = USB_ERR_IOERROR; 2620 goto done; 2621 } 2622 len = sizeof(uhci_hubd_piix); 2623 ptr = (const void *)&uhci_hubd_piix; 2624 break; 2625 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2626 len = 16; 2627 memset(sc->sc_hub_desc.temp, 0, 16); 2628 break; 2629 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2630 if (index == 1) 2631 port = UHCI_PORTSC1; 2632 else if (index == 2) 2633 port = UHCI_PORTSC2; 2634 else { 2635 err = USB_ERR_IOERROR; 2636 goto done; 2637 } 2638 x = UREAD2(sc, port); 2639 status = change = 0; 2640 if (x & UHCI_PORTSC_CCS) 2641 status |= UPS_CURRENT_CONNECT_STATUS; 2642 if (x & UHCI_PORTSC_CSC) 2643 change |= UPS_C_CONNECT_STATUS; 2644 if (x & UHCI_PORTSC_PE) 2645 status |= UPS_PORT_ENABLED; 2646 if (x & UHCI_PORTSC_POEDC) 2647 change |= UPS_C_PORT_ENABLED; 2648 if (x & UHCI_PORTSC_OCI) 2649 status |= UPS_OVERCURRENT_INDICATOR; 2650 if (x & UHCI_PORTSC_OCIC) 2651 change |= UPS_C_OVERCURRENT_INDICATOR; 2652 if (x & UHCI_PORTSC_LSDA) 2653 status |= UPS_LOW_SPEED; 2654 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) { 2655 /* need to do a write back */ 2656 UWRITE2(sc, port, URWMASK(x)); 2657 2658 /* wait 20ms for resume sequence to complete */ 2659 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 2660 2661 /* clear suspend and resume detect */ 2662 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD | 2663 UHCI_PORTSC_SUSP)); 2664 2665 /* wait a little bit */ 2666 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500); 2667 2668 sc->sc_isresumed |= (1 << index); 2669 2670 } else if (x & UHCI_PORTSC_SUSP) { 2671 status |= UPS_SUSPEND; 2672 } 2673 status |= UPS_PORT_POWER; 2674 if (sc->sc_isresumed & (1 << index)) 2675 change |= UPS_C_SUSPEND; 2676 if (sc->sc_isreset) 2677 change |= UPS_C_PORT_RESET; 2678 USETW(sc->sc_hub_desc.ps.wPortStatus, status); 2679 USETW(sc->sc_hub_desc.ps.wPortChange, change); 2680 len = sizeof(sc->sc_hub_desc.ps); 2681 break; 2682 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2683 err = USB_ERR_IOERROR; 2684 goto done; 2685 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2686 break; 2687 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2688 if (index == 1) 2689 port = UHCI_PORTSC1; 2690 else if (index == 2) 2691 port = UHCI_PORTSC2; 2692 else { 2693 err = USB_ERR_IOERROR; 2694 goto done; 2695 } 2696 switch (value) { 2697 case UHF_PORT_ENABLE: 2698 x = URWMASK(UREAD2(sc, port)); 2699 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2700 break; 2701 case UHF_PORT_SUSPEND: 2702 x = URWMASK(UREAD2(sc, port)); 2703 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2704 break; 2705 case UHF_PORT_RESET: 2706 err = uhci_portreset(sc, index); 2707 goto done; 2708 case UHF_PORT_POWER: 2709 /* pretend we turned on power */ 2710 err = USB_ERR_NORMAL_COMPLETION; 2711 goto done; 2712 case UHF_C_PORT_CONNECTION: 2713 case UHF_C_PORT_ENABLE: 2714 case UHF_C_PORT_OVER_CURRENT: 2715 case UHF_PORT_CONNECTION: 2716 case UHF_PORT_OVER_CURRENT: 2717 case UHF_PORT_LOW_SPEED: 2718 case UHF_C_PORT_SUSPEND: 2719 case UHF_C_PORT_RESET: 2720 default: 2721 err = USB_ERR_IOERROR; 2722 goto done; 2723 } 2724 break; 2725 default: 2726 err = USB_ERR_IOERROR; 2727 goto done; 2728 } 2729 done: 2730 *plength = len; 2731 *pptr = ptr; 2732 return (err); 2733 } 2734 2735 /* 2736 * This routine is executed periodically and simulates interrupts from 2737 * the root controller interrupt pipe for port status change: 2738 */ 2739 static void 2740 uhci_root_intr(uhci_softc_t *sc) 2741 { 2742 DPRINTFN(21, "\n"); 2743 2744 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2745 2746 sc->sc_hub_idata[0] = 0; 2747 2748 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | 2749 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2750 sc->sc_hub_idata[0] |= 1 << 1; 2751 } 2752 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | 2753 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2754 sc->sc_hub_idata[0] |= 1 << 2; 2755 } 2756 2757 /* restart timer */ 2758 usb_callout_reset(&sc->sc_root_intr, hz, 2759 (void *)&uhci_root_intr, sc); 2760 2761 if (sc->sc_hub_idata[0] != 0) { 2762 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2763 sizeof(sc->sc_hub_idata)); 2764 } 2765 } 2766 2767 static void 2768 uhci_xfer_setup(struct usb_setup_params *parm) 2769 { 2770 struct usb_page_search page_info; 2771 struct usb_page_cache *pc; 2772 struct usb_xfer *xfer; 2773 void *last_obj; 2774 uint32_t ntd; 2775 uint32_t nqh; 2776 uint32_t nfixup; 2777 uint32_t n; 2778 uint16_t align; 2779 2780 xfer = parm->curr_xfer; 2781 2782 parm->hc_max_packet_size = 0x500; 2783 parm->hc_max_packet_count = 1; 2784 parm->hc_max_frame_size = 0x500; 2785 2786 /* 2787 * compute ntd and nqh 2788 */ 2789 if (parm->methods == &uhci_device_ctrl_methods) { 2790 xfer->flags_int.bdma_enable = 1; 2791 xfer->flags_int.bdma_no_post_sync = 1; 2792 2793 usbd_transfer_setup_sub(parm); 2794 2795 /* see EHCI HC driver for proof of "ntd" formula */ 2796 2797 nqh = 1; 2798 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2799 + (xfer->max_data_length / xfer->max_frame_size)); 2800 2801 } else if (parm->methods == &uhci_device_bulk_methods) { 2802 xfer->flags_int.bdma_enable = 1; 2803 xfer->flags_int.bdma_no_post_sync = 1; 2804 2805 usbd_transfer_setup_sub(parm); 2806 2807 nqh = 1; 2808 ntd = ((2 * xfer->nframes) 2809 + (xfer->max_data_length / xfer->max_frame_size)); 2810 2811 } else if (parm->methods == &uhci_device_intr_methods) { 2812 xfer->flags_int.bdma_enable = 1; 2813 xfer->flags_int.bdma_no_post_sync = 1; 2814 2815 usbd_transfer_setup_sub(parm); 2816 2817 nqh = 1; 2818 ntd = ((2 * xfer->nframes) 2819 + (xfer->max_data_length / xfer->max_frame_size)); 2820 2821 } else if (parm->methods == &uhci_device_isoc_methods) { 2822 xfer->flags_int.bdma_enable = 1; 2823 xfer->flags_int.bdma_no_post_sync = 1; 2824 2825 usbd_transfer_setup_sub(parm); 2826 2827 nqh = 0; 2828 ntd = xfer->nframes; 2829 2830 } else { 2831 usbd_transfer_setup_sub(parm); 2832 2833 nqh = 0; 2834 ntd = 0; 2835 } 2836 2837 if (parm->err) { 2838 return; 2839 } 2840 /* 2841 * NOTE: the UHCI controller requires that 2842 * every packet must be contiguous on 2843 * the same USB memory page ! 2844 */ 2845 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1; 2846 2847 /* 2848 * Compute a suitable power of two alignment 2849 * for our "max_frame_size" fixup buffer(s): 2850 */ 2851 align = xfer->max_frame_size; 2852 n = 0; 2853 while (align) { 2854 align >>= 1; 2855 n++; 2856 } 2857 2858 /* check for power of two */ 2859 if (!(xfer->max_frame_size & 2860 (xfer->max_frame_size - 1))) { 2861 n--; 2862 } 2863 /* 2864 * We don't allow alignments of 2865 * less than 8 bytes: 2866 * 2867 * NOTE: Allocating using an alignment 2868 * of 1 byte has special meaning! 2869 */ 2870 if (n < 3) { 2871 n = 3; 2872 } 2873 align = (1 << n); 2874 2875 if (usbd_transfer_setup_sub_malloc( 2876 parm, &pc, xfer->max_frame_size, 2877 align, nfixup)) { 2878 parm->err = USB_ERR_NOMEM; 2879 return; 2880 } 2881 xfer->buf_fixup = pc; 2882 2883 alloc_dma_set: 2884 2885 if (parm->err) { 2886 return; 2887 } 2888 last_obj = NULL; 2889 2890 if (usbd_transfer_setup_sub_malloc( 2891 parm, &pc, sizeof(uhci_td_t), 2892 UHCI_TD_ALIGN, ntd)) { 2893 parm->err = USB_ERR_NOMEM; 2894 return; 2895 } 2896 if (parm->buf) { 2897 for (n = 0; n != ntd; n++) { 2898 uhci_td_t *td; 2899 2900 usbd_get_page(pc + n, 0, &page_info); 2901 2902 td = page_info.buffer; 2903 2904 /* init TD */ 2905 if ((parm->methods == &uhci_device_bulk_methods) || 2906 (parm->methods == &uhci_device_ctrl_methods) || 2907 (parm->methods == &uhci_device_intr_methods)) { 2908 /* set depth first bit */ 2909 td->td_self = htole32(page_info.physaddr | 2910 UHCI_PTR_TD | UHCI_PTR_VF); 2911 } else { 2912 td->td_self = htole32(page_info.physaddr | 2913 UHCI_PTR_TD); 2914 } 2915 2916 td->obj_next = last_obj; 2917 td->page_cache = pc + n; 2918 2919 last_obj = td; 2920 2921 usb_pc_cpu_flush(pc + n); 2922 } 2923 } 2924 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2925 2926 last_obj = NULL; 2927 2928 if (usbd_transfer_setup_sub_malloc( 2929 parm, &pc, sizeof(uhci_qh_t), 2930 UHCI_QH_ALIGN, nqh)) { 2931 parm->err = USB_ERR_NOMEM; 2932 return; 2933 } 2934 if (parm->buf) { 2935 for (n = 0; n != nqh; n++) { 2936 uhci_qh_t *qh; 2937 2938 usbd_get_page(pc + n, 0, &page_info); 2939 2940 qh = page_info.buffer; 2941 2942 /* init QH */ 2943 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH); 2944 qh->obj_next = last_obj; 2945 qh->page_cache = pc + n; 2946 2947 last_obj = qh; 2948 2949 usb_pc_cpu_flush(pc + n); 2950 } 2951 } 2952 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2953 2954 if (!xfer->flags_int.curr_dma_set) { 2955 xfer->flags_int.curr_dma_set = 1; 2956 goto alloc_dma_set; 2957 } 2958 } 2959 2960 static void 2961 uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2962 struct usb_endpoint *ep) 2963 { 2964 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 2965 2966 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2967 ep, udev->address, 2968 edesc->bEndpointAddress, udev->flags.usb_mode, 2969 sc->sc_addr); 2970 2971 if (udev->device_index != sc->sc_addr) { 2972 switch (edesc->bmAttributes & UE_XFERTYPE) { 2973 case UE_CONTROL: 2974 ep->methods = &uhci_device_ctrl_methods; 2975 break; 2976 case UE_INTERRUPT: 2977 ep->methods = &uhci_device_intr_methods; 2978 break; 2979 case UE_ISOCHRONOUS: 2980 if (udev->speed == USB_SPEED_FULL) { 2981 ep->methods = &uhci_device_isoc_methods; 2982 } 2983 break; 2984 case UE_BULK: 2985 ep->methods = &uhci_device_bulk_methods; 2986 break; 2987 default: 2988 /* do nothing */ 2989 break; 2990 } 2991 } 2992 } 2993 2994 static void 2995 uhci_xfer_unsetup(struct usb_xfer *xfer) 2996 { 2997 return; 2998 } 2999 3000 static void 3001 uhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3002 { 3003 /* 3004 * Wait until hardware has finished any possible use of the 3005 * transfer descriptor(s) and QH 3006 */ 3007 *pus = (1125); /* microseconds */ 3008 } 3009 3010 static void 3011 uhci_device_resume(struct usb_device *udev) 3012 { 3013 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3014 struct usb_xfer *xfer; 3015 const struct usb_pipe_methods *methods; 3016 uhci_qh_t *qh; 3017 3018 DPRINTF("\n"); 3019 3020 USB_BUS_LOCK(udev->bus); 3021 3022 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3023 if (xfer->xroot->udev == udev) { 3024 methods = xfer->endpoint->methods; 3025 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3026 3027 if (methods == &uhci_device_bulk_methods) { 3028 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 3029 uhci_add_loop(sc); 3030 xfer->flags_int.bandwidth_reclaimed = 1; 3031 } 3032 if (methods == &uhci_device_ctrl_methods) { 3033 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3034 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 3035 } else { 3036 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 3037 } 3038 } 3039 if (methods == &uhci_device_intr_methods) { 3040 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3041 } 3042 } 3043 } 3044 3045 USB_BUS_UNLOCK(udev->bus); 3046 3047 return; 3048 } 3049 3050 static void 3051 uhci_device_suspend(struct usb_device *udev) 3052 { 3053 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3054 struct usb_xfer *xfer; 3055 const struct usb_pipe_methods *methods; 3056 uhci_qh_t *qh; 3057 3058 DPRINTF("\n"); 3059 3060 USB_BUS_LOCK(udev->bus); 3061 3062 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3063 if (xfer->xroot->udev == udev) { 3064 methods = xfer->endpoint->methods; 3065 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3066 3067 if (xfer->flags_int.bandwidth_reclaimed) { 3068 xfer->flags_int.bandwidth_reclaimed = 0; 3069 uhci_rem_loop(sc); 3070 } 3071 if (methods == &uhci_device_bulk_methods) { 3072 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 3073 } 3074 if (methods == &uhci_device_ctrl_methods) { 3075 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3076 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 3077 } else { 3078 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 3079 } 3080 } 3081 if (methods == &uhci_device_intr_methods) { 3082 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3083 } 3084 } 3085 } 3086 3087 USB_BUS_UNLOCK(udev->bus); 3088 3089 return; 3090 } 3091 3092 static void 3093 uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3094 { 3095 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3096 3097 switch (state) { 3098 case USB_HW_POWER_SUSPEND: 3099 case USB_HW_POWER_SHUTDOWN: 3100 uhci_suspend(sc); 3101 break; 3102 case USB_HW_POWER_RESUME: 3103 uhci_resume(sc); 3104 break; 3105 default: 3106 break; 3107 } 3108 } 3109 3110 static void 3111 uhci_set_hw_power(struct usb_bus *bus) 3112 { 3113 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3114 uint32_t flags; 3115 3116 DPRINTF("\n"); 3117 3118 USB_BUS_LOCK(bus); 3119 3120 flags = bus->hw_power_state; 3121 3122 /* 3123 * WARNING: Some FULL speed USB devices require periodic SOF 3124 * messages! If any USB devices are connected through the 3125 * UHCI, power save will be disabled! 3126 */ 3127 if (flags & (USB_HW_POWER_CONTROL | 3128 USB_HW_POWER_NON_ROOT_HUB | 3129 USB_HW_POWER_BULK | 3130 USB_HW_POWER_INTERRUPT | 3131 USB_HW_POWER_ISOC)) { 3132 DPRINTF("Some USB transfer is " 3133 "active on unit %u.\n", 3134 device_get_unit(sc->sc_bus.bdev)); 3135 uhci_restart(sc); 3136 } else { 3137 DPRINTF("Power save on unit %u.\n", 3138 device_get_unit(sc->sc_bus.bdev)); 3139 UHCICMD(sc, UHCI_CMD_MAXP); 3140 } 3141 3142 USB_BUS_UNLOCK(bus); 3143 3144 return; 3145 } 3146 3147 static const struct usb_bus_methods uhci_bus_methods = 3148 { 3149 .endpoint_init = uhci_ep_init, 3150 .xfer_setup = uhci_xfer_setup, 3151 .xfer_unsetup = uhci_xfer_unsetup, 3152 .get_dma_delay = uhci_get_dma_delay, 3153 .device_resume = uhci_device_resume, 3154 .device_suspend = uhci_device_suspend, 3155 .set_hw_power = uhci_set_hw_power, 3156 .set_hw_power_sleep = uhci_set_hw_power_sleep, 3157 .roothub_exec = uhci_roothub_exec, 3158 .xfer_poll = uhci_do_poll, 3159 }; 3160