1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * USB Universal Host Controller driver. 33 * Handles e.g. PIIX3 and PIIX4. 34 * 35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 38 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 39 */ 40 41 #include <dev/usb/usb.h> 42 #include <dev/usb/usb_mfunc.h> 43 #include <dev/usb/usb_error.h> 44 45 #define USB_DEBUG_VAR uhcidebug 46 47 #include <dev/usb/usb_core.h> 48 #include <dev/usb/usb_debug.h> 49 #include <dev/usb/usb_busdma.h> 50 #include <dev/usb/usb_process.h> 51 #include <dev/usb/usb_sw_transfer.h> 52 #include <dev/usb/usb_transfer.h> 53 #include <dev/usb/usb_device.h> 54 #include <dev/usb/usb_hub.h> 55 #include <dev/usb/usb_util.h> 56 57 #include <dev/usb/usb_controller.h> 58 #include <dev/usb/usb_bus.h> 59 #include <dev/usb/controller/uhci.h> 60 61 #define alt_next next 62 #define UHCI_BUS2SC(bus) \ 63 ((uhci_softc_t *)(((uint8_t *)(bus)) - \ 64 ((uint8_t *)&(((uhci_softc_t *)0)->sc_bus)))) 65 66 #if USB_DEBUG 67 static int uhcidebug = 0; 68 static int uhcinoloop = 0; 69 70 SYSCTL_NODE(_hw_usb2, OID_AUTO, uhci, CTLFLAG_RW, 0, "USB uhci"); 71 SYSCTL_INT(_hw_usb2_uhci, OID_AUTO, debug, CTLFLAG_RW, 72 &uhcidebug, 0, "uhci debug level"); 73 SYSCTL_INT(_hw_usb2_uhci, OID_AUTO, loop, CTLFLAG_RW, 74 &uhcinoloop, 0, "uhci noloop"); 75 static void uhci_dumpregs(uhci_softc_t *sc); 76 static void uhci_dump_tds(uhci_td_t *td); 77 78 #endif 79 80 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 81 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 82 #define UWRITE1(sc, r, x) \ 83 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 84 } while (/*CONSTCOND*/0) 85 #define UWRITE2(sc, r, x) \ 86 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 87 } while (/*CONSTCOND*/0) 88 #define UWRITE4(sc, r, x) \ 89 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 90 } while (/*CONSTCOND*/0) 91 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 92 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 93 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 94 95 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 96 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 97 98 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 99 100 #define UHCI_INTR_ENDPT 1 101 102 struct uhci_mem_layout { 103 104 struct usb2_page_search buf_res; 105 struct usb2_page_search fix_res; 106 107 struct usb2_page_cache *buf_pc; 108 struct usb2_page_cache *fix_pc; 109 110 uint32_t buf_offset; 111 112 uint16_t max_frame_size; 113 }; 114 115 struct uhci_std_temp { 116 117 struct uhci_mem_layout ml; 118 uhci_td_t *td; 119 uhci_td_t *td_next; 120 uint32_t average; 121 uint32_t td_status; 122 uint32_t td_token; 123 uint32_t len; 124 uint16_t max_frame_size; 125 uint8_t shortpkt; 126 uint8_t setup_alt_next; 127 uint8_t last_frame; 128 }; 129 130 extern struct usb2_bus_methods uhci_bus_methods; 131 extern struct usb2_pipe_methods uhci_device_bulk_methods; 132 extern struct usb2_pipe_methods uhci_device_ctrl_methods; 133 extern struct usb2_pipe_methods uhci_device_intr_methods; 134 extern struct usb2_pipe_methods uhci_device_isoc_methods; 135 extern struct usb2_pipe_methods uhci_root_ctrl_methods; 136 extern struct usb2_pipe_methods uhci_root_intr_methods; 137 138 static void uhci_root_ctrl_poll(struct uhci_softc *); 139 static void uhci_do_poll(struct usb2_bus *); 140 static void uhci_device_done(struct usb2_xfer *, usb2_error_t); 141 static void uhci_transfer_intr_enqueue(struct usb2_xfer *); 142 static void uhci_root_intr_check(void *); 143 static void uhci_timeout(void *); 144 static uint8_t uhci_check_transfer(struct usb2_xfer *); 145 146 void 147 uhci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 148 { 149 struct uhci_softc *sc = UHCI_BUS2SC(bus); 150 uint32_t i; 151 152 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 153 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN); 154 155 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg, 156 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 157 158 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg, 159 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 160 161 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 162 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 163 164 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg, 165 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 166 167 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg, 168 sizeof(uhci_td_t), UHCI_TD_ALIGN); 169 170 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) { 171 cb(bus, sc->sc_hw.isoc_start_pc + i, 172 sc->sc_hw.isoc_start_pg + i, 173 sizeof(uhci_td_t), UHCI_TD_ALIGN); 174 } 175 176 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) { 177 cb(bus, sc->sc_hw.intr_start_pc + i, 178 sc->sc_hw.intr_start_pg + i, 179 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 180 } 181 } 182 183 static void 184 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb2_xfer *xfer) 185 { 186 ml->buf_pc = xfer->frbuffers + 0; 187 ml->fix_pc = xfer->buf_fixup; 188 189 ml->buf_offset = 0; 190 191 ml->max_frame_size = xfer->max_frame_size; 192 } 193 194 static void 195 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td) 196 { 197 usb2_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res); 198 199 if (ml->buf_res.length < td->len) { 200 201 /* need to do a fixup */ 202 203 usb2_get_page(ml->fix_pc, 0, &ml->fix_res); 204 205 td->td_buffer = htole32(ml->fix_res.physaddr); 206 207 /* 208 * The UHCI driver cannot handle 209 * page crossings, so a fixup is 210 * needed: 211 * 212 * +----+----+ - - - 213 * | YYY|Y | 214 * +----+----+ - - - 215 * \ \ 216 * \ \ 217 * +----+ 218 * |YYYY| (fixup) 219 * +----+ 220 */ 221 222 if ((td->td_token & htole32(UHCI_TD_PID)) == 223 htole32(UHCI_TD_PID_IN)) { 224 td->fix_pc = ml->fix_pc; 225 usb2_pc_cpu_invalidate(ml->fix_pc); 226 227 } else { 228 td->fix_pc = NULL; 229 230 /* copy data to fixup location */ 231 232 usb2_copy_out(ml->buf_pc, ml->buf_offset, 233 ml->fix_res.buffer, td->len); 234 235 usb2_pc_cpu_flush(ml->fix_pc); 236 } 237 238 /* prepare next fixup */ 239 240 ml->fix_pc++; 241 242 } else { 243 244 td->td_buffer = htole32(ml->buf_res.physaddr); 245 td->fix_pc = NULL; 246 } 247 248 /* prepare next data location */ 249 250 ml->buf_offset += td->len; 251 } 252 253 void 254 uhci_reset(uhci_softc_t *sc) 255 { 256 struct usb2_page_search buf_res; 257 uint16_t n; 258 259 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 260 261 DPRINTF("resetting the HC\n"); 262 263 /* disable interrupts */ 264 265 UWRITE2(sc, UHCI_INTR, 0); 266 267 /* global reset */ 268 269 UHCICMD(sc, UHCI_CMD_GRESET); 270 271 /* wait */ 272 273 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 274 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 275 276 /* terminate all transfers */ 277 278 UHCICMD(sc, UHCI_CMD_HCRESET); 279 280 /* the reset bit goes low when the controller is done */ 281 282 n = UHCI_RESET_TIMEOUT; 283 while (n--) { 284 /* wait one millisecond */ 285 286 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 287 288 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) { 289 goto done_1; 290 } 291 } 292 293 device_printf(sc->sc_bus.bdev, 294 "controller did not reset\n"); 295 296 done_1: 297 298 n = 10; 299 while (n--) { 300 /* wait one millisecond */ 301 302 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 303 304 /* check if HC is stopped */ 305 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 306 goto done_2; 307 } 308 } 309 310 device_printf(sc->sc_bus.bdev, 311 "controller did not stop\n"); 312 313 done_2: 314 315 /* reload the configuration */ 316 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 317 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr); 318 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 319 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 320 } 321 322 static void 323 uhci_start(uhci_softc_t *sc) 324 { 325 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 326 327 DPRINTFN(2, "enabling\n"); 328 329 /* enable interrupts */ 330 331 UWRITE2(sc, UHCI_INTR, 332 (UHCI_INTR_TOCRCIE | 333 UHCI_INTR_RIE | 334 UHCI_INTR_IOCE | 335 UHCI_INTR_SPIE)); 336 337 /* 338 * assume 64 byte packets at frame end and start HC controller 339 */ 340 341 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 342 343 uint8_t n = 10; 344 345 while (n--) { 346 /* wait one millisecond */ 347 348 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 349 350 /* check that controller has started */ 351 352 if (!(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH)) { 353 goto done; 354 } 355 } 356 357 device_printf(sc->sc_bus.bdev, 358 "cannot start HC controller\n"); 359 360 done: 361 return; 362 } 363 364 static struct uhci_qh * 365 uhci_init_qh(struct usb2_page_cache *pc) 366 { 367 struct usb2_page_search buf_res; 368 struct uhci_qh *qh; 369 370 usb2_get_page(pc, 0, &buf_res); 371 372 qh = buf_res.buffer; 373 374 qh->qh_self = 375 htole32(buf_res.physaddr) | 376 htole32(UHCI_PTR_QH); 377 378 qh->page_cache = pc; 379 380 return (qh); 381 } 382 383 static struct uhci_td * 384 uhci_init_td(struct usb2_page_cache *pc) 385 { 386 struct usb2_page_search buf_res; 387 struct uhci_td *td; 388 389 usb2_get_page(pc, 0, &buf_res); 390 391 td = buf_res.buffer; 392 393 td->td_self = 394 htole32(buf_res.physaddr) | 395 htole32(UHCI_PTR_TD); 396 397 td->page_cache = pc; 398 399 return (td); 400 } 401 402 usb2_error_t 403 uhci_init(uhci_softc_t *sc) 404 { 405 uint16_t bit; 406 uint16_t x; 407 uint16_t y; 408 409 DPRINTF("start\n"); 410 411 #if USB_DEBUG 412 if (uhcidebug > 2) { 413 uhci_dumpregs(sc); 414 } 415 #endif 416 417 sc->sc_saved_sof = 0x40; /* default value */ 418 sc->sc_saved_frnum = 0; /* default frame number */ 419 420 /* 421 * Setup QH's 422 */ 423 sc->sc_ls_ctl_p_last = 424 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc); 425 426 sc->sc_fs_ctl_p_last = 427 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc); 428 429 sc->sc_bulk_p_last = 430 uhci_init_qh(&sc->sc_hw.bulk_start_pc); 431 #if 0 432 sc->sc_reclaim_qh_p = 433 sc->sc_fs_ctl_p_last; 434 #else 435 /* setup reclaim looping point */ 436 sc->sc_reclaim_qh_p = 437 sc->sc_bulk_p_last; 438 #endif 439 440 sc->sc_last_qh_p = 441 uhci_init_qh(&sc->sc_hw.last_qh_pc); 442 443 sc->sc_last_td_p = 444 uhci_init_td(&sc->sc_hw.last_td_pc); 445 446 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 447 sc->sc_isoc_p_last[x] = 448 uhci_init_td(sc->sc_hw.isoc_start_pc + x); 449 } 450 451 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) { 452 sc->sc_intr_p_last[x] = 453 uhci_init_qh(sc->sc_hw.intr_start_pc + x); 454 } 455 456 /* 457 * the QHs are arranged to give poll intervals that are 458 * powers of 2 times 1ms 459 */ 460 bit = UHCI_IFRAMELIST_COUNT / 2; 461 while (bit) { 462 x = bit; 463 while (x & bit) { 464 uhci_qh_t *qh_x; 465 uhci_qh_t *qh_y; 466 467 y = (x ^ bit) | (bit / 2); 468 469 /* 470 * the next QH has half the poll interval 471 */ 472 qh_x = sc->sc_intr_p_last[x]; 473 qh_y = sc->sc_intr_p_last[y]; 474 475 qh_x->h_next = NULL; 476 qh_x->qh_h_next = qh_y->qh_self; 477 qh_x->e_next = NULL; 478 qh_x->qh_e_next = htole32(UHCI_PTR_T); 479 x++; 480 } 481 bit >>= 1; 482 } 483 484 if (1) { 485 uhci_qh_t *qh_ls; 486 uhci_qh_t *qh_intr; 487 488 qh_ls = sc->sc_ls_ctl_p_last; 489 qh_intr = sc->sc_intr_p_last[0]; 490 491 /* start QH for interrupt traffic */ 492 qh_intr->h_next = qh_ls; 493 qh_intr->qh_h_next = qh_ls->qh_self; 494 qh_intr->e_next = 0; 495 qh_intr->qh_e_next = htole32(UHCI_PTR_T); 496 } 497 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 498 499 uhci_td_t *td_x; 500 uhci_qh_t *qh_intr; 501 502 td_x = sc->sc_isoc_p_last[x]; 503 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)]; 504 505 /* start TD for isochronous traffic */ 506 td_x->next = NULL; 507 td_x->td_next = qh_intr->qh_self; 508 td_x->td_status = htole32(UHCI_TD_IOS); 509 td_x->td_token = htole32(0); 510 td_x->td_buffer = htole32(0); 511 } 512 513 if (1) { 514 uhci_qh_t *qh_ls; 515 uhci_qh_t *qh_fs; 516 517 qh_ls = sc->sc_ls_ctl_p_last; 518 qh_fs = sc->sc_fs_ctl_p_last; 519 520 /* start QH where low speed control traffic will be queued */ 521 qh_ls->h_next = qh_fs; 522 qh_ls->qh_h_next = qh_fs->qh_self; 523 qh_ls->e_next = 0; 524 qh_ls->qh_e_next = htole32(UHCI_PTR_T); 525 } 526 if (1) { 527 uhci_qh_t *qh_ctl; 528 uhci_qh_t *qh_blk; 529 uhci_qh_t *qh_lst; 530 uhci_td_t *td_lst; 531 532 qh_ctl = sc->sc_fs_ctl_p_last; 533 qh_blk = sc->sc_bulk_p_last; 534 535 /* start QH where full speed control traffic will be queued */ 536 qh_ctl->h_next = qh_blk; 537 qh_ctl->qh_h_next = qh_blk->qh_self; 538 qh_ctl->e_next = 0; 539 qh_ctl->qh_e_next = htole32(UHCI_PTR_T); 540 541 qh_lst = sc->sc_last_qh_p; 542 543 /* start QH where bulk traffic will be queued */ 544 qh_blk->h_next = qh_lst; 545 qh_blk->qh_h_next = qh_lst->qh_self; 546 qh_blk->e_next = 0; 547 qh_blk->qh_e_next = htole32(UHCI_PTR_T); 548 549 td_lst = sc->sc_last_td_p; 550 551 /* end QH which is used for looping the QHs */ 552 qh_lst->h_next = 0; 553 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */ 554 qh_lst->e_next = td_lst; 555 qh_lst->qh_e_next = td_lst->td_self; 556 557 /* 558 * end TD which hangs from the last QH, to avoid a bug in the PIIX 559 * that makes it run berserk otherwise 560 */ 561 td_lst->next = 0; 562 td_lst->td_next = htole32(UHCI_PTR_T); 563 td_lst->td_status = htole32(0); /* inactive */ 564 td_lst->td_token = htole32(0); 565 td_lst->td_buffer = htole32(0); 566 } 567 if (1) { 568 struct usb2_page_search buf_res; 569 uint32_t *pframes; 570 571 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 572 573 pframes = buf_res.buffer; 574 575 576 /* 577 * Setup UHCI framelist 578 * 579 * Execution order: 580 * 581 * pframes -> full speed isochronous -> interrupt QH's -> low 582 * speed control -> full speed control -> bulk transfers 583 * 584 */ 585 586 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) { 587 pframes[x] = 588 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self; 589 } 590 } 591 /* flush all cache into memory */ 592 593 usb2_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc); 594 595 /* set up the bus struct */ 596 sc->sc_bus.methods = &uhci_bus_methods; 597 598 USB_BUS_LOCK(&sc->sc_bus); 599 /* reset the controller */ 600 uhci_reset(sc); 601 602 /* start the controller */ 603 uhci_start(sc); 604 USB_BUS_UNLOCK(&sc->sc_bus); 605 606 /* catch lost interrupts */ 607 uhci_do_poll(&sc->sc_bus); 608 609 return (0); 610 } 611 612 /* NOTE: suspend/resume is called from 613 * interrupt context and cannot sleep! 614 */ 615 616 void 617 uhci_suspend(uhci_softc_t *sc) 618 { 619 USB_BUS_LOCK(&sc->sc_bus); 620 621 #if USB_DEBUG 622 if (uhcidebug > 2) { 623 uhci_dumpregs(sc); 624 } 625 #endif 626 /* save some state if BIOS doesn't */ 627 628 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 629 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 630 631 /* stop the controller */ 632 633 uhci_reset(sc); 634 635 /* enter global suspend */ 636 637 UHCICMD(sc, UHCI_CMD_EGSM); 638 639 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 640 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 641 642 USB_BUS_UNLOCK(&sc->sc_bus); 643 } 644 645 void 646 uhci_resume(uhci_softc_t *sc) 647 { 648 USB_BUS_LOCK(&sc->sc_bus); 649 650 /* reset the controller */ 651 652 uhci_reset(sc); 653 654 /* force global resume */ 655 656 UHCICMD(sc, UHCI_CMD_FGR); 657 658 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 659 USB_MS_TO_TICKS(USB_RESUME_DELAY)); 660 661 /* and start traffic again */ 662 663 uhci_start(sc); 664 665 #if USB_DEBUG 666 if (uhcidebug > 2) { 667 uhci_dumpregs(sc); 668 } 669 #endif 670 671 USB_BUS_UNLOCK(&sc->sc_bus); 672 673 /* catch lost interrupts */ 674 uhci_do_poll(&sc->sc_bus); 675 } 676 677 #if USB_DEBUG 678 static void 679 uhci_dumpregs(uhci_softc_t *sc) 680 { 681 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 682 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 683 device_get_nameunit(sc->sc_bus.bdev), 684 UREAD2(sc, UHCI_CMD), 685 UREAD2(sc, UHCI_STS), 686 UREAD2(sc, UHCI_INTR), 687 UREAD2(sc, UHCI_FRNUM), 688 UREAD4(sc, UHCI_FLBASEADDR), 689 UREAD1(sc, UHCI_SOF), 690 UREAD2(sc, UHCI_PORTSC1), 691 UREAD2(sc, UHCI_PORTSC2)); 692 } 693 694 static uint8_t 695 uhci_dump_td(uhci_td_t *p) 696 { 697 uint32_t td_next; 698 uint32_t td_status; 699 uint32_t td_token; 700 uint8_t temp; 701 702 usb2_pc_cpu_invalidate(p->page_cache); 703 704 td_next = le32toh(p->td_next); 705 td_status = le32toh(p->td_status); 706 td_token = le32toh(p->td_token); 707 708 /* 709 * Check whether the link pointer in this TD marks the link pointer 710 * as end of queue: 711 */ 712 temp = ((td_next & UHCI_PTR_T) || (td_next == 0)); 713 714 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x " 715 "token=0x%08x buffer=0x%08x\n", 716 p, 717 le32toh(p->td_self), 718 td_next, 719 td_status, 720 td_token, 721 le32toh(p->td_buffer)); 722 723 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x," 724 "addr=%d,endpt=%d,D=%d,maxlen=%d\n", 725 p, 726 (td_next & 1) ? "-T" : "", 727 (td_next & 2) ? "-Q" : "", 728 (td_next & 4) ? "-VF" : "", 729 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "", 730 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "", 731 (td_status & UHCI_TD_NAK) ? "-NAK" : "", 732 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "", 733 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "", 734 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "", 735 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "", 736 (td_status & UHCI_TD_IOC) ? "-IOC" : "", 737 (td_status & UHCI_TD_IOS) ? "-IOS" : "", 738 (td_status & UHCI_TD_LS) ? "-LS" : "", 739 (td_status & UHCI_TD_SPD) ? "-SPD" : "", 740 UHCI_TD_GET_ERRCNT(td_status), 741 UHCI_TD_GET_ACTLEN(td_status), 742 UHCI_TD_GET_PID(td_token), 743 UHCI_TD_GET_DEVADDR(td_token), 744 UHCI_TD_GET_ENDPT(td_token), 745 UHCI_TD_GET_DT(td_token), 746 UHCI_TD_GET_MAXLEN(td_token)); 747 748 return (temp); 749 } 750 751 static uint8_t 752 uhci_dump_qh(uhci_qh_t *sqh) 753 { 754 uint8_t temp; 755 uint32_t qh_h_next; 756 uint32_t qh_e_next; 757 758 usb2_pc_cpu_invalidate(sqh->page_cache); 759 760 qh_h_next = le32toh(sqh->qh_h_next); 761 qh_e_next = le32toh(sqh->qh_e_next); 762 763 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh, 764 le32toh(sqh->qh_self), qh_h_next, qh_e_next); 765 766 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) | 767 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0)); 768 769 return (temp); 770 } 771 772 static void 773 uhci_dump_all(uhci_softc_t *sc) 774 { 775 uhci_dumpregs(sc); 776 uhci_dump_qh(sc->sc_ls_ctl_p_last); 777 uhci_dump_qh(sc->sc_fs_ctl_p_last); 778 uhci_dump_qh(sc->sc_bulk_p_last); 779 uhci_dump_qh(sc->sc_last_qh_p); 780 } 781 782 static void 783 uhci_dump_qhs(uhci_qh_t *sqh) 784 { 785 uint8_t temp; 786 787 temp = uhci_dump_qh(sqh); 788 789 /* 790 * uhci_dump_qhs displays all the QHs and TDs from the given QH 791 * onwards Traverses sideways first, then down. 792 * 793 * QH1 QH2 No QH TD2.1 TD2.2 TD1.1 etc. 794 * 795 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 796 */ 797 798 if (temp & 1) 799 uhci_dump_qhs(sqh->h_next); 800 else 801 DPRINTF("No QH\n"); 802 803 if (temp & 2) 804 uhci_dump_tds(sqh->e_next); 805 else 806 DPRINTF("No TD\n"); 807 } 808 809 static void 810 uhci_dump_tds(uhci_td_t *td) 811 { 812 for (; 813 td != NULL; 814 td = td->obj_next) { 815 if (uhci_dump_td(td)) { 816 break; 817 } 818 } 819 } 820 821 #endif 822 823 /* 824 * Let the last QH loop back to the full speed control transfer QH. 825 * This is what intel calls "bandwidth reclamation" and improves 826 * USB performance a lot for some devices. 827 * If we are already looping, just count it. 828 */ 829 static void 830 uhci_add_loop(uhci_softc_t *sc) 831 { 832 struct uhci_qh *qh_lst; 833 struct uhci_qh *qh_rec; 834 835 #if USB_DEBUG 836 if (uhcinoloop) { 837 return; 838 } 839 #endif 840 if (++(sc->sc_loops) == 1) { 841 DPRINTFN(6, "add\n"); 842 843 qh_lst = sc->sc_last_qh_p; 844 qh_rec = sc->sc_reclaim_qh_p; 845 846 /* NOTE: we don't loop back the soft pointer */ 847 848 qh_lst->qh_h_next = qh_rec->qh_self; 849 usb2_pc_cpu_flush(qh_lst->page_cache); 850 } 851 } 852 853 static void 854 uhci_rem_loop(uhci_softc_t *sc) 855 { 856 struct uhci_qh *qh_lst; 857 858 #if USB_DEBUG 859 if (uhcinoloop) { 860 return; 861 } 862 #endif 863 if (--(sc->sc_loops) == 0) { 864 DPRINTFN(6, "remove\n"); 865 866 qh_lst = sc->sc_last_qh_p; 867 qh_lst->qh_h_next = htole32(UHCI_PTR_T); 868 usb2_pc_cpu_flush(qh_lst->page_cache); 869 } 870 } 871 872 static void 873 uhci_transfer_intr_enqueue(struct usb2_xfer *xfer) 874 { 875 /* check for early completion */ 876 if (uhci_check_transfer(xfer)) { 877 return; 878 } 879 /* put transfer on interrupt queue */ 880 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 881 882 /* start timeout, if any */ 883 if (xfer->timeout != 0) { 884 usb2_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout); 885 } 886 } 887 888 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last) 889 static uhci_td_t * 890 _uhci_append_td(uhci_td_t *std, uhci_td_t *last) 891 { 892 DPRINTFN(11, "%p to %p\n", std, last); 893 894 /* (sc->sc_bus.mtx) must be locked */ 895 896 std->next = last->next; 897 std->td_next = last->td_next; 898 899 std->prev = last; 900 901 usb2_pc_cpu_flush(std->page_cache); 902 903 /* 904 * the last->next->prev is never followed: std->next->prev = std; 905 */ 906 last->next = std; 907 last->td_next = std->td_self; 908 909 usb2_pc_cpu_flush(last->page_cache); 910 911 return (std); 912 } 913 914 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last) 915 static uhci_qh_t * 916 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last) 917 { 918 DPRINTFN(11, "%p to %p\n", sqh, last); 919 920 if (sqh->h_prev != NULL) { 921 /* should not happen */ 922 DPRINTFN(0, "QH already linked!\n"); 923 return (last); 924 } 925 /* (sc->sc_bus.mtx) must be locked */ 926 927 sqh->h_next = last->h_next; 928 sqh->qh_h_next = last->qh_h_next; 929 930 sqh->h_prev = last; 931 932 usb2_pc_cpu_flush(sqh->page_cache); 933 934 /* 935 * The "last->h_next->h_prev" is never followed: 936 * 937 * "sqh->h_next->h_prev" = sqh; 938 */ 939 940 last->h_next = sqh; 941 last->qh_h_next = sqh->qh_self; 942 943 usb2_pc_cpu_flush(last->page_cache); 944 945 return (sqh); 946 } 947 948 /**/ 949 950 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last) 951 static uhci_td_t * 952 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last) 953 { 954 DPRINTFN(11, "%p from %p\n", std, last); 955 956 /* (sc->sc_bus.mtx) must be locked */ 957 958 std->prev->next = std->next; 959 std->prev->td_next = std->td_next; 960 961 usb2_pc_cpu_flush(std->prev->page_cache); 962 963 if (std->next) { 964 std->next->prev = std->prev; 965 usb2_pc_cpu_flush(std->next->page_cache); 966 } 967 return ((last == std) ? std->prev : last); 968 } 969 970 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last) 971 static uhci_qh_t * 972 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last) 973 { 974 DPRINTFN(11, "%p from %p\n", sqh, last); 975 976 /* (sc->sc_bus.mtx) must be locked */ 977 978 /* only remove if not removed from a queue */ 979 if (sqh->h_prev) { 980 981 sqh->h_prev->h_next = sqh->h_next; 982 sqh->h_prev->qh_h_next = sqh->qh_h_next; 983 984 usb2_pc_cpu_flush(sqh->h_prev->page_cache); 985 986 if (sqh->h_next) { 987 sqh->h_next->h_prev = sqh->h_prev; 988 usb2_pc_cpu_flush(sqh->h_next->page_cache); 989 } 990 last = ((last == sqh) ? sqh->h_prev : last); 991 992 sqh->h_prev = 0; 993 994 usb2_pc_cpu_flush(sqh->page_cache); 995 } 996 return (last); 997 } 998 999 static void 1000 uhci_isoc_done(uhci_softc_t *sc, struct usb2_xfer *xfer) 1001 { 1002 struct usb2_page_search res; 1003 uint32_t nframes = xfer->nframes; 1004 uint32_t status; 1005 uint32_t offset = 0; 1006 uint32_t *plen = xfer->frlengths; 1007 uint16_t len = 0; 1008 uhci_td_t *td = xfer->td_transfer_first; 1009 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos]; 1010 1011 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1012 xfer, xfer->pipe); 1013 1014 /* sync any DMA memory before doing fixups */ 1015 1016 usb2_bdma_post_sync(xfer); 1017 1018 while (nframes--) { 1019 if (td == NULL) { 1020 panic("%s:%d: out of TD's\n", 1021 __FUNCTION__, __LINE__); 1022 } 1023 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 1024 pp_last = &sc->sc_isoc_p_last[0]; 1025 } 1026 #if USB_DEBUG 1027 if (uhcidebug > 5) { 1028 DPRINTF("isoc TD\n"); 1029 uhci_dump_td(td); 1030 } 1031 #endif 1032 usb2_pc_cpu_invalidate(td->page_cache); 1033 status = le32toh(td->td_status); 1034 1035 len = UHCI_TD_GET_ACTLEN(status); 1036 1037 if (len > *plen) { 1038 len = *plen; 1039 } 1040 if (td->fix_pc) { 1041 1042 usb2_get_page(td->fix_pc, 0, &res); 1043 1044 /* copy data from fixup location to real location */ 1045 1046 usb2_pc_cpu_invalidate(td->fix_pc); 1047 1048 usb2_copy_in(xfer->frbuffers, offset, 1049 res.buffer, len); 1050 } 1051 offset += *plen; 1052 1053 *plen = len; 1054 1055 /* remove TD from schedule */ 1056 UHCI_REMOVE_TD(td, *pp_last); 1057 1058 pp_last++; 1059 plen++; 1060 td = td->obj_next; 1061 } 1062 1063 xfer->aframes = xfer->nframes; 1064 } 1065 1066 static usb2_error_t 1067 uhci_non_isoc_done_sub(struct usb2_xfer *xfer) 1068 { 1069 struct usb2_page_search res; 1070 uhci_td_t *td; 1071 uhci_td_t *td_alt_next; 1072 uint32_t status; 1073 uint32_t token; 1074 uint16_t len; 1075 1076 td = xfer->td_transfer_cache; 1077 td_alt_next = td->alt_next; 1078 1079 if (xfer->aframes != xfer->nframes) { 1080 xfer->frlengths[xfer->aframes] = 0; 1081 } 1082 while (1) { 1083 1084 usb2_pc_cpu_invalidate(td->page_cache); 1085 status = le32toh(td->td_status); 1086 token = le32toh(td->td_token); 1087 1088 /* 1089 * Verify the status and add 1090 * up the actual length: 1091 */ 1092 1093 len = UHCI_TD_GET_ACTLEN(status); 1094 if (len > td->len) { 1095 /* should not happen */ 1096 DPRINTF("Invalid status length, " 1097 "0x%04x/0x%04x bytes\n", len, td->len); 1098 status |= UHCI_TD_STALLED; 1099 1100 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) { 1101 1102 if (td->fix_pc) { 1103 1104 usb2_get_page(td->fix_pc, 0, &res); 1105 1106 /* 1107 * copy data from fixup location to real 1108 * location 1109 */ 1110 1111 usb2_pc_cpu_invalidate(td->fix_pc); 1112 1113 usb2_copy_in(xfer->frbuffers + xfer->aframes, 1114 xfer->frlengths[xfer->aframes], res.buffer, len); 1115 } 1116 /* update actual length */ 1117 1118 xfer->frlengths[xfer->aframes] += len; 1119 } 1120 /* Check for last transfer */ 1121 if (((void *)td) == xfer->td_transfer_last) { 1122 td = NULL; 1123 break; 1124 } 1125 if (status & UHCI_TD_STALLED) { 1126 /* the transfer is finished */ 1127 td = NULL; 1128 break; 1129 } 1130 /* Check for short transfer */ 1131 if (len != td->len) { 1132 if (xfer->flags_int.short_frames_ok) { 1133 /* follow alt next */ 1134 td = td->alt_next; 1135 } else { 1136 /* the transfer is finished */ 1137 td = NULL; 1138 } 1139 break; 1140 } 1141 td = td->obj_next; 1142 1143 if (td->alt_next != td_alt_next) { 1144 /* this USB frame is complete */ 1145 break; 1146 } 1147 } 1148 1149 /* update transfer cache */ 1150 1151 xfer->td_transfer_cache = td; 1152 1153 /* update data toggle */ 1154 1155 xfer->pipe->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1; 1156 1157 #if USB_DEBUG 1158 if (status & UHCI_TD_ERROR) { 1159 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x " 1160 "status=%s%s%s%s%s%s%s%s%s%s%s\n", 1161 xfer->address, xfer->endpoint, xfer->aframes, 1162 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "", 1163 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "", 1164 (status & UHCI_TD_NAK) ? "[NAK]" : "", 1165 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "", 1166 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "", 1167 (status & UHCI_TD_STALLED) ? "[STALLED]" : "", 1168 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1169 (status & UHCI_TD_IOC) ? "[IOC]" : "", 1170 (status & UHCI_TD_IOS) ? "[IOS]" : "", 1171 (status & UHCI_TD_LS) ? "[LS]" : "", 1172 (status & UHCI_TD_SPD) ? "[SPD]" : ""); 1173 } 1174 #endif 1175 return (status & UHCI_TD_STALLED) ? 1176 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION; 1177 } 1178 1179 static void 1180 uhci_non_isoc_done(struct usb2_xfer *xfer) 1181 { 1182 usb2_error_t err = 0; 1183 1184 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1185 xfer, xfer->pipe); 1186 1187 #if USB_DEBUG 1188 if (uhcidebug > 10) { 1189 uhci_dump_tds(xfer->td_transfer_first); 1190 } 1191 #endif 1192 1193 /* sync any DMA memory before doing fixups */ 1194 1195 usb2_bdma_post_sync(xfer); 1196 1197 /* reset scanner */ 1198 1199 xfer->td_transfer_cache = xfer->td_transfer_first; 1200 1201 if (xfer->flags_int.control_xfr) { 1202 if (xfer->flags_int.control_hdr) { 1203 1204 err = uhci_non_isoc_done_sub(xfer); 1205 } 1206 xfer->aframes = 1; 1207 1208 if (xfer->td_transfer_cache == NULL) { 1209 goto done; 1210 } 1211 } 1212 while (xfer->aframes != xfer->nframes) { 1213 1214 err = uhci_non_isoc_done_sub(xfer); 1215 xfer->aframes++; 1216 1217 if (xfer->td_transfer_cache == NULL) { 1218 goto done; 1219 } 1220 } 1221 1222 if (xfer->flags_int.control_xfr && 1223 !xfer->flags_int.control_act) { 1224 1225 err = uhci_non_isoc_done_sub(xfer); 1226 } 1227 done: 1228 uhci_device_done(xfer, err); 1229 } 1230 1231 /*------------------------------------------------------------------------* 1232 * uhci_check_transfer_sub 1233 * 1234 * The main purpose of this function is to update the data-toggle 1235 * in case it is wrong. 1236 *------------------------------------------------------------------------*/ 1237 static void 1238 uhci_check_transfer_sub(struct usb2_xfer *xfer) 1239 { 1240 uhci_qh_t *qh; 1241 uhci_td_t *td; 1242 uhci_td_t *td_alt_next; 1243 1244 uint32_t td_token; 1245 uint32_t td_self; 1246 1247 td = xfer->td_transfer_cache; 1248 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1249 1250 td_token = td->obj_next->td_token; 1251 td = td->alt_next; 1252 xfer->td_transfer_cache = td; 1253 td_self = td->td_self; 1254 td_alt_next = td->alt_next; 1255 1256 if (xfer->flags_int.control_xfr) 1257 goto skip; /* don't touch the DT value! */ 1258 1259 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1)))) 1260 goto skip; /* data toggle has correct value */ 1261 1262 /* 1263 * The data toggle is wrong and we need to toggle it ! 1264 */ 1265 while (1) { 1266 1267 td->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1268 usb2_pc_cpu_flush(td->page_cache); 1269 1270 if (td == xfer->td_transfer_last) { 1271 /* last transfer */ 1272 break; 1273 } 1274 td = td->obj_next; 1275 1276 if (td->alt_next != td_alt_next) { 1277 /* next frame */ 1278 break; 1279 } 1280 } 1281 skip: 1282 1283 /* update the QH */ 1284 qh->qh_e_next = td_self; 1285 usb2_pc_cpu_flush(qh->page_cache); 1286 1287 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1288 } 1289 1290 /*------------------------------------------------------------------------* 1291 * uhci_check_transfer 1292 * 1293 * Return values: 1294 * 0: USB transfer is not finished 1295 * Else: USB transfer is finished 1296 *------------------------------------------------------------------------*/ 1297 static uint8_t 1298 uhci_check_transfer(struct usb2_xfer *xfer) 1299 { 1300 uint32_t status; 1301 uint32_t token; 1302 uhci_td_t *td; 1303 1304 DPRINTFN(16, "xfer=%p checking transfer\n", xfer); 1305 1306 if (xfer->pipe->methods == &uhci_device_isoc_methods) { 1307 /* isochronous transfer */ 1308 1309 td = xfer->td_transfer_last; 1310 1311 usb2_pc_cpu_invalidate(td->page_cache); 1312 status = le32toh(td->td_status); 1313 1314 /* check also if the first is complete */ 1315 1316 td = xfer->td_transfer_first; 1317 1318 usb2_pc_cpu_invalidate(td->page_cache); 1319 status |= le32toh(td->td_status); 1320 1321 if (!(status & UHCI_TD_ACTIVE)) { 1322 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1323 goto transferred; 1324 } 1325 } else { 1326 /* non-isochronous transfer */ 1327 1328 /* 1329 * check whether there is an error somewhere 1330 * in the middle, or whether there was a short 1331 * packet (SPD and not ACTIVE) 1332 */ 1333 td = xfer->td_transfer_cache; 1334 1335 while (1) { 1336 usb2_pc_cpu_invalidate(td->page_cache); 1337 status = le32toh(td->td_status); 1338 token = le32toh(td->td_token); 1339 1340 /* 1341 * if there is an active TD the transfer isn't done 1342 */ 1343 if (status & UHCI_TD_ACTIVE) { 1344 /* update cache */ 1345 xfer->td_transfer_cache = td; 1346 goto done; 1347 } 1348 /* 1349 * last transfer descriptor makes the transfer done 1350 */ 1351 if (((void *)td) == xfer->td_transfer_last) { 1352 break; 1353 } 1354 /* 1355 * any kind of error makes the transfer done 1356 */ 1357 if (status & UHCI_TD_STALLED) { 1358 break; 1359 } 1360 /* 1361 * check if we reached the last packet 1362 * or if there is a short packet: 1363 */ 1364 if ((td->td_next == htole32(UHCI_PTR_T)) || 1365 (UHCI_TD_GET_ACTLEN(status) < td->len)) { 1366 1367 if (xfer->flags_int.short_frames_ok) { 1368 /* follow alt next */ 1369 if (td->alt_next) { 1370 /* update cache */ 1371 xfer->td_transfer_cache = td; 1372 uhci_check_transfer_sub(xfer); 1373 goto done; 1374 } 1375 } 1376 /* transfer is done */ 1377 break; 1378 } 1379 td = td->obj_next; 1380 } 1381 uhci_non_isoc_done(xfer); 1382 goto transferred; 1383 } 1384 1385 done: 1386 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1387 return (0); 1388 1389 transferred: 1390 return (1); 1391 } 1392 1393 static void 1394 uhci_interrupt_poll(uhci_softc_t *sc) 1395 { 1396 struct usb2_xfer *xfer; 1397 1398 repeat: 1399 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1400 /* 1401 * check if transfer is transferred 1402 */ 1403 if (uhci_check_transfer(xfer)) { 1404 /* queue has been modified */ 1405 goto repeat; 1406 } 1407 } 1408 } 1409 1410 /*------------------------------------------------------------------------* 1411 * uhci_interrupt - UHCI interrupt handler 1412 * 1413 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1414 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1415 * is present ! 1416 *------------------------------------------------------------------------*/ 1417 void 1418 uhci_interrupt(uhci_softc_t *sc) 1419 { 1420 uint32_t status; 1421 1422 USB_BUS_LOCK(&sc->sc_bus); 1423 1424 DPRINTFN(16, "real interrupt\n"); 1425 1426 #if USB_DEBUG 1427 if (uhcidebug > 15) { 1428 uhci_dumpregs(sc); 1429 } 1430 #endif 1431 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1432 if (status == 0) { 1433 /* the interrupt was not for us */ 1434 goto done; 1435 } 1436 if (status & (UHCI_STS_RD | UHCI_STS_HSE | 1437 UHCI_STS_HCPE | UHCI_STS_HCH)) { 1438 1439 if (status & UHCI_STS_RD) { 1440 #if USB_DEBUG 1441 printf("%s: resume detect\n", 1442 __FUNCTION__); 1443 #endif 1444 } 1445 if (status & UHCI_STS_HSE) { 1446 printf("%s: host system error\n", 1447 __FUNCTION__); 1448 } 1449 if (status & UHCI_STS_HCPE) { 1450 printf("%s: host controller process error\n", 1451 __FUNCTION__); 1452 } 1453 if (status & UHCI_STS_HCH) { 1454 /* no acknowledge needed */ 1455 DPRINTF("%s: host controller halted\n", 1456 __FUNCTION__); 1457 #if USB_DEBUG 1458 if (uhcidebug > 0) { 1459 uhci_dump_all(sc); 1460 } 1461 #endif 1462 } 1463 } 1464 /* get acknowledge bits */ 1465 status &= (UHCI_STS_USBINT | 1466 UHCI_STS_USBEI | 1467 UHCI_STS_RD | 1468 UHCI_STS_HSE | 1469 UHCI_STS_HCPE); 1470 1471 if (status == 0) { 1472 /* nothing to acknowledge */ 1473 goto done; 1474 } 1475 /* acknowledge interrupts */ 1476 UWRITE2(sc, UHCI_STS, status); 1477 1478 /* poll all the USB transfers */ 1479 uhci_interrupt_poll(sc); 1480 1481 done: 1482 USB_BUS_UNLOCK(&sc->sc_bus); 1483 } 1484 1485 /* 1486 * called when a request does not complete 1487 */ 1488 static void 1489 uhci_timeout(void *arg) 1490 { 1491 struct usb2_xfer *xfer = arg; 1492 1493 DPRINTF("xfer=%p\n", xfer); 1494 1495 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1496 1497 /* transfer is transferred */ 1498 uhci_device_done(xfer, USB_ERR_TIMEOUT); 1499 } 1500 1501 static void 1502 uhci_do_poll(struct usb2_bus *bus) 1503 { 1504 struct uhci_softc *sc = UHCI_BUS2SC(bus); 1505 1506 USB_BUS_LOCK(&sc->sc_bus); 1507 uhci_interrupt_poll(sc); 1508 uhci_root_ctrl_poll(sc); 1509 USB_BUS_UNLOCK(&sc->sc_bus); 1510 } 1511 1512 static void 1513 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp) 1514 { 1515 uhci_td_t *td; 1516 uhci_td_t *td_next; 1517 uhci_td_t *td_alt_next; 1518 uint32_t average; 1519 uint32_t len_old; 1520 uint8_t shortpkt_old; 1521 uint8_t precompute; 1522 1523 td_alt_next = NULL; 1524 shortpkt_old = temp->shortpkt; 1525 len_old = temp->len; 1526 precompute = 1; 1527 1528 /* software is used to detect short incoming transfers */ 1529 1530 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) { 1531 temp->td_status |= htole32(UHCI_TD_SPD); 1532 } else { 1533 temp->td_status &= ~htole32(UHCI_TD_SPD); 1534 } 1535 1536 temp->ml.buf_offset = 0; 1537 1538 restart: 1539 1540 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1541 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average)); 1542 1543 td = temp->td; 1544 td_next = temp->td_next; 1545 1546 while (1) { 1547 1548 if (temp->len == 0) { 1549 1550 if (temp->shortpkt) { 1551 break; 1552 } 1553 /* send a Zero Length Packet, ZLP, last */ 1554 1555 temp->shortpkt = 1; 1556 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0)); 1557 average = 0; 1558 1559 } else { 1560 1561 average = temp->average; 1562 1563 if (temp->len < average) { 1564 temp->shortpkt = 1; 1565 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1566 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len)); 1567 average = temp->len; 1568 } 1569 } 1570 1571 if (td_next == NULL) { 1572 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__); 1573 } 1574 /* get next TD */ 1575 1576 td = td_next; 1577 td_next = td->obj_next; 1578 1579 /* check if we are pre-computing */ 1580 1581 if (precompute) { 1582 1583 /* update remaining length */ 1584 1585 temp->len -= average; 1586 1587 continue; 1588 } 1589 /* fill out current TD */ 1590 1591 td->td_status = temp->td_status; 1592 td->td_token = temp->td_token; 1593 1594 /* update data toggle */ 1595 1596 temp->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1597 1598 if (average == 0) { 1599 1600 td->len = 0; 1601 td->td_buffer = 0; 1602 td->fix_pc = NULL; 1603 1604 } else { 1605 1606 /* update remaining length */ 1607 1608 temp->len -= average; 1609 1610 td->len = average; 1611 1612 /* fill out buffer pointer and do fixup, if any */ 1613 1614 uhci_mem_layout_fixup(&temp->ml, td); 1615 } 1616 1617 td->alt_next = td_alt_next; 1618 1619 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1620 /* we need to receive these frames one by one ! */ 1621 td->td_status |= htole32(UHCI_TD_IOC); 1622 td->td_next = htole32(UHCI_PTR_T); 1623 } else { 1624 if (td_next) { 1625 /* link the current TD with the next one */ 1626 td->td_next = td_next->td_self; 1627 } 1628 } 1629 1630 usb2_pc_cpu_flush(td->page_cache); 1631 } 1632 1633 if (precompute) { 1634 precompute = 0; 1635 1636 /* setup alt next pointer, if any */ 1637 if (temp->last_frame) { 1638 td_alt_next = NULL; 1639 } else { 1640 /* we use this field internally */ 1641 td_alt_next = td_next; 1642 } 1643 1644 /* restore */ 1645 temp->shortpkt = shortpkt_old; 1646 temp->len = len_old; 1647 goto restart; 1648 } 1649 temp->td = td; 1650 temp->td_next = td_next; 1651 } 1652 1653 static uhci_td_t * 1654 uhci_setup_standard_chain(struct usb2_xfer *xfer) 1655 { 1656 struct uhci_std_temp temp; 1657 uhci_td_t *td; 1658 uint32_t x; 1659 1660 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1661 xfer->address, UE_GET_ADDR(xfer->endpoint), 1662 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1663 1664 temp.average = xfer->max_frame_size; 1665 temp.max_frame_size = xfer->max_frame_size; 1666 1667 /* toggle the DMA set we are using */ 1668 xfer->flags_int.curr_dma_set ^= 1; 1669 1670 /* get next DMA set */ 1671 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1672 xfer->td_transfer_first = td; 1673 xfer->td_transfer_cache = td; 1674 1675 temp.td = NULL; 1676 temp.td_next = td; 1677 temp.last_frame = 0; 1678 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1679 1680 uhci_mem_layout_init(&temp.ml, xfer); 1681 1682 temp.td_status = 1683 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | 1684 UHCI_TD_ACTIVE)); 1685 1686 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1687 temp.td_status |= htole32(UHCI_TD_LS); 1688 } 1689 temp.td_token = 1690 htole32(UHCI_TD_SET_ENDPT(xfer->endpoint) | 1691 UHCI_TD_SET_DEVADDR(xfer->address)); 1692 1693 if (xfer->pipe->toggle_next) { 1694 /* DATA1 is next */ 1695 temp.td_token |= htole32(UHCI_TD_SET_DT(1)); 1696 } 1697 /* check if we should prepend a setup message */ 1698 1699 if (xfer->flags_int.control_xfr) { 1700 1701 if (xfer->flags_int.control_hdr) { 1702 1703 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1704 UHCI_TD_SET_ENDPT(0xF)); 1705 temp.td_token |= htole32(UHCI_TD_PID_SETUP | 1706 UHCI_TD_SET_DT(0)); 1707 1708 temp.len = xfer->frlengths[0]; 1709 temp.ml.buf_pc = xfer->frbuffers + 0; 1710 temp.shortpkt = temp.len ? 1 : 0; 1711 /* check for last frame */ 1712 if (xfer->nframes == 1) { 1713 /* no STATUS stage yet, SETUP is last */ 1714 if (xfer->flags_int.control_act) { 1715 temp.last_frame = 1; 1716 temp.setup_alt_next = 0; 1717 } 1718 } 1719 uhci_setup_standard_chain_sub(&temp); 1720 } 1721 x = 1; 1722 } else { 1723 x = 0; 1724 } 1725 1726 while (x != xfer->nframes) { 1727 1728 /* DATA0 / DATA1 message */ 1729 1730 temp.len = xfer->frlengths[x]; 1731 temp.ml.buf_pc = xfer->frbuffers + x; 1732 1733 x++; 1734 1735 if (x == xfer->nframes) { 1736 if (xfer->flags_int.control_xfr) { 1737 /* no STATUS stage yet, DATA is last */ 1738 if (xfer->flags_int.control_act) { 1739 temp.last_frame = 1; 1740 temp.setup_alt_next = 0; 1741 } 1742 } else { 1743 temp.last_frame = 1; 1744 temp.setup_alt_next = 0; 1745 } 1746 } 1747 /* 1748 * Keep previous data toggle, 1749 * device address and endpoint number: 1750 */ 1751 1752 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1753 UHCI_TD_SET_ENDPT(0xF) | 1754 UHCI_TD_SET_DT(1)); 1755 1756 if (temp.len == 0) { 1757 1758 /* make sure that we send an USB packet */ 1759 1760 temp.shortpkt = 0; 1761 1762 } else { 1763 1764 /* regular data transfer */ 1765 1766 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1767 } 1768 1769 /* set endpoint direction */ 1770 1771 temp.td_token |= 1772 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 1773 htole32(UHCI_TD_PID_IN) : 1774 htole32(UHCI_TD_PID_OUT); 1775 1776 uhci_setup_standard_chain_sub(&temp); 1777 } 1778 1779 /* check if we should append a status stage */ 1780 1781 if (xfer->flags_int.control_xfr && 1782 !xfer->flags_int.control_act) { 1783 1784 /* 1785 * send a DATA1 message and reverse the current endpoint 1786 * direction 1787 */ 1788 1789 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1790 UHCI_TD_SET_ENDPT(0xF) | 1791 UHCI_TD_SET_DT(1)); 1792 temp.td_token |= 1793 (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) ? 1794 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) : 1795 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1)); 1796 1797 temp.len = 0; 1798 temp.ml.buf_pc = NULL; 1799 temp.shortpkt = 0; 1800 temp.last_frame = 1; 1801 temp.setup_alt_next = 0; 1802 1803 uhci_setup_standard_chain_sub(&temp); 1804 } 1805 td = temp.td; 1806 1807 /* Ensure that last TD is terminating: */ 1808 td->td_next = htole32(UHCI_PTR_T); 1809 1810 /* set interrupt bit */ 1811 1812 td->td_status |= htole32(UHCI_TD_IOC); 1813 1814 usb2_pc_cpu_flush(td->page_cache); 1815 1816 /* must have at least one frame! */ 1817 1818 xfer->td_transfer_last = td; 1819 1820 #if USB_DEBUG 1821 if (uhcidebug > 8) { 1822 DPRINTF("nexttog=%d; data before transfer:\n", 1823 xfer->pipe->toggle_next); 1824 uhci_dump_tds(xfer->td_transfer_first); 1825 } 1826 #endif 1827 return (xfer->td_transfer_first); 1828 } 1829 1830 /* NOTE: "done" can be run two times in a row, 1831 * from close and from interrupt 1832 */ 1833 1834 static void 1835 uhci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1836 { 1837 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1838 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1839 uhci_qh_t *qh; 1840 1841 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1842 1843 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1844 xfer, xfer->pipe, error); 1845 1846 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1847 if (qh) { 1848 usb2_pc_cpu_invalidate(qh->page_cache); 1849 } 1850 if (xfer->flags_int.bandwidth_reclaimed) { 1851 xfer->flags_int.bandwidth_reclaimed = 0; 1852 uhci_rem_loop(sc); 1853 } 1854 if (methods == &uhci_device_bulk_methods) { 1855 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 1856 } 1857 if (methods == &uhci_device_ctrl_methods) { 1858 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1859 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 1860 } else { 1861 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 1862 } 1863 } 1864 if (methods == &uhci_device_intr_methods) { 1865 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 1866 } 1867 /* 1868 * Only finish isochronous transfers once 1869 * which will update "xfer->frlengths". 1870 */ 1871 if (xfer->td_transfer_first && 1872 xfer->td_transfer_last) { 1873 if (methods == &uhci_device_isoc_methods) { 1874 uhci_isoc_done(sc, xfer); 1875 } 1876 xfer->td_transfer_first = NULL; 1877 xfer->td_transfer_last = NULL; 1878 } 1879 /* dequeue transfer and start next transfer */ 1880 usb2_transfer_done(xfer, error); 1881 } 1882 1883 /*------------------------------------------------------------------------* 1884 * uhci bulk support 1885 *------------------------------------------------------------------------*/ 1886 static void 1887 uhci_device_bulk_open(struct usb2_xfer *xfer) 1888 { 1889 return; 1890 } 1891 1892 static void 1893 uhci_device_bulk_close(struct usb2_xfer *xfer) 1894 { 1895 uhci_device_done(xfer, USB_ERR_CANCELLED); 1896 } 1897 1898 static void 1899 uhci_device_bulk_enter(struct usb2_xfer *xfer) 1900 { 1901 return; 1902 } 1903 1904 static void 1905 uhci_device_bulk_start(struct usb2_xfer *xfer) 1906 { 1907 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1908 uhci_td_t *td; 1909 uhci_qh_t *qh; 1910 1911 /* setup TD's */ 1912 td = uhci_setup_standard_chain(xfer); 1913 1914 /* setup QH */ 1915 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1916 1917 qh->e_next = td; 1918 qh->qh_e_next = td->td_self; 1919 1920 if (xfer->xroot->udev->pwr_save.suspended == 0) { 1921 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 1922 uhci_add_loop(sc); 1923 xfer->flags_int.bandwidth_reclaimed = 1; 1924 } else { 1925 usb2_pc_cpu_flush(qh->page_cache); 1926 } 1927 1928 /* put transfer on interrupt queue */ 1929 uhci_transfer_intr_enqueue(xfer); 1930 } 1931 1932 struct usb2_pipe_methods uhci_device_bulk_methods = 1933 { 1934 .open = uhci_device_bulk_open, 1935 .close = uhci_device_bulk_close, 1936 .enter = uhci_device_bulk_enter, 1937 .start = uhci_device_bulk_start, 1938 .enter_is_cancelable = 1, 1939 .start_is_cancelable = 1, 1940 }; 1941 1942 /*------------------------------------------------------------------------* 1943 * uhci control support 1944 *------------------------------------------------------------------------*/ 1945 static void 1946 uhci_device_ctrl_open(struct usb2_xfer *xfer) 1947 { 1948 return; 1949 } 1950 1951 static void 1952 uhci_device_ctrl_close(struct usb2_xfer *xfer) 1953 { 1954 uhci_device_done(xfer, USB_ERR_CANCELLED); 1955 } 1956 1957 static void 1958 uhci_device_ctrl_enter(struct usb2_xfer *xfer) 1959 { 1960 return; 1961 } 1962 1963 static void 1964 uhci_device_ctrl_start(struct usb2_xfer *xfer) 1965 { 1966 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1967 uhci_qh_t *qh; 1968 uhci_td_t *td; 1969 1970 /* setup TD's */ 1971 td = uhci_setup_standard_chain(xfer); 1972 1973 /* setup QH */ 1974 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1975 1976 qh->e_next = td; 1977 qh->qh_e_next = td->td_self; 1978 1979 /* 1980 * NOTE: some devices choke on bandwidth- reclamation for control 1981 * transfers 1982 */ 1983 if (xfer->xroot->udev->pwr_save.suspended == 0) { 1984 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1985 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 1986 } else { 1987 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 1988 } 1989 } else { 1990 usb2_pc_cpu_flush(qh->page_cache); 1991 } 1992 /* put transfer on interrupt queue */ 1993 uhci_transfer_intr_enqueue(xfer); 1994 } 1995 1996 struct usb2_pipe_methods uhci_device_ctrl_methods = 1997 { 1998 .open = uhci_device_ctrl_open, 1999 .close = uhci_device_ctrl_close, 2000 .enter = uhci_device_ctrl_enter, 2001 .start = uhci_device_ctrl_start, 2002 .enter_is_cancelable = 1, 2003 .start_is_cancelable = 1, 2004 }; 2005 2006 /*------------------------------------------------------------------------* 2007 * uhci interrupt support 2008 *------------------------------------------------------------------------*/ 2009 static void 2010 uhci_device_intr_open(struct usb2_xfer *xfer) 2011 { 2012 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2013 uint16_t best; 2014 uint16_t bit; 2015 uint16_t x; 2016 2017 best = 0; 2018 bit = UHCI_IFRAMELIST_COUNT / 2; 2019 while (bit) { 2020 if (xfer->interval >= bit) { 2021 x = bit; 2022 best = bit; 2023 while (x & bit) { 2024 if (sc->sc_intr_stat[x] < 2025 sc->sc_intr_stat[best]) { 2026 best = x; 2027 } 2028 x++; 2029 } 2030 break; 2031 } 2032 bit >>= 1; 2033 } 2034 2035 sc->sc_intr_stat[best]++; 2036 xfer->qh_pos = best; 2037 2038 DPRINTFN(3, "best=%d interval=%d\n", 2039 best, xfer->interval); 2040 } 2041 2042 static void 2043 uhci_device_intr_close(struct usb2_xfer *xfer) 2044 { 2045 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2046 2047 sc->sc_intr_stat[xfer->qh_pos]--; 2048 2049 uhci_device_done(xfer, USB_ERR_CANCELLED); 2050 } 2051 2052 static void 2053 uhci_device_intr_enter(struct usb2_xfer *xfer) 2054 { 2055 return; 2056 } 2057 2058 static void 2059 uhci_device_intr_start(struct usb2_xfer *xfer) 2060 { 2061 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2062 uhci_qh_t *qh; 2063 uhci_td_t *td; 2064 2065 /* setup TD's */ 2066 td = uhci_setup_standard_chain(xfer); 2067 2068 /* setup QH */ 2069 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2070 2071 qh->e_next = td; 2072 qh->qh_e_next = td->td_self; 2073 2074 if (xfer->xroot->udev->pwr_save.suspended == 0) { 2075 2076 /* enter QHs into the controller data structures */ 2077 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 2078 2079 } else { 2080 usb2_pc_cpu_flush(qh->page_cache); 2081 } 2082 2083 /* put transfer on interrupt queue */ 2084 uhci_transfer_intr_enqueue(xfer); 2085 } 2086 2087 struct usb2_pipe_methods uhci_device_intr_methods = 2088 { 2089 .open = uhci_device_intr_open, 2090 .close = uhci_device_intr_close, 2091 .enter = uhci_device_intr_enter, 2092 .start = uhci_device_intr_start, 2093 .enter_is_cancelable = 1, 2094 .start_is_cancelable = 1, 2095 }; 2096 2097 /*------------------------------------------------------------------------* 2098 * uhci isochronous support 2099 *------------------------------------------------------------------------*/ 2100 static void 2101 uhci_device_isoc_open(struct usb2_xfer *xfer) 2102 { 2103 uhci_td_t *td; 2104 uint32_t td_token; 2105 uint8_t ds; 2106 2107 td_token = 2108 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 2109 UHCI_TD_IN(0, xfer->endpoint, xfer->address, 0) : 2110 UHCI_TD_OUT(0, xfer->endpoint, xfer->address, 0); 2111 2112 td_token = htole32(td_token); 2113 2114 /* initialize all TD's */ 2115 2116 for (ds = 0; ds != 2; ds++) { 2117 2118 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2119 2120 /* mark TD as inactive */ 2121 td->td_status = htole32(UHCI_TD_IOS); 2122 td->td_token = td_token; 2123 2124 usb2_pc_cpu_flush(td->page_cache); 2125 } 2126 } 2127 } 2128 2129 static void 2130 uhci_device_isoc_close(struct usb2_xfer *xfer) 2131 { 2132 uhci_device_done(xfer, USB_ERR_CANCELLED); 2133 } 2134 2135 static void 2136 uhci_device_isoc_enter(struct usb2_xfer *xfer) 2137 { 2138 struct uhci_mem_layout ml; 2139 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2140 uint32_t nframes; 2141 uint32_t temp; 2142 uint32_t *plen; 2143 2144 #if USB_DEBUG 2145 uint8_t once = 1; 2146 2147 #endif 2148 uhci_td_t *td; 2149 uhci_td_t *td_last = NULL; 2150 uhci_td_t **pp_last; 2151 2152 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2153 xfer, xfer->pipe->isoc_next, xfer->nframes); 2154 2155 nframes = UREAD2(sc, UHCI_FRNUM); 2156 2157 temp = (nframes - xfer->pipe->isoc_next) & 2158 (UHCI_VFRAMELIST_COUNT - 1); 2159 2160 if ((xfer->pipe->is_synced == 0) || 2161 (temp < xfer->nframes)) { 2162 /* 2163 * If there is data underflow or the pipe queue is empty we 2164 * schedule the transfer a few frames ahead of the current 2165 * frame position. Else two isochronous transfers might 2166 * overlap. 2167 */ 2168 xfer->pipe->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1); 2169 xfer->pipe->is_synced = 1; 2170 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2171 } 2172 /* 2173 * compute how many milliseconds the insertion is ahead of the 2174 * current frame position: 2175 */ 2176 temp = (xfer->pipe->isoc_next - nframes) & 2177 (UHCI_VFRAMELIST_COUNT - 1); 2178 2179 /* 2180 * pre-compute when the isochronous transfer will be finished: 2181 */ 2182 xfer->isoc_time_complete = 2183 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2184 xfer->nframes; 2185 2186 /* get the real number of frames */ 2187 2188 nframes = xfer->nframes; 2189 2190 uhci_mem_layout_init(&ml, xfer); 2191 2192 plen = xfer->frlengths; 2193 2194 /* toggle the DMA set we are using */ 2195 xfer->flags_int.curr_dma_set ^= 1; 2196 2197 /* get next DMA set */ 2198 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2199 xfer->td_transfer_first = td; 2200 2201 pp_last = &sc->sc_isoc_p_last[xfer->pipe->isoc_next]; 2202 2203 /* store starting position */ 2204 2205 xfer->qh_pos = xfer->pipe->isoc_next; 2206 2207 while (nframes--) { 2208 if (td == NULL) { 2209 panic("%s:%d: out of TD's\n", 2210 __FUNCTION__, __LINE__); 2211 } 2212 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 2213 pp_last = &sc->sc_isoc_p_last[0]; 2214 } 2215 if (*plen > xfer->max_frame_size) { 2216 #if USB_DEBUG 2217 if (once) { 2218 once = 0; 2219 printf("%s: frame length(%d) exceeds %d " 2220 "bytes (frame truncated)\n", 2221 __FUNCTION__, *plen, 2222 xfer->max_frame_size); 2223 } 2224 #endif 2225 *plen = xfer->max_frame_size; 2226 } 2227 /* reuse td_token from last transfer */ 2228 2229 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2230 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen)); 2231 2232 td->len = *plen; 2233 2234 if (td->len == 0) { 2235 /* 2236 * Do not call "uhci_mem_layout_fixup()" when the 2237 * length is zero! 2238 */ 2239 td->td_buffer = 0; 2240 td->fix_pc = NULL; 2241 2242 } else { 2243 2244 /* fill out buffer pointer and do fixup, if any */ 2245 2246 uhci_mem_layout_fixup(&ml, td); 2247 2248 } 2249 2250 /* update status */ 2251 if (nframes == 0) { 2252 td->td_status = htole32 2253 (UHCI_TD_ZERO_ACTLEN 2254 (UHCI_TD_SET_ERRCNT(0) | 2255 UHCI_TD_ACTIVE | 2256 UHCI_TD_IOS | 2257 UHCI_TD_IOC)); 2258 } else { 2259 td->td_status = htole32 2260 (UHCI_TD_ZERO_ACTLEN 2261 (UHCI_TD_SET_ERRCNT(0) | 2262 UHCI_TD_ACTIVE | 2263 UHCI_TD_IOS)); 2264 } 2265 2266 usb2_pc_cpu_flush(td->page_cache); 2267 2268 #if USB_DEBUG 2269 if (uhcidebug > 5) { 2270 DPRINTF("TD %d\n", nframes); 2271 uhci_dump_td(td); 2272 } 2273 #endif 2274 /* insert TD into schedule */ 2275 UHCI_APPEND_TD(td, *pp_last); 2276 pp_last++; 2277 2278 plen++; 2279 td_last = td; 2280 td = td->obj_next; 2281 } 2282 2283 xfer->td_transfer_last = td_last; 2284 2285 /* update isoc_next */ 2286 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) & 2287 (UHCI_VFRAMELIST_COUNT - 1); 2288 } 2289 2290 static void 2291 uhci_device_isoc_start(struct usb2_xfer *xfer) 2292 { 2293 /* put transfer on interrupt queue */ 2294 uhci_transfer_intr_enqueue(xfer); 2295 } 2296 2297 struct usb2_pipe_methods uhci_device_isoc_methods = 2298 { 2299 .open = uhci_device_isoc_open, 2300 .close = uhci_device_isoc_close, 2301 .enter = uhci_device_isoc_enter, 2302 .start = uhci_device_isoc_start, 2303 .enter_is_cancelable = 1, 2304 .start_is_cancelable = 1, 2305 }; 2306 2307 /*------------------------------------------------------------------------* 2308 * uhci root control support 2309 *------------------------------------------------------------------------* 2310 * simulate a hardware hub by handling 2311 * all the necessary requests 2312 *------------------------------------------------------------------------*/ 2313 2314 static void 2315 uhci_root_ctrl_open(struct usb2_xfer *xfer) 2316 { 2317 return; 2318 } 2319 2320 static void 2321 uhci_root_ctrl_close(struct usb2_xfer *xfer) 2322 { 2323 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2324 2325 if (sc->sc_root_ctrl.xfer == xfer) { 2326 sc->sc_root_ctrl.xfer = NULL; 2327 } 2328 uhci_device_done(xfer, USB_ERR_CANCELLED); 2329 } 2330 2331 /* data structures and routines 2332 * to emulate the root hub: 2333 */ 2334 2335 static const 2336 struct usb2_device_descriptor uhci_devd = 2337 { 2338 sizeof(struct usb2_device_descriptor), 2339 UDESC_DEVICE, /* type */ 2340 {0x00, 0x01}, /* USB version */ 2341 UDCLASS_HUB, /* class */ 2342 UDSUBCLASS_HUB, /* subclass */ 2343 UDPROTO_FSHUB, /* protocol */ 2344 64, /* max packet */ 2345 {0}, {0}, {0x00, 0x01}, /* device id */ 2346 1, 2, 0, /* string indicies */ 2347 1 /* # of configurations */ 2348 }; 2349 2350 static const struct uhci_config_desc uhci_confd = { 2351 .confd = { 2352 .bLength = sizeof(struct usb2_config_descriptor), 2353 .bDescriptorType = UDESC_CONFIG, 2354 .wTotalLength[0] = sizeof(uhci_confd), 2355 .bNumInterface = 1, 2356 .bConfigurationValue = 1, 2357 .iConfiguration = 0, 2358 .bmAttributes = UC_SELF_POWERED, 2359 .bMaxPower = 0 /* max power */ 2360 }, 2361 2362 .ifcd = { 2363 .bLength = sizeof(struct usb2_interface_descriptor), 2364 .bDescriptorType = UDESC_INTERFACE, 2365 .bNumEndpoints = 1, 2366 .bInterfaceClass = UICLASS_HUB, 2367 .bInterfaceSubClass = UISUBCLASS_HUB, 2368 .bInterfaceProtocol = UIPROTO_FSHUB, 2369 }, 2370 2371 .endpd = { 2372 .bLength = sizeof(struct usb2_endpoint_descriptor), 2373 .bDescriptorType = UDESC_ENDPOINT, 2374 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 2375 .bmAttributes = UE_INTERRUPT, 2376 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2377 .bInterval = 255, 2378 }, 2379 }; 2380 2381 static const 2382 struct usb2_hub_descriptor_min uhci_hubd_piix = 2383 { 2384 sizeof(uhci_hubd_piix), 2385 UDESC_HUB, 2386 2, 2387 {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0}, 2388 50, /* power on to power good */ 2389 0, 2390 {0x00}, /* both ports are removable */ 2391 }; 2392 2393 /* 2394 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 2395 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 2396 * should not be used by the USB subsystem. As we cannot issue a 2397 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 2398 * will be enabled as part of the reset. 2399 * 2400 * On the VT83C572, the port cannot be successfully enabled until the 2401 * outstanding "port enable change" and "connection status change" 2402 * events have been reset. 2403 */ 2404 static usb2_error_t 2405 uhci_portreset(uhci_softc_t *sc, uint16_t index) 2406 { 2407 uint16_t port; 2408 uint16_t x; 2409 uint8_t lim; 2410 2411 if (index == 1) 2412 port = UHCI_PORTSC1; 2413 else if (index == 2) 2414 port = UHCI_PORTSC2; 2415 else 2416 return (USB_ERR_IOERROR); 2417 2418 /* 2419 * Before we do anything, turn on SOF messages on the USB 2420 * BUS. Some USB devices do not cope without them! 2421 */ 2422 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 2423 2424 DPRINTF("Activating SOFs!\n"); 2425 2426 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 2427 2428 /* wait a little bit */ 2429 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 2430 } 2431 2432 x = URWMASK(UREAD2(sc, port)); 2433 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2434 2435 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2436 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 2437 2438 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n", 2439 index, UREAD2(sc, port)); 2440 2441 x = URWMASK(UREAD2(sc, port)); 2442 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2443 2444 2445 mtx_unlock(&sc->sc_bus.bus_mtx); 2446 2447 /* 2448 * This delay needs to be exactly 100us, else some USB devices 2449 * fail to attach! 2450 */ 2451 DELAY(100); 2452 2453 mtx_lock(&sc->sc_bus.bus_mtx); 2454 2455 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n", 2456 index, UREAD2(sc, port)); 2457 2458 x = URWMASK(UREAD2(sc, port)); 2459 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2460 2461 for (lim = 0; lim < 12; lim++) { 2462 2463 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2464 USB_MS_TO_TICKS(USB_PORT_RESET_DELAY)); 2465 2466 x = UREAD2(sc, port); 2467 2468 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n", 2469 index, lim, x); 2470 2471 if (!(x & UHCI_PORTSC_CCS)) { 2472 /* 2473 * No device is connected (or was disconnected 2474 * during reset). Consider the port reset. 2475 * The delay must be long enough to ensure on 2476 * the initial iteration that the device 2477 * connection will have been registered. 50ms 2478 * appears to be sufficient, but 20ms is not. 2479 */ 2480 DPRINTFN(4, "uhci port %d loop %u, device detached\n", 2481 index, lim); 2482 goto done; 2483 } 2484 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 2485 /* 2486 * Port enabled changed and/or connection 2487 * status changed were set. Reset either or 2488 * both raised flags (by writing a 1 to that 2489 * bit), and wait again for state to settle. 2490 */ 2491 UWRITE2(sc, port, URWMASK(x) | 2492 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 2493 continue; 2494 } 2495 if (x & UHCI_PORTSC_PE) { 2496 /* port is enabled */ 2497 goto done; 2498 } 2499 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 2500 } 2501 2502 DPRINTFN(2, "uhci port %d reset timed out\n", index); 2503 return (USB_ERR_TIMEOUT); 2504 2505 done: 2506 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n", 2507 index, UREAD2(sc, port)); 2508 2509 sc->sc_isreset = 1; 2510 return (USB_ERR_NORMAL_COMPLETION); 2511 } 2512 2513 static void 2514 uhci_root_ctrl_enter(struct usb2_xfer *xfer) 2515 { 2516 return; 2517 } 2518 2519 static void 2520 uhci_root_ctrl_start(struct usb2_xfer *xfer) 2521 { 2522 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2523 2524 DPRINTF("\n"); 2525 2526 sc->sc_root_ctrl.xfer = xfer; 2527 2528 usb2_bus_roothub_exec(xfer->xroot->bus); 2529 } 2530 2531 static void 2532 uhci_root_ctrl_task(struct usb2_bus *bus) 2533 { 2534 uhci_root_ctrl_poll(UHCI_BUS2SC(bus)); 2535 } 2536 2537 static void 2538 uhci_root_ctrl_done(struct usb2_xfer *xfer, 2539 struct usb2_sw_transfer *std) 2540 { 2541 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2542 char *ptr; 2543 uint16_t x; 2544 uint16_t port; 2545 uint16_t value; 2546 uint16_t index; 2547 uint16_t status; 2548 uint16_t change; 2549 2550 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2551 2552 if (std->state != USB_SW_TR_SETUP) { 2553 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2554 /* transfer transferred */ 2555 uhci_device_done(xfer, std->err); 2556 } 2557 goto done; 2558 } 2559 /* buffer reset */ 2560 std->ptr = sc->sc_hub_desc.temp; 2561 std->len = 0; 2562 2563 value = UGETW(std->req.wValue); 2564 index = UGETW(std->req.wIndex); 2565 2566 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2567 "wValue=0x%04x wIndex=0x%04x\n", 2568 std->req.bmRequestType, std->req.bRequest, 2569 UGETW(std->req.wLength), value, index); 2570 2571 #define C(x,y) ((x) | ((y) << 8)) 2572 switch (C(std->req.bRequest, std->req.bmRequestType)) { 2573 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2574 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2575 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2576 /* 2577 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2578 * for the integrated root hub. 2579 */ 2580 break; 2581 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2582 std->len = 1; 2583 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2584 break; 2585 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2586 switch (value >> 8) { 2587 case UDESC_DEVICE: 2588 if ((value & 0xff) != 0) { 2589 std->err = USB_ERR_IOERROR; 2590 goto done; 2591 } 2592 std->len = sizeof(uhci_devd); 2593 sc->sc_hub_desc.devd = uhci_devd; 2594 break; 2595 2596 case UDESC_CONFIG: 2597 if ((value & 0xff) != 0) { 2598 std->err = USB_ERR_IOERROR; 2599 goto done; 2600 } 2601 std->len = sizeof(uhci_confd); 2602 std->ptr = USB_ADD_BYTES(&uhci_confd, 0); 2603 break; 2604 2605 case UDESC_STRING: 2606 switch (value & 0xff) { 2607 case 0: /* Language table */ 2608 ptr = "\001"; 2609 break; 2610 2611 case 1: /* Vendor */ 2612 ptr = sc->sc_vendor; 2613 break; 2614 2615 case 2: /* Product */ 2616 ptr = "UHCI root HUB"; 2617 break; 2618 2619 default: 2620 ptr = ""; 2621 break; 2622 } 2623 2624 std->len = usb2_make_str_desc 2625 (sc->sc_hub_desc.temp, 2626 sizeof(sc->sc_hub_desc.temp), 2627 ptr); 2628 break; 2629 2630 default: 2631 std->err = USB_ERR_IOERROR; 2632 goto done; 2633 } 2634 break; 2635 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2636 std->len = 1; 2637 sc->sc_hub_desc.temp[0] = 0; 2638 break; 2639 case C(UR_GET_STATUS, UT_READ_DEVICE): 2640 std->len = 2; 2641 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2642 break; 2643 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2644 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2645 std->len = 2; 2646 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2647 break; 2648 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2649 if (value >= UHCI_MAX_DEVICES) { 2650 std->err = USB_ERR_IOERROR; 2651 goto done; 2652 } 2653 sc->sc_addr = value; 2654 break; 2655 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2656 if ((value != 0) && (value != 1)) { 2657 std->err = USB_ERR_IOERROR; 2658 goto done; 2659 } 2660 sc->sc_conf = value; 2661 break; 2662 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2663 break; 2664 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2665 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2666 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2667 std->err = USB_ERR_IOERROR; 2668 goto done; 2669 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2670 break; 2671 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2672 break; 2673 /* Hub requests */ 2674 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2675 break; 2676 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2677 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE " 2678 "port=%d feature=%d\n", 2679 index, value); 2680 if (index == 1) 2681 port = UHCI_PORTSC1; 2682 else if (index == 2) 2683 port = UHCI_PORTSC2; 2684 else { 2685 std->err = USB_ERR_IOERROR; 2686 goto done; 2687 } 2688 switch (value) { 2689 case UHF_PORT_ENABLE: 2690 x = URWMASK(UREAD2(sc, port)); 2691 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2692 break; 2693 case UHF_PORT_SUSPEND: 2694 x = URWMASK(UREAD2(sc, port)); 2695 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP)); 2696 break; 2697 case UHF_PORT_RESET: 2698 x = URWMASK(UREAD2(sc, port)); 2699 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2700 break; 2701 case UHF_C_PORT_CONNECTION: 2702 x = URWMASK(UREAD2(sc, port)); 2703 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2704 break; 2705 case UHF_C_PORT_ENABLE: 2706 x = URWMASK(UREAD2(sc, port)); 2707 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2708 break; 2709 case UHF_C_PORT_OVER_CURRENT: 2710 x = URWMASK(UREAD2(sc, port)); 2711 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2712 break; 2713 case UHF_C_PORT_RESET: 2714 sc->sc_isreset = 0; 2715 std->err = USB_ERR_NORMAL_COMPLETION; 2716 goto done; 2717 case UHF_C_PORT_SUSPEND: 2718 sc->sc_isresumed &= ~(1 << index); 2719 break; 2720 case UHF_PORT_CONNECTION: 2721 case UHF_PORT_OVER_CURRENT: 2722 case UHF_PORT_POWER: 2723 case UHF_PORT_LOW_SPEED: 2724 default: 2725 std->err = USB_ERR_IOERROR; 2726 goto done; 2727 } 2728 break; 2729 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2730 if (index == 1) 2731 port = UHCI_PORTSC1; 2732 else if (index == 2) 2733 port = UHCI_PORTSC2; 2734 else { 2735 std->err = USB_ERR_IOERROR; 2736 goto done; 2737 } 2738 std->len = 1; 2739 sc->sc_hub_desc.temp[0] = 2740 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2741 UHCI_PORTSC_LS_SHIFT); 2742 break; 2743 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2744 if ((value & 0xff) != 0) { 2745 std->err = USB_ERR_IOERROR; 2746 goto done; 2747 } 2748 std->len = sizeof(uhci_hubd_piix); 2749 std->ptr = USB_ADD_BYTES(&uhci_hubd_piix, 0); 2750 break; 2751 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2752 std->len = 16; 2753 bzero(sc->sc_hub_desc.temp, 16); 2754 break; 2755 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2756 if (index == 1) 2757 port = UHCI_PORTSC1; 2758 else if (index == 2) 2759 port = UHCI_PORTSC2; 2760 else { 2761 std->err = USB_ERR_IOERROR; 2762 goto done; 2763 } 2764 x = UREAD2(sc, port); 2765 status = change = 0; 2766 if (x & UHCI_PORTSC_CCS) 2767 status |= UPS_CURRENT_CONNECT_STATUS; 2768 if (x & UHCI_PORTSC_CSC) 2769 change |= UPS_C_CONNECT_STATUS; 2770 if (x & UHCI_PORTSC_PE) 2771 status |= UPS_PORT_ENABLED; 2772 if (x & UHCI_PORTSC_POEDC) 2773 change |= UPS_C_PORT_ENABLED; 2774 if (x & UHCI_PORTSC_OCI) 2775 status |= UPS_OVERCURRENT_INDICATOR; 2776 if (x & UHCI_PORTSC_OCIC) 2777 change |= UPS_C_OVERCURRENT_INDICATOR; 2778 if (x & UHCI_PORTSC_LSDA) 2779 status |= UPS_LOW_SPEED; 2780 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) { 2781 /* need to do a write back */ 2782 UWRITE2(sc, port, URWMASK(x)); 2783 2784 /* wait 20ms for resume sequence to complete */ 2785 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 2786 2787 /* clear suspend and resume detect */ 2788 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD | 2789 UHCI_PORTSC_SUSP)); 2790 2791 /* wait a little bit */ 2792 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500); 2793 2794 sc->sc_isresumed |= (1 << index); 2795 2796 } else if (x & UHCI_PORTSC_SUSP) { 2797 status |= UPS_SUSPEND; 2798 } 2799 status |= UPS_PORT_POWER; 2800 if (sc->sc_isresumed & (1 << index)) 2801 change |= UPS_C_SUSPEND; 2802 if (sc->sc_isreset) 2803 change |= UPS_C_PORT_RESET; 2804 USETW(sc->sc_hub_desc.ps.wPortStatus, status); 2805 USETW(sc->sc_hub_desc.ps.wPortChange, change); 2806 std->len = sizeof(sc->sc_hub_desc.ps); 2807 break; 2808 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2809 std->err = USB_ERR_IOERROR; 2810 goto done; 2811 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2812 break; 2813 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2814 if (index == 1) 2815 port = UHCI_PORTSC1; 2816 else if (index == 2) 2817 port = UHCI_PORTSC2; 2818 else { 2819 std->err = USB_ERR_IOERROR; 2820 goto done; 2821 } 2822 switch (value) { 2823 case UHF_PORT_ENABLE: 2824 x = URWMASK(UREAD2(sc, port)); 2825 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2826 break; 2827 case UHF_PORT_SUSPEND: 2828 x = URWMASK(UREAD2(sc, port)); 2829 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2830 break; 2831 case UHF_PORT_RESET: 2832 std->err = uhci_portreset(sc, index); 2833 goto done; 2834 case UHF_PORT_POWER: 2835 /* pretend we turned on power */ 2836 std->err = USB_ERR_NORMAL_COMPLETION; 2837 goto done; 2838 case UHF_C_PORT_CONNECTION: 2839 case UHF_C_PORT_ENABLE: 2840 case UHF_C_PORT_OVER_CURRENT: 2841 case UHF_PORT_CONNECTION: 2842 case UHF_PORT_OVER_CURRENT: 2843 case UHF_PORT_LOW_SPEED: 2844 case UHF_C_PORT_SUSPEND: 2845 case UHF_C_PORT_RESET: 2846 default: 2847 std->err = USB_ERR_IOERROR; 2848 goto done; 2849 } 2850 break; 2851 default: 2852 std->err = USB_ERR_IOERROR; 2853 goto done; 2854 } 2855 done: 2856 return; 2857 } 2858 2859 static void 2860 uhci_root_ctrl_poll(struct uhci_softc *sc) 2861 { 2862 usb2_sw_transfer(&sc->sc_root_ctrl, 2863 &uhci_root_ctrl_done); 2864 } 2865 2866 struct usb2_pipe_methods uhci_root_ctrl_methods = 2867 { 2868 .open = uhci_root_ctrl_open, 2869 .close = uhci_root_ctrl_close, 2870 .enter = uhci_root_ctrl_enter, 2871 .start = uhci_root_ctrl_start, 2872 .enter_is_cancelable = 1, 2873 .start_is_cancelable = 0, 2874 }; 2875 2876 /*------------------------------------------------------------------------* 2877 * uhci root interrupt support 2878 *------------------------------------------------------------------------*/ 2879 static void 2880 uhci_root_intr_open(struct usb2_xfer *xfer) 2881 { 2882 return; 2883 } 2884 2885 static void 2886 uhci_root_intr_close(struct usb2_xfer *xfer) 2887 { 2888 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2889 2890 if (sc->sc_root_intr.xfer == xfer) { 2891 sc->sc_root_intr.xfer = NULL; 2892 } 2893 uhci_device_done(xfer, USB_ERR_CANCELLED); 2894 } 2895 2896 static void 2897 uhci_root_intr_enter(struct usb2_xfer *xfer) 2898 { 2899 return; 2900 } 2901 2902 static void 2903 uhci_root_intr_start(struct usb2_xfer *xfer) 2904 { 2905 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2906 2907 sc->sc_root_intr.xfer = xfer; 2908 2909 usb2_transfer_timeout_ms(xfer, 2910 &uhci_root_intr_check, xfer->interval); 2911 } 2912 2913 static void 2914 uhci_root_intr_done(struct usb2_xfer *xfer, 2915 struct usb2_sw_transfer *std) 2916 { 2917 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2918 2919 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2920 2921 if (std->state != USB_SW_TR_PRE_DATA) { 2922 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2923 /* transfer is transferred */ 2924 uhci_device_done(xfer, std->err); 2925 } 2926 goto done; 2927 } 2928 /* setup buffer */ 2929 std->ptr = sc->sc_hub_idata; 2930 std->len = sizeof(sc->sc_hub_idata); 2931 done: 2932 return; 2933 } 2934 2935 /* 2936 * this routine is executed periodically and simulates interrupts 2937 * from the root controller interrupt pipe for port status change 2938 */ 2939 static void 2940 uhci_root_intr_check(void *arg) 2941 { 2942 struct usb2_xfer *xfer = arg; 2943 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2944 2945 DPRINTFN(21, "\n"); 2946 2947 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2948 2949 sc->sc_hub_idata[0] = 0; 2950 2951 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | 2952 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2953 sc->sc_hub_idata[0] |= 1 << 1; 2954 } 2955 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | 2956 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2957 sc->sc_hub_idata[0] |= 1 << 2; 2958 } 2959 if (sc->sc_hub_idata[0] == 0) { 2960 /* 2961 * no change or controller not running, try again in a while 2962 */ 2963 uhci_root_intr_start(xfer); 2964 } else { 2965 usb2_sw_transfer(&sc->sc_root_intr, 2966 &uhci_root_intr_done); 2967 } 2968 } 2969 2970 struct usb2_pipe_methods uhci_root_intr_methods = 2971 { 2972 .open = uhci_root_intr_open, 2973 .close = uhci_root_intr_close, 2974 .enter = uhci_root_intr_enter, 2975 .start = uhci_root_intr_start, 2976 .enter_is_cancelable = 1, 2977 .start_is_cancelable = 1, 2978 }; 2979 2980 static void 2981 uhci_xfer_setup(struct usb2_setup_params *parm) 2982 { 2983 struct usb2_page_search page_info; 2984 struct usb2_page_cache *pc; 2985 uhci_softc_t *sc; 2986 struct usb2_xfer *xfer; 2987 void *last_obj; 2988 uint32_t ntd; 2989 uint32_t nqh; 2990 uint32_t nfixup; 2991 uint32_t n; 2992 uint16_t align; 2993 2994 sc = UHCI_BUS2SC(parm->udev->bus); 2995 xfer = parm->curr_xfer; 2996 2997 parm->hc_max_packet_size = 0x500; 2998 parm->hc_max_packet_count = 1; 2999 parm->hc_max_frame_size = 0x500; 3000 3001 /* 3002 * compute ntd and nqh 3003 */ 3004 if (parm->methods == &uhci_device_ctrl_methods) { 3005 xfer->flags_int.bdma_enable = 1; 3006 xfer->flags_int.bdma_no_post_sync = 1; 3007 3008 usb2_transfer_setup_sub(parm); 3009 3010 /* see EHCI HC driver for proof of "ntd" formula */ 3011 3012 nqh = 1; 3013 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3014 + (xfer->max_data_length / xfer->max_frame_size)); 3015 3016 } else if (parm->methods == &uhci_device_bulk_methods) { 3017 xfer->flags_int.bdma_enable = 1; 3018 xfer->flags_int.bdma_no_post_sync = 1; 3019 3020 usb2_transfer_setup_sub(parm); 3021 3022 nqh = 1; 3023 ntd = ((2 * xfer->nframes) 3024 + (xfer->max_data_length / xfer->max_frame_size)); 3025 3026 } else if (parm->methods == &uhci_device_intr_methods) { 3027 xfer->flags_int.bdma_enable = 1; 3028 xfer->flags_int.bdma_no_post_sync = 1; 3029 3030 usb2_transfer_setup_sub(parm); 3031 3032 nqh = 1; 3033 ntd = ((2 * xfer->nframes) 3034 + (xfer->max_data_length / xfer->max_frame_size)); 3035 3036 } else if (parm->methods == &uhci_device_isoc_methods) { 3037 xfer->flags_int.bdma_enable = 1; 3038 xfer->flags_int.bdma_no_post_sync = 1; 3039 3040 usb2_transfer_setup_sub(parm); 3041 3042 nqh = 0; 3043 ntd = xfer->nframes; 3044 3045 } else { 3046 3047 usb2_transfer_setup_sub(parm); 3048 3049 nqh = 0; 3050 ntd = 0; 3051 } 3052 3053 if (parm->err) { 3054 return; 3055 } 3056 /* 3057 * NOTE: the UHCI controller requires that 3058 * every packet must be contiguous on 3059 * the same USB memory page ! 3060 */ 3061 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1; 3062 3063 /* 3064 * Compute a suitable power of two alignment 3065 * for our "max_frame_size" fixup buffer(s): 3066 */ 3067 align = xfer->max_frame_size; 3068 n = 0; 3069 while (align) { 3070 align >>= 1; 3071 n++; 3072 } 3073 3074 /* check for power of two */ 3075 if (!(xfer->max_frame_size & 3076 (xfer->max_frame_size - 1))) { 3077 n--; 3078 } 3079 /* 3080 * We don't allow alignments of 3081 * less than 8 bytes: 3082 * 3083 * NOTE: Allocating using an aligment 3084 * of 1 byte has special meaning! 3085 */ 3086 if (n < 3) { 3087 n = 3; 3088 } 3089 align = (1 << n); 3090 3091 if (usb2_transfer_setup_sub_malloc( 3092 parm, &pc, xfer->max_frame_size, 3093 align, nfixup)) { 3094 parm->err = USB_ERR_NOMEM; 3095 return; 3096 } 3097 xfer->buf_fixup = pc; 3098 3099 alloc_dma_set: 3100 3101 if (parm->err) { 3102 return; 3103 } 3104 last_obj = NULL; 3105 3106 if (usb2_transfer_setup_sub_malloc( 3107 parm, &pc, sizeof(uhci_td_t), 3108 UHCI_TD_ALIGN, ntd)) { 3109 parm->err = USB_ERR_NOMEM; 3110 return; 3111 } 3112 if (parm->buf) { 3113 for (n = 0; n != ntd; n++) { 3114 uhci_td_t *td; 3115 3116 usb2_get_page(pc + n, 0, &page_info); 3117 3118 td = page_info.buffer; 3119 3120 /* init TD */ 3121 if ((parm->methods == &uhci_device_bulk_methods) || 3122 (parm->methods == &uhci_device_ctrl_methods) || 3123 (parm->methods == &uhci_device_intr_methods)) { 3124 /* set depth first bit */ 3125 td->td_self = htole32(page_info.physaddr | 3126 UHCI_PTR_TD | UHCI_PTR_VF); 3127 } else { 3128 td->td_self = htole32(page_info.physaddr | 3129 UHCI_PTR_TD); 3130 } 3131 3132 td->obj_next = last_obj; 3133 td->page_cache = pc + n; 3134 3135 last_obj = td; 3136 3137 usb2_pc_cpu_flush(pc + n); 3138 } 3139 } 3140 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3141 3142 last_obj = NULL; 3143 3144 if (usb2_transfer_setup_sub_malloc( 3145 parm, &pc, sizeof(uhci_qh_t), 3146 UHCI_QH_ALIGN, nqh)) { 3147 parm->err = USB_ERR_NOMEM; 3148 return; 3149 } 3150 if (parm->buf) { 3151 for (n = 0; n != nqh; n++) { 3152 uhci_qh_t *qh; 3153 3154 usb2_get_page(pc + n, 0, &page_info); 3155 3156 qh = page_info.buffer; 3157 3158 /* init QH */ 3159 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH); 3160 qh->obj_next = last_obj; 3161 qh->page_cache = pc + n; 3162 3163 last_obj = qh; 3164 3165 usb2_pc_cpu_flush(pc + n); 3166 } 3167 } 3168 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3169 3170 if (!xfer->flags_int.curr_dma_set) { 3171 xfer->flags_int.curr_dma_set = 1; 3172 goto alloc_dma_set; 3173 } 3174 } 3175 3176 static void 3177 uhci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 3178 struct usb2_pipe *pipe) 3179 { 3180 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 3181 3182 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3183 pipe, udev->address, 3184 edesc->bEndpointAddress, udev->flags.usb2_mode, 3185 sc->sc_addr); 3186 3187 if (udev->flags.usb2_mode != USB_MODE_HOST) { 3188 /* not supported */ 3189 return; 3190 } 3191 if (udev->device_index == sc->sc_addr) { 3192 switch (edesc->bEndpointAddress) { 3193 case USB_CONTROL_ENDPOINT: 3194 pipe->methods = &uhci_root_ctrl_methods; 3195 break; 3196 case UE_DIR_IN | UHCI_INTR_ENDPT: 3197 pipe->methods = &uhci_root_intr_methods; 3198 break; 3199 default: 3200 /* do nothing */ 3201 break; 3202 } 3203 } else { 3204 switch (edesc->bmAttributes & UE_XFERTYPE) { 3205 case UE_CONTROL: 3206 pipe->methods = &uhci_device_ctrl_methods; 3207 break; 3208 case UE_INTERRUPT: 3209 pipe->methods = &uhci_device_intr_methods; 3210 break; 3211 case UE_ISOCHRONOUS: 3212 if (udev->speed == USB_SPEED_FULL) { 3213 pipe->methods = &uhci_device_isoc_methods; 3214 } 3215 break; 3216 case UE_BULK: 3217 if (udev->speed != USB_SPEED_LOW) { 3218 pipe->methods = &uhci_device_bulk_methods; 3219 } 3220 break; 3221 default: 3222 /* do nothing */ 3223 break; 3224 } 3225 } 3226 } 3227 3228 static void 3229 uhci_xfer_unsetup(struct usb2_xfer *xfer) 3230 { 3231 return; 3232 } 3233 3234 static void 3235 uhci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 3236 { 3237 /* 3238 * Wait until hardware has finished any possible use of the 3239 * transfer descriptor(s) and QH 3240 */ 3241 *pus = (1125); /* microseconds */ 3242 } 3243 3244 static void 3245 uhci_device_resume(struct usb2_device *udev) 3246 { 3247 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3248 struct usb2_xfer *xfer; 3249 struct usb2_pipe_methods *methods; 3250 uhci_qh_t *qh; 3251 3252 DPRINTF("\n"); 3253 3254 USB_BUS_LOCK(udev->bus); 3255 3256 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3257 3258 if (xfer->xroot->udev == udev) { 3259 3260 methods = xfer->pipe->methods; 3261 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3262 3263 if (methods == &uhci_device_bulk_methods) { 3264 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 3265 uhci_add_loop(sc); 3266 xfer->flags_int.bandwidth_reclaimed = 1; 3267 } 3268 if (methods == &uhci_device_ctrl_methods) { 3269 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3270 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 3271 } else { 3272 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 3273 } 3274 } 3275 if (methods == &uhci_device_intr_methods) { 3276 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3277 } 3278 } 3279 } 3280 3281 USB_BUS_UNLOCK(udev->bus); 3282 3283 return; 3284 } 3285 3286 static void 3287 uhci_device_suspend(struct usb2_device *udev) 3288 { 3289 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3290 struct usb2_xfer *xfer; 3291 struct usb2_pipe_methods *methods; 3292 uhci_qh_t *qh; 3293 3294 DPRINTF("\n"); 3295 3296 USB_BUS_LOCK(udev->bus); 3297 3298 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3299 3300 if (xfer->xroot->udev == udev) { 3301 3302 methods = xfer->pipe->methods; 3303 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3304 3305 if (xfer->flags_int.bandwidth_reclaimed) { 3306 xfer->flags_int.bandwidth_reclaimed = 0; 3307 uhci_rem_loop(sc); 3308 } 3309 if (methods == &uhci_device_bulk_methods) { 3310 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 3311 } 3312 if (methods == &uhci_device_ctrl_methods) { 3313 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3314 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 3315 } else { 3316 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 3317 } 3318 } 3319 if (methods == &uhci_device_intr_methods) { 3320 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3321 } 3322 } 3323 } 3324 3325 USB_BUS_UNLOCK(udev->bus); 3326 3327 return; 3328 } 3329 3330 static void 3331 uhci_set_hw_power(struct usb2_bus *bus) 3332 { 3333 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3334 uint32_t flags; 3335 3336 DPRINTF("\n"); 3337 3338 USB_BUS_LOCK(bus); 3339 3340 flags = bus->hw_power_state; 3341 3342 /* 3343 * WARNING: Some FULL speed USB devices require periodic SOF 3344 * messages! If any USB devices are connected through the 3345 * UHCI, power save will be disabled! 3346 */ 3347 if (flags & (USB_HW_POWER_CONTROL | 3348 USB_HW_POWER_NON_ROOT_HUB | 3349 USB_HW_POWER_BULK | 3350 USB_HW_POWER_INTERRUPT | 3351 USB_HW_POWER_ISOC)) { 3352 DPRINTF("Some USB transfer is " 3353 "active on %u.\n", 3354 device_get_unit(sc->sc_bus.bdev)); 3355 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 3356 } else { 3357 DPRINTF("Power save on %u.\n", 3358 device_get_unit(sc->sc_bus.bdev)); 3359 UHCICMD(sc, UHCI_CMD_MAXP); 3360 } 3361 3362 USB_BUS_UNLOCK(bus); 3363 3364 return; 3365 } 3366 3367 3368 struct usb2_bus_methods uhci_bus_methods = 3369 { 3370 .pipe_init = uhci_pipe_init, 3371 .xfer_setup = uhci_xfer_setup, 3372 .xfer_unsetup = uhci_xfer_unsetup, 3373 .get_dma_delay = uhci_get_dma_delay, 3374 .device_resume = uhci_device_resume, 3375 .device_suspend = uhci_device_suspend, 3376 .set_hw_power = uhci_set_hw_power, 3377 .roothub_exec = uhci_root_ctrl_task, 3378 }; 3379