1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * USB Universal Host Controller driver. 33 * Handles e.g. PIIX3 and PIIX4. 34 * 35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 38 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 39 */ 40 41 #include <dev/usb/usb.h> 42 #include <dev/usb/usb_mfunc.h> 43 #include <dev/usb/usb_error.h> 44 #include <dev/usb/usb_defs.h> 45 46 #define USB_DEBUG_VAR uhcidebug 47 48 #include <dev/usb/usb_core.h> 49 #include <dev/usb/usb_debug.h> 50 #include <dev/usb/usb_busdma.h> 51 #include <dev/usb/usb_process.h> 52 #include <dev/usb/usb_sw_transfer.h> 53 #include <dev/usb/usb_transfer.h> 54 #include <dev/usb/usb_device.h> 55 #include <dev/usb/usb_hub.h> 56 #include <dev/usb/usb_util.h> 57 58 #include <dev/usb/usb_controller.h> 59 #include <dev/usb/usb_bus.h> 60 #include <dev/usb/controller/uhci.h> 61 62 #define alt_next next 63 #define UHCI_BUS2SC(bus) ((uhci_softc_t *)(((uint8_t *)(bus)) - \ 64 USB_P2U(&(((uhci_softc_t *)0)->sc_bus)))) 65 66 #if USB_DEBUG 67 static int uhcidebug = 0; 68 static int uhcinoloop = 0; 69 70 SYSCTL_NODE(_hw_usb2, OID_AUTO, uhci, CTLFLAG_RW, 0, "USB uhci"); 71 SYSCTL_INT(_hw_usb2_uhci, OID_AUTO, debug, CTLFLAG_RW, 72 &uhcidebug, 0, "uhci debug level"); 73 SYSCTL_INT(_hw_usb2_uhci, OID_AUTO, loop, CTLFLAG_RW, 74 &uhcinoloop, 0, "uhci noloop"); 75 static void uhci_dumpregs(uhci_softc_t *sc); 76 static void uhci_dump_tds(uhci_td_t *td); 77 78 #endif 79 80 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 81 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 82 #define UWRITE1(sc, r, x) \ 83 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 84 } while (/*CONSTCOND*/0) 85 #define UWRITE2(sc, r, x) \ 86 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 87 } while (/*CONSTCOND*/0) 88 #define UWRITE4(sc, r, x) \ 89 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 90 } while (/*CONSTCOND*/0) 91 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 92 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 93 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 94 95 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 96 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 97 98 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 99 100 #define UHCI_INTR_ENDPT 1 101 102 struct uhci_mem_layout { 103 104 struct usb2_page_search buf_res; 105 struct usb2_page_search fix_res; 106 107 struct usb2_page_cache *buf_pc; 108 struct usb2_page_cache *fix_pc; 109 110 uint32_t buf_offset; 111 112 uint16_t max_frame_size; 113 }; 114 115 struct uhci_std_temp { 116 117 struct uhci_mem_layout ml; 118 uhci_td_t *td; 119 uhci_td_t *td_next; 120 uint32_t average; 121 uint32_t td_status; 122 uint32_t td_token; 123 uint32_t len; 124 uint16_t max_frame_size; 125 uint8_t shortpkt; 126 uint8_t setup_alt_next; 127 uint8_t short_frames_ok; 128 }; 129 130 extern struct usb2_bus_methods uhci_bus_methods; 131 extern struct usb2_pipe_methods uhci_device_bulk_methods; 132 extern struct usb2_pipe_methods uhci_device_ctrl_methods; 133 extern struct usb2_pipe_methods uhci_device_intr_methods; 134 extern struct usb2_pipe_methods uhci_device_isoc_methods; 135 extern struct usb2_pipe_methods uhci_root_ctrl_methods; 136 extern struct usb2_pipe_methods uhci_root_intr_methods; 137 138 static void uhci_root_ctrl_poll(struct uhci_softc *); 139 static void uhci_do_poll(struct usb2_bus *); 140 static void uhci_device_done(struct usb2_xfer *, usb2_error_t); 141 static void uhci_transfer_intr_enqueue(struct usb2_xfer *); 142 static void uhci_root_intr_check(void *); 143 static void uhci_timeout(void *); 144 static uint8_t uhci_check_transfer(struct usb2_xfer *); 145 146 void 147 uhci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 148 { 149 struct uhci_softc *sc = UHCI_BUS2SC(bus); 150 uint32_t i; 151 152 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 153 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN); 154 155 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg, 156 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 157 158 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg, 159 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 160 161 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 162 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 163 164 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg, 165 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 166 167 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg, 168 sizeof(uhci_td_t), UHCI_TD_ALIGN); 169 170 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) { 171 cb(bus, sc->sc_hw.isoc_start_pc + i, 172 sc->sc_hw.isoc_start_pg + i, 173 sizeof(uhci_td_t), UHCI_TD_ALIGN); 174 } 175 176 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) { 177 cb(bus, sc->sc_hw.intr_start_pc + i, 178 sc->sc_hw.intr_start_pg + i, 179 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 180 } 181 } 182 183 static void 184 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb2_xfer *xfer) 185 { 186 ml->buf_pc = xfer->frbuffers + 0; 187 ml->fix_pc = xfer->buf_fixup; 188 189 ml->buf_offset = 0; 190 191 ml->max_frame_size = xfer->max_frame_size; 192 } 193 194 static void 195 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td) 196 { 197 usb2_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res); 198 199 if (ml->buf_res.length < td->len) { 200 201 /* need to do a fixup */ 202 203 usb2_get_page(ml->fix_pc, 0, &ml->fix_res); 204 205 td->td_buffer = htole32(ml->fix_res.physaddr); 206 207 /* 208 * The UHCI driver cannot handle 209 * page crossings, so a fixup is 210 * needed: 211 * 212 * +----+----+ - - - 213 * | YYY|Y | 214 * +----+----+ - - - 215 * \ \ 216 * \ \ 217 * +----+ 218 * |YYYY| (fixup) 219 * +----+ 220 */ 221 222 if ((td->td_token & htole32(UHCI_TD_PID)) == 223 htole32(UHCI_TD_PID_IN)) { 224 td->fix_pc = ml->fix_pc; 225 usb2_pc_cpu_invalidate(ml->fix_pc); 226 227 } else { 228 td->fix_pc = NULL; 229 230 /* copy data to fixup location */ 231 232 usb2_copy_out(ml->buf_pc, ml->buf_offset, 233 ml->fix_res.buffer, td->len); 234 235 usb2_pc_cpu_flush(ml->fix_pc); 236 } 237 238 /* prepare next fixup */ 239 240 ml->fix_pc++; 241 242 } else { 243 244 td->td_buffer = htole32(ml->buf_res.physaddr); 245 td->fix_pc = NULL; 246 } 247 248 /* prepare next data location */ 249 250 ml->buf_offset += td->len; 251 } 252 253 void 254 uhci_reset(uhci_softc_t *sc) 255 { 256 struct usb2_page_search buf_res; 257 uint16_t n; 258 259 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 260 261 DPRINTF("resetting the HC\n"); 262 263 /* disable interrupts */ 264 265 UWRITE2(sc, UHCI_INTR, 0); 266 267 /* global reset */ 268 269 UHCICMD(sc, UHCI_CMD_GRESET); 270 271 /* wait */ 272 273 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 274 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 275 276 /* terminate all transfers */ 277 278 UHCICMD(sc, UHCI_CMD_HCRESET); 279 280 /* the reset bit goes low when the controller is done */ 281 282 n = UHCI_RESET_TIMEOUT; 283 while (n--) { 284 /* wait one millisecond */ 285 286 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 287 288 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) { 289 goto done_1; 290 } 291 } 292 293 device_printf(sc->sc_bus.bdev, 294 "controller did not reset\n"); 295 296 done_1: 297 298 n = 10; 299 while (n--) { 300 /* wait one millisecond */ 301 302 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 303 304 /* check if HC is stopped */ 305 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 306 goto done_2; 307 } 308 } 309 310 device_printf(sc->sc_bus.bdev, 311 "controller did not stop\n"); 312 313 done_2: 314 315 /* reload the configuration */ 316 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 317 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr); 318 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 319 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 320 } 321 322 static void 323 uhci_start(uhci_softc_t *sc) 324 { 325 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 326 327 DPRINTFN(2, "enabling\n"); 328 329 /* enable interrupts */ 330 331 UWRITE2(sc, UHCI_INTR, 332 (UHCI_INTR_TOCRCIE | 333 UHCI_INTR_RIE | 334 UHCI_INTR_IOCE | 335 UHCI_INTR_SPIE)); 336 337 /* 338 * assume 64 byte packets at frame end and start HC controller 339 */ 340 341 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 342 343 uint8_t n = 10; 344 345 while (n--) { 346 /* wait one millisecond */ 347 348 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 349 350 /* check that controller has started */ 351 352 if (!(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH)) { 353 goto done; 354 } 355 } 356 357 device_printf(sc->sc_bus.bdev, 358 "cannot start HC controller\n"); 359 360 done: 361 return; 362 } 363 364 static struct uhci_qh * 365 uhci_init_qh(struct usb2_page_cache *pc) 366 { 367 struct usb2_page_search buf_res; 368 struct uhci_qh *qh; 369 370 usb2_get_page(pc, 0, &buf_res); 371 372 qh = buf_res.buffer; 373 374 qh->qh_self = 375 htole32(buf_res.physaddr) | 376 htole32(UHCI_PTR_QH); 377 378 qh->page_cache = pc; 379 380 return (qh); 381 } 382 383 static struct uhci_td * 384 uhci_init_td(struct usb2_page_cache *pc) 385 { 386 struct usb2_page_search buf_res; 387 struct uhci_td *td; 388 389 usb2_get_page(pc, 0, &buf_res); 390 391 td = buf_res.buffer; 392 393 td->td_self = 394 htole32(buf_res.physaddr) | 395 htole32(UHCI_PTR_TD); 396 397 td->page_cache = pc; 398 399 return (td); 400 } 401 402 usb2_error_t 403 uhci_init(uhci_softc_t *sc) 404 { 405 uint16_t bit; 406 uint16_t x; 407 uint16_t y; 408 409 DPRINTF("start\n"); 410 411 #if USB_DEBUG 412 if (uhcidebug > 2) { 413 uhci_dumpregs(sc); 414 } 415 #endif 416 417 sc->sc_saved_sof = 0x40; /* default value */ 418 sc->sc_saved_frnum = 0; /* default frame number */ 419 420 /* 421 * Setup QH's 422 */ 423 sc->sc_ls_ctl_p_last = 424 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc); 425 426 sc->sc_fs_ctl_p_last = 427 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc); 428 429 sc->sc_bulk_p_last = 430 uhci_init_qh(&sc->sc_hw.bulk_start_pc); 431 #if 0 432 sc->sc_reclaim_qh_p = 433 sc->sc_fs_ctl_p_last; 434 #else 435 /* setup reclaim looping point */ 436 sc->sc_reclaim_qh_p = 437 sc->sc_bulk_p_last; 438 #endif 439 440 sc->sc_last_qh_p = 441 uhci_init_qh(&sc->sc_hw.last_qh_pc); 442 443 sc->sc_last_td_p = 444 uhci_init_td(&sc->sc_hw.last_td_pc); 445 446 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 447 sc->sc_isoc_p_last[x] = 448 uhci_init_td(sc->sc_hw.isoc_start_pc + x); 449 } 450 451 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) { 452 sc->sc_intr_p_last[x] = 453 uhci_init_qh(sc->sc_hw.intr_start_pc + x); 454 } 455 456 /* 457 * the QHs are arranged to give poll intervals that are 458 * powers of 2 times 1ms 459 */ 460 bit = UHCI_IFRAMELIST_COUNT / 2; 461 while (bit) { 462 x = bit; 463 while (x & bit) { 464 uhci_qh_t *qh_x; 465 uhci_qh_t *qh_y; 466 467 y = (x ^ bit) | (bit / 2); 468 469 /* 470 * the next QH has half the poll interval 471 */ 472 qh_x = sc->sc_intr_p_last[x]; 473 qh_y = sc->sc_intr_p_last[y]; 474 475 qh_x->h_next = NULL; 476 qh_x->qh_h_next = qh_y->qh_self; 477 qh_x->e_next = NULL; 478 qh_x->qh_e_next = htole32(UHCI_PTR_T); 479 x++; 480 } 481 bit >>= 1; 482 } 483 484 if (1) { 485 uhci_qh_t *qh_ls; 486 uhci_qh_t *qh_intr; 487 488 qh_ls = sc->sc_ls_ctl_p_last; 489 qh_intr = sc->sc_intr_p_last[0]; 490 491 /* start QH for interrupt traffic */ 492 qh_intr->h_next = qh_ls; 493 qh_intr->qh_h_next = qh_ls->qh_self; 494 qh_intr->e_next = 0; 495 qh_intr->qh_e_next = htole32(UHCI_PTR_T); 496 } 497 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 498 499 uhci_td_t *td_x; 500 uhci_qh_t *qh_intr; 501 502 td_x = sc->sc_isoc_p_last[x]; 503 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)]; 504 505 /* start TD for isochronous traffic */ 506 td_x->next = NULL; 507 td_x->td_next = qh_intr->qh_self; 508 td_x->td_status = htole32(UHCI_TD_IOS); 509 td_x->td_token = htole32(0); 510 td_x->td_buffer = htole32(0); 511 } 512 513 if (1) { 514 uhci_qh_t *qh_ls; 515 uhci_qh_t *qh_fs; 516 517 qh_ls = sc->sc_ls_ctl_p_last; 518 qh_fs = sc->sc_fs_ctl_p_last; 519 520 /* start QH where low speed control traffic will be queued */ 521 qh_ls->h_next = qh_fs; 522 qh_ls->qh_h_next = qh_fs->qh_self; 523 qh_ls->e_next = 0; 524 qh_ls->qh_e_next = htole32(UHCI_PTR_T); 525 } 526 if (1) { 527 uhci_qh_t *qh_ctl; 528 uhci_qh_t *qh_blk; 529 uhci_qh_t *qh_lst; 530 uhci_td_t *td_lst; 531 532 qh_ctl = sc->sc_fs_ctl_p_last; 533 qh_blk = sc->sc_bulk_p_last; 534 535 /* start QH where full speed control traffic will be queued */ 536 qh_ctl->h_next = qh_blk; 537 qh_ctl->qh_h_next = qh_blk->qh_self; 538 qh_ctl->e_next = 0; 539 qh_ctl->qh_e_next = htole32(UHCI_PTR_T); 540 541 qh_lst = sc->sc_last_qh_p; 542 543 /* start QH where bulk traffic will be queued */ 544 qh_blk->h_next = qh_lst; 545 qh_blk->qh_h_next = qh_lst->qh_self; 546 qh_blk->e_next = 0; 547 qh_blk->qh_e_next = htole32(UHCI_PTR_T); 548 549 td_lst = sc->sc_last_td_p; 550 551 /* end QH which is used for looping the QHs */ 552 qh_lst->h_next = 0; 553 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */ 554 qh_lst->e_next = td_lst; 555 qh_lst->qh_e_next = td_lst->td_self; 556 557 /* 558 * end TD which hangs from the last QH, to avoid a bug in the PIIX 559 * that makes it run berserk otherwise 560 */ 561 td_lst->next = 0; 562 td_lst->td_next = htole32(UHCI_PTR_T); 563 td_lst->td_status = htole32(0); /* inactive */ 564 td_lst->td_token = htole32(0); 565 td_lst->td_buffer = htole32(0); 566 } 567 if (1) { 568 struct usb2_page_search buf_res; 569 uint32_t *pframes; 570 571 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 572 573 pframes = buf_res.buffer; 574 575 576 /* 577 * Setup UHCI framelist 578 * 579 * Execution order: 580 * 581 * pframes -> full speed isochronous -> interrupt QH's -> low 582 * speed control -> full speed control -> bulk transfers 583 * 584 */ 585 586 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) { 587 pframes[x] = 588 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self; 589 } 590 } 591 /* flush all cache into memory */ 592 593 usb2_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc); 594 595 /* set up the bus struct */ 596 sc->sc_bus.methods = &uhci_bus_methods; 597 598 USB_BUS_LOCK(&sc->sc_bus); 599 /* reset the controller */ 600 uhci_reset(sc); 601 602 /* start the controller */ 603 uhci_start(sc); 604 USB_BUS_UNLOCK(&sc->sc_bus); 605 606 /* catch lost interrupts */ 607 uhci_do_poll(&sc->sc_bus); 608 609 return (0); 610 } 611 612 /* NOTE: suspend/resume is called from 613 * interrupt context and cannot sleep! 614 */ 615 616 void 617 uhci_suspend(uhci_softc_t *sc) 618 { 619 USB_BUS_LOCK(&sc->sc_bus); 620 621 #if USB_DEBUG 622 if (uhcidebug > 2) { 623 uhci_dumpregs(sc); 624 } 625 #endif 626 /* save some state if BIOS doesn't */ 627 628 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 629 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 630 631 /* stop the controller */ 632 633 uhci_reset(sc); 634 635 /* enter global suspend */ 636 637 UHCICMD(sc, UHCI_CMD_EGSM); 638 639 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 640 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 641 642 USB_BUS_UNLOCK(&sc->sc_bus); 643 } 644 645 void 646 uhci_resume(uhci_softc_t *sc) 647 { 648 USB_BUS_LOCK(&sc->sc_bus); 649 650 /* reset the controller */ 651 652 uhci_reset(sc); 653 654 /* force global resume */ 655 656 UHCICMD(sc, UHCI_CMD_FGR); 657 658 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 659 USB_MS_TO_TICKS(USB_RESUME_DELAY)); 660 661 /* and start traffic again */ 662 663 uhci_start(sc); 664 665 #if USB_DEBUG 666 if (uhcidebug > 2) { 667 uhci_dumpregs(sc); 668 } 669 #endif 670 671 USB_BUS_UNLOCK(&sc->sc_bus); 672 673 /* catch lost interrupts */ 674 uhci_do_poll(&sc->sc_bus); 675 } 676 677 #if USB_DEBUG 678 static void 679 uhci_dumpregs(uhci_softc_t *sc) 680 { 681 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 682 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 683 device_get_nameunit(sc->sc_bus.bdev), 684 UREAD2(sc, UHCI_CMD), 685 UREAD2(sc, UHCI_STS), 686 UREAD2(sc, UHCI_INTR), 687 UREAD2(sc, UHCI_FRNUM), 688 UREAD4(sc, UHCI_FLBASEADDR), 689 UREAD1(sc, UHCI_SOF), 690 UREAD2(sc, UHCI_PORTSC1), 691 UREAD2(sc, UHCI_PORTSC2)); 692 } 693 694 static uint8_t 695 uhci_dump_td(uhci_td_t *p) 696 { 697 uint32_t td_next; 698 uint32_t td_status; 699 uint32_t td_token; 700 uint8_t temp; 701 702 usb2_pc_cpu_invalidate(p->page_cache); 703 704 td_next = le32toh(p->td_next); 705 td_status = le32toh(p->td_status); 706 td_token = le32toh(p->td_token); 707 708 /* 709 * Check whether the link pointer in this TD marks the link pointer 710 * as end of queue: 711 */ 712 temp = ((td_next & UHCI_PTR_T) || (td_next == 0)); 713 714 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x " 715 "token=0x%08x buffer=0x%08x\n", 716 p, 717 le32toh(p->td_self), 718 td_next, 719 td_status, 720 td_token, 721 le32toh(p->td_buffer)); 722 723 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x," 724 "addr=%d,endpt=%d,D=%d,maxlen=%d\n", 725 p, 726 (td_next & 1) ? "-T" : "", 727 (td_next & 2) ? "-Q" : "", 728 (td_next & 4) ? "-VF" : "", 729 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "", 730 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "", 731 (td_status & UHCI_TD_NAK) ? "-NAK" : "", 732 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "", 733 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "", 734 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "", 735 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "", 736 (td_status & UHCI_TD_IOC) ? "-IOC" : "", 737 (td_status & UHCI_TD_IOS) ? "-IOS" : "", 738 (td_status & UHCI_TD_LS) ? "-LS" : "", 739 (td_status & UHCI_TD_SPD) ? "-SPD" : "", 740 UHCI_TD_GET_ERRCNT(td_status), 741 UHCI_TD_GET_ACTLEN(td_status), 742 UHCI_TD_GET_PID(td_token), 743 UHCI_TD_GET_DEVADDR(td_token), 744 UHCI_TD_GET_ENDPT(td_token), 745 UHCI_TD_GET_DT(td_token), 746 UHCI_TD_GET_MAXLEN(td_token)); 747 748 return (temp); 749 } 750 751 static uint8_t 752 uhci_dump_qh(uhci_qh_t *sqh) 753 { 754 uint8_t temp; 755 uint32_t qh_h_next; 756 uint32_t qh_e_next; 757 758 usb2_pc_cpu_invalidate(sqh->page_cache); 759 760 qh_h_next = le32toh(sqh->qh_h_next); 761 qh_e_next = le32toh(sqh->qh_e_next); 762 763 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh, 764 le32toh(sqh->qh_self), qh_h_next, qh_e_next); 765 766 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) | 767 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0)); 768 769 return (temp); 770 } 771 772 static void 773 uhci_dump_all(uhci_softc_t *sc) 774 { 775 uhci_dumpregs(sc); 776 uhci_dump_qh(sc->sc_ls_ctl_p_last); 777 uhci_dump_qh(sc->sc_fs_ctl_p_last); 778 uhci_dump_qh(sc->sc_bulk_p_last); 779 uhci_dump_qh(sc->sc_last_qh_p); 780 } 781 782 static void 783 uhci_dump_qhs(uhci_qh_t *sqh) 784 { 785 uint8_t temp; 786 787 temp = uhci_dump_qh(sqh); 788 789 /* 790 * uhci_dump_qhs displays all the QHs and TDs from the given QH 791 * onwards Traverses sideways first, then down. 792 * 793 * QH1 QH2 No QH TD2.1 TD2.2 TD1.1 etc. 794 * 795 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 796 */ 797 798 if (temp & 1) 799 uhci_dump_qhs(sqh->h_next); 800 else 801 DPRINTF("No QH\n"); 802 803 if (temp & 2) 804 uhci_dump_tds(sqh->e_next); 805 else 806 DPRINTF("No TD\n"); 807 } 808 809 static void 810 uhci_dump_tds(uhci_td_t *td) 811 { 812 for (; 813 td != NULL; 814 td = td->obj_next) { 815 if (uhci_dump_td(td)) { 816 break; 817 } 818 } 819 } 820 821 #endif 822 823 /* 824 * Let the last QH loop back to the full speed control transfer QH. 825 * This is what intel calls "bandwidth reclamation" and improves 826 * USB performance a lot for some devices. 827 * If we are already looping, just count it. 828 */ 829 static void 830 uhci_add_loop(uhci_softc_t *sc) 831 { 832 struct uhci_qh *qh_lst; 833 struct uhci_qh *qh_rec; 834 835 #if USB_DEBUG 836 if (uhcinoloop) { 837 return; 838 } 839 #endif 840 if (++(sc->sc_loops) == 1) { 841 DPRINTFN(6, "add\n"); 842 843 qh_lst = sc->sc_last_qh_p; 844 qh_rec = sc->sc_reclaim_qh_p; 845 846 /* NOTE: we don't loop back the soft pointer */ 847 848 qh_lst->qh_h_next = qh_rec->qh_self; 849 usb2_pc_cpu_flush(qh_lst->page_cache); 850 } 851 } 852 853 static void 854 uhci_rem_loop(uhci_softc_t *sc) 855 { 856 struct uhci_qh *qh_lst; 857 858 #if USB_DEBUG 859 if (uhcinoloop) { 860 return; 861 } 862 #endif 863 if (--(sc->sc_loops) == 0) { 864 DPRINTFN(6, "remove\n"); 865 866 qh_lst = sc->sc_last_qh_p; 867 qh_lst->qh_h_next = htole32(UHCI_PTR_T); 868 usb2_pc_cpu_flush(qh_lst->page_cache); 869 } 870 } 871 872 static void 873 uhci_transfer_intr_enqueue(struct usb2_xfer *xfer) 874 { 875 /* check for early completion */ 876 if (uhci_check_transfer(xfer)) { 877 return; 878 } 879 /* put transfer on interrupt queue */ 880 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 881 882 /* start timeout, if any */ 883 if (xfer->timeout != 0) { 884 usb2_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout); 885 } 886 } 887 888 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last) 889 static uhci_td_t * 890 _uhci_append_td(uhci_td_t *std, uhci_td_t *last) 891 { 892 DPRINTFN(11, "%p to %p\n", std, last); 893 894 /* (sc->sc_bus.mtx) must be locked */ 895 896 std->next = last->next; 897 std->td_next = last->td_next; 898 899 std->prev = last; 900 901 usb2_pc_cpu_flush(std->page_cache); 902 903 /* 904 * the last->next->prev is never followed: std->next->prev = std; 905 */ 906 last->next = std; 907 last->td_next = std->td_self; 908 909 usb2_pc_cpu_flush(last->page_cache); 910 911 return (std); 912 } 913 914 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last) 915 static uhci_qh_t * 916 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last) 917 { 918 DPRINTFN(11, "%p to %p\n", sqh, last); 919 920 if (sqh->h_prev != NULL) { 921 /* should not happen */ 922 DPRINTFN(0, "QH already linked!\n"); 923 return (last); 924 } 925 /* (sc->sc_bus.mtx) must be locked */ 926 927 sqh->h_next = last->h_next; 928 sqh->qh_h_next = last->qh_h_next; 929 930 sqh->h_prev = last; 931 932 usb2_pc_cpu_flush(sqh->page_cache); 933 934 /* 935 * The "last->h_next->h_prev" is never followed: 936 * 937 * "sqh->h_next->h_prev" = sqh; 938 */ 939 940 last->h_next = sqh; 941 last->qh_h_next = sqh->qh_self; 942 943 usb2_pc_cpu_flush(last->page_cache); 944 945 return (sqh); 946 } 947 948 /**/ 949 950 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last) 951 static uhci_td_t * 952 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last) 953 { 954 DPRINTFN(11, "%p from %p\n", std, last); 955 956 /* (sc->sc_bus.mtx) must be locked */ 957 958 std->prev->next = std->next; 959 std->prev->td_next = std->td_next; 960 961 usb2_pc_cpu_flush(std->prev->page_cache); 962 963 if (std->next) { 964 std->next->prev = std->prev; 965 usb2_pc_cpu_flush(std->next->page_cache); 966 } 967 return ((last == std) ? std->prev : last); 968 } 969 970 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last) 971 static uhci_qh_t * 972 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last) 973 { 974 DPRINTFN(11, "%p from %p\n", sqh, last); 975 976 /* (sc->sc_bus.mtx) must be locked */ 977 978 /* only remove if not removed from a queue */ 979 if (sqh->h_prev) { 980 981 sqh->h_prev->h_next = sqh->h_next; 982 sqh->h_prev->qh_h_next = sqh->qh_h_next; 983 984 usb2_pc_cpu_flush(sqh->h_prev->page_cache); 985 986 if (sqh->h_next) { 987 sqh->h_next->h_prev = sqh->h_prev; 988 usb2_pc_cpu_flush(sqh->h_next->page_cache); 989 } 990 last = ((last == sqh) ? sqh->h_prev : last); 991 992 sqh->h_prev = 0; 993 994 usb2_pc_cpu_flush(sqh->page_cache); 995 } 996 return (last); 997 } 998 999 static void 1000 uhci_isoc_done(uhci_softc_t *sc, struct usb2_xfer *xfer) 1001 { 1002 struct usb2_page_search res; 1003 uint32_t nframes = xfer->nframes; 1004 uint32_t status; 1005 uint32_t offset = 0; 1006 uint32_t *plen = xfer->frlengths; 1007 uint16_t len = 0; 1008 uhci_td_t *td = xfer->td_transfer_first; 1009 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos]; 1010 1011 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1012 xfer, xfer->pipe); 1013 1014 /* sync any DMA memory before doing fixups */ 1015 1016 usb2_bdma_post_sync(xfer); 1017 1018 while (nframes--) { 1019 if (td == NULL) { 1020 panic("%s:%d: out of TD's\n", 1021 __FUNCTION__, __LINE__); 1022 } 1023 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 1024 pp_last = &sc->sc_isoc_p_last[0]; 1025 } 1026 #if USB_DEBUG 1027 if (uhcidebug > 5) { 1028 DPRINTF("isoc TD\n"); 1029 uhci_dump_td(td); 1030 } 1031 #endif 1032 usb2_pc_cpu_invalidate(td->page_cache); 1033 status = le32toh(td->td_status); 1034 1035 len = UHCI_TD_GET_ACTLEN(status); 1036 1037 if (len > *plen) { 1038 len = *plen; 1039 } 1040 if (td->fix_pc) { 1041 1042 usb2_get_page(td->fix_pc, 0, &res); 1043 1044 /* copy data from fixup location to real location */ 1045 1046 usb2_pc_cpu_invalidate(td->fix_pc); 1047 1048 usb2_copy_in(xfer->frbuffers, offset, 1049 res.buffer, len); 1050 } 1051 offset += *plen; 1052 1053 *plen = len; 1054 1055 /* remove TD from schedule */ 1056 UHCI_REMOVE_TD(td, *pp_last); 1057 1058 pp_last++; 1059 plen++; 1060 td = td->obj_next; 1061 } 1062 1063 xfer->aframes = xfer->nframes; 1064 } 1065 1066 static usb2_error_t 1067 uhci_non_isoc_done_sub(struct usb2_xfer *xfer) 1068 { 1069 struct usb2_page_search res; 1070 uhci_td_t *td; 1071 uhci_td_t *td_alt_next; 1072 uint32_t status; 1073 uint32_t token; 1074 uint16_t len; 1075 1076 td = xfer->td_transfer_cache; 1077 td_alt_next = td->alt_next; 1078 1079 if (xfer->aframes != xfer->nframes) { 1080 xfer->frlengths[xfer->aframes] = 0; 1081 } 1082 while (1) { 1083 1084 usb2_pc_cpu_invalidate(td->page_cache); 1085 status = le32toh(td->td_status); 1086 token = le32toh(td->td_token); 1087 1088 /* 1089 * Verify the status and add 1090 * up the actual length: 1091 */ 1092 1093 len = UHCI_TD_GET_ACTLEN(status); 1094 if (len > td->len) { 1095 /* should not happen */ 1096 DPRINTF("Invalid status length, " 1097 "0x%04x/0x%04x bytes\n", len, td->len); 1098 status |= UHCI_TD_STALLED; 1099 1100 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) { 1101 1102 if (td->fix_pc) { 1103 1104 usb2_get_page(td->fix_pc, 0, &res); 1105 1106 /* 1107 * copy data from fixup location to real 1108 * location 1109 */ 1110 1111 usb2_pc_cpu_invalidate(td->fix_pc); 1112 1113 usb2_copy_in(xfer->frbuffers + xfer->aframes, 1114 xfer->frlengths[xfer->aframes], res.buffer, len); 1115 } 1116 /* update actual length */ 1117 1118 xfer->frlengths[xfer->aframes] += len; 1119 } 1120 /* Check for last transfer */ 1121 if (((void *)td) == xfer->td_transfer_last) { 1122 td = NULL; 1123 break; 1124 } 1125 if (status & UHCI_TD_STALLED) { 1126 /* the transfer is finished */ 1127 td = NULL; 1128 break; 1129 } 1130 /* Check for short transfer */ 1131 if (len != td->len) { 1132 if (xfer->flags_int.short_frames_ok) { 1133 /* follow alt next */ 1134 td = td->alt_next; 1135 } else { 1136 /* the transfer is finished */ 1137 td = NULL; 1138 } 1139 break; 1140 } 1141 td = td->obj_next; 1142 1143 if (td->alt_next != td_alt_next) { 1144 /* this USB frame is complete */ 1145 break; 1146 } 1147 } 1148 1149 /* update transfer cache */ 1150 1151 xfer->td_transfer_cache = td; 1152 1153 /* update data toggle */ 1154 1155 xfer->pipe->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1; 1156 1157 #if USB_DEBUG 1158 if (status & UHCI_TD_ERROR) { 1159 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x " 1160 "status=%s%s%s%s%s%s%s%s%s%s%s\n", 1161 xfer->address, xfer->endpoint, xfer->aframes, 1162 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "", 1163 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "", 1164 (status & UHCI_TD_NAK) ? "[NAK]" : "", 1165 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "", 1166 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "", 1167 (status & UHCI_TD_STALLED) ? "[STALLED]" : "", 1168 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1169 (status & UHCI_TD_IOC) ? "[IOC]" : "", 1170 (status & UHCI_TD_IOS) ? "[IOS]" : "", 1171 (status & UHCI_TD_LS) ? "[LS]" : "", 1172 (status & UHCI_TD_SPD) ? "[SPD]" : ""); 1173 } 1174 #endif 1175 return (status & UHCI_TD_STALLED) ? 1176 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION; 1177 } 1178 1179 static void 1180 uhci_non_isoc_done(struct usb2_xfer *xfer) 1181 { 1182 usb2_error_t err = 0; 1183 1184 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1185 xfer, xfer->pipe); 1186 1187 #if USB_DEBUG 1188 if (uhcidebug > 10) { 1189 uhci_dump_tds(xfer->td_transfer_first); 1190 } 1191 #endif 1192 1193 /* sync any DMA memory before doing fixups */ 1194 1195 usb2_bdma_post_sync(xfer); 1196 1197 /* reset scanner */ 1198 1199 xfer->td_transfer_cache = xfer->td_transfer_first; 1200 1201 if (xfer->flags_int.control_xfr) { 1202 if (xfer->flags_int.control_hdr) { 1203 1204 err = uhci_non_isoc_done_sub(xfer); 1205 } 1206 xfer->aframes = 1; 1207 1208 if (xfer->td_transfer_cache == NULL) { 1209 goto done; 1210 } 1211 } 1212 while (xfer->aframes != xfer->nframes) { 1213 1214 err = uhci_non_isoc_done_sub(xfer); 1215 xfer->aframes++; 1216 1217 if (xfer->td_transfer_cache == NULL) { 1218 goto done; 1219 } 1220 } 1221 1222 if (xfer->flags_int.control_xfr && 1223 !xfer->flags_int.control_act) { 1224 1225 err = uhci_non_isoc_done_sub(xfer); 1226 } 1227 done: 1228 uhci_device_done(xfer, err); 1229 } 1230 1231 /*------------------------------------------------------------------------* 1232 * uhci_check_transfer_sub 1233 * 1234 * The main purpose of this function is to update the data-toggle 1235 * in case it is wrong. 1236 *------------------------------------------------------------------------*/ 1237 static void 1238 uhci_check_transfer_sub(struct usb2_xfer *xfer) 1239 { 1240 uhci_qh_t *qh; 1241 uhci_td_t *td; 1242 uhci_td_t *td_alt_next; 1243 1244 uint32_t td_token; 1245 uint32_t td_self; 1246 1247 td = xfer->td_transfer_cache; 1248 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1249 1250 td_token = td->obj_next->td_token; 1251 td = td->alt_next; 1252 xfer->td_transfer_cache = td; 1253 td_self = td->td_self; 1254 td_alt_next = td->alt_next; 1255 1256 if ((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1))) { 1257 1258 /* 1259 * The data toggle is wrong and 1260 * we need to switch it ! 1261 */ 1262 1263 while (1) { 1264 1265 td->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1266 usb2_pc_cpu_flush(td->page_cache); 1267 1268 if (td == xfer->td_transfer_last) { 1269 /* last transfer */ 1270 break; 1271 } 1272 td = td->obj_next; 1273 1274 if (td->alt_next != td_alt_next) { 1275 /* next frame */ 1276 break; 1277 } 1278 } 1279 } 1280 /* update the QH */ 1281 qh->qh_e_next = td_self; 1282 usb2_pc_cpu_flush(qh->page_cache); 1283 1284 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1285 } 1286 1287 /*------------------------------------------------------------------------* 1288 * uhci_check_transfer 1289 * 1290 * Return values: 1291 * 0: USB transfer is not finished 1292 * Else: USB transfer is finished 1293 *------------------------------------------------------------------------*/ 1294 static uint8_t 1295 uhci_check_transfer(struct usb2_xfer *xfer) 1296 { 1297 uint32_t status; 1298 uint32_t token; 1299 uhci_td_t *td; 1300 1301 DPRINTFN(16, "xfer=%p checking transfer\n", xfer); 1302 1303 if (xfer->pipe->methods == &uhci_device_isoc_methods) { 1304 /* isochronous transfer */ 1305 1306 td = xfer->td_transfer_last; 1307 1308 usb2_pc_cpu_invalidate(td->page_cache); 1309 status = le32toh(td->td_status); 1310 1311 /* check also if the first is complete */ 1312 1313 td = xfer->td_transfer_first; 1314 1315 usb2_pc_cpu_invalidate(td->page_cache); 1316 status |= le32toh(td->td_status); 1317 1318 if (!(status & UHCI_TD_ACTIVE)) { 1319 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1320 goto transferred; 1321 } 1322 } else { 1323 /* non-isochronous transfer */ 1324 1325 /* 1326 * check whether there is an error somewhere 1327 * in the middle, or whether there was a short 1328 * packet (SPD and not ACTIVE) 1329 */ 1330 td = xfer->td_transfer_cache; 1331 1332 while (1) { 1333 usb2_pc_cpu_invalidate(td->page_cache); 1334 status = le32toh(td->td_status); 1335 token = le32toh(td->td_token); 1336 1337 /* 1338 * if there is an active TD the transfer isn't done 1339 */ 1340 if (status & UHCI_TD_ACTIVE) { 1341 /* update cache */ 1342 xfer->td_transfer_cache = td; 1343 goto done; 1344 } 1345 /* 1346 * last transfer descriptor makes the transfer done 1347 */ 1348 if (((void *)td) == xfer->td_transfer_last) { 1349 break; 1350 } 1351 /* 1352 * any kind of error makes the transfer done 1353 */ 1354 if (status & UHCI_TD_STALLED) { 1355 break; 1356 } 1357 /* 1358 * check if we reached the last packet 1359 * or if there is a short packet: 1360 */ 1361 if ((td->td_next == htole32(UHCI_PTR_T)) || 1362 (UHCI_TD_GET_ACTLEN(status) < td->len)) { 1363 1364 if (xfer->flags_int.short_frames_ok) { 1365 /* follow alt next */ 1366 if (td->alt_next) { 1367 /* update cache */ 1368 xfer->td_transfer_cache = td; 1369 uhci_check_transfer_sub(xfer); 1370 goto done; 1371 } 1372 } 1373 /* transfer is done */ 1374 break; 1375 } 1376 td = td->obj_next; 1377 } 1378 uhci_non_isoc_done(xfer); 1379 goto transferred; 1380 } 1381 1382 done: 1383 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1384 return (0); 1385 1386 transferred: 1387 return (1); 1388 } 1389 1390 static void 1391 uhci_interrupt_poll(uhci_softc_t *sc) 1392 { 1393 struct usb2_xfer *xfer; 1394 1395 repeat: 1396 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1397 /* 1398 * check if transfer is transferred 1399 */ 1400 if (uhci_check_transfer(xfer)) { 1401 /* queue has been modified */ 1402 goto repeat; 1403 } 1404 } 1405 } 1406 1407 /*------------------------------------------------------------------------* 1408 * uhci_interrupt - UHCI interrupt handler 1409 * 1410 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1411 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1412 * is present ! 1413 *------------------------------------------------------------------------*/ 1414 void 1415 uhci_interrupt(uhci_softc_t *sc) 1416 { 1417 uint32_t status; 1418 1419 USB_BUS_LOCK(&sc->sc_bus); 1420 1421 DPRINTFN(16, "real interrupt\n"); 1422 1423 #if USB_DEBUG 1424 if (uhcidebug > 15) { 1425 uhci_dumpregs(sc); 1426 } 1427 #endif 1428 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1429 if (status == 0) { 1430 /* the interrupt was not for us */ 1431 goto done; 1432 } 1433 if (status & (UHCI_STS_RD | UHCI_STS_HSE | 1434 UHCI_STS_HCPE | UHCI_STS_HCH)) { 1435 1436 if (status & UHCI_STS_RD) { 1437 #if USB_DEBUG 1438 printf("%s: resume detect\n", 1439 __FUNCTION__); 1440 #endif 1441 } 1442 if (status & UHCI_STS_HSE) { 1443 printf("%s: host system error\n", 1444 __FUNCTION__); 1445 } 1446 if (status & UHCI_STS_HCPE) { 1447 printf("%s: host controller process error\n", 1448 __FUNCTION__); 1449 } 1450 if (status & UHCI_STS_HCH) { 1451 /* no acknowledge needed */ 1452 DPRINTF("%s: host controller halted\n", 1453 __FUNCTION__); 1454 #if USB_DEBUG 1455 if (uhcidebug > 0) { 1456 uhci_dump_all(sc); 1457 } 1458 #endif 1459 } 1460 } 1461 /* get acknowledge bits */ 1462 status &= (UHCI_STS_USBINT | 1463 UHCI_STS_USBEI | 1464 UHCI_STS_RD | 1465 UHCI_STS_HSE | 1466 UHCI_STS_HCPE); 1467 1468 if (status == 0) { 1469 /* nothing to acknowledge */ 1470 goto done; 1471 } 1472 /* acknowledge interrupts */ 1473 UWRITE2(sc, UHCI_STS, status); 1474 1475 /* poll all the USB transfers */ 1476 uhci_interrupt_poll(sc); 1477 1478 done: 1479 USB_BUS_UNLOCK(&sc->sc_bus); 1480 } 1481 1482 /* 1483 * called when a request does not complete 1484 */ 1485 static void 1486 uhci_timeout(void *arg) 1487 { 1488 struct usb2_xfer *xfer = arg; 1489 1490 DPRINTF("xfer=%p\n", xfer); 1491 1492 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1493 1494 /* transfer is transferred */ 1495 uhci_device_done(xfer, USB_ERR_TIMEOUT); 1496 } 1497 1498 static void 1499 uhci_do_poll(struct usb2_bus *bus) 1500 { 1501 struct uhci_softc *sc = UHCI_BUS2SC(bus); 1502 1503 USB_BUS_LOCK(&sc->sc_bus); 1504 uhci_interrupt_poll(sc); 1505 uhci_root_ctrl_poll(sc); 1506 USB_BUS_UNLOCK(&sc->sc_bus); 1507 } 1508 1509 static void 1510 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp) 1511 { 1512 uhci_td_t *td; 1513 uhci_td_t *td_next; 1514 uhci_td_t *td_alt_next; 1515 uint32_t average; 1516 uint32_t len_old; 1517 uint8_t shortpkt_old; 1518 uint8_t precompute; 1519 1520 td_alt_next = NULL; 1521 shortpkt_old = temp->shortpkt; 1522 len_old = temp->len; 1523 precompute = 1; 1524 1525 /* software is used to detect short incoming transfers */ 1526 1527 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) { 1528 temp->td_status |= htole32(UHCI_TD_SPD); 1529 } else { 1530 temp->td_status &= ~htole32(UHCI_TD_SPD); 1531 } 1532 1533 temp->ml.buf_offset = 0; 1534 1535 restart: 1536 1537 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1538 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average)); 1539 1540 td = temp->td; 1541 td_next = temp->td_next; 1542 1543 while (1) { 1544 1545 if (temp->len == 0) { 1546 1547 if (temp->shortpkt) { 1548 break; 1549 } 1550 /* send a Zero Length Packet, ZLP, last */ 1551 1552 temp->shortpkt = 1; 1553 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0)); 1554 average = 0; 1555 1556 } else { 1557 1558 average = temp->average; 1559 1560 if (temp->len < average) { 1561 temp->shortpkt = 1; 1562 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1563 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len)); 1564 average = temp->len; 1565 } 1566 } 1567 1568 if (td_next == NULL) { 1569 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__); 1570 } 1571 /* get next TD */ 1572 1573 td = td_next; 1574 td_next = td->obj_next; 1575 1576 /* check if we are pre-computing */ 1577 1578 if (precompute) { 1579 1580 /* update remaining length */ 1581 1582 temp->len -= average; 1583 1584 continue; 1585 } 1586 /* fill out current TD */ 1587 1588 td->td_status = temp->td_status; 1589 td->td_token = temp->td_token; 1590 1591 /* update data toggle */ 1592 1593 temp->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1594 1595 if (average == 0) { 1596 1597 td->len = 0; 1598 td->td_buffer = 0; 1599 td->fix_pc = NULL; 1600 1601 } else { 1602 1603 /* update remaining length */ 1604 1605 temp->len -= average; 1606 1607 td->len = average; 1608 1609 /* fill out buffer pointer and do fixup, if any */ 1610 1611 uhci_mem_layout_fixup(&temp->ml, td); 1612 } 1613 1614 td->alt_next = td_alt_next; 1615 1616 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1617 /* we need to receive these frames one by one ! */ 1618 td->td_status |= htole32(UHCI_TD_IOC); 1619 td->td_next = htole32(UHCI_PTR_T); 1620 } else { 1621 if (td_next) { 1622 /* link the current TD with the next one */ 1623 td->td_next = td_next->td_self; 1624 } 1625 } 1626 1627 usb2_pc_cpu_flush(td->page_cache); 1628 } 1629 1630 if (precompute) { 1631 precompute = 0; 1632 1633 /* setup alt next pointer, if any */ 1634 if (temp->short_frames_ok) { 1635 if (temp->setup_alt_next) { 1636 td_alt_next = td_next; 1637 } 1638 } else { 1639 /* we use this field internally */ 1640 td_alt_next = td_next; 1641 } 1642 1643 /* restore */ 1644 temp->shortpkt = shortpkt_old; 1645 temp->len = len_old; 1646 goto restart; 1647 } 1648 temp->td = td; 1649 temp->td_next = td_next; 1650 } 1651 1652 static uhci_td_t * 1653 uhci_setup_standard_chain(struct usb2_xfer *xfer) 1654 { 1655 struct uhci_std_temp temp; 1656 uhci_td_t *td; 1657 uint32_t x; 1658 1659 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1660 xfer->address, UE_GET_ADDR(xfer->endpoint), 1661 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1662 1663 temp.average = xfer->max_frame_size; 1664 temp.max_frame_size = xfer->max_frame_size; 1665 1666 /* toggle the DMA set we are using */ 1667 xfer->flags_int.curr_dma_set ^= 1; 1668 1669 /* get next DMA set */ 1670 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1671 xfer->td_transfer_first = td; 1672 xfer->td_transfer_cache = td; 1673 1674 temp.td = NULL; 1675 temp.td_next = td; 1676 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1677 temp.short_frames_ok = xfer->flags_int.short_frames_ok; 1678 1679 uhci_mem_layout_init(&temp.ml, xfer); 1680 1681 temp.td_status = 1682 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | 1683 UHCI_TD_ACTIVE)); 1684 1685 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1686 temp.td_status |= htole32(UHCI_TD_LS); 1687 } 1688 temp.td_token = 1689 htole32(UHCI_TD_SET_ENDPT(xfer->endpoint) | 1690 UHCI_TD_SET_DEVADDR(xfer->address)); 1691 1692 if (xfer->pipe->toggle_next) { 1693 /* DATA1 is next */ 1694 temp.td_token |= htole32(UHCI_TD_SET_DT(1)); 1695 } 1696 /* check if we should prepend a setup message */ 1697 1698 if (xfer->flags_int.control_xfr) { 1699 1700 if (xfer->flags_int.control_hdr) { 1701 1702 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1703 UHCI_TD_SET_ENDPT(0xF)); 1704 temp.td_token |= htole32(UHCI_TD_PID_SETUP | 1705 UHCI_TD_SET_DT(0)); 1706 1707 temp.len = xfer->frlengths[0]; 1708 temp.ml.buf_pc = xfer->frbuffers + 0; 1709 temp.shortpkt = temp.len ? 1 : 0; 1710 1711 uhci_setup_standard_chain_sub(&temp); 1712 } 1713 x = 1; 1714 } else { 1715 x = 0; 1716 } 1717 1718 while (x != xfer->nframes) { 1719 1720 /* DATA0 / DATA1 message */ 1721 1722 temp.len = xfer->frlengths[x]; 1723 temp.ml.buf_pc = xfer->frbuffers + x; 1724 1725 x++; 1726 1727 if (x == xfer->nframes) { 1728 temp.setup_alt_next = 0; 1729 } 1730 /* 1731 * Keep previous data toggle, 1732 * device address and endpoint number: 1733 */ 1734 1735 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1736 UHCI_TD_SET_ENDPT(0xF) | 1737 UHCI_TD_SET_DT(1)); 1738 1739 if (temp.len == 0) { 1740 1741 /* make sure that we send an USB packet */ 1742 1743 temp.shortpkt = 0; 1744 1745 } else { 1746 1747 /* regular data transfer */ 1748 1749 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1750 } 1751 1752 /* set endpoint direction */ 1753 1754 temp.td_token |= 1755 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 1756 htole32(UHCI_TD_PID_IN) : 1757 htole32(UHCI_TD_PID_OUT); 1758 1759 uhci_setup_standard_chain_sub(&temp); 1760 } 1761 1762 /* check if we should append a status stage */ 1763 1764 if (xfer->flags_int.control_xfr && 1765 !xfer->flags_int.control_act) { 1766 1767 /* 1768 * send a DATA1 message and reverse the current endpoint 1769 * direction 1770 */ 1771 1772 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1773 UHCI_TD_SET_ENDPT(0xF) | 1774 UHCI_TD_SET_DT(1)); 1775 temp.td_token |= 1776 (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) ? 1777 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) : 1778 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1)); 1779 1780 temp.len = 0; 1781 temp.ml.buf_pc = NULL; 1782 temp.shortpkt = 0; 1783 1784 uhci_setup_standard_chain_sub(&temp); 1785 } 1786 td = temp.td; 1787 1788 td->td_next = htole32(UHCI_PTR_T); 1789 1790 /* set interrupt bit */ 1791 1792 td->td_status |= htole32(UHCI_TD_IOC); 1793 1794 usb2_pc_cpu_flush(td->page_cache); 1795 1796 /* must have at least one frame! */ 1797 1798 xfer->td_transfer_last = td; 1799 1800 #if USB_DEBUG 1801 if (uhcidebug > 8) { 1802 DPRINTF("nexttog=%d; data before transfer:\n", 1803 xfer->pipe->toggle_next); 1804 uhci_dump_tds(xfer->td_transfer_first); 1805 } 1806 #endif 1807 return (xfer->td_transfer_first); 1808 } 1809 1810 /* NOTE: "done" can be run two times in a row, 1811 * from close and from interrupt 1812 */ 1813 1814 static void 1815 uhci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1816 { 1817 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1818 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1819 uhci_qh_t *qh; 1820 1821 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1822 1823 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1824 xfer, xfer->pipe, error); 1825 1826 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1827 if (qh) { 1828 usb2_pc_cpu_invalidate(qh->page_cache); 1829 } 1830 if (xfer->flags_int.bandwidth_reclaimed) { 1831 xfer->flags_int.bandwidth_reclaimed = 0; 1832 uhci_rem_loop(sc); 1833 } 1834 if (methods == &uhci_device_bulk_methods) { 1835 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 1836 } 1837 if (methods == &uhci_device_ctrl_methods) { 1838 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1839 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 1840 } else { 1841 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 1842 } 1843 } 1844 if (methods == &uhci_device_intr_methods) { 1845 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 1846 } 1847 /* 1848 * Only finish isochronous transfers once 1849 * which will update "xfer->frlengths". 1850 */ 1851 if (xfer->td_transfer_first && 1852 xfer->td_transfer_last) { 1853 if (methods == &uhci_device_isoc_methods) { 1854 uhci_isoc_done(sc, xfer); 1855 } 1856 xfer->td_transfer_first = NULL; 1857 xfer->td_transfer_last = NULL; 1858 } 1859 /* dequeue transfer and start next transfer */ 1860 usb2_transfer_done(xfer, error); 1861 } 1862 1863 /*------------------------------------------------------------------------* 1864 * uhci bulk support 1865 *------------------------------------------------------------------------*/ 1866 static void 1867 uhci_device_bulk_open(struct usb2_xfer *xfer) 1868 { 1869 return; 1870 } 1871 1872 static void 1873 uhci_device_bulk_close(struct usb2_xfer *xfer) 1874 { 1875 uhci_device_done(xfer, USB_ERR_CANCELLED); 1876 } 1877 1878 static void 1879 uhci_device_bulk_enter(struct usb2_xfer *xfer) 1880 { 1881 return; 1882 } 1883 1884 static void 1885 uhci_device_bulk_start(struct usb2_xfer *xfer) 1886 { 1887 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1888 uhci_td_t *td; 1889 uhci_qh_t *qh; 1890 1891 /* setup TD's */ 1892 td = uhci_setup_standard_chain(xfer); 1893 1894 /* setup QH */ 1895 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1896 1897 qh->e_next = td; 1898 qh->qh_e_next = td->td_self; 1899 1900 if (xfer->xroot->udev->pwr_save.suspended == 0) { 1901 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 1902 uhci_add_loop(sc); 1903 xfer->flags_int.bandwidth_reclaimed = 1; 1904 } else { 1905 usb2_pc_cpu_flush(qh->page_cache); 1906 } 1907 1908 /* put transfer on interrupt queue */ 1909 uhci_transfer_intr_enqueue(xfer); 1910 } 1911 1912 struct usb2_pipe_methods uhci_device_bulk_methods = 1913 { 1914 .open = uhci_device_bulk_open, 1915 .close = uhci_device_bulk_close, 1916 .enter = uhci_device_bulk_enter, 1917 .start = uhci_device_bulk_start, 1918 .enter_is_cancelable = 1, 1919 .start_is_cancelable = 1, 1920 }; 1921 1922 /*------------------------------------------------------------------------* 1923 * uhci control support 1924 *------------------------------------------------------------------------*/ 1925 static void 1926 uhci_device_ctrl_open(struct usb2_xfer *xfer) 1927 { 1928 return; 1929 } 1930 1931 static void 1932 uhci_device_ctrl_close(struct usb2_xfer *xfer) 1933 { 1934 uhci_device_done(xfer, USB_ERR_CANCELLED); 1935 } 1936 1937 static void 1938 uhci_device_ctrl_enter(struct usb2_xfer *xfer) 1939 { 1940 return; 1941 } 1942 1943 static void 1944 uhci_device_ctrl_start(struct usb2_xfer *xfer) 1945 { 1946 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1947 uhci_qh_t *qh; 1948 uhci_td_t *td; 1949 1950 /* setup TD's */ 1951 td = uhci_setup_standard_chain(xfer); 1952 1953 /* setup QH */ 1954 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1955 1956 qh->e_next = td; 1957 qh->qh_e_next = td->td_self; 1958 1959 /* 1960 * NOTE: some devices choke on bandwidth- reclamation for control 1961 * transfers 1962 */ 1963 if (xfer->xroot->udev->pwr_save.suspended == 0) { 1964 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1965 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 1966 } else { 1967 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 1968 } 1969 } else { 1970 usb2_pc_cpu_flush(qh->page_cache); 1971 } 1972 /* put transfer on interrupt queue */ 1973 uhci_transfer_intr_enqueue(xfer); 1974 } 1975 1976 struct usb2_pipe_methods uhci_device_ctrl_methods = 1977 { 1978 .open = uhci_device_ctrl_open, 1979 .close = uhci_device_ctrl_close, 1980 .enter = uhci_device_ctrl_enter, 1981 .start = uhci_device_ctrl_start, 1982 .enter_is_cancelable = 1, 1983 .start_is_cancelable = 1, 1984 }; 1985 1986 /*------------------------------------------------------------------------* 1987 * uhci interrupt support 1988 *------------------------------------------------------------------------*/ 1989 static void 1990 uhci_device_intr_open(struct usb2_xfer *xfer) 1991 { 1992 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1993 uint16_t best; 1994 uint16_t bit; 1995 uint16_t x; 1996 1997 best = 0; 1998 bit = UHCI_IFRAMELIST_COUNT / 2; 1999 while (bit) { 2000 if (xfer->interval >= bit) { 2001 x = bit; 2002 best = bit; 2003 while (x & bit) { 2004 if (sc->sc_intr_stat[x] < 2005 sc->sc_intr_stat[best]) { 2006 best = x; 2007 } 2008 x++; 2009 } 2010 break; 2011 } 2012 bit >>= 1; 2013 } 2014 2015 sc->sc_intr_stat[best]++; 2016 xfer->qh_pos = best; 2017 2018 DPRINTFN(3, "best=%d interval=%d\n", 2019 best, xfer->interval); 2020 } 2021 2022 static void 2023 uhci_device_intr_close(struct usb2_xfer *xfer) 2024 { 2025 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2026 2027 sc->sc_intr_stat[xfer->qh_pos]--; 2028 2029 uhci_device_done(xfer, USB_ERR_CANCELLED); 2030 } 2031 2032 static void 2033 uhci_device_intr_enter(struct usb2_xfer *xfer) 2034 { 2035 return; 2036 } 2037 2038 static void 2039 uhci_device_intr_start(struct usb2_xfer *xfer) 2040 { 2041 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2042 uhci_qh_t *qh; 2043 uhci_td_t *td; 2044 2045 /* setup TD's */ 2046 td = uhci_setup_standard_chain(xfer); 2047 2048 /* setup QH */ 2049 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2050 2051 qh->e_next = td; 2052 qh->qh_e_next = td->td_self; 2053 2054 if (xfer->xroot->udev->pwr_save.suspended == 0) { 2055 2056 /* enter QHs into the controller data structures */ 2057 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 2058 2059 } else { 2060 usb2_pc_cpu_flush(qh->page_cache); 2061 } 2062 2063 /* put transfer on interrupt queue */ 2064 uhci_transfer_intr_enqueue(xfer); 2065 } 2066 2067 struct usb2_pipe_methods uhci_device_intr_methods = 2068 { 2069 .open = uhci_device_intr_open, 2070 .close = uhci_device_intr_close, 2071 .enter = uhci_device_intr_enter, 2072 .start = uhci_device_intr_start, 2073 .enter_is_cancelable = 1, 2074 .start_is_cancelable = 1, 2075 }; 2076 2077 /*------------------------------------------------------------------------* 2078 * uhci isochronous support 2079 *------------------------------------------------------------------------*/ 2080 static void 2081 uhci_device_isoc_open(struct usb2_xfer *xfer) 2082 { 2083 uhci_td_t *td; 2084 uint32_t td_token; 2085 uint8_t ds; 2086 2087 td_token = 2088 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 2089 UHCI_TD_IN(0, xfer->endpoint, xfer->address, 0) : 2090 UHCI_TD_OUT(0, xfer->endpoint, xfer->address, 0); 2091 2092 td_token = htole32(td_token); 2093 2094 /* initialize all TD's */ 2095 2096 for (ds = 0; ds != 2; ds++) { 2097 2098 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2099 2100 /* mark TD as inactive */ 2101 td->td_status = htole32(UHCI_TD_IOS); 2102 td->td_token = td_token; 2103 2104 usb2_pc_cpu_flush(td->page_cache); 2105 } 2106 } 2107 } 2108 2109 static void 2110 uhci_device_isoc_close(struct usb2_xfer *xfer) 2111 { 2112 uhci_device_done(xfer, USB_ERR_CANCELLED); 2113 } 2114 2115 static void 2116 uhci_device_isoc_enter(struct usb2_xfer *xfer) 2117 { 2118 struct uhci_mem_layout ml; 2119 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2120 uint32_t nframes; 2121 uint32_t temp; 2122 uint32_t *plen; 2123 2124 #if USB_DEBUG 2125 uint8_t once = 1; 2126 2127 #endif 2128 uhci_td_t *td; 2129 uhci_td_t *td_last = NULL; 2130 uhci_td_t **pp_last; 2131 2132 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2133 xfer, xfer->pipe->isoc_next, xfer->nframes); 2134 2135 nframes = UREAD2(sc, UHCI_FRNUM); 2136 2137 temp = (nframes - xfer->pipe->isoc_next) & 2138 (UHCI_VFRAMELIST_COUNT - 1); 2139 2140 if ((xfer->pipe->is_synced == 0) || 2141 (temp < xfer->nframes)) { 2142 /* 2143 * If there is data underflow or the pipe queue is empty we 2144 * schedule the transfer a few frames ahead of the current 2145 * frame position. Else two isochronous transfers might 2146 * overlap. 2147 */ 2148 xfer->pipe->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1); 2149 xfer->pipe->is_synced = 1; 2150 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2151 } 2152 /* 2153 * compute how many milliseconds the insertion is ahead of the 2154 * current frame position: 2155 */ 2156 temp = (xfer->pipe->isoc_next - nframes) & 2157 (UHCI_VFRAMELIST_COUNT - 1); 2158 2159 /* 2160 * pre-compute when the isochronous transfer will be finished: 2161 */ 2162 xfer->isoc_time_complete = 2163 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2164 xfer->nframes; 2165 2166 /* get the real number of frames */ 2167 2168 nframes = xfer->nframes; 2169 2170 uhci_mem_layout_init(&ml, xfer); 2171 2172 plen = xfer->frlengths; 2173 2174 /* toggle the DMA set we are using */ 2175 xfer->flags_int.curr_dma_set ^= 1; 2176 2177 /* get next DMA set */ 2178 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2179 xfer->td_transfer_first = td; 2180 2181 pp_last = &sc->sc_isoc_p_last[xfer->pipe->isoc_next]; 2182 2183 /* store starting position */ 2184 2185 xfer->qh_pos = xfer->pipe->isoc_next; 2186 2187 while (nframes--) { 2188 if (td == NULL) { 2189 panic("%s:%d: out of TD's\n", 2190 __FUNCTION__, __LINE__); 2191 } 2192 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 2193 pp_last = &sc->sc_isoc_p_last[0]; 2194 } 2195 if (*plen > xfer->max_frame_size) { 2196 #if USB_DEBUG 2197 if (once) { 2198 once = 0; 2199 printf("%s: frame length(%d) exceeds %d " 2200 "bytes (frame truncated)\n", 2201 __FUNCTION__, *plen, 2202 xfer->max_frame_size); 2203 } 2204 #endif 2205 *plen = xfer->max_frame_size; 2206 } 2207 /* reuse td_token from last transfer */ 2208 2209 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2210 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen)); 2211 2212 td->len = *plen; 2213 2214 if (td->len == 0) { 2215 /* 2216 * Do not call "uhci_mem_layout_fixup()" when the 2217 * length is zero! 2218 */ 2219 td->td_buffer = 0; 2220 td->fix_pc = NULL; 2221 2222 } else { 2223 2224 /* fill out buffer pointer and do fixup, if any */ 2225 2226 uhci_mem_layout_fixup(&ml, td); 2227 2228 } 2229 2230 /* update status */ 2231 if (nframes == 0) { 2232 td->td_status = htole32 2233 (UHCI_TD_ZERO_ACTLEN 2234 (UHCI_TD_SET_ERRCNT(0) | 2235 UHCI_TD_ACTIVE | 2236 UHCI_TD_IOS | 2237 UHCI_TD_IOC)); 2238 } else { 2239 td->td_status = htole32 2240 (UHCI_TD_ZERO_ACTLEN 2241 (UHCI_TD_SET_ERRCNT(0) | 2242 UHCI_TD_ACTIVE | 2243 UHCI_TD_IOS)); 2244 } 2245 2246 usb2_pc_cpu_flush(td->page_cache); 2247 2248 #if USB_DEBUG 2249 if (uhcidebug > 5) { 2250 DPRINTF("TD %d\n", nframes); 2251 uhci_dump_td(td); 2252 } 2253 #endif 2254 /* insert TD into schedule */ 2255 UHCI_APPEND_TD(td, *pp_last); 2256 pp_last++; 2257 2258 plen++; 2259 td_last = td; 2260 td = td->obj_next; 2261 } 2262 2263 xfer->td_transfer_last = td_last; 2264 2265 /* update isoc_next */ 2266 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) & 2267 (UHCI_VFRAMELIST_COUNT - 1); 2268 } 2269 2270 static void 2271 uhci_device_isoc_start(struct usb2_xfer *xfer) 2272 { 2273 /* put transfer on interrupt queue */ 2274 uhci_transfer_intr_enqueue(xfer); 2275 } 2276 2277 struct usb2_pipe_methods uhci_device_isoc_methods = 2278 { 2279 .open = uhci_device_isoc_open, 2280 .close = uhci_device_isoc_close, 2281 .enter = uhci_device_isoc_enter, 2282 .start = uhci_device_isoc_start, 2283 .enter_is_cancelable = 1, 2284 .start_is_cancelable = 1, 2285 }; 2286 2287 /*------------------------------------------------------------------------* 2288 * uhci root control support 2289 *------------------------------------------------------------------------* 2290 * simulate a hardware hub by handling 2291 * all the necessary requests 2292 *------------------------------------------------------------------------*/ 2293 2294 static void 2295 uhci_root_ctrl_open(struct usb2_xfer *xfer) 2296 { 2297 return; 2298 } 2299 2300 static void 2301 uhci_root_ctrl_close(struct usb2_xfer *xfer) 2302 { 2303 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2304 2305 if (sc->sc_root_ctrl.xfer == xfer) { 2306 sc->sc_root_ctrl.xfer = NULL; 2307 } 2308 uhci_device_done(xfer, USB_ERR_CANCELLED); 2309 } 2310 2311 /* data structures and routines 2312 * to emulate the root hub: 2313 */ 2314 2315 static const 2316 struct usb2_device_descriptor uhci_devd = 2317 { 2318 sizeof(struct usb2_device_descriptor), 2319 UDESC_DEVICE, /* type */ 2320 {0x00, 0x01}, /* USB version */ 2321 UDCLASS_HUB, /* class */ 2322 UDSUBCLASS_HUB, /* subclass */ 2323 UDPROTO_FSHUB, /* protocol */ 2324 64, /* max packet */ 2325 {0}, {0}, {0x00, 0x01}, /* device id */ 2326 1, 2, 0, /* string indicies */ 2327 1 /* # of configurations */ 2328 }; 2329 2330 static const struct uhci_config_desc uhci_confd = { 2331 .confd = { 2332 .bLength = sizeof(struct usb2_config_descriptor), 2333 .bDescriptorType = UDESC_CONFIG, 2334 .wTotalLength[0] = sizeof(uhci_confd), 2335 .bNumInterface = 1, 2336 .bConfigurationValue = 1, 2337 .iConfiguration = 0, 2338 .bmAttributes = UC_SELF_POWERED, 2339 .bMaxPower = 0 /* max power */ 2340 }, 2341 2342 .ifcd = { 2343 .bLength = sizeof(struct usb2_interface_descriptor), 2344 .bDescriptorType = UDESC_INTERFACE, 2345 .bNumEndpoints = 1, 2346 .bInterfaceClass = UICLASS_HUB, 2347 .bInterfaceSubClass = UISUBCLASS_HUB, 2348 .bInterfaceProtocol = UIPROTO_FSHUB, 2349 }, 2350 2351 .endpd = { 2352 .bLength = sizeof(struct usb2_endpoint_descriptor), 2353 .bDescriptorType = UDESC_ENDPOINT, 2354 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 2355 .bmAttributes = UE_INTERRUPT, 2356 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2357 .bInterval = 255, 2358 }, 2359 }; 2360 2361 static const 2362 struct usb2_hub_descriptor_min uhci_hubd_piix = 2363 { 2364 sizeof(uhci_hubd_piix), 2365 UDESC_HUB, 2366 2, 2367 {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0}, 2368 50, /* power on to power good */ 2369 0, 2370 {0x00}, /* both ports are removable */ 2371 }; 2372 2373 /* 2374 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 2375 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 2376 * should not be used by the USB subsystem. As we cannot issue a 2377 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 2378 * will be enabled as part of the reset. 2379 * 2380 * On the VT83C572, the port cannot be successfully enabled until the 2381 * outstanding "port enable change" and "connection status change" 2382 * events have been reset. 2383 */ 2384 static usb2_error_t 2385 uhci_portreset(uhci_softc_t *sc, uint16_t index, uint8_t use_polling) 2386 { 2387 uint16_t port; 2388 uint16_t x; 2389 uint8_t lim; 2390 2391 if (index == 1) 2392 port = UHCI_PORTSC1; 2393 else if (index == 2) 2394 port = UHCI_PORTSC2; 2395 else 2396 return (USB_ERR_IOERROR); 2397 2398 /* 2399 * Before we do anything, turn on SOF messages on the USB 2400 * BUS. Some USB devices do not cope without them! 2401 */ 2402 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 2403 2404 DPRINTF("Activating SOFs!\n"); 2405 2406 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 2407 2408 /* wait a little bit */ 2409 if (use_polling) { 2410 DELAY(10000); 2411 } else { 2412 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 2413 } 2414 } 2415 2416 x = URWMASK(UREAD2(sc, port)); 2417 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2418 2419 if (use_polling) { 2420 /* polling */ 2421 DELAY(USB_PORT_ROOT_RESET_DELAY * 1000); 2422 } else { 2423 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2424 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 2425 } 2426 2427 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n", 2428 index, UREAD2(sc, port)); 2429 2430 x = URWMASK(UREAD2(sc, port)); 2431 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2432 2433 2434 mtx_unlock(&sc->sc_bus.bus_mtx); 2435 2436 /* 2437 * This delay needs to be exactly 100us, else some USB devices 2438 * fail to attach! 2439 */ 2440 DELAY(100); 2441 2442 mtx_lock(&sc->sc_bus.bus_mtx); 2443 2444 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n", 2445 index, UREAD2(sc, port)); 2446 2447 x = URWMASK(UREAD2(sc, port)); 2448 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2449 2450 for (lim = 0; lim < 12; lim++) { 2451 2452 if (use_polling) { 2453 /* polling */ 2454 DELAY(USB_PORT_RESET_DELAY * 1000); 2455 } else { 2456 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2457 USB_MS_TO_TICKS(USB_PORT_RESET_DELAY)); 2458 } 2459 2460 x = UREAD2(sc, port); 2461 2462 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n", 2463 index, lim, x); 2464 2465 if (!(x & UHCI_PORTSC_CCS)) { 2466 /* 2467 * No device is connected (or was disconnected 2468 * during reset). Consider the port reset. 2469 * The delay must be long enough to ensure on 2470 * the initial iteration that the device 2471 * connection will have been registered. 50ms 2472 * appears to be sufficient, but 20ms is not. 2473 */ 2474 DPRINTFN(4, "uhci port %d loop %u, device detached\n", 2475 index, lim); 2476 goto done; 2477 } 2478 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 2479 /* 2480 * Port enabled changed and/or connection 2481 * status changed were set. Reset either or 2482 * both raised flags (by writing a 1 to that 2483 * bit), and wait again for state to settle. 2484 */ 2485 UWRITE2(sc, port, URWMASK(x) | 2486 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 2487 continue; 2488 } 2489 if (x & UHCI_PORTSC_PE) { 2490 /* port is enabled */ 2491 goto done; 2492 } 2493 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 2494 } 2495 2496 DPRINTFN(2, "uhci port %d reset timed out\n", index); 2497 return (USB_ERR_TIMEOUT); 2498 2499 done: 2500 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n", 2501 index, UREAD2(sc, port)); 2502 2503 sc->sc_isreset = 1; 2504 return (USB_ERR_NORMAL_COMPLETION); 2505 } 2506 2507 static void 2508 uhci_root_ctrl_enter(struct usb2_xfer *xfer) 2509 { 2510 return; 2511 } 2512 2513 static void 2514 uhci_root_ctrl_start(struct usb2_xfer *xfer) 2515 { 2516 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2517 2518 DPRINTF("\n"); 2519 2520 sc->sc_root_ctrl.xfer = xfer; 2521 2522 usb2_bus_roothub_exec(xfer->xroot->bus); 2523 } 2524 2525 static void 2526 uhci_root_ctrl_task(struct usb2_bus *bus) 2527 { 2528 uhci_root_ctrl_poll(UHCI_BUS2SC(bus)); 2529 } 2530 2531 static void 2532 uhci_root_ctrl_done(struct usb2_xfer *xfer, 2533 struct usb2_sw_transfer *std) 2534 { 2535 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2536 char *ptr; 2537 uint16_t x; 2538 uint16_t port; 2539 uint16_t value; 2540 uint16_t index; 2541 uint16_t status; 2542 uint16_t change; 2543 uint8_t use_polling; 2544 2545 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2546 2547 if (std->state != USB_SW_TR_SETUP) { 2548 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2549 /* transfer transferred */ 2550 uhci_device_done(xfer, std->err); 2551 } 2552 goto done; 2553 } 2554 /* buffer reset */ 2555 std->ptr = sc->sc_hub_desc.temp; 2556 std->len = 0; 2557 2558 value = UGETW(std->req.wValue); 2559 index = UGETW(std->req.wIndex); 2560 2561 use_polling = mtx_owned(xfer->xroot->xfer_mtx) ? 1 : 0; 2562 2563 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2564 "wValue=0x%04x wIndex=0x%04x\n", 2565 std->req.bmRequestType, std->req.bRequest, 2566 UGETW(std->req.wLength), value, index); 2567 2568 #define C(x,y) ((x) | ((y) << 8)) 2569 switch (C(std->req.bRequest, std->req.bmRequestType)) { 2570 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2571 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2572 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2573 /* 2574 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2575 * for the integrated root hub. 2576 */ 2577 break; 2578 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2579 std->len = 1; 2580 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2581 break; 2582 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2583 switch (value >> 8) { 2584 case UDESC_DEVICE: 2585 if ((value & 0xff) != 0) { 2586 std->err = USB_ERR_IOERROR; 2587 goto done; 2588 } 2589 std->len = sizeof(uhci_devd); 2590 sc->sc_hub_desc.devd = uhci_devd; 2591 break; 2592 2593 case UDESC_CONFIG: 2594 if ((value & 0xff) != 0) { 2595 std->err = USB_ERR_IOERROR; 2596 goto done; 2597 } 2598 std->len = sizeof(uhci_confd); 2599 std->ptr = USB_ADD_BYTES(&uhci_confd, 0); 2600 break; 2601 2602 case UDESC_STRING: 2603 switch (value & 0xff) { 2604 case 0: /* Language table */ 2605 ptr = "\001"; 2606 break; 2607 2608 case 1: /* Vendor */ 2609 ptr = sc->sc_vendor; 2610 break; 2611 2612 case 2: /* Product */ 2613 ptr = "UHCI root HUB"; 2614 break; 2615 2616 default: 2617 ptr = ""; 2618 break; 2619 } 2620 2621 std->len = usb2_make_str_desc 2622 (sc->sc_hub_desc.temp, 2623 sizeof(sc->sc_hub_desc.temp), 2624 ptr); 2625 break; 2626 2627 default: 2628 std->err = USB_ERR_IOERROR; 2629 goto done; 2630 } 2631 break; 2632 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2633 std->len = 1; 2634 sc->sc_hub_desc.temp[0] = 0; 2635 break; 2636 case C(UR_GET_STATUS, UT_READ_DEVICE): 2637 std->len = 2; 2638 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2639 break; 2640 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2641 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2642 std->len = 2; 2643 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2644 break; 2645 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2646 if (value >= USB_MAX_DEVICES) { 2647 std->err = USB_ERR_IOERROR; 2648 goto done; 2649 } 2650 sc->sc_addr = value; 2651 break; 2652 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2653 if ((value != 0) && (value != 1)) { 2654 std->err = USB_ERR_IOERROR; 2655 goto done; 2656 } 2657 sc->sc_conf = value; 2658 break; 2659 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2660 break; 2661 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2662 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2663 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2664 std->err = USB_ERR_IOERROR; 2665 goto done; 2666 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2667 break; 2668 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2669 break; 2670 /* Hub requests */ 2671 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2672 break; 2673 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2674 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE " 2675 "port=%d feature=%d\n", 2676 index, value); 2677 if (index == 1) 2678 port = UHCI_PORTSC1; 2679 else if (index == 2) 2680 port = UHCI_PORTSC2; 2681 else { 2682 std->err = USB_ERR_IOERROR; 2683 goto done; 2684 } 2685 switch (value) { 2686 case UHF_PORT_ENABLE: 2687 x = URWMASK(UREAD2(sc, port)); 2688 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2689 break; 2690 case UHF_PORT_SUSPEND: 2691 x = URWMASK(UREAD2(sc, port)); 2692 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP)); 2693 break; 2694 case UHF_PORT_RESET: 2695 x = URWMASK(UREAD2(sc, port)); 2696 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2697 break; 2698 case UHF_C_PORT_CONNECTION: 2699 x = URWMASK(UREAD2(sc, port)); 2700 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2701 break; 2702 case UHF_C_PORT_ENABLE: 2703 x = URWMASK(UREAD2(sc, port)); 2704 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2705 break; 2706 case UHF_C_PORT_OVER_CURRENT: 2707 x = URWMASK(UREAD2(sc, port)); 2708 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2709 break; 2710 case UHF_C_PORT_RESET: 2711 sc->sc_isreset = 0; 2712 std->err = USB_ERR_NORMAL_COMPLETION; 2713 goto done; 2714 case UHF_C_PORT_SUSPEND: 2715 sc->sc_isresumed &= ~(1 << index); 2716 break; 2717 case UHF_PORT_CONNECTION: 2718 case UHF_PORT_OVER_CURRENT: 2719 case UHF_PORT_POWER: 2720 case UHF_PORT_LOW_SPEED: 2721 default: 2722 std->err = USB_ERR_IOERROR; 2723 goto done; 2724 } 2725 break; 2726 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2727 if (index == 1) 2728 port = UHCI_PORTSC1; 2729 else if (index == 2) 2730 port = UHCI_PORTSC2; 2731 else { 2732 std->err = USB_ERR_IOERROR; 2733 goto done; 2734 } 2735 std->len = 1; 2736 sc->sc_hub_desc.temp[0] = 2737 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2738 UHCI_PORTSC_LS_SHIFT); 2739 break; 2740 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2741 if ((value & 0xff) != 0) { 2742 std->err = USB_ERR_IOERROR; 2743 goto done; 2744 } 2745 std->len = sizeof(uhci_hubd_piix); 2746 std->ptr = USB_ADD_BYTES(&uhci_hubd_piix, 0); 2747 break; 2748 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2749 std->len = 16; 2750 bzero(sc->sc_hub_desc.temp, 16); 2751 break; 2752 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2753 if (index == 1) 2754 port = UHCI_PORTSC1; 2755 else if (index == 2) 2756 port = UHCI_PORTSC2; 2757 else { 2758 std->err = USB_ERR_IOERROR; 2759 goto done; 2760 } 2761 x = UREAD2(sc, port); 2762 status = change = 0; 2763 if (x & UHCI_PORTSC_CCS) 2764 status |= UPS_CURRENT_CONNECT_STATUS; 2765 if (x & UHCI_PORTSC_CSC) 2766 change |= UPS_C_CONNECT_STATUS; 2767 if (x & UHCI_PORTSC_PE) 2768 status |= UPS_PORT_ENABLED; 2769 if (x & UHCI_PORTSC_POEDC) 2770 change |= UPS_C_PORT_ENABLED; 2771 if (x & UHCI_PORTSC_OCI) 2772 status |= UPS_OVERCURRENT_INDICATOR; 2773 if (x & UHCI_PORTSC_OCIC) 2774 change |= UPS_C_OVERCURRENT_INDICATOR; 2775 if (x & UHCI_PORTSC_LSDA) 2776 status |= UPS_LOW_SPEED; 2777 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) { 2778 /* need to do a write back */ 2779 UWRITE2(sc, port, URWMASK(x)); 2780 2781 /* wait 20ms for resume sequence to complete */ 2782 if (use_polling) { 2783 /* polling */ 2784 DELAY(20000); 2785 } else { 2786 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 2787 } 2788 2789 /* clear suspend and resume detect */ 2790 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD | 2791 UHCI_PORTSC_SUSP)); 2792 2793 /* wait a little bit */ 2794 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500); 2795 2796 sc->sc_isresumed |= (1 << index); 2797 2798 } else if (x & UHCI_PORTSC_SUSP) { 2799 status |= UPS_SUSPEND; 2800 } 2801 status |= UPS_PORT_POWER; 2802 if (sc->sc_isresumed & (1 << index)) 2803 change |= UPS_C_SUSPEND; 2804 if (sc->sc_isreset) 2805 change |= UPS_C_PORT_RESET; 2806 USETW(sc->sc_hub_desc.ps.wPortStatus, status); 2807 USETW(sc->sc_hub_desc.ps.wPortChange, change); 2808 std->len = sizeof(sc->sc_hub_desc.ps); 2809 break; 2810 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2811 std->err = USB_ERR_IOERROR; 2812 goto done; 2813 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2814 break; 2815 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2816 if (index == 1) 2817 port = UHCI_PORTSC1; 2818 else if (index == 2) 2819 port = UHCI_PORTSC2; 2820 else { 2821 std->err = USB_ERR_IOERROR; 2822 goto done; 2823 } 2824 switch (value) { 2825 case UHF_PORT_ENABLE: 2826 x = URWMASK(UREAD2(sc, port)); 2827 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2828 break; 2829 case UHF_PORT_SUSPEND: 2830 x = URWMASK(UREAD2(sc, port)); 2831 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2832 break; 2833 case UHF_PORT_RESET: 2834 std->err = uhci_portreset(sc, index, use_polling); 2835 goto done; 2836 case UHF_PORT_POWER: 2837 /* pretend we turned on power */ 2838 std->err = USB_ERR_NORMAL_COMPLETION; 2839 goto done; 2840 case UHF_C_PORT_CONNECTION: 2841 case UHF_C_PORT_ENABLE: 2842 case UHF_C_PORT_OVER_CURRENT: 2843 case UHF_PORT_CONNECTION: 2844 case UHF_PORT_OVER_CURRENT: 2845 case UHF_PORT_LOW_SPEED: 2846 case UHF_C_PORT_SUSPEND: 2847 case UHF_C_PORT_RESET: 2848 default: 2849 std->err = USB_ERR_IOERROR; 2850 goto done; 2851 } 2852 break; 2853 default: 2854 std->err = USB_ERR_IOERROR; 2855 goto done; 2856 } 2857 done: 2858 return; 2859 } 2860 2861 static void 2862 uhci_root_ctrl_poll(struct uhci_softc *sc) 2863 { 2864 usb2_sw_transfer(&sc->sc_root_ctrl, 2865 &uhci_root_ctrl_done); 2866 } 2867 2868 struct usb2_pipe_methods uhci_root_ctrl_methods = 2869 { 2870 .open = uhci_root_ctrl_open, 2871 .close = uhci_root_ctrl_close, 2872 .enter = uhci_root_ctrl_enter, 2873 .start = uhci_root_ctrl_start, 2874 .enter_is_cancelable = 1, 2875 .start_is_cancelable = 0, 2876 }; 2877 2878 /*------------------------------------------------------------------------* 2879 * uhci root interrupt support 2880 *------------------------------------------------------------------------*/ 2881 static void 2882 uhci_root_intr_open(struct usb2_xfer *xfer) 2883 { 2884 return; 2885 } 2886 2887 static void 2888 uhci_root_intr_close(struct usb2_xfer *xfer) 2889 { 2890 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2891 2892 if (sc->sc_root_intr.xfer == xfer) { 2893 sc->sc_root_intr.xfer = NULL; 2894 } 2895 uhci_device_done(xfer, USB_ERR_CANCELLED); 2896 } 2897 2898 static void 2899 uhci_root_intr_enter(struct usb2_xfer *xfer) 2900 { 2901 return; 2902 } 2903 2904 static void 2905 uhci_root_intr_start(struct usb2_xfer *xfer) 2906 { 2907 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2908 2909 sc->sc_root_intr.xfer = xfer; 2910 2911 usb2_transfer_timeout_ms(xfer, 2912 &uhci_root_intr_check, xfer->interval); 2913 } 2914 2915 static void 2916 uhci_root_intr_done(struct usb2_xfer *xfer, 2917 struct usb2_sw_transfer *std) 2918 { 2919 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2920 2921 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2922 2923 if (std->state != USB_SW_TR_PRE_DATA) { 2924 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2925 /* transfer is transferred */ 2926 uhci_device_done(xfer, std->err); 2927 } 2928 goto done; 2929 } 2930 /* setup buffer */ 2931 std->ptr = sc->sc_hub_idata; 2932 std->len = sizeof(sc->sc_hub_idata); 2933 done: 2934 return; 2935 } 2936 2937 /* 2938 * this routine is executed periodically and simulates interrupts 2939 * from the root controller interrupt pipe for port status change 2940 */ 2941 static void 2942 uhci_root_intr_check(void *arg) 2943 { 2944 struct usb2_xfer *xfer = arg; 2945 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2946 2947 DPRINTFN(21, "\n"); 2948 2949 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2950 2951 sc->sc_hub_idata[0] = 0; 2952 2953 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | 2954 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2955 sc->sc_hub_idata[0] |= 1 << 1; 2956 } 2957 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | 2958 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2959 sc->sc_hub_idata[0] |= 1 << 2; 2960 } 2961 if (sc->sc_hub_idata[0] == 0) { 2962 /* 2963 * no change or controller not running, try again in a while 2964 */ 2965 uhci_root_intr_start(xfer); 2966 } else { 2967 usb2_sw_transfer(&sc->sc_root_intr, 2968 &uhci_root_intr_done); 2969 } 2970 } 2971 2972 struct usb2_pipe_methods uhci_root_intr_methods = 2973 { 2974 .open = uhci_root_intr_open, 2975 .close = uhci_root_intr_close, 2976 .enter = uhci_root_intr_enter, 2977 .start = uhci_root_intr_start, 2978 .enter_is_cancelable = 1, 2979 .start_is_cancelable = 1, 2980 }; 2981 2982 static void 2983 uhci_xfer_setup(struct usb2_setup_params *parm) 2984 { 2985 struct usb2_page_search page_info; 2986 struct usb2_page_cache *pc; 2987 uhci_softc_t *sc; 2988 struct usb2_xfer *xfer; 2989 void *last_obj; 2990 uint32_t ntd; 2991 uint32_t nqh; 2992 uint32_t nfixup; 2993 uint32_t n; 2994 uint16_t align; 2995 2996 sc = UHCI_BUS2SC(parm->udev->bus); 2997 xfer = parm->curr_xfer; 2998 2999 parm->hc_max_packet_size = 0x500; 3000 parm->hc_max_packet_count = 1; 3001 parm->hc_max_frame_size = 0x500; 3002 3003 /* 3004 * compute ntd and nqh 3005 */ 3006 if (parm->methods == &uhci_device_ctrl_methods) { 3007 xfer->flags_int.bdma_enable = 1; 3008 xfer->flags_int.bdma_no_post_sync = 1; 3009 3010 usb2_transfer_setup_sub(parm); 3011 3012 /* see EHCI HC driver for proof of "ntd" formula */ 3013 3014 nqh = 1; 3015 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3016 + (xfer->max_data_length / xfer->max_frame_size)); 3017 3018 } else if (parm->methods == &uhci_device_bulk_methods) { 3019 xfer->flags_int.bdma_enable = 1; 3020 xfer->flags_int.bdma_no_post_sync = 1; 3021 3022 usb2_transfer_setup_sub(parm); 3023 3024 nqh = 1; 3025 ntd = ((2 * xfer->nframes) 3026 + (xfer->max_data_length / xfer->max_frame_size)); 3027 3028 } else if (parm->methods == &uhci_device_intr_methods) { 3029 xfer->flags_int.bdma_enable = 1; 3030 xfer->flags_int.bdma_no_post_sync = 1; 3031 3032 usb2_transfer_setup_sub(parm); 3033 3034 nqh = 1; 3035 ntd = ((2 * xfer->nframes) 3036 + (xfer->max_data_length / xfer->max_frame_size)); 3037 3038 } else if (parm->methods == &uhci_device_isoc_methods) { 3039 xfer->flags_int.bdma_enable = 1; 3040 xfer->flags_int.bdma_no_post_sync = 1; 3041 3042 usb2_transfer_setup_sub(parm); 3043 3044 nqh = 0; 3045 ntd = xfer->nframes; 3046 3047 } else { 3048 3049 usb2_transfer_setup_sub(parm); 3050 3051 nqh = 0; 3052 ntd = 0; 3053 } 3054 3055 if (parm->err) { 3056 return; 3057 } 3058 /* 3059 * NOTE: the UHCI controller requires that 3060 * every packet must be contiguous on 3061 * the same USB memory page ! 3062 */ 3063 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1; 3064 3065 /* 3066 * Compute a suitable power of two alignment 3067 * for our "max_frame_size" fixup buffer(s): 3068 */ 3069 align = xfer->max_frame_size; 3070 n = 0; 3071 while (align) { 3072 align >>= 1; 3073 n++; 3074 } 3075 3076 /* check for power of two */ 3077 if (!(xfer->max_frame_size & 3078 (xfer->max_frame_size - 1))) { 3079 n--; 3080 } 3081 /* 3082 * We don't allow alignments of 3083 * less than 8 bytes: 3084 * 3085 * NOTE: Allocating using an aligment 3086 * of 1 byte has special meaning! 3087 */ 3088 if (n < 3) { 3089 n = 3; 3090 } 3091 align = (1 << n); 3092 3093 if (usb2_transfer_setup_sub_malloc( 3094 parm, &pc, xfer->max_frame_size, 3095 align, nfixup)) { 3096 parm->err = USB_ERR_NOMEM; 3097 return; 3098 } 3099 xfer->buf_fixup = pc; 3100 3101 alloc_dma_set: 3102 3103 if (parm->err) { 3104 return; 3105 } 3106 last_obj = NULL; 3107 3108 if (usb2_transfer_setup_sub_malloc( 3109 parm, &pc, sizeof(uhci_td_t), 3110 UHCI_TD_ALIGN, ntd)) { 3111 parm->err = USB_ERR_NOMEM; 3112 return; 3113 } 3114 if (parm->buf) { 3115 for (n = 0; n != ntd; n++) { 3116 uhci_td_t *td; 3117 3118 usb2_get_page(pc + n, 0, &page_info); 3119 3120 td = page_info.buffer; 3121 3122 /* init TD */ 3123 if ((parm->methods == &uhci_device_bulk_methods) || 3124 (parm->methods == &uhci_device_ctrl_methods) || 3125 (parm->methods == &uhci_device_intr_methods)) { 3126 /* set depth first bit */ 3127 td->td_self = htole32(page_info.physaddr | 3128 UHCI_PTR_TD | UHCI_PTR_VF); 3129 } else { 3130 td->td_self = htole32(page_info.physaddr | 3131 UHCI_PTR_TD); 3132 } 3133 3134 td->obj_next = last_obj; 3135 td->page_cache = pc + n; 3136 3137 last_obj = td; 3138 3139 usb2_pc_cpu_flush(pc + n); 3140 } 3141 } 3142 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3143 3144 last_obj = NULL; 3145 3146 if (usb2_transfer_setup_sub_malloc( 3147 parm, &pc, sizeof(uhci_qh_t), 3148 UHCI_QH_ALIGN, nqh)) { 3149 parm->err = USB_ERR_NOMEM; 3150 return; 3151 } 3152 if (parm->buf) { 3153 for (n = 0; n != nqh; n++) { 3154 uhci_qh_t *qh; 3155 3156 usb2_get_page(pc + n, 0, &page_info); 3157 3158 qh = page_info.buffer; 3159 3160 /* init QH */ 3161 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH); 3162 qh->obj_next = last_obj; 3163 qh->page_cache = pc + n; 3164 3165 last_obj = qh; 3166 3167 usb2_pc_cpu_flush(pc + n); 3168 } 3169 } 3170 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3171 3172 if (!xfer->flags_int.curr_dma_set) { 3173 xfer->flags_int.curr_dma_set = 1; 3174 goto alloc_dma_set; 3175 } 3176 } 3177 3178 static void 3179 uhci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 3180 struct usb2_pipe *pipe) 3181 { 3182 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 3183 3184 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3185 pipe, udev->address, 3186 edesc->bEndpointAddress, udev->flags.usb2_mode, 3187 sc->sc_addr); 3188 3189 if (udev->flags.usb2_mode != USB_MODE_HOST) { 3190 /* not supported */ 3191 return; 3192 } 3193 if (udev->device_index == sc->sc_addr) { 3194 switch (edesc->bEndpointAddress) { 3195 case USB_CONTROL_ENDPOINT: 3196 pipe->methods = &uhci_root_ctrl_methods; 3197 break; 3198 case UE_DIR_IN | UHCI_INTR_ENDPT: 3199 pipe->methods = &uhci_root_intr_methods; 3200 break; 3201 default: 3202 /* do nothing */ 3203 break; 3204 } 3205 } else { 3206 switch (edesc->bmAttributes & UE_XFERTYPE) { 3207 case UE_CONTROL: 3208 pipe->methods = &uhci_device_ctrl_methods; 3209 break; 3210 case UE_INTERRUPT: 3211 pipe->methods = &uhci_device_intr_methods; 3212 break; 3213 case UE_ISOCHRONOUS: 3214 if (udev->speed == USB_SPEED_FULL) { 3215 pipe->methods = &uhci_device_isoc_methods; 3216 } 3217 break; 3218 case UE_BULK: 3219 if (udev->speed != USB_SPEED_LOW) { 3220 pipe->methods = &uhci_device_bulk_methods; 3221 } 3222 break; 3223 default: 3224 /* do nothing */ 3225 break; 3226 } 3227 } 3228 } 3229 3230 static void 3231 uhci_xfer_unsetup(struct usb2_xfer *xfer) 3232 { 3233 return; 3234 } 3235 3236 static void 3237 uhci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 3238 { 3239 /* 3240 * Wait until hardware has finished any possible use of the 3241 * transfer descriptor(s) and QH 3242 */ 3243 *pus = (1125); /* microseconds */ 3244 } 3245 3246 static void 3247 uhci_device_resume(struct usb2_device *udev) 3248 { 3249 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3250 struct usb2_xfer *xfer; 3251 struct usb2_pipe_methods *methods; 3252 uhci_qh_t *qh; 3253 3254 DPRINTF("\n"); 3255 3256 USB_BUS_LOCK(udev->bus); 3257 3258 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3259 3260 if (xfer->xroot->udev == udev) { 3261 3262 methods = xfer->pipe->methods; 3263 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3264 3265 if (methods == &uhci_device_bulk_methods) { 3266 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 3267 uhci_add_loop(sc); 3268 xfer->flags_int.bandwidth_reclaimed = 1; 3269 } 3270 if (methods == &uhci_device_ctrl_methods) { 3271 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3272 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 3273 } else { 3274 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 3275 } 3276 } 3277 if (methods == &uhci_device_intr_methods) { 3278 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3279 } 3280 } 3281 } 3282 3283 USB_BUS_UNLOCK(udev->bus); 3284 3285 return; 3286 } 3287 3288 static void 3289 uhci_device_suspend(struct usb2_device *udev) 3290 { 3291 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3292 struct usb2_xfer *xfer; 3293 struct usb2_pipe_methods *methods; 3294 uhci_qh_t *qh; 3295 3296 DPRINTF("\n"); 3297 3298 USB_BUS_LOCK(udev->bus); 3299 3300 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3301 3302 if (xfer->xroot->udev == udev) { 3303 3304 methods = xfer->pipe->methods; 3305 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3306 3307 if (xfer->flags_int.bandwidth_reclaimed) { 3308 xfer->flags_int.bandwidth_reclaimed = 0; 3309 uhci_rem_loop(sc); 3310 } 3311 if (methods == &uhci_device_bulk_methods) { 3312 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 3313 } 3314 if (methods == &uhci_device_ctrl_methods) { 3315 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3316 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 3317 } else { 3318 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 3319 } 3320 } 3321 if (methods == &uhci_device_intr_methods) { 3322 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3323 } 3324 } 3325 } 3326 3327 USB_BUS_UNLOCK(udev->bus); 3328 3329 return; 3330 } 3331 3332 static void 3333 uhci_set_hw_power(struct usb2_bus *bus) 3334 { 3335 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3336 uint32_t flags; 3337 3338 DPRINTF("\n"); 3339 3340 USB_BUS_LOCK(bus); 3341 3342 flags = bus->hw_power_state; 3343 3344 /* 3345 * WARNING: Some FULL speed USB devices require periodic SOF 3346 * messages! If any USB devices are connected through the 3347 * UHCI, power save will be disabled! 3348 */ 3349 if (flags & (USB_HW_POWER_CONTROL | 3350 USB_HW_POWER_NON_ROOT_HUB | 3351 USB_HW_POWER_BULK | 3352 USB_HW_POWER_INTERRUPT | 3353 USB_HW_POWER_ISOC)) { 3354 DPRINTF("Some USB transfer is " 3355 "active on %u.\n", 3356 device_get_unit(sc->sc_bus.bdev)); 3357 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 3358 } else { 3359 DPRINTF("Power save on %u.\n", 3360 device_get_unit(sc->sc_bus.bdev)); 3361 UHCICMD(sc, UHCI_CMD_MAXP); 3362 } 3363 3364 USB_BUS_UNLOCK(bus); 3365 3366 return; 3367 } 3368 3369 3370 struct usb2_bus_methods uhci_bus_methods = 3371 { 3372 .pipe_init = uhci_pipe_init, 3373 .xfer_setup = uhci_xfer_setup, 3374 .xfer_unsetup = uhci_xfer_unsetup, 3375 .do_poll = uhci_do_poll, 3376 .get_dma_delay = uhci_get_dma_delay, 3377 .device_resume = uhci_device_resume, 3378 .device_suspend = uhci_device_suspend, 3379 .set_hw_power = uhci_set_hw_power, 3380 .roothub_exec = uhci_root_ctrl_task, 3381 }; 3382