1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * USB Universal Host Controller driver. 33 * Handles e.g. PIIX3 and PIIX4. 34 * 35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 38 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 39 */ 40 41 #include <sys/stdint.h> 42 #include <sys/stddef.h> 43 #include <sys/param.h> 44 #include <sys/queue.h> 45 #include <sys/types.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/bus.h> 49 #include <sys/module.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/sysctl.h> 54 #include <sys/sx.h> 55 #include <sys/unistd.h> 56 #include <sys/callout.h> 57 #include <sys/malloc.h> 58 #include <sys/priv.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 63 #define USB_DEBUG_VAR uhcidebug 64 65 #include <dev/usb/usb_core.h> 66 #include <dev/usb/usb_debug.h> 67 #include <dev/usb/usb_busdma.h> 68 #include <dev/usb/usb_process.h> 69 #include <dev/usb/usb_transfer.h> 70 #include <dev/usb/usb_device.h> 71 #include <dev/usb/usb_hub.h> 72 #include <dev/usb/usb_util.h> 73 74 #include <dev/usb/usb_controller.h> 75 #include <dev/usb/usb_bus.h> 76 #include <dev/usb/controller/uhci.h> 77 #include <dev/usb/controller/uhcireg.h> 78 79 #define alt_next next 80 #define UHCI_BUS2SC(bus) \ 81 ((uhci_softc_t *)(((uint8_t *)(bus)) - \ 82 ((uint8_t *)&(((uhci_softc_t *)0)->sc_bus)))) 83 84 #ifdef USB_DEBUG 85 static int uhcidebug = 0; 86 static int uhcinoloop = 0; 87 88 static SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW, 0, "USB uhci"); 89 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 90 &uhcidebug, 0, "uhci debug level"); 91 TUNABLE_INT("hw.usb.uhci.debug", &uhcidebug); 92 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RW | CTLFLAG_TUN, 93 &uhcinoloop, 0, "uhci noloop"); 94 TUNABLE_INT("hw.usb.uhci.loop", &uhcinoloop); 95 96 static void uhci_dumpregs(uhci_softc_t *sc); 97 static void uhci_dump_tds(uhci_td_t *td); 98 99 #endif 100 101 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 102 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 103 #define UWRITE1(sc, r, x) \ 104 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 105 } while (/*CONSTCOND*/0) 106 #define UWRITE2(sc, r, x) \ 107 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 108 } while (/*CONSTCOND*/0) 109 #define UWRITE4(sc, r, x) \ 110 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 111 } while (/*CONSTCOND*/0) 112 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 113 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 114 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 115 116 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 117 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 118 119 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 120 121 #define UHCI_INTR_ENDPT 1 122 123 struct uhci_mem_layout { 124 125 struct usb_page_search buf_res; 126 struct usb_page_search fix_res; 127 128 struct usb_page_cache *buf_pc; 129 struct usb_page_cache *fix_pc; 130 131 uint32_t buf_offset; 132 133 uint16_t max_frame_size; 134 }; 135 136 struct uhci_std_temp { 137 138 struct uhci_mem_layout ml; 139 uhci_td_t *td; 140 uhci_td_t *td_next; 141 uint32_t average; 142 uint32_t td_status; 143 uint32_t td_token; 144 uint32_t len; 145 uint16_t max_frame_size; 146 uint8_t shortpkt; 147 uint8_t setup_alt_next; 148 uint8_t last_frame; 149 }; 150 151 extern struct usb_bus_methods uhci_bus_methods; 152 extern struct usb_pipe_methods uhci_device_bulk_methods; 153 extern struct usb_pipe_methods uhci_device_ctrl_methods; 154 extern struct usb_pipe_methods uhci_device_intr_methods; 155 extern struct usb_pipe_methods uhci_device_isoc_methods; 156 157 static uint8_t uhci_restart(uhci_softc_t *sc); 158 static void uhci_do_poll(struct usb_bus *); 159 static void uhci_device_done(struct usb_xfer *, usb_error_t); 160 static void uhci_transfer_intr_enqueue(struct usb_xfer *); 161 static void uhci_timeout(void *); 162 static uint8_t uhci_check_transfer(struct usb_xfer *); 163 static void uhci_root_intr(uhci_softc_t *sc); 164 165 void 166 uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 167 { 168 struct uhci_softc *sc = UHCI_BUS2SC(bus); 169 uint32_t i; 170 171 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 172 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN); 173 174 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg, 175 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 176 177 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg, 178 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 179 180 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 181 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 182 183 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg, 184 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 185 186 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg, 187 sizeof(uhci_td_t), UHCI_TD_ALIGN); 188 189 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) { 190 cb(bus, sc->sc_hw.isoc_start_pc + i, 191 sc->sc_hw.isoc_start_pg + i, 192 sizeof(uhci_td_t), UHCI_TD_ALIGN); 193 } 194 195 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) { 196 cb(bus, sc->sc_hw.intr_start_pc + i, 197 sc->sc_hw.intr_start_pg + i, 198 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 199 } 200 } 201 202 static void 203 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer) 204 { 205 ml->buf_pc = xfer->frbuffers + 0; 206 ml->fix_pc = xfer->buf_fixup; 207 208 ml->buf_offset = 0; 209 210 ml->max_frame_size = xfer->max_frame_size; 211 } 212 213 static void 214 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td) 215 { 216 usbd_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res); 217 218 if (ml->buf_res.length < td->len) { 219 220 /* need to do a fixup */ 221 222 usbd_get_page(ml->fix_pc, 0, &ml->fix_res); 223 224 td->td_buffer = htole32(ml->fix_res.physaddr); 225 226 /* 227 * The UHCI driver cannot handle 228 * page crossings, so a fixup is 229 * needed: 230 * 231 * +----+----+ - - - 232 * | YYY|Y | 233 * +----+----+ - - - 234 * \ \ 235 * \ \ 236 * +----+ 237 * |YYYY| (fixup) 238 * +----+ 239 */ 240 241 if ((td->td_token & htole32(UHCI_TD_PID)) == 242 htole32(UHCI_TD_PID_IN)) { 243 td->fix_pc = ml->fix_pc; 244 usb_pc_cpu_invalidate(ml->fix_pc); 245 246 } else { 247 td->fix_pc = NULL; 248 249 /* copy data to fixup location */ 250 251 usbd_copy_out(ml->buf_pc, ml->buf_offset, 252 ml->fix_res.buffer, td->len); 253 254 usb_pc_cpu_flush(ml->fix_pc); 255 } 256 257 /* prepare next fixup */ 258 259 ml->fix_pc++; 260 261 } else { 262 263 td->td_buffer = htole32(ml->buf_res.physaddr); 264 td->fix_pc = NULL; 265 } 266 267 /* prepare next data location */ 268 269 ml->buf_offset += td->len; 270 } 271 272 /* 273 * Return values: 274 * 0: Success 275 * Else: Failure 276 */ 277 static uint8_t 278 uhci_restart(uhci_softc_t *sc) 279 { 280 struct usb_page_search buf_res; 281 282 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 283 284 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) { 285 DPRINTFN(2, "Already started\n"); 286 return (0); 287 } 288 289 DPRINTFN(2, "Restarting\n"); 290 291 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 292 293 /* Reload fresh base address */ 294 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr); 295 296 /* 297 * Assume 64 byte packets at frame end and start HC controller: 298 */ 299 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 300 301 /* wait 10 milliseconds */ 302 303 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 304 305 /* check that controller has started */ 306 307 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 308 DPRINTFN(2, "Failed\n"); 309 return (1); 310 } 311 return (0); 312 } 313 314 void 315 uhci_reset(uhci_softc_t *sc) 316 { 317 uint16_t n; 318 319 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 320 321 DPRINTF("resetting the HC\n"); 322 323 /* disable interrupts */ 324 325 UWRITE2(sc, UHCI_INTR, 0); 326 327 /* global reset */ 328 329 UHCICMD(sc, UHCI_CMD_GRESET); 330 331 /* wait */ 332 333 usb_pause_mtx(&sc->sc_bus.bus_mtx, 334 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 335 336 /* terminate all transfers */ 337 338 UHCICMD(sc, UHCI_CMD_HCRESET); 339 340 /* the reset bit goes low when the controller is done */ 341 342 n = UHCI_RESET_TIMEOUT; 343 while (n--) { 344 /* wait one millisecond */ 345 346 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 347 348 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) { 349 goto done_1; 350 } 351 } 352 353 device_printf(sc->sc_bus.bdev, 354 "controller did not reset\n"); 355 356 done_1: 357 358 n = 10; 359 while (n--) { 360 /* wait one millisecond */ 361 362 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 363 364 /* check if HC is stopped */ 365 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 366 goto done_2; 367 } 368 } 369 370 device_printf(sc->sc_bus.bdev, 371 "controller did not stop\n"); 372 373 done_2: 374 375 /* reset frame number */ 376 UWRITE2(sc, UHCI_FRNUM, 0); 377 /* set default SOF value */ 378 UWRITE1(sc, UHCI_SOF, 0x40); 379 380 USB_BUS_UNLOCK(&sc->sc_bus); 381 382 /* stop root interrupt */ 383 usb_callout_drain(&sc->sc_root_intr); 384 385 USB_BUS_LOCK(&sc->sc_bus); 386 } 387 388 static void 389 uhci_start(uhci_softc_t *sc) 390 { 391 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 392 393 DPRINTFN(2, "enabling\n"); 394 395 /* enable interrupts */ 396 397 UWRITE2(sc, UHCI_INTR, 398 (UHCI_INTR_TOCRCIE | 399 UHCI_INTR_RIE | 400 UHCI_INTR_IOCE | 401 UHCI_INTR_SPIE)); 402 403 if (uhci_restart(sc)) { 404 device_printf(sc->sc_bus.bdev, 405 "cannot start HC controller\n"); 406 } 407 408 /* start root interrupt */ 409 uhci_root_intr(sc); 410 } 411 412 static struct uhci_qh * 413 uhci_init_qh(struct usb_page_cache *pc) 414 { 415 struct usb_page_search buf_res; 416 struct uhci_qh *qh; 417 418 usbd_get_page(pc, 0, &buf_res); 419 420 qh = buf_res.buffer; 421 422 qh->qh_self = 423 htole32(buf_res.physaddr) | 424 htole32(UHCI_PTR_QH); 425 426 qh->page_cache = pc; 427 428 return (qh); 429 } 430 431 static struct uhci_td * 432 uhci_init_td(struct usb_page_cache *pc) 433 { 434 struct usb_page_search buf_res; 435 struct uhci_td *td; 436 437 usbd_get_page(pc, 0, &buf_res); 438 439 td = buf_res.buffer; 440 441 td->td_self = 442 htole32(buf_res.physaddr) | 443 htole32(UHCI_PTR_TD); 444 445 td->page_cache = pc; 446 447 return (td); 448 } 449 450 usb_error_t 451 uhci_init(uhci_softc_t *sc) 452 { 453 uint16_t bit; 454 uint16_t x; 455 uint16_t y; 456 457 DPRINTF("start\n"); 458 459 usb_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_mtx, 0); 460 461 #ifdef USB_DEBUG 462 if (uhcidebug > 2) { 463 uhci_dumpregs(sc); 464 } 465 #endif 466 /* 467 * Setup QH's 468 */ 469 sc->sc_ls_ctl_p_last = 470 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc); 471 472 sc->sc_fs_ctl_p_last = 473 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc); 474 475 sc->sc_bulk_p_last = 476 uhci_init_qh(&sc->sc_hw.bulk_start_pc); 477 #if 0 478 sc->sc_reclaim_qh_p = 479 sc->sc_fs_ctl_p_last; 480 #else 481 /* setup reclaim looping point */ 482 sc->sc_reclaim_qh_p = 483 sc->sc_bulk_p_last; 484 #endif 485 486 sc->sc_last_qh_p = 487 uhci_init_qh(&sc->sc_hw.last_qh_pc); 488 489 sc->sc_last_td_p = 490 uhci_init_td(&sc->sc_hw.last_td_pc); 491 492 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 493 sc->sc_isoc_p_last[x] = 494 uhci_init_td(sc->sc_hw.isoc_start_pc + x); 495 } 496 497 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) { 498 sc->sc_intr_p_last[x] = 499 uhci_init_qh(sc->sc_hw.intr_start_pc + x); 500 } 501 502 /* 503 * the QHs are arranged to give poll intervals that are 504 * powers of 2 times 1ms 505 */ 506 bit = UHCI_IFRAMELIST_COUNT / 2; 507 while (bit) { 508 x = bit; 509 while (x & bit) { 510 uhci_qh_t *qh_x; 511 uhci_qh_t *qh_y; 512 513 y = (x ^ bit) | (bit / 2); 514 515 /* 516 * the next QH has half the poll interval 517 */ 518 qh_x = sc->sc_intr_p_last[x]; 519 qh_y = sc->sc_intr_p_last[y]; 520 521 qh_x->h_next = NULL; 522 qh_x->qh_h_next = qh_y->qh_self; 523 qh_x->e_next = NULL; 524 qh_x->qh_e_next = htole32(UHCI_PTR_T); 525 x++; 526 } 527 bit >>= 1; 528 } 529 530 if (1) { 531 uhci_qh_t *qh_ls; 532 uhci_qh_t *qh_intr; 533 534 qh_ls = sc->sc_ls_ctl_p_last; 535 qh_intr = sc->sc_intr_p_last[0]; 536 537 /* start QH for interrupt traffic */ 538 qh_intr->h_next = qh_ls; 539 qh_intr->qh_h_next = qh_ls->qh_self; 540 qh_intr->e_next = 0; 541 qh_intr->qh_e_next = htole32(UHCI_PTR_T); 542 } 543 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 544 545 uhci_td_t *td_x; 546 uhci_qh_t *qh_intr; 547 548 td_x = sc->sc_isoc_p_last[x]; 549 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)]; 550 551 /* start TD for isochronous traffic */ 552 td_x->next = NULL; 553 td_x->td_next = qh_intr->qh_self; 554 td_x->td_status = htole32(UHCI_TD_IOS); 555 td_x->td_token = htole32(0); 556 td_x->td_buffer = htole32(0); 557 } 558 559 if (1) { 560 uhci_qh_t *qh_ls; 561 uhci_qh_t *qh_fs; 562 563 qh_ls = sc->sc_ls_ctl_p_last; 564 qh_fs = sc->sc_fs_ctl_p_last; 565 566 /* start QH where low speed control traffic will be queued */ 567 qh_ls->h_next = qh_fs; 568 qh_ls->qh_h_next = qh_fs->qh_self; 569 qh_ls->e_next = 0; 570 qh_ls->qh_e_next = htole32(UHCI_PTR_T); 571 } 572 if (1) { 573 uhci_qh_t *qh_ctl; 574 uhci_qh_t *qh_blk; 575 uhci_qh_t *qh_lst; 576 uhci_td_t *td_lst; 577 578 qh_ctl = sc->sc_fs_ctl_p_last; 579 qh_blk = sc->sc_bulk_p_last; 580 581 /* start QH where full speed control traffic will be queued */ 582 qh_ctl->h_next = qh_blk; 583 qh_ctl->qh_h_next = qh_blk->qh_self; 584 qh_ctl->e_next = 0; 585 qh_ctl->qh_e_next = htole32(UHCI_PTR_T); 586 587 qh_lst = sc->sc_last_qh_p; 588 589 /* start QH where bulk traffic will be queued */ 590 qh_blk->h_next = qh_lst; 591 qh_blk->qh_h_next = qh_lst->qh_self; 592 qh_blk->e_next = 0; 593 qh_blk->qh_e_next = htole32(UHCI_PTR_T); 594 595 td_lst = sc->sc_last_td_p; 596 597 /* end QH which is used for looping the QHs */ 598 qh_lst->h_next = 0; 599 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */ 600 qh_lst->e_next = td_lst; 601 qh_lst->qh_e_next = td_lst->td_self; 602 603 /* 604 * end TD which hangs from the last QH, to avoid a bug in the PIIX 605 * that makes it run berserk otherwise 606 */ 607 td_lst->next = 0; 608 td_lst->td_next = htole32(UHCI_PTR_T); 609 td_lst->td_status = htole32(0); /* inactive */ 610 td_lst->td_token = htole32(0); 611 td_lst->td_buffer = htole32(0); 612 } 613 if (1) { 614 struct usb_page_search buf_res; 615 uint32_t *pframes; 616 617 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 618 619 pframes = buf_res.buffer; 620 621 622 /* 623 * Setup UHCI framelist 624 * 625 * Execution order: 626 * 627 * pframes -> full speed isochronous -> interrupt QH's -> low 628 * speed control -> full speed control -> bulk transfers 629 * 630 */ 631 632 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) { 633 pframes[x] = 634 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self; 635 } 636 } 637 /* flush all cache into memory */ 638 639 usb_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc); 640 641 /* set up the bus struct */ 642 sc->sc_bus.methods = &uhci_bus_methods; 643 644 USB_BUS_LOCK(&sc->sc_bus); 645 /* reset the controller */ 646 uhci_reset(sc); 647 648 /* start the controller */ 649 uhci_start(sc); 650 USB_BUS_UNLOCK(&sc->sc_bus); 651 652 /* catch lost interrupts */ 653 uhci_do_poll(&sc->sc_bus); 654 655 return (0); 656 } 657 658 static void 659 uhci_suspend(uhci_softc_t *sc) 660 { 661 #ifdef USB_DEBUG 662 if (uhcidebug > 2) { 663 uhci_dumpregs(sc); 664 } 665 #endif 666 667 USB_BUS_LOCK(&sc->sc_bus); 668 669 /* stop the controller */ 670 671 uhci_reset(sc); 672 673 /* enter global suspend */ 674 675 UHCICMD(sc, UHCI_CMD_EGSM); 676 677 USB_BUS_UNLOCK(&sc->sc_bus); 678 } 679 680 static void 681 uhci_resume(uhci_softc_t *sc) 682 { 683 USB_BUS_LOCK(&sc->sc_bus); 684 685 /* reset the controller */ 686 687 uhci_reset(sc); 688 689 /* force global resume */ 690 691 UHCICMD(sc, UHCI_CMD_FGR); 692 693 /* and start traffic again */ 694 695 uhci_start(sc); 696 697 USB_BUS_UNLOCK(&sc->sc_bus); 698 699 #ifdef USB_DEBUG 700 if (uhcidebug > 2) 701 uhci_dumpregs(sc); 702 #endif 703 704 /* catch lost interrupts */ 705 uhci_do_poll(&sc->sc_bus); 706 } 707 708 #ifdef USB_DEBUG 709 static void 710 uhci_dumpregs(uhci_softc_t *sc) 711 { 712 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 713 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 714 device_get_nameunit(sc->sc_bus.bdev), 715 UREAD2(sc, UHCI_CMD), 716 UREAD2(sc, UHCI_STS), 717 UREAD2(sc, UHCI_INTR), 718 UREAD2(sc, UHCI_FRNUM), 719 UREAD4(sc, UHCI_FLBASEADDR), 720 UREAD1(sc, UHCI_SOF), 721 UREAD2(sc, UHCI_PORTSC1), 722 UREAD2(sc, UHCI_PORTSC2)); 723 } 724 725 static uint8_t 726 uhci_dump_td(uhci_td_t *p) 727 { 728 uint32_t td_next; 729 uint32_t td_status; 730 uint32_t td_token; 731 uint8_t temp; 732 733 usb_pc_cpu_invalidate(p->page_cache); 734 735 td_next = le32toh(p->td_next); 736 td_status = le32toh(p->td_status); 737 td_token = le32toh(p->td_token); 738 739 /* 740 * Check whether the link pointer in this TD marks the link pointer 741 * as end of queue: 742 */ 743 temp = ((td_next & UHCI_PTR_T) || (td_next == 0)); 744 745 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x " 746 "token=0x%08x buffer=0x%08x\n", 747 p, 748 le32toh(p->td_self), 749 td_next, 750 td_status, 751 td_token, 752 le32toh(p->td_buffer)); 753 754 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x," 755 "addr=%d,endpt=%d,D=%d,maxlen=%d\n", 756 p, 757 (td_next & 1) ? "-T" : "", 758 (td_next & 2) ? "-Q" : "", 759 (td_next & 4) ? "-VF" : "", 760 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "", 761 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "", 762 (td_status & UHCI_TD_NAK) ? "-NAK" : "", 763 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "", 764 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "", 765 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "", 766 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "", 767 (td_status & UHCI_TD_IOC) ? "-IOC" : "", 768 (td_status & UHCI_TD_IOS) ? "-IOS" : "", 769 (td_status & UHCI_TD_LS) ? "-LS" : "", 770 (td_status & UHCI_TD_SPD) ? "-SPD" : "", 771 UHCI_TD_GET_ERRCNT(td_status), 772 UHCI_TD_GET_ACTLEN(td_status), 773 UHCI_TD_GET_PID(td_token), 774 UHCI_TD_GET_DEVADDR(td_token), 775 UHCI_TD_GET_ENDPT(td_token), 776 UHCI_TD_GET_DT(td_token), 777 UHCI_TD_GET_MAXLEN(td_token)); 778 779 return (temp); 780 } 781 782 static uint8_t 783 uhci_dump_qh(uhci_qh_t *sqh) 784 { 785 uint8_t temp; 786 uint32_t qh_h_next; 787 uint32_t qh_e_next; 788 789 usb_pc_cpu_invalidate(sqh->page_cache); 790 791 qh_h_next = le32toh(sqh->qh_h_next); 792 qh_e_next = le32toh(sqh->qh_e_next); 793 794 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh, 795 le32toh(sqh->qh_self), qh_h_next, qh_e_next); 796 797 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) | 798 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0)); 799 800 return (temp); 801 } 802 803 static void 804 uhci_dump_all(uhci_softc_t *sc) 805 { 806 uhci_dumpregs(sc); 807 uhci_dump_qh(sc->sc_ls_ctl_p_last); 808 uhci_dump_qh(sc->sc_fs_ctl_p_last); 809 uhci_dump_qh(sc->sc_bulk_p_last); 810 uhci_dump_qh(sc->sc_last_qh_p); 811 } 812 813 static void 814 uhci_dump_tds(uhci_td_t *td) 815 { 816 for (; 817 td != NULL; 818 td = td->obj_next) { 819 if (uhci_dump_td(td)) { 820 break; 821 } 822 } 823 } 824 825 #endif 826 827 /* 828 * Let the last QH loop back to the full speed control transfer QH. 829 * This is what intel calls "bandwidth reclamation" and improves 830 * USB performance a lot for some devices. 831 * If we are already looping, just count it. 832 */ 833 static void 834 uhci_add_loop(uhci_softc_t *sc) 835 { 836 struct uhci_qh *qh_lst; 837 struct uhci_qh *qh_rec; 838 839 #ifdef USB_DEBUG 840 if (uhcinoloop) { 841 return; 842 } 843 #endif 844 if (++(sc->sc_loops) == 1) { 845 DPRINTFN(6, "add\n"); 846 847 qh_lst = sc->sc_last_qh_p; 848 qh_rec = sc->sc_reclaim_qh_p; 849 850 /* NOTE: we don't loop back the soft pointer */ 851 852 qh_lst->qh_h_next = qh_rec->qh_self; 853 usb_pc_cpu_flush(qh_lst->page_cache); 854 } 855 } 856 857 static void 858 uhci_rem_loop(uhci_softc_t *sc) 859 { 860 struct uhci_qh *qh_lst; 861 862 #ifdef USB_DEBUG 863 if (uhcinoloop) { 864 return; 865 } 866 #endif 867 if (--(sc->sc_loops) == 0) { 868 DPRINTFN(6, "remove\n"); 869 870 qh_lst = sc->sc_last_qh_p; 871 qh_lst->qh_h_next = htole32(UHCI_PTR_T); 872 usb_pc_cpu_flush(qh_lst->page_cache); 873 } 874 } 875 876 static void 877 uhci_transfer_intr_enqueue(struct usb_xfer *xfer) 878 { 879 /* check for early completion */ 880 if (uhci_check_transfer(xfer)) { 881 return; 882 } 883 /* put transfer on interrupt queue */ 884 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 885 886 /* start timeout, if any */ 887 if (xfer->timeout != 0) { 888 usbd_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout); 889 } 890 } 891 892 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last) 893 static uhci_td_t * 894 _uhci_append_td(uhci_td_t *std, uhci_td_t *last) 895 { 896 DPRINTFN(11, "%p to %p\n", std, last); 897 898 /* (sc->sc_bus.mtx) must be locked */ 899 900 std->next = last->next; 901 std->td_next = last->td_next; 902 903 std->prev = last; 904 905 usb_pc_cpu_flush(std->page_cache); 906 907 /* 908 * the last->next->prev is never followed: std->next->prev = std; 909 */ 910 last->next = std; 911 last->td_next = std->td_self; 912 913 usb_pc_cpu_flush(last->page_cache); 914 915 return (std); 916 } 917 918 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last) 919 static uhci_qh_t * 920 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last) 921 { 922 DPRINTFN(11, "%p to %p\n", sqh, last); 923 924 if (sqh->h_prev != NULL) { 925 /* should not happen */ 926 DPRINTFN(0, "QH already linked!\n"); 927 return (last); 928 } 929 /* (sc->sc_bus.mtx) must be locked */ 930 931 sqh->h_next = last->h_next; 932 sqh->qh_h_next = last->qh_h_next; 933 934 sqh->h_prev = last; 935 936 usb_pc_cpu_flush(sqh->page_cache); 937 938 /* 939 * The "last->h_next->h_prev" is never followed: 940 * 941 * "sqh->h_next->h_prev" = sqh; 942 */ 943 944 last->h_next = sqh; 945 last->qh_h_next = sqh->qh_self; 946 947 usb_pc_cpu_flush(last->page_cache); 948 949 return (sqh); 950 } 951 952 /**/ 953 954 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last) 955 static uhci_td_t * 956 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last) 957 { 958 DPRINTFN(11, "%p from %p\n", std, last); 959 960 /* (sc->sc_bus.mtx) must be locked */ 961 962 std->prev->next = std->next; 963 std->prev->td_next = std->td_next; 964 965 usb_pc_cpu_flush(std->prev->page_cache); 966 967 if (std->next) { 968 std->next->prev = std->prev; 969 usb_pc_cpu_flush(std->next->page_cache); 970 } 971 return ((last == std) ? std->prev : last); 972 } 973 974 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last) 975 static uhci_qh_t * 976 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last) 977 { 978 DPRINTFN(11, "%p from %p\n", sqh, last); 979 980 /* (sc->sc_bus.mtx) must be locked */ 981 982 /* only remove if not removed from a queue */ 983 if (sqh->h_prev) { 984 985 sqh->h_prev->h_next = sqh->h_next; 986 sqh->h_prev->qh_h_next = sqh->qh_h_next; 987 988 usb_pc_cpu_flush(sqh->h_prev->page_cache); 989 990 if (sqh->h_next) { 991 sqh->h_next->h_prev = sqh->h_prev; 992 usb_pc_cpu_flush(sqh->h_next->page_cache); 993 } 994 last = ((last == sqh) ? sqh->h_prev : last); 995 996 sqh->h_prev = 0; 997 998 usb_pc_cpu_flush(sqh->page_cache); 999 } 1000 return (last); 1001 } 1002 1003 static void 1004 uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer) 1005 { 1006 struct usb_page_search res; 1007 uint32_t nframes = xfer->nframes; 1008 uint32_t status; 1009 uint32_t offset = 0; 1010 uint32_t *plen = xfer->frlengths; 1011 uint16_t len = 0; 1012 uhci_td_t *td = xfer->td_transfer_first; 1013 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos]; 1014 1015 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1016 xfer, xfer->endpoint); 1017 1018 /* sync any DMA memory before doing fixups */ 1019 1020 usb_bdma_post_sync(xfer); 1021 1022 while (nframes--) { 1023 if (td == NULL) { 1024 panic("%s:%d: out of TD's\n", 1025 __FUNCTION__, __LINE__); 1026 } 1027 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 1028 pp_last = &sc->sc_isoc_p_last[0]; 1029 } 1030 #ifdef USB_DEBUG 1031 if (uhcidebug > 5) { 1032 DPRINTF("isoc TD\n"); 1033 uhci_dump_td(td); 1034 } 1035 #endif 1036 usb_pc_cpu_invalidate(td->page_cache); 1037 status = le32toh(td->td_status); 1038 1039 len = UHCI_TD_GET_ACTLEN(status); 1040 1041 if (len > *plen) { 1042 len = *plen; 1043 } 1044 if (td->fix_pc) { 1045 1046 usbd_get_page(td->fix_pc, 0, &res); 1047 1048 /* copy data from fixup location to real location */ 1049 1050 usb_pc_cpu_invalidate(td->fix_pc); 1051 1052 usbd_copy_in(xfer->frbuffers, offset, 1053 res.buffer, len); 1054 } 1055 offset += *plen; 1056 1057 *plen = len; 1058 1059 /* remove TD from schedule */ 1060 UHCI_REMOVE_TD(td, *pp_last); 1061 1062 pp_last++; 1063 plen++; 1064 td = td->obj_next; 1065 } 1066 1067 xfer->aframes = xfer->nframes; 1068 } 1069 1070 static usb_error_t 1071 uhci_non_isoc_done_sub(struct usb_xfer *xfer) 1072 { 1073 struct usb_page_search res; 1074 uhci_td_t *td; 1075 uhci_td_t *td_alt_next; 1076 uint32_t status; 1077 uint32_t token; 1078 uint16_t len; 1079 1080 td = xfer->td_transfer_cache; 1081 td_alt_next = td->alt_next; 1082 1083 if (xfer->aframes != xfer->nframes) { 1084 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1085 } 1086 while (1) { 1087 1088 usb_pc_cpu_invalidate(td->page_cache); 1089 status = le32toh(td->td_status); 1090 token = le32toh(td->td_token); 1091 1092 /* 1093 * Verify the status and add 1094 * up the actual length: 1095 */ 1096 1097 len = UHCI_TD_GET_ACTLEN(status); 1098 if (len > td->len) { 1099 /* should not happen */ 1100 DPRINTF("Invalid status length, " 1101 "0x%04x/0x%04x bytes\n", len, td->len); 1102 status |= UHCI_TD_STALLED; 1103 1104 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) { 1105 1106 if (td->fix_pc) { 1107 1108 usbd_get_page(td->fix_pc, 0, &res); 1109 1110 /* 1111 * copy data from fixup location to real 1112 * location 1113 */ 1114 1115 usb_pc_cpu_invalidate(td->fix_pc); 1116 1117 usbd_copy_in(xfer->frbuffers + xfer->aframes, 1118 xfer->frlengths[xfer->aframes], res.buffer, len); 1119 } 1120 /* update actual length */ 1121 1122 xfer->frlengths[xfer->aframes] += len; 1123 } 1124 /* Check for last transfer */ 1125 if (((void *)td) == xfer->td_transfer_last) { 1126 td = NULL; 1127 break; 1128 } 1129 if (status & UHCI_TD_STALLED) { 1130 /* the transfer is finished */ 1131 td = NULL; 1132 break; 1133 } 1134 /* Check for short transfer */ 1135 if (len != td->len) { 1136 if (xfer->flags_int.short_frames_ok) { 1137 /* follow alt next */ 1138 td = td->alt_next; 1139 } else { 1140 /* the transfer is finished */ 1141 td = NULL; 1142 } 1143 break; 1144 } 1145 td = td->obj_next; 1146 1147 if (td->alt_next != td_alt_next) { 1148 /* this USB frame is complete */ 1149 break; 1150 } 1151 } 1152 1153 /* update transfer cache */ 1154 1155 xfer->td_transfer_cache = td; 1156 1157 /* update data toggle */ 1158 1159 xfer->endpoint->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1; 1160 1161 #ifdef USB_DEBUG 1162 if (status & UHCI_TD_ERROR) { 1163 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x " 1164 "status=%s%s%s%s%s%s%s%s%s%s%s\n", 1165 xfer->address, xfer->endpointno, xfer->aframes, 1166 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "", 1167 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "", 1168 (status & UHCI_TD_NAK) ? "[NAK]" : "", 1169 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "", 1170 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "", 1171 (status & UHCI_TD_STALLED) ? "[STALLED]" : "", 1172 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1173 (status & UHCI_TD_IOC) ? "[IOC]" : "", 1174 (status & UHCI_TD_IOS) ? "[IOS]" : "", 1175 (status & UHCI_TD_LS) ? "[LS]" : "", 1176 (status & UHCI_TD_SPD) ? "[SPD]" : ""); 1177 } 1178 #endif 1179 return (status & UHCI_TD_STALLED) ? 1180 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION; 1181 } 1182 1183 static void 1184 uhci_non_isoc_done(struct usb_xfer *xfer) 1185 { 1186 usb_error_t err = 0; 1187 1188 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1189 xfer, xfer->endpoint); 1190 1191 #ifdef USB_DEBUG 1192 if (uhcidebug > 10) { 1193 uhci_dump_tds(xfer->td_transfer_first); 1194 } 1195 #endif 1196 1197 /* sync any DMA memory before doing fixups */ 1198 1199 usb_bdma_post_sync(xfer); 1200 1201 /* reset scanner */ 1202 1203 xfer->td_transfer_cache = xfer->td_transfer_first; 1204 1205 if (xfer->flags_int.control_xfr) { 1206 if (xfer->flags_int.control_hdr) { 1207 1208 err = uhci_non_isoc_done_sub(xfer); 1209 } 1210 xfer->aframes = 1; 1211 1212 if (xfer->td_transfer_cache == NULL) { 1213 goto done; 1214 } 1215 } 1216 while (xfer->aframes != xfer->nframes) { 1217 1218 err = uhci_non_isoc_done_sub(xfer); 1219 xfer->aframes++; 1220 1221 if (xfer->td_transfer_cache == NULL) { 1222 goto done; 1223 } 1224 } 1225 1226 if (xfer->flags_int.control_xfr && 1227 !xfer->flags_int.control_act) { 1228 1229 err = uhci_non_isoc_done_sub(xfer); 1230 } 1231 done: 1232 uhci_device_done(xfer, err); 1233 } 1234 1235 /*------------------------------------------------------------------------* 1236 * uhci_check_transfer_sub 1237 * 1238 * The main purpose of this function is to update the data-toggle 1239 * in case it is wrong. 1240 *------------------------------------------------------------------------*/ 1241 static void 1242 uhci_check_transfer_sub(struct usb_xfer *xfer) 1243 { 1244 uhci_qh_t *qh; 1245 uhci_td_t *td; 1246 uhci_td_t *td_alt_next; 1247 1248 uint32_t td_token; 1249 uint32_t td_self; 1250 1251 td = xfer->td_transfer_cache; 1252 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1253 1254 td_token = td->obj_next->td_token; 1255 td = td->alt_next; 1256 xfer->td_transfer_cache = td; 1257 td_self = td->td_self; 1258 td_alt_next = td->alt_next; 1259 1260 if (xfer->flags_int.control_xfr) 1261 goto skip; /* don't touch the DT value! */ 1262 1263 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1)))) 1264 goto skip; /* data toggle has correct value */ 1265 1266 /* 1267 * The data toggle is wrong and we need to toggle it ! 1268 */ 1269 while (1) { 1270 1271 td->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1272 usb_pc_cpu_flush(td->page_cache); 1273 1274 if (td == xfer->td_transfer_last) { 1275 /* last transfer */ 1276 break; 1277 } 1278 td = td->obj_next; 1279 1280 if (td->alt_next != td_alt_next) { 1281 /* next frame */ 1282 break; 1283 } 1284 } 1285 skip: 1286 1287 /* update the QH */ 1288 qh->qh_e_next = td_self; 1289 usb_pc_cpu_flush(qh->page_cache); 1290 1291 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1292 } 1293 1294 /*------------------------------------------------------------------------* 1295 * uhci_check_transfer 1296 * 1297 * Return values: 1298 * 0: USB transfer is not finished 1299 * Else: USB transfer is finished 1300 *------------------------------------------------------------------------*/ 1301 static uint8_t 1302 uhci_check_transfer(struct usb_xfer *xfer) 1303 { 1304 uint32_t status; 1305 uint32_t token; 1306 uhci_td_t *td; 1307 1308 DPRINTFN(16, "xfer=%p checking transfer\n", xfer); 1309 1310 if (xfer->endpoint->methods == &uhci_device_isoc_methods) { 1311 /* isochronous transfer */ 1312 1313 td = xfer->td_transfer_last; 1314 1315 usb_pc_cpu_invalidate(td->page_cache); 1316 status = le32toh(td->td_status); 1317 1318 /* check also if the first is complete */ 1319 1320 td = xfer->td_transfer_first; 1321 1322 usb_pc_cpu_invalidate(td->page_cache); 1323 status |= le32toh(td->td_status); 1324 1325 if (!(status & UHCI_TD_ACTIVE)) { 1326 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1327 goto transferred; 1328 } 1329 } else { 1330 /* non-isochronous transfer */ 1331 1332 /* 1333 * check whether there is an error somewhere 1334 * in the middle, or whether there was a short 1335 * packet (SPD and not ACTIVE) 1336 */ 1337 td = xfer->td_transfer_cache; 1338 1339 while (1) { 1340 usb_pc_cpu_invalidate(td->page_cache); 1341 status = le32toh(td->td_status); 1342 token = le32toh(td->td_token); 1343 1344 /* 1345 * if there is an active TD the transfer isn't done 1346 */ 1347 if (status & UHCI_TD_ACTIVE) { 1348 /* update cache */ 1349 xfer->td_transfer_cache = td; 1350 goto done; 1351 } 1352 /* 1353 * last transfer descriptor makes the transfer done 1354 */ 1355 if (((void *)td) == xfer->td_transfer_last) { 1356 break; 1357 } 1358 /* 1359 * any kind of error makes the transfer done 1360 */ 1361 if (status & UHCI_TD_STALLED) { 1362 break; 1363 } 1364 /* 1365 * check if we reached the last packet 1366 * or if there is a short packet: 1367 */ 1368 if ((td->td_next == htole32(UHCI_PTR_T)) || 1369 (UHCI_TD_GET_ACTLEN(status) < td->len)) { 1370 1371 if (xfer->flags_int.short_frames_ok) { 1372 /* follow alt next */ 1373 if (td->alt_next) { 1374 /* update cache */ 1375 xfer->td_transfer_cache = td; 1376 uhci_check_transfer_sub(xfer); 1377 goto done; 1378 } 1379 } 1380 /* transfer is done */ 1381 break; 1382 } 1383 td = td->obj_next; 1384 } 1385 uhci_non_isoc_done(xfer); 1386 goto transferred; 1387 } 1388 1389 done: 1390 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1391 return (0); 1392 1393 transferred: 1394 return (1); 1395 } 1396 1397 static void 1398 uhci_interrupt_poll(uhci_softc_t *sc) 1399 { 1400 struct usb_xfer *xfer; 1401 1402 repeat: 1403 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1404 /* 1405 * check if transfer is transferred 1406 */ 1407 if (uhci_check_transfer(xfer)) { 1408 /* queue has been modified */ 1409 goto repeat; 1410 } 1411 } 1412 } 1413 1414 /*------------------------------------------------------------------------* 1415 * uhci_interrupt - UHCI interrupt handler 1416 * 1417 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1418 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1419 * is present ! 1420 *------------------------------------------------------------------------*/ 1421 void 1422 uhci_interrupt(uhci_softc_t *sc) 1423 { 1424 uint32_t status; 1425 1426 USB_BUS_LOCK(&sc->sc_bus); 1427 1428 DPRINTFN(16, "real interrupt\n"); 1429 1430 #ifdef USB_DEBUG 1431 if (uhcidebug > 15) { 1432 uhci_dumpregs(sc); 1433 } 1434 #endif 1435 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1436 if (status == 0) { 1437 /* the interrupt was not for us */ 1438 goto done; 1439 } 1440 if (status & (UHCI_STS_RD | UHCI_STS_HSE | 1441 UHCI_STS_HCPE | UHCI_STS_HCH)) { 1442 1443 if (status & UHCI_STS_RD) { 1444 #ifdef USB_DEBUG 1445 printf("%s: resume detect\n", 1446 __FUNCTION__); 1447 #endif 1448 } 1449 if (status & UHCI_STS_HSE) { 1450 printf("%s: host system error\n", 1451 __FUNCTION__); 1452 } 1453 if (status & UHCI_STS_HCPE) { 1454 printf("%s: host controller process error\n", 1455 __FUNCTION__); 1456 } 1457 if (status & UHCI_STS_HCH) { 1458 /* no acknowledge needed */ 1459 DPRINTF("%s: host controller halted\n", 1460 __FUNCTION__); 1461 #ifdef USB_DEBUG 1462 if (uhcidebug > 0) { 1463 uhci_dump_all(sc); 1464 } 1465 #endif 1466 } 1467 } 1468 /* get acknowledge bits */ 1469 status &= (UHCI_STS_USBINT | 1470 UHCI_STS_USBEI | 1471 UHCI_STS_RD | 1472 UHCI_STS_HSE | 1473 UHCI_STS_HCPE); 1474 1475 if (status == 0) { 1476 /* nothing to acknowledge */ 1477 goto done; 1478 } 1479 /* acknowledge interrupts */ 1480 UWRITE2(sc, UHCI_STS, status); 1481 1482 /* poll all the USB transfers */ 1483 uhci_interrupt_poll(sc); 1484 1485 done: 1486 USB_BUS_UNLOCK(&sc->sc_bus); 1487 } 1488 1489 /* 1490 * called when a request does not complete 1491 */ 1492 static void 1493 uhci_timeout(void *arg) 1494 { 1495 struct usb_xfer *xfer = arg; 1496 1497 DPRINTF("xfer=%p\n", xfer); 1498 1499 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1500 1501 /* transfer is transferred */ 1502 uhci_device_done(xfer, USB_ERR_TIMEOUT); 1503 } 1504 1505 static void 1506 uhci_do_poll(struct usb_bus *bus) 1507 { 1508 struct uhci_softc *sc = UHCI_BUS2SC(bus); 1509 1510 USB_BUS_LOCK(&sc->sc_bus); 1511 uhci_interrupt_poll(sc); 1512 USB_BUS_UNLOCK(&sc->sc_bus); 1513 } 1514 1515 static void 1516 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp) 1517 { 1518 uhci_td_t *td; 1519 uhci_td_t *td_next; 1520 uhci_td_t *td_alt_next; 1521 uint32_t average; 1522 uint32_t len_old; 1523 uint8_t shortpkt_old; 1524 uint8_t precompute; 1525 1526 td_alt_next = NULL; 1527 shortpkt_old = temp->shortpkt; 1528 len_old = temp->len; 1529 precompute = 1; 1530 1531 /* software is used to detect short incoming transfers */ 1532 1533 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) { 1534 temp->td_status |= htole32(UHCI_TD_SPD); 1535 } else { 1536 temp->td_status &= ~htole32(UHCI_TD_SPD); 1537 } 1538 1539 temp->ml.buf_offset = 0; 1540 1541 restart: 1542 1543 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1544 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average)); 1545 1546 td = temp->td; 1547 td_next = temp->td_next; 1548 1549 while (1) { 1550 1551 if (temp->len == 0) { 1552 1553 if (temp->shortpkt) { 1554 break; 1555 } 1556 /* send a Zero Length Packet, ZLP, last */ 1557 1558 temp->shortpkt = 1; 1559 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0)); 1560 average = 0; 1561 1562 } else { 1563 1564 average = temp->average; 1565 1566 if (temp->len < average) { 1567 temp->shortpkt = 1; 1568 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1569 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len)); 1570 average = temp->len; 1571 } 1572 } 1573 1574 if (td_next == NULL) { 1575 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__); 1576 } 1577 /* get next TD */ 1578 1579 td = td_next; 1580 td_next = td->obj_next; 1581 1582 /* check if we are pre-computing */ 1583 1584 if (precompute) { 1585 1586 /* update remaining length */ 1587 1588 temp->len -= average; 1589 1590 continue; 1591 } 1592 /* fill out current TD */ 1593 1594 td->td_status = temp->td_status; 1595 td->td_token = temp->td_token; 1596 1597 /* update data toggle */ 1598 1599 temp->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1600 1601 if (average == 0) { 1602 1603 td->len = 0; 1604 td->td_buffer = 0; 1605 td->fix_pc = NULL; 1606 1607 } else { 1608 1609 /* update remaining length */ 1610 1611 temp->len -= average; 1612 1613 td->len = average; 1614 1615 /* fill out buffer pointer and do fixup, if any */ 1616 1617 uhci_mem_layout_fixup(&temp->ml, td); 1618 } 1619 1620 td->alt_next = td_alt_next; 1621 1622 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1623 /* we need to receive these frames one by one ! */ 1624 td->td_status |= htole32(UHCI_TD_IOC); 1625 td->td_next = htole32(UHCI_PTR_T); 1626 } else { 1627 if (td_next) { 1628 /* link the current TD with the next one */ 1629 td->td_next = td_next->td_self; 1630 } 1631 } 1632 1633 usb_pc_cpu_flush(td->page_cache); 1634 } 1635 1636 if (precompute) { 1637 precompute = 0; 1638 1639 /* setup alt next pointer, if any */ 1640 if (temp->last_frame) { 1641 td_alt_next = NULL; 1642 } else { 1643 /* we use this field internally */ 1644 td_alt_next = td_next; 1645 } 1646 1647 /* restore */ 1648 temp->shortpkt = shortpkt_old; 1649 temp->len = len_old; 1650 goto restart; 1651 } 1652 temp->td = td; 1653 temp->td_next = td_next; 1654 } 1655 1656 static uhci_td_t * 1657 uhci_setup_standard_chain(struct usb_xfer *xfer) 1658 { 1659 struct uhci_std_temp temp; 1660 uhci_td_t *td; 1661 uint32_t x; 1662 1663 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1664 xfer->address, UE_GET_ADDR(xfer->endpointno), 1665 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1666 1667 temp.average = xfer->max_frame_size; 1668 temp.max_frame_size = xfer->max_frame_size; 1669 1670 /* toggle the DMA set we are using */ 1671 xfer->flags_int.curr_dma_set ^= 1; 1672 1673 /* get next DMA set */ 1674 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1675 xfer->td_transfer_first = td; 1676 xfer->td_transfer_cache = td; 1677 1678 temp.td = NULL; 1679 temp.td_next = td; 1680 temp.last_frame = 0; 1681 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1682 1683 uhci_mem_layout_init(&temp.ml, xfer); 1684 1685 temp.td_status = 1686 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | 1687 UHCI_TD_ACTIVE)); 1688 1689 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1690 temp.td_status |= htole32(UHCI_TD_LS); 1691 } 1692 temp.td_token = 1693 htole32(UHCI_TD_SET_ENDPT(xfer->endpointno) | 1694 UHCI_TD_SET_DEVADDR(xfer->address)); 1695 1696 if (xfer->endpoint->toggle_next) { 1697 /* DATA1 is next */ 1698 temp.td_token |= htole32(UHCI_TD_SET_DT(1)); 1699 } 1700 /* check if we should prepend a setup message */ 1701 1702 if (xfer->flags_int.control_xfr) { 1703 1704 if (xfer->flags_int.control_hdr) { 1705 1706 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1707 UHCI_TD_SET_ENDPT(0xF)); 1708 temp.td_token |= htole32(UHCI_TD_PID_SETUP | 1709 UHCI_TD_SET_DT(0)); 1710 1711 temp.len = xfer->frlengths[0]; 1712 temp.ml.buf_pc = xfer->frbuffers + 0; 1713 temp.shortpkt = temp.len ? 1 : 0; 1714 /* check for last frame */ 1715 if (xfer->nframes == 1) { 1716 /* no STATUS stage yet, SETUP is last */ 1717 if (xfer->flags_int.control_act) { 1718 temp.last_frame = 1; 1719 temp.setup_alt_next = 0; 1720 } 1721 } 1722 uhci_setup_standard_chain_sub(&temp); 1723 } 1724 x = 1; 1725 } else { 1726 x = 0; 1727 } 1728 1729 while (x != xfer->nframes) { 1730 1731 /* DATA0 / DATA1 message */ 1732 1733 temp.len = xfer->frlengths[x]; 1734 temp.ml.buf_pc = xfer->frbuffers + x; 1735 1736 x++; 1737 1738 if (x == xfer->nframes) { 1739 if (xfer->flags_int.control_xfr) { 1740 /* no STATUS stage yet, DATA is last */ 1741 if (xfer->flags_int.control_act) { 1742 temp.last_frame = 1; 1743 temp.setup_alt_next = 0; 1744 } 1745 } else { 1746 temp.last_frame = 1; 1747 temp.setup_alt_next = 0; 1748 } 1749 } 1750 /* 1751 * Keep previous data toggle, 1752 * device address and endpoint number: 1753 */ 1754 1755 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1756 UHCI_TD_SET_ENDPT(0xF) | 1757 UHCI_TD_SET_DT(1)); 1758 1759 if (temp.len == 0) { 1760 1761 /* make sure that we send an USB packet */ 1762 1763 temp.shortpkt = 0; 1764 1765 } else { 1766 1767 /* regular data transfer */ 1768 1769 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1770 } 1771 1772 /* set endpoint direction */ 1773 1774 temp.td_token |= 1775 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1776 htole32(UHCI_TD_PID_IN) : 1777 htole32(UHCI_TD_PID_OUT); 1778 1779 uhci_setup_standard_chain_sub(&temp); 1780 } 1781 1782 /* check if we should append a status stage */ 1783 1784 if (xfer->flags_int.control_xfr && 1785 !xfer->flags_int.control_act) { 1786 1787 /* 1788 * send a DATA1 message and reverse the current endpoint 1789 * direction 1790 */ 1791 1792 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1793 UHCI_TD_SET_ENDPT(0xF) | 1794 UHCI_TD_SET_DT(1)); 1795 temp.td_token |= 1796 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1797 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) : 1798 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1)); 1799 1800 temp.len = 0; 1801 temp.ml.buf_pc = NULL; 1802 temp.shortpkt = 0; 1803 temp.last_frame = 1; 1804 temp.setup_alt_next = 0; 1805 1806 uhci_setup_standard_chain_sub(&temp); 1807 } 1808 td = temp.td; 1809 1810 /* Ensure that last TD is terminating: */ 1811 td->td_next = htole32(UHCI_PTR_T); 1812 1813 /* set interrupt bit */ 1814 1815 td->td_status |= htole32(UHCI_TD_IOC); 1816 1817 usb_pc_cpu_flush(td->page_cache); 1818 1819 /* must have at least one frame! */ 1820 1821 xfer->td_transfer_last = td; 1822 1823 #ifdef USB_DEBUG 1824 if (uhcidebug > 8) { 1825 DPRINTF("nexttog=%d; data before transfer:\n", 1826 xfer->endpoint->toggle_next); 1827 uhci_dump_tds(xfer->td_transfer_first); 1828 } 1829 #endif 1830 return (xfer->td_transfer_first); 1831 } 1832 1833 /* NOTE: "done" can be run two times in a row, 1834 * from close and from interrupt 1835 */ 1836 1837 static void 1838 uhci_device_done(struct usb_xfer *xfer, usb_error_t error) 1839 { 1840 struct usb_pipe_methods *methods = xfer->endpoint->methods; 1841 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1842 uhci_qh_t *qh; 1843 1844 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1845 1846 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1847 xfer, xfer->endpoint, error); 1848 1849 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1850 if (qh) { 1851 usb_pc_cpu_invalidate(qh->page_cache); 1852 } 1853 if (xfer->flags_int.bandwidth_reclaimed) { 1854 xfer->flags_int.bandwidth_reclaimed = 0; 1855 uhci_rem_loop(sc); 1856 } 1857 if (methods == &uhci_device_bulk_methods) { 1858 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 1859 } 1860 if (methods == &uhci_device_ctrl_methods) { 1861 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1862 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 1863 } else { 1864 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 1865 } 1866 } 1867 if (methods == &uhci_device_intr_methods) { 1868 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 1869 } 1870 /* 1871 * Only finish isochronous transfers once 1872 * which will update "xfer->frlengths". 1873 */ 1874 if (xfer->td_transfer_first && 1875 xfer->td_transfer_last) { 1876 if (methods == &uhci_device_isoc_methods) { 1877 uhci_isoc_done(sc, xfer); 1878 } 1879 xfer->td_transfer_first = NULL; 1880 xfer->td_transfer_last = NULL; 1881 } 1882 /* dequeue transfer and start next transfer */ 1883 usbd_transfer_done(xfer, error); 1884 } 1885 1886 /*------------------------------------------------------------------------* 1887 * uhci bulk support 1888 *------------------------------------------------------------------------*/ 1889 static void 1890 uhci_device_bulk_open(struct usb_xfer *xfer) 1891 { 1892 return; 1893 } 1894 1895 static void 1896 uhci_device_bulk_close(struct usb_xfer *xfer) 1897 { 1898 uhci_device_done(xfer, USB_ERR_CANCELLED); 1899 } 1900 1901 static void 1902 uhci_device_bulk_enter(struct usb_xfer *xfer) 1903 { 1904 return; 1905 } 1906 1907 static void 1908 uhci_device_bulk_start(struct usb_xfer *xfer) 1909 { 1910 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1911 uhci_td_t *td; 1912 uhci_qh_t *qh; 1913 1914 /* setup TD's */ 1915 td = uhci_setup_standard_chain(xfer); 1916 1917 /* setup QH */ 1918 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1919 1920 qh->e_next = td; 1921 qh->qh_e_next = td->td_self; 1922 1923 if (xfer->xroot->udev->flags.self_suspended == 0) { 1924 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 1925 uhci_add_loop(sc); 1926 xfer->flags_int.bandwidth_reclaimed = 1; 1927 } else { 1928 usb_pc_cpu_flush(qh->page_cache); 1929 } 1930 1931 /* put transfer on interrupt queue */ 1932 uhci_transfer_intr_enqueue(xfer); 1933 } 1934 1935 struct usb_pipe_methods uhci_device_bulk_methods = 1936 { 1937 .open = uhci_device_bulk_open, 1938 .close = uhci_device_bulk_close, 1939 .enter = uhci_device_bulk_enter, 1940 .start = uhci_device_bulk_start, 1941 }; 1942 1943 /*------------------------------------------------------------------------* 1944 * uhci control support 1945 *------------------------------------------------------------------------*/ 1946 static void 1947 uhci_device_ctrl_open(struct usb_xfer *xfer) 1948 { 1949 return; 1950 } 1951 1952 static void 1953 uhci_device_ctrl_close(struct usb_xfer *xfer) 1954 { 1955 uhci_device_done(xfer, USB_ERR_CANCELLED); 1956 } 1957 1958 static void 1959 uhci_device_ctrl_enter(struct usb_xfer *xfer) 1960 { 1961 return; 1962 } 1963 1964 static void 1965 uhci_device_ctrl_start(struct usb_xfer *xfer) 1966 { 1967 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1968 uhci_qh_t *qh; 1969 uhci_td_t *td; 1970 1971 /* setup TD's */ 1972 td = uhci_setup_standard_chain(xfer); 1973 1974 /* setup QH */ 1975 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1976 1977 qh->e_next = td; 1978 qh->qh_e_next = td->td_self; 1979 1980 /* 1981 * NOTE: some devices choke on bandwidth- reclamation for control 1982 * transfers 1983 */ 1984 if (xfer->xroot->udev->flags.self_suspended == 0) { 1985 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1986 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 1987 } else { 1988 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 1989 } 1990 } else { 1991 usb_pc_cpu_flush(qh->page_cache); 1992 } 1993 /* put transfer on interrupt queue */ 1994 uhci_transfer_intr_enqueue(xfer); 1995 } 1996 1997 struct usb_pipe_methods uhci_device_ctrl_methods = 1998 { 1999 .open = uhci_device_ctrl_open, 2000 .close = uhci_device_ctrl_close, 2001 .enter = uhci_device_ctrl_enter, 2002 .start = uhci_device_ctrl_start, 2003 }; 2004 2005 /*------------------------------------------------------------------------* 2006 * uhci interrupt support 2007 *------------------------------------------------------------------------*/ 2008 static void 2009 uhci_device_intr_open(struct usb_xfer *xfer) 2010 { 2011 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2012 uint16_t best; 2013 uint16_t bit; 2014 uint16_t x; 2015 2016 best = 0; 2017 bit = UHCI_IFRAMELIST_COUNT / 2; 2018 while (bit) { 2019 if (xfer->interval >= bit) { 2020 x = bit; 2021 best = bit; 2022 while (x & bit) { 2023 if (sc->sc_intr_stat[x] < 2024 sc->sc_intr_stat[best]) { 2025 best = x; 2026 } 2027 x++; 2028 } 2029 break; 2030 } 2031 bit >>= 1; 2032 } 2033 2034 sc->sc_intr_stat[best]++; 2035 xfer->qh_pos = best; 2036 2037 DPRINTFN(3, "best=%d interval=%d\n", 2038 best, xfer->interval); 2039 } 2040 2041 static void 2042 uhci_device_intr_close(struct usb_xfer *xfer) 2043 { 2044 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2045 2046 sc->sc_intr_stat[xfer->qh_pos]--; 2047 2048 uhci_device_done(xfer, USB_ERR_CANCELLED); 2049 } 2050 2051 static void 2052 uhci_device_intr_enter(struct usb_xfer *xfer) 2053 { 2054 return; 2055 } 2056 2057 static void 2058 uhci_device_intr_start(struct usb_xfer *xfer) 2059 { 2060 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2061 uhci_qh_t *qh; 2062 uhci_td_t *td; 2063 2064 /* setup TD's */ 2065 td = uhci_setup_standard_chain(xfer); 2066 2067 /* setup QH */ 2068 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2069 2070 qh->e_next = td; 2071 qh->qh_e_next = td->td_self; 2072 2073 if (xfer->xroot->udev->flags.self_suspended == 0) { 2074 /* enter QHs into the controller data structures */ 2075 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 2076 } else { 2077 usb_pc_cpu_flush(qh->page_cache); 2078 } 2079 2080 /* put transfer on interrupt queue */ 2081 uhci_transfer_intr_enqueue(xfer); 2082 } 2083 2084 struct usb_pipe_methods uhci_device_intr_methods = 2085 { 2086 .open = uhci_device_intr_open, 2087 .close = uhci_device_intr_close, 2088 .enter = uhci_device_intr_enter, 2089 .start = uhci_device_intr_start, 2090 }; 2091 2092 /*------------------------------------------------------------------------* 2093 * uhci isochronous support 2094 *------------------------------------------------------------------------*/ 2095 static void 2096 uhci_device_isoc_open(struct usb_xfer *xfer) 2097 { 2098 uhci_td_t *td; 2099 uint32_t td_token; 2100 uint8_t ds; 2101 2102 td_token = 2103 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 2104 UHCI_TD_IN(0, xfer->endpointno, xfer->address, 0) : 2105 UHCI_TD_OUT(0, xfer->endpointno, xfer->address, 0); 2106 2107 td_token = htole32(td_token); 2108 2109 /* initialize all TD's */ 2110 2111 for (ds = 0; ds != 2; ds++) { 2112 2113 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2114 2115 /* mark TD as inactive */ 2116 td->td_status = htole32(UHCI_TD_IOS); 2117 td->td_token = td_token; 2118 2119 usb_pc_cpu_flush(td->page_cache); 2120 } 2121 } 2122 } 2123 2124 static void 2125 uhci_device_isoc_close(struct usb_xfer *xfer) 2126 { 2127 uhci_device_done(xfer, USB_ERR_CANCELLED); 2128 } 2129 2130 static void 2131 uhci_device_isoc_enter(struct usb_xfer *xfer) 2132 { 2133 struct uhci_mem_layout ml; 2134 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2135 uint32_t nframes; 2136 uint32_t temp; 2137 uint32_t *plen; 2138 2139 #ifdef USB_DEBUG 2140 uint8_t once = 1; 2141 2142 #endif 2143 uhci_td_t *td; 2144 uhci_td_t *td_last = NULL; 2145 uhci_td_t **pp_last; 2146 2147 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2148 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2149 2150 nframes = UREAD2(sc, UHCI_FRNUM); 2151 2152 temp = (nframes - xfer->endpoint->isoc_next) & 2153 (UHCI_VFRAMELIST_COUNT - 1); 2154 2155 if ((xfer->endpoint->is_synced == 0) || 2156 (temp < xfer->nframes)) { 2157 /* 2158 * If there is data underflow or the pipe queue is empty we 2159 * schedule the transfer a few frames ahead of the current 2160 * frame position. Else two isochronous transfers might 2161 * overlap. 2162 */ 2163 xfer->endpoint->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1); 2164 xfer->endpoint->is_synced = 1; 2165 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2166 } 2167 /* 2168 * compute how many milliseconds the insertion is ahead of the 2169 * current frame position: 2170 */ 2171 temp = (xfer->endpoint->isoc_next - nframes) & 2172 (UHCI_VFRAMELIST_COUNT - 1); 2173 2174 /* 2175 * pre-compute when the isochronous transfer will be finished: 2176 */ 2177 xfer->isoc_time_complete = 2178 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2179 xfer->nframes; 2180 2181 /* get the real number of frames */ 2182 2183 nframes = xfer->nframes; 2184 2185 uhci_mem_layout_init(&ml, xfer); 2186 2187 plen = xfer->frlengths; 2188 2189 /* toggle the DMA set we are using */ 2190 xfer->flags_int.curr_dma_set ^= 1; 2191 2192 /* get next DMA set */ 2193 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2194 xfer->td_transfer_first = td; 2195 2196 pp_last = &sc->sc_isoc_p_last[xfer->endpoint->isoc_next]; 2197 2198 /* store starting position */ 2199 2200 xfer->qh_pos = xfer->endpoint->isoc_next; 2201 2202 while (nframes--) { 2203 if (td == NULL) { 2204 panic("%s:%d: out of TD's\n", 2205 __FUNCTION__, __LINE__); 2206 } 2207 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 2208 pp_last = &sc->sc_isoc_p_last[0]; 2209 } 2210 if (*plen > xfer->max_frame_size) { 2211 #ifdef USB_DEBUG 2212 if (once) { 2213 once = 0; 2214 printf("%s: frame length(%d) exceeds %d " 2215 "bytes (frame truncated)\n", 2216 __FUNCTION__, *plen, 2217 xfer->max_frame_size); 2218 } 2219 #endif 2220 *plen = xfer->max_frame_size; 2221 } 2222 /* reuse td_token from last transfer */ 2223 2224 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2225 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen)); 2226 2227 td->len = *plen; 2228 2229 if (td->len == 0) { 2230 /* 2231 * Do not call "uhci_mem_layout_fixup()" when the 2232 * length is zero! 2233 */ 2234 td->td_buffer = 0; 2235 td->fix_pc = NULL; 2236 2237 } else { 2238 2239 /* fill out buffer pointer and do fixup, if any */ 2240 2241 uhci_mem_layout_fixup(&ml, td); 2242 2243 } 2244 2245 /* update status */ 2246 if (nframes == 0) { 2247 td->td_status = htole32 2248 (UHCI_TD_ZERO_ACTLEN 2249 (UHCI_TD_SET_ERRCNT(0) | 2250 UHCI_TD_ACTIVE | 2251 UHCI_TD_IOS | 2252 UHCI_TD_IOC)); 2253 } else { 2254 td->td_status = htole32 2255 (UHCI_TD_ZERO_ACTLEN 2256 (UHCI_TD_SET_ERRCNT(0) | 2257 UHCI_TD_ACTIVE | 2258 UHCI_TD_IOS)); 2259 } 2260 2261 usb_pc_cpu_flush(td->page_cache); 2262 2263 #ifdef USB_DEBUG 2264 if (uhcidebug > 5) { 2265 DPRINTF("TD %d\n", nframes); 2266 uhci_dump_td(td); 2267 } 2268 #endif 2269 /* insert TD into schedule */ 2270 UHCI_APPEND_TD(td, *pp_last); 2271 pp_last++; 2272 2273 plen++; 2274 td_last = td; 2275 td = td->obj_next; 2276 } 2277 2278 xfer->td_transfer_last = td_last; 2279 2280 /* update isoc_next */ 2281 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) & 2282 (UHCI_VFRAMELIST_COUNT - 1); 2283 } 2284 2285 static void 2286 uhci_device_isoc_start(struct usb_xfer *xfer) 2287 { 2288 /* put transfer on interrupt queue */ 2289 uhci_transfer_intr_enqueue(xfer); 2290 } 2291 2292 struct usb_pipe_methods uhci_device_isoc_methods = 2293 { 2294 .open = uhci_device_isoc_open, 2295 .close = uhci_device_isoc_close, 2296 .enter = uhci_device_isoc_enter, 2297 .start = uhci_device_isoc_start, 2298 }; 2299 2300 /*------------------------------------------------------------------------* 2301 * uhci root control support 2302 *------------------------------------------------------------------------* 2303 * Simulate a hardware hub by handling all the necessary requests. 2304 *------------------------------------------------------------------------*/ 2305 2306 static const 2307 struct usb_device_descriptor uhci_devd = 2308 { 2309 sizeof(struct usb_device_descriptor), 2310 UDESC_DEVICE, /* type */ 2311 {0x00, 0x01}, /* USB version */ 2312 UDCLASS_HUB, /* class */ 2313 UDSUBCLASS_HUB, /* subclass */ 2314 UDPROTO_FSHUB, /* protocol */ 2315 64, /* max packet */ 2316 {0}, {0}, {0x00, 0x01}, /* device id */ 2317 1, 2, 0, /* string indicies */ 2318 1 /* # of configurations */ 2319 }; 2320 2321 static const struct uhci_config_desc uhci_confd = { 2322 .confd = { 2323 .bLength = sizeof(struct usb_config_descriptor), 2324 .bDescriptorType = UDESC_CONFIG, 2325 .wTotalLength[0] = sizeof(uhci_confd), 2326 .bNumInterface = 1, 2327 .bConfigurationValue = 1, 2328 .iConfiguration = 0, 2329 .bmAttributes = UC_SELF_POWERED, 2330 .bMaxPower = 0 /* max power */ 2331 }, 2332 .ifcd = { 2333 .bLength = sizeof(struct usb_interface_descriptor), 2334 .bDescriptorType = UDESC_INTERFACE, 2335 .bNumEndpoints = 1, 2336 .bInterfaceClass = UICLASS_HUB, 2337 .bInterfaceSubClass = UISUBCLASS_HUB, 2338 .bInterfaceProtocol = UIPROTO_FSHUB, 2339 }, 2340 .endpd = { 2341 .bLength = sizeof(struct usb_endpoint_descriptor), 2342 .bDescriptorType = UDESC_ENDPOINT, 2343 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 2344 .bmAttributes = UE_INTERRUPT, 2345 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2346 .bInterval = 255, 2347 }, 2348 }; 2349 2350 static const 2351 struct usb_hub_descriptor_min uhci_hubd_piix = 2352 { 2353 .bDescLength = sizeof(uhci_hubd_piix), 2354 .bDescriptorType = UDESC_HUB, 2355 .bNbrPorts = 2, 2356 .wHubCharacteristics = {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0}, 2357 .bPwrOn2PwrGood = 50, 2358 }; 2359 2360 /* 2361 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 2362 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 2363 * should not be used by the USB subsystem. As we cannot issue a 2364 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 2365 * will be enabled as part of the reset. 2366 * 2367 * On the VT83C572, the port cannot be successfully enabled until the 2368 * outstanding "port enable change" and "connection status change" 2369 * events have been reset. 2370 */ 2371 static usb_error_t 2372 uhci_portreset(uhci_softc_t *sc, uint16_t index) 2373 { 2374 uint16_t port; 2375 uint16_t x; 2376 uint8_t lim; 2377 2378 if (index == 1) 2379 port = UHCI_PORTSC1; 2380 else if (index == 2) 2381 port = UHCI_PORTSC2; 2382 else 2383 return (USB_ERR_IOERROR); 2384 2385 /* 2386 * Before we do anything, turn on SOF messages on the USB 2387 * BUS. Some USB devices do not cope without them! 2388 */ 2389 uhci_restart(sc); 2390 2391 x = URWMASK(UREAD2(sc, port)); 2392 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2393 2394 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2395 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 2396 2397 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n", 2398 index, UREAD2(sc, port)); 2399 2400 x = URWMASK(UREAD2(sc, port)); 2401 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2402 2403 2404 mtx_unlock(&sc->sc_bus.bus_mtx); 2405 2406 /* 2407 * This delay needs to be exactly 100us, else some USB devices 2408 * fail to attach! 2409 */ 2410 DELAY(100); 2411 2412 mtx_lock(&sc->sc_bus.bus_mtx); 2413 2414 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n", 2415 index, UREAD2(sc, port)); 2416 2417 x = URWMASK(UREAD2(sc, port)); 2418 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2419 2420 for (lim = 0; lim < 12; lim++) { 2421 2422 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2423 USB_MS_TO_TICKS(usb_port_reset_delay)); 2424 2425 x = UREAD2(sc, port); 2426 2427 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n", 2428 index, lim, x); 2429 2430 if (!(x & UHCI_PORTSC_CCS)) { 2431 /* 2432 * No device is connected (or was disconnected 2433 * during reset). Consider the port reset. 2434 * The delay must be long enough to ensure on 2435 * the initial iteration that the device 2436 * connection will have been registered. 50ms 2437 * appears to be sufficient, but 20ms is not. 2438 */ 2439 DPRINTFN(4, "uhci port %d loop %u, device detached\n", 2440 index, lim); 2441 goto done; 2442 } 2443 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 2444 /* 2445 * Port enabled changed and/or connection 2446 * status changed were set. Reset either or 2447 * both raised flags (by writing a 1 to that 2448 * bit), and wait again for state to settle. 2449 */ 2450 UWRITE2(sc, port, URWMASK(x) | 2451 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 2452 continue; 2453 } 2454 if (x & UHCI_PORTSC_PE) { 2455 /* port is enabled */ 2456 goto done; 2457 } 2458 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 2459 } 2460 2461 DPRINTFN(2, "uhci port %d reset timed out\n", index); 2462 return (USB_ERR_TIMEOUT); 2463 2464 done: 2465 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n", 2466 index, UREAD2(sc, port)); 2467 2468 sc->sc_isreset = 1; 2469 return (USB_ERR_NORMAL_COMPLETION); 2470 } 2471 2472 static usb_error_t 2473 uhci_roothub_exec(struct usb_device *udev, 2474 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2475 { 2476 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 2477 const void *ptr; 2478 const char *str_ptr; 2479 uint16_t x; 2480 uint16_t port; 2481 uint16_t value; 2482 uint16_t index; 2483 uint16_t status; 2484 uint16_t change; 2485 uint16_t len; 2486 usb_error_t err; 2487 2488 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2489 2490 /* buffer reset */ 2491 ptr = (const void *)&sc->sc_hub_desc.temp; 2492 len = 0; 2493 err = 0; 2494 2495 value = UGETW(req->wValue); 2496 index = UGETW(req->wIndex); 2497 2498 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2499 "wValue=0x%04x wIndex=0x%04x\n", 2500 req->bmRequestType, req->bRequest, 2501 UGETW(req->wLength), value, index); 2502 2503 #define C(x,y) ((x) | ((y) << 8)) 2504 switch (C(req->bRequest, req->bmRequestType)) { 2505 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2506 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2507 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2508 /* 2509 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2510 * for the integrated root hub. 2511 */ 2512 break; 2513 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2514 len = 1; 2515 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2516 break; 2517 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2518 switch (value >> 8) { 2519 case UDESC_DEVICE: 2520 if ((value & 0xff) != 0) { 2521 err = USB_ERR_IOERROR; 2522 goto done; 2523 } 2524 len = sizeof(uhci_devd); 2525 ptr = (const void *)&uhci_devd; 2526 break; 2527 2528 case UDESC_CONFIG: 2529 if ((value & 0xff) != 0) { 2530 err = USB_ERR_IOERROR; 2531 goto done; 2532 } 2533 len = sizeof(uhci_confd); 2534 ptr = (const void *)&uhci_confd; 2535 break; 2536 2537 case UDESC_STRING: 2538 switch (value & 0xff) { 2539 case 0: /* Language table */ 2540 str_ptr = "\001"; 2541 break; 2542 2543 case 1: /* Vendor */ 2544 str_ptr = sc->sc_vendor; 2545 break; 2546 2547 case 2: /* Product */ 2548 str_ptr = "UHCI root HUB"; 2549 break; 2550 2551 default: 2552 str_ptr = ""; 2553 break; 2554 } 2555 2556 len = usb_make_str_desc 2557 (sc->sc_hub_desc.temp, 2558 sizeof(sc->sc_hub_desc.temp), 2559 str_ptr); 2560 break; 2561 2562 default: 2563 err = USB_ERR_IOERROR; 2564 goto done; 2565 } 2566 break; 2567 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2568 len = 1; 2569 sc->sc_hub_desc.temp[0] = 0; 2570 break; 2571 case C(UR_GET_STATUS, UT_READ_DEVICE): 2572 len = 2; 2573 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2574 break; 2575 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2576 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2577 len = 2; 2578 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2579 break; 2580 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2581 if (value >= UHCI_MAX_DEVICES) { 2582 err = USB_ERR_IOERROR; 2583 goto done; 2584 } 2585 sc->sc_addr = value; 2586 break; 2587 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2588 if ((value != 0) && (value != 1)) { 2589 err = USB_ERR_IOERROR; 2590 goto done; 2591 } 2592 sc->sc_conf = value; 2593 break; 2594 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2595 break; 2596 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2597 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2598 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2599 err = USB_ERR_IOERROR; 2600 goto done; 2601 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2602 break; 2603 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2604 break; 2605 /* Hub requests */ 2606 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2607 break; 2608 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2609 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE " 2610 "port=%d feature=%d\n", 2611 index, value); 2612 if (index == 1) 2613 port = UHCI_PORTSC1; 2614 else if (index == 2) 2615 port = UHCI_PORTSC2; 2616 else { 2617 err = USB_ERR_IOERROR; 2618 goto done; 2619 } 2620 switch (value) { 2621 case UHF_PORT_ENABLE: 2622 x = URWMASK(UREAD2(sc, port)); 2623 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2624 break; 2625 case UHF_PORT_SUSPEND: 2626 x = URWMASK(UREAD2(sc, port)); 2627 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP)); 2628 break; 2629 case UHF_PORT_RESET: 2630 x = URWMASK(UREAD2(sc, port)); 2631 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2632 break; 2633 case UHF_C_PORT_CONNECTION: 2634 x = URWMASK(UREAD2(sc, port)); 2635 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2636 break; 2637 case UHF_C_PORT_ENABLE: 2638 x = URWMASK(UREAD2(sc, port)); 2639 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2640 break; 2641 case UHF_C_PORT_OVER_CURRENT: 2642 x = URWMASK(UREAD2(sc, port)); 2643 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2644 break; 2645 case UHF_C_PORT_RESET: 2646 sc->sc_isreset = 0; 2647 err = USB_ERR_NORMAL_COMPLETION; 2648 goto done; 2649 case UHF_C_PORT_SUSPEND: 2650 sc->sc_isresumed &= ~(1 << index); 2651 break; 2652 case UHF_PORT_CONNECTION: 2653 case UHF_PORT_OVER_CURRENT: 2654 case UHF_PORT_POWER: 2655 case UHF_PORT_LOW_SPEED: 2656 default: 2657 err = USB_ERR_IOERROR; 2658 goto done; 2659 } 2660 break; 2661 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2662 if (index == 1) 2663 port = UHCI_PORTSC1; 2664 else if (index == 2) 2665 port = UHCI_PORTSC2; 2666 else { 2667 err = USB_ERR_IOERROR; 2668 goto done; 2669 } 2670 len = 1; 2671 sc->sc_hub_desc.temp[0] = 2672 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2673 UHCI_PORTSC_LS_SHIFT); 2674 break; 2675 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2676 if ((value & 0xff) != 0) { 2677 err = USB_ERR_IOERROR; 2678 goto done; 2679 } 2680 len = sizeof(uhci_hubd_piix); 2681 ptr = (const void *)&uhci_hubd_piix; 2682 break; 2683 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2684 len = 16; 2685 memset(sc->sc_hub_desc.temp, 0, 16); 2686 break; 2687 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2688 if (index == 1) 2689 port = UHCI_PORTSC1; 2690 else if (index == 2) 2691 port = UHCI_PORTSC2; 2692 else { 2693 err = USB_ERR_IOERROR; 2694 goto done; 2695 } 2696 x = UREAD2(sc, port); 2697 status = change = 0; 2698 if (x & UHCI_PORTSC_CCS) 2699 status |= UPS_CURRENT_CONNECT_STATUS; 2700 if (x & UHCI_PORTSC_CSC) 2701 change |= UPS_C_CONNECT_STATUS; 2702 if (x & UHCI_PORTSC_PE) 2703 status |= UPS_PORT_ENABLED; 2704 if (x & UHCI_PORTSC_POEDC) 2705 change |= UPS_C_PORT_ENABLED; 2706 if (x & UHCI_PORTSC_OCI) 2707 status |= UPS_OVERCURRENT_INDICATOR; 2708 if (x & UHCI_PORTSC_OCIC) 2709 change |= UPS_C_OVERCURRENT_INDICATOR; 2710 if (x & UHCI_PORTSC_LSDA) 2711 status |= UPS_LOW_SPEED; 2712 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) { 2713 /* need to do a write back */ 2714 UWRITE2(sc, port, URWMASK(x)); 2715 2716 /* wait 20ms for resume sequence to complete */ 2717 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 2718 2719 /* clear suspend and resume detect */ 2720 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD | 2721 UHCI_PORTSC_SUSP)); 2722 2723 /* wait a little bit */ 2724 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500); 2725 2726 sc->sc_isresumed |= (1 << index); 2727 2728 } else if (x & UHCI_PORTSC_SUSP) { 2729 status |= UPS_SUSPEND; 2730 } 2731 status |= UPS_PORT_POWER; 2732 if (sc->sc_isresumed & (1 << index)) 2733 change |= UPS_C_SUSPEND; 2734 if (sc->sc_isreset) 2735 change |= UPS_C_PORT_RESET; 2736 USETW(sc->sc_hub_desc.ps.wPortStatus, status); 2737 USETW(sc->sc_hub_desc.ps.wPortChange, change); 2738 len = sizeof(sc->sc_hub_desc.ps); 2739 break; 2740 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2741 err = USB_ERR_IOERROR; 2742 goto done; 2743 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2744 break; 2745 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2746 if (index == 1) 2747 port = UHCI_PORTSC1; 2748 else if (index == 2) 2749 port = UHCI_PORTSC2; 2750 else { 2751 err = USB_ERR_IOERROR; 2752 goto done; 2753 } 2754 switch (value) { 2755 case UHF_PORT_ENABLE: 2756 x = URWMASK(UREAD2(sc, port)); 2757 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2758 break; 2759 case UHF_PORT_SUSPEND: 2760 x = URWMASK(UREAD2(sc, port)); 2761 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2762 break; 2763 case UHF_PORT_RESET: 2764 err = uhci_portreset(sc, index); 2765 goto done; 2766 case UHF_PORT_POWER: 2767 /* pretend we turned on power */ 2768 err = USB_ERR_NORMAL_COMPLETION; 2769 goto done; 2770 case UHF_C_PORT_CONNECTION: 2771 case UHF_C_PORT_ENABLE: 2772 case UHF_C_PORT_OVER_CURRENT: 2773 case UHF_PORT_CONNECTION: 2774 case UHF_PORT_OVER_CURRENT: 2775 case UHF_PORT_LOW_SPEED: 2776 case UHF_C_PORT_SUSPEND: 2777 case UHF_C_PORT_RESET: 2778 default: 2779 err = USB_ERR_IOERROR; 2780 goto done; 2781 } 2782 break; 2783 default: 2784 err = USB_ERR_IOERROR; 2785 goto done; 2786 } 2787 done: 2788 *plength = len; 2789 *pptr = ptr; 2790 return (err); 2791 } 2792 2793 /* 2794 * This routine is executed periodically and simulates interrupts from 2795 * the root controller interrupt pipe for port status change: 2796 */ 2797 static void 2798 uhci_root_intr(uhci_softc_t *sc) 2799 { 2800 DPRINTFN(21, "\n"); 2801 2802 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2803 2804 sc->sc_hub_idata[0] = 0; 2805 2806 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | 2807 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2808 sc->sc_hub_idata[0] |= 1 << 1; 2809 } 2810 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | 2811 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2812 sc->sc_hub_idata[0] |= 1 << 2; 2813 } 2814 2815 /* restart timer */ 2816 usb_callout_reset(&sc->sc_root_intr, hz, 2817 (void *)&uhci_root_intr, sc); 2818 2819 if (sc->sc_hub_idata[0] != 0) { 2820 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2821 sizeof(sc->sc_hub_idata)); 2822 } 2823 } 2824 2825 static void 2826 uhci_xfer_setup(struct usb_setup_params *parm) 2827 { 2828 struct usb_page_search page_info; 2829 struct usb_page_cache *pc; 2830 uhci_softc_t *sc; 2831 struct usb_xfer *xfer; 2832 void *last_obj; 2833 uint32_t ntd; 2834 uint32_t nqh; 2835 uint32_t nfixup; 2836 uint32_t n; 2837 uint16_t align; 2838 2839 sc = UHCI_BUS2SC(parm->udev->bus); 2840 xfer = parm->curr_xfer; 2841 2842 parm->hc_max_packet_size = 0x500; 2843 parm->hc_max_packet_count = 1; 2844 parm->hc_max_frame_size = 0x500; 2845 2846 /* 2847 * compute ntd and nqh 2848 */ 2849 if (parm->methods == &uhci_device_ctrl_methods) { 2850 xfer->flags_int.bdma_enable = 1; 2851 xfer->flags_int.bdma_no_post_sync = 1; 2852 2853 usbd_transfer_setup_sub(parm); 2854 2855 /* see EHCI HC driver for proof of "ntd" formula */ 2856 2857 nqh = 1; 2858 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2859 + (xfer->max_data_length / xfer->max_frame_size)); 2860 2861 } else if (parm->methods == &uhci_device_bulk_methods) { 2862 xfer->flags_int.bdma_enable = 1; 2863 xfer->flags_int.bdma_no_post_sync = 1; 2864 2865 usbd_transfer_setup_sub(parm); 2866 2867 nqh = 1; 2868 ntd = ((2 * xfer->nframes) 2869 + (xfer->max_data_length / xfer->max_frame_size)); 2870 2871 } else if (parm->methods == &uhci_device_intr_methods) { 2872 xfer->flags_int.bdma_enable = 1; 2873 xfer->flags_int.bdma_no_post_sync = 1; 2874 2875 usbd_transfer_setup_sub(parm); 2876 2877 nqh = 1; 2878 ntd = ((2 * xfer->nframes) 2879 + (xfer->max_data_length / xfer->max_frame_size)); 2880 2881 } else if (parm->methods == &uhci_device_isoc_methods) { 2882 xfer->flags_int.bdma_enable = 1; 2883 xfer->flags_int.bdma_no_post_sync = 1; 2884 2885 usbd_transfer_setup_sub(parm); 2886 2887 nqh = 0; 2888 ntd = xfer->nframes; 2889 2890 } else { 2891 2892 usbd_transfer_setup_sub(parm); 2893 2894 nqh = 0; 2895 ntd = 0; 2896 } 2897 2898 if (parm->err) { 2899 return; 2900 } 2901 /* 2902 * NOTE: the UHCI controller requires that 2903 * every packet must be contiguous on 2904 * the same USB memory page ! 2905 */ 2906 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1; 2907 2908 /* 2909 * Compute a suitable power of two alignment 2910 * for our "max_frame_size" fixup buffer(s): 2911 */ 2912 align = xfer->max_frame_size; 2913 n = 0; 2914 while (align) { 2915 align >>= 1; 2916 n++; 2917 } 2918 2919 /* check for power of two */ 2920 if (!(xfer->max_frame_size & 2921 (xfer->max_frame_size - 1))) { 2922 n--; 2923 } 2924 /* 2925 * We don't allow alignments of 2926 * less than 8 bytes: 2927 * 2928 * NOTE: Allocating using an aligment 2929 * of 1 byte has special meaning! 2930 */ 2931 if (n < 3) { 2932 n = 3; 2933 } 2934 align = (1 << n); 2935 2936 if (usbd_transfer_setup_sub_malloc( 2937 parm, &pc, xfer->max_frame_size, 2938 align, nfixup)) { 2939 parm->err = USB_ERR_NOMEM; 2940 return; 2941 } 2942 xfer->buf_fixup = pc; 2943 2944 alloc_dma_set: 2945 2946 if (parm->err) { 2947 return; 2948 } 2949 last_obj = NULL; 2950 2951 if (usbd_transfer_setup_sub_malloc( 2952 parm, &pc, sizeof(uhci_td_t), 2953 UHCI_TD_ALIGN, ntd)) { 2954 parm->err = USB_ERR_NOMEM; 2955 return; 2956 } 2957 if (parm->buf) { 2958 for (n = 0; n != ntd; n++) { 2959 uhci_td_t *td; 2960 2961 usbd_get_page(pc + n, 0, &page_info); 2962 2963 td = page_info.buffer; 2964 2965 /* init TD */ 2966 if ((parm->methods == &uhci_device_bulk_methods) || 2967 (parm->methods == &uhci_device_ctrl_methods) || 2968 (parm->methods == &uhci_device_intr_methods)) { 2969 /* set depth first bit */ 2970 td->td_self = htole32(page_info.physaddr | 2971 UHCI_PTR_TD | UHCI_PTR_VF); 2972 } else { 2973 td->td_self = htole32(page_info.physaddr | 2974 UHCI_PTR_TD); 2975 } 2976 2977 td->obj_next = last_obj; 2978 td->page_cache = pc + n; 2979 2980 last_obj = td; 2981 2982 usb_pc_cpu_flush(pc + n); 2983 } 2984 } 2985 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2986 2987 last_obj = NULL; 2988 2989 if (usbd_transfer_setup_sub_malloc( 2990 parm, &pc, sizeof(uhci_qh_t), 2991 UHCI_QH_ALIGN, nqh)) { 2992 parm->err = USB_ERR_NOMEM; 2993 return; 2994 } 2995 if (parm->buf) { 2996 for (n = 0; n != nqh; n++) { 2997 uhci_qh_t *qh; 2998 2999 usbd_get_page(pc + n, 0, &page_info); 3000 3001 qh = page_info.buffer; 3002 3003 /* init QH */ 3004 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH); 3005 qh->obj_next = last_obj; 3006 qh->page_cache = pc + n; 3007 3008 last_obj = qh; 3009 3010 usb_pc_cpu_flush(pc + n); 3011 } 3012 } 3013 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3014 3015 if (!xfer->flags_int.curr_dma_set) { 3016 xfer->flags_int.curr_dma_set = 1; 3017 goto alloc_dma_set; 3018 } 3019 } 3020 3021 static void 3022 uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3023 struct usb_endpoint *ep) 3024 { 3025 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 3026 3027 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3028 ep, udev->address, 3029 edesc->bEndpointAddress, udev->flags.usb_mode, 3030 sc->sc_addr); 3031 3032 if (udev->device_index != sc->sc_addr) { 3033 switch (edesc->bmAttributes & UE_XFERTYPE) { 3034 case UE_CONTROL: 3035 ep->methods = &uhci_device_ctrl_methods; 3036 break; 3037 case UE_INTERRUPT: 3038 ep->methods = &uhci_device_intr_methods; 3039 break; 3040 case UE_ISOCHRONOUS: 3041 if (udev->speed == USB_SPEED_FULL) { 3042 ep->methods = &uhci_device_isoc_methods; 3043 } 3044 break; 3045 case UE_BULK: 3046 ep->methods = &uhci_device_bulk_methods; 3047 break; 3048 default: 3049 /* do nothing */ 3050 break; 3051 } 3052 } 3053 } 3054 3055 static void 3056 uhci_xfer_unsetup(struct usb_xfer *xfer) 3057 { 3058 return; 3059 } 3060 3061 static void 3062 uhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3063 { 3064 /* 3065 * Wait until hardware has finished any possible use of the 3066 * transfer descriptor(s) and QH 3067 */ 3068 *pus = (1125); /* microseconds */ 3069 } 3070 3071 static void 3072 uhci_device_resume(struct usb_device *udev) 3073 { 3074 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3075 struct usb_xfer *xfer; 3076 struct usb_pipe_methods *methods; 3077 uhci_qh_t *qh; 3078 3079 DPRINTF("\n"); 3080 3081 USB_BUS_LOCK(udev->bus); 3082 3083 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3084 3085 if (xfer->xroot->udev == udev) { 3086 3087 methods = xfer->endpoint->methods; 3088 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3089 3090 if (methods == &uhci_device_bulk_methods) { 3091 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 3092 uhci_add_loop(sc); 3093 xfer->flags_int.bandwidth_reclaimed = 1; 3094 } 3095 if (methods == &uhci_device_ctrl_methods) { 3096 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3097 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 3098 } else { 3099 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 3100 } 3101 } 3102 if (methods == &uhci_device_intr_methods) { 3103 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3104 } 3105 } 3106 } 3107 3108 USB_BUS_UNLOCK(udev->bus); 3109 3110 return; 3111 } 3112 3113 static void 3114 uhci_device_suspend(struct usb_device *udev) 3115 { 3116 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3117 struct usb_xfer *xfer; 3118 struct usb_pipe_methods *methods; 3119 uhci_qh_t *qh; 3120 3121 DPRINTF("\n"); 3122 3123 USB_BUS_LOCK(udev->bus); 3124 3125 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3126 3127 if (xfer->xroot->udev == udev) { 3128 3129 methods = xfer->endpoint->methods; 3130 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3131 3132 if (xfer->flags_int.bandwidth_reclaimed) { 3133 xfer->flags_int.bandwidth_reclaimed = 0; 3134 uhci_rem_loop(sc); 3135 } 3136 if (methods == &uhci_device_bulk_methods) { 3137 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 3138 } 3139 if (methods == &uhci_device_ctrl_methods) { 3140 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3141 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 3142 } else { 3143 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 3144 } 3145 } 3146 if (methods == &uhci_device_intr_methods) { 3147 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3148 } 3149 } 3150 } 3151 3152 USB_BUS_UNLOCK(udev->bus); 3153 3154 return; 3155 } 3156 3157 static void 3158 uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3159 { 3160 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3161 3162 switch (state) { 3163 case USB_HW_POWER_SUSPEND: 3164 case USB_HW_POWER_SHUTDOWN: 3165 uhci_suspend(sc); 3166 break; 3167 case USB_HW_POWER_RESUME: 3168 uhci_resume(sc); 3169 break; 3170 default: 3171 break; 3172 } 3173 } 3174 3175 static void 3176 uhci_set_hw_power(struct usb_bus *bus) 3177 { 3178 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3179 uint32_t flags; 3180 3181 DPRINTF("\n"); 3182 3183 USB_BUS_LOCK(bus); 3184 3185 flags = bus->hw_power_state; 3186 3187 /* 3188 * WARNING: Some FULL speed USB devices require periodic SOF 3189 * messages! If any USB devices are connected through the 3190 * UHCI, power save will be disabled! 3191 */ 3192 if (flags & (USB_HW_POWER_CONTROL | 3193 USB_HW_POWER_NON_ROOT_HUB | 3194 USB_HW_POWER_BULK | 3195 USB_HW_POWER_INTERRUPT | 3196 USB_HW_POWER_ISOC)) { 3197 DPRINTF("Some USB transfer is " 3198 "active on unit %u.\n", 3199 device_get_unit(sc->sc_bus.bdev)); 3200 uhci_restart(sc); 3201 } else { 3202 DPRINTF("Power save on unit %u.\n", 3203 device_get_unit(sc->sc_bus.bdev)); 3204 UHCICMD(sc, UHCI_CMD_MAXP); 3205 } 3206 3207 USB_BUS_UNLOCK(bus); 3208 3209 return; 3210 } 3211 3212 3213 struct usb_bus_methods uhci_bus_methods = 3214 { 3215 .endpoint_init = uhci_ep_init, 3216 .xfer_setup = uhci_xfer_setup, 3217 .xfer_unsetup = uhci_xfer_unsetup, 3218 .get_dma_delay = uhci_get_dma_delay, 3219 .device_resume = uhci_device_resume, 3220 .device_suspend = uhci_device_suspend, 3221 .set_hw_power = uhci_set_hw_power, 3222 .set_hw_power_sleep = uhci_set_hw_power_sleep, 3223 .roothub_exec = uhci_roothub_exec, 3224 .xfer_poll = uhci_do_poll, 3225 }; 3226