1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * USB Universal Host Controller driver. 33 * Handles e.g. PIIX3 and PIIX4. 34 * 35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 38 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 39 */ 40 41 #include <dev/usb/usb.h> 42 #include <dev/usb/usb_mfunc.h> 43 #include <dev/usb/usb_error.h> 44 45 #define USB_DEBUG_VAR uhcidebug 46 47 #include <dev/usb/usb_core.h> 48 #include <dev/usb/usb_debug.h> 49 #include <dev/usb/usb_busdma.h> 50 #include <dev/usb/usb_process.h> 51 #include <dev/usb/usb_transfer.h> 52 #include <dev/usb/usb_device.h> 53 #include <dev/usb/usb_hub.h> 54 #include <dev/usb/usb_util.h> 55 56 #include <dev/usb/usb_controller.h> 57 #include <dev/usb/usb_bus.h> 58 #include <dev/usb/controller/uhci.h> 59 60 #define alt_next next 61 #define UHCI_BUS2SC(bus) \ 62 ((uhci_softc_t *)(((uint8_t *)(bus)) - \ 63 ((uint8_t *)&(((uhci_softc_t *)0)->sc_bus)))) 64 65 #if USB_DEBUG 66 static int uhcidebug = 0; 67 static int uhcinoloop = 0; 68 69 SYSCTL_NODE(_hw_usb2, OID_AUTO, uhci, CTLFLAG_RW, 0, "USB uhci"); 70 SYSCTL_INT(_hw_usb2_uhci, OID_AUTO, debug, CTLFLAG_RW, 71 &uhcidebug, 0, "uhci debug level"); 72 SYSCTL_INT(_hw_usb2_uhci, OID_AUTO, loop, CTLFLAG_RW, 73 &uhcinoloop, 0, "uhci noloop"); 74 static void uhci_dumpregs(uhci_softc_t *sc); 75 static void uhci_dump_tds(uhci_td_t *td); 76 77 #endif 78 79 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 80 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 81 #define UWRITE1(sc, r, x) \ 82 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 83 } while (/*CONSTCOND*/0) 84 #define UWRITE2(sc, r, x) \ 85 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 86 } while (/*CONSTCOND*/0) 87 #define UWRITE4(sc, r, x) \ 88 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 89 } while (/*CONSTCOND*/0) 90 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 91 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 92 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 93 94 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 95 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 96 97 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 98 99 #define UHCI_INTR_ENDPT 1 100 101 struct uhci_mem_layout { 102 103 struct usb2_page_search buf_res; 104 struct usb2_page_search fix_res; 105 106 struct usb2_page_cache *buf_pc; 107 struct usb2_page_cache *fix_pc; 108 109 uint32_t buf_offset; 110 111 uint16_t max_frame_size; 112 }; 113 114 struct uhci_std_temp { 115 116 struct uhci_mem_layout ml; 117 uhci_td_t *td; 118 uhci_td_t *td_next; 119 uint32_t average; 120 uint32_t td_status; 121 uint32_t td_token; 122 uint32_t len; 123 uint16_t max_frame_size; 124 uint8_t shortpkt; 125 uint8_t setup_alt_next; 126 uint8_t last_frame; 127 }; 128 129 extern struct usb2_bus_methods uhci_bus_methods; 130 extern struct usb2_pipe_methods uhci_device_bulk_methods; 131 extern struct usb2_pipe_methods uhci_device_ctrl_methods; 132 extern struct usb2_pipe_methods uhci_device_intr_methods; 133 extern struct usb2_pipe_methods uhci_device_isoc_methods; 134 135 static void uhci_do_poll(struct usb2_bus *); 136 static void uhci_device_done(struct usb2_xfer *, usb2_error_t); 137 static void uhci_transfer_intr_enqueue(struct usb2_xfer *); 138 static void uhci_timeout(void *); 139 static uint8_t uhci_check_transfer(struct usb2_xfer *); 140 static void uhci_root_intr(uhci_softc_t *sc); 141 142 void 143 uhci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 144 { 145 struct uhci_softc *sc = UHCI_BUS2SC(bus); 146 uint32_t i; 147 148 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 149 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN); 150 151 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg, 152 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 153 154 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg, 155 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 156 157 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 158 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 159 160 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg, 161 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 162 163 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg, 164 sizeof(uhci_td_t), UHCI_TD_ALIGN); 165 166 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) { 167 cb(bus, sc->sc_hw.isoc_start_pc + i, 168 sc->sc_hw.isoc_start_pg + i, 169 sizeof(uhci_td_t), UHCI_TD_ALIGN); 170 } 171 172 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) { 173 cb(bus, sc->sc_hw.intr_start_pc + i, 174 sc->sc_hw.intr_start_pg + i, 175 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 176 } 177 } 178 179 static void 180 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb2_xfer *xfer) 181 { 182 ml->buf_pc = xfer->frbuffers + 0; 183 ml->fix_pc = xfer->buf_fixup; 184 185 ml->buf_offset = 0; 186 187 ml->max_frame_size = xfer->max_frame_size; 188 } 189 190 static void 191 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td) 192 { 193 usb2_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res); 194 195 if (ml->buf_res.length < td->len) { 196 197 /* need to do a fixup */ 198 199 usb2_get_page(ml->fix_pc, 0, &ml->fix_res); 200 201 td->td_buffer = htole32(ml->fix_res.physaddr); 202 203 /* 204 * The UHCI driver cannot handle 205 * page crossings, so a fixup is 206 * needed: 207 * 208 * +----+----+ - - - 209 * | YYY|Y | 210 * +----+----+ - - - 211 * \ \ 212 * \ \ 213 * +----+ 214 * |YYYY| (fixup) 215 * +----+ 216 */ 217 218 if ((td->td_token & htole32(UHCI_TD_PID)) == 219 htole32(UHCI_TD_PID_IN)) { 220 td->fix_pc = ml->fix_pc; 221 usb2_pc_cpu_invalidate(ml->fix_pc); 222 223 } else { 224 td->fix_pc = NULL; 225 226 /* copy data to fixup location */ 227 228 usb2_copy_out(ml->buf_pc, ml->buf_offset, 229 ml->fix_res.buffer, td->len); 230 231 usb2_pc_cpu_flush(ml->fix_pc); 232 } 233 234 /* prepare next fixup */ 235 236 ml->fix_pc++; 237 238 } else { 239 240 td->td_buffer = htole32(ml->buf_res.physaddr); 241 td->fix_pc = NULL; 242 } 243 244 /* prepare next data location */ 245 246 ml->buf_offset += td->len; 247 } 248 249 void 250 uhci_reset(uhci_softc_t *sc) 251 { 252 struct usb2_page_search buf_res; 253 uint16_t n; 254 255 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 256 257 DPRINTF("resetting the HC\n"); 258 259 /* disable interrupts */ 260 261 UWRITE2(sc, UHCI_INTR, 0); 262 263 /* global reset */ 264 265 UHCICMD(sc, UHCI_CMD_GRESET); 266 267 /* wait */ 268 269 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 270 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 271 272 /* terminate all transfers */ 273 274 UHCICMD(sc, UHCI_CMD_HCRESET); 275 276 /* the reset bit goes low when the controller is done */ 277 278 n = UHCI_RESET_TIMEOUT; 279 while (n--) { 280 /* wait one millisecond */ 281 282 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 283 284 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) { 285 goto done_1; 286 } 287 } 288 289 device_printf(sc->sc_bus.bdev, 290 "controller did not reset\n"); 291 292 done_1: 293 294 n = 10; 295 while (n--) { 296 /* wait one millisecond */ 297 298 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 299 300 /* check if HC is stopped */ 301 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 302 goto done_2; 303 } 304 } 305 306 device_printf(sc->sc_bus.bdev, 307 "controller did not stop\n"); 308 309 done_2: 310 311 /* reload the configuration */ 312 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 313 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr); 314 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 315 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 316 317 USB_BUS_UNLOCK(&sc->sc_bus); 318 319 /* stop root interrupt */ 320 usb2_callout_drain(&sc->sc_root_intr); 321 322 USB_BUS_LOCK(&sc->sc_bus); 323 } 324 325 static void 326 uhci_start(uhci_softc_t *sc) 327 { 328 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 329 330 DPRINTFN(2, "enabling\n"); 331 332 /* enable interrupts */ 333 334 UWRITE2(sc, UHCI_INTR, 335 (UHCI_INTR_TOCRCIE | 336 UHCI_INTR_RIE | 337 UHCI_INTR_IOCE | 338 UHCI_INTR_SPIE)); 339 340 /* 341 * assume 64 byte packets at frame end and start HC controller 342 */ 343 344 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 345 346 uint8_t n = 10; 347 348 while (n--) { 349 /* wait one millisecond */ 350 351 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 352 353 /* check that controller has started */ 354 355 if (!(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH)) { 356 goto done; 357 } 358 } 359 360 device_printf(sc->sc_bus.bdev, 361 "cannot start HC controller\n"); 362 363 done: 364 /* start root interrupt */ 365 uhci_root_intr(sc); 366 } 367 368 static struct uhci_qh * 369 uhci_init_qh(struct usb2_page_cache *pc) 370 { 371 struct usb2_page_search buf_res; 372 struct uhci_qh *qh; 373 374 usb2_get_page(pc, 0, &buf_res); 375 376 qh = buf_res.buffer; 377 378 qh->qh_self = 379 htole32(buf_res.physaddr) | 380 htole32(UHCI_PTR_QH); 381 382 qh->page_cache = pc; 383 384 return (qh); 385 } 386 387 static struct uhci_td * 388 uhci_init_td(struct usb2_page_cache *pc) 389 { 390 struct usb2_page_search buf_res; 391 struct uhci_td *td; 392 393 usb2_get_page(pc, 0, &buf_res); 394 395 td = buf_res.buffer; 396 397 td->td_self = 398 htole32(buf_res.physaddr) | 399 htole32(UHCI_PTR_TD); 400 401 td->page_cache = pc; 402 403 return (td); 404 } 405 406 usb2_error_t 407 uhci_init(uhci_softc_t *sc) 408 { 409 uint16_t bit; 410 uint16_t x; 411 uint16_t y; 412 413 DPRINTF("start\n"); 414 415 usb2_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_mtx, 0); 416 417 #if USB_DEBUG 418 if (uhcidebug > 2) { 419 uhci_dumpregs(sc); 420 } 421 #endif 422 sc->sc_saved_sof = 0x40; /* default value */ 423 sc->sc_saved_frnum = 0; /* default frame number */ 424 425 /* 426 * Setup QH's 427 */ 428 sc->sc_ls_ctl_p_last = 429 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc); 430 431 sc->sc_fs_ctl_p_last = 432 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc); 433 434 sc->sc_bulk_p_last = 435 uhci_init_qh(&sc->sc_hw.bulk_start_pc); 436 #if 0 437 sc->sc_reclaim_qh_p = 438 sc->sc_fs_ctl_p_last; 439 #else 440 /* setup reclaim looping point */ 441 sc->sc_reclaim_qh_p = 442 sc->sc_bulk_p_last; 443 #endif 444 445 sc->sc_last_qh_p = 446 uhci_init_qh(&sc->sc_hw.last_qh_pc); 447 448 sc->sc_last_td_p = 449 uhci_init_td(&sc->sc_hw.last_td_pc); 450 451 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 452 sc->sc_isoc_p_last[x] = 453 uhci_init_td(sc->sc_hw.isoc_start_pc + x); 454 } 455 456 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) { 457 sc->sc_intr_p_last[x] = 458 uhci_init_qh(sc->sc_hw.intr_start_pc + x); 459 } 460 461 /* 462 * the QHs are arranged to give poll intervals that are 463 * powers of 2 times 1ms 464 */ 465 bit = UHCI_IFRAMELIST_COUNT / 2; 466 while (bit) { 467 x = bit; 468 while (x & bit) { 469 uhci_qh_t *qh_x; 470 uhci_qh_t *qh_y; 471 472 y = (x ^ bit) | (bit / 2); 473 474 /* 475 * the next QH has half the poll interval 476 */ 477 qh_x = sc->sc_intr_p_last[x]; 478 qh_y = sc->sc_intr_p_last[y]; 479 480 qh_x->h_next = NULL; 481 qh_x->qh_h_next = qh_y->qh_self; 482 qh_x->e_next = NULL; 483 qh_x->qh_e_next = htole32(UHCI_PTR_T); 484 x++; 485 } 486 bit >>= 1; 487 } 488 489 if (1) { 490 uhci_qh_t *qh_ls; 491 uhci_qh_t *qh_intr; 492 493 qh_ls = sc->sc_ls_ctl_p_last; 494 qh_intr = sc->sc_intr_p_last[0]; 495 496 /* start QH for interrupt traffic */ 497 qh_intr->h_next = qh_ls; 498 qh_intr->qh_h_next = qh_ls->qh_self; 499 qh_intr->e_next = 0; 500 qh_intr->qh_e_next = htole32(UHCI_PTR_T); 501 } 502 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 503 504 uhci_td_t *td_x; 505 uhci_qh_t *qh_intr; 506 507 td_x = sc->sc_isoc_p_last[x]; 508 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)]; 509 510 /* start TD for isochronous traffic */ 511 td_x->next = NULL; 512 td_x->td_next = qh_intr->qh_self; 513 td_x->td_status = htole32(UHCI_TD_IOS); 514 td_x->td_token = htole32(0); 515 td_x->td_buffer = htole32(0); 516 } 517 518 if (1) { 519 uhci_qh_t *qh_ls; 520 uhci_qh_t *qh_fs; 521 522 qh_ls = sc->sc_ls_ctl_p_last; 523 qh_fs = sc->sc_fs_ctl_p_last; 524 525 /* start QH where low speed control traffic will be queued */ 526 qh_ls->h_next = qh_fs; 527 qh_ls->qh_h_next = qh_fs->qh_self; 528 qh_ls->e_next = 0; 529 qh_ls->qh_e_next = htole32(UHCI_PTR_T); 530 } 531 if (1) { 532 uhci_qh_t *qh_ctl; 533 uhci_qh_t *qh_blk; 534 uhci_qh_t *qh_lst; 535 uhci_td_t *td_lst; 536 537 qh_ctl = sc->sc_fs_ctl_p_last; 538 qh_blk = sc->sc_bulk_p_last; 539 540 /* start QH where full speed control traffic will be queued */ 541 qh_ctl->h_next = qh_blk; 542 qh_ctl->qh_h_next = qh_blk->qh_self; 543 qh_ctl->e_next = 0; 544 qh_ctl->qh_e_next = htole32(UHCI_PTR_T); 545 546 qh_lst = sc->sc_last_qh_p; 547 548 /* start QH where bulk traffic will be queued */ 549 qh_blk->h_next = qh_lst; 550 qh_blk->qh_h_next = qh_lst->qh_self; 551 qh_blk->e_next = 0; 552 qh_blk->qh_e_next = htole32(UHCI_PTR_T); 553 554 td_lst = sc->sc_last_td_p; 555 556 /* end QH which is used for looping the QHs */ 557 qh_lst->h_next = 0; 558 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */ 559 qh_lst->e_next = td_lst; 560 qh_lst->qh_e_next = td_lst->td_self; 561 562 /* 563 * end TD which hangs from the last QH, to avoid a bug in the PIIX 564 * that makes it run berserk otherwise 565 */ 566 td_lst->next = 0; 567 td_lst->td_next = htole32(UHCI_PTR_T); 568 td_lst->td_status = htole32(0); /* inactive */ 569 td_lst->td_token = htole32(0); 570 td_lst->td_buffer = htole32(0); 571 } 572 if (1) { 573 struct usb2_page_search buf_res; 574 uint32_t *pframes; 575 576 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 577 578 pframes = buf_res.buffer; 579 580 581 /* 582 * Setup UHCI framelist 583 * 584 * Execution order: 585 * 586 * pframes -> full speed isochronous -> interrupt QH's -> low 587 * speed control -> full speed control -> bulk transfers 588 * 589 */ 590 591 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) { 592 pframes[x] = 593 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self; 594 } 595 } 596 /* flush all cache into memory */ 597 598 usb2_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc); 599 600 /* set up the bus struct */ 601 sc->sc_bus.methods = &uhci_bus_methods; 602 603 USB_BUS_LOCK(&sc->sc_bus); 604 /* reset the controller */ 605 uhci_reset(sc); 606 607 /* start the controller */ 608 uhci_start(sc); 609 USB_BUS_UNLOCK(&sc->sc_bus); 610 611 /* catch lost interrupts */ 612 uhci_do_poll(&sc->sc_bus); 613 614 return (0); 615 } 616 617 /* NOTE: suspend/resume is called from 618 * interrupt context and cannot sleep! 619 */ 620 621 void 622 uhci_suspend(uhci_softc_t *sc) 623 { 624 USB_BUS_LOCK(&sc->sc_bus); 625 626 #if USB_DEBUG 627 if (uhcidebug > 2) { 628 uhci_dumpregs(sc); 629 } 630 #endif 631 /* save some state if BIOS doesn't */ 632 633 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 634 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 635 636 /* stop the controller */ 637 638 uhci_reset(sc); 639 640 /* enter global suspend */ 641 642 UHCICMD(sc, UHCI_CMD_EGSM); 643 644 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 645 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 646 647 USB_BUS_UNLOCK(&sc->sc_bus); 648 } 649 650 void 651 uhci_resume(uhci_softc_t *sc) 652 { 653 USB_BUS_LOCK(&sc->sc_bus); 654 655 /* reset the controller */ 656 657 uhci_reset(sc); 658 659 /* force global resume */ 660 661 UHCICMD(sc, UHCI_CMD_FGR); 662 663 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 664 USB_MS_TO_TICKS(USB_RESUME_DELAY)); 665 666 /* and start traffic again */ 667 668 uhci_start(sc); 669 670 #if USB_DEBUG 671 if (uhcidebug > 2) { 672 uhci_dumpregs(sc); 673 } 674 #endif 675 676 USB_BUS_UNLOCK(&sc->sc_bus); 677 678 /* catch lost interrupts */ 679 uhci_do_poll(&sc->sc_bus); 680 } 681 682 #if USB_DEBUG 683 static void 684 uhci_dumpregs(uhci_softc_t *sc) 685 { 686 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 687 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 688 device_get_nameunit(sc->sc_bus.bdev), 689 UREAD2(sc, UHCI_CMD), 690 UREAD2(sc, UHCI_STS), 691 UREAD2(sc, UHCI_INTR), 692 UREAD2(sc, UHCI_FRNUM), 693 UREAD4(sc, UHCI_FLBASEADDR), 694 UREAD1(sc, UHCI_SOF), 695 UREAD2(sc, UHCI_PORTSC1), 696 UREAD2(sc, UHCI_PORTSC2)); 697 } 698 699 static uint8_t 700 uhci_dump_td(uhci_td_t *p) 701 { 702 uint32_t td_next; 703 uint32_t td_status; 704 uint32_t td_token; 705 uint8_t temp; 706 707 usb2_pc_cpu_invalidate(p->page_cache); 708 709 td_next = le32toh(p->td_next); 710 td_status = le32toh(p->td_status); 711 td_token = le32toh(p->td_token); 712 713 /* 714 * Check whether the link pointer in this TD marks the link pointer 715 * as end of queue: 716 */ 717 temp = ((td_next & UHCI_PTR_T) || (td_next == 0)); 718 719 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x " 720 "token=0x%08x buffer=0x%08x\n", 721 p, 722 le32toh(p->td_self), 723 td_next, 724 td_status, 725 td_token, 726 le32toh(p->td_buffer)); 727 728 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x," 729 "addr=%d,endpt=%d,D=%d,maxlen=%d\n", 730 p, 731 (td_next & 1) ? "-T" : "", 732 (td_next & 2) ? "-Q" : "", 733 (td_next & 4) ? "-VF" : "", 734 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "", 735 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "", 736 (td_status & UHCI_TD_NAK) ? "-NAK" : "", 737 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "", 738 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "", 739 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "", 740 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "", 741 (td_status & UHCI_TD_IOC) ? "-IOC" : "", 742 (td_status & UHCI_TD_IOS) ? "-IOS" : "", 743 (td_status & UHCI_TD_LS) ? "-LS" : "", 744 (td_status & UHCI_TD_SPD) ? "-SPD" : "", 745 UHCI_TD_GET_ERRCNT(td_status), 746 UHCI_TD_GET_ACTLEN(td_status), 747 UHCI_TD_GET_PID(td_token), 748 UHCI_TD_GET_DEVADDR(td_token), 749 UHCI_TD_GET_ENDPT(td_token), 750 UHCI_TD_GET_DT(td_token), 751 UHCI_TD_GET_MAXLEN(td_token)); 752 753 return (temp); 754 } 755 756 static uint8_t 757 uhci_dump_qh(uhci_qh_t *sqh) 758 { 759 uint8_t temp; 760 uint32_t qh_h_next; 761 uint32_t qh_e_next; 762 763 usb2_pc_cpu_invalidate(sqh->page_cache); 764 765 qh_h_next = le32toh(sqh->qh_h_next); 766 qh_e_next = le32toh(sqh->qh_e_next); 767 768 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh, 769 le32toh(sqh->qh_self), qh_h_next, qh_e_next); 770 771 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) | 772 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0)); 773 774 return (temp); 775 } 776 777 static void 778 uhci_dump_all(uhci_softc_t *sc) 779 { 780 uhci_dumpregs(sc); 781 uhci_dump_qh(sc->sc_ls_ctl_p_last); 782 uhci_dump_qh(sc->sc_fs_ctl_p_last); 783 uhci_dump_qh(sc->sc_bulk_p_last); 784 uhci_dump_qh(sc->sc_last_qh_p); 785 } 786 787 static void 788 uhci_dump_qhs(uhci_qh_t *sqh) 789 { 790 uint8_t temp; 791 792 temp = uhci_dump_qh(sqh); 793 794 /* 795 * uhci_dump_qhs displays all the QHs and TDs from the given QH 796 * onwards Traverses sideways first, then down. 797 * 798 * QH1 QH2 No QH TD2.1 TD2.2 TD1.1 etc. 799 * 800 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 801 */ 802 803 if (temp & 1) 804 uhci_dump_qhs(sqh->h_next); 805 else 806 DPRINTF("No QH\n"); 807 808 if (temp & 2) 809 uhci_dump_tds(sqh->e_next); 810 else 811 DPRINTF("No TD\n"); 812 } 813 814 static void 815 uhci_dump_tds(uhci_td_t *td) 816 { 817 for (; 818 td != NULL; 819 td = td->obj_next) { 820 if (uhci_dump_td(td)) { 821 break; 822 } 823 } 824 } 825 826 #endif 827 828 /* 829 * Let the last QH loop back to the full speed control transfer QH. 830 * This is what intel calls "bandwidth reclamation" and improves 831 * USB performance a lot for some devices. 832 * If we are already looping, just count it. 833 */ 834 static void 835 uhci_add_loop(uhci_softc_t *sc) 836 { 837 struct uhci_qh *qh_lst; 838 struct uhci_qh *qh_rec; 839 840 #if USB_DEBUG 841 if (uhcinoloop) { 842 return; 843 } 844 #endif 845 if (++(sc->sc_loops) == 1) { 846 DPRINTFN(6, "add\n"); 847 848 qh_lst = sc->sc_last_qh_p; 849 qh_rec = sc->sc_reclaim_qh_p; 850 851 /* NOTE: we don't loop back the soft pointer */ 852 853 qh_lst->qh_h_next = qh_rec->qh_self; 854 usb2_pc_cpu_flush(qh_lst->page_cache); 855 } 856 } 857 858 static void 859 uhci_rem_loop(uhci_softc_t *sc) 860 { 861 struct uhci_qh *qh_lst; 862 863 #if USB_DEBUG 864 if (uhcinoloop) { 865 return; 866 } 867 #endif 868 if (--(sc->sc_loops) == 0) { 869 DPRINTFN(6, "remove\n"); 870 871 qh_lst = sc->sc_last_qh_p; 872 qh_lst->qh_h_next = htole32(UHCI_PTR_T); 873 usb2_pc_cpu_flush(qh_lst->page_cache); 874 } 875 } 876 877 static void 878 uhci_transfer_intr_enqueue(struct usb2_xfer *xfer) 879 { 880 /* check for early completion */ 881 if (uhci_check_transfer(xfer)) { 882 return; 883 } 884 /* put transfer on interrupt queue */ 885 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 886 887 /* start timeout, if any */ 888 if (xfer->timeout != 0) { 889 usb2_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout); 890 } 891 } 892 893 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last) 894 static uhci_td_t * 895 _uhci_append_td(uhci_td_t *std, uhci_td_t *last) 896 { 897 DPRINTFN(11, "%p to %p\n", std, last); 898 899 /* (sc->sc_bus.mtx) must be locked */ 900 901 std->next = last->next; 902 std->td_next = last->td_next; 903 904 std->prev = last; 905 906 usb2_pc_cpu_flush(std->page_cache); 907 908 /* 909 * the last->next->prev is never followed: std->next->prev = std; 910 */ 911 last->next = std; 912 last->td_next = std->td_self; 913 914 usb2_pc_cpu_flush(last->page_cache); 915 916 return (std); 917 } 918 919 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last) 920 static uhci_qh_t * 921 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last) 922 { 923 DPRINTFN(11, "%p to %p\n", sqh, last); 924 925 if (sqh->h_prev != NULL) { 926 /* should not happen */ 927 DPRINTFN(0, "QH already linked!\n"); 928 return (last); 929 } 930 /* (sc->sc_bus.mtx) must be locked */ 931 932 sqh->h_next = last->h_next; 933 sqh->qh_h_next = last->qh_h_next; 934 935 sqh->h_prev = last; 936 937 usb2_pc_cpu_flush(sqh->page_cache); 938 939 /* 940 * The "last->h_next->h_prev" is never followed: 941 * 942 * "sqh->h_next->h_prev" = sqh; 943 */ 944 945 last->h_next = sqh; 946 last->qh_h_next = sqh->qh_self; 947 948 usb2_pc_cpu_flush(last->page_cache); 949 950 return (sqh); 951 } 952 953 /**/ 954 955 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last) 956 static uhci_td_t * 957 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last) 958 { 959 DPRINTFN(11, "%p from %p\n", std, last); 960 961 /* (sc->sc_bus.mtx) must be locked */ 962 963 std->prev->next = std->next; 964 std->prev->td_next = std->td_next; 965 966 usb2_pc_cpu_flush(std->prev->page_cache); 967 968 if (std->next) { 969 std->next->prev = std->prev; 970 usb2_pc_cpu_flush(std->next->page_cache); 971 } 972 return ((last == std) ? std->prev : last); 973 } 974 975 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last) 976 static uhci_qh_t * 977 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last) 978 { 979 DPRINTFN(11, "%p from %p\n", sqh, last); 980 981 /* (sc->sc_bus.mtx) must be locked */ 982 983 /* only remove if not removed from a queue */ 984 if (sqh->h_prev) { 985 986 sqh->h_prev->h_next = sqh->h_next; 987 sqh->h_prev->qh_h_next = sqh->qh_h_next; 988 989 usb2_pc_cpu_flush(sqh->h_prev->page_cache); 990 991 if (sqh->h_next) { 992 sqh->h_next->h_prev = sqh->h_prev; 993 usb2_pc_cpu_flush(sqh->h_next->page_cache); 994 } 995 last = ((last == sqh) ? sqh->h_prev : last); 996 997 sqh->h_prev = 0; 998 999 usb2_pc_cpu_flush(sqh->page_cache); 1000 } 1001 return (last); 1002 } 1003 1004 static void 1005 uhci_isoc_done(uhci_softc_t *sc, struct usb2_xfer *xfer) 1006 { 1007 struct usb2_page_search res; 1008 uint32_t nframes = xfer->nframes; 1009 uint32_t status; 1010 uint32_t offset = 0; 1011 uint32_t *plen = xfer->frlengths; 1012 uint16_t len = 0; 1013 uhci_td_t *td = xfer->td_transfer_first; 1014 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos]; 1015 1016 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1017 xfer, xfer->pipe); 1018 1019 /* sync any DMA memory before doing fixups */ 1020 1021 usb2_bdma_post_sync(xfer); 1022 1023 while (nframes--) { 1024 if (td == NULL) { 1025 panic("%s:%d: out of TD's\n", 1026 __FUNCTION__, __LINE__); 1027 } 1028 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 1029 pp_last = &sc->sc_isoc_p_last[0]; 1030 } 1031 #if USB_DEBUG 1032 if (uhcidebug > 5) { 1033 DPRINTF("isoc TD\n"); 1034 uhci_dump_td(td); 1035 } 1036 #endif 1037 usb2_pc_cpu_invalidate(td->page_cache); 1038 status = le32toh(td->td_status); 1039 1040 len = UHCI_TD_GET_ACTLEN(status); 1041 1042 if (len > *plen) { 1043 len = *plen; 1044 } 1045 if (td->fix_pc) { 1046 1047 usb2_get_page(td->fix_pc, 0, &res); 1048 1049 /* copy data from fixup location to real location */ 1050 1051 usb2_pc_cpu_invalidate(td->fix_pc); 1052 1053 usb2_copy_in(xfer->frbuffers, offset, 1054 res.buffer, len); 1055 } 1056 offset += *plen; 1057 1058 *plen = len; 1059 1060 /* remove TD from schedule */ 1061 UHCI_REMOVE_TD(td, *pp_last); 1062 1063 pp_last++; 1064 plen++; 1065 td = td->obj_next; 1066 } 1067 1068 xfer->aframes = xfer->nframes; 1069 } 1070 1071 static usb2_error_t 1072 uhci_non_isoc_done_sub(struct usb2_xfer *xfer) 1073 { 1074 struct usb2_page_search res; 1075 uhci_td_t *td; 1076 uhci_td_t *td_alt_next; 1077 uint32_t status; 1078 uint32_t token; 1079 uint16_t len; 1080 1081 td = xfer->td_transfer_cache; 1082 td_alt_next = td->alt_next; 1083 1084 if (xfer->aframes != xfer->nframes) { 1085 xfer->frlengths[xfer->aframes] = 0; 1086 } 1087 while (1) { 1088 1089 usb2_pc_cpu_invalidate(td->page_cache); 1090 status = le32toh(td->td_status); 1091 token = le32toh(td->td_token); 1092 1093 /* 1094 * Verify the status and add 1095 * up the actual length: 1096 */ 1097 1098 len = UHCI_TD_GET_ACTLEN(status); 1099 if (len > td->len) { 1100 /* should not happen */ 1101 DPRINTF("Invalid status length, " 1102 "0x%04x/0x%04x bytes\n", len, td->len); 1103 status |= UHCI_TD_STALLED; 1104 1105 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) { 1106 1107 if (td->fix_pc) { 1108 1109 usb2_get_page(td->fix_pc, 0, &res); 1110 1111 /* 1112 * copy data from fixup location to real 1113 * location 1114 */ 1115 1116 usb2_pc_cpu_invalidate(td->fix_pc); 1117 1118 usb2_copy_in(xfer->frbuffers + xfer->aframes, 1119 xfer->frlengths[xfer->aframes], res.buffer, len); 1120 } 1121 /* update actual length */ 1122 1123 xfer->frlengths[xfer->aframes] += len; 1124 } 1125 /* Check for last transfer */ 1126 if (((void *)td) == xfer->td_transfer_last) { 1127 td = NULL; 1128 break; 1129 } 1130 if (status & UHCI_TD_STALLED) { 1131 /* the transfer is finished */ 1132 td = NULL; 1133 break; 1134 } 1135 /* Check for short transfer */ 1136 if (len != td->len) { 1137 if (xfer->flags_int.short_frames_ok) { 1138 /* follow alt next */ 1139 td = td->alt_next; 1140 } else { 1141 /* the transfer is finished */ 1142 td = NULL; 1143 } 1144 break; 1145 } 1146 td = td->obj_next; 1147 1148 if (td->alt_next != td_alt_next) { 1149 /* this USB frame is complete */ 1150 break; 1151 } 1152 } 1153 1154 /* update transfer cache */ 1155 1156 xfer->td_transfer_cache = td; 1157 1158 /* update data toggle */ 1159 1160 xfer->pipe->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1; 1161 1162 #if USB_DEBUG 1163 if (status & UHCI_TD_ERROR) { 1164 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x " 1165 "status=%s%s%s%s%s%s%s%s%s%s%s\n", 1166 xfer->address, xfer->endpoint, xfer->aframes, 1167 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "", 1168 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "", 1169 (status & UHCI_TD_NAK) ? "[NAK]" : "", 1170 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "", 1171 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "", 1172 (status & UHCI_TD_STALLED) ? "[STALLED]" : "", 1173 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1174 (status & UHCI_TD_IOC) ? "[IOC]" : "", 1175 (status & UHCI_TD_IOS) ? "[IOS]" : "", 1176 (status & UHCI_TD_LS) ? "[LS]" : "", 1177 (status & UHCI_TD_SPD) ? "[SPD]" : ""); 1178 } 1179 #endif 1180 return (status & UHCI_TD_STALLED) ? 1181 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION; 1182 } 1183 1184 static void 1185 uhci_non_isoc_done(struct usb2_xfer *xfer) 1186 { 1187 usb2_error_t err = 0; 1188 1189 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1190 xfer, xfer->pipe); 1191 1192 #if USB_DEBUG 1193 if (uhcidebug > 10) { 1194 uhci_dump_tds(xfer->td_transfer_first); 1195 } 1196 #endif 1197 1198 /* sync any DMA memory before doing fixups */ 1199 1200 usb2_bdma_post_sync(xfer); 1201 1202 /* reset scanner */ 1203 1204 xfer->td_transfer_cache = xfer->td_transfer_first; 1205 1206 if (xfer->flags_int.control_xfr) { 1207 if (xfer->flags_int.control_hdr) { 1208 1209 err = uhci_non_isoc_done_sub(xfer); 1210 } 1211 xfer->aframes = 1; 1212 1213 if (xfer->td_transfer_cache == NULL) { 1214 goto done; 1215 } 1216 } 1217 while (xfer->aframes != xfer->nframes) { 1218 1219 err = uhci_non_isoc_done_sub(xfer); 1220 xfer->aframes++; 1221 1222 if (xfer->td_transfer_cache == NULL) { 1223 goto done; 1224 } 1225 } 1226 1227 if (xfer->flags_int.control_xfr && 1228 !xfer->flags_int.control_act) { 1229 1230 err = uhci_non_isoc_done_sub(xfer); 1231 } 1232 done: 1233 uhci_device_done(xfer, err); 1234 } 1235 1236 /*------------------------------------------------------------------------* 1237 * uhci_check_transfer_sub 1238 * 1239 * The main purpose of this function is to update the data-toggle 1240 * in case it is wrong. 1241 *------------------------------------------------------------------------*/ 1242 static void 1243 uhci_check_transfer_sub(struct usb2_xfer *xfer) 1244 { 1245 uhci_qh_t *qh; 1246 uhci_td_t *td; 1247 uhci_td_t *td_alt_next; 1248 1249 uint32_t td_token; 1250 uint32_t td_self; 1251 1252 td = xfer->td_transfer_cache; 1253 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1254 1255 td_token = td->obj_next->td_token; 1256 td = td->alt_next; 1257 xfer->td_transfer_cache = td; 1258 td_self = td->td_self; 1259 td_alt_next = td->alt_next; 1260 1261 if (xfer->flags_int.control_xfr) 1262 goto skip; /* don't touch the DT value! */ 1263 1264 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1)))) 1265 goto skip; /* data toggle has correct value */ 1266 1267 /* 1268 * The data toggle is wrong and we need to toggle it ! 1269 */ 1270 while (1) { 1271 1272 td->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1273 usb2_pc_cpu_flush(td->page_cache); 1274 1275 if (td == xfer->td_transfer_last) { 1276 /* last transfer */ 1277 break; 1278 } 1279 td = td->obj_next; 1280 1281 if (td->alt_next != td_alt_next) { 1282 /* next frame */ 1283 break; 1284 } 1285 } 1286 skip: 1287 1288 /* update the QH */ 1289 qh->qh_e_next = td_self; 1290 usb2_pc_cpu_flush(qh->page_cache); 1291 1292 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1293 } 1294 1295 /*------------------------------------------------------------------------* 1296 * uhci_check_transfer 1297 * 1298 * Return values: 1299 * 0: USB transfer is not finished 1300 * Else: USB transfer is finished 1301 *------------------------------------------------------------------------*/ 1302 static uint8_t 1303 uhci_check_transfer(struct usb2_xfer *xfer) 1304 { 1305 uint32_t status; 1306 uint32_t token; 1307 uhci_td_t *td; 1308 1309 DPRINTFN(16, "xfer=%p checking transfer\n", xfer); 1310 1311 if (xfer->pipe->methods == &uhci_device_isoc_methods) { 1312 /* isochronous transfer */ 1313 1314 td = xfer->td_transfer_last; 1315 1316 usb2_pc_cpu_invalidate(td->page_cache); 1317 status = le32toh(td->td_status); 1318 1319 /* check also if the first is complete */ 1320 1321 td = xfer->td_transfer_first; 1322 1323 usb2_pc_cpu_invalidate(td->page_cache); 1324 status |= le32toh(td->td_status); 1325 1326 if (!(status & UHCI_TD_ACTIVE)) { 1327 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1328 goto transferred; 1329 } 1330 } else { 1331 /* non-isochronous transfer */ 1332 1333 /* 1334 * check whether there is an error somewhere 1335 * in the middle, or whether there was a short 1336 * packet (SPD and not ACTIVE) 1337 */ 1338 td = xfer->td_transfer_cache; 1339 1340 while (1) { 1341 usb2_pc_cpu_invalidate(td->page_cache); 1342 status = le32toh(td->td_status); 1343 token = le32toh(td->td_token); 1344 1345 /* 1346 * if there is an active TD the transfer isn't done 1347 */ 1348 if (status & UHCI_TD_ACTIVE) { 1349 /* update cache */ 1350 xfer->td_transfer_cache = td; 1351 goto done; 1352 } 1353 /* 1354 * last transfer descriptor makes the transfer done 1355 */ 1356 if (((void *)td) == xfer->td_transfer_last) { 1357 break; 1358 } 1359 /* 1360 * any kind of error makes the transfer done 1361 */ 1362 if (status & UHCI_TD_STALLED) { 1363 break; 1364 } 1365 /* 1366 * check if we reached the last packet 1367 * or if there is a short packet: 1368 */ 1369 if ((td->td_next == htole32(UHCI_PTR_T)) || 1370 (UHCI_TD_GET_ACTLEN(status) < td->len)) { 1371 1372 if (xfer->flags_int.short_frames_ok) { 1373 /* follow alt next */ 1374 if (td->alt_next) { 1375 /* update cache */ 1376 xfer->td_transfer_cache = td; 1377 uhci_check_transfer_sub(xfer); 1378 goto done; 1379 } 1380 } 1381 /* transfer is done */ 1382 break; 1383 } 1384 td = td->obj_next; 1385 } 1386 uhci_non_isoc_done(xfer); 1387 goto transferred; 1388 } 1389 1390 done: 1391 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1392 return (0); 1393 1394 transferred: 1395 return (1); 1396 } 1397 1398 static void 1399 uhci_interrupt_poll(uhci_softc_t *sc) 1400 { 1401 struct usb2_xfer *xfer; 1402 1403 repeat: 1404 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1405 /* 1406 * check if transfer is transferred 1407 */ 1408 if (uhci_check_transfer(xfer)) { 1409 /* queue has been modified */ 1410 goto repeat; 1411 } 1412 } 1413 } 1414 1415 /*------------------------------------------------------------------------* 1416 * uhci_interrupt - UHCI interrupt handler 1417 * 1418 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1419 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1420 * is present ! 1421 *------------------------------------------------------------------------*/ 1422 void 1423 uhci_interrupt(uhci_softc_t *sc) 1424 { 1425 uint32_t status; 1426 1427 USB_BUS_LOCK(&sc->sc_bus); 1428 1429 DPRINTFN(16, "real interrupt\n"); 1430 1431 #if USB_DEBUG 1432 if (uhcidebug > 15) { 1433 uhci_dumpregs(sc); 1434 } 1435 #endif 1436 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1437 if (status == 0) { 1438 /* the interrupt was not for us */ 1439 goto done; 1440 } 1441 if (status & (UHCI_STS_RD | UHCI_STS_HSE | 1442 UHCI_STS_HCPE | UHCI_STS_HCH)) { 1443 1444 if (status & UHCI_STS_RD) { 1445 #if USB_DEBUG 1446 printf("%s: resume detect\n", 1447 __FUNCTION__); 1448 #endif 1449 } 1450 if (status & UHCI_STS_HSE) { 1451 printf("%s: host system error\n", 1452 __FUNCTION__); 1453 } 1454 if (status & UHCI_STS_HCPE) { 1455 printf("%s: host controller process error\n", 1456 __FUNCTION__); 1457 } 1458 if (status & UHCI_STS_HCH) { 1459 /* no acknowledge needed */ 1460 DPRINTF("%s: host controller halted\n", 1461 __FUNCTION__); 1462 #if USB_DEBUG 1463 if (uhcidebug > 0) { 1464 uhci_dump_all(sc); 1465 } 1466 #endif 1467 } 1468 } 1469 /* get acknowledge bits */ 1470 status &= (UHCI_STS_USBINT | 1471 UHCI_STS_USBEI | 1472 UHCI_STS_RD | 1473 UHCI_STS_HSE | 1474 UHCI_STS_HCPE); 1475 1476 if (status == 0) { 1477 /* nothing to acknowledge */ 1478 goto done; 1479 } 1480 /* acknowledge interrupts */ 1481 UWRITE2(sc, UHCI_STS, status); 1482 1483 /* poll all the USB transfers */ 1484 uhci_interrupt_poll(sc); 1485 1486 done: 1487 USB_BUS_UNLOCK(&sc->sc_bus); 1488 } 1489 1490 /* 1491 * called when a request does not complete 1492 */ 1493 static void 1494 uhci_timeout(void *arg) 1495 { 1496 struct usb2_xfer *xfer = arg; 1497 1498 DPRINTF("xfer=%p\n", xfer); 1499 1500 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1501 1502 /* transfer is transferred */ 1503 uhci_device_done(xfer, USB_ERR_TIMEOUT); 1504 } 1505 1506 static void 1507 uhci_do_poll(struct usb2_bus *bus) 1508 { 1509 struct uhci_softc *sc = UHCI_BUS2SC(bus); 1510 1511 USB_BUS_LOCK(&sc->sc_bus); 1512 uhci_interrupt_poll(sc); 1513 USB_BUS_UNLOCK(&sc->sc_bus); 1514 } 1515 1516 static void 1517 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp) 1518 { 1519 uhci_td_t *td; 1520 uhci_td_t *td_next; 1521 uhci_td_t *td_alt_next; 1522 uint32_t average; 1523 uint32_t len_old; 1524 uint8_t shortpkt_old; 1525 uint8_t precompute; 1526 1527 td_alt_next = NULL; 1528 shortpkt_old = temp->shortpkt; 1529 len_old = temp->len; 1530 precompute = 1; 1531 1532 /* software is used to detect short incoming transfers */ 1533 1534 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) { 1535 temp->td_status |= htole32(UHCI_TD_SPD); 1536 } else { 1537 temp->td_status &= ~htole32(UHCI_TD_SPD); 1538 } 1539 1540 temp->ml.buf_offset = 0; 1541 1542 restart: 1543 1544 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1545 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average)); 1546 1547 td = temp->td; 1548 td_next = temp->td_next; 1549 1550 while (1) { 1551 1552 if (temp->len == 0) { 1553 1554 if (temp->shortpkt) { 1555 break; 1556 } 1557 /* send a Zero Length Packet, ZLP, last */ 1558 1559 temp->shortpkt = 1; 1560 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0)); 1561 average = 0; 1562 1563 } else { 1564 1565 average = temp->average; 1566 1567 if (temp->len < average) { 1568 temp->shortpkt = 1; 1569 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1570 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len)); 1571 average = temp->len; 1572 } 1573 } 1574 1575 if (td_next == NULL) { 1576 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__); 1577 } 1578 /* get next TD */ 1579 1580 td = td_next; 1581 td_next = td->obj_next; 1582 1583 /* check if we are pre-computing */ 1584 1585 if (precompute) { 1586 1587 /* update remaining length */ 1588 1589 temp->len -= average; 1590 1591 continue; 1592 } 1593 /* fill out current TD */ 1594 1595 td->td_status = temp->td_status; 1596 td->td_token = temp->td_token; 1597 1598 /* update data toggle */ 1599 1600 temp->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1601 1602 if (average == 0) { 1603 1604 td->len = 0; 1605 td->td_buffer = 0; 1606 td->fix_pc = NULL; 1607 1608 } else { 1609 1610 /* update remaining length */ 1611 1612 temp->len -= average; 1613 1614 td->len = average; 1615 1616 /* fill out buffer pointer and do fixup, if any */ 1617 1618 uhci_mem_layout_fixup(&temp->ml, td); 1619 } 1620 1621 td->alt_next = td_alt_next; 1622 1623 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1624 /* we need to receive these frames one by one ! */ 1625 td->td_status |= htole32(UHCI_TD_IOC); 1626 td->td_next = htole32(UHCI_PTR_T); 1627 } else { 1628 if (td_next) { 1629 /* link the current TD with the next one */ 1630 td->td_next = td_next->td_self; 1631 } 1632 } 1633 1634 usb2_pc_cpu_flush(td->page_cache); 1635 } 1636 1637 if (precompute) { 1638 precompute = 0; 1639 1640 /* setup alt next pointer, if any */ 1641 if (temp->last_frame) { 1642 td_alt_next = NULL; 1643 } else { 1644 /* we use this field internally */ 1645 td_alt_next = td_next; 1646 } 1647 1648 /* restore */ 1649 temp->shortpkt = shortpkt_old; 1650 temp->len = len_old; 1651 goto restart; 1652 } 1653 temp->td = td; 1654 temp->td_next = td_next; 1655 } 1656 1657 static uhci_td_t * 1658 uhci_setup_standard_chain(struct usb2_xfer *xfer) 1659 { 1660 struct uhci_std_temp temp; 1661 uhci_td_t *td; 1662 uint32_t x; 1663 1664 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1665 xfer->address, UE_GET_ADDR(xfer->endpoint), 1666 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1667 1668 temp.average = xfer->max_frame_size; 1669 temp.max_frame_size = xfer->max_frame_size; 1670 1671 /* toggle the DMA set we are using */ 1672 xfer->flags_int.curr_dma_set ^= 1; 1673 1674 /* get next DMA set */ 1675 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1676 xfer->td_transfer_first = td; 1677 xfer->td_transfer_cache = td; 1678 1679 temp.td = NULL; 1680 temp.td_next = td; 1681 temp.last_frame = 0; 1682 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1683 1684 uhci_mem_layout_init(&temp.ml, xfer); 1685 1686 temp.td_status = 1687 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | 1688 UHCI_TD_ACTIVE)); 1689 1690 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1691 temp.td_status |= htole32(UHCI_TD_LS); 1692 } 1693 temp.td_token = 1694 htole32(UHCI_TD_SET_ENDPT(xfer->endpoint) | 1695 UHCI_TD_SET_DEVADDR(xfer->address)); 1696 1697 if (xfer->pipe->toggle_next) { 1698 /* DATA1 is next */ 1699 temp.td_token |= htole32(UHCI_TD_SET_DT(1)); 1700 } 1701 /* check if we should prepend a setup message */ 1702 1703 if (xfer->flags_int.control_xfr) { 1704 1705 if (xfer->flags_int.control_hdr) { 1706 1707 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1708 UHCI_TD_SET_ENDPT(0xF)); 1709 temp.td_token |= htole32(UHCI_TD_PID_SETUP | 1710 UHCI_TD_SET_DT(0)); 1711 1712 temp.len = xfer->frlengths[0]; 1713 temp.ml.buf_pc = xfer->frbuffers + 0; 1714 temp.shortpkt = temp.len ? 1 : 0; 1715 /* check for last frame */ 1716 if (xfer->nframes == 1) { 1717 /* no STATUS stage yet, SETUP is last */ 1718 if (xfer->flags_int.control_act) { 1719 temp.last_frame = 1; 1720 temp.setup_alt_next = 0; 1721 } 1722 } 1723 uhci_setup_standard_chain_sub(&temp); 1724 } 1725 x = 1; 1726 } else { 1727 x = 0; 1728 } 1729 1730 while (x != xfer->nframes) { 1731 1732 /* DATA0 / DATA1 message */ 1733 1734 temp.len = xfer->frlengths[x]; 1735 temp.ml.buf_pc = xfer->frbuffers + x; 1736 1737 x++; 1738 1739 if (x == xfer->nframes) { 1740 if (xfer->flags_int.control_xfr) { 1741 /* no STATUS stage yet, DATA is last */ 1742 if (xfer->flags_int.control_act) { 1743 temp.last_frame = 1; 1744 temp.setup_alt_next = 0; 1745 } 1746 } else { 1747 temp.last_frame = 1; 1748 temp.setup_alt_next = 0; 1749 } 1750 } 1751 /* 1752 * Keep previous data toggle, 1753 * device address and endpoint number: 1754 */ 1755 1756 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1757 UHCI_TD_SET_ENDPT(0xF) | 1758 UHCI_TD_SET_DT(1)); 1759 1760 if (temp.len == 0) { 1761 1762 /* make sure that we send an USB packet */ 1763 1764 temp.shortpkt = 0; 1765 1766 } else { 1767 1768 /* regular data transfer */ 1769 1770 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1771 } 1772 1773 /* set endpoint direction */ 1774 1775 temp.td_token |= 1776 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 1777 htole32(UHCI_TD_PID_IN) : 1778 htole32(UHCI_TD_PID_OUT); 1779 1780 uhci_setup_standard_chain_sub(&temp); 1781 } 1782 1783 /* check if we should append a status stage */ 1784 1785 if (xfer->flags_int.control_xfr && 1786 !xfer->flags_int.control_act) { 1787 1788 /* 1789 * send a DATA1 message and reverse the current endpoint 1790 * direction 1791 */ 1792 1793 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1794 UHCI_TD_SET_ENDPT(0xF) | 1795 UHCI_TD_SET_DT(1)); 1796 temp.td_token |= 1797 (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) ? 1798 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) : 1799 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1)); 1800 1801 temp.len = 0; 1802 temp.ml.buf_pc = NULL; 1803 temp.shortpkt = 0; 1804 temp.last_frame = 1; 1805 temp.setup_alt_next = 0; 1806 1807 uhci_setup_standard_chain_sub(&temp); 1808 } 1809 td = temp.td; 1810 1811 /* Ensure that last TD is terminating: */ 1812 td->td_next = htole32(UHCI_PTR_T); 1813 1814 /* set interrupt bit */ 1815 1816 td->td_status |= htole32(UHCI_TD_IOC); 1817 1818 usb2_pc_cpu_flush(td->page_cache); 1819 1820 /* must have at least one frame! */ 1821 1822 xfer->td_transfer_last = td; 1823 1824 #if USB_DEBUG 1825 if (uhcidebug > 8) { 1826 DPRINTF("nexttog=%d; data before transfer:\n", 1827 xfer->pipe->toggle_next); 1828 uhci_dump_tds(xfer->td_transfer_first); 1829 } 1830 #endif 1831 return (xfer->td_transfer_first); 1832 } 1833 1834 /* NOTE: "done" can be run two times in a row, 1835 * from close and from interrupt 1836 */ 1837 1838 static void 1839 uhci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1840 { 1841 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1842 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1843 uhci_qh_t *qh; 1844 1845 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1846 1847 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1848 xfer, xfer->pipe, error); 1849 1850 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1851 if (qh) { 1852 usb2_pc_cpu_invalidate(qh->page_cache); 1853 } 1854 if (xfer->flags_int.bandwidth_reclaimed) { 1855 xfer->flags_int.bandwidth_reclaimed = 0; 1856 uhci_rem_loop(sc); 1857 } 1858 if (methods == &uhci_device_bulk_methods) { 1859 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 1860 } 1861 if (methods == &uhci_device_ctrl_methods) { 1862 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1863 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 1864 } else { 1865 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 1866 } 1867 } 1868 if (methods == &uhci_device_intr_methods) { 1869 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 1870 } 1871 /* 1872 * Only finish isochronous transfers once 1873 * which will update "xfer->frlengths". 1874 */ 1875 if (xfer->td_transfer_first && 1876 xfer->td_transfer_last) { 1877 if (methods == &uhci_device_isoc_methods) { 1878 uhci_isoc_done(sc, xfer); 1879 } 1880 xfer->td_transfer_first = NULL; 1881 xfer->td_transfer_last = NULL; 1882 } 1883 /* dequeue transfer and start next transfer */ 1884 usb2_transfer_done(xfer, error); 1885 } 1886 1887 /*------------------------------------------------------------------------* 1888 * uhci bulk support 1889 *------------------------------------------------------------------------*/ 1890 static void 1891 uhci_device_bulk_open(struct usb2_xfer *xfer) 1892 { 1893 return; 1894 } 1895 1896 static void 1897 uhci_device_bulk_close(struct usb2_xfer *xfer) 1898 { 1899 uhci_device_done(xfer, USB_ERR_CANCELLED); 1900 } 1901 1902 static void 1903 uhci_device_bulk_enter(struct usb2_xfer *xfer) 1904 { 1905 return; 1906 } 1907 1908 static void 1909 uhci_device_bulk_start(struct usb2_xfer *xfer) 1910 { 1911 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1912 uhci_td_t *td; 1913 uhci_qh_t *qh; 1914 1915 /* setup TD's */ 1916 td = uhci_setup_standard_chain(xfer); 1917 1918 /* setup QH */ 1919 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1920 1921 qh->e_next = td; 1922 qh->qh_e_next = td->td_self; 1923 1924 if (xfer->xroot->udev->state != USB_STATE_SUSPENDED) { 1925 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 1926 uhci_add_loop(sc); 1927 xfer->flags_int.bandwidth_reclaimed = 1; 1928 } else { 1929 usb2_pc_cpu_flush(qh->page_cache); 1930 } 1931 1932 /* put transfer on interrupt queue */ 1933 uhci_transfer_intr_enqueue(xfer); 1934 } 1935 1936 struct usb2_pipe_methods uhci_device_bulk_methods = 1937 { 1938 .open = uhci_device_bulk_open, 1939 .close = uhci_device_bulk_close, 1940 .enter = uhci_device_bulk_enter, 1941 .start = uhci_device_bulk_start, 1942 }; 1943 1944 /*------------------------------------------------------------------------* 1945 * uhci control support 1946 *------------------------------------------------------------------------*/ 1947 static void 1948 uhci_device_ctrl_open(struct usb2_xfer *xfer) 1949 { 1950 return; 1951 } 1952 1953 static void 1954 uhci_device_ctrl_close(struct usb2_xfer *xfer) 1955 { 1956 uhci_device_done(xfer, USB_ERR_CANCELLED); 1957 } 1958 1959 static void 1960 uhci_device_ctrl_enter(struct usb2_xfer *xfer) 1961 { 1962 return; 1963 } 1964 1965 static void 1966 uhci_device_ctrl_start(struct usb2_xfer *xfer) 1967 { 1968 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1969 uhci_qh_t *qh; 1970 uhci_td_t *td; 1971 1972 /* setup TD's */ 1973 td = uhci_setup_standard_chain(xfer); 1974 1975 /* setup QH */ 1976 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1977 1978 qh->e_next = td; 1979 qh->qh_e_next = td->td_self; 1980 1981 /* 1982 * NOTE: some devices choke on bandwidth- reclamation for control 1983 * transfers 1984 */ 1985 if (xfer->xroot->udev->state != USB_STATE_SUSPENDED) { 1986 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1987 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 1988 } else { 1989 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 1990 } 1991 } else { 1992 usb2_pc_cpu_flush(qh->page_cache); 1993 } 1994 /* put transfer on interrupt queue */ 1995 uhci_transfer_intr_enqueue(xfer); 1996 } 1997 1998 struct usb2_pipe_methods uhci_device_ctrl_methods = 1999 { 2000 .open = uhci_device_ctrl_open, 2001 .close = uhci_device_ctrl_close, 2002 .enter = uhci_device_ctrl_enter, 2003 .start = uhci_device_ctrl_start, 2004 }; 2005 2006 /*------------------------------------------------------------------------* 2007 * uhci interrupt support 2008 *------------------------------------------------------------------------*/ 2009 static void 2010 uhci_device_intr_open(struct usb2_xfer *xfer) 2011 { 2012 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2013 uint16_t best; 2014 uint16_t bit; 2015 uint16_t x; 2016 2017 best = 0; 2018 bit = UHCI_IFRAMELIST_COUNT / 2; 2019 while (bit) { 2020 if (xfer->interval >= bit) { 2021 x = bit; 2022 best = bit; 2023 while (x & bit) { 2024 if (sc->sc_intr_stat[x] < 2025 sc->sc_intr_stat[best]) { 2026 best = x; 2027 } 2028 x++; 2029 } 2030 break; 2031 } 2032 bit >>= 1; 2033 } 2034 2035 sc->sc_intr_stat[best]++; 2036 xfer->qh_pos = best; 2037 2038 DPRINTFN(3, "best=%d interval=%d\n", 2039 best, xfer->interval); 2040 } 2041 2042 static void 2043 uhci_device_intr_close(struct usb2_xfer *xfer) 2044 { 2045 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2046 2047 sc->sc_intr_stat[xfer->qh_pos]--; 2048 2049 uhci_device_done(xfer, USB_ERR_CANCELLED); 2050 } 2051 2052 static void 2053 uhci_device_intr_enter(struct usb2_xfer *xfer) 2054 { 2055 return; 2056 } 2057 2058 static void 2059 uhci_device_intr_start(struct usb2_xfer *xfer) 2060 { 2061 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2062 uhci_qh_t *qh; 2063 uhci_td_t *td; 2064 2065 /* setup TD's */ 2066 td = uhci_setup_standard_chain(xfer); 2067 2068 /* setup QH */ 2069 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2070 2071 qh->e_next = td; 2072 qh->qh_e_next = td->td_self; 2073 2074 if (xfer->xroot->udev->state != USB_STATE_SUSPENDED) { 2075 2076 /* enter QHs into the controller data structures */ 2077 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 2078 2079 } else { 2080 usb2_pc_cpu_flush(qh->page_cache); 2081 } 2082 2083 /* put transfer on interrupt queue */ 2084 uhci_transfer_intr_enqueue(xfer); 2085 } 2086 2087 struct usb2_pipe_methods uhci_device_intr_methods = 2088 { 2089 .open = uhci_device_intr_open, 2090 .close = uhci_device_intr_close, 2091 .enter = uhci_device_intr_enter, 2092 .start = uhci_device_intr_start, 2093 }; 2094 2095 /*------------------------------------------------------------------------* 2096 * uhci isochronous support 2097 *------------------------------------------------------------------------*/ 2098 static void 2099 uhci_device_isoc_open(struct usb2_xfer *xfer) 2100 { 2101 uhci_td_t *td; 2102 uint32_t td_token; 2103 uint8_t ds; 2104 2105 td_token = 2106 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 2107 UHCI_TD_IN(0, xfer->endpoint, xfer->address, 0) : 2108 UHCI_TD_OUT(0, xfer->endpoint, xfer->address, 0); 2109 2110 td_token = htole32(td_token); 2111 2112 /* initialize all TD's */ 2113 2114 for (ds = 0; ds != 2; ds++) { 2115 2116 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2117 2118 /* mark TD as inactive */ 2119 td->td_status = htole32(UHCI_TD_IOS); 2120 td->td_token = td_token; 2121 2122 usb2_pc_cpu_flush(td->page_cache); 2123 } 2124 } 2125 } 2126 2127 static void 2128 uhci_device_isoc_close(struct usb2_xfer *xfer) 2129 { 2130 uhci_device_done(xfer, USB_ERR_CANCELLED); 2131 } 2132 2133 static void 2134 uhci_device_isoc_enter(struct usb2_xfer *xfer) 2135 { 2136 struct uhci_mem_layout ml; 2137 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2138 uint32_t nframes; 2139 uint32_t temp; 2140 uint32_t *plen; 2141 2142 #if USB_DEBUG 2143 uint8_t once = 1; 2144 2145 #endif 2146 uhci_td_t *td; 2147 uhci_td_t *td_last = NULL; 2148 uhci_td_t **pp_last; 2149 2150 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2151 xfer, xfer->pipe->isoc_next, xfer->nframes); 2152 2153 nframes = UREAD2(sc, UHCI_FRNUM); 2154 2155 temp = (nframes - xfer->pipe->isoc_next) & 2156 (UHCI_VFRAMELIST_COUNT - 1); 2157 2158 if ((xfer->pipe->is_synced == 0) || 2159 (temp < xfer->nframes)) { 2160 /* 2161 * If there is data underflow or the pipe queue is empty we 2162 * schedule the transfer a few frames ahead of the current 2163 * frame position. Else two isochronous transfers might 2164 * overlap. 2165 */ 2166 xfer->pipe->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1); 2167 xfer->pipe->is_synced = 1; 2168 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2169 } 2170 /* 2171 * compute how many milliseconds the insertion is ahead of the 2172 * current frame position: 2173 */ 2174 temp = (xfer->pipe->isoc_next - nframes) & 2175 (UHCI_VFRAMELIST_COUNT - 1); 2176 2177 /* 2178 * pre-compute when the isochronous transfer will be finished: 2179 */ 2180 xfer->isoc_time_complete = 2181 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2182 xfer->nframes; 2183 2184 /* get the real number of frames */ 2185 2186 nframes = xfer->nframes; 2187 2188 uhci_mem_layout_init(&ml, xfer); 2189 2190 plen = xfer->frlengths; 2191 2192 /* toggle the DMA set we are using */ 2193 xfer->flags_int.curr_dma_set ^= 1; 2194 2195 /* get next DMA set */ 2196 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2197 xfer->td_transfer_first = td; 2198 2199 pp_last = &sc->sc_isoc_p_last[xfer->pipe->isoc_next]; 2200 2201 /* store starting position */ 2202 2203 xfer->qh_pos = xfer->pipe->isoc_next; 2204 2205 while (nframes--) { 2206 if (td == NULL) { 2207 panic("%s:%d: out of TD's\n", 2208 __FUNCTION__, __LINE__); 2209 } 2210 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 2211 pp_last = &sc->sc_isoc_p_last[0]; 2212 } 2213 if (*plen > xfer->max_frame_size) { 2214 #if USB_DEBUG 2215 if (once) { 2216 once = 0; 2217 printf("%s: frame length(%d) exceeds %d " 2218 "bytes (frame truncated)\n", 2219 __FUNCTION__, *plen, 2220 xfer->max_frame_size); 2221 } 2222 #endif 2223 *plen = xfer->max_frame_size; 2224 } 2225 /* reuse td_token from last transfer */ 2226 2227 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2228 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen)); 2229 2230 td->len = *plen; 2231 2232 if (td->len == 0) { 2233 /* 2234 * Do not call "uhci_mem_layout_fixup()" when the 2235 * length is zero! 2236 */ 2237 td->td_buffer = 0; 2238 td->fix_pc = NULL; 2239 2240 } else { 2241 2242 /* fill out buffer pointer and do fixup, if any */ 2243 2244 uhci_mem_layout_fixup(&ml, td); 2245 2246 } 2247 2248 /* update status */ 2249 if (nframes == 0) { 2250 td->td_status = htole32 2251 (UHCI_TD_ZERO_ACTLEN 2252 (UHCI_TD_SET_ERRCNT(0) | 2253 UHCI_TD_ACTIVE | 2254 UHCI_TD_IOS | 2255 UHCI_TD_IOC)); 2256 } else { 2257 td->td_status = htole32 2258 (UHCI_TD_ZERO_ACTLEN 2259 (UHCI_TD_SET_ERRCNT(0) | 2260 UHCI_TD_ACTIVE | 2261 UHCI_TD_IOS)); 2262 } 2263 2264 usb2_pc_cpu_flush(td->page_cache); 2265 2266 #if USB_DEBUG 2267 if (uhcidebug > 5) { 2268 DPRINTF("TD %d\n", nframes); 2269 uhci_dump_td(td); 2270 } 2271 #endif 2272 /* insert TD into schedule */ 2273 UHCI_APPEND_TD(td, *pp_last); 2274 pp_last++; 2275 2276 plen++; 2277 td_last = td; 2278 td = td->obj_next; 2279 } 2280 2281 xfer->td_transfer_last = td_last; 2282 2283 /* update isoc_next */ 2284 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) & 2285 (UHCI_VFRAMELIST_COUNT - 1); 2286 } 2287 2288 static void 2289 uhci_device_isoc_start(struct usb2_xfer *xfer) 2290 { 2291 /* put transfer on interrupt queue */ 2292 uhci_transfer_intr_enqueue(xfer); 2293 } 2294 2295 struct usb2_pipe_methods uhci_device_isoc_methods = 2296 { 2297 .open = uhci_device_isoc_open, 2298 .close = uhci_device_isoc_close, 2299 .enter = uhci_device_isoc_enter, 2300 .start = uhci_device_isoc_start, 2301 }; 2302 2303 /*------------------------------------------------------------------------* 2304 * uhci root control support 2305 *------------------------------------------------------------------------* 2306 * Simulate a hardware hub by handling all the necessary requests. 2307 *------------------------------------------------------------------------*/ 2308 2309 static const 2310 struct usb2_device_descriptor uhci_devd = 2311 { 2312 sizeof(struct usb2_device_descriptor), 2313 UDESC_DEVICE, /* type */ 2314 {0x00, 0x01}, /* USB version */ 2315 UDCLASS_HUB, /* class */ 2316 UDSUBCLASS_HUB, /* subclass */ 2317 UDPROTO_FSHUB, /* protocol */ 2318 64, /* max packet */ 2319 {0}, {0}, {0x00, 0x01}, /* device id */ 2320 1, 2, 0, /* string indicies */ 2321 1 /* # of configurations */ 2322 }; 2323 2324 static const struct uhci_config_desc uhci_confd = { 2325 .confd = { 2326 .bLength = sizeof(struct usb2_config_descriptor), 2327 .bDescriptorType = UDESC_CONFIG, 2328 .wTotalLength[0] = sizeof(uhci_confd), 2329 .bNumInterface = 1, 2330 .bConfigurationValue = 1, 2331 .iConfiguration = 0, 2332 .bmAttributes = UC_SELF_POWERED, 2333 .bMaxPower = 0 /* max power */ 2334 }, 2335 .ifcd = { 2336 .bLength = sizeof(struct usb2_interface_descriptor), 2337 .bDescriptorType = UDESC_INTERFACE, 2338 .bNumEndpoints = 1, 2339 .bInterfaceClass = UICLASS_HUB, 2340 .bInterfaceSubClass = UISUBCLASS_HUB, 2341 .bInterfaceProtocol = UIPROTO_FSHUB, 2342 }, 2343 .endpd = { 2344 .bLength = sizeof(struct usb2_endpoint_descriptor), 2345 .bDescriptorType = UDESC_ENDPOINT, 2346 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 2347 .bmAttributes = UE_INTERRUPT, 2348 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2349 .bInterval = 255, 2350 }, 2351 }; 2352 2353 static const 2354 struct usb2_hub_descriptor_min uhci_hubd_piix = 2355 { 2356 sizeof(uhci_hubd_piix), 2357 UDESC_HUB, 2358 2, 2359 {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0}, 2360 50, /* power on to power good */ 2361 0, 2362 {0x00}, /* both ports are removable */ 2363 }; 2364 2365 /* 2366 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 2367 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 2368 * should not be used by the USB subsystem. As we cannot issue a 2369 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 2370 * will be enabled as part of the reset. 2371 * 2372 * On the VT83C572, the port cannot be successfully enabled until the 2373 * outstanding "port enable change" and "connection status change" 2374 * events have been reset. 2375 */ 2376 static usb2_error_t 2377 uhci_portreset(uhci_softc_t *sc, uint16_t index) 2378 { 2379 uint16_t port; 2380 uint16_t x; 2381 uint8_t lim; 2382 2383 if (index == 1) 2384 port = UHCI_PORTSC1; 2385 else if (index == 2) 2386 port = UHCI_PORTSC2; 2387 else 2388 return (USB_ERR_IOERROR); 2389 2390 /* 2391 * Before we do anything, turn on SOF messages on the USB 2392 * BUS. Some USB devices do not cope without them! 2393 */ 2394 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) { 2395 2396 DPRINTF("Activating SOFs!\n"); 2397 2398 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 2399 2400 /* wait a little bit */ 2401 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 2402 } 2403 2404 x = URWMASK(UREAD2(sc, port)); 2405 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2406 2407 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2408 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 2409 2410 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n", 2411 index, UREAD2(sc, port)); 2412 2413 x = URWMASK(UREAD2(sc, port)); 2414 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2415 2416 2417 mtx_unlock(&sc->sc_bus.bus_mtx); 2418 2419 /* 2420 * This delay needs to be exactly 100us, else some USB devices 2421 * fail to attach! 2422 */ 2423 DELAY(100); 2424 2425 mtx_lock(&sc->sc_bus.bus_mtx); 2426 2427 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n", 2428 index, UREAD2(sc, port)); 2429 2430 x = URWMASK(UREAD2(sc, port)); 2431 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2432 2433 for (lim = 0; lim < 12; lim++) { 2434 2435 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2436 USB_MS_TO_TICKS(USB_PORT_RESET_DELAY)); 2437 2438 x = UREAD2(sc, port); 2439 2440 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n", 2441 index, lim, x); 2442 2443 if (!(x & UHCI_PORTSC_CCS)) { 2444 /* 2445 * No device is connected (or was disconnected 2446 * during reset). Consider the port reset. 2447 * The delay must be long enough to ensure on 2448 * the initial iteration that the device 2449 * connection will have been registered. 50ms 2450 * appears to be sufficient, but 20ms is not. 2451 */ 2452 DPRINTFN(4, "uhci port %d loop %u, device detached\n", 2453 index, lim); 2454 goto done; 2455 } 2456 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 2457 /* 2458 * Port enabled changed and/or connection 2459 * status changed were set. Reset either or 2460 * both raised flags (by writing a 1 to that 2461 * bit), and wait again for state to settle. 2462 */ 2463 UWRITE2(sc, port, URWMASK(x) | 2464 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 2465 continue; 2466 } 2467 if (x & UHCI_PORTSC_PE) { 2468 /* port is enabled */ 2469 goto done; 2470 } 2471 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 2472 } 2473 2474 DPRINTFN(2, "uhci port %d reset timed out\n", index); 2475 return (USB_ERR_TIMEOUT); 2476 2477 done: 2478 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n", 2479 index, UREAD2(sc, port)); 2480 2481 sc->sc_isreset = 1; 2482 return (USB_ERR_NORMAL_COMPLETION); 2483 } 2484 2485 static usb2_error_t 2486 uhci_roothub_exec(struct usb2_device *udev, 2487 struct usb2_device_request *req, const void **pptr, uint16_t *plength) 2488 { 2489 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 2490 const void *ptr; 2491 const char *str_ptr; 2492 uint16_t x; 2493 uint16_t port; 2494 uint16_t value; 2495 uint16_t index; 2496 uint16_t status; 2497 uint16_t change; 2498 uint16_t len; 2499 usb2_error_t err; 2500 2501 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2502 2503 /* buffer reset */ 2504 ptr = (const void *)&sc->sc_hub_desc.temp; 2505 len = 0; 2506 err = 0; 2507 2508 value = UGETW(req->wValue); 2509 index = UGETW(req->wIndex); 2510 2511 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2512 "wValue=0x%04x wIndex=0x%04x\n", 2513 req->bmRequestType, req->bRequest, 2514 UGETW(req->wLength), value, index); 2515 2516 #define C(x,y) ((x) | ((y) << 8)) 2517 switch (C(req->bRequest, req->bmRequestType)) { 2518 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2519 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2520 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2521 /* 2522 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2523 * for the integrated root hub. 2524 */ 2525 break; 2526 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2527 len = 1; 2528 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2529 break; 2530 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2531 switch (value >> 8) { 2532 case UDESC_DEVICE: 2533 if ((value & 0xff) != 0) { 2534 err = USB_ERR_IOERROR; 2535 goto done; 2536 } 2537 len = sizeof(uhci_devd); 2538 ptr = (const void *)&uhci_devd; 2539 break; 2540 2541 case UDESC_CONFIG: 2542 if ((value & 0xff) != 0) { 2543 err = USB_ERR_IOERROR; 2544 goto done; 2545 } 2546 len = sizeof(uhci_confd); 2547 ptr = (const void *)&uhci_confd; 2548 break; 2549 2550 case UDESC_STRING: 2551 switch (value & 0xff) { 2552 case 0: /* Language table */ 2553 str_ptr = "\001"; 2554 break; 2555 2556 case 1: /* Vendor */ 2557 str_ptr = sc->sc_vendor; 2558 break; 2559 2560 case 2: /* Product */ 2561 str_ptr = "UHCI root HUB"; 2562 break; 2563 2564 default: 2565 str_ptr = ""; 2566 break; 2567 } 2568 2569 len = usb2_make_str_desc 2570 (sc->sc_hub_desc.temp, 2571 sizeof(sc->sc_hub_desc.temp), 2572 str_ptr); 2573 break; 2574 2575 default: 2576 err = USB_ERR_IOERROR; 2577 goto done; 2578 } 2579 break; 2580 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2581 len = 1; 2582 sc->sc_hub_desc.temp[0] = 0; 2583 break; 2584 case C(UR_GET_STATUS, UT_READ_DEVICE): 2585 len = 2; 2586 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2587 break; 2588 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2589 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2590 len = 2; 2591 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2592 break; 2593 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2594 if (value >= UHCI_MAX_DEVICES) { 2595 err = USB_ERR_IOERROR; 2596 goto done; 2597 } 2598 sc->sc_addr = value; 2599 break; 2600 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2601 if ((value != 0) && (value != 1)) { 2602 err = USB_ERR_IOERROR; 2603 goto done; 2604 } 2605 sc->sc_conf = value; 2606 break; 2607 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2608 break; 2609 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2610 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2611 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2612 err = USB_ERR_IOERROR; 2613 goto done; 2614 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2615 break; 2616 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2617 break; 2618 /* Hub requests */ 2619 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2620 break; 2621 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2622 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE " 2623 "port=%d feature=%d\n", 2624 index, value); 2625 if (index == 1) 2626 port = UHCI_PORTSC1; 2627 else if (index == 2) 2628 port = UHCI_PORTSC2; 2629 else { 2630 err = USB_ERR_IOERROR; 2631 goto done; 2632 } 2633 switch (value) { 2634 case UHF_PORT_ENABLE: 2635 x = URWMASK(UREAD2(sc, port)); 2636 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2637 break; 2638 case UHF_PORT_SUSPEND: 2639 x = URWMASK(UREAD2(sc, port)); 2640 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP)); 2641 break; 2642 case UHF_PORT_RESET: 2643 x = URWMASK(UREAD2(sc, port)); 2644 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2645 break; 2646 case UHF_C_PORT_CONNECTION: 2647 x = URWMASK(UREAD2(sc, port)); 2648 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2649 break; 2650 case UHF_C_PORT_ENABLE: 2651 x = URWMASK(UREAD2(sc, port)); 2652 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2653 break; 2654 case UHF_C_PORT_OVER_CURRENT: 2655 x = URWMASK(UREAD2(sc, port)); 2656 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2657 break; 2658 case UHF_C_PORT_RESET: 2659 sc->sc_isreset = 0; 2660 err = USB_ERR_NORMAL_COMPLETION; 2661 goto done; 2662 case UHF_C_PORT_SUSPEND: 2663 sc->sc_isresumed &= ~(1 << index); 2664 break; 2665 case UHF_PORT_CONNECTION: 2666 case UHF_PORT_OVER_CURRENT: 2667 case UHF_PORT_POWER: 2668 case UHF_PORT_LOW_SPEED: 2669 default: 2670 err = USB_ERR_IOERROR; 2671 goto done; 2672 } 2673 break; 2674 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2675 if (index == 1) 2676 port = UHCI_PORTSC1; 2677 else if (index == 2) 2678 port = UHCI_PORTSC2; 2679 else { 2680 err = USB_ERR_IOERROR; 2681 goto done; 2682 } 2683 len = 1; 2684 sc->sc_hub_desc.temp[0] = 2685 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2686 UHCI_PORTSC_LS_SHIFT); 2687 break; 2688 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2689 if ((value & 0xff) != 0) { 2690 err = USB_ERR_IOERROR; 2691 goto done; 2692 } 2693 len = sizeof(uhci_hubd_piix); 2694 ptr = (const void *)&uhci_hubd_piix; 2695 break; 2696 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2697 len = 16; 2698 bzero(sc->sc_hub_desc.temp, 16); 2699 break; 2700 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2701 if (index == 1) 2702 port = UHCI_PORTSC1; 2703 else if (index == 2) 2704 port = UHCI_PORTSC2; 2705 else { 2706 err = USB_ERR_IOERROR; 2707 goto done; 2708 } 2709 x = UREAD2(sc, port); 2710 status = change = 0; 2711 if (x & UHCI_PORTSC_CCS) 2712 status |= UPS_CURRENT_CONNECT_STATUS; 2713 if (x & UHCI_PORTSC_CSC) 2714 change |= UPS_C_CONNECT_STATUS; 2715 if (x & UHCI_PORTSC_PE) 2716 status |= UPS_PORT_ENABLED; 2717 if (x & UHCI_PORTSC_POEDC) 2718 change |= UPS_C_PORT_ENABLED; 2719 if (x & UHCI_PORTSC_OCI) 2720 status |= UPS_OVERCURRENT_INDICATOR; 2721 if (x & UHCI_PORTSC_OCIC) 2722 change |= UPS_C_OVERCURRENT_INDICATOR; 2723 if (x & UHCI_PORTSC_LSDA) 2724 status |= UPS_LOW_SPEED; 2725 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) { 2726 /* need to do a write back */ 2727 UWRITE2(sc, port, URWMASK(x)); 2728 2729 /* wait 20ms for resume sequence to complete */ 2730 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 2731 2732 /* clear suspend and resume detect */ 2733 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD | 2734 UHCI_PORTSC_SUSP)); 2735 2736 /* wait a little bit */ 2737 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500); 2738 2739 sc->sc_isresumed |= (1 << index); 2740 2741 } else if (x & UHCI_PORTSC_SUSP) { 2742 status |= UPS_SUSPEND; 2743 } 2744 status |= UPS_PORT_POWER; 2745 if (sc->sc_isresumed & (1 << index)) 2746 change |= UPS_C_SUSPEND; 2747 if (sc->sc_isreset) 2748 change |= UPS_C_PORT_RESET; 2749 USETW(sc->sc_hub_desc.ps.wPortStatus, status); 2750 USETW(sc->sc_hub_desc.ps.wPortChange, change); 2751 len = sizeof(sc->sc_hub_desc.ps); 2752 break; 2753 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2754 err = USB_ERR_IOERROR; 2755 goto done; 2756 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2757 break; 2758 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2759 if (index == 1) 2760 port = UHCI_PORTSC1; 2761 else if (index == 2) 2762 port = UHCI_PORTSC2; 2763 else { 2764 err = USB_ERR_IOERROR; 2765 goto done; 2766 } 2767 switch (value) { 2768 case UHF_PORT_ENABLE: 2769 x = URWMASK(UREAD2(sc, port)); 2770 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2771 break; 2772 case UHF_PORT_SUSPEND: 2773 x = URWMASK(UREAD2(sc, port)); 2774 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2775 break; 2776 case UHF_PORT_RESET: 2777 err = uhci_portreset(sc, index); 2778 goto done; 2779 case UHF_PORT_POWER: 2780 /* pretend we turned on power */ 2781 err = USB_ERR_NORMAL_COMPLETION; 2782 goto done; 2783 case UHF_C_PORT_CONNECTION: 2784 case UHF_C_PORT_ENABLE: 2785 case UHF_C_PORT_OVER_CURRENT: 2786 case UHF_PORT_CONNECTION: 2787 case UHF_PORT_OVER_CURRENT: 2788 case UHF_PORT_LOW_SPEED: 2789 case UHF_C_PORT_SUSPEND: 2790 case UHF_C_PORT_RESET: 2791 default: 2792 err = USB_ERR_IOERROR; 2793 goto done; 2794 } 2795 break; 2796 default: 2797 err = USB_ERR_IOERROR; 2798 goto done; 2799 } 2800 done: 2801 *plength = len; 2802 *pptr = ptr; 2803 return (err); 2804 } 2805 2806 /* 2807 * This routine is executed periodically and simulates interrupts from 2808 * the root controller interrupt pipe for port status change: 2809 */ 2810 static void 2811 uhci_root_intr(uhci_softc_t *sc) 2812 { 2813 DPRINTFN(21, "\n"); 2814 2815 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2816 2817 sc->sc_hub_idata[0] = 0; 2818 2819 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | 2820 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2821 sc->sc_hub_idata[0] |= 1 << 1; 2822 } 2823 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | 2824 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2825 sc->sc_hub_idata[0] |= 1 << 2; 2826 } 2827 2828 /* restart timer */ 2829 usb2_callout_reset(&sc->sc_root_intr, hz, 2830 (void *)&uhci_root_intr, sc); 2831 2832 if (sc->sc_hub_idata[0] != 0) { 2833 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2834 sizeof(sc->sc_hub_idata)); 2835 } 2836 } 2837 2838 static void 2839 uhci_xfer_setup(struct usb2_setup_params *parm) 2840 { 2841 struct usb2_page_search page_info; 2842 struct usb2_page_cache *pc; 2843 uhci_softc_t *sc; 2844 struct usb2_xfer *xfer; 2845 void *last_obj; 2846 uint32_t ntd; 2847 uint32_t nqh; 2848 uint32_t nfixup; 2849 uint32_t n; 2850 uint16_t align; 2851 2852 sc = UHCI_BUS2SC(parm->udev->bus); 2853 xfer = parm->curr_xfer; 2854 2855 parm->hc_max_packet_size = 0x500; 2856 parm->hc_max_packet_count = 1; 2857 parm->hc_max_frame_size = 0x500; 2858 2859 /* 2860 * compute ntd and nqh 2861 */ 2862 if (parm->methods == &uhci_device_ctrl_methods) { 2863 xfer->flags_int.bdma_enable = 1; 2864 xfer->flags_int.bdma_no_post_sync = 1; 2865 2866 usb2_transfer_setup_sub(parm); 2867 2868 /* see EHCI HC driver for proof of "ntd" formula */ 2869 2870 nqh = 1; 2871 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2872 + (xfer->max_data_length / xfer->max_frame_size)); 2873 2874 } else if (parm->methods == &uhci_device_bulk_methods) { 2875 xfer->flags_int.bdma_enable = 1; 2876 xfer->flags_int.bdma_no_post_sync = 1; 2877 2878 usb2_transfer_setup_sub(parm); 2879 2880 nqh = 1; 2881 ntd = ((2 * xfer->nframes) 2882 + (xfer->max_data_length / xfer->max_frame_size)); 2883 2884 } else if (parm->methods == &uhci_device_intr_methods) { 2885 xfer->flags_int.bdma_enable = 1; 2886 xfer->flags_int.bdma_no_post_sync = 1; 2887 2888 usb2_transfer_setup_sub(parm); 2889 2890 nqh = 1; 2891 ntd = ((2 * xfer->nframes) 2892 + (xfer->max_data_length / xfer->max_frame_size)); 2893 2894 } else if (parm->methods == &uhci_device_isoc_methods) { 2895 xfer->flags_int.bdma_enable = 1; 2896 xfer->flags_int.bdma_no_post_sync = 1; 2897 2898 usb2_transfer_setup_sub(parm); 2899 2900 nqh = 0; 2901 ntd = xfer->nframes; 2902 2903 } else { 2904 2905 usb2_transfer_setup_sub(parm); 2906 2907 nqh = 0; 2908 ntd = 0; 2909 } 2910 2911 if (parm->err) { 2912 return; 2913 } 2914 /* 2915 * NOTE: the UHCI controller requires that 2916 * every packet must be contiguous on 2917 * the same USB memory page ! 2918 */ 2919 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1; 2920 2921 /* 2922 * Compute a suitable power of two alignment 2923 * for our "max_frame_size" fixup buffer(s): 2924 */ 2925 align = xfer->max_frame_size; 2926 n = 0; 2927 while (align) { 2928 align >>= 1; 2929 n++; 2930 } 2931 2932 /* check for power of two */ 2933 if (!(xfer->max_frame_size & 2934 (xfer->max_frame_size - 1))) { 2935 n--; 2936 } 2937 /* 2938 * We don't allow alignments of 2939 * less than 8 bytes: 2940 * 2941 * NOTE: Allocating using an aligment 2942 * of 1 byte has special meaning! 2943 */ 2944 if (n < 3) { 2945 n = 3; 2946 } 2947 align = (1 << n); 2948 2949 if (usb2_transfer_setup_sub_malloc( 2950 parm, &pc, xfer->max_frame_size, 2951 align, nfixup)) { 2952 parm->err = USB_ERR_NOMEM; 2953 return; 2954 } 2955 xfer->buf_fixup = pc; 2956 2957 alloc_dma_set: 2958 2959 if (parm->err) { 2960 return; 2961 } 2962 last_obj = NULL; 2963 2964 if (usb2_transfer_setup_sub_malloc( 2965 parm, &pc, sizeof(uhci_td_t), 2966 UHCI_TD_ALIGN, ntd)) { 2967 parm->err = USB_ERR_NOMEM; 2968 return; 2969 } 2970 if (parm->buf) { 2971 for (n = 0; n != ntd; n++) { 2972 uhci_td_t *td; 2973 2974 usb2_get_page(pc + n, 0, &page_info); 2975 2976 td = page_info.buffer; 2977 2978 /* init TD */ 2979 if ((parm->methods == &uhci_device_bulk_methods) || 2980 (parm->methods == &uhci_device_ctrl_methods) || 2981 (parm->methods == &uhci_device_intr_methods)) { 2982 /* set depth first bit */ 2983 td->td_self = htole32(page_info.physaddr | 2984 UHCI_PTR_TD | UHCI_PTR_VF); 2985 } else { 2986 td->td_self = htole32(page_info.physaddr | 2987 UHCI_PTR_TD); 2988 } 2989 2990 td->obj_next = last_obj; 2991 td->page_cache = pc + n; 2992 2993 last_obj = td; 2994 2995 usb2_pc_cpu_flush(pc + n); 2996 } 2997 } 2998 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2999 3000 last_obj = NULL; 3001 3002 if (usb2_transfer_setup_sub_malloc( 3003 parm, &pc, sizeof(uhci_qh_t), 3004 UHCI_QH_ALIGN, nqh)) { 3005 parm->err = USB_ERR_NOMEM; 3006 return; 3007 } 3008 if (parm->buf) { 3009 for (n = 0; n != nqh; n++) { 3010 uhci_qh_t *qh; 3011 3012 usb2_get_page(pc + n, 0, &page_info); 3013 3014 qh = page_info.buffer; 3015 3016 /* init QH */ 3017 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH); 3018 qh->obj_next = last_obj; 3019 qh->page_cache = pc + n; 3020 3021 last_obj = qh; 3022 3023 usb2_pc_cpu_flush(pc + n); 3024 } 3025 } 3026 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3027 3028 if (!xfer->flags_int.curr_dma_set) { 3029 xfer->flags_int.curr_dma_set = 1; 3030 goto alloc_dma_set; 3031 } 3032 } 3033 3034 static void 3035 uhci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 3036 struct usb2_pipe *pipe) 3037 { 3038 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 3039 3040 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3041 pipe, udev->address, 3042 edesc->bEndpointAddress, udev->flags.usb2_mode, 3043 sc->sc_addr); 3044 3045 if (udev->flags.usb2_mode != USB_MODE_HOST) { 3046 /* not supported */ 3047 return; 3048 } 3049 if (udev->device_index != sc->sc_addr) { 3050 switch (edesc->bmAttributes & UE_XFERTYPE) { 3051 case UE_CONTROL: 3052 pipe->methods = &uhci_device_ctrl_methods; 3053 break; 3054 case UE_INTERRUPT: 3055 pipe->methods = &uhci_device_intr_methods; 3056 break; 3057 case UE_ISOCHRONOUS: 3058 if (udev->speed == USB_SPEED_FULL) { 3059 pipe->methods = &uhci_device_isoc_methods; 3060 } 3061 break; 3062 case UE_BULK: 3063 if (udev->speed != USB_SPEED_LOW) { 3064 pipe->methods = &uhci_device_bulk_methods; 3065 } 3066 break; 3067 default: 3068 /* do nothing */ 3069 break; 3070 } 3071 } 3072 } 3073 3074 static void 3075 uhci_xfer_unsetup(struct usb2_xfer *xfer) 3076 { 3077 return; 3078 } 3079 3080 static void 3081 uhci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 3082 { 3083 /* 3084 * Wait until hardware has finished any possible use of the 3085 * transfer descriptor(s) and QH 3086 */ 3087 *pus = (1125); /* microseconds */ 3088 } 3089 3090 static void 3091 uhci_device_resume(struct usb2_device *udev) 3092 { 3093 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3094 struct usb2_xfer *xfer; 3095 struct usb2_pipe_methods *methods; 3096 uhci_qh_t *qh; 3097 3098 DPRINTF("\n"); 3099 3100 USB_BUS_LOCK(udev->bus); 3101 3102 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3103 3104 if (xfer->xroot->udev == udev) { 3105 3106 methods = xfer->pipe->methods; 3107 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3108 3109 if (methods == &uhci_device_bulk_methods) { 3110 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 3111 uhci_add_loop(sc); 3112 xfer->flags_int.bandwidth_reclaimed = 1; 3113 } 3114 if (methods == &uhci_device_ctrl_methods) { 3115 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3116 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 3117 } else { 3118 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 3119 } 3120 } 3121 if (methods == &uhci_device_intr_methods) { 3122 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3123 } 3124 } 3125 } 3126 3127 USB_BUS_UNLOCK(udev->bus); 3128 3129 return; 3130 } 3131 3132 static void 3133 uhci_device_suspend(struct usb2_device *udev) 3134 { 3135 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3136 struct usb2_xfer *xfer; 3137 struct usb2_pipe_methods *methods; 3138 uhci_qh_t *qh; 3139 3140 DPRINTF("\n"); 3141 3142 USB_BUS_LOCK(udev->bus); 3143 3144 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3145 3146 if (xfer->xroot->udev == udev) { 3147 3148 methods = xfer->pipe->methods; 3149 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3150 3151 if (xfer->flags_int.bandwidth_reclaimed) { 3152 xfer->flags_int.bandwidth_reclaimed = 0; 3153 uhci_rem_loop(sc); 3154 } 3155 if (methods == &uhci_device_bulk_methods) { 3156 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 3157 } 3158 if (methods == &uhci_device_ctrl_methods) { 3159 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3160 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 3161 } else { 3162 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 3163 } 3164 } 3165 if (methods == &uhci_device_intr_methods) { 3166 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3167 } 3168 } 3169 } 3170 3171 USB_BUS_UNLOCK(udev->bus); 3172 3173 return; 3174 } 3175 3176 static void 3177 uhci_set_hw_power(struct usb2_bus *bus) 3178 { 3179 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3180 uint32_t flags; 3181 3182 DPRINTF("\n"); 3183 3184 USB_BUS_LOCK(bus); 3185 3186 flags = bus->hw_power_state; 3187 3188 /* 3189 * WARNING: Some FULL speed USB devices require periodic SOF 3190 * messages! If any USB devices are connected through the 3191 * UHCI, power save will be disabled! 3192 */ 3193 if (flags & (USB_HW_POWER_CONTROL | 3194 USB_HW_POWER_NON_ROOT_HUB | 3195 USB_HW_POWER_BULK | 3196 USB_HW_POWER_INTERRUPT | 3197 USB_HW_POWER_ISOC)) { 3198 DPRINTF("Some USB transfer is " 3199 "active on %u.\n", 3200 device_get_unit(sc->sc_bus.bdev)); 3201 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 3202 } else { 3203 DPRINTF("Power save on %u.\n", 3204 device_get_unit(sc->sc_bus.bdev)); 3205 UHCICMD(sc, UHCI_CMD_MAXP); 3206 } 3207 3208 USB_BUS_UNLOCK(bus); 3209 3210 return; 3211 } 3212 3213 3214 struct usb2_bus_methods uhci_bus_methods = 3215 { 3216 .pipe_init = uhci_pipe_init, 3217 .xfer_setup = uhci_xfer_setup, 3218 .xfer_unsetup = uhci_xfer_unsetup, 3219 .get_dma_delay = uhci_get_dma_delay, 3220 .device_resume = uhci_device_resume, 3221 .device_suspend = uhci_device_suspend, 3222 .set_hw_power = uhci_set_hw_power, 3223 .roothub_exec = uhci_roothub_exec, 3224 }; 3225