1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * USB Universal Host Controller driver. 33 * Handles e.g. PIIX3 and PIIX4. 34 * 35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 38 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 39 */ 40 41 #include <sys/stdint.h> 42 #include <sys/stddef.h> 43 #include <sys/param.h> 44 #include <sys/queue.h> 45 #include <sys/types.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/bus.h> 49 #include <sys/module.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/sysctl.h> 54 #include <sys/sx.h> 55 #include <sys/unistd.h> 56 #include <sys/callout.h> 57 #include <sys/malloc.h> 58 #include <sys/priv.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 63 #define USB_DEBUG_VAR uhcidebug 64 65 #include <dev/usb/usb_core.h> 66 #include <dev/usb/usb_debug.h> 67 #include <dev/usb/usb_busdma.h> 68 #include <dev/usb/usb_process.h> 69 #include <dev/usb/usb_transfer.h> 70 #include <dev/usb/usb_device.h> 71 #include <dev/usb/usb_hub.h> 72 #include <dev/usb/usb_util.h> 73 74 #include <dev/usb/usb_controller.h> 75 #include <dev/usb/usb_bus.h> 76 #include <dev/usb/controller/uhci.h> 77 #include <dev/usb/controller/uhcireg.h> 78 79 #define alt_next next 80 #define UHCI_BUS2SC(bus) \ 81 ((uhci_softc_t *)(((uint8_t *)(bus)) - \ 82 ((uint8_t *)&(((uhci_softc_t *)0)->sc_bus)))) 83 84 #ifdef USB_DEBUG 85 static int uhcidebug = 0; 86 static int uhcinoloop = 0; 87 88 static SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW, 0, "USB uhci"); 89 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RW, 90 &uhcidebug, 0, "uhci debug level"); 91 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RW, 92 &uhcinoloop, 0, "uhci noloop"); 93 94 TUNABLE_INT("hw.usb.uhci.debug", &uhcidebug); 95 TUNABLE_INT("hw.usb.uhci.loop", &uhcinoloop); 96 97 static void uhci_dumpregs(uhci_softc_t *sc); 98 static void uhci_dump_tds(uhci_td_t *td); 99 100 #endif 101 102 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 103 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 104 #define UWRITE1(sc, r, x) \ 105 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 106 } while (/*CONSTCOND*/0) 107 #define UWRITE2(sc, r, x) \ 108 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 109 } while (/*CONSTCOND*/0) 110 #define UWRITE4(sc, r, x) \ 111 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 112 } while (/*CONSTCOND*/0) 113 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 114 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 115 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 116 117 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 118 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 119 120 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 121 122 #define UHCI_INTR_ENDPT 1 123 124 struct uhci_mem_layout { 125 126 struct usb_page_search buf_res; 127 struct usb_page_search fix_res; 128 129 struct usb_page_cache *buf_pc; 130 struct usb_page_cache *fix_pc; 131 132 uint32_t buf_offset; 133 134 uint16_t max_frame_size; 135 }; 136 137 struct uhci_std_temp { 138 139 struct uhci_mem_layout ml; 140 uhci_td_t *td; 141 uhci_td_t *td_next; 142 uint32_t average; 143 uint32_t td_status; 144 uint32_t td_token; 145 uint32_t len; 146 uint16_t max_frame_size; 147 uint8_t shortpkt; 148 uint8_t setup_alt_next; 149 uint8_t last_frame; 150 }; 151 152 extern struct usb_bus_methods uhci_bus_methods; 153 extern struct usb_pipe_methods uhci_device_bulk_methods; 154 extern struct usb_pipe_methods uhci_device_ctrl_methods; 155 extern struct usb_pipe_methods uhci_device_intr_methods; 156 extern struct usb_pipe_methods uhci_device_isoc_methods; 157 158 static uint8_t uhci_restart(uhci_softc_t *sc); 159 static void uhci_do_poll(struct usb_bus *); 160 static void uhci_device_done(struct usb_xfer *, usb_error_t); 161 static void uhci_transfer_intr_enqueue(struct usb_xfer *); 162 static void uhci_timeout(void *); 163 static uint8_t uhci_check_transfer(struct usb_xfer *); 164 static void uhci_root_intr(uhci_softc_t *sc); 165 166 void 167 uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 168 { 169 struct uhci_softc *sc = UHCI_BUS2SC(bus); 170 uint32_t i; 171 172 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 173 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN); 174 175 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg, 176 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 177 178 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg, 179 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 180 181 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 182 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 183 184 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg, 185 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 186 187 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg, 188 sizeof(uhci_td_t), UHCI_TD_ALIGN); 189 190 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) { 191 cb(bus, sc->sc_hw.isoc_start_pc + i, 192 sc->sc_hw.isoc_start_pg + i, 193 sizeof(uhci_td_t), UHCI_TD_ALIGN); 194 } 195 196 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) { 197 cb(bus, sc->sc_hw.intr_start_pc + i, 198 sc->sc_hw.intr_start_pg + i, 199 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 200 } 201 } 202 203 static void 204 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer) 205 { 206 ml->buf_pc = xfer->frbuffers + 0; 207 ml->fix_pc = xfer->buf_fixup; 208 209 ml->buf_offset = 0; 210 211 ml->max_frame_size = xfer->max_frame_size; 212 } 213 214 static void 215 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td) 216 { 217 usbd_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res); 218 219 if (ml->buf_res.length < td->len) { 220 221 /* need to do a fixup */ 222 223 usbd_get_page(ml->fix_pc, 0, &ml->fix_res); 224 225 td->td_buffer = htole32(ml->fix_res.physaddr); 226 227 /* 228 * The UHCI driver cannot handle 229 * page crossings, so a fixup is 230 * needed: 231 * 232 * +----+----+ - - - 233 * | YYY|Y | 234 * +----+----+ - - - 235 * \ \ 236 * \ \ 237 * +----+ 238 * |YYYY| (fixup) 239 * +----+ 240 */ 241 242 if ((td->td_token & htole32(UHCI_TD_PID)) == 243 htole32(UHCI_TD_PID_IN)) { 244 td->fix_pc = ml->fix_pc; 245 usb_pc_cpu_invalidate(ml->fix_pc); 246 247 } else { 248 td->fix_pc = NULL; 249 250 /* copy data to fixup location */ 251 252 usbd_copy_out(ml->buf_pc, ml->buf_offset, 253 ml->fix_res.buffer, td->len); 254 255 usb_pc_cpu_flush(ml->fix_pc); 256 } 257 258 /* prepare next fixup */ 259 260 ml->fix_pc++; 261 262 } else { 263 264 td->td_buffer = htole32(ml->buf_res.physaddr); 265 td->fix_pc = NULL; 266 } 267 268 /* prepare next data location */ 269 270 ml->buf_offset += td->len; 271 } 272 273 /* 274 * Return values: 275 * 0: Success 276 * Else: Failure 277 */ 278 static uint8_t 279 uhci_restart(uhci_softc_t *sc) 280 { 281 struct usb_page_search buf_res; 282 283 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 284 285 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) { 286 DPRINTFN(2, "Already started\n"); 287 return (0); 288 } 289 290 DPRINTFN(2, "Restarting\n"); 291 292 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 293 294 /* Reload fresh base address */ 295 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr); 296 297 /* 298 * Assume 64 byte packets at frame end and start HC controller: 299 */ 300 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 301 302 /* wait 10 milliseconds */ 303 304 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 305 306 /* check that controller has started */ 307 308 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 309 DPRINTFN(2, "Failed\n"); 310 return (1); 311 } 312 return (0); 313 } 314 315 void 316 uhci_reset(uhci_softc_t *sc) 317 { 318 uint16_t n; 319 320 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 321 322 DPRINTF("resetting the HC\n"); 323 324 /* disable interrupts */ 325 326 UWRITE2(sc, UHCI_INTR, 0); 327 328 /* global reset */ 329 330 UHCICMD(sc, UHCI_CMD_GRESET); 331 332 /* wait */ 333 334 usb_pause_mtx(&sc->sc_bus.bus_mtx, 335 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 336 337 /* terminate all transfers */ 338 339 UHCICMD(sc, UHCI_CMD_HCRESET); 340 341 /* the reset bit goes low when the controller is done */ 342 343 n = UHCI_RESET_TIMEOUT; 344 while (n--) { 345 /* wait one millisecond */ 346 347 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 348 349 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) { 350 goto done_1; 351 } 352 } 353 354 device_printf(sc->sc_bus.bdev, 355 "controller did not reset\n"); 356 357 done_1: 358 359 n = 10; 360 while (n--) { 361 /* wait one millisecond */ 362 363 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 364 365 /* check if HC is stopped */ 366 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 367 goto done_2; 368 } 369 } 370 371 device_printf(sc->sc_bus.bdev, 372 "controller did not stop\n"); 373 374 done_2: 375 376 /* reset frame number */ 377 UWRITE2(sc, UHCI_FRNUM, 0); 378 /* set default SOF value */ 379 UWRITE1(sc, UHCI_SOF, 0x40); 380 381 USB_BUS_UNLOCK(&sc->sc_bus); 382 383 /* stop root interrupt */ 384 usb_callout_drain(&sc->sc_root_intr); 385 386 USB_BUS_LOCK(&sc->sc_bus); 387 } 388 389 static void 390 uhci_start(uhci_softc_t *sc) 391 { 392 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 393 394 DPRINTFN(2, "enabling\n"); 395 396 /* enable interrupts */ 397 398 UWRITE2(sc, UHCI_INTR, 399 (UHCI_INTR_TOCRCIE | 400 UHCI_INTR_RIE | 401 UHCI_INTR_IOCE | 402 UHCI_INTR_SPIE)); 403 404 if (uhci_restart(sc)) { 405 device_printf(sc->sc_bus.bdev, 406 "cannot start HC controller\n"); 407 } 408 409 /* start root interrupt */ 410 uhci_root_intr(sc); 411 } 412 413 static struct uhci_qh * 414 uhci_init_qh(struct usb_page_cache *pc) 415 { 416 struct usb_page_search buf_res; 417 struct uhci_qh *qh; 418 419 usbd_get_page(pc, 0, &buf_res); 420 421 qh = buf_res.buffer; 422 423 qh->qh_self = 424 htole32(buf_res.physaddr) | 425 htole32(UHCI_PTR_QH); 426 427 qh->page_cache = pc; 428 429 return (qh); 430 } 431 432 static struct uhci_td * 433 uhci_init_td(struct usb_page_cache *pc) 434 { 435 struct usb_page_search buf_res; 436 struct uhci_td *td; 437 438 usbd_get_page(pc, 0, &buf_res); 439 440 td = buf_res.buffer; 441 442 td->td_self = 443 htole32(buf_res.physaddr) | 444 htole32(UHCI_PTR_TD); 445 446 td->page_cache = pc; 447 448 return (td); 449 } 450 451 usb_error_t 452 uhci_init(uhci_softc_t *sc) 453 { 454 uint16_t bit; 455 uint16_t x; 456 uint16_t y; 457 458 DPRINTF("start\n"); 459 460 usb_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_mtx, 0); 461 462 #ifdef USB_DEBUG 463 if (uhcidebug > 2) { 464 uhci_dumpregs(sc); 465 } 466 #endif 467 /* 468 * Setup QH's 469 */ 470 sc->sc_ls_ctl_p_last = 471 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc); 472 473 sc->sc_fs_ctl_p_last = 474 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc); 475 476 sc->sc_bulk_p_last = 477 uhci_init_qh(&sc->sc_hw.bulk_start_pc); 478 #if 0 479 sc->sc_reclaim_qh_p = 480 sc->sc_fs_ctl_p_last; 481 #else 482 /* setup reclaim looping point */ 483 sc->sc_reclaim_qh_p = 484 sc->sc_bulk_p_last; 485 #endif 486 487 sc->sc_last_qh_p = 488 uhci_init_qh(&sc->sc_hw.last_qh_pc); 489 490 sc->sc_last_td_p = 491 uhci_init_td(&sc->sc_hw.last_td_pc); 492 493 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 494 sc->sc_isoc_p_last[x] = 495 uhci_init_td(sc->sc_hw.isoc_start_pc + x); 496 } 497 498 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) { 499 sc->sc_intr_p_last[x] = 500 uhci_init_qh(sc->sc_hw.intr_start_pc + x); 501 } 502 503 /* 504 * the QHs are arranged to give poll intervals that are 505 * powers of 2 times 1ms 506 */ 507 bit = UHCI_IFRAMELIST_COUNT / 2; 508 while (bit) { 509 x = bit; 510 while (x & bit) { 511 uhci_qh_t *qh_x; 512 uhci_qh_t *qh_y; 513 514 y = (x ^ bit) | (bit / 2); 515 516 /* 517 * the next QH has half the poll interval 518 */ 519 qh_x = sc->sc_intr_p_last[x]; 520 qh_y = sc->sc_intr_p_last[y]; 521 522 qh_x->h_next = NULL; 523 qh_x->qh_h_next = qh_y->qh_self; 524 qh_x->e_next = NULL; 525 qh_x->qh_e_next = htole32(UHCI_PTR_T); 526 x++; 527 } 528 bit >>= 1; 529 } 530 531 if (1) { 532 uhci_qh_t *qh_ls; 533 uhci_qh_t *qh_intr; 534 535 qh_ls = sc->sc_ls_ctl_p_last; 536 qh_intr = sc->sc_intr_p_last[0]; 537 538 /* start QH for interrupt traffic */ 539 qh_intr->h_next = qh_ls; 540 qh_intr->qh_h_next = qh_ls->qh_self; 541 qh_intr->e_next = 0; 542 qh_intr->qh_e_next = htole32(UHCI_PTR_T); 543 } 544 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 545 546 uhci_td_t *td_x; 547 uhci_qh_t *qh_intr; 548 549 td_x = sc->sc_isoc_p_last[x]; 550 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)]; 551 552 /* start TD for isochronous traffic */ 553 td_x->next = NULL; 554 td_x->td_next = qh_intr->qh_self; 555 td_x->td_status = htole32(UHCI_TD_IOS); 556 td_x->td_token = htole32(0); 557 td_x->td_buffer = htole32(0); 558 } 559 560 if (1) { 561 uhci_qh_t *qh_ls; 562 uhci_qh_t *qh_fs; 563 564 qh_ls = sc->sc_ls_ctl_p_last; 565 qh_fs = sc->sc_fs_ctl_p_last; 566 567 /* start QH where low speed control traffic will be queued */ 568 qh_ls->h_next = qh_fs; 569 qh_ls->qh_h_next = qh_fs->qh_self; 570 qh_ls->e_next = 0; 571 qh_ls->qh_e_next = htole32(UHCI_PTR_T); 572 } 573 if (1) { 574 uhci_qh_t *qh_ctl; 575 uhci_qh_t *qh_blk; 576 uhci_qh_t *qh_lst; 577 uhci_td_t *td_lst; 578 579 qh_ctl = sc->sc_fs_ctl_p_last; 580 qh_blk = sc->sc_bulk_p_last; 581 582 /* start QH where full speed control traffic will be queued */ 583 qh_ctl->h_next = qh_blk; 584 qh_ctl->qh_h_next = qh_blk->qh_self; 585 qh_ctl->e_next = 0; 586 qh_ctl->qh_e_next = htole32(UHCI_PTR_T); 587 588 qh_lst = sc->sc_last_qh_p; 589 590 /* start QH where bulk traffic will be queued */ 591 qh_blk->h_next = qh_lst; 592 qh_blk->qh_h_next = qh_lst->qh_self; 593 qh_blk->e_next = 0; 594 qh_blk->qh_e_next = htole32(UHCI_PTR_T); 595 596 td_lst = sc->sc_last_td_p; 597 598 /* end QH which is used for looping the QHs */ 599 qh_lst->h_next = 0; 600 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */ 601 qh_lst->e_next = td_lst; 602 qh_lst->qh_e_next = td_lst->td_self; 603 604 /* 605 * end TD which hangs from the last QH, to avoid a bug in the PIIX 606 * that makes it run berserk otherwise 607 */ 608 td_lst->next = 0; 609 td_lst->td_next = htole32(UHCI_PTR_T); 610 td_lst->td_status = htole32(0); /* inactive */ 611 td_lst->td_token = htole32(0); 612 td_lst->td_buffer = htole32(0); 613 } 614 if (1) { 615 struct usb_page_search buf_res; 616 uint32_t *pframes; 617 618 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 619 620 pframes = buf_res.buffer; 621 622 623 /* 624 * Setup UHCI framelist 625 * 626 * Execution order: 627 * 628 * pframes -> full speed isochronous -> interrupt QH's -> low 629 * speed control -> full speed control -> bulk transfers 630 * 631 */ 632 633 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) { 634 pframes[x] = 635 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self; 636 } 637 } 638 /* flush all cache into memory */ 639 640 usb_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc); 641 642 /* set up the bus struct */ 643 sc->sc_bus.methods = &uhci_bus_methods; 644 645 USB_BUS_LOCK(&sc->sc_bus); 646 /* reset the controller */ 647 uhci_reset(sc); 648 649 /* start the controller */ 650 uhci_start(sc); 651 USB_BUS_UNLOCK(&sc->sc_bus); 652 653 /* catch lost interrupts */ 654 uhci_do_poll(&sc->sc_bus); 655 656 return (0); 657 } 658 659 static void 660 uhci_suspend(uhci_softc_t *sc) 661 { 662 #ifdef USB_DEBUG 663 if (uhcidebug > 2) { 664 uhci_dumpregs(sc); 665 } 666 #endif 667 668 USB_BUS_LOCK(&sc->sc_bus); 669 670 /* stop the controller */ 671 672 uhci_reset(sc); 673 674 /* enter global suspend */ 675 676 UHCICMD(sc, UHCI_CMD_EGSM); 677 678 USB_BUS_UNLOCK(&sc->sc_bus); 679 } 680 681 static void 682 uhci_resume(uhci_softc_t *sc) 683 { 684 USB_BUS_LOCK(&sc->sc_bus); 685 686 /* reset the controller */ 687 688 uhci_reset(sc); 689 690 /* force global resume */ 691 692 UHCICMD(sc, UHCI_CMD_FGR); 693 694 /* and start traffic again */ 695 696 uhci_start(sc); 697 698 USB_BUS_UNLOCK(&sc->sc_bus); 699 700 #ifdef USB_DEBUG 701 if (uhcidebug > 2) 702 uhci_dumpregs(sc); 703 #endif 704 705 /* catch lost interrupts */ 706 uhci_do_poll(&sc->sc_bus); 707 } 708 709 #ifdef USB_DEBUG 710 static void 711 uhci_dumpregs(uhci_softc_t *sc) 712 { 713 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 714 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 715 device_get_nameunit(sc->sc_bus.bdev), 716 UREAD2(sc, UHCI_CMD), 717 UREAD2(sc, UHCI_STS), 718 UREAD2(sc, UHCI_INTR), 719 UREAD2(sc, UHCI_FRNUM), 720 UREAD4(sc, UHCI_FLBASEADDR), 721 UREAD1(sc, UHCI_SOF), 722 UREAD2(sc, UHCI_PORTSC1), 723 UREAD2(sc, UHCI_PORTSC2)); 724 } 725 726 static uint8_t 727 uhci_dump_td(uhci_td_t *p) 728 { 729 uint32_t td_next; 730 uint32_t td_status; 731 uint32_t td_token; 732 uint8_t temp; 733 734 usb_pc_cpu_invalidate(p->page_cache); 735 736 td_next = le32toh(p->td_next); 737 td_status = le32toh(p->td_status); 738 td_token = le32toh(p->td_token); 739 740 /* 741 * Check whether the link pointer in this TD marks the link pointer 742 * as end of queue: 743 */ 744 temp = ((td_next & UHCI_PTR_T) || (td_next == 0)); 745 746 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x " 747 "token=0x%08x buffer=0x%08x\n", 748 p, 749 le32toh(p->td_self), 750 td_next, 751 td_status, 752 td_token, 753 le32toh(p->td_buffer)); 754 755 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x," 756 "addr=%d,endpt=%d,D=%d,maxlen=%d\n", 757 p, 758 (td_next & 1) ? "-T" : "", 759 (td_next & 2) ? "-Q" : "", 760 (td_next & 4) ? "-VF" : "", 761 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "", 762 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "", 763 (td_status & UHCI_TD_NAK) ? "-NAK" : "", 764 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "", 765 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "", 766 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "", 767 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "", 768 (td_status & UHCI_TD_IOC) ? "-IOC" : "", 769 (td_status & UHCI_TD_IOS) ? "-IOS" : "", 770 (td_status & UHCI_TD_LS) ? "-LS" : "", 771 (td_status & UHCI_TD_SPD) ? "-SPD" : "", 772 UHCI_TD_GET_ERRCNT(td_status), 773 UHCI_TD_GET_ACTLEN(td_status), 774 UHCI_TD_GET_PID(td_token), 775 UHCI_TD_GET_DEVADDR(td_token), 776 UHCI_TD_GET_ENDPT(td_token), 777 UHCI_TD_GET_DT(td_token), 778 UHCI_TD_GET_MAXLEN(td_token)); 779 780 return (temp); 781 } 782 783 static uint8_t 784 uhci_dump_qh(uhci_qh_t *sqh) 785 { 786 uint8_t temp; 787 uint32_t qh_h_next; 788 uint32_t qh_e_next; 789 790 usb_pc_cpu_invalidate(sqh->page_cache); 791 792 qh_h_next = le32toh(sqh->qh_h_next); 793 qh_e_next = le32toh(sqh->qh_e_next); 794 795 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh, 796 le32toh(sqh->qh_self), qh_h_next, qh_e_next); 797 798 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) | 799 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0)); 800 801 return (temp); 802 } 803 804 static void 805 uhci_dump_all(uhci_softc_t *sc) 806 { 807 uhci_dumpregs(sc); 808 uhci_dump_qh(sc->sc_ls_ctl_p_last); 809 uhci_dump_qh(sc->sc_fs_ctl_p_last); 810 uhci_dump_qh(sc->sc_bulk_p_last); 811 uhci_dump_qh(sc->sc_last_qh_p); 812 } 813 814 static void 815 uhci_dump_tds(uhci_td_t *td) 816 { 817 for (; 818 td != NULL; 819 td = td->obj_next) { 820 if (uhci_dump_td(td)) { 821 break; 822 } 823 } 824 } 825 826 #endif 827 828 /* 829 * Let the last QH loop back to the full speed control transfer QH. 830 * This is what intel calls "bandwidth reclamation" and improves 831 * USB performance a lot for some devices. 832 * If we are already looping, just count it. 833 */ 834 static void 835 uhci_add_loop(uhci_softc_t *sc) 836 { 837 struct uhci_qh *qh_lst; 838 struct uhci_qh *qh_rec; 839 840 #ifdef USB_DEBUG 841 if (uhcinoloop) { 842 return; 843 } 844 #endif 845 if (++(sc->sc_loops) == 1) { 846 DPRINTFN(6, "add\n"); 847 848 qh_lst = sc->sc_last_qh_p; 849 qh_rec = sc->sc_reclaim_qh_p; 850 851 /* NOTE: we don't loop back the soft pointer */ 852 853 qh_lst->qh_h_next = qh_rec->qh_self; 854 usb_pc_cpu_flush(qh_lst->page_cache); 855 } 856 } 857 858 static void 859 uhci_rem_loop(uhci_softc_t *sc) 860 { 861 struct uhci_qh *qh_lst; 862 863 #ifdef USB_DEBUG 864 if (uhcinoloop) { 865 return; 866 } 867 #endif 868 if (--(sc->sc_loops) == 0) { 869 DPRINTFN(6, "remove\n"); 870 871 qh_lst = sc->sc_last_qh_p; 872 qh_lst->qh_h_next = htole32(UHCI_PTR_T); 873 usb_pc_cpu_flush(qh_lst->page_cache); 874 } 875 } 876 877 static void 878 uhci_transfer_intr_enqueue(struct usb_xfer *xfer) 879 { 880 /* check for early completion */ 881 if (uhci_check_transfer(xfer)) { 882 return; 883 } 884 /* put transfer on interrupt queue */ 885 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 886 887 /* start timeout, if any */ 888 if (xfer->timeout != 0) { 889 usbd_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout); 890 } 891 } 892 893 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last) 894 static uhci_td_t * 895 _uhci_append_td(uhci_td_t *std, uhci_td_t *last) 896 { 897 DPRINTFN(11, "%p to %p\n", std, last); 898 899 /* (sc->sc_bus.mtx) must be locked */ 900 901 std->next = last->next; 902 std->td_next = last->td_next; 903 904 std->prev = last; 905 906 usb_pc_cpu_flush(std->page_cache); 907 908 /* 909 * the last->next->prev is never followed: std->next->prev = std; 910 */ 911 last->next = std; 912 last->td_next = std->td_self; 913 914 usb_pc_cpu_flush(last->page_cache); 915 916 return (std); 917 } 918 919 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last) 920 static uhci_qh_t * 921 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last) 922 { 923 DPRINTFN(11, "%p to %p\n", sqh, last); 924 925 if (sqh->h_prev != NULL) { 926 /* should not happen */ 927 DPRINTFN(0, "QH already linked!\n"); 928 return (last); 929 } 930 /* (sc->sc_bus.mtx) must be locked */ 931 932 sqh->h_next = last->h_next; 933 sqh->qh_h_next = last->qh_h_next; 934 935 sqh->h_prev = last; 936 937 usb_pc_cpu_flush(sqh->page_cache); 938 939 /* 940 * The "last->h_next->h_prev" is never followed: 941 * 942 * "sqh->h_next->h_prev" = sqh; 943 */ 944 945 last->h_next = sqh; 946 last->qh_h_next = sqh->qh_self; 947 948 usb_pc_cpu_flush(last->page_cache); 949 950 return (sqh); 951 } 952 953 /**/ 954 955 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last) 956 static uhci_td_t * 957 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last) 958 { 959 DPRINTFN(11, "%p from %p\n", std, last); 960 961 /* (sc->sc_bus.mtx) must be locked */ 962 963 std->prev->next = std->next; 964 std->prev->td_next = std->td_next; 965 966 usb_pc_cpu_flush(std->prev->page_cache); 967 968 if (std->next) { 969 std->next->prev = std->prev; 970 usb_pc_cpu_flush(std->next->page_cache); 971 } 972 return ((last == std) ? std->prev : last); 973 } 974 975 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last) 976 static uhci_qh_t * 977 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last) 978 { 979 DPRINTFN(11, "%p from %p\n", sqh, last); 980 981 /* (sc->sc_bus.mtx) must be locked */ 982 983 /* only remove if not removed from a queue */ 984 if (sqh->h_prev) { 985 986 sqh->h_prev->h_next = sqh->h_next; 987 sqh->h_prev->qh_h_next = sqh->qh_h_next; 988 989 usb_pc_cpu_flush(sqh->h_prev->page_cache); 990 991 if (sqh->h_next) { 992 sqh->h_next->h_prev = sqh->h_prev; 993 usb_pc_cpu_flush(sqh->h_next->page_cache); 994 } 995 last = ((last == sqh) ? sqh->h_prev : last); 996 997 sqh->h_prev = 0; 998 999 usb_pc_cpu_flush(sqh->page_cache); 1000 } 1001 return (last); 1002 } 1003 1004 static void 1005 uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer) 1006 { 1007 struct usb_page_search res; 1008 uint32_t nframes = xfer->nframes; 1009 uint32_t status; 1010 uint32_t offset = 0; 1011 uint32_t *plen = xfer->frlengths; 1012 uint16_t len = 0; 1013 uhci_td_t *td = xfer->td_transfer_first; 1014 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos]; 1015 1016 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1017 xfer, xfer->endpoint); 1018 1019 /* sync any DMA memory before doing fixups */ 1020 1021 usb_bdma_post_sync(xfer); 1022 1023 while (nframes--) { 1024 if (td == NULL) { 1025 panic("%s:%d: out of TD's\n", 1026 __FUNCTION__, __LINE__); 1027 } 1028 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 1029 pp_last = &sc->sc_isoc_p_last[0]; 1030 } 1031 #ifdef USB_DEBUG 1032 if (uhcidebug > 5) { 1033 DPRINTF("isoc TD\n"); 1034 uhci_dump_td(td); 1035 } 1036 #endif 1037 usb_pc_cpu_invalidate(td->page_cache); 1038 status = le32toh(td->td_status); 1039 1040 len = UHCI_TD_GET_ACTLEN(status); 1041 1042 if (len > *plen) { 1043 len = *plen; 1044 } 1045 if (td->fix_pc) { 1046 1047 usbd_get_page(td->fix_pc, 0, &res); 1048 1049 /* copy data from fixup location to real location */ 1050 1051 usb_pc_cpu_invalidate(td->fix_pc); 1052 1053 usbd_copy_in(xfer->frbuffers, offset, 1054 res.buffer, len); 1055 } 1056 offset += *plen; 1057 1058 *plen = len; 1059 1060 /* remove TD from schedule */ 1061 UHCI_REMOVE_TD(td, *pp_last); 1062 1063 pp_last++; 1064 plen++; 1065 td = td->obj_next; 1066 } 1067 1068 xfer->aframes = xfer->nframes; 1069 } 1070 1071 static usb_error_t 1072 uhci_non_isoc_done_sub(struct usb_xfer *xfer) 1073 { 1074 struct usb_page_search res; 1075 uhci_td_t *td; 1076 uhci_td_t *td_alt_next; 1077 uint32_t status; 1078 uint32_t token; 1079 uint16_t len; 1080 1081 td = xfer->td_transfer_cache; 1082 td_alt_next = td->alt_next; 1083 1084 if (xfer->aframes != xfer->nframes) { 1085 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1086 } 1087 while (1) { 1088 1089 usb_pc_cpu_invalidate(td->page_cache); 1090 status = le32toh(td->td_status); 1091 token = le32toh(td->td_token); 1092 1093 /* 1094 * Verify the status and add 1095 * up the actual length: 1096 */ 1097 1098 len = UHCI_TD_GET_ACTLEN(status); 1099 if (len > td->len) { 1100 /* should not happen */ 1101 DPRINTF("Invalid status length, " 1102 "0x%04x/0x%04x bytes\n", len, td->len); 1103 status |= UHCI_TD_STALLED; 1104 1105 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) { 1106 1107 if (td->fix_pc) { 1108 1109 usbd_get_page(td->fix_pc, 0, &res); 1110 1111 /* 1112 * copy data from fixup location to real 1113 * location 1114 */ 1115 1116 usb_pc_cpu_invalidate(td->fix_pc); 1117 1118 usbd_copy_in(xfer->frbuffers + xfer->aframes, 1119 xfer->frlengths[xfer->aframes], res.buffer, len); 1120 } 1121 /* update actual length */ 1122 1123 xfer->frlengths[xfer->aframes] += len; 1124 } 1125 /* Check for last transfer */ 1126 if (((void *)td) == xfer->td_transfer_last) { 1127 td = NULL; 1128 break; 1129 } 1130 if (status & UHCI_TD_STALLED) { 1131 /* the transfer is finished */ 1132 td = NULL; 1133 break; 1134 } 1135 /* Check for short transfer */ 1136 if (len != td->len) { 1137 if (xfer->flags_int.short_frames_ok) { 1138 /* follow alt next */ 1139 td = td->alt_next; 1140 } else { 1141 /* the transfer is finished */ 1142 td = NULL; 1143 } 1144 break; 1145 } 1146 td = td->obj_next; 1147 1148 if (td->alt_next != td_alt_next) { 1149 /* this USB frame is complete */ 1150 break; 1151 } 1152 } 1153 1154 /* update transfer cache */ 1155 1156 xfer->td_transfer_cache = td; 1157 1158 /* update data toggle */ 1159 1160 xfer->endpoint->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1; 1161 1162 #ifdef USB_DEBUG 1163 if (status & UHCI_TD_ERROR) { 1164 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x " 1165 "status=%s%s%s%s%s%s%s%s%s%s%s\n", 1166 xfer->address, xfer->endpointno, xfer->aframes, 1167 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "", 1168 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "", 1169 (status & UHCI_TD_NAK) ? "[NAK]" : "", 1170 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "", 1171 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "", 1172 (status & UHCI_TD_STALLED) ? "[STALLED]" : "", 1173 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1174 (status & UHCI_TD_IOC) ? "[IOC]" : "", 1175 (status & UHCI_TD_IOS) ? "[IOS]" : "", 1176 (status & UHCI_TD_LS) ? "[LS]" : "", 1177 (status & UHCI_TD_SPD) ? "[SPD]" : ""); 1178 } 1179 #endif 1180 return (status & UHCI_TD_STALLED) ? 1181 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION; 1182 } 1183 1184 static void 1185 uhci_non_isoc_done(struct usb_xfer *xfer) 1186 { 1187 usb_error_t err = 0; 1188 1189 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1190 xfer, xfer->endpoint); 1191 1192 #ifdef USB_DEBUG 1193 if (uhcidebug > 10) { 1194 uhci_dump_tds(xfer->td_transfer_first); 1195 } 1196 #endif 1197 1198 /* sync any DMA memory before doing fixups */ 1199 1200 usb_bdma_post_sync(xfer); 1201 1202 /* reset scanner */ 1203 1204 xfer->td_transfer_cache = xfer->td_transfer_first; 1205 1206 if (xfer->flags_int.control_xfr) { 1207 if (xfer->flags_int.control_hdr) { 1208 1209 err = uhci_non_isoc_done_sub(xfer); 1210 } 1211 xfer->aframes = 1; 1212 1213 if (xfer->td_transfer_cache == NULL) { 1214 goto done; 1215 } 1216 } 1217 while (xfer->aframes != xfer->nframes) { 1218 1219 err = uhci_non_isoc_done_sub(xfer); 1220 xfer->aframes++; 1221 1222 if (xfer->td_transfer_cache == NULL) { 1223 goto done; 1224 } 1225 } 1226 1227 if (xfer->flags_int.control_xfr && 1228 !xfer->flags_int.control_act) { 1229 1230 err = uhci_non_isoc_done_sub(xfer); 1231 } 1232 done: 1233 uhci_device_done(xfer, err); 1234 } 1235 1236 /*------------------------------------------------------------------------* 1237 * uhci_check_transfer_sub 1238 * 1239 * The main purpose of this function is to update the data-toggle 1240 * in case it is wrong. 1241 *------------------------------------------------------------------------*/ 1242 static void 1243 uhci_check_transfer_sub(struct usb_xfer *xfer) 1244 { 1245 uhci_qh_t *qh; 1246 uhci_td_t *td; 1247 uhci_td_t *td_alt_next; 1248 1249 uint32_t td_token; 1250 uint32_t td_self; 1251 1252 td = xfer->td_transfer_cache; 1253 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1254 1255 td_token = td->obj_next->td_token; 1256 td = td->alt_next; 1257 xfer->td_transfer_cache = td; 1258 td_self = td->td_self; 1259 td_alt_next = td->alt_next; 1260 1261 if (xfer->flags_int.control_xfr) 1262 goto skip; /* don't touch the DT value! */ 1263 1264 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1)))) 1265 goto skip; /* data toggle has correct value */ 1266 1267 /* 1268 * The data toggle is wrong and we need to toggle it ! 1269 */ 1270 while (1) { 1271 1272 td->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1273 usb_pc_cpu_flush(td->page_cache); 1274 1275 if (td == xfer->td_transfer_last) { 1276 /* last transfer */ 1277 break; 1278 } 1279 td = td->obj_next; 1280 1281 if (td->alt_next != td_alt_next) { 1282 /* next frame */ 1283 break; 1284 } 1285 } 1286 skip: 1287 1288 /* update the QH */ 1289 qh->qh_e_next = td_self; 1290 usb_pc_cpu_flush(qh->page_cache); 1291 1292 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1293 } 1294 1295 /*------------------------------------------------------------------------* 1296 * uhci_check_transfer 1297 * 1298 * Return values: 1299 * 0: USB transfer is not finished 1300 * Else: USB transfer is finished 1301 *------------------------------------------------------------------------*/ 1302 static uint8_t 1303 uhci_check_transfer(struct usb_xfer *xfer) 1304 { 1305 uint32_t status; 1306 uint32_t token; 1307 uhci_td_t *td; 1308 1309 DPRINTFN(16, "xfer=%p checking transfer\n", xfer); 1310 1311 if (xfer->endpoint->methods == &uhci_device_isoc_methods) { 1312 /* isochronous transfer */ 1313 1314 td = xfer->td_transfer_last; 1315 1316 usb_pc_cpu_invalidate(td->page_cache); 1317 status = le32toh(td->td_status); 1318 1319 /* check also if the first is complete */ 1320 1321 td = xfer->td_transfer_first; 1322 1323 usb_pc_cpu_invalidate(td->page_cache); 1324 status |= le32toh(td->td_status); 1325 1326 if (!(status & UHCI_TD_ACTIVE)) { 1327 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1328 goto transferred; 1329 } 1330 } else { 1331 /* non-isochronous transfer */ 1332 1333 /* 1334 * check whether there is an error somewhere 1335 * in the middle, or whether there was a short 1336 * packet (SPD and not ACTIVE) 1337 */ 1338 td = xfer->td_transfer_cache; 1339 1340 while (1) { 1341 usb_pc_cpu_invalidate(td->page_cache); 1342 status = le32toh(td->td_status); 1343 token = le32toh(td->td_token); 1344 1345 /* 1346 * if there is an active TD the transfer isn't done 1347 */ 1348 if (status & UHCI_TD_ACTIVE) { 1349 /* update cache */ 1350 xfer->td_transfer_cache = td; 1351 goto done; 1352 } 1353 /* 1354 * last transfer descriptor makes the transfer done 1355 */ 1356 if (((void *)td) == xfer->td_transfer_last) { 1357 break; 1358 } 1359 /* 1360 * any kind of error makes the transfer done 1361 */ 1362 if (status & UHCI_TD_STALLED) { 1363 break; 1364 } 1365 /* 1366 * check if we reached the last packet 1367 * or if there is a short packet: 1368 */ 1369 if ((td->td_next == htole32(UHCI_PTR_T)) || 1370 (UHCI_TD_GET_ACTLEN(status) < td->len)) { 1371 1372 if (xfer->flags_int.short_frames_ok) { 1373 /* follow alt next */ 1374 if (td->alt_next) { 1375 /* update cache */ 1376 xfer->td_transfer_cache = td; 1377 uhci_check_transfer_sub(xfer); 1378 goto done; 1379 } 1380 } 1381 /* transfer is done */ 1382 break; 1383 } 1384 td = td->obj_next; 1385 } 1386 uhci_non_isoc_done(xfer); 1387 goto transferred; 1388 } 1389 1390 done: 1391 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1392 return (0); 1393 1394 transferred: 1395 return (1); 1396 } 1397 1398 static void 1399 uhci_interrupt_poll(uhci_softc_t *sc) 1400 { 1401 struct usb_xfer *xfer; 1402 1403 repeat: 1404 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1405 /* 1406 * check if transfer is transferred 1407 */ 1408 if (uhci_check_transfer(xfer)) { 1409 /* queue has been modified */ 1410 goto repeat; 1411 } 1412 } 1413 } 1414 1415 /*------------------------------------------------------------------------* 1416 * uhci_interrupt - UHCI interrupt handler 1417 * 1418 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1419 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1420 * is present ! 1421 *------------------------------------------------------------------------*/ 1422 void 1423 uhci_interrupt(uhci_softc_t *sc) 1424 { 1425 uint32_t status; 1426 1427 USB_BUS_LOCK(&sc->sc_bus); 1428 1429 DPRINTFN(16, "real interrupt\n"); 1430 1431 #ifdef USB_DEBUG 1432 if (uhcidebug > 15) { 1433 uhci_dumpregs(sc); 1434 } 1435 #endif 1436 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1437 if (status == 0) { 1438 /* the interrupt was not for us */ 1439 goto done; 1440 } 1441 if (status & (UHCI_STS_RD | UHCI_STS_HSE | 1442 UHCI_STS_HCPE | UHCI_STS_HCH)) { 1443 1444 if (status & UHCI_STS_RD) { 1445 #ifdef USB_DEBUG 1446 printf("%s: resume detect\n", 1447 __FUNCTION__); 1448 #endif 1449 } 1450 if (status & UHCI_STS_HSE) { 1451 printf("%s: host system error\n", 1452 __FUNCTION__); 1453 } 1454 if (status & UHCI_STS_HCPE) { 1455 printf("%s: host controller process error\n", 1456 __FUNCTION__); 1457 } 1458 if (status & UHCI_STS_HCH) { 1459 /* no acknowledge needed */ 1460 DPRINTF("%s: host controller halted\n", 1461 __FUNCTION__); 1462 #ifdef USB_DEBUG 1463 if (uhcidebug > 0) { 1464 uhci_dump_all(sc); 1465 } 1466 #endif 1467 } 1468 } 1469 /* get acknowledge bits */ 1470 status &= (UHCI_STS_USBINT | 1471 UHCI_STS_USBEI | 1472 UHCI_STS_RD | 1473 UHCI_STS_HSE | 1474 UHCI_STS_HCPE); 1475 1476 if (status == 0) { 1477 /* nothing to acknowledge */ 1478 goto done; 1479 } 1480 /* acknowledge interrupts */ 1481 UWRITE2(sc, UHCI_STS, status); 1482 1483 /* poll all the USB transfers */ 1484 uhci_interrupt_poll(sc); 1485 1486 done: 1487 USB_BUS_UNLOCK(&sc->sc_bus); 1488 } 1489 1490 /* 1491 * called when a request does not complete 1492 */ 1493 static void 1494 uhci_timeout(void *arg) 1495 { 1496 struct usb_xfer *xfer = arg; 1497 1498 DPRINTF("xfer=%p\n", xfer); 1499 1500 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1501 1502 /* transfer is transferred */ 1503 uhci_device_done(xfer, USB_ERR_TIMEOUT); 1504 } 1505 1506 static void 1507 uhci_do_poll(struct usb_bus *bus) 1508 { 1509 struct uhci_softc *sc = UHCI_BUS2SC(bus); 1510 1511 USB_BUS_LOCK(&sc->sc_bus); 1512 uhci_interrupt_poll(sc); 1513 USB_BUS_UNLOCK(&sc->sc_bus); 1514 } 1515 1516 static void 1517 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp) 1518 { 1519 uhci_td_t *td; 1520 uhci_td_t *td_next; 1521 uhci_td_t *td_alt_next; 1522 uint32_t average; 1523 uint32_t len_old; 1524 uint8_t shortpkt_old; 1525 uint8_t precompute; 1526 1527 td_alt_next = NULL; 1528 shortpkt_old = temp->shortpkt; 1529 len_old = temp->len; 1530 precompute = 1; 1531 1532 /* software is used to detect short incoming transfers */ 1533 1534 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) { 1535 temp->td_status |= htole32(UHCI_TD_SPD); 1536 } else { 1537 temp->td_status &= ~htole32(UHCI_TD_SPD); 1538 } 1539 1540 temp->ml.buf_offset = 0; 1541 1542 restart: 1543 1544 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1545 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average)); 1546 1547 td = temp->td; 1548 td_next = temp->td_next; 1549 1550 while (1) { 1551 1552 if (temp->len == 0) { 1553 1554 if (temp->shortpkt) { 1555 break; 1556 } 1557 /* send a Zero Length Packet, ZLP, last */ 1558 1559 temp->shortpkt = 1; 1560 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0)); 1561 average = 0; 1562 1563 } else { 1564 1565 average = temp->average; 1566 1567 if (temp->len < average) { 1568 temp->shortpkt = 1; 1569 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1570 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len)); 1571 average = temp->len; 1572 } 1573 } 1574 1575 if (td_next == NULL) { 1576 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__); 1577 } 1578 /* get next TD */ 1579 1580 td = td_next; 1581 td_next = td->obj_next; 1582 1583 /* check if we are pre-computing */ 1584 1585 if (precompute) { 1586 1587 /* update remaining length */ 1588 1589 temp->len -= average; 1590 1591 continue; 1592 } 1593 /* fill out current TD */ 1594 1595 td->td_status = temp->td_status; 1596 td->td_token = temp->td_token; 1597 1598 /* update data toggle */ 1599 1600 temp->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1601 1602 if (average == 0) { 1603 1604 td->len = 0; 1605 td->td_buffer = 0; 1606 td->fix_pc = NULL; 1607 1608 } else { 1609 1610 /* update remaining length */ 1611 1612 temp->len -= average; 1613 1614 td->len = average; 1615 1616 /* fill out buffer pointer and do fixup, if any */ 1617 1618 uhci_mem_layout_fixup(&temp->ml, td); 1619 } 1620 1621 td->alt_next = td_alt_next; 1622 1623 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1624 /* we need to receive these frames one by one ! */ 1625 td->td_status |= htole32(UHCI_TD_IOC); 1626 td->td_next = htole32(UHCI_PTR_T); 1627 } else { 1628 if (td_next) { 1629 /* link the current TD with the next one */ 1630 td->td_next = td_next->td_self; 1631 } 1632 } 1633 1634 usb_pc_cpu_flush(td->page_cache); 1635 } 1636 1637 if (precompute) { 1638 precompute = 0; 1639 1640 /* setup alt next pointer, if any */ 1641 if (temp->last_frame) { 1642 td_alt_next = NULL; 1643 } else { 1644 /* we use this field internally */ 1645 td_alt_next = td_next; 1646 } 1647 1648 /* restore */ 1649 temp->shortpkt = shortpkt_old; 1650 temp->len = len_old; 1651 goto restart; 1652 } 1653 temp->td = td; 1654 temp->td_next = td_next; 1655 } 1656 1657 static uhci_td_t * 1658 uhci_setup_standard_chain(struct usb_xfer *xfer) 1659 { 1660 struct uhci_std_temp temp; 1661 uhci_td_t *td; 1662 uint32_t x; 1663 1664 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1665 xfer->address, UE_GET_ADDR(xfer->endpointno), 1666 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1667 1668 temp.average = xfer->max_frame_size; 1669 temp.max_frame_size = xfer->max_frame_size; 1670 1671 /* toggle the DMA set we are using */ 1672 xfer->flags_int.curr_dma_set ^= 1; 1673 1674 /* get next DMA set */ 1675 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1676 xfer->td_transfer_first = td; 1677 xfer->td_transfer_cache = td; 1678 1679 temp.td = NULL; 1680 temp.td_next = td; 1681 temp.last_frame = 0; 1682 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1683 1684 uhci_mem_layout_init(&temp.ml, xfer); 1685 1686 temp.td_status = 1687 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | 1688 UHCI_TD_ACTIVE)); 1689 1690 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1691 temp.td_status |= htole32(UHCI_TD_LS); 1692 } 1693 temp.td_token = 1694 htole32(UHCI_TD_SET_ENDPT(xfer->endpointno) | 1695 UHCI_TD_SET_DEVADDR(xfer->address)); 1696 1697 if (xfer->endpoint->toggle_next) { 1698 /* DATA1 is next */ 1699 temp.td_token |= htole32(UHCI_TD_SET_DT(1)); 1700 } 1701 /* check if we should prepend a setup message */ 1702 1703 if (xfer->flags_int.control_xfr) { 1704 1705 if (xfer->flags_int.control_hdr) { 1706 1707 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1708 UHCI_TD_SET_ENDPT(0xF)); 1709 temp.td_token |= htole32(UHCI_TD_PID_SETUP | 1710 UHCI_TD_SET_DT(0)); 1711 1712 temp.len = xfer->frlengths[0]; 1713 temp.ml.buf_pc = xfer->frbuffers + 0; 1714 temp.shortpkt = temp.len ? 1 : 0; 1715 /* check for last frame */ 1716 if (xfer->nframes == 1) { 1717 /* no STATUS stage yet, SETUP is last */ 1718 if (xfer->flags_int.control_act) { 1719 temp.last_frame = 1; 1720 temp.setup_alt_next = 0; 1721 } 1722 } 1723 uhci_setup_standard_chain_sub(&temp); 1724 } 1725 x = 1; 1726 } else { 1727 x = 0; 1728 } 1729 1730 while (x != xfer->nframes) { 1731 1732 /* DATA0 / DATA1 message */ 1733 1734 temp.len = xfer->frlengths[x]; 1735 temp.ml.buf_pc = xfer->frbuffers + x; 1736 1737 x++; 1738 1739 if (x == xfer->nframes) { 1740 if (xfer->flags_int.control_xfr) { 1741 /* no STATUS stage yet, DATA is last */ 1742 if (xfer->flags_int.control_act) { 1743 temp.last_frame = 1; 1744 temp.setup_alt_next = 0; 1745 } 1746 } else { 1747 temp.last_frame = 1; 1748 temp.setup_alt_next = 0; 1749 } 1750 } 1751 /* 1752 * Keep previous data toggle, 1753 * device address and endpoint number: 1754 */ 1755 1756 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1757 UHCI_TD_SET_ENDPT(0xF) | 1758 UHCI_TD_SET_DT(1)); 1759 1760 if (temp.len == 0) { 1761 1762 /* make sure that we send an USB packet */ 1763 1764 temp.shortpkt = 0; 1765 1766 } else { 1767 1768 /* regular data transfer */ 1769 1770 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1771 } 1772 1773 /* set endpoint direction */ 1774 1775 temp.td_token |= 1776 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1777 htole32(UHCI_TD_PID_IN) : 1778 htole32(UHCI_TD_PID_OUT); 1779 1780 uhci_setup_standard_chain_sub(&temp); 1781 } 1782 1783 /* check if we should append a status stage */ 1784 1785 if (xfer->flags_int.control_xfr && 1786 !xfer->flags_int.control_act) { 1787 1788 /* 1789 * send a DATA1 message and reverse the current endpoint 1790 * direction 1791 */ 1792 1793 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1794 UHCI_TD_SET_ENDPT(0xF) | 1795 UHCI_TD_SET_DT(1)); 1796 temp.td_token |= 1797 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1798 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) : 1799 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1)); 1800 1801 temp.len = 0; 1802 temp.ml.buf_pc = NULL; 1803 temp.shortpkt = 0; 1804 temp.last_frame = 1; 1805 temp.setup_alt_next = 0; 1806 1807 uhci_setup_standard_chain_sub(&temp); 1808 } 1809 td = temp.td; 1810 1811 /* Ensure that last TD is terminating: */ 1812 td->td_next = htole32(UHCI_PTR_T); 1813 1814 /* set interrupt bit */ 1815 1816 td->td_status |= htole32(UHCI_TD_IOC); 1817 1818 usb_pc_cpu_flush(td->page_cache); 1819 1820 /* must have at least one frame! */ 1821 1822 xfer->td_transfer_last = td; 1823 1824 #ifdef USB_DEBUG 1825 if (uhcidebug > 8) { 1826 DPRINTF("nexttog=%d; data before transfer:\n", 1827 xfer->endpoint->toggle_next); 1828 uhci_dump_tds(xfer->td_transfer_first); 1829 } 1830 #endif 1831 return (xfer->td_transfer_first); 1832 } 1833 1834 /* NOTE: "done" can be run two times in a row, 1835 * from close and from interrupt 1836 */ 1837 1838 static void 1839 uhci_device_done(struct usb_xfer *xfer, usb_error_t error) 1840 { 1841 struct usb_pipe_methods *methods = xfer->endpoint->methods; 1842 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1843 uhci_qh_t *qh; 1844 1845 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1846 1847 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1848 xfer, xfer->endpoint, error); 1849 1850 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1851 if (qh) { 1852 usb_pc_cpu_invalidate(qh->page_cache); 1853 } 1854 if (xfer->flags_int.bandwidth_reclaimed) { 1855 xfer->flags_int.bandwidth_reclaimed = 0; 1856 uhci_rem_loop(sc); 1857 } 1858 if (methods == &uhci_device_bulk_methods) { 1859 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 1860 } 1861 if (methods == &uhci_device_ctrl_methods) { 1862 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1863 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 1864 } else { 1865 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 1866 } 1867 } 1868 if (methods == &uhci_device_intr_methods) { 1869 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 1870 } 1871 /* 1872 * Only finish isochronous transfers once 1873 * which will update "xfer->frlengths". 1874 */ 1875 if (xfer->td_transfer_first && 1876 xfer->td_transfer_last) { 1877 if (methods == &uhci_device_isoc_methods) { 1878 uhci_isoc_done(sc, xfer); 1879 } 1880 xfer->td_transfer_first = NULL; 1881 xfer->td_transfer_last = NULL; 1882 } 1883 /* dequeue transfer and start next transfer */ 1884 usbd_transfer_done(xfer, error); 1885 } 1886 1887 /*------------------------------------------------------------------------* 1888 * uhci bulk support 1889 *------------------------------------------------------------------------*/ 1890 static void 1891 uhci_device_bulk_open(struct usb_xfer *xfer) 1892 { 1893 return; 1894 } 1895 1896 static void 1897 uhci_device_bulk_close(struct usb_xfer *xfer) 1898 { 1899 uhci_device_done(xfer, USB_ERR_CANCELLED); 1900 } 1901 1902 static void 1903 uhci_device_bulk_enter(struct usb_xfer *xfer) 1904 { 1905 return; 1906 } 1907 1908 static void 1909 uhci_device_bulk_start(struct usb_xfer *xfer) 1910 { 1911 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1912 uhci_td_t *td; 1913 uhci_qh_t *qh; 1914 1915 /* setup TD's */ 1916 td = uhci_setup_standard_chain(xfer); 1917 1918 /* setup QH */ 1919 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1920 1921 qh->e_next = td; 1922 qh->qh_e_next = td->td_self; 1923 1924 if (xfer->xroot->udev->flags.self_suspended == 0) { 1925 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 1926 uhci_add_loop(sc); 1927 xfer->flags_int.bandwidth_reclaimed = 1; 1928 } else { 1929 usb_pc_cpu_flush(qh->page_cache); 1930 } 1931 1932 /* put transfer on interrupt queue */ 1933 uhci_transfer_intr_enqueue(xfer); 1934 } 1935 1936 struct usb_pipe_methods uhci_device_bulk_methods = 1937 { 1938 .open = uhci_device_bulk_open, 1939 .close = uhci_device_bulk_close, 1940 .enter = uhci_device_bulk_enter, 1941 .start = uhci_device_bulk_start, 1942 }; 1943 1944 /*------------------------------------------------------------------------* 1945 * uhci control support 1946 *------------------------------------------------------------------------*/ 1947 static void 1948 uhci_device_ctrl_open(struct usb_xfer *xfer) 1949 { 1950 return; 1951 } 1952 1953 static void 1954 uhci_device_ctrl_close(struct usb_xfer *xfer) 1955 { 1956 uhci_device_done(xfer, USB_ERR_CANCELLED); 1957 } 1958 1959 static void 1960 uhci_device_ctrl_enter(struct usb_xfer *xfer) 1961 { 1962 return; 1963 } 1964 1965 static void 1966 uhci_device_ctrl_start(struct usb_xfer *xfer) 1967 { 1968 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1969 uhci_qh_t *qh; 1970 uhci_td_t *td; 1971 1972 /* setup TD's */ 1973 td = uhci_setup_standard_chain(xfer); 1974 1975 /* setup QH */ 1976 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1977 1978 qh->e_next = td; 1979 qh->qh_e_next = td->td_self; 1980 1981 /* 1982 * NOTE: some devices choke on bandwidth- reclamation for control 1983 * transfers 1984 */ 1985 if (xfer->xroot->udev->flags.self_suspended == 0) { 1986 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1987 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 1988 } else { 1989 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 1990 } 1991 } else { 1992 usb_pc_cpu_flush(qh->page_cache); 1993 } 1994 /* put transfer on interrupt queue */ 1995 uhci_transfer_intr_enqueue(xfer); 1996 } 1997 1998 struct usb_pipe_methods uhci_device_ctrl_methods = 1999 { 2000 .open = uhci_device_ctrl_open, 2001 .close = uhci_device_ctrl_close, 2002 .enter = uhci_device_ctrl_enter, 2003 .start = uhci_device_ctrl_start, 2004 }; 2005 2006 /*------------------------------------------------------------------------* 2007 * uhci interrupt support 2008 *------------------------------------------------------------------------*/ 2009 static void 2010 uhci_device_intr_open(struct usb_xfer *xfer) 2011 { 2012 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2013 uint16_t best; 2014 uint16_t bit; 2015 uint16_t x; 2016 2017 best = 0; 2018 bit = UHCI_IFRAMELIST_COUNT / 2; 2019 while (bit) { 2020 if (xfer->interval >= bit) { 2021 x = bit; 2022 best = bit; 2023 while (x & bit) { 2024 if (sc->sc_intr_stat[x] < 2025 sc->sc_intr_stat[best]) { 2026 best = x; 2027 } 2028 x++; 2029 } 2030 break; 2031 } 2032 bit >>= 1; 2033 } 2034 2035 sc->sc_intr_stat[best]++; 2036 xfer->qh_pos = best; 2037 2038 DPRINTFN(3, "best=%d interval=%d\n", 2039 best, xfer->interval); 2040 } 2041 2042 static void 2043 uhci_device_intr_close(struct usb_xfer *xfer) 2044 { 2045 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2046 2047 sc->sc_intr_stat[xfer->qh_pos]--; 2048 2049 uhci_device_done(xfer, USB_ERR_CANCELLED); 2050 } 2051 2052 static void 2053 uhci_device_intr_enter(struct usb_xfer *xfer) 2054 { 2055 return; 2056 } 2057 2058 static void 2059 uhci_device_intr_start(struct usb_xfer *xfer) 2060 { 2061 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2062 uhci_qh_t *qh; 2063 uhci_td_t *td; 2064 2065 /* setup TD's */ 2066 td = uhci_setup_standard_chain(xfer); 2067 2068 /* setup QH */ 2069 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2070 2071 qh->e_next = td; 2072 qh->qh_e_next = td->td_self; 2073 2074 if (xfer->xroot->udev->flags.self_suspended == 0) { 2075 /* enter QHs into the controller data structures */ 2076 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 2077 } else { 2078 usb_pc_cpu_flush(qh->page_cache); 2079 } 2080 2081 /* put transfer on interrupt queue */ 2082 uhci_transfer_intr_enqueue(xfer); 2083 } 2084 2085 struct usb_pipe_methods uhci_device_intr_methods = 2086 { 2087 .open = uhci_device_intr_open, 2088 .close = uhci_device_intr_close, 2089 .enter = uhci_device_intr_enter, 2090 .start = uhci_device_intr_start, 2091 }; 2092 2093 /*------------------------------------------------------------------------* 2094 * uhci isochronous support 2095 *------------------------------------------------------------------------*/ 2096 static void 2097 uhci_device_isoc_open(struct usb_xfer *xfer) 2098 { 2099 uhci_td_t *td; 2100 uint32_t td_token; 2101 uint8_t ds; 2102 2103 td_token = 2104 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 2105 UHCI_TD_IN(0, xfer->endpointno, xfer->address, 0) : 2106 UHCI_TD_OUT(0, xfer->endpointno, xfer->address, 0); 2107 2108 td_token = htole32(td_token); 2109 2110 /* initialize all TD's */ 2111 2112 for (ds = 0; ds != 2; ds++) { 2113 2114 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2115 2116 /* mark TD as inactive */ 2117 td->td_status = htole32(UHCI_TD_IOS); 2118 td->td_token = td_token; 2119 2120 usb_pc_cpu_flush(td->page_cache); 2121 } 2122 } 2123 } 2124 2125 static void 2126 uhci_device_isoc_close(struct usb_xfer *xfer) 2127 { 2128 uhci_device_done(xfer, USB_ERR_CANCELLED); 2129 } 2130 2131 static void 2132 uhci_device_isoc_enter(struct usb_xfer *xfer) 2133 { 2134 struct uhci_mem_layout ml; 2135 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2136 uint32_t nframes; 2137 uint32_t temp; 2138 uint32_t *plen; 2139 2140 #ifdef USB_DEBUG 2141 uint8_t once = 1; 2142 2143 #endif 2144 uhci_td_t *td; 2145 uhci_td_t *td_last = NULL; 2146 uhci_td_t **pp_last; 2147 2148 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2149 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2150 2151 nframes = UREAD2(sc, UHCI_FRNUM); 2152 2153 temp = (nframes - xfer->endpoint->isoc_next) & 2154 (UHCI_VFRAMELIST_COUNT - 1); 2155 2156 if ((xfer->endpoint->is_synced == 0) || 2157 (temp < xfer->nframes)) { 2158 /* 2159 * If there is data underflow or the pipe queue is empty we 2160 * schedule the transfer a few frames ahead of the current 2161 * frame position. Else two isochronous transfers might 2162 * overlap. 2163 */ 2164 xfer->endpoint->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1); 2165 xfer->endpoint->is_synced = 1; 2166 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2167 } 2168 /* 2169 * compute how many milliseconds the insertion is ahead of the 2170 * current frame position: 2171 */ 2172 temp = (xfer->endpoint->isoc_next - nframes) & 2173 (UHCI_VFRAMELIST_COUNT - 1); 2174 2175 /* 2176 * pre-compute when the isochronous transfer will be finished: 2177 */ 2178 xfer->isoc_time_complete = 2179 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2180 xfer->nframes; 2181 2182 /* get the real number of frames */ 2183 2184 nframes = xfer->nframes; 2185 2186 uhci_mem_layout_init(&ml, xfer); 2187 2188 plen = xfer->frlengths; 2189 2190 /* toggle the DMA set we are using */ 2191 xfer->flags_int.curr_dma_set ^= 1; 2192 2193 /* get next DMA set */ 2194 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2195 xfer->td_transfer_first = td; 2196 2197 pp_last = &sc->sc_isoc_p_last[xfer->endpoint->isoc_next]; 2198 2199 /* store starting position */ 2200 2201 xfer->qh_pos = xfer->endpoint->isoc_next; 2202 2203 while (nframes--) { 2204 if (td == NULL) { 2205 panic("%s:%d: out of TD's\n", 2206 __FUNCTION__, __LINE__); 2207 } 2208 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 2209 pp_last = &sc->sc_isoc_p_last[0]; 2210 } 2211 if (*plen > xfer->max_frame_size) { 2212 #ifdef USB_DEBUG 2213 if (once) { 2214 once = 0; 2215 printf("%s: frame length(%d) exceeds %d " 2216 "bytes (frame truncated)\n", 2217 __FUNCTION__, *plen, 2218 xfer->max_frame_size); 2219 } 2220 #endif 2221 *plen = xfer->max_frame_size; 2222 } 2223 /* reuse td_token from last transfer */ 2224 2225 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2226 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen)); 2227 2228 td->len = *plen; 2229 2230 if (td->len == 0) { 2231 /* 2232 * Do not call "uhci_mem_layout_fixup()" when the 2233 * length is zero! 2234 */ 2235 td->td_buffer = 0; 2236 td->fix_pc = NULL; 2237 2238 } else { 2239 2240 /* fill out buffer pointer and do fixup, if any */ 2241 2242 uhci_mem_layout_fixup(&ml, td); 2243 2244 } 2245 2246 /* update status */ 2247 if (nframes == 0) { 2248 td->td_status = htole32 2249 (UHCI_TD_ZERO_ACTLEN 2250 (UHCI_TD_SET_ERRCNT(0) | 2251 UHCI_TD_ACTIVE | 2252 UHCI_TD_IOS | 2253 UHCI_TD_IOC)); 2254 } else { 2255 td->td_status = htole32 2256 (UHCI_TD_ZERO_ACTLEN 2257 (UHCI_TD_SET_ERRCNT(0) | 2258 UHCI_TD_ACTIVE | 2259 UHCI_TD_IOS)); 2260 } 2261 2262 usb_pc_cpu_flush(td->page_cache); 2263 2264 #ifdef USB_DEBUG 2265 if (uhcidebug > 5) { 2266 DPRINTF("TD %d\n", nframes); 2267 uhci_dump_td(td); 2268 } 2269 #endif 2270 /* insert TD into schedule */ 2271 UHCI_APPEND_TD(td, *pp_last); 2272 pp_last++; 2273 2274 plen++; 2275 td_last = td; 2276 td = td->obj_next; 2277 } 2278 2279 xfer->td_transfer_last = td_last; 2280 2281 /* update isoc_next */ 2282 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) & 2283 (UHCI_VFRAMELIST_COUNT - 1); 2284 } 2285 2286 static void 2287 uhci_device_isoc_start(struct usb_xfer *xfer) 2288 { 2289 /* put transfer on interrupt queue */ 2290 uhci_transfer_intr_enqueue(xfer); 2291 } 2292 2293 struct usb_pipe_methods uhci_device_isoc_methods = 2294 { 2295 .open = uhci_device_isoc_open, 2296 .close = uhci_device_isoc_close, 2297 .enter = uhci_device_isoc_enter, 2298 .start = uhci_device_isoc_start, 2299 }; 2300 2301 /*------------------------------------------------------------------------* 2302 * uhci root control support 2303 *------------------------------------------------------------------------* 2304 * Simulate a hardware hub by handling all the necessary requests. 2305 *------------------------------------------------------------------------*/ 2306 2307 static const 2308 struct usb_device_descriptor uhci_devd = 2309 { 2310 sizeof(struct usb_device_descriptor), 2311 UDESC_DEVICE, /* type */ 2312 {0x00, 0x01}, /* USB version */ 2313 UDCLASS_HUB, /* class */ 2314 UDSUBCLASS_HUB, /* subclass */ 2315 UDPROTO_FSHUB, /* protocol */ 2316 64, /* max packet */ 2317 {0}, {0}, {0x00, 0x01}, /* device id */ 2318 1, 2, 0, /* string indicies */ 2319 1 /* # of configurations */ 2320 }; 2321 2322 static const struct uhci_config_desc uhci_confd = { 2323 .confd = { 2324 .bLength = sizeof(struct usb_config_descriptor), 2325 .bDescriptorType = UDESC_CONFIG, 2326 .wTotalLength[0] = sizeof(uhci_confd), 2327 .bNumInterface = 1, 2328 .bConfigurationValue = 1, 2329 .iConfiguration = 0, 2330 .bmAttributes = UC_SELF_POWERED, 2331 .bMaxPower = 0 /* max power */ 2332 }, 2333 .ifcd = { 2334 .bLength = sizeof(struct usb_interface_descriptor), 2335 .bDescriptorType = UDESC_INTERFACE, 2336 .bNumEndpoints = 1, 2337 .bInterfaceClass = UICLASS_HUB, 2338 .bInterfaceSubClass = UISUBCLASS_HUB, 2339 .bInterfaceProtocol = UIPROTO_FSHUB, 2340 }, 2341 .endpd = { 2342 .bLength = sizeof(struct usb_endpoint_descriptor), 2343 .bDescriptorType = UDESC_ENDPOINT, 2344 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 2345 .bmAttributes = UE_INTERRUPT, 2346 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2347 .bInterval = 255, 2348 }, 2349 }; 2350 2351 static const 2352 struct usb_hub_descriptor_min uhci_hubd_piix = 2353 { 2354 .bDescLength = sizeof(uhci_hubd_piix), 2355 .bDescriptorType = UDESC_HUB, 2356 .bNbrPorts = 2, 2357 .wHubCharacteristics = {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0}, 2358 .bPwrOn2PwrGood = 50, 2359 }; 2360 2361 /* 2362 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 2363 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 2364 * should not be used by the USB subsystem. As we cannot issue a 2365 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 2366 * will be enabled as part of the reset. 2367 * 2368 * On the VT83C572, the port cannot be successfully enabled until the 2369 * outstanding "port enable change" and "connection status change" 2370 * events have been reset. 2371 */ 2372 static usb_error_t 2373 uhci_portreset(uhci_softc_t *sc, uint16_t index) 2374 { 2375 uint16_t port; 2376 uint16_t x; 2377 uint8_t lim; 2378 2379 if (index == 1) 2380 port = UHCI_PORTSC1; 2381 else if (index == 2) 2382 port = UHCI_PORTSC2; 2383 else 2384 return (USB_ERR_IOERROR); 2385 2386 /* 2387 * Before we do anything, turn on SOF messages on the USB 2388 * BUS. Some USB devices do not cope without them! 2389 */ 2390 uhci_restart(sc); 2391 2392 x = URWMASK(UREAD2(sc, port)); 2393 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2394 2395 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2396 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 2397 2398 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n", 2399 index, UREAD2(sc, port)); 2400 2401 x = URWMASK(UREAD2(sc, port)); 2402 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2403 2404 2405 mtx_unlock(&sc->sc_bus.bus_mtx); 2406 2407 /* 2408 * This delay needs to be exactly 100us, else some USB devices 2409 * fail to attach! 2410 */ 2411 DELAY(100); 2412 2413 mtx_lock(&sc->sc_bus.bus_mtx); 2414 2415 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n", 2416 index, UREAD2(sc, port)); 2417 2418 x = URWMASK(UREAD2(sc, port)); 2419 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2420 2421 for (lim = 0; lim < 12; lim++) { 2422 2423 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2424 USB_MS_TO_TICKS(usb_port_reset_delay)); 2425 2426 x = UREAD2(sc, port); 2427 2428 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n", 2429 index, lim, x); 2430 2431 if (!(x & UHCI_PORTSC_CCS)) { 2432 /* 2433 * No device is connected (or was disconnected 2434 * during reset). Consider the port reset. 2435 * The delay must be long enough to ensure on 2436 * the initial iteration that the device 2437 * connection will have been registered. 50ms 2438 * appears to be sufficient, but 20ms is not. 2439 */ 2440 DPRINTFN(4, "uhci port %d loop %u, device detached\n", 2441 index, lim); 2442 goto done; 2443 } 2444 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 2445 /* 2446 * Port enabled changed and/or connection 2447 * status changed were set. Reset either or 2448 * both raised flags (by writing a 1 to that 2449 * bit), and wait again for state to settle. 2450 */ 2451 UWRITE2(sc, port, URWMASK(x) | 2452 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 2453 continue; 2454 } 2455 if (x & UHCI_PORTSC_PE) { 2456 /* port is enabled */ 2457 goto done; 2458 } 2459 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 2460 } 2461 2462 DPRINTFN(2, "uhci port %d reset timed out\n", index); 2463 return (USB_ERR_TIMEOUT); 2464 2465 done: 2466 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n", 2467 index, UREAD2(sc, port)); 2468 2469 sc->sc_isreset = 1; 2470 return (USB_ERR_NORMAL_COMPLETION); 2471 } 2472 2473 static usb_error_t 2474 uhci_roothub_exec(struct usb_device *udev, 2475 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2476 { 2477 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 2478 const void *ptr; 2479 const char *str_ptr; 2480 uint16_t x; 2481 uint16_t port; 2482 uint16_t value; 2483 uint16_t index; 2484 uint16_t status; 2485 uint16_t change; 2486 uint16_t len; 2487 usb_error_t err; 2488 2489 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2490 2491 /* buffer reset */ 2492 ptr = (const void *)&sc->sc_hub_desc.temp; 2493 len = 0; 2494 err = 0; 2495 2496 value = UGETW(req->wValue); 2497 index = UGETW(req->wIndex); 2498 2499 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2500 "wValue=0x%04x wIndex=0x%04x\n", 2501 req->bmRequestType, req->bRequest, 2502 UGETW(req->wLength), value, index); 2503 2504 #define C(x,y) ((x) | ((y) << 8)) 2505 switch (C(req->bRequest, req->bmRequestType)) { 2506 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2507 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2508 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2509 /* 2510 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2511 * for the integrated root hub. 2512 */ 2513 break; 2514 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2515 len = 1; 2516 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2517 break; 2518 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2519 switch (value >> 8) { 2520 case UDESC_DEVICE: 2521 if ((value & 0xff) != 0) { 2522 err = USB_ERR_IOERROR; 2523 goto done; 2524 } 2525 len = sizeof(uhci_devd); 2526 ptr = (const void *)&uhci_devd; 2527 break; 2528 2529 case UDESC_CONFIG: 2530 if ((value & 0xff) != 0) { 2531 err = USB_ERR_IOERROR; 2532 goto done; 2533 } 2534 len = sizeof(uhci_confd); 2535 ptr = (const void *)&uhci_confd; 2536 break; 2537 2538 case UDESC_STRING: 2539 switch (value & 0xff) { 2540 case 0: /* Language table */ 2541 str_ptr = "\001"; 2542 break; 2543 2544 case 1: /* Vendor */ 2545 str_ptr = sc->sc_vendor; 2546 break; 2547 2548 case 2: /* Product */ 2549 str_ptr = "UHCI root HUB"; 2550 break; 2551 2552 default: 2553 str_ptr = ""; 2554 break; 2555 } 2556 2557 len = usb_make_str_desc 2558 (sc->sc_hub_desc.temp, 2559 sizeof(sc->sc_hub_desc.temp), 2560 str_ptr); 2561 break; 2562 2563 default: 2564 err = USB_ERR_IOERROR; 2565 goto done; 2566 } 2567 break; 2568 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2569 len = 1; 2570 sc->sc_hub_desc.temp[0] = 0; 2571 break; 2572 case C(UR_GET_STATUS, UT_READ_DEVICE): 2573 len = 2; 2574 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2575 break; 2576 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2577 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2578 len = 2; 2579 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2580 break; 2581 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2582 if (value >= UHCI_MAX_DEVICES) { 2583 err = USB_ERR_IOERROR; 2584 goto done; 2585 } 2586 sc->sc_addr = value; 2587 break; 2588 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2589 if ((value != 0) && (value != 1)) { 2590 err = USB_ERR_IOERROR; 2591 goto done; 2592 } 2593 sc->sc_conf = value; 2594 break; 2595 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2596 break; 2597 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2598 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2599 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2600 err = USB_ERR_IOERROR; 2601 goto done; 2602 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2603 break; 2604 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2605 break; 2606 /* Hub requests */ 2607 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2608 break; 2609 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2610 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE " 2611 "port=%d feature=%d\n", 2612 index, value); 2613 if (index == 1) 2614 port = UHCI_PORTSC1; 2615 else if (index == 2) 2616 port = UHCI_PORTSC2; 2617 else { 2618 err = USB_ERR_IOERROR; 2619 goto done; 2620 } 2621 switch (value) { 2622 case UHF_PORT_ENABLE: 2623 x = URWMASK(UREAD2(sc, port)); 2624 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2625 break; 2626 case UHF_PORT_SUSPEND: 2627 x = URWMASK(UREAD2(sc, port)); 2628 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP)); 2629 break; 2630 case UHF_PORT_RESET: 2631 x = URWMASK(UREAD2(sc, port)); 2632 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2633 break; 2634 case UHF_C_PORT_CONNECTION: 2635 x = URWMASK(UREAD2(sc, port)); 2636 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2637 break; 2638 case UHF_C_PORT_ENABLE: 2639 x = URWMASK(UREAD2(sc, port)); 2640 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2641 break; 2642 case UHF_C_PORT_OVER_CURRENT: 2643 x = URWMASK(UREAD2(sc, port)); 2644 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2645 break; 2646 case UHF_C_PORT_RESET: 2647 sc->sc_isreset = 0; 2648 err = USB_ERR_NORMAL_COMPLETION; 2649 goto done; 2650 case UHF_C_PORT_SUSPEND: 2651 sc->sc_isresumed &= ~(1 << index); 2652 break; 2653 case UHF_PORT_CONNECTION: 2654 case UHF_PORT_OVER_CURRENT: 2655 case UHF_PORT_POWER: 2656 case UHF_PORT_LOW_SPEED: 2657 default: 2658 err = USB_ERR_IOERROR; 2659 goto done; 2660 } 2661 break; 2662 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2663 if (index == 1) 2664 port = UHCI_PORTSC1; 2665 else if (index == 2) 2666 port = UHCI_PORTSC2; 2667 else { 2668 err = USB_ERR_IOERROR; 2669 goto done; 2670 } 2671 len = 1; 2672 sc->sc_hub_desc.temp[0] = 2673 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2674 UHCI_PORTSC_LS_SHIFT); 2675 break; 2676 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2677 if ((value & 0xff) != 0) { 2678 err = USB_ERR_IOERROR; 2679 goto done; 2680 } 2681 len = sizeof(uhci_hubd_piix); 2682 ptr = (const void *)&uhci_hubd_piix; 2683 break; 2684 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2685 len = 16; 2686 memset(sc->sc_hub_desc.temp, 0, 16); 2687 break; 2688 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2689 if (index == 1) 2690 port = UHCI_PORTSC1; 2691 else if (index == 2) 2692 port = UHCI_PORTSC2; 2693 else { 2694 err = USB_ERR_IOERROR; 2695 goto done; 2696 } 2697 x = UREAD2(sc, port); 2698 status = change = 0; 2699 if (x & UHCI_PORTSC_CCS) 2700 status |= UPS_CURRENT_CONNECT_STATUS; 2701 if (x & UHCI_PORTSC_CSC) 2702 change |= UPS_C_CONNECT_STATUS; 2703 if (x & UHCI_PORTSC_PE) 2704 status |= UPS_PORT_ENABLED; 2705 if (x & UHCI_PORTSC_POEDC) 2706 change |= UPS_C_PORT_ENABLED; 2707 if (x & UHCI_PORTSC_OCI) 2708 status |= UPS_OVERCURRENT_INDICATOR; 2709 if (x & UHCI_PORTSC_OCIC) 2710 change |= UPS_C_OVERCURRENT_INDICATOR; 2711 if (x & UHCI_PORTSC_LSDA) 2712 status |= UPS_LOW_SPEED; 2713 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) { 2714 /* need to do a write back */ 2715 UWRITE2(sc, port, URWMASK(x)); 2716 2717 /* wait 20ms for resume sequence to complete */ 2718 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 2719 2720 /* clear suspend and resume detect */ 2721 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD | 2722 UHCI_PORTSC_SUSP)); 2723 2724 /* wait a little bit */ 2725 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500); 2726 2727 sc->sc_isresumed |= (1 << index); 2728 2729 } else if (x & UHCI_PORTSC_SUSP) { 2730 status |= UPS_SUSPEND; 2731 } 2732 status |= UPS_PORT_POWER; 2733 if (sc->sc_isresumed & (1 << index)) 2734 change |= UPS_C_SUSPEND; 2735 if (sc->sc_isreset) 2736 change |= UPS_C_PORT_RESET; 2737 USETW(sc->sc_hub_desc.ps.wPortStatus, status); 2738 USETW(sc->sc_hub_desc.ps.wPortChange, change); 2739 len = sizeof(sc->sc_hub_desc.ps); 2740 break; 2741 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2742 err = USB_ERR_IOERROR; 2743 goto done; 2744 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2745 break; 2746 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2747 if (index == 1) 2748 port = UHCI_PORTSC1; 2749 else if (index == 2) 2750 port = UHCI_PORTSC2; 2751 else { 2752 err = USB_ERR_IOERROR; 2753 goto done; 2754 } 2755 switch (value) { 2756 case UHF_PORT_ENABLE: 2757 x = URWMASK(UREAD2(sc, port)); 2758 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2759 break; 2760 case UHF_PORT_SUSPEND: 2761 x = URWMASK(UREAD2(sc, port)); 2762 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2763 break; 2764 case UHF_PORT_RESET: 2765 err = uhci_portreset(sc, index); 2766 goto done; 2767 case UHF_PORT_POWER: 2768 /* pretend we turned on power */ 2769 err = USB_ERR_NORMAL_COMPLETION; 2770 goto done; 2771 case UHF_C_PORT_CONNECTION: 2772 case UHF_C_PORT_ENABLE: 2773 case UHF_C_PORT_OVER_CURRENT: 2774 case UHF_PORT_CONNECTION: 2775 case UHF_PORT_OVER_CURRENT: 2776 case UHF_PORT_LOW_SPEED: 2777 case UHF_C_PORT_SUSPEND: 2778 case UHF_C_PORT_RESET: 2779 default: 2780 err = USB_ERR_IOERROR; 2781 goto done; 2782 } 2783 break; 2784 default: 2785 err = USB_ERR_IOERROR; 2786 goto done; 2787 } 2788 done: 2789 *plength = len; 2790 *pptr = ptr; 2791 return (err); 2792 } 2793 2794 /* 2795 * This routine is executed periodically and simulates interrupts from 2796 * the root controller interrupt pipe for port status change: 2797 */ 2798 static void 2799 uhci_root_intr(uhci_softc_t *sc) 2800 { 2801 DPRINTFN(21, "\n"); 2802 2803 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2804 2805 sc->sc_hub_idata[0] = 0; 2806 2807 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | 2808 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2809 sc->sc_hub_idata[0] |= 1 << 1; 2810 } 2811 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | 2812 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2813 sc->sc_hub_idata[0] |= 1 << 2; 2814 } 2815 2816 /* restart timer */ 2817 usb_callout_reset(&sc->sc_root_intr, hz, 2818 (void *)&uhci_root_intr, sc); 2819 2820 if (sc->sc_hub_idata[0] != 0) { 2821 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2822 sizeof(sc->sc_hub_idata)); 2823 } 2824 } 2825 2826 static void 2827 uhci_xfer_setup(struct usb_setup_params *parm) 2828 { 2829 struct usb_page_search page_info; 2830 struct usb_page_cache *pc; 2831 uhci_softc_t *sc; 2832 struct usb_xfer *xfer; 2833 void *last_obj; 2834 uint32_t ntd; 2835 uint32_t nqh; 2836 uint32_t nfixup; 2837 uint32_t n; 2838 uint16_t align; 2839 2840 sc = UHCI_BUS2SC(parm->udev->bus); 2841 xfer = parm->curr_xfer; 2842 2843 parm->hc_max_packet_size = 0x500; 2844 parm->hc_max_packet_count = 1; 2845 parm->hc_max_frame_size = 0x500; 2846 2847 /* 2848 * compute ntd and nqh 2849 */ 2850 if (parm->methods == &uhci_device_ctrl_methods) { 2851 xfer->flags_int.bdma_enable = 1; 2852 xfer->flags_int.bdma_no_post_sync = 1; 2853 2854 usbd_transfer_setup_sub(parm); 2855 2856 /* see EHCI HC driver for proof of "ntd" formula */ 2857 2858 nqh = 1; 2859 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2860 + (xfer->max_data_length / xfer->max_frame_size)); 2861 2862 } else if (parm->methods == &uhci_device_bulk_methods) { 2863 xfer->flags_int.bdma_enable = 1; 2864 xfer->flags_int.bdma_no_post_sync = 1; 2865 2866 usbd_transfer_setup_sub(parm); 2867 2868 nqh = 1; 2869 ntd = ((2 * xfer->nframes) 2870 + (xfer->max_data_length / xfer->max_frame_size)); 2871 2872 } else if (parm->methods == &uhci_device_intr_methods) { 2873 xfer->flags_int.bdma_enable = 1; 2874 xfer->flags_int.bdma_no_post_sync = 1; 2875 2876 usbd_transfer_setup_sub(parm); 2877 2878 nqh = 1; 2879 ntd = ((2 * xfer->nframes) 2880 + (xfer->max_data_length / xfer->max_frame_size)); 2881 2882 } else if (parm->methods == &uhci_device_isoc_methods) { 2883 xfer->flags_int.bdma_enable = 1; 2884 xfer->flags_int.bdma_no_post_sync = 1; 2885 2886 usbd_transfer_setup_sub(parm); 2887 2888 nqh = 0; 2889 ntd = xfer->nframes; 2890 2891 } else { 2892 2893 usbd_transfer_setup_sub(parm); 2894 2895 nqh = 0; 2896 ntd = 0; 2897 } 2898 2899 if (parm->err) { 2900 return; 2901 } 2902 /* 2903 * NOTE: the UHCI controller requires that 2904 * every packet must be contiguous on 2905 * the same USB memory page ! 2906 */ 2907 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1; 2908 2909 /* 2910 * Compute a suitable power of two alignment 2911 * for our "max_frame_size" fixup buffer(s): 2912 */ 2913 align = xfer->max_frame_size; 2914 n = 0; 2915 while (align) { 2916 align >>= 1; 2917 n++; 2918 } 2919 2920 /* check for power of two */ 2921 if (!(xfer->max_frame_size & 2922 (xfer->max_frame_size - 1))) { 2923 n--; 2924 } 2925 /* 2926 * We don't allow alignments of 2927 * less than 8 bytes: 2928 * 2929 * NOTE: Allocating using an aligment 2930 * of 1 byte has special meaning! 2931 */ 2932 if (n < 3) { 2933 n = 3; 2934 } 2935 align = (1 << n); 2936 2937 if (usbd_transfer_setup_sub_malloc( 2938 parm, &pc, xfer->max_frame_size, 2939 align, nfixup)) { 2940 parm->err = USB_ERR_NOMEM; 2941 return; 2942 } 2943 xfer->buf_fixup = pc; 2944 2945 alloc_dma_set: 2946 2947 if (parm->err) { 2948 return; 2949 } 2950 last_obj = NULL; 2951 2952 if (usbd_transfer_setup_sub_malloc( 2953 parm, &pc, sizeof(uhci_td_t), 2954 UHCI_TD_ALIGN, ntd)) { 2955 parm->err = USB_ERR_NOMEM; 2956 return; 2957 } 2958 if (parm->buf) { 2959 for (n = 0; n != ntd; n++) { 2960 uhci_td_t *td; 2961 2962 usbd_get_page(pc + n, 0, &page_info); 2963 2964 td = page_info.buffer; 2965 2966 /* init TD */ 2967 if ((parm->methods == &uhci_device_bulk_methods) || 2968 (parm->methods == &uhci_device_ctrl_methods) || 2969 (parm->methods == &uhci_device_intr_methods)) { 2970 /* set depth first bit */ 2971 td->td_self = htole32(page_info.physaddr | 2972 UHCI_PTR_TD | UHCI_PTR_VF); 2973 } else { 2974 td->td_self = htole32(page_info.physaddr | 2975 UHCI_PTR_TD); 2976 } 2977 2978 td->obj_next = last_obj; 2979 td->page_cache = pc + n; 2980 2981 last_obj = td; 2982 2983 usb_pc_cpu_flush(pc + n); 2984 } 2985 } 2986 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2987 2988 last_obj = NULL; 2989 2990 if (usbd_transfer_setup_sub_malloc( 2991 parm, &pc, sizeof(uhci_qh_t), 2992 UHCI_QH_ALIGN, nqh)) { 2993 parm->err = USB_ERR_NOMEM; 2994 return; 2995 } 2996 if (parm->buf) { 2997 for (n = 0; n != nqh; n++) { 2998 uhci_qh_t *qh; 2999 3000 usbd_get_page(pc + n, 0, &page_info); 3001 3002 qh = page_info.buffer; 3003 3004 /* init QH */ 3005 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH); 3006 qh->obj_next = last_obj; 3007 qh->page_cache = pc + n; 3008 3009 last_obj = qh; 3010 3011 usb_pc_cpu_flush(pc + n); 3012 } 3013 } 3014 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3015 3016 if (!xfer->flags_int.curr_dma_set) { 3017 xfer->flags_int.curr_dma_set = 1; 3018 goto alloc_dma_set; 3019 } 3020 } 3021 3022 static void 3023 uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3024 struct usb_endpoint *ep) 3025 { 3026 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 3027 3028 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3029 ep, udev->address, 3030 edesc->bEndpointAddress, udev->flags.usb_mode, 3031 sc->sc_addr); 3032 3033 if (udev->device_index != sc->sc_addr) { 3034 switch (edesc->bmAttributes & UE_XFERTYPE) { 3035 case UE_CONTROL: 3036 ep->methods = &uhci_device_ctrl_methods; 3037 break; 3038 case UE_INTERRUPT: 3039 ep->methods = &uhci_device_intr_methods; 3040 break; 3041 case UE_ISOCHRONOUS: 3042 if (udev->speed == USB_SPEED_FULL) { 3043 ep->methods = &uhci_device_isoc_methods; 3044 } 3045 break; 3046 case UE_BULK: 3047 ep->methods = &uhci_device_bulk_methods; 3048 break; 3049 default: 3050 /* do nothing */ 3051 break; 3052 } 3053 } 3054 } 3055 3056 static void 3057 uhci_xfer_unsetup(struct usb_xfer *xfer) 3058 { 3059 return; 3060 } 3061 3062 static void 3063 uhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3064 { 3065 /* 3066 * Wait until hardware has finished any possible use of the 3067 * transfer descriptor(s) and QH 3068 */ 3069 *pus = (1125); /* microseconds */ 3070 } 3071 3072 static void 3073 uhci_device_resume(struct usb_device *udev) 3074 { 3075 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3076 struct usb_xfer *xfer; 3077 struct usb_pipe_methods *methods; 3078 uhci_qh_t *qh; 3079 3080 DPRINTF("\n"); 3081 3082 USB_BUS_LOCK(udev->bus); 3083 3084 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3085 3086 if (xfer->xroot->udev == udev) { 3087 3088 methods = xfer->endpoint->methods; 3089 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3090 3091 if (methods == &uhci_device_bulk_methods) { 3092 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 3093 uhci_add_loop(sc); 3094 xfer->flags_int.bandwidth_reclaimed = 1; 3095 } 3096 if (methods == &uhci_device_ctrl_methods) { 3097 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3098 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 3099 } else { 3100 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 3101 } 3102 } 3103 if (methods == &uhci_device_intr_methods) { 3104 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3105 } 3106 } 3107 } 3108 3109 USB_BUS_UNLOCK(udev->bus); 3110 3111 return; 3112 } 3113 3114 static void 3115 uhci_device_suspend(struct usb_device *udev) 3116 { 3117 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3118 struct usb_xfer *xfer; 3119 struct usb_pipe_methods *methods; 3120 uhci_qh_t *qh; 3121 3122 DPRINTF("\n"); 3123 3124 USB_BUS_LOCK(udev->bus); 3125 3126 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3127 3128 if (xfer->xroot->udev == udev) { 3129 3130 methods = xfer->endpoint->methods; 3131 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3132 3133 if (xfer->flags_int.bandwidth_reclaimed) { 3134 xfer->flags_int.bandwidth_reclaimed = 0; 3135 uhci_rem_loop(sc); 3136 } 3137 if (methods == &uhci_device_bulk_methods) { 3138 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 3139 } 3140 if (methods == &uhci_device_ctrl_methods) { 3141 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3142 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 3143 } else { 3144 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 3145 } 3146 } 3147 if (methods == &uhci_device_intr_methods) { 3148 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3149 } 3150 } 3151 } 3152 3153 USB_BUS_UNLOCK(udev->bus); 3154 3155 return; 3156 } 3157 3158 static void 3159 uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3160 { 3161 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3162 3163 switch (state) { 3164 case USB_HW_POWER_SUSPEND: 3165 case USB_HW_POWER_SHUTDOWN: 3166 uhci_suspend(sc); 3167 break; 3168 case USB_HW_POWER_RESUME: 3169 uhci_resume(sc); 3170 break; 3171 default: 3172 break; 3173 } 3174 } 3175 3176 static void 3177 uhci_set_hw_power(struct usb_bus *bus) 3178 { 3179 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3180 uint32_t flags; 3181 3182 DPRINTF("\n"); 3183 3184 USB_BUS_LOCK(bus); 3185 3186 flags = bus->hw_power_state; 3187 3188 /* 3189 * WARNING: Some FULL speed USB devices require periodic SOF 3190 * messages! If any USB devices are connected through the 3191 * UHCI, power save will be disabled! 3192 */ 3193 if (flags & (USB_HW_POWER_CONTROL | 3194 USB_HW_POWER_NON_ROOT_HUB | 3195 USB_HW_POWER_BULK | 3196 USB_HW_POWER_INTERRUPT | 3197 USB_HW_POWER_ISOC)) { 3198 DPRINTF("Some USB transfer is " 3199 "active on unit %u.\n", 3200 device_get_unit(sc->sc_bus.bdev)); 3201 uhci_restart(sc); 3202 } else { 3203 DPRINTF("Power save on unit %u.\n", 3204 device_get_unit(sc->sc_bus.bdev)); 3205 UHCICMD(sc, UHCI_CMD_MAXP); 3206 } 3207 3208 USB_BUS_UNLOCK(bus); 3209 3210 return; 3211 } 3212 3213 3214 struct usb_bus_methods uhci_bus_methods = 3215 { 3216 .endpoint_init = uhci_ep_init, 3217 .xfer_setup = uhci_xfer_setup, 3218 .xfer_unsetup = uhci_xfer_unsetup, 3219 .get_dma_delay = uhci_get_dma_delay, 3220 .device_resume = uhci_device_resume, 3221 .device_suspend = uhci_device_suspend, 3222 .set_hw_power = uhci_set_hw_power, 3223 .set_hw_power_sleep = uhci_set_hw_power_sleep, 3224 .roothub_exec = uhci_roothub_exec, 3225 .xfer_poll = uhci_do_poll, 3226 }; 3227