1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * USB Universal Host Controller driver. 33 * Handles e.g. PIIX3 and PIIX4. 34 * 35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 38 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 39 */ 40 41 #include <sys/stdint.h> 42 #include <sys/stddef.h> 43 #include <sys/param.h> 44 #include <sys/queue.h> 45 #include <sys/types.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/bus.h> 49 #include <sys/linker_set.h> 50 #include <sys/module.h> 51 #include <sys/lock.h> 52 #include <sys/mutex.h> 53 #include <sys/condvar.h> 54 #include <sys/sysctl.h> 55 #include <sys/sx.h> 56 #include <sys/unistd.h> 57 #include <sys/callout.h> 58 #include <sys/malloc.h> 59 #include <sys/priv.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 64 #define USB_DEBUG_VAR uhcidebug 65 66 #include <dev/usb/usb_core.h> 67 #include <dev/usb/usb_debug.h> 68 #include <dev/usb/usb_busdma.h> 69 #include <dev/usb/usb_process.h> 70 #include <dev/usb/usb_transfer.h> 71 #include <dev/usb/usb_device.h> 72 #include <dev/usb/usb_hub.h> 73 #include <dev/usb/usb_util.h> 74 75 #include <dev/usb/usb_controller.h> 76 #include <dev/usb/usb_bus.h> 77 #include <dev/usb/controller/uhci.h> 78 79 #define alt_next next 80 #define UHCI_BUS2SC(bus) \ 81 ((uhci_softc_t *)(((uint8_t *)(bus)) - \ 82 ((uint8_t *)&(((uhci_softc_t *)0)->sc_bus)))) 83 84 #if USB_DEBUG 85 static int uhcidebug = 0; 86 static int uhcinoloop = 0; 87 88 SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW, 0, "USB uhci"); 89 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RW, 90 &uhcidebug, 0, "uhci debug level"); 91 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RW, 92 &uhcinoloop, 0, "uhci noloop"); 93 static void uhci_dumpregs(uhci_softc_t *sc); 94 static void uhci_dump_tds(uhci_td_t *td); 95 96 #endif 97 98 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 99 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 100 #define UWRITE1(sc, r, x) \ 101 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 102 } while (/*CONSTCOND*/0) 103 #define UWRITE2(sc, r, x) \ 104 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 105 } while (/*CONSTCOND*/0) 106 #define UWRITE4(sc, r, x) \ 107 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 108 } while (/*CONSTCOND*/0) 109 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 110 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 111 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 112 113 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 114 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 115 116 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 117 118 #define UHCI_INTR_ENDPT 1 119 120 struct uhci_mem_layout { 121 122 struct usb_page_search buf_res; 123 struct usb_page_search fix_res; 124 125 struct usb_page_cache *buf_pc; 126 struct usb_page_cache *fix_pc; 127 128 uint32_t buf_offset; 129 130 uint16_t max_frame_size; 131 }; 132 133 struct uhci_std_temp { 134 135 struct uhci_mem_layout ml; 136 uhci_td_t *td; 137 uhci_td_t *td_next; 138 uint32_t average; 139 uint32_t td_status; 140 uint32_t td_token; 141 uint32_t len; 142 uint16_t max_frame_size; 143 uint8_t shortpkt; 144 uint8_t setup_alt_next; 145 uint8_t last_frame; 146 }; 147 148 extern struct usb_bus_methods uhci_bus_methods; 149 extern struct usb_pipe_methods uhci_device_bulk_methods; 150 extern struct usb_pipe_methods uhci_device_ctrl_methods; 151 extern struct usb_pipe_methods uhci_device_intr_methods; 152 extern struct usb_pipe_methods uhci_device_isoc_methods; 153 154 static uint8_t uhci_restart(uhci_softc_t *sc); 155 static void uhci_do_poll(struct usb_bus *); 156 static void uhci_device_done(struct usb_xfer *, usb_error_t); 157 static void uhci_transfer_intr_enqueue(struct usb_xfer *); 158 static void uhci_timeout(void *); 159 static uint8_t uhci_check_transfer(struct usb_xfer *); 160 static void uhci_root_intr(uhci_softc_t *sc); 161 162 void 163 uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 164 { 165 struct uhci_softc *sc = UHCI_BUS2SC(bus); 166 uint32_t i; 167 168 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 169 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN); 170 171 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg, 172 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 173 174 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg, 175 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 176 177 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 178 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 179 180 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg, 181 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 182 183 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg, 184 sizeof(uhci_td_t), UHCI_TD_ALIGN); 185 186 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) { 187 cb(bus, sc->sc_hw.isoc_start_pc + i, 188 sc->sc_hw.isoc_start_pg + i, 189 sizeof(uhci_td_t), UHCI_TD_ALIGN); 190 } 191 192 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) { 193 cb(bus, sc->sc_hw.intr_start_pc + i, 194 sc->sc_hw.intr_start_pg + i, 195 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 196 } 197 } 198 199 static void 200 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer) 201 { 202 ml->buf_pc = xfer->frbuffers + 0; 203 ml->fix_pc = xfer->buf_fixup; 204 205 ml->buf_offset = 0; 206 207 ml->max_frame_size = xfer->max_frame_size; 208 } 209 210 static void 211 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td) 212 { 213 usbd_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res); 214 215 if (ml->buf_res.length < td->len) { 216 217 /* need to do a fixup */ 218 219 usbd_get_page(ml->fix_pc, 0, &ml->fix_res); 220 221 td->td_buffer = htole32(ml->fix_res.physaddr); 222 223 /* 224 * The UHCI driver cannot handle 225 * page crossings, so a fixup is 226 * needed: 227 * 228 * +----+----+ - - - 229 * | YYY|Y | 230 * +----+----+ - - - 231 * \ \ 232 * \ \ 233 * +----+ 234 * |YYYY| (fixup) 235 * +----+ 236 */ 237 238 if ((td->td_token & htole32(UHCI_TD_PID)) == 239 htole32(UHCI_TD_PID_IN)) { 240 td->fix_pc = ml->fix_pc; 241 usb_pc_cpu_invalidate(ml->fix_pc); 242 243 } else { 244 td->fix_pc = NULL; 245 246 /* copy data to fixup location */ 247 248 usbd_copy_out(ml->buf_pc, ml->buf_offset, 249 ml->fix_res.buffer, td->len); 250 251 usb_pc_cpu_flush(ml->fix_pc); 252 } 253 254 /* prepare next fixup */ 255 256 ml->fix_pc++; 257 258 } else { 259 260 td->td_buffer = htole32(ml->buf_res.physaddr); 261 td->fix_pc = NULL; 262 } 263 264 /* prepare next data location */ 265 266 ml->buf_offset += td->len; 267 } 268 269 /* 270 * Return values: 271 * 0: Success 272 * Else: Failure 273 */ 274 static uint8_t 275 uhci_restart(uhci_softc_t *sc) 276 { 277 struct usb_page_search buf_res; 278 279 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 280 281 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) { 282 DPRINTFN(2, "Already started\n"); 283 return (0); 284 } 285 286 DPRINTFN(2, "Restarting\n"); 287 288 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 289 290 /* Reload fresh base address */ 291 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr); 292 293 /* 294 * Assume 64 byte packets at frame end and start HC controller: 295 */ 296 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 297 298 /* wait 10 milliseconds */ 299 300 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 301 302 /* check that controller has started */ 303 304 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 305 DPRINTFN(2, "Failed\n"); 306 return (1); 307 } 308 return (0); 309 } 310 311 void 312 uhci_reset(uhci_softc_t *sc) 313 { 314 uint16_t n; 315 316 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 317 318 DPRINTF("resetting the HC\n"); 319 320 /* disable interrupts */ 321 322 UWRITE2(sc, UHCI_INTR, 0); 323 324 /* global reset */ 325 326 UHCICMD(sc, UHCI_CMD_GRESET); 327 328 /* wait */ 329 330 usb_pause_mtx(&sc->sc_bus.bus_mtx, 331 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 332 333 /* terminate all transfers */ 334 335 UHCICMD(sc, UHCI_CMD_HCRESET); 336 337 /* the reset bit goes low when the controller is done */ 338 339 n = UHCI_RESET_TIMEOUT; 340 while (n--) { 341 /* wait one millisecond */ 342 343 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 344 345 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) { 346 goto done_1; 347 } 348 } 349 350 device_printf(sc->sc_bus.bdev, 351 "controller did not reset\n"); 352 353 done_1: 354 355 n = 10; 356 while (n--) { 357 /* wait one millisecond */ 358 359 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 360 361 /* check if HC is stopped */ 362 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 363 goto done_2; 364 } 365 } 366 367 device_printf(sc->sc_bus.bdev, 368 "controller did not stop\n"); 369 370 done_2: 371 372 /* reload the configuration */ 373 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 374 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 375 376 USB_BUS_UNLOCK(&sc->sc_bus); 377 378 /* stop root interrupt */ 379 usb_callout_drain(&sc->sc_root_intr); 380 381 USB_BUS_LOCK(&sc->sc_bus); 382 } 383 384 static void 385 uhci_start(uhci_softc_t *sc) 386 { 387 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 388 389 DPRINTFN(2, "enabling\n"); 390 391 /* enable interrupts */ 392 393 UWRITE2(sc, UHCI_INTR, 394 (UHCI_INTR_TOCRCIE | 395 UHCI_INTR_RIE | 396 UHCI_INTR_IOCE | 397 UHCI_INTR_SPIE)); 398 399 if (uhci_restart(sc)) { 400 device_printf(sc->sc_bus.bdev, 401 "cannot start HC controller\n"); 402 } 403 404 /* start root interrupt */ 405 uhci_root_intr(sc); 406 } 407 408 static struct uhci_qh * 409 uhci_init_qh(struct usb_page_cache *pc) 410 { 411 struct usb_page_search buf_res; 412 struct uhci_qh *qh; 413 414 usbd_get_page(pc, 0, &buf_res); 415 416 qh = buf_res.buffer; 417 418 qh->qh_self = 419 htole32(buf_res.physaddr) | 420 htole32(UHCI_PTR_QH); 421 422 qh->page_cache = pc; 423 424 return (qh); 425 } 426 427 static struct uhci_td * 428 uhci_init_td(struct usb_page_cache *pc) 429 { 430 struct usb_page_search buf_res; 431 struct uhci_td *td; 432 433 usbd_get_page(pc, 0, &buf_res); 434 435 td = buf_res.buffer; 436 437 td->td_self = 438 htole32(buf_res.physaddr) | 439 htole32(UHCI_PTR_TD); 440 441 td->page_cache = pc; 442 443 return (td); 444 } 445 446 usb_error_t 447 uhci_init(uhci_softc_t *sc) 448 { 449 uint16_t bit; 450 uint16_t x; 451 uint16_t y; 452 453 DPRINTF("start\n"); 454 455 usb_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_mtx, 0); 456 457 #if USB_DEBUG 458 if (uhcidebug > 2) { 459 uhci_dumpregs(sc); 460 } 461 #endif 462 sc->sc_saved_sof = 0x40; /* default value */ 463 sc->sc_saved_frnum = 0; /* default frame number */ 464 465 /* 466 * Setup QH's 467 */ 468 sc->sc_ls_ctl_p_last = 469 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc); 470 471 sc->sc_fs_ctl_p_last = 472 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc); 473 474 sc->sc_bulk_p_last = 475 uhci_init_qh(&sc->sc_hw.bulk_start_pc); 476 #if 0 477 sc->sc_reclaim_qh_p = 478 sc->sc_fs_ctl_p_last; 479 #else 480 /* setup reclaim looping point */ 481 sc->sc_reclaim_qh_p = 482 sc->sc_bulk_p_last; 483 #endif 484 485 sc->sc_last_qh_p = 486 uhci_init_qh(&sc->sc_hw.last_qh_pc); 487 488 sc->sc_last_td_p = 489 uhci_init_td(&sc->sc_hw.last_td_pc); 490 491 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 492 sc->sc_isoc_p_last[x] = 493 uhci_init_td(sc->sc_hw.isoc_start_pc + x); 494 } 495 496 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) { 497 sc->sc_intr_p_last[x] = 498 uhci_init_qh(sc->sc_hw.intr_start_pc + x); 499 } 500 501 /* 502 * the QHs are arranged to give poll intervals that are 503 * powers of 2 times 1ms 504 */ 505 bit = UHCI_IFRAMELIST_COUNT / 2; 506 while (bit) { 507 x = bit; 508 while (x & bit) { 509 uhci_qh_t *qh_x; 510 uhci_qh_t *qh_y; 511 512 y = (x ^ bit) | (bit / 2); 513 514 /* 515 * the next QH has half the poll interval 516 */ 517 qh_x = sc->sc_intr_p_last[x]; 518 qh_y = sc->sc_intr_p_last[y]; 519 520 qh_x->h_next = NULL; 521 qh_x->qh_h_next = qh_y->qh_self; 522 qh_x->e_next = NULL; 523 qh_x->qh_e_next = htole32(UHCI_PTR_T); 524 x++; 525 } 526 bit >>= 1; 527 } 528 529 if (1) { 530 uhci_qh_t *qh_ls; 531 uhci_qh_t *qh_intr; 532 533 qh_ls = sc->sc_ls_ctl_p_last; 534 qh_intr = sc->sc_intr_p_last[0]; 535 536 /* start QH for interrupt traffic */ 537 qh_intr->h_next = qh_ls; 538 qh_intr->qh_h_next = qh_ls->qh_self; 539 qh_intr->e_next = 0; 540 qh_intr->qh_e_next = htole32(UHCI_PTR_T); 541 } 542 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 543 544 uhci_td_t *td_x; 545 uhci_qh_t *qh_intr; 546 547 td_x = sc->sc_isoc_p_last[x]; 548 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)]; 549 550 /* start TD for isochronous traffic */ 551 td_x->next = NULL; 552 td_x->td_next = qh_intr->qh_self; 553 td_x->td_status = htole32(UHCI_TD_IOS); 554 td_x->td_token = htole32(0); 555 td_x->td_buffer = htole32(0); 556 } 557 558 if (1) { 559 uhci_qh_t *qh_ls; 560 uhci_qh_t *qh_fs; 561 562 qh_ls = sc->sc_ls_ctl_p_last; 563 qh_fs = sc->sc_fs_ctl_p_last; 564 565 /* start QH where low speed control traffic will be queued */ 566 qh_ls->h_next = qh_fs; 567 qh_ls->qh_h_next = qh_fs->qh_self; 568 qh_ls->e_next = 0; 569 qh_ls->qh_e_next = htole32(UHCI_PTR_T); 570 } 571 if (1) { 572 uhci_qh_t *qh_ctl; 573 uhci_qh_t *qh_blk; 574 uhci_qh_t *qh_lst; 575 uhci_td_t *td_lst; 576 577 qh_ctl = sc->sc_fs_ctl_p_last; 578 qh_blk = sc->sc_bulk_p_last; 579 580 /* start QH where full speed control traffic will be queued */ 581 qh_ctl->h_next = qh_blk; 582 qh_ctl->qh_h_next = qh_blk->qh_self; 583 qh_ctl->e_next = 0; 584 qh_ctl->qh_e_next = htole32(UHCI_PTR_T); 585 586 qh_lst = sc->sc_last_qh_p; 587 588 /* start QH where bulk traffic will be queued */ 589 qh_blk->h_next = qh_lst; 590 qh_blk->qh_h_next = qh_lst->qh_self; 591 qh_blk->e_next = 0; 592 qh_blk->qh_e_next = htole32(UHCI_PTR_T); 593 594 td_lst = sc->sc_last_td_p; 595 596 /* end QH which is used for looping the QHs */ 597 qh_lst->h_next = 0; 598 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */ 599 qh_lst->e_next = td_lst; 600 qh_lst->qh_e_next = td_lst->td_self; 601 602 /* 603 * end TD which hangs from the last QH, to avoid a bug in the PIIX 604 * that makes it run berserk otherwise 605 */ 606 td_lst->next = 0; 607 td_lst->td_next = htole32(UHCI_PTR_T); 608 td_lst->td_status = htole32(0); /* inactive */ 609 td_lst->td_token = htole32(0); 610 td_lst->td_buffer = htole32(0); 611 } 612 if (1) { 613 struct usb_page_search buf_res; 614 uint32_t *pframes; 615 616 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 617 618 pframes = buf_res.buffer; 619 620 621 /* 622 * Setup UHCI framelist 623 * 624 * Execution order: 625 * 626 * pframes -> full speed isochronous -> interrupt QH's -> low 627 * speed control -> full speed control -> bulk transfers 628 * 629 */ 630 631 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) { 632 pframes[x] = 633 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self; 634 } 635 } 636 /* flush all cache into memory */ 637 638 usb_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc); 639 640 /* set up the bus struct */ 641 sc->sc_bus.methods = &uhci_bus_methods; 642 643 USB_BUS_LOCK(&sc->sc_bus); 644 /* reset the controller */ 645 uhci_reset(sc); 646 647 /* start the controller */ 648 uhci_start(sc); 649 USB_BUS_UNLOCK(&sc->sc_bus); 650 651 /* catch lost interrupts */ 652 uhci_do_poll(&sc->sc_bus); 653 654 return (0); 655 } 656 657 /* NOTE: suspend/resume is called from 658 * interrupt context and cannot sleep! 659 */ 660 661 void 662 uhci_suspend(uhci_softc_t *sc) 663 { 664 USB_BUS_LOCK(&sc->sc_bus); 665 666 #if USB_DEBUG 667 if (uhcidebug > 2) { 668 uhci_dumpregs(sc); 669 } 670 #endif 671 /* save some state if BIOS doesn't */ 672 673 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 674 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 675 676 /* stop the controller */ 677 678 uhci_reset(sc); 679 680 /* enter global suspend */ 681 682 UHCICMD(sc, UHCI_CMD_EGSM); 683 684 usb_pause_mtx(&sc->sc_bus.bus_mtx, 685 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 686 687 USB_BUS_UNLOCK(&sc->sc_bus); 688 } 689 690 void 691 uhci_resume(uhci_softc_t *sc) 692 { 693 USB_BUS_LOCK(&sc->sc_bus); 694 695 /* reset the controller */ 696 697 uhci_reset(sc); 698 699 /* force global resume */ 700 701 UHCICMD(sc, UHCI_CMD_FGR); 702 703 usb_pause_mtx(&sc->sc_bus.bus_mtx, 704 USB_MS_TO_TICKS(USB_RESUME_DELAY)); 705 706 /* and start traffic again */ 707 708 uhci_start(sc); 709 710 #if USB_DEBUG 711 if (uhcidebug > 2) { 712 uhci_dumpregs(sc); 713 } 714 #endif 715 716 USB_BUS_UNLOCK(&sc->sc_bus); 717 718 /* catch lost interrupts */ 719 uhci_do_poll(&sc->sc_bus); 720 } 721 722 #if USB_DEBUG 723 static void 724 uhci_dumpregs(uhci_softc_t *sc) 725 { 726 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 727 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 728 device_get_nameunit(sc->sc_bus.bdev), 729 UREAD2(sc, UHCI_CMD), 730 UREAD2(sc, UHCI_STS), 731 UREAD2(sc, UHCI_INTR), 732 UREAD2(sc, UHCI_FRNUM), 733 UREAD4(sc, UHCI_FLBASEADDR), 734 UREAD1(sc, UHCI_SOF), 735 UREAD2(sc, UHCI_PORTSC1), 736 UREAD2(sc, UHCI_PORTSC2)); 737 } 738 739 static uint8_t 740 uhci_dump_td(uhci_td_t *p) 741 { 742 uint32_t td_next; 743 uint32_t td_status; 744 uint32_t td_token; 745 uint8_t temp; 746 747 usb_pc_cpu_invalidate(p->page_cache); 748 749 td_next = le32toh(p->td_next); 750 td_status = le32toh(p->td_status); 751 td_token = le32toh(p->td_token); 752 753 /* 754 * Check whether the link pointer in this TD marks the link pointer 755 * as end of queue: 756 */ 757 temp = ((td_next & UHCI_PTR_T) || (td_next == 0)); 758 759 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x " 760 "token=0x%08x buffer=0x%08x\n", 761 p, 762 le32toh(p->td_self), 763 td_next, 764 td_status, 765 td_token, 766 le32toh(p->td_buffer)); 767 768 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x," 769 "addr=%d,endpt=%d,D=%d,maxlen=%d\n", 770 p, 771 (td_next & 1) ? "-T" : "", 772 (td_next & 2) ? "-Q" : "", 773 (td_next & 4) ? "-VF" : "", 774 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "", 775 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "", 776 (td_status & UHCI_TD_NAK) ? "-NAK" : "", 777 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "", 778 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "", 779 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "", 780 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "", 781 (td_status & UHCI_TD_IOC) ? "-IOC" : "", 782 (td_status & UHCI_TD_IOS) ? "-IOS" : "", 783 (td_status & UHCI_TD_LS) ? "-LS" : "", 784 (td_status & UHCI_TD_SPD) ? "-SPD" : "", 785 UHCI_TD_GET_ERRCNT(td_status), 786 UHCI_TD_GET_ACTLEN(td_status), 787 UHCI_TD_GET_PID(td_token), 788 UHCI_TD_GET_DEVADDR(td_token), 789 UHCI_TD_GET_ENDPT(td_token), 790 UHCI_TD_GET_DT(td_token), 791 UHCI_TD_GET_MAXLEN(td_token)); 792 793 return (temp); 794 } 795 796 static uint8_t 797 uhci_dump_qh(uhci_qh_t *sqh) 798 { 799 uint8_t temp; 800 uint32_t qh_h_next; 801 uint32_t qh_e_next; 802 803 usb_pc_cpu_invalidate(sqh->page_cache); 804 805 qh_h_next = le32toh(sqh->qh_h_next); 806 qh_e_next = le32toh(sqh->qh_e_next); 807 808 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh, 809 le32toh(sqh->qh_self), qh_h_next, qh_e_next); 810 811 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) | 812 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0)); 813 814 return (temp); 815 } 816 817 static void 818 uhci_dump_all(uhci_softc_t *sc) 819 { 820 uhci_dumpregs(sc); 821 uhci_dump_qh(sc->sc_ls_ctl_p_last); 822 uhci_dump_qh(sc->sc_fs_ctl_p_last); 823 uhci_dump_qh(sc->sc_bulk_p_last); 824 uhci_dump_qh(sc->sc_last_qh_p); 825 } 826 827 static void 828 uhci_dump_qhs(uhci_qh_t *sqh) 829 { 830 uint8_t temp; 831 832 temp = uhci_dump_qh(sqh); 833 834 /* 835 * uhci_dump_qhs displays all the QHs and TDs from the given QH 836 * onwards Traverses sideways first, then down. 837 * 838 * QH1 QH2 No QH TD2.1 TD2.2 TD1.1 etc. 839 * 840 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 841 */ 842 843 if (temp & 1) 844 uhci_dump_qhs(sqh->h_next); 845 else 846 DPRINTF("No QH\n"); 847 848 if (temp & 2) 849 uhci_dump_tds(sqh->e_next); 850 else 851 DPRINTF("No TD\n"); 852 } 853 854 static void 855 uhci_dump_tds(uhci_td_t *td) 856 { 857 for (; 858 td != NULL; 859 td = td->obj_next) { 860 if (uhci_dump_td(td)) { 861 break; 862 } 863 } 864 } 865 866 #endif 867 868 /* 869 * Let the last QH loop back to the full speed control transfer QH. 870 * This is what intel calls "bandwidth reclamation" and improves 871 * USB performance a lot for some devices. 872 * If we are already looping, just count it. 873 */ 874 static void 875 uhci_add_loop(uhci_softc_t *sc) 876 { 877 struct uhci_qh *qh_lst; 878 struct uhci_qh *qh_rec; 879 880 #if USB_DEBUG 881 if (uhcinoloop) { 882 return; 883 } 884 #endif 885 if (++(sc->sc_loops) == 1) { 886 DPRINTFN(6, "add\n"); 887 888 qh_lst = sc->sc_last_qh_p; 889 qh_rec = sc->sc_reclaim_qh_p; 890 891 /* NOTE: we don't loop back the soft pointer */ 892 893 qh_lst->qh_h_next = qh_rec->qh_self; 894 usb_pc_cpu_flush(qh_lst->page_cache); 895 } 896 } 897 898 static void 899 uhci_rem_loop(uhci_softc_t *sc) 900 { 901 struct uhci_qh *qh_lst; 902 903 #if USB_DEBUG 904 if (uhcinoloop) { 905 return; 906 } 907 #endif 908 if (--(sc->sc_loops) == 0) { 909 DPRINTFN(6, "remove\n"); 910 911 qh_lst = sc->sc_last_qh_p; 912 qh_lst->qh_h_next = htole32(UHCI_PTR_T); 913 usb_pc_cpu_flush(qh_lst->page_cache); 914 } 915 } 916 917 static void 918 uhci_transfer_intr_enqueue(struct usb_xfer *xfer) 919 { 920 /* check for early completion */ 921 if (uhci_check_transfer(xfer)) { 922 return; 923 } 924 /* put transfer on interrupt queue */ 925 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 926 927 /* start timeout, if any */ 928 if (xfer->timeout != 0) { 929 usbd_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout); 930 } 931 } 932 933 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last) 934 static uhci_td_t * 935 _uhci_append_td(uhci_td_t *std, uhci_td_t *last) 936 { 937 DPRINTFN(11, "%p to %p\n", std, last); 938 939 /* (sc->sc_bus.mtx) must be locked */ 940 941 std->next = last->next; 942 std->td_next = last->td_next; 943 944 std->prev = last; 945 946 usb_pc_cpu_flush(std->page_cache); 947 948 /* 949 * the last->next->prev is never followed: std->next->prev = std; 950 */ 951 last->next = std; 952 last->td_next = std->td_self; 953 954 usb_pc_cpu_flush(last->page_cache); 955 956 return (std); 957 } 958 959 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last) 960 static uhci_qh_t * 961 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last) 962 { 963 DPRINTFN(11, "%p to %p\n", sqh, last); 964 965 if (sqh->h_prev != NULL) { 966 /* should not happen */ 967 DPRINTFN(0, "QH already linked!\n"); 968 return (last); 969 } 970 /* (sc->sc_bus.mtx) must be locked */ 971 972 sqh->h_next = last->h_next; 973 sqh->qh_h_next = last->qh_h_next; 974 975 sqh->h_prev = last; 976 977 usb_pc_cpu_flush(sqh->page_cache); 978 979 /* 980 * The "last->h_next->h_prev" is never followed: 981 * 982 * "sqh->h_next->h_prev" = sqh; 983 */ 984 985 last->h_next = sqh; 986 last->qh_h_next = sqh->qh_self; 987 988 usb_pc_cpu_flush(last->page_cache); 989 990 return (sqh); 991 } 992 993 /**/ 994 995 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last) 996 static uhci_td_t * 997 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last) 998 { 999 DPRINTFN(11, "%p from %p\n", std, last); 1000 1001 /* (sc->sc_bus.mtx) must be locked */ 1002 1003 std->prev->next = std->next; 1004 std->prev->td_next = std->td_next; 1005 1006 usb_pc_cpu_flush(std->prev->page_cache); 1007 1008 if (std->next) { 1009 std->next->prev = std->prev; 1010 usb_pc_cpu_flush(std->next->page_cache); 1011 } 1012 return ((last == std) ? std->prev : last); 1013 } 1014 1015 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last) 1016 static uhci_qh_t * 1017 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last) 1018 { 1019 DPRINTFN(11, "%p from %p\n", sqh, last); 1020 1021 /* (sc->sc_bus.mtx) must be locked */ 1022 1023 /* only remove if not removed from a queue */ 1024 if (sqh->h_prev) { 1025 1026 sqh->h_prev->h_next = sqh->h_next; 1027 sqh->h_prev->qh_h_next = sqh->qh_h_next; 1028 1029 usb_pc_cpu_flush(sqh->h_prev->page_cache); 1030 1031 if (sqh->h_next) { 1032 sqh->h_next->h_prev = sqh->h_prev; 1033 usb_pc_cpu_flush(sqh->h_next->page_cache); 1034 } 1035 last = ((last == sqh) ? sqh->h_prev : last); 1036 1037 sqh->h_prev = 0; 1038 1039 usb_pc_cpu_flush(sqh->page_cache); 1040 } 1041 return (last); 1042 } 1043 1044 static void 1045 uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer) 1046 { 1047 struct usb_page_search res; 1048 uint32_t nframes = xfer->nframes; 1049 uint32_t status; 1050 uint32_t offset = 0; 1051 uint32_t *plen = xfer->frlengths; 1052 uint16_t len = 0; 1053 uhci_td_t *td = xfer->td_transfer_first; 1054 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos]; 1055 1056 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1057 xfer, xfer->endpoint); 1058 1059 /* sync any DMA memory before doing fixups */ 1060 1061 usb_bdma_post_sync(xfer); 1062 1063 while (nframes--) { 1064 if (td == NULL) { 1065 panic("%s:%d: out of TD's\n", 1066 __FUNCTION__, __LINE__); 1067 } 1068 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 1069 pp_last = &sc->sc_isoc_p_last[0]; 1070 } 1071 #if USB_DEBUG 1072 if (uhcidebug > 5) { 1073 DPRINTF("isoc TD\n"); 1074 uhci_dump_td(td); 1075 } 1076 #endif 1077 usb_pc_cpu_invalidate(td->page_cache); 1078 status = le32toh(td->td_status); 1079 1080 len = UHCI_TD_GET_ACTLEN(status); 1081 1082 if (len > *plen) { 1083 len = *plen; 1084 } 1085 if (td->fix_pc) { 1086 1087 usbd_get_page(td->fix_pc, 0, &res); 1088 1089 /* copy data from fixup location to real location */ 1090 1091 usb_pc_cpu_invalidate(td->fix_pc); 1092 1093 usbd_copy_in(xfer->frbuffers, offset, 1094 res.buffer, len); 1095 } 1096 offset += *plen; 1097 1098 *plen = len; 1099 1100 /* remove TD from schedule */ 1101 UHCI_REMOVE_TD(td, *pp_last); 1102 1103 pp_last++; 1104 plen++; 1105 td = td->obj_next; 1106 } 1107 1108 xfer->aframes = xfer->nframes; 1109 } 1110 1111 static usb_error_t 1112 uhci_non_isoc_done_sub(struct usb_xfer *xfer) 1113 { 1114 struct usb_page_search res; 1115 uhci_td_t *td; 1116 uhci_td_t *td_alt_next; 1117 uint32_t status; 1118 uint32_t token; 1119 uint16_t len; 1120 1121 td = xfer->td_transfer_cache; 1122 td_alt_next = td->alt_next; 1123 1124 if (xfer->aframes != xfer->nframes) { 1125 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1126 } 1127 while (1) { 1128 1129 usb_pc_cpu_invalidate(td->page_cache); 1130 status = le32toh(td->td_status); 1131 token = le32toh(td->td_token); 1132 1133 /* 1134 * Verify the status and add 1135 * up the actual length: 1136 */ 1137 1138 len = UHCI_TD_GET_ACTLEN(status); 1139 if (len > td->len) { 1140 /* should not happen */ 1141 DPRINTF("Invalid status length, " 1142 "0x%04x/0x%04x bytes\n", len, td->len); 1143 status |= UHCI_TD_STALLED; 1144 1145 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) { 1146 1147 if (td->fix_pc) { 1148 1149 usbd_get_page(td->fix_pc, 0, &res); 1150 1151 /* 1152 * copy data from fixup location to real 1153 * location 1154 */ 1155 1156 usb_pc_cpu_invalidate(td->fix_pc); 1157 1158 usbd_copy_in(xfer->frbuffers + xfer->aframes, 1159 xfer->frlengths[xfer->aframes], res.buffer, len); 1160 } 1161 /* update actual length */ 1162 1163 xfer->frlengths[xfer->aframes] += len; 1164 } 1165 /* Check for last transfer */ 1166 if (((void *)td) == xfer->td_transfer_last) { 1167 td = NULL; 1168 break; 1169 } 1170 if (status & UHCI_TD_STALLED) { 1171 /* the transfer is finished */ 1172 td = NULL; 1173 break; 1174 } 1175 /* Check for short transfer */ 1176 if (len != td->len) { 1177 if (xfer->flags_int.short_frames_ok) { 1178 /* follow alt next */ 1179 td = td->alt_next; 1180 } else { 1181 /* the transfer is finished */ 1182 td = NULL; 1183 } 1184 break; 1185 } 1186 td = td->obj_next; 1187 1188 if (td->alt_next != td_alt_next) { 1189 /* this USB frame is complete */ 1190 break; 1191 } 1192 } 1193 1194 /* update transfer cache */ 1195 1196 xfer->td_transfer_cache = td; 1197 1198 /* update data toggle */ 1199 1200 xfer->endpoint->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1; 1201 1202 #if USB_DEBUG 1203 if (status & UHCI_TD_ERROR) { 1204 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x " 1205 "status=%s%s%s%s%s%s%s%s%s%s%s\n", 1206 xfer->address, xfer->endpointno, xfer->aframes, 1207 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "", 1208 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "", 1209 (status & UHCI_TD_NAK) ? "[NAK]" : "", 1210 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "", 1211 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "", 1212 (status & UHCI_TD_STALLED) ? "[STALLED]" : "", 1213 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1214 (status & UHCI_TD_IOC) ? "[IOC]" : "", 1215 (status & UHCI_TD_IOS) ? "[IOS]" : "", 1216 (status & UHCI_TD_LS) ? "[LS]" : "", 1217 (status & UHCI_TD_SPD) ? "[SPD]" : ""); 1218 } 1219 #endif 1220 return (status & UHCI_TD_STALLED) ? 1221 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION; 1222 } 1223 1224 static void 1225 uhci_non_isoc_done(struct usb_xfer *xfer) 1226 { 1227 usb_error_t err = 0; 1228 1229 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1230 xfer, xfer->endpoint); 1231 1232 #if USB_DEBUG 1233 if (uhcidebug > 10) { 1234 uhci_dump_tds(xfer->td_transfer_first); 1235 } 1236 #endif 1237 1238 /* sync any DMA memory before doing fixups */ 1239 1240 usb_bdma_post_sync(xfer); 1241 1242 /* reset scanner */ 1243 1244 xfer->td_transfer_cache = xfer->td_transfer_first; 1245 1246 if (xfer->flags_int.control_xfr) { 1247 if (xfer->flags_int.control_hdr) { 1248 1249 err = uhci_non_isoc_done_sub(xfer); 1250 } 1251 xfer->aframes = 1; 1252 1253 if (xfer->td_transfer_cache == NULL) { 1254 goto done; 1255 } 1256 } 1257 while (xfer->aframes != xfer->nframes) { 1258 1259 err = uhci_non_isoc_done_sub(xfer); 1260 xfer->aframes++; 1261 1262 if (xfer->td_transfer_cache == NULL) { 1263 goto done; 1264 } 1265 } 1266 1267 if (xfer->flags_int.control_xfr && 1268 !xfer->flags_int.control_act) { 1269 1270 err = uhci_non_isoc_done_sub(xfer); 1271 } 1272 done: 1273 uhci_device_done(xfer, err); 1274 } 1275 1276 /*------------------------------------------------------------------------* 1277 * uhci_check_transfer_sub 1278 * 1279 * The main purpose of this function is to update the data-toggle 1280 * in case it is wrong. 1281 *------------------------------------------------------------------------*/ 1282 static void 1283 uhci_check_transfer_sub(struct usb_xfer *xfer) 1284 { 1285 uhci_qh_t *qh; 1286 uhci_td_t *td; 1287 uhci_td_t *td_alt_next; 1288 1289 uint32_t td_token; 1290 uint32_t td_self; 1291 1292 td = xfer->td_transfer_cache; 1293 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1294 1295 td_token = td->obj_next->td_token; 1296 td = td->alt_next; 1297 xfer->td_transfer_cache = td; 1298 td_self = td->td_self; 1299 td_alt_next = td->alt_next; 1300 1301 if (xfer->flags_int.control_xfr) 1302 goto skip; /* don't touch the DT value! */ 1303 1304 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1)))) 1305 goto skip; /* data toggle has correct value */ 1306 1307 /* 1308 * The data toggle is wrong and we need to toggle it ! 1309 */ 1310 while (1) { 1311 1312 td->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1313 usb_pc_cpu_flush(td->page_cache); 1314 1315 if (td == xfer->td_transfer_last) { 1316 /* last transfer */ 1317 break; 1318 } 1319 td = td->obj_next; 1320 1321 if (td->alt_next != td_alt_next) { 1322 /* next frame */ 1323 break; 1324 } 1325 } 1326 skip: 1327 1328 /* update the QH */ 1329 qh->qh_e_next = td_self; 1330 usb_pc_cpu_flush(qh->page_cache); 1331 1332 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1333 } 1334 1335 /*------------------------------------------------------------------------* 1336 * uhci_check_transfer 1337 * 1338 * Return values: 1339 * 0: USB transfer is not finished 1340 * Else: USB transfer is finished 1341 *------------------------------------------------------------------------*/ 1342 static uint8_t 1343 uhci_check_transfer(struct usb_xfer *xfer) 1344 { 1345 uint32_t status; 1346 uint32_t token; 1347 uhci_td_t *td; 1348 1349 DPRINTFN(16, "xfer=%p checking transfer\n", xfer); 1350 1351 if (xfer->endpoint->methods == &uhci_device_isoc_methods) { 1352 /* isochronous transfer */ 1353 1354 td = xfer->td_transfer_last; 1355 1356 usb_pc_cpu_invalidate(td->page_cache); 1357 status = le32toh(td->td_status); 1358 1359 /* check also if the first is complete */ 1360 1361 td = xfer->td_transfer_first; 1362 1363 usb_pc_cpu_invalidate(td->page_cache); 1364 status |= le32toh(td->td_status); 1365 1366 if (!(status & UHCI_TD_ACTIVE)) { 1367 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1368 goto transferred; 1369 } 1370 } else { 1371 /* non-isochronous transfer */ 1372 1373 /* 1374 * check whether there is an error somewhere 1375 * in the middle, or whether there was a short 1376 * packet (SPD and not ACTIVE) 1377 */ 1378 td = xfer->td_transfer_cache; 1379 1380 while (1) { 1381 usb_pc_cpu_invalidate(td->page_cache); 1382 status = le32toh(td->td_status); 1383 token = le32toh(td->td_token); 1384 1385 /* 1386 * if there is an active TD the transfer isn't done 1387 */ 1388 if (status & UHCI_TD_ACTIVE) { 1389 /* update cache */ 1390 xfer->td_transfer_cache = td; 1391 goto done; 1392 } 1393 /* 1394 * last transfer descriptor makes the transfer done 1395 */ 1396 if (((void *)td) == xfer->td_transfer_last) { 1397 break; 1398 } 1399 /* 1400 * any kind of error makes the transfer done 1401 */ 1402 if (status & UHCI_TD_STALLED) { 1403 break; 1404 } 1405 /* 1406 * check if we reached the last packet 1407 * or if there is a short packet: 1408 */ 1409 if ((td->td_next == htole32(UHCI_PTR_T)) || 1410 (UHCI_TD_GET_ACTLEN(status) < td->len)) { 1411 1412 if (xfer->flags_int.short_frames_ok) { 1413 /* follow alt next */ 1414 if (td->alt_next) { 1415 /* update cache */ 1416 xfer->td_transfer_cache = td; 1417 uhci_check_transfer_sub(xfer); 1418 goto done; 1419 } 1420 } 1421 /* transfer is done */ 1422 break; 1423 } 1424 td = td->obj_next; 1425 } 1426 uhci_non_isoc_done(xfer); 1427 goto transferred; 1428 } 1429 1430 done: 1431 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1432 return (0); 1433 1434 transferred: 1435 return (1); 1436 } 1437 1438 static void 1439 uhci_interrupt_poll(uhci_softc_t *sc) 1440 { 1441 struct usb_xfer *xfer; 1442 1443 repeat: 1444 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1445 /* 1446 * check if transfer is transferred 1447 */ 1448 if (uhci_check_transfer(xfer)) { 1449 /* queue has been modified */ 1450 goto repeat; 1451 } 1452 } 1453 } 1454 1455 /*------------------------------------------------------------------------* 1456 * uhci_interrupt - UHCI interrupt handler 1457 * 1458 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1459 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1460 * is present ! 1461 *------------------------------------------------------------------------*/ 1462 void 1463 uhci_interrupt(uhci_softc_t *sc) 1464 { 1465 uint32_t status; 1466 1467 USB_BUS_LOCK(&sc->sc_bus); 1468 1469 DPRINTFN(16, "real interrupt\n"); 1470 1471 #if USB_DEBUG 1472 if (uhcidebug > 15) { 1473 uhci_dumpregs(sc); 1474 } 1475 #endif 1476 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1477 if (status == 0) { 1478 /* the interrupt was not for us */ 1479 goto done; 1480 } 1481 if (status & (UHCI_STS_RD | UHCI_STS_HSE | 1482 UHCI_STS_HCPE | UHCI_STS_HCH)) { 1483 1484 if (status & UHCI_STS_RD) { 1485 #if USB_DEBUG 1486 printf("%s: resume detect\n", 1487 __FUNCTION__); 1488 #endif 1489 } 1490 if (status & UHCI_STS_HSE) { 1491 printf("%s: host system error\n", 1492 __FUNCTION__); 1493 } 1494 if (status & UHCI_STS_HCPE) { 1495 printf("%s: host controller process error\n", 1496 __FUNCTION__); 1497 } 1498 if (status & UHCI_STS_HCH) { 1499 /* no acknowledge needed */ 1500 DPRINTF("%s: host controller halted\n", 1501 __FUNCTION__); 1502 #if USB_DEBUG 1503 if (uhcidebug > 0) { 1504 uhci_dump_all(sc); 1505 } 1506 #endif 1507 } 1508 } 1509 /* get acknowledge bits */ 1510 status &= (UHCI_STS_USBINT | 1511 UHCI_STS_USBEI | 1512 UHCI_STS_RD | 1513 UHCI_STS_HSE | 1514 UHCI_STS_HCPE); 1515 1516 if (status == 0) { 1517 /* nothing to acknowledge */ 1518 goto done; 1519 } 1520 /* acknowledge interrupts */ 1521 UWRITE2(sc, UHCI_STS, status); 1522 1523 /* poll all the USB transfers */ 1524 uhci_interrupt_poll(sc); 1525 1526 done: 1527 USB_BUS_UNLOCK(&sc->sc_bus); 1528 } 1529 1530 /* 1531 * called when a request does not complete 1532 */ 1533 static void 1534 uhci_timeout(void *arg) 1535 { 1536 struct usb_xfer *xfer = arg; 1537 1538 DPRINTF("xfer=%p\n", xfer); 1539 1540 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1541 1542 /* transfer is transferred */ 1543 uhci_device_done(xfer, USB_ERR_TIMEOUT); 1544 } 1545 1546 static void 1547 uhci_do_poll(struct usb_bus *bus) 1548 { 1549 struct uhci_softc *sc = UHCI_BUS2SC(bus); 1550 1551 USB_BUS_LOCK(&sc->sc_bus); 1552 uhci_interrupt_poll(sc); 1553 USB_BUS_UNLOCK(&sc->sc_bus); 1554 } 1555 1556 static void 1557 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp) 1558 { 1559 uhci_td_t *td; 1560 uhci_td_t *td_next; 1561 uhci_td_t *td_alt_next; 1562 uint32_t average; 1563 uint32_t len_old; 1564 uint8_t shortpkt_old; 1565 uint8_t precompute; 1566 1567 td_alt_next = NULL; 1568 shortpkt_old = temp->shortpkt; 1569 len_old = temp->len; 1570 precompute = 1; 1571 1572 /* software is used to detect short incoming transfers */ 1573 1574 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) { 1575 temp->td_status |= htole32(UHCI_TD_SPD); 1576 } else { 1577 temp->td_status &= ~htole32(UHCI_TD_SPD); 1578 } 1579 1580 temp->ml.buf_offset = 0; 1581 1582 restart: 1583 1584 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1585 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average)); 1586 1587 td = temp->td; 1588 td_next = temp->td_next; 1589 1590 while (1) { 1591 1592 if (temp->len == 0) { 1593 1594 if (temp->shortpkt) { 1595 break; 1596 } 1597 /* send a Zero Length Packet, ZLP, last */ 1598 1599 temp->shortpkt = 1; 1600 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0)); 1601 average = 0; 1602 1603 } else { 1604 1605 average = temp->average; 1606 1607 if (temp->len < average) { 1608 temp->shortpkt = 1; 1609 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1610 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len)); 1611 average = temp->len; 1612 } 1613 } 1614 1615 if (td_next == NULL) { 1616 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__); 1617 } 1618 /* get next TD */ 1619 1620 td = td_next; 1621 td_next = td->obj_next; 1622 1623 /* check if we are pre-computing */ 1624 1625 if (precompute) { 1626 1627 /* update remaining length */ 1628 1629 temp->len -= average; 1630 1631 continue; 1632 } 1633 /* fill out current TD */ 1634 1635 td->td_status = temp->td_status; 1636 td->td_token = temp->td_token; 1637 1638 /* update data toggle */ 1639 1640 temp->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1641 1642 if (average == 0) { 1643 1644 td->len = 0; 1645 td->td_buffer = 0; 1646 td->fix_pc = NULL; 1647 1648 } else { 1649 1650 /* update remaining length */ 1651 1652 temp->len -= average; 1653 1654 td->len = average; 1655 1656 /* fill out buffer pointer and do fixup, if any */ 1657 1658 uhci_mem_layout_fixup(&temp->ml, td); 1659 } 1660 1661 td->alt_next = td_alt_next; 1662 1663 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1664 /* we need to receive these frames one by one ! */ 1665 td->td_status |= htole32(UHCI_TD_IOC); 1666 td->td_next = htole32(UHCI_PTR_T); 1667 } else { 1668 if (td_next) { 1669 /* link the current TD with the next one */ 1670 td->td_next = td_next->td_self; 1671 } 1672 } 1673 1674 usb_pc_cpu_flush(td->page_cache); 1675 } 1676 1677 if (precompute) { 1678 precompute = 0; 1679 1680 /* setup alt next pointer, if any */ 1681 if (temp->last_frame) { 1682 td_alt_next = NULL; 1683 } else { 1684 /* we use this field internally */ 1685 td_alt_next = td_next; 1686 } 1687 1688 /* restore */ 1689 temp->shortpkt = shortpkt_old; 1690 temp->len = len_old; 1691 goto restart; 1692 } 1693 temp->td = td; 1694 temp->td_next = td_next; 1695 } 1696 1697 static uhci_td_t * 1698 uhci_setup_standard_chain(struct usb_xfer *xfer) 1699 { 1700 struct uhci_std_temp temp; 1701 uhci_td_t *td; 1702 uint32_t x; 1703 1704 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1705 xfer->address, UE_GET_ADDR(xfer->endpointno), 1706 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1707 1708 temp.average = xfer->max_frame_size; 1709 temp.max_frame_size = xfer->max_frame_size; 1710 1711 /* toggle the DMA set we are using */ 1712 xfer->flags_int.curr_dma_set ^= 1; 1713 1714 /* get next DMA set */ 1715 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1716 xfer->td_transfer_first = td; 1717 xfer->td_transfer_cache = td; 1718 1719 temp.td = NULL; 1720 temp.td_next = td; 1721 temp.last_frame = 0; 1722 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1723 1724 uhci_mem_layout_init(&temp.ml, xfer); 1725 1726 temp.td_status = 1727 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | 1728 UHCI_TD_ACTIVE)); 1729 1730 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1731 temp.td_status |= htole32(UHCI_TD_LS); 1732 } 1733 temp.td_token = 1734 htole32(UHCI_TD_SET_ENDPT(xfer->endpointno) | 1735 UHCI_TD_SET_DEVADDR(xfer->address)); 1736 1737 if (xfer->endpoint->toggle_next) { 1738 /* DATA1 is next */ 1739 temp.td_token |= htole32(UHCI_TD_SET_DT(1)); 1740 } 1741 /* check if we should prepend a setup message */ 1742 1743 if (xfer->flags_int.control_xfr) { 1744 1745 if (xfer->flags_int.control_hdr) { 1746 1747 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1748 UHCI_TD_SET_ENDPT(0xF)); 1749 temp.td_token |= htole32(UHCI_TD_PID_SETUP | 1750 UHCI_TD_SET_DT(0)); 1751 1752 temp.len = xfer->frlengths[0]; 1753 temp.ml.buf_pc = xfer->frbuffers + 0; 1754 temp.shortpkt = temp.len ? 1 : 0; 1755 /* check for last frame */ 1756 if (xfer->nframes == 1) { 1757 /* no STATUS stage yet, SETUP is last */ 1758 if (xfer->flags_int.control_act) { 1759 temp.last_frame = 1; 1760 temp.setup_alt_next = 0; 1761 } 1762 } 1763 uhci_setup_standard_chain_sub(&temp); 1764 } 1765 x = 1; 1766 } else { 1767 x = 0; 1768 } 1769 1770 while (x != xfer->nframes) { 1771 1772 /* DATA0 / DATA1 message */ 1773 1774 temp.len = xfer->frlengths[x]; 1775 temp.ml.buf_pc = xfer->frbuffers + x; 1776 1777 x++; 1778 1779 if (x == xfer->nframes) { 1780 if (xfer->flags_int.control_xfr) { 1781 /* no STATUS stage yet, DATA is last */ 1782 if (xfer->flags_int.control_act) { 1783 temp.last_frame = 1; 1784 temp.setup_alt_next = 0; 1785 } 1786 } else { 1787 temp.last_frame = 1; 1788 temp.setup_alt_next = 0; 1789 } 1790 } 1791 /* 1792 * Keep previous data toggle, 1793 * device address and endpoint number: 1794 */ 1795 1796 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1797 UHCI_TD_SET_ENDPT(0xF) | 1798 UHCI_TD_SET_DT(1)); 1799 1800 if (temp.len == 0) { 1801 1802 /* make sure that we send an USB packet */ 1803 1804 temp.shortpkt = 0; 1805 1806 } else { 1807 1808 /* regular data transfer */ 1809 1810 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1811 } 1812 1813 /* set endpoint direction */ 1814 1815 temp.td_token |= 1816 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1817 htole32(UHCI_TD_PID_IN) : 1818 htole32(UHCI_TD_PID_OUT); 1819 1820 uhci_setup_standard_chain_sub(&temp); 1821 } 1822 1823 /* check if we should append a status stage */ 1824 1825 if (xfer->flags_int.control_xfr && 1826 !xfer->flags_int.control_act) { 1827 1828 /* 1829 * send a DATA1 message and reverse the current endpoint 1830 * direction 1831 */ 1832 1833 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1834 UHCI_TD_SET_ENDPT(0xF) | 1835 UHCI_TD_SET_DT(1)); 1836 temp.td_token |= 1837 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1838 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) : 1839 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1)); 1840 1841 temp.len = 0; 1842 temp.ml.buf_pc = NULL; 1843 temp.shortpkt = 0; 1844 temp.last_frame = 1; 1845 temp.setup_alt_next = 0; 1846 1847 uhci_setup_standard_chain_sub(&temp); 1848 } 1849 td = temp.td; 1850 1851 /* Ensure that last TD is terminating: */ 1852 td->td_next = htole32(UHCI_PTR_T); 1853 1854 /* set interrupt bit */ 1855 1856 td->td_status |= htole32(UHCI_TD_IOC); 1857 1858 usb_pc_cpu_flush(td->page_cache); 1859 1860 /* must have at least one frame! */ 1861 1862 xfer->td_transfer_last = td; 1863 1864 #if USB_DEBUG 1865 if (uhcidebug > 8) { 1866 DPRINTF("nexttog=%d; data before transfer:\n", 1867 xfer->endpoint->toggle_next); 1868 uhci_dump_tds(xfer->td_transfer_first); 1869 } 1870 #endif 1871 return (xfer->td_transfer_first); 1872 } 1873 1874 /* NOTE: "done" can be run two times in a row, 1875 * from close and from interrupt 1876 */ 1877 1878 static void 1879 uhci_device_done(struct usb_xfer *xfer, usb_error_t error) 1880 { 1881 struct usb_pipe_methods *methods = xfer->endpoint->methods; 1882 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1883 uhci_qh_t *qh; 1884 1885 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1886 1887 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1888 xfer, xfer->endpoint, error); 1889 1890 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1891 if (qh) { 1892 usb_pc_cpu_invalidate(qh->page_cache); 1893 } 1894 if (xfer->flags_int.bandwidth_reclaimed) { 1895 xfer->flags_int.bandwidth_reclaimed = 0; 1896 uhci_rem_loop(sc); 1897 } 1898 if (methods == &uhci_device_bulk_methods) { 1899 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 1900 } 1901 if (methods == &uhci_device_ctrl_methods) { 1902 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1903 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 1904 } else { 1905 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 1906 } 1907 } 1908 if (methods == &uhci_device_intr_methods) { 1909 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 1910 } 1911 /* 1912 * Only finish isochronous transfers once 1913 * which will update "xfer->frlengths". 1914 */ 1915 if (xfer->td_transfer_first && 1916 xfer->td_transfer_last) { 1917 if (methods == &uhci_device_isoc_methods) { 1918 uhci_isoc_done(sc, xfer); 1919 } 1920 xfer->td_transfer_first = NULL; 1921 xfer->td_transfer_last = NULL; 1922 } 1923 /* dequeue transfer and start next transfer */ 1924 usbd_transfer_done(xfer, error); 1925 } 1926 1927 /*------------------------------------------------------------------------* 1928 * uhci bulk support 1929 *------------------------------------------------------------------------*/ 1930 static void 1931 uhci_device_bulk_open(struct usb_xfer *xfer) 1932 { 1933 return; 1934 } 1935 1936 static void 1937 uhci_device_bulk_close(struct usb_xfer *xfer) 1938 { 1939 uhci_device_done(xfer, USB_ERR_CANCELLED); 1940 } 1941 1942 static void 1943 uhci_device_bulk_enter(struct usb_xfer *xfer) 1944 { 1945 return; 1946 } 1947 1948 static void 1949 uhci_device_bulk_start(struct usb_xfer *xfer) 1950 { 1951 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1952 uhci_td_t *td; 1953 uhci_qh_t *qh; 1954 1955 /* setup TD's */ 1956 td = uhci_setup_standard_chain(xfer); 1957 1958 /* setup QH */ 1959 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1960 1961 qh->e_next = td; 1962 qh->qh_e_next = td->td_self; 1963 1964 if (xfer->xroot->udev->flags.self_suspended == 0) { 1965 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 1966 uhci_add_loop(sc); 1967 xfer->flags_int.bandwidth_reclaimed = 1; 1968 } else { 1969 usb_pc_cpu_flush(qh->page_cache); 1970 } 1971 1972 /* put transfer on interrupt queue */ 1973 uhci_transfer_intr_enqueue(xfer); 1974 } 1975 1976 struct usb_pipe_methods uhci_device_bulk_methods = 1977 { 1978 .open = uhci_device_bulk_open, 1979 .close = uhci_device_bulk_close, 1980 .enter = uhci_device_bulk_enter, 1981 .start = uhci_device_bulk_start, 1982 }; 1983 1984 /*------------------------------------------------------------------------* 1985 * uhci control support 1986 *------------------------------------------------------------------------*/ 1987 static void 1988 uhci_device_ctrl_open(struct usb_xfer *xfer) 1989 { 1990 return; 1991 } 1992 1993 static void 1994 uhci_device_ctrl_close(struct usb_xfer *xfer) 1995 { 1996 uhci_device_done(xfer, USB_ERR_CANCELLED); 1997 } 1998 1999 static void 2000 uhci_device_ctrl_enter(struct usb_xfer *xfer) 2001 { 2002 return; 2003 } 2004 2005 static void 2006 uhci_device_ctrl_start(struct usb_xfer *xfer) 2007 { 2008 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2009 uhci_qh_t *qh; 2010 uhci_td_t *td; 2011 2012 /* setup TD's */ 2013 td = uhci_setup_standard_chain(xfer); 2014 2015 /* setup QH */ 2016 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2017 2018 qh->e_next = td; 2019 qh->qh_e_next = td->td_self; 2020 2021 /* 2022 * NOTE: some devices choke on bandwidth- reclamation for control 2023 * transfers 2024 */ 2025 if (xfer->xroot->udev->flags.self_suspended == 0) { 2026 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 2027 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 2028 } else { 2029 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 2030 } 2031 } else { 2032 usb_pc_cpu_flush(qh->page_cache); 2033 } 2034 /* put transfer on interrupt queue */ 2035 uhci_transfer_intr_enqueue(xfer); 2036 } 2037 2038 struct usb_pipe_methods uhci_device_ctrl_methods = 2039 { 2040 .open = uhci_device_ctrl_open, 2041 .close = uhci_device_ctrl_close, 2042 .enter = uhci_device_ctrl_enter, 2043 .start = uhci_device_ctrl_start, 2044 }; 2045 2046 /*------------------------------------------------------------------------* 2047 * uhci interrupt support 2048 *------------------------------------------------------------------------*/ 2049 static void 2050 uhci_device_intr_open(struct usb_xfer *xfer) 2051 { 2052 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2053 uint16_t best; 2054 uint16_t bit; 2055 uint16_t x; 2056 2057 best = 0; 2058 bit = UHCI_IFRAMELIST_COUNT / 2; 2059 while (bit) { 2060 if (xfer->interval >= bit) { 2061 x = bit; 2062 best = bit; 2063 while (x & bit) { 2064 if (sc->sc_intr_stat[x] < 2065 sc->sc_intr_stat[best]) { 2066 best = x; 2067 } 2068 x++; 2069 } 2070 break; 2071 } 2072 bit >>= 1; 2073 } 2074 2075 sc->sc_intr_stat[best]++; 2076 xfer->qh_pos = best; 2077 2078 DPRINTFN(3, "best=%d interval=%d\n", 2079 best, xfer->interval); 2080 } 2081 2082 static void 2083 uhci_device_intr_close(struct usb_xfer *xfer) 2084 { 2085 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2086 2087 sc->sc_intr_stat[xfer->qh_pos]--; 2088 2089 uhci_device_done(xfer, USB_ERR_CANCELLED); 2090 } 2091 2092 static void 2093 uhci_device_intr_enter(struct usb_xfer *xfer) 2094 { 2095 return; 2096 } 2097 2098 static void 2099 uhci_device_intr_start(struct usb_xfer *xfer) 2100 { 2101 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2102 uhci_qh_t *qh; 2103 uhci_td_t *td; 2104 2105 /* setup TD's */ 2106 td = uhci_setup_standard_chain(xfer); 2107 2108 /* setup QH */ 2109 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2110 2111 qh->e_next = td; 2112 qh->qh_e_next = td->td_self; 2113 2114 if (xfer->xroot->udev->flags.self_suspended == 0) { 2115 /* enter QHs into the controller data structures */ 2116 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 2117 } else { 2118 usb_pc_cpu_flush(qh->page_cache); 2119 } 2120 2121 /* put transfer on interrupt queue */ 2122 uhci_transfer_intr_enqueue(xfer); 2123 } 2124 2125 struct usb_pipe_methods uhci_device_intr_methods = 2126 { 2127 .open = uhci_device_intr_open, 2128 .close = uhci_device_intr_close, 2129 .enter = uhci_device_intr_enter, 2130 .start = uhci_device_intr_start, 2131 }; 2132 2133 /*------------------------------------------------------------------------* 2134 * uhci isochronous support 2135 *------------------------------------------------------------------------*/ 2136 static void 2137 uhci_device_isoc_open(struct usb_xfer *xfer) 2138 { 2139 uhci_td_t *td; 2140 uint32_t td_token; 2141 uint8_t ds; 2142 2143 td_token = 2144 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 2145 UHCI_TD_IN(0, xfer->endpointno, xfer->address, 0) : 2146 UHCI_TD_OUT(0, xfer->endpointno, xfer->address, 0); 2147 2148 td_token = htole32(td_token); 2149 2150 /* initialize all TD's */ 2151 2152 for (ds = 0; ds != 2; ds++) { 2153 2154 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2155 2156 /* mark TD as inactive */ 2157 td->td_status = htole32(UHCI_TD_IOS); 2158 td->td_token = td_token; 2159 2160 usb_pc_cpu_flush(td->page_cache); 2161 } 2162 } 2163 } 2164 2165 static void 2166 uhci_device_isoc_close(struct usb_xfer *xfer) 2167 { 2168 uhci_device_done(xfer, USB_ERR_CANCELLED); 2169 } 2170 2171 static void 2172 uhci_device_isoc_enter(struct usb_xfer *xfer) 2173 { 2174 struct uhci_mem_layout ml; 2175 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2176 uint32_t nframes; 2177 uint32_t temp; 2178 uint32_t *plen; 2179 2180 #if USB_DEBUG 2181 uint8_t once = 1; 2182 2183 #endif 2184 uhci_td_t *td; 2185 uhci_td_t *td_last = NULL; 2186 uhci_td_t **pp_last; 2187 2188 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2189 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2190 2191 nframes = UREAD2(sc, UHCI_FRNUM); 2192 2193 temp = (nframes - xfer->endpoint->isoc_next) & 2194 (UHCI_VFRAMELIST_COUNT - 1); 2195 2196 if ((xfer->endpoint->is_synced == 0) || 2197 (temp < xfer->nframes)) { 2198 /* 2199 * If there is data underflow or the pipe queue is empty we 2200 * schedule the transfer a few frames ahead of the current 2201 * frame position. Else two isochronous transfers might 2202 * overlap. 2203 */ 2204 xfer->endpoint->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1); 2205 xfer->endpoint->is_synced = 1; 2206 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2207 } 2208 /* 2209 * compute how many milliseconds the insertion is ahead of the 2210 * current frame position: 2211 */ 2212 temp = (xfer->endpoint->isoc_next - nframes) & 2213 (UHCI_VFRAMELIST_COUNT - 1); 2214 2215 /* 2216 * pre-compute when the isochronous transfer will be finished: 2217 */ 2218 xfer->isoc_time_complete = 2219 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2220 xfer->nframes; 2221 2222 /* get the real number of frames */ 2223 2224 nframes = xfer->nframes; 2225 2226 uhci_mem_layout_init(&ml, xfer); 2227 2228 plen = xfer->frlengths; 2229 2230 /* toggle the DMA set we are using */ 2231 xfer->flags_int.curr_dma_set ^= 1; 2232 2233 /* get next DMA set */ 2234 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2235 xfer->td_transfer_first = td; 2236 2237 pp_last = &sc->sc_isoc_p_last[xfer->endpoint->isoc_next]; 2238 2239 /* store starting position */ 2240 2241 xfer->qh_pos = xfer->endpoint->isoc_next; 2242 2243 while (nframes--) { 2244 if (td == NULL) { 2245 panic("%s:%d: out of TD's\n", 2246 __FUNCTION__, __LINE__); 2247 } 2248 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 2249 pp_last = &sc->sc_isoc_p_last[0]; 2250 } 2251 if (*plen > xfer->max_frame_size) { 2252 #if USB_DEBUG 2253 if (once) { 2254 once = 0; 2255 printf("%s: frame length(%d) exceeds %d " 2256 "bytes (frame truncated)\n", 2257 __FUNCTION__, *plen, 2258 xfer->max_frame_size); 2259 } 2260 #endif 2261 *plen = xfer->max_frame_size; 2262 } 2263 /* reuse td_token from last transfer */ 2264 2265 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2266 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen)); 2267 2268 td->len = *plen; 2269 2270 if (td->len == 0) { 2271 /* 2272 * Do not call "uhci_mem_layout_fixup()" when the 2273 * length is zero! 2274 */ 2275 td->td_buffer = 0; 2276 td->fix_pc = NULL; 2277 2278 } else { 2279 2280 /* fill out buffer pointer and do fixup, if any */ 2281 2282 uhci_mem_layout_fixup(&ml, td); 2283 2284 } 2285 2286 /* update status */ 2287 if (nframes == 0) { 2288 td->td_status = htole32 2289 (UHCI_TD_ZERO_ACTLEN 2290 (UHCI_TD_SET_ERRCNT(0) | 2291 UHCI_TD_ACTIVE | 2292 UHCI_TD_IOS | 2293 UHCI_TD_IOC)); 2294 } else { 2295 td->td_status = htole32 2296 (UHCI_TD_ZERO_ACTLEN 2297 (UHCI_TD_SET_ERRCNT(0) | 2298 UHCI_TD_ACTIVE | 2299 UHCI_TD_IOS)); 2300 } 2301 2302 usb_pc_cpu_flush(td->page_cache); 2303 2304 #if USB_DEBUG 2305 if (uhcidebug > 5) { 2306 DPRINTF("TD %d\n", nframes); 2307 uhci_dump_td(td); 2308 } 2309 #endif 2310 /* insert TD into schedule */ 2311 UHCI_APPEND_TD(td, *pp_last); 2312 pp_last++; 2313 2314 plen++; 2315 td_last = td; 2316 td = td->obj_next; 2317 } 2318 2319 xfer->td_transfer_last = td_last; 2320 2321 /* update isoc_next */ 2322 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) & 2323 (UHCI_VFRAMELIST_COUNT - 1); 2324 } 2325 2326 static void 2327 uhci_device_isoc_start(struct usb_xfer *xfer) 2328 { 2329 /* put transfer on interrupt queue */ 2330 uhci_transfer_intr_enqueue(xfer); 2331 } 2332 2333 struct usb_pipe_methods uhci_device_isoc_methods = 2334 { 2335 .open = uhci_device_isoc_open, 2336 .close = uhci_device_isoc_close, 2337 .enter = uhci_device_isoc_enter, 2338 .start = uhci_device_isoc_start, 2339 }; 2340 2341 /*------------------------------------------------------------------------* 2342 * uhci root control support 2343 *------------------------------------------------------------------------* 2344 * Simulate a hardware hub by handling all the necessary requests. 2345 *------------------------------------------------------------------------*/ 2346 2347 static const 2348 struct usb_device_descriptor uhci_devd = 2349 { 2350 sizeof(struct usb_device_descriptor), 2351 UDESC_DEVICE, /* type */ 2352 {0x00, 0x01}, /* USB version */ 2353 UDCLASS_HUB, /* class */ 2354 UDSUBCLASS_HUB, /* subclass */ 2355 UDPROTO_FSHUB, /* protocol */ 2356 64, /* max packet */ 2357 {0}, {0}, {0x00, 0x01}, /* device id */ 2358 1, 2, 0, /* string indicies */ 2359 1 /* # of configurations */ 2360 }; 2361 2362 static const struct uhci_config_desc uhci_confd = { 2363 .confd = { 2364 .bLength = sizeof(struct usb_config_descriptor), 2365 .bDescriptorType = UDESC_CONFIG, 2366 .wTotalLength[0] = sizeof(uhci_confd), 2367 .bNumInterface = 1, 2368 .bConfigurationValue = 1, 2369 .iConfiguration = 0, 2370 .bmAttributes = UC_SELF_POWERED, 2371 .bMaxPower = 0 /* max power */ 2372 }, 2373 .ifcd = { 2374 .bLength = sizeof(struct usb_interface_descriptor), 2375 .bDescriptorType = UDESC_INTERFACE, 2376 .bNumEndpoints = 1, 2377 .bInterfaceClass = UICLASS_HUB, 2378 .bInterfaceSubClass = UISUBCLASS_HUB, 2379 .bInterfaceProtocol = UIPROTO_FSHUB, 2380 }, 2381 .endpd = { 2382 .bLength = sizeof(struct usb_endpoint_descriptor), 2383 .bDescriptorType = UDESC_ENDPOINT, 2384 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 2385 .bmAttributes = UE_INTERRUPT, 2386 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2387 .bInterval = 255, 2388 }, 2389 }; 2390 2391 static const 2392 struct usb_hub_descriptor_min uhci_hubd_piix = 2393 { 2394 sizeof(uhci_hubd_piix), 2395 UDESC_HUB, 2396 2, 2397 {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0}, 2398 50, /* power on to power good */ 2399 0, 2400 {0x00}, /* both ports are removable */ 2401 }; 2402 2403 /* 2404 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 2405 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 2406 * should not be used by the USB subsystem. As we cannot issue a 2407 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 2408 * will be enabled as part of the reset. 2409 * 2410 * On the VT83C572, the port cannot be successfully enabled until the 2411 * outstanding "port enable change" and "connection status change" 2412 * events have been reset. 2413 */ 2414 static usb_error_t 2415 uhci_portreset(uhci_softc_t *sc, uint16_t index) 2416 { 2417 uint16_t port; 2418 uint16_t x; 2419 uint8_t lim; 2420 2421 if (index == 1) 2422 port = UHCI_PORTSC1; 2423 else if (index == 2) 2424 port = UHCI_PORTSC2; 2425 else 2426 return (USB_ERR_IOERROR); 2427 2428 /* 2429 * Before we do anything, turn on SOF messages on the USB 2430 * BUS. Some USB devices do not cope without them! 2431 */ 2432 uhci_restart(sc); 2433 2434 x = URWMASK(UREAD2(sc, port)); 2435 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2436 2437 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2438 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 2439 2440 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n", 2441 index, UREAD2(sc, port)); 2442 2443 x = URWMASK(UREAD2(sc, port)); 2444 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2445 2446 2447 mtx_unlock(&sc->sc_bus.bus_mtx); 2448 2449 /* 2450 * This delay needs to be exactly 100us, else some USB devices 2451 * fail to attach! 2452 */ 2453 DELAY(100); 2454 2455 mtx_lock(&sc->sc_bus.bus_mtx); 2456 2457 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n", 2458 index, UREAD2(sc, port)); 2459 2460 x = URWMASK(UREAD2(sc, port)); 2461 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2462 2463 for (lim = 0; lim < 12; lim++) { 2464 2465 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2466 USB_MS_TO_TICKS(USB_PORT_RESET_DELAY)); 2467 2468 x = UREAD2(sc, port); 2469 2470 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n", 2471 index, lim, x); 2472 2473 if (!(x & UHCI_PORTSC_CCS)) { 2474 /* 2475 * No device is connected (or was disconnected 2476 * during reset). Consider the port reset. 2477 * The delay must be long enough to ensure on 2478 * the initial iteration that the device 2479 * connection will have been registered. 50ms 2480 * appears to be sufficient, but 20ms is not. 2481 */ 2482 DPRINTFN(4, "uhci port %d loop %u, device detached\n", 2483 index, lim); 2484 goto done; 2485 } 2486 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 2487 /* 2488 * Port enabled changed and/or connection 2489 * status changed were set. Reset either or 2490 * both raised flags (by writing a 1 to that 2491 * bit), and wait again for state to settle. 2492 */ 2493 UWRITE2(sc, port, URWMASK(x) | 2494 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 2495 continue; 2496 } 2497 if (x & UHCI_PORTSC_PE) { 2498 /* port is enabled */ 2499 goto done; 2500 } 2501 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 2502 } 2503 2504 DPRINTFN(2, "uhci port %d reset timed out\n", index); 2505 return (USB_ERR_TIMEOUT); 2506 2507 done: 2508 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n", 2509 index, UREAD2(sc, port)); 2510 2511 sc->sc_isreset = 1; 2512 return (USB_ERR_NORMAL_COMPLETION); 2513 } 2514 2515 static usb_error_t 2516 uhci_roothub_exec(struct usb_device *udev, 2517 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2518 { 2519 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 2520 const void *ptr; 2521 const char *str_ptr; 2522 uint16_t x; 2523 uint16_t port; 2524 uint16_t value; 2525 uint16_t index; 2526 uint16_t status; 2527 uint16_t change; 2528 uint16_t len; 2529 usb_error_t err; 2530 2531 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2532 2533 /* buffer reset */ 2534 ptr = (const void *)&sc->sc_hub_desc.temp; 2535 len = 0; 2536 err = 0; 2537 2538 value = UGETW(req->wValue); 2539 index = UGETW(req->wIndex); 2540 2541 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2542 "wValue=0x%04x wIndex=0x%04x\n", 2543 req->bmRequestType, req->bRequest, 2544 UGETW(req->wLength), value, index); 2545 2546 #define C(x,y) ((x) | ((y) << 8)) 2547 switch (C(req->bRequest, req->bmRequestType)) { 2548 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2549 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2550 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2551 /* 2552 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2553 * for the integrated root hub. 2554 */ 2555 break; 2556 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2557 len = 1; 2558 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2559 break; 2560 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2561 switch (value >> 8) { 2562 case UDESC_DEVICE: 2563 if ((value & 0xff) != 0) { 2564 err = USB_ERR_IOERROR; 2565 goto done; 2566 } 2567 len = sizeof(uhci_devd); 2568 ptr = (const void *)&uhci_devd; 2569 break; 2570 2571 case UDESC_CONFIG: 2572 if ((value & 0xff) != 0) { 2573 err = USB_ERR_IOERROR; 2574 goto done; 2575 } 2576 len = sizeof(uhci_confd); 2577 ptr = (const void *)&uhci_confd; 2578 break; 2579 2580 case UDESC_STRING: 2581 switch (value & 0xff) { 2582 case 0: /* Language table */ 2583 str_ptr = "\001"; 2584 break; 2585 2586 case 1: /* Vendor */ 2587 str_ptr = sc->sc_vendor; 2588 break; 2589 2590 case 2: /* Product */ 2591 str_ptr = "UHCI root HUB"; 2592 break; 2593 2594 default: 2595 str_ptr = ""; 2596 break; 2597 } 2598 2599 len = usb_make_str_desc 2600 (sc->sc_hub_desc.temp, 2601 sizeof(sc->sc_hub_desc.temp), 2602 str_ptr); 2603 break; 2604 2605 default: 2606 err = USB_ERR_IOERROR; 2607 goto done; 2608 } 2609 break; 2610 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2611 len = 1; 2612 sc->sc_hub_desc.temp[0] = 0; 2613 break; 2614 case C(UR_GET_STATUS, UT_READ_DEVICE): 2615 len = 2; 2616 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2617 break; 2618 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2619 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2620 len = 2; 2621 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2622 break; 2623 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2624 if (value >= UHCI_MAX_DEVICES) { 2625 err = USB_ERR_IOERROR; 2626 goto done; 2627 } 2628 sc->sc_addr = value; 2629 break; 2630 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2631 if ((value != 0) && (value != 1)) { 2632 err = USB_ERR_IOERROR; 2633 goto done; 2634 } 2635 sc->sc_conf = value; 2636 break; 2637 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2638 break; 2639 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2640 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2641 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2642 err = USB_ERR_IOERROR; 2643 goto done; 2644 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2645 break; 2646 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2647 break; 2648 /* Hub requests */ 2649 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2650 break; 2651 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2652 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE " 2653 "port=%d feature=%d\n", 2654 index, value); 2655 if (index == 1) 2656 port = UHCI_PORTSC1; 2657 else if (index == 2) 2658 port = UHCI_PORTSC2; 2659 else { 2660 err = USB_ERR_IOERROR; 2661 goto done; 2662 } 2663 switch (value) { 2664 case UHF_PORT_ENABLE: 2665 x = URWMASK(UREAD2(sc, port)); 2666 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2667 break; 2668 case UHF_PORT_SUSPEND: 2669 x = URWMASK(UREAD2(sc, port)); 2670 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP)); 2671 break; 2672 case UHF_PORT_RESET: 2673 x = URWMASK(UREAD2(sc, port)); 2674 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2675 break; 2676 case UHF_C_PORT_CONNECTION: 2677 x = URWMASK(UREAD2(sc, port)); 2678 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2679 break; 2680 case UHF_C_PORT_ENABLE: 2681 x = URWMASK(UREAD2(sc, port)); 2682 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2683 break; 2684 case UHF_C_PORT_OVER_CURRENT: 2685 x = URWMASK(UREAD2(sc, port)); 2686 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2687 break; 2688 case UHF_C_PORT_RESET: 2689 sc->sc_isreset = 0; 2690 err = USB_ERR_NORMAL_COMPLETION; 2691 goto done; 2692 case UHF_C_PORT_SUSPEND: 2693 sc->sc_isresumed &= ~(1 << index); 2694 break; 2695 case UHF_PORT_CONNECTION: 2696 case UHF_PORT_OVER_CURRENT: 2697 case UHF_PORT_POWER: 2698 case UHF_PORT_LOW_SPEED: 2699 default: 2700 err = USB_ERR_IOERROR; 2701 goto done; 2702 } 2703 break; 2704 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2705 if (index == 1) 2706 port = UHCI_PORTSC1; 2707 else if (index == 2) 2708 port = UHCI_PORTSC2; 2709 else { 2710 err = USB_ERR_IOERROR; 2711 goto done; 2712 } 2713 len = 1; 2714 sc->sc_hub_desc.temp[0] = 2715 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2716 UHCI_PORTSC_LS_SHIFT); 2717 break; 2718 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2719 if ((value & 0xff) != 0) { 2720 err = USB_ERR_IOERROR; 2721 goto done; 2722 } 2723 len = sizeof(uhci_hubd_piix); 2724 ptr = (const void *)&uhci_hubd_piix; 2725 break; 2726 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2727 len = 16; 2728 bzero(sc->sc_hub_desc.temp, 16); 2729 break; 2730 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2731 if (index == 1) 2732 port = UHCI_PORTSC1; 2733 else if (index == 2) 2734 port = UHCI_PORTSC2; 2735 else { 2736 err = USB_ERR_IOERROR; 2737 goto done; 2738 } 2739 x = UREAD2(sc, port); 2740 status = change = 0; 2741 if (x & UHCI_PORTSC_CCS) 2742 status |= UPS_CURRENT_CONNECT_STATUS; 2743 if (x & UHCI_PORTSC_CSC) 2744 change |= UPS_C_CONNECT_STATUS; 2745 if (x & UHCI_PORTSC_PE) 2746 status |= UPS_PORT_ENABLED; 2747 if (x & UHCI_PORTSC_POEDC) 2748 change |= UPS_C_PORT_ENABLED; 2749 if (x & UHCI_PORTSC_OCI) 2750 status |= UPS_OVERCURRENT_INDICATOR; 2751 if (x & UHCI_PORTSC_OCIC) 2752 change |= UPS_C_OVERCURRENT_INDICATOR; 2753 if (x & UHCI_PORTSC_LSDA) 2754 status |= UPS_LOW_SPEED; 2755 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) { 2756 /* need to do a write back */ 2757 UWRITE2(sc, port, URWMASK(x)); 2758 2759 /* wait 20ms for resume sequence to complete */ 2760 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 2761 2762 /* clear suspend and resume detect */ 2763 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD | 2764 UHCI_PORTSC_SUSP)); 2765 2766 /* wait a little bit */ 2767 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500); 2768 2769 sc->sc_isresumed |= (1 << index); 2770 2771 } else if (x & UHCI_PORTSC_SUSP) { 2772 status |= UPS_SUSPEND; 2773 } 2774 status |= UPS_PORT_POWER; 2775 if (sc->sc_isresumed & (1 << index)) 2776 change |= UPS_C_SUSPEND; 2777 if (sc->sc_isreset) 2778 change |= UPS_C_PORT_RESET; 2779 USETW(sc->sc_hub_desc.ps.wPortStatus, status); 2780 USETW(sc->sc_hub_desc.ps.wPortChange, change); 2781 len = sizeof(sc->sc_hub_desc.ps); 2782 break; 2783 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2784 err = USB_ERR_IOERROR; 2785 goto done; 2786 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2787 break; 2788 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2789 if (index == 1) 2790 port = UHCI_PORTSC1; 2791 else if (index == 2) 2792 port = UHCI_PORTSC2; 2793 else { 2794 err = USB_ERR_IOERROR; 2795 goto done; 2796 } 2797 switch (value) { 2798 case UHF_PORT_ENABLE: 2799 x = URWMASK(UREAD2(sc, port)); 2800 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2801 break; 2802 case UHF_PORT_SUSPEND: 2803 x = URWMASK(UREAD2(sc, port)); 2804 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2805 break; 2806 case UHF_PORT_RESET: 2807 err = uhci_portreset(sc, index); 2808 goto done; 2809 case UHF_PORT_POWER: 2810 /* pretend we turned on power */ 2811 err = USB_ERR_NORMAL_COMPLETION; 2812 goto done; 2813 case UHF_C_PORT_CONNECTION: 2814 case UHF_C_PORT_ENABLE: 2815 case UHF_C_PORT_OVER_CURRENT: 2816 case UHF_PORT_CONNECTION: 2817 case UHF_PORT_OVER_CURRENT: 2818 case UHF_PORT_LOW_SPEED: 2819 case UHF_C_PORT_SUSPEND: 2820 case UHF_C_PORT_RESET: 2821 default: 2822 err = USB_ERR_IOERROR; 2823 goto done; 2824 } 2825 break; 2826 default: 2827 err = USB_ERR_IOERROR; 2828 goto done; 2829 } 2830 done: 2831 *plength = len; 2832 *pptr = ptr; 2833 return (err); 2834 } 2835 2836 /* 2837 * This routine is executed periodically and simulates interrupts from 2838 * the root controller interrupt pipe for port status change: 2839 */ 2840 static void 2841 uhci_root_intr(uhci_softc_t *sc) 2842 { 2843 DPRINTFN(21, "\n"); 2844 2845 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2846 2847 sc->sc_hub_idata[0] = 0; 2848 2849 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | 2850 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2851 sc->sc_hub_idata[0] |= 1 << 1; 2852 } 2853 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | 2854 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2855 sc->sc_hub_idata[0] |= 1 << 2; 2856 } 2857 2858 /* restart timer */ 2859 usb_callout_reset(&sc->sc_root_intr, hz, 2860 (void *)&uhci_root_intr, sc); 2861 2862 if (sc->sc_hub_idata[0] != 0) { 2863 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2864 sizeof(sc->sc_hub_idata)); 2865 } 2866 } 2867 2868 static void 2869 uhci_xfer_setup(struct usb_setup_params *parm) 2870 { 2871 struct usb_page_search page_info; 2872 struct usb_page_cache *pc; 2873 uhci_softc_t *sc; 2874 struct usb_xfer *xfer; 2875 void *last_obj; 2876 uint32_t ntd; 2877 uint32_t nqh; 2878 uint32_t nfixup; 2879 uint32_t n; 2880 uint16_t align; 2881 2882 sc = UHCI_BUS2SC(parm->udev->bus); 2883 xfer = parm->curr_xfer; 2884 2885 parm->hc_max_packet_size = 0x500; 2886 parm->hc_max_packet_count = 1; 2887 parm->hc_max_frame_size = 0x500; 2888 2889 /* 2890 * compute ntd and nqh 2891 */ 2892 if (parm->methods == &uhci_device_ctrl_methods) { 2893 xfer->flags_int.bdma_enable = 1; 2894 xfer->flags_int.bdma_no_post_sync = 1; 2895 2896 usbd_transfer_setup_sub(parm); 2897 2898 /* see EHCI HC driver for proof of "ntd" formula */ 2899 2900 nqh = 1; 2901 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2902 + (xfer->max_data_length / xfer->max_frame_size)); 2903 2904 } else if (parm->methods == &uhci_device_bulk_methods) { 2905 xfer->flags_int.bdma_enable = 1; 2906 xfer->flags_int.bdma_no_post_sync = 1; 2907 2908 usbd_transfer_setup_sub(parm); 2909 2910 nqh = 1; 2911 ntd = ((2 * xfer->nframes) 2912 + (xfer->max_data_length / xfer->max_frame_size)); 2913 2914 } else if (parm->methods == &uhci_device_intr_methods) { 2915 xfer->flags_int.bdma_enable = 1; 2916 xfer->flags_int.bdma_no_post_sync = 1; 2917 2918 usbd_transfer_setup_sub(parm); 2919 2920 nqh = 1; 2921 ntd = ((2 * xfer->nframes) 2922 + (xfer->max_data_length / xfer->max_frame_size)); 2923 2924 } else if (parm->methods == &uhci_device_isoc_methods) { 2925 xfer->flags_int.bdma_enable = 1; 2926 xfer->flags_int.bdma_no_post_sync = 1; 2927 2928 usbd_transfer_setup_sub(parm); 2929 2930 nqh = 0; 2931 ntd = xfer->nframes; 2932 2933 } else { 2934 2935 usbd_transfer_setup_sub(parm); 2936 2937 nqh = 0; 2938 ntd = 0; 2939 } 2940 2941 if (parm->err) { 2942 return; 2943 } 2944 /* 2945 * NOTE: the UHCI controller requires that 2946 * every packet must be contiguous on 2947 * the same USB memory page ! 2948 */ 2949 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1; 2950 2951 /* 2952 * Compute a suitable power of two alignment 2953 * for our "max_frame_size" fixup buffer(s): 2954 */ 2955 align = xfer->max_frame_size; 2956 n = 0; 2957 while (align) { 2958 align >>= 1; 2959 n++; 2960 } 2961 2962 /* check for power of two */ 2963 if (!(xfer->max_frame_size & 2964 (xfer->max_frame_size - 1))) { 2965 n--; 2966 } 2967 /* 2968 * We don't allow alignments of 2969 * less than 8 bytes: 2970 * 2971 * NOTE: Allocating using an aligment 2972 * of 1 byte has special meaning! 2973 */ 2974 if (n < 3) { 2975 n = 3; 2976 } 2977 align = (1 << n); 2978 2979 if (usbd_transfer_setup_sub_malloc( 2980 parm, &pc, xfer->max_frame_size, 2981 align, nfixup)) { 2982 parm->err = USB_ERR_NOMEM; 2983 return; 2984 } 2985 xfer->buf_fixup = pc; 2986 2987 alloc_dma_set: 2988 2989 if (parm->err) { 2990 return; 2991 } 2992 last_obj = NULL; 2993 2994 if (usbd_transfer_setup_sub_malloc( 2995 parm, &pc, sizeof(uhci_td_t), 2996 UHCI_TD_ALIGN, ntd)) { 2997 parm->err = USB_ERR_NOMEM; 2998 return; 2999 } 3000 if (parm->buf) { 3001 for (n = 0; n != ntd; n++) { 3002 uhci_td_t *td; 3003 3004 usbd_get_page(pc + n, 0, &page_info); 3005 3006 td = page_info.buffer; 3007 3008 /* init TD */ 3009 if ((parm->methods == &uhci_device_bulk_methods) || 3010 (parm->methods == &uhci_device_ctrl_methods) || 3011 (parm->methods == &uhci_device_intr_methods)) { 3012 /* set depth first bit */ 3013 td->td_self = htole32(page_info.physaddr | 3014 UHCI_PTR_TD | UHCI_PTR_VF); 3015 } else { 3016 td->td_self = htole32(page_info.physaddr | 3017 UHCI_PTR_TD); 3018 } 3019 3020 td->obj_next = last_obj; 3021 td->page_cache = pc + n; 3022 3023 last_obj = td; 3024 3025 usb_pc_cpu_flush(pc + n); 3026 } 3027 } 3028 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3029 3030 last_obj = NULL; 3031 3032 if (usbd_transfer_setup_sub_malloc( 3033 parm, &pc, sizeof(uhci_qh_t), 3034 UHCI_QH_ALIGN, nqh)) { 3035 parm->err = USB_ERR_NOMEM; 3036 return; 3037 } 3038 if (parm->buf) { 3039 for (n = 0; n != nqh; n++) { 3040 uhci_qh_t *qh; 3041 3042 usbd_get_page(pc + n, 0, &page_info); 3043 3044 qh = page_info.buffer; 3045 3046 /* init QH */ 3047 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH); 3048 qh->obj_next = last_obj; 3049 qh->page_cache = pc + n; 3050 3051 last_obj = qh; 3052 3053 usb_pc_cpu_flush(pc + n); 3054 } 3055 } 3056 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3057 3058 if (!xfer->flags_int.curr_dma_set) { 3059 xfer->flags_int.curr_dma_set = 1; 3060 goto alloc_dma_set; 3061 } 3062 } 3063 3064 static void 3065 uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3066 struct usb_endpoint *ep) 3067 { 3068 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 3069 3070 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3071 ep, udev->address, 3072 edesc->bEndpointAddress, udev->flags.usb_mode, 3073 sc->sc_addr); 3074 3075 if (udev->flags.usb_mode != USB_MODE_HOST) { 3076 /* not supported */ 3077 return; 3078 } 3079 if (udev->device_index != sc->sc_addr) { 3080 switch (edesc->bmAttributes & UE_XFERTYPE) { 3081 case UE_CONTROL: 3082 ep->methods = &uhci_device_ctrl_methods; 3083 break; 3084 case UE_INTERRUPT: 3085 ep->methods = &uhci_device_intr_methods; 3086 break; 3087 case UE_ISOCHRONOUS: 3088 if (udev->speed == USB_SPEED_FULL) { 3089 ep->methods = &uhci_device_isoc_methods; 3090 } 3091 break; 3092 case UE_BULK: 3093 if (udev->speed != USB_SPEED_LOW) { 3094 ep->methods = &uhci_device_bulk_methods; 3095 } 3096 break; 3097 default: 3098 /* do nothing */ 3099 break; 3100 } 3101 } 3102 } 3103 3104 static void 3105 uhci_xfer_unsetup(struct usb_xfer *xfer) 3106 { 3107 return; 3108 } 3109 3110 static void 3111 uhci_get_dma_delay(struct usb_bus *bus, uint32_t *pus) 3112 { 3113 /* 3114 * Wait until hardware has finished any possible use of the 3115 * transfer descriptor(s) and QH 3116 */ 3117 *pus = (1125); /* microseconds */ 3118 } 3119 3120 static void 3121 uhci_device_resume(struct usb_device *udev) 3122 { 3123 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3124 struct usb_xfer *xfer; 3125 struct usb_pipe_methods *methods; 3126 uhci_qh_t *qh; 3127 3128 DPRINTF("\n"); 3129 3130 USB_BUS_LOCK(udev->bus); 3131 3132 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3133 3134 if (xfer->xroot->udev == udev) { 3135 3136 methods = xfer->endpoint->methods; 3137 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3138 3139 if (methods == &uhci_device_bulk_methods) { 3140 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 3141 uhci_add_loop(sc); 3142 xfer->flags_int.bandwidth_reclaimed = 1; 3143 } 3144 if (methods == &uhci_device_ctrl_methods) { 3145 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3146 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 3147 } else { 3148 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 3149 } 3150 } 3151 if (methods == &uhci_device_intr_methods) { 3152 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3153 } 3154 } 3155 } 3156 3157 USB_BUS_UNLOCK(udev->bus); 3158 3159 return; 3160 } 3161 3162 static void 3163 uhci_device_suspend(struct usb_device *udev) 3164 { 3165 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3166 struct usb_xfer *xfer; 3167 struct usb_pipe_methods *methods; 3168 uhci_qh_t *qh; 3169 3170 DPRINTF("\n"); 3171 3172 USB_BUS_LOCK(udev->bus); 3173 3174 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3175 3176 if (xfer->xroot->udev == udev) { 3177 3178 methods = xfer->endpoint->methods; 3179 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3180 3181 if (xfer->flags_int.bandwidth_reclaimed) { 3182 xfer->flags_int.bandwidth_reclaimed = 0; 3183 uhci_rem_loop(sc); 3184 } 3185 if (methods == &uhci_device_bulk_methods) { 3186 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 3187 } 3188 if (methods == &uhci_device_ctrl_methods) { 3189 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3190 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 3191 } else { 3192 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 3193 } 3194 } 3195 if (methods == &uhci_device_intr_methods) { 3196 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3197 } 3198 } 3199 } 3200 3201 USB_BUS_UNLOCK(udev->bus); 3202 3203 return; 3204 } 3205 3206 static void 3207 uhci_set_hw_power(struct usb_bus *bus) 3208 { 3209 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3210 uint32_t flags; 3211 3212 DPRINTF("\n"); 3213 3214 USB_BUS_LOCK(bus); 3215 3216 flags = bus->hw_power_state; 3217 3218 /* 3219 * WARNING: Some FULL speed USB devices require periodic SOF 3220 * messages! If any USB devices are connected through the 3221 * UHCI, power save will be disabled! 3222 */ 3223 if (flags & (USB_HW_POWER_CONTROL | 3224 USB_HW_POWER_NON_ROOT_HUB | 3225 USB_HW_POWER_BULK | 3226 USB_HW_POWER_INTERRUPT | 3227 USB_HW_POWER_ISOC)) { 3228 DPRINTF("Some USB transfer is " 3229 "active on unit %u.\n", 3230 device_get_unit(sc->sc_bus.bdev)); 3231 uhci_restart(sc); 3232 } else { 3233 DPRINTF("Power save on unit %u.\n", 3234 device_get_unit(sc->sc_bus.bdev)); 3235 UHCICMD(sc, UHCI_CMD_MAXP); 3236 } 3237 3238 USB_BUS_UNLOCK(bus); 3239 3240 return; 3241 } 3242 3243 3244 struct usb_bus_methods uhci_bus_methods = 3245 { 3246 .endpoint_init = uhci_ep_init, 3247 .xfer_setup = uhci_xfer_setup, 3248 .xfer_unsetup = uhci_xfer_unsetup, 3249 .get_dma_delay = uhci_get_dma_delay, 3250 .device_resume = uhci_device_resume, 3251 .device_suspend = uhci_device_suspend, 3252 .set_hw_power = uhci_set_hw_power, 3253 .roothub_exec = uhci_roothub_exec, 3254 }; 3255