1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * USB Universal Host Controller driver. 33 * Handles e.g. PIIX3 and PIIX4. 34 * 35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 38 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 39 */ 40 41 #include <dev/usb/usb.h> 42 #include <dev/usb/usb_mfunc.h> 43 #include <dev/usb/usb_error.h> 44 45 #define USB_DEBUG_VAR uhcidebug 46 47 #include <dev/usb/usb_core.h> 48 #include <dev/usb/usb_debug.h> 49 #include <dev/usb/usb_busdma.h> 50 #include <dev/usb/usb_process.h> 51 #include <dev/usb/usb_transfer.h> 52 #include <dev/usb/usb_device.h> 53 #include <dev/usb/usb_hub.h> 54 #include <dev/usb/usb_util.h> 55 56 #include <dev/usb/usb_controller.h> 57 #include <dev/usb/usb_bus.h> 58 #include <dev/usb/controller/uhci.h> 59 60 #define alt_next next 61 #define UHCI_BUS2SC(bus) \ 62 ((uhci_softc_t *)(((uint8_t *)(bus)) - \ 63 ((uint8_t *)&(((uhci_softc_t *)0)->sc_bus)))) 64 65 #if USB_DEBUG 66 static int uhcidebug = 0; 67 static int uhcinoloop = 0; 68 69 SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW, 0, "USB uhci"); 70 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RW, 71 &uhcidebug, 0, "uhci debug level"); 72 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RW, 73 &uhcinoloop, 0, "uhci noloop"); 74 static void uhci_dumpregs(uhci_softc_t *sc); 75 static void uhci_dump_tds(uhci_td_t *td); 76 77 #endif 78 79 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 80 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 81 #define UWRITE1(sc, r, x) \ 82 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 83 } while (/*CONSTCOND*/0) 84 #define UWRITE2(sc, r, x) \ 85 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 86 } while (/*CONSTCOND*/0) 87 #define UWRITE4(sc, r, x) \ 88 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 89 } while (/*CONSTCOND*/0) 90 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 91 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 92 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 93 94 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 95 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 96 97 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 98 99 #define UHCI_INTR_ENDPT 1 100 101 struct uhci_mem_layout { 102 103 struct usb_page_search buf_res; 104 struct usb_page_search fix_res; 105 106 struct usb_page_cache *buf_pc; 107 struct usb_page_cache *fix_pc; 108 109 uint32_t buf_offset; 110 111 uint16_t max_frame_size; 112 }; 113 114 struct uhci_std_temp { 115 116 struct uhci_mem_layout ml; 117 uhci_td_t *td; 118 uhci_td_t *td_next; 119 uint32_t average; 120 uint32_t td_status; 121 uint32_t td_token; 122 uint32_t len; 123 uint16_t max_frame_size; 124 uint8_t shortpkt; 125 uint8_t setup_alt_next; 126 uint8_t last_frame; 127 }; 128 129 extern struct usb_bus_methods uhci_bus_methods; 130 extern struct usb_pipe_methods uhci_device_bulk_methods; 131 extern struct usb_pipe_methods uhci_device_ctrl_methods; 132 extern struct usb_pipe_methods uhci_device_intr_methods; 133 extern struct usb_pipe_methods uhci_device_isoc_methods; 134 135 static uint8_t uhci_restart(uhci_softc_t *sc); 136 static void uhci_do_poll(struct usb_bus *); 137 static void uhci_device_done(struct usb_xfer *, usb_error_t); 138 static void uhci_transfer_intr_enqueue(struct usb_xfer *); 139 static void uhci_timeout(void *); 140 static uint8_t uhci_check_transfer(struct usb_xfer *); 141 static void uhci_root_intr(uhci_softc_t *sc); 142 143 void 144 uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 145 { 146 struct uhci_softc *sc = UHCI_BUS2SC(bus); 147 uint32_t i; 148 149 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 150 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN); 151 152 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg, 153 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 154 155 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg, 156 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 157 158 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 159 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 160 161 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg, 162 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 163 164 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg, 165 sizeof(uhci_td_t), UHCI_TD_ALIGN); 166 167 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) { 168 cb(bus, sc->sc_hw.isoc_start_pc + i, 169 sc->sc_hw.isoc_start_pg + i, 170 sizeof(uhci_td_t), UHCI_TD_ALIGN); 171 } 172 173 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) { 174 cb(bus, sc->sc_hw.intr_start_pc + i, 175 sc->sc_hw.intr_start_pg + i, 176 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 177 } 178 } 179 180 static void 181 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer) 182 { 183 ml->buf_pc = xfer->frbuffers + 0; 184 ml->fix_pc = xfer->buf_fixup; 185 186 ml->buf_offset = 0; 187 188 ml->max_frame_size = xfer->max_frame_size; 189 } 190 191 static void 192 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td) 193 { 194 usb2_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res); 195 196 if (ml->buf_res.length < td->len) { 197 198 /* need to do a fixup */ 199 200 usb2_get_page(ml->fix_pc, 0, &ml->fix_res); 201 202 td->td_buffer = htole32(ml->fix_res.physaddr); 203 204 /* 205 * The UHCI driver cannot handle 206 * page crossings, so a fixup is 207 * needed: 208 * 209 * +----+----+ - - - 210 * | YYY|Y | 211 * +----+----+ - - - 212 * \ \ 213 * \ \ 214 * +----+ 215 * |YYYY| (fixup) 216 * +----+ 217 */ 218 219 if ((td->td_token & htole32(UHCI_TD_PID)) == 220 htole32(UHCI_TD_PID_IN)) { 221 td->fix_pc = ml->fix_pc; 222 usb2_pc_cpu_invalidate(ml->fix_pc); 223 224 } else { 225 td->fix_pc = NULL; 226 227 /* copy data to fixup location */ 228 229 usb2_copy_out(ml->buf_pc, ml->buf_offset, 230 ml->fix_res.buffer, td->len); 231 232 usb2_pc_cpu_flush(ml->fix_pc); 233 } 234 235 /* prepare next fixup */ 236 237 ml->fix_pc++; 238 239 } else { 240 241 td->td_buffer = htole32(ml->buf_res.physaddr); 242 td->fix_pc = NULL; 243 } 244 245 /* prepare next data location */ 246 247 ml->buf_offset += td->len; 248 } 249 250 /* 251 * Return values: 252 * 0: Success 253 * Else: Failure 254 */ 255 static uint8_t 256 uhci_restart(uhci_softc_t *sc) 257 { 258 struct usb_page_search buf_res; 259 260 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 261 262 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) { 263 DPRINTFN(2, "Already started\n"); 264 return (0); 265 } 266 267 DPRINTFN(2, "Restarting\n"); 268 269 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 270 271 /* Reload fresh base address */ 272 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr); 273 274 /* 275 * Assume 64 byte packets at frame end and start HC controller: 276 */ 277 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 278 279 /* wait 10 milliseconds */ 280 281 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 282 283 /* check that controller has started */ 284 285 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 286 DPRINTFN(2, "Failed\n"); 287 return (1); 288 } 289 return (0); 290 } 291 292 void 293 uhci_reset(uhci_softc_t *sc) 294 { 295 uint16_t n; 296 297 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 298 299 DPRINTF("resetting the HC\n"); 300 301 /* disable interrupts */ 302 303 UWRITE2(sc, UHCI_INTR, 0); 304 305 /* global reset */ 306 307 UHCICMD(sc, UHCI_CMD_GRESET); 308 309 /* wait */ 310 311 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 312 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 313 314 /* terminate all transfers */ 315 316 UHCICMD(sc, UHCI_CMD_HCRESET); 317 318 /* the reset bit goes low when the controller is done */ 319 320 n = UHCI_RESET_TIMEOUT; 321 while (n--) { 322 /* wait one millisecond */ 323 324 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 325 326 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) { 327 goto done_1; 328 } 329 } 330 331 device_printf(sc->sc_bus.bdev, 332 "controller did not reset\n"); 333 334 done_1: 335 336 n = 10; 337 while (n--) { 338 /* wait one millisecond */ 339 340 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 341 342 /* check if HC is stopped */ 343 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 344 goto done_2; 345 } 346 } 347 348 device_printf(sc->sc_bus.bdev, 349 "controller did not stop\n"); 350 351 done_2: 352 353 /* reload the configuration */ 354 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum); 355 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof); 356 357 USB_BUS_UNLOCK(&sc->sc_bus); 358 359 /* stop root interrupt */ 360 usb2_callout_drain(&sc->sc_root_intr); 361 362 USB_BUS_LOCK(&sc->sc_bus); 363 } 364 365 static void 366 uhci_start(uhci_softc_t *sc) 367 { 368 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 369 370 DPRINTFN(2, "enabling\n"); 371 372 /* enable interrupts */ 373 374 UWRITE2(sc, UHCI_INTR, 375 (UHCI_INTR_TOCRCIE | 376 UHCI_INTR_RIE | 377 UHCI_INTR_IOCE | 378 UHCI_INTR_SPIE)); 379 380 if (uhci_restart(sc)) { 381 device_printf(sc->sc_bus.bdev, 382 "cannot start HC controller\n"); 383 } 384 385 /* start root interrupt */ 386 uhci_root_intr(sc); 387 } 388 389 static struct uhci_qh * 390 uhci_init_qh(struct usb_page_cache *pc) 391 { 392 struct usb_page_search buf_res; 393 struct uhci_qh *qh; 394 395 usb2_get_page(pc, 0, &buf_res); 396 397 qh = buf_res.buffer; 398 399 qh->qh_self = 400 htole32(buf_res.physaddr) | 401 htole32(UHCI_PTR_QH); 402 403 qh->page_cache = pc; 404 405 return (qh); 406 } 407 408 static struct uhci_td * 409 uhci_init_td(struct usb_page_cache *pc) 410 { 411 struct usb_page_search buf_res; 412 struct uhci_td *td; 413 414 usb2_get_page(pc, 0, &buf_res); 415 416 td = buf_res.buffer; 417 418 td->td_self = 419 htole32(buf_res.physaddr) | 420 htole32(UHCI_PTR_TD); 421 422 td->page_cache = pc; 423 424 return (td); 425 } 426 427 usb_error_t 428 uhci_init(uhci_softc_t *sc) 429 { 430 uint16_t bit; 431 uint16_t x; 432 uint16_t y; 433 434 DPRINTF("start\n"); 435 436 usb2_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_mtx, 0); 437 438 #if USB_DEBUG 439 if (uhcidebug > 2) { 440 uhci_dumpregs(sc); 441 } 442 #endif 443 sc->sc_saved_sof = 0x40; /* default value */ 444 sc->sc_saved_frnum = 0; /* default frame number */ 445 446 /* 447 * Setup QH's 448 */ 449 sc->sc_ls_ctl_p_last = 450 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc); 451 452 sc->sc_fs_ctl_p_last = 453 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc); 454 455 sc->sc_bulk_p_last = 456 uhci_init_qh(&sc->sc_hw.bulk_start_pc); 457 #if 0 458 sc->sc_reclaim_qh_p = 459 sc->sc_fs_ctl_p_last; 460 #else 461 /* setup reclaim looping point */ 462 sc->sc_reclaim_qh_p = 463 sc->sc_bulk_p_last; 464 #endif 465 466 sc->sc_last_qh_p = 467 uhci_init_qh(&sc->sc_hw.last_qh_pc); 468 469 sc->sc_last_td_p = 470 uhci_init_td(&sc->sc_hw.last_td_pc); 471 472 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 473 sc->sc_isoc_p_last[x] = 474 uhci_init_td(sc->sc_hw.isoc_start_pc + x); 475 } 476 477 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) { 478 sc->sc_intr_p_last[x] = 479 uhci_init_qh(sc->sc_hw.intr_start_pc + x); 480 } 481 482 /* 483 * the QHs are arranged to give poll intervals that are 484 * powers of 2 times 1ms 485 */ 486 bit = UHCI_IFRAMELIST_COUNT / 2; 487 while (bit) { 488 x = bit; 489 while (x & bit) { 490 uhci_qh_t *qh_x; 491 uhci_qh_t *qh_y; 492 493 y = (x ^ bit) | (bit / 2); 494 495 /* 496 * the next QH has half the poll interval 497 */ 498 qh_x = sc->sc_intr_p_last[x]; 499 qh_y = sc->sc_intr_p_last[y]; 500 501 qh_x->h_next = NULL; 502 qh_x->qh_h_next = qh_y->qh_self; 503 qh_x->e_next = NULL; 504 qh_x->qh_e_next = htole32(UHCI_PTR_T); 505 x++; 506 } 507 bit >>= 1; 508 } 509 510 if (1) { 511 uhci_qh_t *qh_ls; 512 uhci_qh_t *qh_intr; 513 514 qh_ls = sc->sc_ls_ctl_p_last; 515 qh_intr = sc->sc_intr_p_last[0]; 516 517 /* start QH for interrupt traffic */ 518 qh_intr->h_next = qh_ls; 519 qh_intr->qh_h_next = qh_ls->qh_self; 520 qh_intr->e_next = 0; 521 qh_intr->qh_e_next = htole32(UHCI_PTR_T); 522 } 523 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 524 525 uhci_td_t *td_x; 526 uhci_qh_t *qh_intr; 527 528 td_x = sc->sc_isoc_p_last[x]; 529 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)]; 530 531 /* start TD for isochronous traffic */ 532 td_x->next = NULL; 533 td_x->td_next = qh_intr->qh_self; 534 td_x->td_status = htole32(UHCI_TD_IOS); 535 td_x->td_token = htole32(0); 536 td_x->td_buffer = htole32(0); 537 } 538 539 if (1) { 540 uhci_qh_t *qh_ls; 541 uhci_qh_t *qh_fs; 542 543 qh_ls = sc->sc_ls_ctl_p_last; 544 qh_fs = sc->sc_fs_ctl_p_last; 545 546 /* start QH where low speed control traffic will be queued */ 547 qh_ls->h_next = qh_fs; 548 qh_ls->qh_h_next = qh_fs->qh_self; 549 qh_ls->e_next = 0; 550 qh_ls->qh_e_next = htole32(UHCI_PTR_T); 551 } 552 if (1) { 553 uhci_qh_t *qh_ctl; 554 uhci_qh_t *qh_blk; 555 uhci_qh_t *qh_lst; 556 uhci_td_t *td_lst; 557 558 qh_ctl = sc->sc_fs_ctl_p_last; 559 qh_blk = sc->sc_bulk_p_last; 560 561 /* start QH where full speed control traffic will be queued */ 562 qh_ctl->h_next = qh_blk; 563 qh_ctl->qh_h_next = qh_blk->qh_self; 564 qh_ctl->e_next = 0; 565 qh_ctl->qh_e_next = htole32(UHCI_PTR_T); 566 567 qh_lst = sc->sc_last_qh_p; 568 569 /* start QH where bulk traffic will be queued */ 570 qh_blk->h_next = qh_lst; 571 qh_blk->qh_h_next = qh_lst->qh_self; 572 qh_blk->e_next = 0; 573 qh_blk->qh_e_next = htole32(UHCI_PTR_T); 574 575 td_lst = sc->sc_last_td_p; 576 577 /* end QH which is used for looping the QHs */ 578 qh_lst->h_next = 0; 579 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */ 580 qh_lst->e_next = td_lst; 581 qh_lst->qh_e_next = td_lst->td_self; 582 583 /* 584 * end TD which hangs from the last QH, to avoid a bug in the PIIX 585 * that makes it run berserk otherwise 586 */ 587 td_lst->next = 0; 588 td_lst->td_next = htole32(UHCI_PTR_T); 589 td_lst->td_status = htole32(0); /* inactive */ 590 td_lst->td_token = htole32(0); 591 td_lst->td_buffer = htole32(0); 592 } 593 if (1) { 594 struct usb_page_search buf_res; 595 uint32_t *pframes; 596 597 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 598 599 pframes = buf_res.buffer; 600 601 602 /* 603 * Setup UHCI framelist 604 * 605 * Execution order: 606 * 607 * pframes -> full speed isochronous -> interrupt QH's -> low 608 * speed control -> full speed control -> bulk transfers 609 * 610 */ 611 612 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) { 613 pframes[x] = 614 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self; 615 } 616 } 617 /* flush all cache into memory */ 618 619 usb2_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc); 620 621 /* set up the bus struct */ 622 sc->sc_bus.methods = &uhci_bus_methods; 623 624 USB_BUS_LOCK(&sc->sc_bus); 625 /* reset the controller */ 626 uhci_reset(sc); 627 628 /* start the controller */ 629 uhci_start(sc); 630 USB_BUS_UNLOCK(&sc->sc_bus); 631 632 /* catch lost interrupts */ 633 uhci_do_poll(&sc->sc_bus); 634 635 return (0); 636 } 637 638 /* NOTE: suspend/resume is called from 639 * interrupt context and cannot sleep! 640 */ 641 642 void 643 uhci_suspend(uhci_softc_t *sc) 644 { 645 USB_BUS_LOCK(&sc->sc_bus); 646 647 #if USB_DEBUG 648 if (uhcidebug > 2) { 649 uhci_dumpregs(sc); 650 } 651 #endif 652 /* save some state if BIOS doesn't */ 653 654 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM); 655 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF); 656 657 /* stop the controller */ 658 659 uhci_reset(sc); 660 661 /* enter global suspend */ 662 663 UHCICMD(sc, UHCI_CMD_EGSM); 664 665 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 666 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 667 668 USB_BUS_UNLOCK(&sc->sc_bus); 669 } 670 671 void 672 uhci_resume(uhci_softc_t *sc) 673 { 674 USB_BUS_LOCK(&sc->sc_bus); 675 676 /* reset the controller */ 677 678 uhci_reset(sc); 679 680 /* force global resume */ 681 682 UHCICMD(sc, UHCI_CMD_FGR); 683 684 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 685 USB_MS_TO_TICKS(USB_RESUME_DELAY)); 686 687 /* and start traffic again */ 688 689 uhci_start(sc); 690 691 #if USB_DEBUG 692 if (uhcidebug > 2) { 693 uhci_dumpregs(sc); 694 } 695 #endif 696 697 USB_BUS_UNLOCK(&sc->sc_bus); 698 699 /* catch lost interrupts */ 700 uhci_do_poll(&sc->sc_bus); 701 } 702 703 #if USB_DEBUG 704 static void 705 uhci_dumpregs(uhci_softc_t *sc) 706 { 707 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 708 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 709 device_get_nameunit(sc->sc_bus.bdev), 710 UREAD2(sc, UHCI_CMD), 711 UREAD2(sc, UHCI_STS), 712 UREAD2(sc, UHCI_INTR), 713 UREAD2(sc, UHCI_FRNUM), 714 UREAD4(sc, UHCI_FLBASEADDR), 715 UREAD1(sc, UHCI_SOF), 716 UREAD2(sc, UHCI_PORTSC1), 717 UREAD2(sc, UHCI_PORTSC2)); 718 } 719 720 static uint8_t 721 uhci_dump_td(uhci_td_t *p) 722 { 723 uint32_t td_next; 724 uint32_t td_status; 725 uint32_t td_token; 726 uint8_t temp; 727 728 usb2_pc_cpu_invalidate(p->page_cache); 729 730 td_next = le32toh(p->td_next); 731 td_status = le32toh(p->td_status); 732 td_token = le32toh(p->td_token); 733 734 /* 735 * Check whether the link pointer in this TD marks the link pointer 736 * as end of queue: 737 */ 738 temp = ((td_next & UHCI_PTR_T) || (td_next == 0)); 739 740 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x " 741 "token=0x%08x buffer=0x%08x\n", 742 p, 743 le32toh(p->td_self), 744 td_next, 745 td_status, 746 td_token, 747 le32toh(p->td_buffer)); 748 749 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x," 750 "addr=%d,endpt=%d,D=%d,maxlen=%d\n", 751 p, 752 (td_next & 1) ? "-T" : "", 753 (td_next & 2) ? "-Q" : "", 754 (td_next & 4) ? "-VF" : "", 755 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "", 756 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "", 757 (td_status & UHCI_TD_NAK) ? "-NAK" : "", 758 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "", 759 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "", 760 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "", 761 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "", 762 (td_status & UHCI_TD_IOC) ? "-IOC" : "", 763 (td_status & UHCI_TD_IOS) ? "-IOS" : "", 764 (td_status & UHCI_TD_LS) ? "-LS" : "", 765 (td_status & UHCI_TD_SPD) ? "-SPD" : "", 766 UHCI_TD_GET_ERRCNT(td_status), 767 UHCI_TD_GET_ACTLEN(td_status), 768 UHCI_TD_GET_PID(td_token), 769 UHCI_TD_GET_DEVADDR(td_token), 770 UHCI_TD_GET_ENDPT(td_token), 771 UHCI_TD_GET_DT(td_token), 772 UHCI_TD_GET_MAXLEN(td_token)); 773 774 return (temp); 775 } 776 777 static uint8_t 778 uhci_dump_qh(uhci_qh_t *sqh) 779 { 780 uint8_t temp; 781 uint32_t qh_h_next; 782 uint32_t qh_e_next; 783 784 usb2_pc_cpu_invalidate(sqh->page_cache); 785 786 qh_h_next = le32toh(sqh->qh_h_next); 787 qh_e_next = le32toh(sqh->qh_e_next); 788 789 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh, 790 le32toh(sqh->qh_self), qh_h_next, qh_e_next); 791 792 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) | 793 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0)); 794 795 return (temp); 796 } 797 798 static void 799 uhci_dump_all(uhci_softc_t *sc) 800 { 801 uhci_dumpregs(sc); 802 uhci_dump_qh(sc->sc_ls_ctl_p_last); 803 uhci_dump_qh(sc->sc_fs_ctl_p_last); 804 uhci_dump_qh(sc->sc_bulk_p_last); 805 uhci_dump_qh(sc->sc_last_qh_p); 806 } 807 808 static void 809 uhci_dump_qhs(uhci_qh_t *sqh) 810 { 811 uint8_t temp; 812 813 temp = uhci_dump_qh(sqh); 814 815 /* 816 * uhci_dump_qhs displays all the QHs and TDs from the given QH 817 * onwards Traverses sideways first, then down. 818 * 819 * QH1 QH2 No QH TD2.1 TD2.2 TD1.1 etc. 820 * 821 * TD2.x being the TDs queued at QH2 and QH1 being referenced from QH1. 822 */ 823 824 if (temp & 1) 825 uhci_dump_qhs(sqh->h_next); 826 else 827 DPRINTF("No QH\n"); 828 829 if (temp & 2) 830 uhci_dump_tds(sqh->e_next); 831 else 832 DPRINTF("No TD\n"); 833 } 834 835 static void 836 uhci_dump_tds(uhci_td_t *td) 837 { 838 for (; 839 td != NULL; 840 td = td->obj_next) { 841 if (uhci_dump_td(td)) { 842 break; 843 } 844 } 845 } 846 847 #endif 848 849 /* 850 * Let the last QH loop back to the full speed control transfer QH. 851 * This is what intel calls "bandwidth reclamation" and improves 852 * USB performance a lot for some devices. 853 * If we are already looping, just count it. 854 */ 855 static void 856 uhci_add_loop(uhci_softc_t *sc) 857 { 858 struct uhci_qh *qh_lst; 859 struct uhci_qh *qh_rec; 860 861 #if USB_DEBUG 862 if (uhcinoloop) { 863 return; 864 } 865 #endif 866 if (++(sc->sc_loops) == 1) { 867 DPRINTFN(6, "add\n"); 868 869 qh_lst = sc->sc_last_qh_p; 870 qh_rec = sc->sc_reclaim_qh_p; 871 872 /* NOTE: we don't loop back the soft pointer */ 873 874 qh_lst->qh_h_next = qh_rec->qh_self; 875 usb2_pc_cpu_flush(qh_lst->page_cache); 876 } 877 } 878 879 static void 880 uhci_rem_loop(uhci_softc_t *sc) 881 { 882 struct uhci_qh *qh_lst; 883 884 #if USB_DEBUG 885 if (uhcinoloop) { 886 return; 887 } 888 #endif 889 if (--(sc->sc_loops) == 0) { 890 DPRINTFN(6, "remove\n"); 891 892 qh_lst = sc->sc_last_qh_p; 893 qh_lst->qh_h_next = htole32(UHCI_PTR_T); 894 usb2_pc_cpu_flush(qh_lst->page_cache); 895 } 896 } 897 898 static void 899 uhci_transfer_intr_enqueue(struct usb_xfer *xfer) 900 { 901 /* check for early completion */ 902 if (uhci_check_transfer(xfer)) { 903 return; 904 } 905 /* put transfer on interrupt queue */ 906 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 907 908 /* start timeout, if any */ 909 if (xfer->timeout != 0) { 910 usb2_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout); 911 } 912 } 913 914 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last) 915 static uhci_td_t * 916 _uhci_append_td(uhci_td_t *std, uhci_td_t *last) 917 { 918 DPRINTFN(11, "%p to %p\n", std, last); 919 920 /* (sc->sc_bus.mtx) must be locked */ 921 922 std->next = last->next; 923 std->td_next = last->td_next; 924 925 std->prev = last; 926 927 usb2_pc_cpu_flush(std->page_cache); 928 929 /* 930 * the last->next->prev is never followed: std->next->prev = std; 931 */ 932 last->next = std; 933 last->td_next = std->td_self; 934 935 usb2_pc_cpu_flush(last->page_cache); 936 937 return (std); 938 } 939 940 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last) 941 static uhci_qh_t * 942 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last) 943 { 944 DPRINTFN(11, "%p to %p\n", sqh, last); 945 946 if (sqh->h_prev != NULL) { 947 /* should not happen */ 948 DPRINTFN(0, "QH already linked!\n"); 949 return (last); 950 } 951 /* (sc->sc_bus.mtx) must be locked */ 952 953 sqh->h_next = last->h_next; 954 sqh->qh_h_next = last->qh_h_next; 955 956 sqh->h_prev = last; 957 958 usb2_pc_cpu_flush(sqh->page_cache); 959 960 /* 961 * The "last->h_next->h_prev" is never followed: 962 * 963 * "sqh->h_next->h_prev" = sqh; 964 */ 965 966 last->h_next = sqh; 967 last->qh_h_next = sqh->qh_self; 968 969 usb2_pc_cpu_flush(last->page_cache); 970 971 return (sqh); 972 } 973 974 /**/ 975 976 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last) 977 static uhci_td_t * 978 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last) 979 { 980 DPRINTFN(11, "%p from %p\n", std, last); 981 982 /* (sc->sc_bus.mtx) must be locked */ 983 984 std->prev->next = std->next; 985 std->prev->td_next = std->td_next; 986 987 usb2_pc_cpu_flush(std->prev->page_cache); 988 989 if (std->next) { 990 std->next->prev = std->prev; 991 usb2_pc_cpu_flush(std->next->page_cache); 992 } 993 return ((last == std) ? std->prev : last); 994 } 995 996 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last) 997 static uhci_qh_t * 998 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last) 999 { 1000 DPRINTFN(11, "%p from %p\n", sqh, last); 1001 1002 /* (sc->sc_bus.mtx) must be locked */ 1003 1004 /* only remove if not removed from a queue */ 1005 if (sqh->h_prev) { 1006 1007 sqh->h_prev->h_next = sqh->h_next; 1008 sqh->h_prev->qh_h_next = sqh->qh_h_next; 1009 1010 usb2_pc_cpu_flush(sqh->h_prev->page_cache); 1011 1012 if (sqh->h_next) { 1013 sqh->h_next->h_prev = sqh->h_prev; 1014 usb2_pc_cpu_flush(sqh->h_next->page_cache); 1015 } 1016 last = ((last == sqh) ? sqh->h_prev : last); 1017 1018 sqh->h_prev = 0; 1019 1020 usb2_pc_cpu_flush(sqh->page_cache); 1021 } 1022 return (last); 1023 } 1024 1025 static void 1026 uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer) 1027 { 1028 struct usb_page_search res; 1029 uint32_t nframes = xfer->nframes; 1030 uint32_t status; 1031 uint32_t offset = 0; 1032 uint32_t *plen = xfer->frlengths; 1033 uint16_t len = 0; 1034 uhci_td_t *td = xfer->td_transfer_first; 1035 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos]; 1036 1037 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1038 xfer, xfer->pipe); 1039 1040 /* sync any DMA memory before doing fixups */ 1041 1042 usb2_bdma_post_sync(xfer); 1043 1044 while (nframes--) { 1045 if (td == NULL) { 1046 panic("%s:%d: out of TD's\n", 1047 __FUNCTION__, __LINE__); 1048 } 1049 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 1050 pp_last = &sc->sc_isoc_p_last[0]; 1051 } 1052 #if USB_DEBUG 1053 if (uhcidebug > 5) { 1054 DPRINTF("isoc TD\n"); 1055 uhci_dump_td(td); 1056 } 1057 #endif 1058 usb2_pc_cpu_invalidate(td->page_cache); 1059 status = le32toh(td->td_status); 1060 1061 len = UHCI_TD_GET_ACTLEN(status); 1062 1063 if (len > *plen) { 1064 len = *plen; 1065 } 1066 if (td->fix_pc) { 1067 1068 usb2_get_page(td->fix_pc, 0, &res); 1069 1070 /* copy data from fixup location to real location */ 1071 1072 usb2_pc_cpu_invalidate(td->fix_pc); 1073 1074 usb2_copy_in(xfer->frbuffers, offset, 1075 res.buffer, len); 1076 } 1077 offset += *plen; 1078 1079 *plen = len; 1080 1081 /* remove TD from schedule */ 1082 UHCI_REMOVE_TD(td, *pp_last); 1083 1084 pp_last++; 1085 plen++; 1086 td = td->obj_next; 1087 } 1088 1089 xfer->aframes = xfer->nframes; 1090 } 1091 1092 static usb_error_t 1093 uhci_non_isoc_done_sub(struct usb_xfer *xfer) 1094 { 1095 struct usb_page_search res; 1096 uhci_td_t *td; 1097 uhci_td_t *td_alt_next; 1098 uint32_t status; 1099 uint32_t token; 1100 uint16_t len; 1101 1102 td = xfer->td_transfer_cache; 1103 td_alt_next = td->alt_next; 1104 1105 if (xfer->aframes != xfer->nframes) { 1106 xfer->frlengths[xfer->aframes] = 0; 1107 } 1108 while (1) { 1109 1110 usb2_pc_cpu_invalidate(td->page_cache); 1111 status = le32toh(td->td_status); 1112 token = le32toh(td->td_token); 1113 1114 /* 1115 * Verify the status and add 1116 * up the actual length: 1117 */ 1118 1119 len = UHCI_TD_GET_ACTLEN(status); 1120 if (len > td->len) { 1121 /* should not happen */ 1122 DPRINTF("Invalid status length, " 1123 "0x%04x/0x%04x bytes\n", len, td->len); 1124 status |= UHCI_TD_STALLED; 1125 1126 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) { 1127 1128 if (td->fix_pc) { 1129 1130 usb2_get_page(td->fix_pc, 0, &res); 1131 1132 /* 1133 * copy data from fixup location to real 1134 * location 1135 */ 1136 1137 usb2_pc_cpu_invalidate(td->fix_pc); 1138 1139 usb2_copy_in(xfer->frbuffers + xfer->aframes, 1140 xfer->frlengths[xfer->aframes], res.buffer, len); 1141 } 1142 /* update actual length */ 1143 1144 xfer->frlengths[xfer->aframes] += len; 1145 } 1146 /* Check for last transfer */ 1147 if (((void *)td) == xfer->td_transfer_last) { 1148 td = NULL; 1149 break; 1150 } 1151 if (status & UHCI_TD_STALLED) { 1152 /* the transfer is finished */ 1153 td = NULL; 1154 break; 1155 } 1156 /* Check for short transfer */ 1157 if (len != td->len) { 1158 if (xfer->flags_int.short_frames_ok) { 1159 /* follow alt next */ 1160 td = td->alt_next; 1161 } else { 1162 /* the transfer is finished */ 1163 td = NULL; 1164 } 1165 break; 1166 } 1167 td = td->obj_next; 1168 1169 if (td->alt_next != td_alt_next) { 1170 /* this USB frame is complete */ 1171 break; 1172 } 1173 } 1174 1175 /* update transfer cache */ 1176 1177 xfer->td_transfer_cache = td; 1178 1179 /* update data toggle */ 1180 1181 xfer->pipe->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1; 1182 1183 #if USB_DEBUG 1184 if (status & UHCI_TD_ERROR) { 1185 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x " 1186 "status=%s%s%s%s%s%s%s%s%s%s%s\n", 1187 xfer->address, xfer->endpoint, xfer->aframes, 1188 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "", 1189 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "", 1190 (status & UHCI_TD_NAK) ? "[NAK]" : "", 1191 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "", 1192 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "", 1193 (status & UHCI_TD_STALLED) ? "[STALLED]" : "", 1194 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1195 (status & UHCI_TD_IOC) ? "[IOC]" : "", 1196 (status & UHCI_TD_IOS) ? "[IOS]" : "", 1197 (status & UHCI_TD_LS) ? "[LS]" : "", 1198 (status & UHCI_TD_SPD) ? "[SPD]" : ""); 1199 } 1200 #endif 1201 return (status & UHCI_TD_STALLED) ? 1202 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION; 1203 } 1204 1205 static void 1206 uhci_non_isoc_done(struct usb_xfer *xfer) 1207 { 1208 usb_error_t err = 0; 1209 1210 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1211 xfer, xfer->pipe); 1212 1213 #if USB_DEBUG 1214 if (uhcidebug > 10) { 1215 uhci_dump_tds(xfer->td_transfer_first); 1216 } 1217 #endif 1218 1219 /* sync any DMA memory before doing fixups */ 1220 1221 usb2_bdma_post_sync(xfer); 1222 1223 /* reset scanner */ 1224 1225 xfer->td_transfer_cache = xfer->td_transfer_first; 1226 1227 if (xfer->flags_int.control_xfr) { 1228 if (xfer->flags_int.control_hdr) { 1229 1230 err = uhci_non_isoc_done_sub(xfer); 1231 } 1232 xfer->aframes = 1; 1233 1234 if (xfer->td_transfer_cache == NULL) { 1235 goto done; 1236 } 1237 } 1238 while (xfer->aframes != xfer->nframes) { 1239 1240 err = uhci_non_isoc_done_sub(xfer); 1241 xfer->aframes++; 1242 1243 if (xfer->td_transfer_cache == NULL) { 1244 goto done; 1245 } 1246 } 1247 1248 if (xfer->flags_int.control_xfr && 1249 !xfer->flags_int.control_act) { 1250 1251 err = uhci_non_isoc_done_sub(xfer); 1252 } 1253 done: 1254 uhci_device_done(xfer, err); 1255 } 1256 1257 /*------------------------------------------------------------------------* 1258 * uhci_check_transfer_sub 1259 * 1260 * The main purpose of this function is to update the data-toggle 1261 * in case it is wrong. 1262 *------------------------------------------------------------------------*/ 1263 static void 1264 uhci_check_transfer_sub(struct usb_xfer *xfer) 1265 { 1266 uhci_qh_t *qh; 1267 uhci_td_t *td; 1268 uhci_td_t *td_alt_next; 1269 1270 uint32_t td_token; 1271 uint32_t td_self; 1272 1273 td = xfer->td_transfer_cache; 1274 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1275 1276 td_token = td->obj_next->td_token; 1277 td = td->alt_next; 1278 xfer->td_transfer_cache = td; 1279 td_self = td->td_self; 1280 td_alt_next = td->alt_next; 1281 1282 if (xfer->flags_int.control_xfr) 1283 goto skip; /* don't touch the DT value! */ 1284 1285 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1)))) 1286 goto skip; /* data toggle has correct value */ 1287 1288 /* 1289 * The data toggle is wrong and we need to toggle it ! 1290 */ 1291 while (1) { 1292 1293 td->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1294 usb2_pc_cpu_flush(td->page_cache); 1295 1296 if (td == xfer->td_transfer_last) { 1297 /* last transfer */ 1298 break; 1299 } 1300 td = td->obj_next; 1301 1302 if (td->alt_next != td_alt_next) { 1303 /* next frame */ 1304 break; 1305 } 1306 } 1307 skip: 1308 1309 /* update the QH */ 1310 qh->qh_e_next = td_self; 1311 usb2_pc_cpu_flush(qh->page_cache); 1312 1313 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1314 } 1315 1316 /*------------------------------------------------------------------------* 1317 * uhci_check_transfer 1318 * 1319 * Return values: 1320 * 0: USB transfer is not finished 1321 * Else: USB transfer is finished 1322 *------------------------------------------------------------------------*/ 1323 static uint8_t 1324 uhci_check_transfer(struct usb_xfer *xfer) 1325 { 1326 uint32_t status; 1327 uint32_t token; 1328 uhci_td_t *td; 1329 1330 DPRINTFN(16, "xfer=%p checking transfer\n", xfer); 1331 1332 if (xfer->pipe->methods == &uhci_device_isoc_methods) { 1333 /* isochronous transfer */ 1334 1335 td = xfer->td_transfer_last; 1336 1337 usb2_pc_cpu_invalidate(td->page_cache); 1338 status = le32toh(td->td_status); 1339 1340 /* check also if the first is complete */ 1341 1342 td = xfer->td_transfer_first; 1343 1344 usb2_pc_cpu_invalidate(td->page_cache); 1345 status |= le32toh(td->td_status); 1346 1347 if (!(status & UHCI_TD_ACTIVE)) { 1348 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1349 goto transferred; 1350 } 1351 } else { 1352 /* non-isochronous transfer */ 1353 1354 /* 1355 * check whether there is an error somewhere 1356 * in the middle, or whether there was a short 1357 * packet (SPD and not ACTIVE) 1358 */ 1359 td = xfer->td_transfer_cache; 1360 1361 while (1) { 1362 usb2_pc_cpu_invalidate(td->page_cache); 1363 status = le32toh(td->td_status); 1364 token = le32toh(td->td_token); 1365 1366 /* 1367 * if there is an active TD the transfer isn't done 1368 */ 1369 if (status & UHCI_TD_ACTIVE) { 1370 /* update cache */ 1371 xfer->td_transfer_cache = td; 1372 goto done; 1373 } 1374 /* 1375 * last transfer descriptor makes the transfer done 1376 */ 1377 if (((void *)td) == xfer->td_transfer_last) { 1378 break; 1379 } 1380 /* 1381 * any kind of error makes the transfer done 1382 */ 1383 if (status & UHCI_TD_STALLED) { 1384 break; 1385 } 1386 /* 1387 * check if we reached the last packet 1388 * or if there is a short packet: 1389 */ 1390 if ((td->td_next == htole32(UHCI_PTR_T)) || 1391 (UHCI_TD_GET_ACTLEN(status) < td->len)) { 1392 1393 if (xfer->flags_int.short_frames_ok) { 1394 /* follow alt next */ 1395 if (td->alt_next) { 1396 /* update cache */ 1397 xfer->td_transfer_cache = td; 1398 uhci_check_transfer_sub(xfer); 1399 goto done; 1400 } 1401 } 1402 /* transfer is done */ 1403 break; 1404 } 1405 td = td->obj_next; 1406 } 1407 uhci_non_isoc_done(xfer); 1408 goto transferred; 1409 } 1410 1411 done: 1412 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1413 return (0); 1414 1415 transferred: 1416 return (1); 1417 } 1418 1419 static void 1420 uhci_interrupt_poll(uhci_softc_t *sc) 1421 { 1422 struct usb_xfer *xfer; 1423 1424 repeat: 1425 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1426 /* 1427 * check if transfer is transferred 1428 */ 1429 if (uhci_check_transfer(xfer)) { 1430 /* queue has been modified */ 1431 goto repeat; 1432 } 1433 } 1434 } 1435 1436 /*------------------------------------------------------------------------* 1437 * uhci_interrupt - UHCI interrupt handler 1438 * 1439 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1440 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1441 * is present ! 1442 *------------------------------------------------------------------------*/ 1443 void 1444 uhci_interrupt(uhci_softc_t *sc) 1445 { 1446 uint32_t status; 1447 1448 USB_BUS_LOCK(&sc->sc_bus); 1449 1450 DPRINTFN(16, "real interrupt\n"); 1451 1452 #if USB_DEBUG 1453 if (uhcidebug > 15) { 1454 uhci_dumpregs(sc); 1455 } 1456 #endif 1457 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1458 if (status == 0) { 1459 /* the interrupt was not for us */ 1460 goto done; 1461 } 1462 if (status & (UHCI_STS_RD | UHCI_STS_HSE | 1463 UHCI_STS_HCPE | UHCI_STS_HCH)) { 1464 1465 if (status & UHCI_STS_RD) { 1466 #if USB_DEBUG 1467 printf("%s: resume detect\n", 1468 __FUNCTION__); 1469 #endif 1470 } 1471 if (status & UHCI_STS_HSE) { 1472 printf("%s: host system error\n", 1473 __FUNCTION__); 1474 } 1475 if (status & UHCI_STS_HCPE) { 1476 printf("%s: host controller process error\n", 1477 __FUNCTION__); 1478 } 1479 if (status & UHCI_STS_HCH) { 1480 /* no acknowledge needed */ 1481 DPRINTF("%s: host controller halted\n", 1482 __FUNCTION__); 1483 #if USB_DEBUG 1484 if (uhcidebug > 0) { 1485 uhci_dump_all(sc); 1486 } 1487 #endif 1488 } 1489 } 1490 /* get acknowledge bits */ 1491 status &= (UHCI_STS_USBINT | 1492 UHCI_STS_USBEI | 1493 UHCI_STS_RD | 1494 UHCI_STS_HSE | 1495 UHCI_STS_HCPE); 1496 1497 if (status == 0) { 1498 /* nothing to acknowledge */ 1499 goto done; 1500 } 1501 /* acknowledge interrupts */ 1502 UWRITE2(sc, UHCI_STS, status); 1503 1504 /* poll all the USB transfers */ 1505 uhci_interrupt_poll(sc); 1506 1507 done: 1508 USB_BUS_UNLOCK(&sc->sc_bus); 1509 } 1510 1511 /* 1512 * called when a request does not complete 1513 */ 1514 static void 1515 uhci_timeout(void *arg) 1516 { 1517 struct usb_xfer *xfer = arg; 1518 1519 DPRINTF("xfer=%p\n", xfer); 1520 1521 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1522 1523 /* transfer is transferred */ 1524 uhci_device_done(xfer, USB_ERR_TIMEOUT); 1525 } 1526 1527 static void 1528 uhci_do_poll(struct usb_bus *bus) 1529 { 1530 struct uhci_softc *sc = UHCI_BUS2SC(bus); 1531 1532 USB_BUS_LOCK(&sc->sc_bus); 1533 uhci_interrupt_poll(sc); 1534 USB_BUS_UNLOCK(&sc->sc_bus); 1535 } 1536 1537 static void 1538 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp) 1539 { 1540 uhci_td_t *td; 1541 uhci_td_t *td_next; 1542 uhci_td_t *td_alt_next; 1543 uint32_t average; 1544 uint32_t len_old; 1545 uint8_t shortpkt_old; 1546 uint8_t precompute; 1547 1548 td_alt_next = NULL; 1549 shortpkt_old = temp->shortpkt; 1550 len_old = temp->len; 1551 precompute = 1; 1552 1553 /* software is used to detect short incoming transfers */ 1554 1555 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) { 1556 temp->td_status |= htole32(UHCI_TD_SPD); 1557 } else { 1558 temp->td_status &= ~htole32(UHCI_TD_SPD); 1559 } 1560 1561 temp->ml.buf_offset = 0; 1562 1563 restart: 1564 1565 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1566 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average)); 1567 1568 td = temp->td; 1569 td_next = temp->td_next; 1570 1571 while (1) { 1572 1573 if (temp->len == 0) { 1574 1575 if (temp->shortpkt) { 1576 break; 1577 } 1578 /* send a Zero Length Packet, ZLP, last */ 1579 1580 temp->shortpkt = 1; 1581 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0)); 1582 average = 0; 1583 1584 } else { 1585 1586 average = temp->average; 1587 1588 if (temp->len < average) { 1589 temp->shortpkt = 1; 1590 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1591 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len)); 1592 average = temp->len; 1593 } 1594 } 1595 1596 if (td_next == NULL) { 1597 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__); 1598 } 1599 /* get next TD */ 1600 1601 td = td_next; 1602 td_next = td->obj_next; 1603 1604 /* check if we are pre-computing */ 1605 1606 if (precompute) { 1607 1608 /* update remaining length */ 1609 1610 temp->len -= average; 1611 1612 continue; 1613 } 1614 /* fill out current TD */ 1615 1616 td->td_status = temp->td_status; 1617 td->td_token = temp->td_token; 1618 1619 /* update data toggle */ 1620 1621 temp->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1622 1623 if (average == 0) { 1624 1625 td->len = 0; 1626 td->td_buffer = 0; 1627 td->fix_pc = NULL; 1628 1629 } else { 1630 1631 /* update remaining length */ 1632 1633 temp->len -= average; 1634 1635 td->len = average; 1636 1637 /* fill out buffer pointer and do fixup, if any */ 1638 1639 uhci_mem_layout_fixup(&temp->ml, td); 1640 } 1641 1642 td->alt_next = td_alt_next; 1643 1644 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1645 /* we need to receive these frames one by one ! */ 1646 td->td_status |= htole32(UHCI_TD_IOC); 1647 td->td_next = htole32(UHCI_PTR_T); 1648 } else { 1649 if (td_next) { 1650 /* link the current TD with the next one */ 1651 td->td_next = td_next->td_self; 1652 } 1653 } 1654 1655 usb2_pc_cpu_flush(td->page_cache); 1656 } 1657 1658 if (precompute) { 1659 precompute = 0; 1660 1661 /* setup alt next pointer, if any */ 1662 if (temp->last_frame) { 1663 td_alt_next = NULL; 1664 } else { 1665 /* we use this field internally */ 1666 td_alt_next = td_next; 1667 } 1668 1669 /* restore */ 1670 temp->shortpkt = shortpkt_old; 1671 temp->len = len_old; 1672 goto restart; 1673 } 1674 temp->td = td; 1675 temp->td_next = td_next; 1676 } 1677 1678 static uhci_td_t * 1679 uhci_setup_standard_chain(struct usb_xfer *xfer) 1680 { 1681 struct uhci_std_temp temp; 1682 uhci_td_t *td; 1683 uint32_t x; 1684 1685 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1686 xfer->address, UE_GET_ADDR(xfer->endpoint), 1687 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1688 1689 temp.average = xfer->max_frame_size; 1690 temp.max_frame_size = xfer->max_frame_size; 1691 1692 /* toggle the DMA set we are using */ 1693 xfer->flags_int.curr_dma_set ^= 1; 1694 1695 /* get next DMA set */ 1696 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1697 xfer->td_transfer_first = td; 1698 xfer->td_transfer_cache = td; 1699 1700 temp.td = NULL; 1701 temp.td_next = td; 1702 temp.last_frame = 0; 1703 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1704 1705 uhci_mem_layout_init(&temp.ml, xfer); 1706 1707 temp.td_status = 1708 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | 1709 UHCI_TD_ACTIVE)); 1710 1711 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1712 temp.td_status |= htole32(UHCI_TD_LS); 1713 } 1714 temp.td_token = 1715 htole32(UHCI_TD_SET_ENDPT(xfer->endpoint) | 1716 UHCI_TD_SET_DEVADDR(xfer->address)); 1717 1718 if (xfer->pipe->toggle_next) { 1719 /* DATA1 is next */ 1720 temp.td_token |= htole32(UHCI_TD_SET_DT(1)); 1721 } 1722 /* check if we should prepend a setup message */ 1723 1724 if (xfer->flags_int.control_xfr) { 1725 1726 if (xfer->flags_int.control_hdr) { 1727 1728 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1729 UHCI_TD_SET_ENDPT(0xF)); 1730 temp.td_token |= htole32(UHCI_TD_PID_SETUP | 1731 UHCI_TD_SET_DT(0)); 1732 1733 temp.len = xfer->frlengths[0]; 1734 temp.ml.buf_pc = xfer->frbuffers + 0; 1735 temp.shortpkt = temp.len ? 1 : 0; 1736 /* check for last frame */ 1737 if (xfer->nframes == 1) { 1738 /* no STATUS stage yet, SETUP is last */ 1739 if (xfer->flags_int.control_act) { 1740 temp.last_frame = 1; 1741 temp.setup_alt_next = 0; 1742 } 1743 } 1744 uhci_setup_standard_chain_sub(&temp); 1745 } 1746 x = 1; 1747 } else { 1748 x = 0; 1749 } 1750 1751 while (x != xfer->nframes) { 1752 1753 /* DATA0 / DATA1 message */ 1754 1755 temp.len = xfer->frlengths[x]; 1756 temp.ml.buf_pc = xfer->frbuffers + x; 1757 1758 x++; 1759 1760 if (x == xfer->nframes) { 1761 if (xfer->flags_int.control_xfr) { 1762 /* no STATUS stage yet, DATA is last */ 1763 if (xfer->flags_int.control_act) { 1764 temp.last_frame = 1; 1765 temp.setup_alt_next = 0; 1766 } 1767 } else { 1768 temp.last_frame = 1; 1769 temp.setup_alt_next = 0; 1770 } 1771 } 1772 /* 1773 * Keep previous data toggle, 1774 * device address and endpoint number: 1775 */ 1776 1777 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1778 UHCI_TD_SET_ENDPT(0xF) | 1779 UHCI_TD_SET_DT(1)); 1780 1781 if (temp.len == 0) { 1782 1783 /* make sure that we send an USB packet */ 1784 1785 temp.shortpkt = 0; 1786 1787 } else { 1788 1789 /* regular data transfer */ 1790 1791 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1792 } 1793 1794 /* set endpoint direction */ 1795 1796 temp.td_token |= 1797 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 1798 htole32(UHCI_TD_PID_IN) : 1799 htole32(UHCI_TD_PID_OUT); 1800 1801 uhci_setup_standard_chain_sub(&temp); 1802 } 1803 1804 /* check if we should append a status stage */ 1805 1806 if (xfer->flags_int.control_xfr && 1807 !xfer->flags_int.control_act) { 1808 1809 /* 1810 * send a DATA1 message and reverse the current endpoint 1811 * direction 1812 */ 1813 1814 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1815 UHCI_TD_SET_ENDPT(0xF) | 1816 UHCI_TD_SET_DT(1)); 1817 temp.td_token |= 1818 (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) ? 1819 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) : 1820 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1)); 1821 1822 temp.len = 0; 1823 temp.ml.buf_pc = NULL; 1824 temp.shortpkt = 0; 1825 temp.last_frame = 1; 1826 temp.setup_alt_next = 0; 1827 1828 uhci_setup_standard_chain_sub(&temp); 1829 } 1830 td = temp.td; 1831 1832 /* Ensure that last TD is terminating: */ 1833 td->td_next = htole32(UHCI_PTR_T); 1834 1835 /* set interrupt bit */ 1836 1837 td->td_status |= htole32(UHCI_TD_IOC); 1838 1839 usb2_pc_cpu_flush(td->page_cache); 1840 1841 /* must have at least one frame! */ 1842 1843 xfer->td_transfer_last = td; 1844 1845 #if USB_DEBUG 1846 if (uhcidebug > 8) { 1847 DPRINTF("nexttog=%d; data before transfer:\n", 1848 xfer->pipe->toggle_next); 1849 uhci_dump_tds(xfer->td_transfer_first); 1850 } 1851 #endif 1852 return (xfer->td_transfer_first); 1853 } 1854 1855 /* NOTE: "done" can be run two times in a row, 1856 * from close and from interrupt 1857 */ 1858 1859 static void 1860 uhci_device_done(struct usb_xfer *xfer, usb_error_t error) 1861 { 1862 struct usb_pipe_methods *methods = xfer->pipe->methods; 1863 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1864 uhci_qh_t *qh; 1865 1866 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1867 1868 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1869 xfer, xfer->pipe, error); 1870 1871 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1872 if (qh) { 1873 usb2_pc_cpu_invalidate(qh->page_cache); 1874 } 1875 if (xfer->flags_int.bandwidth_reclaimed) { 1876 xfer->flags_int.bandwidth_reclaimed = 0; 1877 uhci_rem_loop(sc); 1878 } 1879 if (methods == &uhci_device_bulk_methods) { 1880 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 1881 } 1882 if (methods == &uhci_device_ctrl_methods) { 1883 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1884 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 1885 } else { 1886 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 1887 } 1888 } 1889 if (methods == &uhci_device_intr_methods) { 1890 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 1891 } 1892 /* 1893 * Only finish isochronous transfers once 1894 * which will update "xfer->frlengths". 1895 */ 1896 if (xfer->td_transfer_first && 1897 xfer->td_transfer_last) { 1898 if (methods == &uhci_device_isoc_methods) { 1899 uhci_isoc_done(sc, xfer); 1900 } 1901 xfer->td_transfer_first = NULL; 1902 xfer->td_transfer_last = NULL; 1903 } 1904 /* dequeue transfer and start next transfer */ 1905 usb2_transfer_done(xfer, error); 1906 } 1907 1908 /*------------------------------------------------------------------------* 1909 * uhci bulk support 1910 *------------------------------------------------------------------------*/ 1911 static void 1912 uhci_device_bulk_open(struct usb_xfer *xfer) 1913 { 1914 return; 1915 } 1916 1917 static void 1918 uhci_device_bulk_close(struct usb_xfer *xfer) 1919 { 1920 uhci_device_done(xfer, USB_ERR_CANCELLED); 1921 } 1922 1923 static void 1924 uhci_device_bulk_enter(struct usb_xfer *xfer) 1925 { 1926 return; 1927 } 1928 1929 static void 1930 uhci_device_bulk_start(struct usb_xfer *xfer) 1931 { 1932 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1933 uhci_td_t *td; 1934 uhci_qh_t *qh; 1935 1936 /* setup TD's */ 1937 td = uhci_setup_standard_chain(xfer); 1938 1939 /* setup QH */ 1940 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1941 1942 qh->e_next = td; 1943 qh->qh_e_next = td->td_self; 1944 1945 if (xfer->xroot->udev->flags.self_suspended == 0) { 1946 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 1947 uhci_add_loop(sc); 1948 xfer->flags_int.bandwidth_reclaimed = 1; 1949 } else { 1950 usb2_pc_cpu_flush(qh->page_cache); 1951 } 1952 1953 /* put transfer on interrupt queue */ 1954 uhci_transfer_intr_enqueue(xfer); 1955 } 1956 1957 struct usb_pipe_methods uhci_device_bulk_methods = 1958 { 1959 .open = uhci_device_bulk_open, 1960 .close = uhci_device_bulk_close, 1961 .enter = uhci_device_bulk_enter, 1962 .start = uhci_device_bulk_start, 1963 }; 1964 1965 /*------------------------------------------------------------------------* 1966 * uhci control support 1967 *------------------------------------------------------------------------*/ 1968 static void 1969 uhci_device_ctrl_open(struct usb_xfer *xfer) 1970 { 1971 return; 1972 } 1973 1974 static void 1975 uhci_device_ctrl_close(struct usb_xfer *xfer) 1976 { 1977 uhci_device_done(xfer, USB_ERR_CANCELLED); 1978 } 1979 1980 static void 1981 uhci_device_ctrl_enter(struct usb_xfer *xfer) 1982 { 1983 return; 1984 } 1985 1986 static void 1987 uhci_device_ctrl_start(struct usb_xfer *xfer) 1988 { 1989 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1990 uhci_qh_t *qh; 1991 uhci_td_t *td; 1992 1993 /* setup TD's */ 1994 td = uhci_setup_standard_chain(xfer); 1995 1996 /* setup QH */ 1997 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1998 1999 qh->e_next = td; 2000 qh->qh_e_next = td->td_self; 2001 2002 /* 2003 * NOTE: some devices choke on bandwidth- reclamation for control 2004 * transfers 2005 */ 2006 if (xfer->xroot->udev->flags.self_suspended == 0) { 2007 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 2008 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 2009 } else { 2010 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 2011 } 2012 } else { 2013 usb2_pc_cpu_flush(qh->page_cache); 2014 } 2015 /* put transfer on interrupt queue */ 2016 uhci_transfer_intr_enqueue(xfer); 2017 } 2018 2019 struct usb_pipe_methods uhci_device_ctrl_methods = 2020 { 2021 .open = uhci_device_ctrl_open, 2022 .close = uhci_device_ctrl_close, 2023 .enter = uhci_device_ctrl_enter, 2024 .start = uhci_device_ctrl_start, 2025 }; 2026 2027 /*------------------------------------------------------------------------* 2028 * uhci interrupt support 2029 *------------------------------------------------------------------------*/ 2030 static void 2031 uhci_device_intr_open(struct usb_xfer *xfer) 2032 { 2033 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2034 uint16_t best; 2035 uint16_t bit; 2036 uint16_t x; 2037 2038 best = 0; 2039 bit = UHCI_IFRAMELIST_COUNT / 2; 2040 while (bit) { 2041 if (xfer->interval >= bit) { 2042 x = bit; 2043 best = bit; 2044 while (x & bit) { 2045 if (sc->sc_intr_stat[x] < 2046 sc->sc_intr_stat[best]) { 2047 best = x; 2048 } 2049 x++; 2050 } 2051 break; 2052 } 2053 bit >>= 1; 2054 } 2055 2056 sc->sc_intr_stat[best]++; 2057 xfer->qh_pos = best; 2058 2059 DPRINTFN(3, "best=%d interval=%d\n", 2060 best, xfer->interval); 2061 } 2062 2063 static void 2064 uhci_device_intr_close(struct usb_xfer *xfer) 2065 { 2066 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2067 2068 sc->sc_intr_stat[xfer->qh_pos]--; 2069 2070 uhci_device_done(xfer, USB_ERR_CANCELLED); 2071 } 2072 2073 static void 2074 uhci_device_intr_enter(struct usb_xfer *xfer) 2075 { 2076 return; 2077 } 2078 2079 static void 2080 uhci_device_intr_start(struct usb_xfer *xfer) 2081 { 2082 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2083 uhci_qh_t *qh; 2084 uhci_td_t *td; 2085 2086 /* setup TD's */ 2087 td = uhci_setup_standard_chain(xfer); 2088 2089 /* setup QH */ 2090 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2091 2092 qh->e_next = td; 2093 qh->qh_e_next = td->td_self; 2094 2095 if (xfer->xroot->udev->flags.self_suspended == 0) { 2096 /* enter QHs into the controller data structures */ 2097 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 2098 } else { 2099 usb2_pc_cpu_flush(qh->page_cache); 2100 } 2101 2102 /* put transfer on interrupt queue */ 2103 uhci_transfer_intr_enqueue(xfer); 2104 } 2105 2106 struct usb_pipe_methods uhci_device_intr_methods = 2107 { 2108 .open = uhci_device_intr_open, 2109 .close = uhci_device_intr_close, 2110 .enter = uhci_device_intr_enter, 2111 .start = uhci_device_intr_start, 2112 }; 2113 2114 /*------------------------------------------------------------------------* 2115 * uhci isochronous support 2116 *------------------------------------------------------------------------*/ 2117 static void 2118 uhci_device_isoc_open(struct usb_xfer *xfer) 2119 { 2120 uhci_td_t *td; 2121 uint32_t td_token; 2122 uint8_t ds; 2123 2124 td_token = 2125 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 2126 UHCI_TD_IN(0, xfer->endpoint, xfer->address, 0) : 2127 UHCI_TD_OUT(0, xfer->endpoint, xfer->address, 0); 2128 2129 td_token = htole32(td_token); 2130 2131 /* initialize all TD's */ 2132 2133 for (ds = 0; ds != 2; ds++) { 2134 2135 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2136 2137 /* mark TD as inactive */ 2138 td->td_status = htole32(UHCI_TD_IOS); 2139 td->td_token = td_token; 2140 2141 usb2_pc_cpu_flush(td->page_cache); 2142 } 2143 } 2144 } 2145 2146 static void 2147 uhci_device_isoc_close(struct usb_xfer *xfer) 2148 { 2149 uhci_device_done(xfer, USB_ERR_CANCELLED); 2150 } 2151 2152 static void 2153 uhci_device_isoc_enter(struct usb_xfer *xfer) 2154 { 2155 struct uhci_mem_layout ml; 2156 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2157 uint32_t nframes; 2158 uint32_t temp; 2159 uint32_t *plen; 2160 2161 #if USB_DEBUG 2162 uint8_t once = 1; 2163 2164 #endif 2165 uhci_td_t *td; 2166 uhci_td_t *td_last = NULL; 2167 uhci_td_t **pp_last; 2168 2169 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2170 xfer, xfer->pipe->isoc_next, xfer->nframes); 2171 2172 nframes = UREAD2(sc, UHCI_FRNUM); 2173 2174 temp = (nframes - xfer->pipe->isoc_next) & 2175 (UHCI_VFRAMELIST_COUNT - 1); 2176 2177 if ((xfer->pipe->is_synced == 0) || 2178 (temp < xfer->nframes)) { 2179 /* 2180 * If there is data underflow or the pipe queue is empty we 2181 * schedule the transfer a few frames ahead of the current 2182 * frame position. Else two isochronous transfers might 2183 * overlap. 2184 */ 2185 xfer->pipe->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1); 2186 xfer->pipe->is_synced = 1; 2187 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2188 } 2189 /* 2190 * compute how many milliseconds the insertion is ahead of the 2191 * current frame position: 2192 */ 2193 temp = (xfer->pipe->isoc_next - nframes) & 2194 (UHCI_VFRAMELIST_COUNT - 1); 2195 2196 /* 2197 * pre-compute when the isochronous transfer will be finished: 2198 */ 2199 xfer->isoc_time_complete = 2200 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2201 xfer->nframes; 2202 2203 /* get the real number of frames */ 2204 2205 nframes = xfer->nframes; 2206 2207 uhci_mem_layout_init(&ml, xfer); 2208 2209 plen = xfer->frlengths; 2210 2211 /* toggle the DMA set we are using */ 2212 xfer->flags_int.curr_dma_set ^= 1; 2213 2214 /* get next DMA set */ 2215 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2216 xfer->td_transfer_first = td; 2217 2218 pp_last = &sc->sc_isoc_p_last[xfer->pipe->isoc_next]; 2219 2220 /* store starting position */ 2221 2222 xfer->qh_pos = xfer->pipe->isoc_next; 2223 2224 while (nframes--) { 2225 if (td == NULL) { 2226 panic("%s:%d: out of TD's\n", 2227 __FUNCTION__, __LINE__); 2228 } 2229 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 2230 pp_last = &sc->sc_isoc_p_last[0]; 2231 } 2232 if (*plen > xfer->max_frame_size) { 2233 #if USB_DEBUG 2234 if (once) { 2235 once = 0; 2236 printf("%s: frame length(%d) exceeds %d " 2237 "bytes (frame truncated)\n", 2238 __FUNCTION__, *plen, 2239 xfer->max_frame_size); 2240 } 2241 #endif 2242 *plen = xfer->max_frame_size; 2243 } 2244 /* reuse td_token from last transfer */ 2245 2246 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2247 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen)); 2248 2249 td->len = *plen; 2250 2251 if (td->len == 0) { 2252 /* 2253 * Do not call "uhci_mem_layout_fixup()" when the 2254 * length is zero! 2255 */ 2256 td->td_buffer = 0; 2257 td->fix_pc = NULL; 2258 2259 } else { 2260 2261 /* fill out buffer pointer and do fixup, if any */ 2262 2263 uhci_mem_layout_fixup(&ml, td); 2264 2265 } 2266 2267 /* update status */ 2268 if (nframes == 0) { 2269 td->td_status = htole32 2270 (UHCI_TD_ZERO_ACTLEN 2271 (UHCI_TD_SET_ERRCNT(0) | 2272 UHCI_TD_ACTIVE | 2273 UHCI_TD_IOS | 2274 UHCI_TD_IOC)); 2275 } else { 2276 td->td_status = htole32 2277 (UHCI_TD_ZERO_ACTLEN 2278 (UHCI_TD_SET_ERRCNT(0) | 2279 UHCI_TD_ACTIVE | 2280 UHCI_TD_IOS)); 2281 } 2282 2283 usb2_pc_cpu_flush(td->page_cache); 2284 2285 #if USB_DEBUG 2286 if (uhcidebug > 5) { 2287 DPRINTF("TD %d\n", nframes); 2288 uhci_dump_td(td); 2289 } 2290 #endif 2291 /* insert TD into schedule */ 2292 UHCI_APPEND_TD(td, *pp_last); 2293 pp_last++; 2294 2295 plen++; 2296 td_last = td; 2297 td = td->obj_next; 2298 } 2299 2300 xfer->td_transfer_last = td_last; 2301 2302 /* update isoc_next */ 2303 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) & 2304 (UHCI_VFRAMELIST_COUNT - 1); 2305 } 2306 2307 static void 2308 uhci_device_isoc_start(struct usb_xfer *xfer) 2309 { 2310 /* put transfer on interrupt queue */ 2311 uhci_transfer_intr_enqueue(xfer); 2312 } 2313 2314 struct usb_pipe_methods uhci_device_isoc_methods = 2315 { 2316 .open = uhci_device_isoc_open, 2317 .close = uhci_device_isoc_close, 2318 .enter = uhci_device_isoc_enter, 2319 .start = uhci_device_isoc_start, 2320 }; 2321 2322 /*------------------------------------------------------------------------* 2323 * uhci root control support 2324 *------------------------------------------------------------------------* 2325 * Simulate a hardware hub by handling all the necessary requests. 2326 *------------------------------------------------------------------------*/ 2327 2328 static const 2329 struct usb_device_descriptor uhci_devd = 2330 { 2331 sizeof(struct usb_device_descriptor), 2332 UDESC_DEVICE, /* type */ 2333 {0x00, 0x01}, /* USB version */ 2334 UDCLASS_HUB, /* class */ 2335 UDSUBCLASS_HUB, /* subclass */ 2336 UDPROTO_FSHUB, /* protocol */ 2337 64, /* max packet */ 2338 {0}, {0}, {0x00, 0x01}, /* device id */ 2339 1, 2, 0, /* string indicies */ 2340 1 /* # of configurations */ 2341 }; 2342 2343 static const struct uhci_config_desc uhci_confd = { 2344 .confd = { 2345 .bLength = sizeof(struct usb_config_descriptor), 2346 .bDescriptorType = UDESC_CONFIG, 2347 .wTotalLength[0] = sizeof(uhci_confd), 2348 .bNumInterface = 1, 2349 .bConfigurationValue = 1, 2350 .iConfiguration = 0, 2351 .bmAttributes = UC_SELF_POWERED, 2352 .bMaxPower = 0 /* max power */ 2353 }, 2354 .ifcd = { 2355 .bLength = sizeof(struct usb_interface_descriptor), 2356 .bDescriptorType = UDESC_INTERFACE, 2357 .bNumEndpoints = 1, 2358 .bInterfaceClass = UICLASS_HUB, 2359 .bInterfaceSubClass = UISUBCLASS_HUB, 2360 .bInterfaceProtocol = UIPROTO_FSHUB, 2361 }, 2362 .endpd = { 2363 .bLength = sizeof(struct usb_endpoint_descriptor), 2364 .bDescriptorType = UDESC_ENDPOINT, 2365 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 2366 .bmAttributes = UE_INTERRUPT, 2367 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2368 .bInterval = 255, 2369 }, 2370 }; 2371 2372 static const 2373 struct usb_hub_descriptor_min uhci_hubd_piix = 2374 { 2375 sizeof(uhci_hubd_piix), 2376 UDESC_HUB, 2377 2, 2378 {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0}, 2379 50, /* power on to power good */ 2380 0, 2381 {0x00}, /* both ports are removable */ 2382 }; 2383 2384 /* 2385 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 2386 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 2387 * should not be used by the USB subsystem. As we cannot issue a 2388 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 2389 * will be enabled as part of the reset. 2390 * 2391 * On the VT83C572, the port cannot be successfully enabled until the 2392 * outstanding "port enable change" and "connection status change" 2393 * events have been reset. 2394 */ 2395 static usb_error_t 2396 uhci_portreset(uhci_softc_t *sc, uint16_t index) 2397 { 2398 uint16_t port; 2399 uint16_t x; 2400 uint8_t lim; 2401 2402 if (index == 1) 2403 port = UHCI_PORTSC1; 2404 else if (index == 2) 2405 port = UHCI_PORTSC2; 2406 else 2407 return (USB_ERR_IOERROR); 2408 2409 /* 2410 * Before we do anything, turn on SOF messages on the USB 2411 * BUS. Some USB devices do not cope without them! 2412 */ 2413 uhci_restart(sc); 2414 2415 x = URWMASK(UREAD2(sc, port)); 2416 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2417 2418 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2419 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 2420 2421 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n", 2422 index, UREAD2(sc, port)); 2423 2424 x = URWMASK(UREAD2(sc, port)); 2425 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2426 2427 2428 mtx_unlock(&sc->sc_bus.bus_mtx); 2429 2430 /* 2431 * This delay needs to be exactly 100us, else some USB devices 2432 * fail to attach! 2433 */ 2434 DELAY(100); 2435 2436 mtx_lock(&sc->sc_bus.bus_mtx); 2437 2438 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n", 2439 index, UREAD2(sc, port)); 2440 2441 x = URWMASK(UREAD2(sc, port)); 2442 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2443 2444 for (lim = 0; lim < 12; lim++) { 2445 2446 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2447 USB_MS_TO_TICKS(USB_PORT_RESET_DELAY)); 2448 2449 x = UREAD2(sc, port); 2450 2451 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n", 2452 index, lim, x); 2453 2454 if (!(x & UHCI_PORTSC_CCS)) { 2455 /* 2456 * No device is connected (or was disconnected 2457 * during reset). Consider the port reset. 2458 * The delay must be long enough to ensure on 2459 * the initial iteration that the device 2460 * connection will have been registered. 50ms 2461 * appears to be sufficient, but 20ms is not. 2462 */ 2463 DPRINTFN(4, "uhci port %d loop %u, device detached\n", 2464 index, lim); 2465 goto done; 2466 } 2467 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 2468 /* 2469 * Port enabled changed and/or connection 2470 * status changed were set. Reset either or 2471 * both raised flags (by writing a 1 to that 2472 * bit), and wait again for state to settle. 2473 */ 2474 UWRITE2(sc, port, URWMASK(x) | 2475 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 2476 continue; 2477 } 2478 if (x & UHCI_PORTSC_PE) { 2479 /* port is enabled */ 2480 goto done; 2481 } 2482 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 2483 } 2484 2485 DPRINTFN(2, "uhci port %d reset timed out\n", index); 2486 return (USB_ERR_TIMEOUT); 2487 2488 done: 2489 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n", 2490 index, UREAD2(sc, port)); 2491 2492 sc->sc_isreset = 1; 2493 return (USB_ERR_NORMAL_COMPLETION); 2494 } 2495 2496 static usb_error_t 2497 uhci_roothub_exec(struct usb_device *udev, 2498 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2499 { 2500 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 2501 const void *ptr; 2502 const char *str_ptr; 2503 uint16_t x; 2504 uint16_t port; 2505 uint16_t value; 2506 uint16_t index; 2507 uint16_t status; 2508 uint16_t change; 2509 uint16_t len; 2510 usb_error_t err; 2511 2512 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2513 2514 /* buffer reset */ 2515 ptr = (const void *)&sc->sc_hub_desc.temp; 2516 len = 0; 2517 err = 0; 2518 2519 value = UGETW(req->wValue); 2520 index = UGETW(req->wIndex); 2521 2522 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2523 "wValue=0x%04x wIndex=0x%04x\n", 2524 req->bmRequestType, req->bRequest, 2525 UGETW(req->wLength), value, index); 2526 2527 #define C(x,y) ((x) | ((y) << 8)) 2528 switch (C(req->bRequest, req->bmRequestType)) { 2529 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2530 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2531 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2532 /* 2533 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2534 * for the integrated root hub. 2535 */ 2536 break; 2537 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2538 len = 1; 2539 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2540 break; 2541 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2542 switch (value >> 8) { 2543 case UDESC_DEVICE: 2544 if ((value & 0xff) != 0) { 2545 err = USB_ERR_IOERROR; 2546 goto done; 2547 } 2548 len = sizeof(uhci_devd); 2549 ptr = (const void *)&uhci_devd; 2550 break; 2551 2552 case UDESC_CONFIG: 2553 if ((value & 0xff) != 0) { 2554 err = USB_ERR_IOERROR; 2555 goto done; 2556 } 2557 len = sizeof(uhci_confd); 2558 ptr = (const void *)&uhci_confd; 2559 break; 2560 2561 case UDESC_STRING: 2562 switch (value & 0xff) { 2563 case 0: /* Language table */ 2564 str_ptr = "\001"; 2565 break; 2566 2567 case 1: /* Vendor */ 2568 str_ptr = sc->sc_vendor; 2569 break; 2570 2571 case 2: /* Product */ 2572 str_ptr = "UHCI root HUB"; 2573 break; 2574 2575 default: 2576 str_ptr = ""; 2577 break; 2578 } 2579 2580 len = usb2_make_str_desc 2581 (sc->sc_hub_desc.temp, 2582 sizeof(sc->sc_hub_desc.temp), 2583 str_ptr); 2584 break; 2585 2586 default: 2587 err = USB_ERR_IOERROR; 2588 goto done; 2589 } 2590 break; 2591 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2592 len = 1; 2593 sc->sc_hub_desc.temp[0] = 0; 2594 break; 2595 case C(UR_GET_STATUS, UT_READ_DEVICE): 2596 len = 2; 2597 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2598 break; 2599 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2600 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2601 len = 2; 2602 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2603 break; 2604 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2605 if (value >= UHCI_MAX_DEVICES) { 2606 err = USB_ERR_IOERROR; 2607 goto done; 2608 } 2609 sc->sc_addr = value; 2610 break; 2611 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2612 if ((value != 0) && (value != 1)) { 2613 err = USB_ERR_IOERROR; 2614 goto done; 2615 } 2616 sc->sc_conf = value; 2617 break; 2618 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2619 break; 2620 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2621 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2622 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2623 err = USB_ERR_IOERROR; 2624 goto done; 2625 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2626 break; 2627 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2628 break; 2629 /* Hub requests */ 2630 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2631 break; 2632 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2633 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE " 2634 "port=%d feature=%d\n", 2635 index, value); 2636 if (index == 1) 2637 port = UHCI_PORTSC1; 2638 else if (index == 2) 2639 port = UHCI_PORTSC2; 2640 else { 2641 err = USB_ERR_IOERROR; 2642 goto done; 2643 } 2644 switch (value) { 2645 case UHF_PORT_ENABLE: 2646 x = URWMASK(UREAD2(sc, port)); 2647 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2648 break; 2649 case UHF_PORT_SUSPEND: 2650 x = URWMASK(UREAD2(sc, port)); 2651 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP)); 2652 break; 2653 case UHF_PORT_RESET: 2654 x = URWMASK(UREAD2(sc, port)); 2655 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2656 break; 2657 case UHF_C_PORT_CONNECTION: 2658 x = URWMASK(UREAD2(sc, port)); 2659 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2660 break; 2661 case UHF_C_PORT_ENABLE: 2662 x = URWMASK(UREAD2(sc, port)); 2663 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2664 break; 2665 case UHF_C_PORT_OVER_CURRENT: 2666 x = URWMASK(UREAD2(sc, port)); 2667 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2668 break; 2669 case UHF_C_PORT_RESET: 2670 sc->sc_isreset = 0; 2671 err = USB_ERR_NORMAL_COMPLETION; 2672 goto done; 2673 case UHF_C_PORT_SUSPEND: 2674 sc->sc_isresumed &= ~(1 << index); 2675 break; 2676 case UHF_PORT_CONNECTION: 2677 case UHF_PORT_OVER_CURRENT: 2678 case UHF_PORT_POWER: 2679 case UHF_PORT_LOW_SPEED: 2680 default: 2681 err = USB_ERR_IOERROR; 2682 goto done; 2683 } 2684 break; 2685 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2686 if (index == 1) 2687 port = UHCI_PORTSC1; 2688 else if (index == 2) 2689 port = UHCI_PORTSC2; 2690 else { 2691 err = USB_ERR_IOERROR; 2692 goto done; 2693 } 2694 len = 1; 2695 sc->sc_hub_desc.temp[0] = 2696 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2697 UHCI_PORTSC_LS_SHIFT); 2698 break; 2699 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2700 if ((value & 0xff) != 0) { 2701 err = USB_ERR_IOERROR; 2702 goto done; 2703 } 2704 len = sizeof(uhci_hubd_piix); 2705 ptr = (const void *)&uhci_hubd_piix; 2706 break; 2707 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2708 len = 16; 2709 bzero(sc->sc_hub_desc.temp, 16); 2710 break; 2711 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2712 if (index == 1) 2713 port = UHCI_PORTSC1; 2714 else if (index == 2) 2715 port = UHCI_PORTSC2; 2716 else { 2717 err = USB_ERR_IOERROR; 2718 goto done; 2719 } 2720 x = UREAD2(sc, port); 2721 status = change = 0; 2722 if (x & UHCI_PORTSC_CCS) 2723 status |= UPS_CURRENT_CONNECT_STATUS; 2724 if (x & UHCI_PORTSC_CSC) 2725 change |= UPS_C_CONNECT_STATUS; 2726 if (x & UHCI_PORTSC_PE) 2727 status |= UPS_PORT_ENABLED; 2728 if (x & UHCI_PORTSC_POEDC) 2729 change |= UPS_C_PORT_ENABLED; 2730 if (x & UHCI_PORTSC_OCI) 2731 status |= UPS_OVERCURRENT_INDICATOR; 2732 if (x & UHCI_PORTSC_OCIC) 2733 change |= UPS_C_OVERCURRENT_INDICATOR; 2734 if (x & UHCI_PORTSC_LSDA) 2735 status |= UPS_LOW_SPEED; 2736 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) { 2737 /* need to do a write back */ 2738 UWRITE2(sc, port, URWMASK(x)); 2739 2740 /* wait 20ms for resume sequence to complete */ 2741 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 2742 2743 /* clear suspend and resume detect */ 2744 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD | 2745 UHCI_PORTSC_SUSP)); 2746 2747 /* wait a little bit */ 2748 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500); 2749 2750 sc->sc_isresumed |= (1 << index); 2751 2752 } else if (x & UHCI_PORTSC_SUSP) { 2753 status |= UPS_SUSPEND; 2754 } 2755 status |= UPS_PORT_POWER; 2756 if (sc->sc_isresumed & (1 << index)) 2757 change |= UPS_C_SUSPEND; 2758 if (sc->sc_isreset) 2759 change |= UPS_C_PORT_RESET; 2760 USETW(sc->sc_hub_desc.ps.wPortStatus, status); 2761 USETW(sc->sc_hub_desc.ps.wPortChange, change); 2762 len = sizeof(sc->sc_hub_desc.ps); 2763 break; 2764 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2765 err = USB_ERR_IOERROR; 2766 goto done; 2767 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2768 break; 2769 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2770 if (index == 1) 2771 port = UHCI_PORTSC1; 2772 else if (index == 2) 2773 port = UHCI_PORTSC2; 2774 else { 2775 err = USB_ERR_IOERROR; 2776 goto done; 2777 } 2778 switch (value) { 2779 case UHF_PORT_ENABLE: 2780 x = URWMASK(UREAD2(sc, port)); 2781 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2782 break; 2783 case UHF_PORT_SUSPEND: 2784 x = URWMASK(UREAD2(sc, port)); 2785 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2786 break; 2787 case UHF_PORT_RESET: 2788 err = uhci_portreset(sc, index); 2789 goto done; 2790 case UHF_PORT_POWER: 2791 /* pretend we turned on power */ 2792 err = USB_ERR_NORMAL_COMPLETION; 2793 goto done; 2794 case UHF_C_PORT_CONNECTION: 2795 case UHF_C_PORT_ENABLE: 2796 case UHF_C_PORT_OVER_CURRENT: 2797 case UHF_PORT_CONNECTION: 2798 case UHF_PORT_OVER_CURRENT: 2799 case UHF_PORT_LOW_SPEED: 2800 case UHF_C_PORT_SUSPEND: 2801 case UHF_C_PORT_RESET: 2802 default: 2803 err = USB_ERR_IOERROR; 2804 goto done; 2805 } 2806 break; 2807 default: 2808 err = USB_ERR_IOERROR; 2809 goto done; 2810 } 2811 done: 2812 *plength = len; 2813 *pptr = ptr; 2814 return (err); 2815 } 2816 2817 /* 2818 * This routine is executed periodically and simulates interrupts from 2819 * the root controller interrupt pipe for port status change: 2820 */ 2821 static void 2822 uhci_root_intr(uhci_softc_t *sc) 2823 { 2824 DPRINTFN(21, "\n"); 2825 2826 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2827 2828 sc->sc_hub_idata[0] = 0; 2829 2830 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | 2831 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2832 sc->sc_hub_idata[0] |= 1 << 1; 2833 } 2834 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | 2835 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2836 sc->sc_hub_idata[0] |= 1 << 2; 2837 } 2838 2839 /* restart timer */ 2840 usb2_callout_reset(&sc->sc_root_intr, hz, 2841 (void *)&uhci_root_intr, sc); 2842 2843 if (sc->sc_hub_idata[0] != 0) { 2844 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2845 sizeof(sc->sc_hub_idata)); 2846 } 2847 } 2848 2849 static void 2850 uhci_xfer_setup(struct usb_setup_params *parm) 2851 { 2852 struct usb_page_search page_info; 2853 struct usb_page_cache *pc; 2854 uhci_softc_t *sc; 2855 struct usb_xfer *xfer; 2856 void *last_obj; 2857 uint32_t ntd; 2858 uint32_t nqh; 2859 uint32_t nfixup; 2860 uint32_t n; 2861 uint16_t align; 2862 2863 sc = UHCI_BUS2SC(parm->udev->bus); 2864 xfer = parm->curr_xfer; 2865 2866 parm->hc_max_packet_size = 0x500; 2867 parm->hc_max_packet_count = 1; 2868 parm->hc_max_frame_size = 0x500; 2869 2870 /* 2871 * compute ntd and nqh 2872 */ 2873 if (parm->methods == &uhci_device_ctrl_methods) { 2874 xfer->flags_int.bdma_enable = 1; 2875 xfer->flags_int.bdma_no_post_sync = 1; 2876 2877 usb2_transfer_setup_sub(parm); 2878 2879 /* see EHCI HC driver for proof of "ntd" formula */ 2880 2881 nqh = 1; 2882 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2883 + (xfer->max_data_length / xfer->max_frame_size)); 2884 2885 } else if (parm->methods == &uhci_device_bulk_methods) { 2886 xfer->flags_int.bdma_enable = 1; 2887 xfer->flags_int.bdma_no_post_sync = 1; 2888 2889 usb2_transfer_setup_sub(parm); 2890 2891 nqh = 1; 2892 ntd = ((2 * xfer->nframes) 2893 + (xfer->max_data_length / xfer->max_frame_size)); 2894 2895 } else if (parm->methods == &uhci_device_intr_methods) { 2896 xfer->flags_int.bdma_enable = 1; 2897 xfer->flags_int.bdma_no_post_sync = 1; 2898 2899 usb2_transfer_setup_sub(parm); 2900 2901 nqh = 1; 2902 ntd = ((2 * xfer->nframes) 2903 + (xfer->max_data_length / xfer->max_frame_size)); 2904 2905 } else if (parm->methods == &uhci_device_isoc_methods) { 2906 xfer->flags_int.bdma_enable = 1; 2907 xfer->flags_int.bdma_no_post_sync = 1; 2908 2909 usb2_transfer_setup_sub(parm); 2910 2911 nqh = 0; 2912 ntd = xfer->nframes; 2913 2914 } else { 2915 2916 usb2_transfer_setup_sub(parm); 2917 2918 nqh = 0; 2919 ntd = 0; 2920 } 2921 2922 if (parm->err) { 2923 return; 2924 } 2925 /* 2926 * NOTE: the UHCI controller requires that 2927 * every packet must be contiguous on 2928 * the same USB memory page ! 2929 */ 2930 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1; 2931 2932 /* 2933 * Compute a suitable power of two alignment 2934 * for our "max_frame_size" fixup buffer(s): 2935 */ 2936 align = xfer->max_frame_size; 2937 n = 0; 2938 while (align) { 2939 align >>= 1; 2940 n++; 2941 } 2942 2943 /* check for power of two */ 2944 if (!(xfer->max_frame_size & 2945 (xfer->max_frame_size - 1))) { 2946 n--; 2947 } 2948 /* 2949 * We don't allow alignments of 2950 * less than 8 bytes: 2951 * 2952 * NOTE: Allocating using an aligment 2953 * of 1 byte has special meaning! 2954 */ 2955 if (n < 3) { 2956 n = 3; 2957 } 2958 align = (1 << n); 2959 2960 if (usb2_transfer_setup_sub_malloc( 2961 parm, &pc, xfer->max_frame_size, 2962 align, nfixup)) { 2963 parm->err = USB_ERR_NOMEM; 2964 return; 2965 } 2966 xfer->buf_fixup = pc; 2967 2968 alloc_dma_set: 2969 2970 if (parm->err) { 2971 return; 2972 } 2973 last_obj = NULL; 2974 2975 if (usb2_transfer_setup_sub_malloc( 2976 parm, &pc, sizeof(uhci_td_t), 2977 UHCI_TD_ALIGN, ntd)) { 2978 parm->err = USB_ERR_NOMEM; 2979 return; 2980 } 2981 if (parm->buf) { 2982 for (n = 0; n != ntd; n++) { 2983 uhci_td_t *td; 2984 2985 usb2_get_page(pc + n, 0, &page_info); 2986 2987 td = page_info.buffer; 2988 2989 /* init TD */ 2990 if ((parm->methods == &uhci_device_bulk_methods) || 2991 (parm->methods == &uhci_device_ctrl_methods) || 2992 (parm->methods == &uhci_device_intr_methods)) { 2993 /* set depth first bit */ 2994 td->td_self = htole32(page_info.physaddr | 2995 UHCI_PTR_TD | UHCI_PTR_VF); 2996 } else { 2997 td->td_self = htole32(page_info.physaddr | 2998 UHCI_PTR_TD); 2999 } 3000 3001 td->obj_next = last_obj; 3002 td->page_cache = pc + n; 3003 3004 last_obj = td; 3005 3006 usb2_pc_cpu_flush(pc + n); 3007 } 3008 } 3009 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3010 3011 last_obj = NULL; 3012 3013 if (usb2_transfer_setup_sub_malloc( 3014 parm, &pc, sizeof(uhci_qh_t), 3015 UHCI_QH_ALIGN, nqh)) { 3016 parm->err = USB_ERR_NOMEM; 3017 return; 3018 } 3019 if (parm->buf) { 3020 for (n = 0; n != nqh; n++) { 3021 uhci_qh_t *qh; 3022 3023 usb2_get_page(pc + n, 0, &page_info); 3024 3025 qh = page_info.buffer; 3026 3027 /* init QH */ 3028 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH); 3029 qh->obj_next = last_obj; 3030 qh->page_cache = pc + n; 3031 3032 last_obj = qh; 3033 3034 usb2_pc_cpu_flush(pc + n); 3035 } 3036 } 3037 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3038 3039 if (!xfer->flags_int.curr_dma_set) { 3040 xfer->flags_int.curr_dma_set = 1; 3041 goto alloc_dma_set; 3042 } 3043 } 3044 3045 static void 3046 uhci_pipe_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3047 struct usb_pipe *pipe) 3048 { 3049 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 3050 3051 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3052 pipe, udev->address, 3053 edesc->bEndpointAddress, udev->flags.usb_mode, 3054 sc->sc_addr); 3055 3056 if (udev->flags.usb_mode != USB_MODE_HOST) { 3057 /* not supported */ 3058 return; 3059 } 3060 if (udev->device_index != sc->sc_addr) { 3061 switch (edesc->bmAttributes & UE_XFERTYPE) { 3062 case UE_CONTROL: 3063 pipe->methods = &uhci_device_ctrl_methods; 3064 break; 3065 case UE_INTERRUPT: 3066 pipe->methods = &uhci_device_intr_methods; 3067 break; 3068 case UE_ISOCHRONOUS: 3069 if (udev->speed == USB_SPEED_FULL) { 3070 pipe->methods = &uhci_device_isoc_methods; 3071 } 3072 break; 3073 case UE_BULK: 3074 if (udev->speed != USB_SPEED_LOW) { 3075 pipe->methods = &uhci_device_bulk_methods; 3076 } 3077 break; 3078 default: 3079 /* do nothing */ 3080 break; 3081 } 3082 } 3083 } 3084 3085 static void 3086 uhci_xfer_unsetup(struct usb_xfer *xfer) 3087 { 3088 return; 3089 } 3090 3091 static void 3092 uhci_get_dma_delay(struct usb_bus *bus, uint32_t *pus) 3093 { 3094 /* 3095 * Wait until hardware has finished any possible use of the 3096 * transfer descriptor(s) and QH 3097 */ 3098 *pus = (1125); /* microseconds */ 3099 } 3100 3101 static void 3102 uhci_device_resume(struct usb_device *udev) 3103 { 3104 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3105 struct usb_xfer *xfer; 3106 struct usb_pipe_methods *methods; 3107 uhci_qh_t *qh; 3108 3109 DPRINTF("\n"); 3110 3111 USB_BUS_LOCK(udev->bus); 3112 3113 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3114 3115 if (xfer->xroot->udev == udev) { 3116 3117 methods = xfer->pipe->methods; 3118 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3119 3120 if (methods == &uhci_device_bulk_methods) { 3121 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 3122 uhci_add_loop(sc); 3123 xfer->flags_int.bandwidth_reclaimed = 1; 3124 } 3125 if (methods == &uhci_device_ctrl_methods) { 3126 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3127 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 3128 } else { 3129 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 3130 } 3131 } 3132 if (methods == &uhci_device_intr_methods) { 3133 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3134 } 3135 } 3136 } 3137 3138 USB_BUS_UNLOCK(udev->bus); 3139 3140 return; 3141 } 3142 3143 static void 3144 uhci_device_suspend(struct usb_device *udev) 3145 { 3146 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3147 struct usb_xfer *xfer; 3148 struct usb_pipe_methods *methods; 3149 uhci_qh_t *qh; 3150 3151 DPRINTF("\n"); 3152 3153 USB_BUS_LOCK(udev->bus); 3154 3155 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3156 3157 if (xfer->xroot->udev == udev) { 3158 3159 methods = xfer->pipe->methods; 3160 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3161 3162 if (xfer->flags_int.bandwidth_reclaimed) { 3163 xfer->flags_int.bandwidth_reclaimed = 0; 3164 uhci_rem_loop(sc); 3165 } 3166 if (methods == &uhci_device_bulk_methods) { 3167 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 3168 } 3169 if (methods == &uhci_device_ctrl_methods) { 3170 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3171 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 3172 } else { 3173 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 3174 } 3175 } 3176 if (methods == &uhci_device_intr_methods) { 3177 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3178 } 3179 } 3180 } 3181 3182 USB_BUS_UNLOCK(udev->bus); 3183 3184 return; 3185 } 3186 3187 static void 3188 uhci_set_hw_power(struct usb_bus *bus) 3189 { 3190 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3191 uint32_t flags; 3192 3193 DPRINTF("\n"); 3194 3195 USB_BUS_LOCK(bus); 3196 3197 flags = bus->hw_power_state; 3198 3199 /* 3200 * WARNING: Some FULL speed USB devices require periodic SOF 3201 * messages! If any USB devices are connected through the 3202 * UHCI, power save will be disabled! 3203 */ 3204 if (flags & (USB_HW_POWER_CONTROL | 3205 USB_HW_POWER_NON_ROOT_HUB | 3206 USB_HW_POWER_BULK | 3207 USB_HW_POWER_INTERRUPT | 3208 USB_HW_POWER_ISOC)) { 3209 DPRINTF("Some USB transfer is " 3210 "active on unit %u.\n", 3211 device_get_unit(sc->sc_bus.bdev)); 3212 uhci_restart(sc); 3213 } else { 3214 DPRINTF("Power save on unit %u.\n", 3215 device_get_unit(sc->sc_bus.bdev)); 3216 UHCICMD(sc, UHCI_CMD_MAXP); 3217 } 3218 3219 USB_BUS_UNLOCK(bus); 3220 3221 return; 3222 } 3223 3224 3225 struct usb_bus_methods uhci_bus_methods = 3226 { 3227 .pipe_init = uhci_pipe_init, 3228 .xfer_setup = uhci_xfer_setup, 3229 .xfer_unsetup = uhci_xfer_unsetup, 3230 .get_dma_delay = uhci_get_dma_delay, 3231 .device_resume = uhci_device_resume, 3232 .device_suspend = uhci_device_suspend, 3233 .set_hw_power = uhci_set_hw_power, 3234 .roothub_exec = uhci_roothub_exec, 3235 }; 3236