1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 5 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB Universal Host Controller driver. 31 * Handles e.g. PIIX3 and PIIX4. 32 * 33 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm 34 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 35 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf 36 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf 37 */ 38 39 #ifdef USB_GLOBAL_INCLUDE_FILE 40 #include USB_GLOBAL_INCLUDE_FILE 41 #else 42 #include <sys/stdint.h> 43 #include <sys/stddef.h> 44 #include <sys/param.h> 45 #include <sys/queue.h> 46 #include <sys/types.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/module.h> 51 #include <sys/lock.h> 52 #include <sys/mutex.h> 53 #include <sys/condvar.h> 54 #include <sys/sysctl.h> 55 #include <sys/sx.h> 56 #include <sys/unistd.h> 57 #include <sys/callout.h> 58 #include <sys/malloc.h> 59 #include <sys/priv.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 64 #define USB_DEBUG_VAR uhcidebug 65 66 #include <dev/usb/usb_core.h> 67 #include <dev/usb/usb_debug.h> 68 #include <dev/usb/usb_busdma.h> 69 #include <dev/usb/usb_process.h> 70 #include <dev/usb/usb_transfer.h> 71 #include <dev/usb/usb_device.h> 72 #include <dev/usb/usb_hub.h> 73 #include <dev/usb/usb_util.h> 74 75 #include <dev/usb/usb_controller.h> 76 #include <dev/usb/usb_bus.h> 77 #endif /* USB_GLOBAL_INCLUDE_FILE */ 78 79 #include <dev/usb/controller/uhci.h> 80 #include <dev/usb/controller/uhcireg.h> 81 82 #define alt_next next 83 #define UHCI_BUS2SC(bus) \ 84 ((uhci_softc_t *)(((uint8_t *)(bus)) - \ 85 ((uint8_t *)&(((uhci_softc_t *)0)->sc_bus)))) 86 87 #ifdef USB_DEBUG 88 static int uhcidebug = 0; 89 static int uhcinoloop = 0; 90 91 static SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW, 0, "USB uhci"); 92 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 93 &uhcidebug, 0, "uhci debug level"); 94 TUNABLE_INT("hw.usb.uhci.debug", &uhcidebug); 95 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RW | CTLFLAG_TUN, 96 &uhcinoloop, 0, "uhci noloop"); 97 TUNABLE_INT("hw.usb.uhci.loop", &uhcinoloop); 98 99 static void uhci_dumpregs(uhci_softc_t *sc); 100 static void uhci_dump_tds(uhci_td_t *td); 101 102 #endif 103 104 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 105 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 106 #define UWRITE1(sc, r, x) \ 107 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 108 } while (/*CONSTCOND*/0) 109 #define UWRITE2(sc, r, x) \ 110 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 111 } while (/*CONSTCOND*/0) 112 #define UWRITE4(sc, r, x) \ 113 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \ 114 } while (/*CONSTCOND*/0) 115 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 116 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 117 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 118 119 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd) 120 #define UHCISTS(sc) UREAD2(sc, UHCI_STS) 121 122 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */ 123 124 #define UHCI_INTR_ENDPT 1 125 126 struct uhci_mem_layout { 127 128 struct usb_page_search buf_res; 129 struct usb_page_search fix_res; 130 131 struct usb_page_cache *buf_pc; 132 struct usb_page_cache *fix_pc; 133 134 uint32_t buf_offset; 135 136 uint16_t max_frame_size; 137 }; 138 139 struct uhci_std_temp { 140 141 struct uhci_mem_layout ml; 142 uhci_td_t *td; 143 uhci_td_t *td_next; 144 uint32_t average; 145 uint32_t td_status; 146 uint32_t td_token; 147 uint32_t len; 148 uint16_t max_frame_size; 149 uint8_t shortpkt; 150 uint8_t setup_alt_next; 151 uint8_t last_frame; 152 }; 153 154 static const struct usb_bus_methods uhci_bus_methods; 155 static const struct usb_pipe_methods uhci_device_bulk_methods; 156 static const struct usb_pipe_methods uhci_device_ctrl_methods; 157 static const struct usb_pipe_methods uhci_device_intr_methods; 158 static const struct usb_pipe_methods uhci_device_isoc_methods; 159 160 static uint8_t uhci_restart(uhci_softc_t *sc); 161 static void uhci_do_poll(struct usb_bus *); 162 static void uhci_device_done(struct usb_xfer *, usb_error_t); 163 static void uhci_transfer_intr_enqueue(struct usb_xfer *); 164 static void uhci_timeout(void *); 165 static uint8_t uhci_check_transfer(struct usb_xfer *); 166 static void uhci_root_intr(uhci_softc_t *sc); 167 168 void 169 uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 170 { 171 struct uhci_softc *sc = UHCI_BUS2SC(bus); 172 uint32_t i; 173 174 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 175 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN); 176 177 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg, 178 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 179 180 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg, 181 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 182 183 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 184 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 185 186 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg, 187 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 188 189 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg, 190 sizeof(uhci_td_t), UHCI_TD_ALIGN); 191 192 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) { 193 cb(bus, sc->sc_hw.isoc_start_pc + i, 194 sc->sc_hw.isoc_start_pg + i, 195 sizeof(uhci_td_t), UHCI_TD_ALIGN); 196 } 197 198 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) { 199 cb(bus, sc->sc_hw.intr_start_pc + i, 200 sc->sc_hw.intr_start_pg + i, 201 sizeof(uhci_qh_t), UHCI_QH_ALIGN); 202 } 203 } 204 205 static void 206 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer) 207 { 208 ml->buf_pc = xfer->frbuffers + 0; 209 ml->fix_pc = xfer->buf_fixup; 210 211 ml->buf_offset = 0; 212 213 ml->max_frame_size = xfer->max_frame_size; 214 } 215 216 static void 217 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td) 218 { 219 usbd_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res); 220 221 if (ml->buf_res.length < td->len) { 222 223 /* need to do a fixup */ 224 225 usbd_get_page(ml->fix_pc, 0, &ml->fix_res); 226 227 td->td_buffer = htole32(ml->fix_res.physaddr); 228 229 /* 230 * The UHCI driver cannot handle 231 * page crossings, so a fixup is 232 * needed: 233 * 234 * +----+----+ - - - 235 * | YYY|Y | 236 * +----+----+ - - - 237 * \ \ 238 * \ \ 239 * +----+ 240 * |YYYY| (fixup) 241 * +----+ 242 */ 243 244 if ((td->td_token & htole32(UHCI_TD_PID)) == 245 htole32(UHCI_TD_PID_IN)) { 246 td->fix_pc = ml->fix_pc; 247 usb_pc_cpu_invalidate(ml->fix_pc); 248 249 } else { 250 td->fix_pc = NULL; 251 252 /* copy data to fixup location */ 253 254 usbd_copy_out(ml->buf_pc, ml->buf_offset, 255 ml->fix_res.buffer, td->len); 256 257 usb_pc_cpu_flush(ml->fix_pc); 258 } 259 260 /* prepare next fixup */ 261 262 ml->fix_pc++; 263 264 } else { 265 266 td->td_buffer = htole32(ml->buf_res.physaddr); 267 td->fix_pc = NULL; 268 } 269 270 /* prepare next data location */ 271 272 ml->buf_offset += td->len; 273 } 274 275 /* 276 * Return values: 277 * 0: Success 278 * Else: Failure 279 */ 280 static uint8_t 281 uhci_restart(uhci_softc_t *sc) 282 { 283 struct usb_page_search buf_res; 284 285 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 286 287 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) { 288 DPRINTFN(2, "Already started\n"); 289 return (0); 290 } 291 292 DPRINTFN(2, "Restarting\n"); 293 294 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 295 296 /* Reload fresh base address */ 297 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr); 298 299 /* 300 * Assume 64 byte packets at frame end and start HC controller: 301 */ 302 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS)); 303 304 /* wait 10 milliseconds */ 305 306 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 307 308 /* check that controller has started */ 309 310 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 311 DPRINTFN(2, "Failed\n"); 312 return (1); 313 } 314 return (0); 315 } 316 317 void 318 uhci_reset(uhci_softc_t *sc) 319 { 320 uint16_t n; 321 322 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 323 324 DPRINTF("resetting the HC\n"); 325 326 /* disable interrupts */ 327 328 UWRITE2(sc, UHCI_INTR, 0); 329 330 /* global reset */ 331 332 UHCICMD(sc, UHCI_CMD_GRESET); 333 334 /* wait */ 335 336 usb_pause_mtx(&sc->sc_bus.bus_mtx, 337 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 338 339 /* terminate all transfers */ 340 341 UHCICMD(sc, UHCI_CMD_HCRESET); 342 343 /* the reset bit goes low when the controller is done */ 344 345 n = UHCI_RESET_TIMEOUT; 346 while (n--) { 347 /* wait one millisecond */ 348 349 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 350 351 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) { 352 goto done_1; 353 } 354 } 355 356 device_printf(sc->sc_bus.bdev, 357 "controller did not reset\n"); 358 359 done_1: 360 361 n = 10; 362 while (n--) { 363 /* wait one millisecond */ 364 365 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 366 367 /* check if HC is stopped */ 368 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) { 369 goto done_2; 370 } 371 } 372 373 device_printf(sc->sc_bus.bdev, 374 "controller did not stop\n"); 375 376 done_2: 377 378 /* reset frame number */ 379 UWRITE2(sc, UHCI_FRNUM, 0); 380 /* set default SOF value */ 381 UWRITE1(sc, UHCI_SOF, 0x40); 382 383 USB_BUS_UNLOCK(&sc->sc_bus); 384 385 /* stop root interrupt */ 386 usb_callout_drain(&sc->sc_root_intr); 387 388 USB_BUS_LOCK(&sc->sc_bus); 389 } 390 391 static void 392 uhci_start(uhci_softc_t *sc) 393 { 394 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 395 396 DPRINTFN(2, "enabling\n"); 397 398 /* enable interrupts */ 399 400 UWRITE2(sc, UHCI_INTR, 401 (UHCI_INTR_TOCRCIE | 402 UHCI_INTR_RIE | 403 UHCI_INTR_IOCE | 404 UHCI_INTR_SPIE)); 405 406 if (uhci_restart(sc)) { 407 device_printf(sc->sc_bus.bdev, 408 "cannot start HC controller\n"); 409 } 410 411 /* start root interrupt */ 412 uhci_root_intr(sc); 413 } 414 415 static struct uhci_qh * 416 uhci_init_qh(struct usb_page_cache *pc) 417 { 418 struct usb_page_search buf_res; 419 struct uhci_qh *qh; 420 421 usbd_get_page(pc, 0, &buf_res); 422 423 qh = buf_res.buffer; 424 425 qh->qh_self = 426 htole32(buf_res.physaddr) | 427 htole32(UHCI_PTR_QH); 428 429 qh->page_cache = pc; 430 431 return (qh); 432 } 433 434 static struct uhci_td * 435 uhci_init_td(struct usb_page_cache *pc) 436 { 437 struct usb_page_search buf_res; 438 struct uhci_td *td; 439 440 usbd_get_page(pc, 0, &buf_res); 441 442 td = buf_res.buffer; 443 444 td->td_self = 445 htole32(buf_res.physaddr) | 446 htole32(UHCI_PTR_TD); 447 448 td->page_cache = pc; 449 450 return (td); 451 } 452 453 usb_error_t 454 uhci_init(uhci_softc_t *sc) 455 { 456 uint16_t bit; 457 uint16_t x; 458 uint16_t y; 459 460 DPRINTF("start\n"); 461 462 usb_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_mtx, 0); 463 464 #ifdef USB_DEBUG 465 if (uhcidebug > 2) { 466 uhci_dumpregs(sc); 467 } 468 #endif 469 /* 470 * Setup QH's 471 */ 472 sc->sc_ls_ctl_p_last = 473 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc); 474 475 sc->sc_fs_ctl_p_last = 476 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc); 477 478 sc->sc_bulk_p_last = 479 uhci_init_qh(&sc->sc_hw.bulk_start_pc); 480 #if 0 481 sc->sc_reclaim_qh_p = 482 sc->sc_fs_ctl_p_last; 483 #else 484 /* setup reclaim looping point */ 485 sc->sc_reclaim_qh_p = 486 sc->sc_bulk_p_last; 487 #endif 488 489 sc->sc_last_qh_p = 490 uhci_init_qh(&sc->sc_hw.last_qh_pc); 491 492 sc->sc_last_td_p = 493 uhci_init_td(&sc->sc_hw.last_td_pc); 494 495 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 496 sc->sc_isoc_p_last[x] = 497 uhci_init_td(sc->sc_hw.isoc_start_pc + x); 498 } 499 500 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) { 501 sc->sc_intr_p_last[x] = 502 uhci_init_qh(sc->sc_hw.intr_start_pc + x); 503 } 504 505 /* 506 * the QHs are arranged to give poll intervals that are 507 * powers of 2 times 1ms 508 */ 509 bit = UHCI_IFRAMELIST_COUNT / 2; 510 while (bit) { 511 x = bit; 512 while (x & bit) { 513 uhci_qh_t *qh_x; 514 uhci_qh_t *qh_y; 515 516 y = (x ^ bit) | (bit / 2); 517 518 /* 519 * the next QH has half the poll interval 520 */ 521 qh_x = sc->sc_intr_p_last[x]; 522 qh_y = sc->sc_intr_p_last[y]; 523 524 qh_x->h_next = NULL; 525 qh_x->qh_h_next = qh_y->qh_self; 526 qh_x->e_next = NULL; 527 qh_x->qh_e_next = htole32(UHCI_PTR_T); 528 x++; 529 } 530 bit >>= 1; 531 } 532 533 if (1) { 534 uhci_qh_t *qh_ls; 535 uhci_qh_t *qh_intr; 536 537 qh_ls = sc->sc_ls_ctl_p_last; 538 qh_intr = sc->sc_intr_p_last[0]; 539 540 /* start QH for interrupt traffic */ 541 qh_intr->h_next = qh_ls; 542 qh_intr->qh_h_next = qh_ls->qh_self; 543 qh_intr->e_next = 0; 544 qh_intr->qh_e_next = htole32(UHCI_PTR_T); 545 } 546 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) { 547 548 uhci_td_t *td_x; 549 uhci_qh_t *qh_intr; 550 551 td_x = sc->sc_isoc_p_last[x]; 552 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)]; 553 554 /* start TD for isochronous traffic */ 555 td_x->next = NULL; 556 td_x->td_next = qh_intr->qh_self; 557 td_x->td_status = htole32(UHCI_TD_IOS); 558 td_x->td_token = htole32(0); 559 td_x->td_buffer = htole32(0); 560 } 561 562 if (1) { 563 uhci_qh_t *qh_ls; 564 uhci_qh_t *qh_fs; 565 566 qh_ls = sc->sc_ls_ctl_p_last; 567 qh_fs = sc->sc_fs_ctl_p_last; 568 569 /* start QH where low speed control traffic will be queued */ 570 qh_ls->h_next = qh_fs; 571 qh_ls->qh_h_next = qh_fs->qh_self; 572 qh_ls->e_next = 0; 573 qh_ls->qh_e_next = htole32(UHCI_PTR_T); 574 } 575 if (1) { 576 uhci_qh_t *qh_ctl; 577 uhci_qh_t *qh_blk; 578 uhci_qh_t *qh_lst; 579 uhci_td_t *td_lst; 580 581 qh_ctl = sc->sc_fs_ctl_p_last; 582 qh_blk = sc->sc_bulk_p_last; 583 584 /* start QH where full speed control traffic will be queued */ 585 qh_ctl->h_next = qh_blk; 586 qh_ctl->qh_h_next = qh_blk->qh_self; 587 qh_ctl->e_next = 0; 588 qh_ctl->qh_e_next = htole32(UHCI_PTR_T); 589 590 qh_lst = sc->sc_last_qh_p; 591 592 /* start QH where bulk traffic will be queued */ 593 qh_blk->h_next = qh_lst; 594 qh_blk->qh_h_next = qh_lst->qh_self; 595 qh_blk->e_next = 0; 596 qh_blk->qh_e_next = htole32(UHCI_PTR_T); 597 598 td_lst = sc->sc_last_td_p; 599 600 /* end QH which is used for looping the QHs */ 601 qh_lst->h_next = 0; 602 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */ 603 qh_lst->e_next = td_lst; 604 qh_lst->qh_e_next = td_lst->td_self; 605 606 /* 607 * end TD which hangs from the last QH, to avoid a bug in the PIIX 608 * that makes it run berserk otherwise 609 */ 610 td_lst->next = 0; 611 td_lst->td_next = htole32(UHCI_PTR_T); 612 td_lst->td_status = htole32(0); /* inactive */ 613 td_lst->td_token = htole32(0); 614 td_lst->td_buffer = htole32(0); 615 } 616 if (1) { 617 struct usb_page_search buf_res; 618 uint32_t *pframes; 619 620 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 621 622 pframes = buf_res.buffer; 623 624 625 /* 626 * Setup UHCI framelist 627 * 628 * Execution order: 629 * 630 * pframes -> full speed isochronous -> interrupt QH's -> low 631 * speed control -> full speed control -> bulk transfers 632 * 633 */ 634 635 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) { 636 pframes[x] = 637 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self; 638 } 639 } 640 /* flush all cache into memory */ 641 642 usb_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc); 643 644 /* set up the bus struct */ 645 sc->sc_bus.methods = &uhci_bus_methods; 646 647 USB_BUS_LOCK(&sc->sc_bus); 648 /* reset the controller */ 649 uhci_reset(sc); 650 651 /* start the controller */ 652 uhci_start(sc); 653 USB_BUS_UNLOCK(&sc->sc_bus); 654 655 /* catch lost interrupts */ 656 uhci_do_poll(&sc->sc_bus); 657 658 return (0); 659 } 660 661 static void 662 uhci_suspend(uhci_softc_t *sc) 663 { 664 #ifdef USB_DEBUG 665 if (uhcidebug > 2) { 666 uhci_dumpregs(sc); 667 } 668 #endif 669 670 USB_BUS_LOCK(&sc->sc_bus); 671 672 /* stop the controller */ 673 674 uhci_reset(sc); 675 676 /* enter global suspend */ 677 678 UHCICMD(sc, UHCI_CMD_EGSM); 679 680 USB_BUS_UNLOCK(&sc->sc_bus); 681 } 682 683 static void 684 uhci_resume(uhci_softc_t *sc) 685 { 686 USB_BUS_LOCK(&sc->sc_bus); 687 688 /* reset the controller */ 689 690 uhci_reset(sc); 691 692 /* force global resume */ 693 694 UHCICMD(sc, UHCI_CMD_FGR); 695 696 /* and start traffic again */ 697 698 uhci_start(sc); 699 700 USB_BUS_UNLOCK(&sc->sc_bus); 701 702 #ifdef USB_DEBUG 703 if (uhcidebug > 2) 704 uhci_dumpregs(sc); 705 #endif 706 707 /* catch lost interrupts */ 708 uhci_do_poll(&sc->sc_bus); 709 } 710 711 #ifdef USB_DEBUG 712 static void 713 uhci_dumpregs(uhci_softc_t *sc) 714 { 715 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, " 716 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n", 717 device_get_nameunit(sc->sc_bus.bdev), 718 UREAD2(sc, UHCI_CMD), 719 UREAD2(sc, UHCI_STS), 720 UREAD2(sc, UHCI_INTR), 721 UREAD2(sc, UHCI_FRNUM), 722 UREAD4(sc, UHCI_FLBASEADDR), 723 UREAD1(sc, UHCI_SOF), 724 UREAD2(sc, UHCI_PORTSC1), 725 UREAD2(sc, UHCI_PORTSC2)); 726 } 727 728 static uint8_t 729 uhci_dump_td(uhci_td_t *p) 730 { 731 uint32_t td_next; 732 uint32_t td_status; 733 uint32_t td_token; 734 uint8_t temp; 735 736 usb_pc_cpu_invalidate(p->page_cache); 737 738 td_next = le32toh(p->td_next); 739 td_status = le32toh(p->td_status); 740 td_token = le32toh(p->td_token); 741 742 /* 743 * Check whether the link pointer in this TD marks the link pointer 744 * as end of queue: 745 */ 746 temp = ((td_next & UHCI_PTR_T) || (td_next == 0)); 747 748 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x " 749 "token=0x%08x buffer=0x%08x\n", 750 p, 751 le32toh(p->td_self), 752 td_next, 753 td_status, 754 td_token, 755 le32toh(p->td_buffer)); 756 757 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x," 758 "addr=%d,endpt=%d,D=%d,maxlen=%d\n", 759 p, 760 (td_next & 1) ? "-T" : "", 761 (td_next & 2) ? "-Q" : "", 762 (td_next & 4) ? "-VF" : "", 763 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "", 764 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "", 765 (td_status & UHCI_TD_NAK) ? "-NAK" : "", 766 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "", 767 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "", 768 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "", 769 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "", 770 (td_status & UHCI_TD_IOC) ? "-IOC" : "", 771 (td_status & UHCI_TD_IOS) ? "-IOS" : "", 772 (td_status & UHCI_TD_LS) ? "-LS" : "", 773 (td_status & UHCI_TD_SPD) ? "-SPD" : "", 774 UHCI_TD_GET_ERRCNT(td_status), 775 UHCI_TD_GET_ACTLEN(td_status), 776 UHCI_TD_GET_PID(td_token), 777 UHCI_TD_GET_DEVADDR(td_token), 778 UHCI_TD_GET_ENDPT(td_token), 779 UHCI_TD_GET_DT(td_token), 780 UHCI_TD_GET_MAXLEN(td_token)); 781 782 return (temp); 783 } 784 785 static uint8_t 786 uhci_dump_qh(uhci_qh_t *sqh) 787 { 788 uint8_t temp; 789 uint32_t qh_h_next; 790 uint32_t qh_e_next; 791 792 usb_pc_cpu_invalidate(sqh->page_cache); 793 794 qh_h_next = le32toh(sqh->qh_h_next); 795 qh_e_next = le32toh(sqh->qh_e_next); 796 797 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh, 798 le32toh(sqh->qh_self), qh_h_next, qh_e_next); 799 800 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) | 801 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0)); 802 803 return (temp); 804 } 805 806 static void 807 uhci_dump_all(uhci_softc_t *sc) 808 { 809 uhci_dumpregs(sc); 810 uhci_dump_qh(sc->sc_ls_ctl_p_last); 811 uhci_dump_qh(sc->sc_fs_ctl_p_last); 812 uhci_dump_qh(sc->sc_bulk_p_last); 813 uhci_dump_qh(sc->sc_last_qh_p); 814 } 815 816 static void 817 uhci_dump_tds(uhci_td_t *td) 818 { 819 for (; 820 td != NULL; 821 td = td->obj_next) { 822 if (uhci_dump_td(td)) { 823 break; 824 } 825 } 826 } 827 828 #endif 829 830 /* 831 * Let the last QH loop back to the full speed control transfer QH. 832 * This is what intel calls "bandwidth reclamation" and improves 833 * USB performance a lot for some devices. 834 * If we are already looping, just count it. 835 */ 836 static void 837 uhci_add_loop(uhci_softc_t *sc) 838 { 839 struct uhci_qh *qh_lst; 840 struct uhci_qh *qh_rec; 841 842 #ifdef USB_DEBUG 843 if (uhcinoloop) { 844 return; 845 } 846 #endif 847 if (++(sc->sc_loops) == 1) { 848 DPRINTFN(6, "add\n"); 849 850 qh_lst = sc->sc_last_qh_p; 851 qh_rec = sc->sc_reclaim_qh_p; 852 853 /* NOTE: we don't loop back the soft pointer */ 854 855 qh_lst->qh_h_next = qh_rec->qh_self; 856 usb_pc_cpu_flush(qh_lst->page_cache); 857 } 858 } 859 860 static void 861 uhci_rem_loop(uhci_softc_t *sc) 862 { 863 struct uhci_qh *qh_lst; 864 865 #ifdef USB_DEBUG 866 if (uhcinoloop) { 867 return; 868 } 869 #endif 870 if (--(sc->sc_loops) == 0) { 871 DPRINTFN(6, "remove\n"); 872 873 qh_lst = sc->sc_last_qh_p; 874 qh_lst->qh_h_next = htole32(UHCI_PTR_T); 875 usb_pc_cpu_flush(qh_lst->page_cache); 876 } 877 } 878 879 static void 880 uhci_transfer_intr_enqueue(struct usb_xfer *xfer) 881 { 882 /* check for early completion */ 883 if (uhci_check_transfer(xfer)) { 884 return; 885 } 886 /* put transfer on interrupt queue */ 887 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 888 889 /* start timeout, if any */ 890 if (xfer->timeout != 0) { 891 usbd_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout); 892 } 893 } 894 895 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last) 896 static uhci_td_t * 897 _uhci_append_td(uhci_td_t *std, uhci_td_t *last) 898 { 899 DPRINTFN(11, "%p to %p\n", std, last); 900 901 /* (sc->sc_bus.mtx) must be locked */ 902 903 std->next = last->next; 904 std->td_next = last->td_next; 905 906 std->prev = last; 907 908 usb_pc_cpu_flush(std->page_cache); 909 910 /* 911 * the last->next->prev is never followed: std->next->prev = std; 912 */ 913 last->next = std; 914 last->td_next = std->td_self; 915 916 usb_pc_cpu_flush(last->page_cache); 917 918 return (std); 919 } 920 921 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last) 922 static uhci_qh_t * 923 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last) 924 { 925 DPRINTFN(11, "%p to %p\n", sqh, last); 926 927 if (sqh->h_prev != NULL) { 928 /* should not happen */ 929 DPRINTFN(0, "QH already linked!\n"); 930 return (last); 931 } 932 /* (sc->sc_bus.mtx) must be locked */ 933 934 sqh->h_next = last->h_next; 935 sqh->qh_h_next = last->qh_h_next; 936 937 sqh->h_prev = last; 938 939 usb_pc_cpu_flush(sqh->page_cache); 940 941 /* 942 * The "last->h_next->h_prev" is never followed: 943 * 944 * "sqh->h_next->h_prev" = sqh; 945 */ 946 947 last->h_next = sqh; 948 last->qh_h_next = sqh->qh_self; 949 950 usb_pc_cpu_flush(last->page_cache); 951 952 return (sqh); 953 } 954 955 /**/ 956 957 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last) 958 static uhci_td_t * 959 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last) 960 { 961 DPRINTFN(11, "%p from %p\n", std, last); 962 963 /* (sc->sc_bus.mtx) must be locked */ 964 965 std->prev->next = std->next; 966 std->prev->td_next = std->td_next; 967 968 usb_pc_cpu_flush(std->prev->page_cache); 969 970 if (std->next) { 971 std->next->prev = std->prev; 972 usb_pc_cpu_flush(std->next->page_cache); 973 } 974 return ((last == std) ? std->prev : last); 975 } 976 977 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last) 978 static uhci_qh_t * 979 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last) 980 { 981 DPRINTFN(11, "%p from %p\n", sqh, last); 982 983 /* (sc->sc_bus.mtx) must be locked */ 984 985 /* only remove if not removed from a queue */ 986 if (sqh->h_prev) { 987 988 sqh->h_prev->h_next = sqh->h_next; 989 sqh->h_prev->qh_h_next = sqh->qh_h_next; 990 991 usb_pc_cpu_flush(sqh->h_prev->page_cache); 992 993 if (sqh->h_next) { 994 sqh->h_next->h_prev = sqh->h_prev; 995 usb_pc_cpu_flush(sqh->h_next->page_cache); 996 } 997 last = ((last == sqh) ? sqh->h_prev : last); 998 999 sqh->h_prev = 0; 1000 1001 usb_pc_cpu_flush(sqh->page_cache); 1002 } 1003 return (last); 1004 } 1005 1006 static void 1007 uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer) 1008 { 1009 struct usb_page_search res; 1010 uint32_t nframes = xfer->nframes; 1011 uint32_t status; 1012 uint32_t offset = 0; 1013 uint32_t *plen = xfer->frlengths; 1014 uint16_t len = 0; 1015 uhci_td_t *td = xfer->td_transfer_first; 1016 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos]; 1017 1018 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1019 xfer, xfer->endpoint); 1020 1021 /* sync any DMA memory before doing fixups */ 1022 1023 usb_bdma_post_sync(xfer); 1024 1025 while (nframes--) { 1026 if (td == NULL) { 1027 panic("%s:%d: out of TD's\n", 1028 __FUNCTION__, __LINE__); 1029 } 1030 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 1031 pp_last = &sc->sc_isoc_p_last[0]; 1032 } 1033 #ifdef USB_DEBUG 1034 if (uhcidebug > 5) { 1035 DPRINTF("isoc TD\n"); 1036 uhci_dump_td(td); 1037 } 1038 #endif 1039 usb_pc_cpu_invalidate(td->page_cache); 1040 status = le32toh(td->td_status); 1041 1042 len = UHCI_TD_GET_ACTLEN(status); 1043 1044 if (len > *plen) { 1045 len = *plen; 1046 } 1047 if (td->fix_pc) { 1048 1049 usbd_get_page(td->fix_pc, 0, &res); 1050 1051 /* copy data from fixup location to real location */ 1052 1053 usb_pc_cpu_invalidate(td->fix_pc); 1054 1055 usbd_copy_in(xfer->frbuffers, offset, 1056 res.buffer, len); 1057 } 1058 offset += *plen; 1059 1060 *plen = len; 1061 1062 /* remove TD from schedule */ 1063 UHCI_REMOVE_TD(td, *pp_last); 1064 1065 pp_last++; 1066 plen++; 1067 td = td->obj_next; 1068 } 1069 1070 xfer->aframes = xfer->nframes; 1071 } 1072 1073 static usb_error_t 1074 uhci_non_isoc_done_sub(struct usb_xfer *xfer) 1075 { 1076 struct usb_page_search res; 1077 uhci_td_t *td; 1078 uhci_td_t *td_alt_next; 1079 uint32_t status; 1080 uint32_t token; 1081 uint16_t len; 1082 1083 td = xfer->td_transfer_cache; 1084 td_alt_next = td->alt_next; 1085 1086 if (xfer->aframes != xfer->nframes) { 1087 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1088 } 1089 while (1) { 1090 1091 usb_pc_cpu_invalidate(td->page_cache); 1092 status = le32toh(td->td_status); 1093 token = le32toh(td->td_token); 1094 1095 /* 1096 * Verify the status and add 1097 * up the actual length: 1098 */ 1099 1100 len = UHCI_TD_GET_ACTLEN(status); 1101 if (len > td->len) { 1102 /* should not happen */ 1103 DPRINTF("Invalid status length, " 1104 "0x%04x/0x%04x bytes\n", len, td->len); 1105 status |= UHCI_TD_STALLED; 1106 1107 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) { 1108 1109 if (td->fix_pc) { 1110 1111 usbd_get_page(td->fix_pc, 0, &res); 1112 1113 /* 1114 * copy data from fixup location to real 1115 * location 1116 */ 1117 1118 usb_pc_cpu_invalidate(td->fix_pc); 1119 1120 usbd_copy_in(xfer->frbuffers + xfer->aframes, 1121 xfer->frlengths[xfer->aframes], res.buffer, len); 1122 } 1123 /* update actual length */ 1124 1125 xfer->frlengths[xfer->aframes] += len; 1126 } 1127 /* Check for last transfer */ 1128 if (((void *)td) == xfer->td_transfer_last) { 1129 td = NULL; 1130 break; 1131 } 1132 if (status & UHCI_TD_STALLED) { 1133 /* the transfer is finished */ 1134 td = NULL; 1135 break; 1136 } 1137 /* Check for short transfer */ 1138 if (len != td->len) { 1139 if (xfer->flags_int.short_frames_ok) { 1140 /* follow alt next */ 1141 td = td->alt_next; 1142 } else { 1143 /* the transfer is finished */ 1144 td = NULL; 1145 } 1146 break; 1147 } 1148 td = td->obj_next; 1149 1150 if (td->alt_next != td_alt_next) { 1151 /* this USB frame is complete */ 1152 break; 1153 } 1154 } 1155 1156 /* update transfer cache */ 1157 1158 xfer->td_transfer_cache = td; 1159 1160 /* update data toggle */ 1161 1162 xfer->endpoint->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1; 1163 1164 #ifdef USB_DEBUG 1165 if (status & UHCI_TD_ERROR) { 1166 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x " 1167 "status=%s%s%s%s%s%s%s%s%s%s%s\n", 1168 xfer->address, xfer->endpointno, xfer->aframes, 1169 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "", 1170 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "", 1171 (status & UHCI_TD_NAK) ? "[NAK]" : "", 1172 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "", 1173 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "", 1174 (status & UHCI_TD_STALLED) ? "[STALLED]" : "", 1175 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1176 (status & UHCI_TD_IOC) ? "[IOC]" : "", 1177 (status & UHCI_TD_IOS) ? "[IOS]" : "", 1178 (status & UHCI_TD_LS) ? "[LS]" : "", 1179 (status & UHCI_TD_SPD) ? "[SPD]" : ""); 1180 } 1181 #endif 1182 if (status & UHCI_TD_STALLED) { 1183 /* try to separate I/O errors from STALL */ 1184 if (UHCI_TD_GET_ERRCNT(status) == 0) 1185 return (USB_ERR_IOERROR); 1186 return (USB_ERR_STALLED); 1187 } 1188 return (USB_ERR_NORMAL_COMPLETION); 1189 } 1190 1191 static void 1192 uhci_non_isoc_done(struct usb_xfer *xfer) 1193 { 1194 usb_error_t err = 0; 1195 1196 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1197 xfer, xfer->endpoint); 1198 1199 #ifdef USB_DEBUG 1200 if (uhcidebug > 10) { 1201 uhci_dump_tds(xfer->td_transfer_first); 1202 } 1203 #endif 1204 1205 /* sync any DMA memory before doing fixups */ 1206 1207 usb_bdma_post_sync(xfer); 1208 1209 /* reset scanner */ 1210 1211 xfer->td_transfer_cache = xfer->td_transfer_first; 1212 1213 if (xfer->flags_int.control_xfr) { 1214 if (xfer->flags_int.control_hdr) { 1215 1216 err = uhci_non_isoc_done_sub(xfer); 1217 } 1218 xfer->aframes = 1; 1219 1220 if (xfer->td_transfer_cache == NULL) { 1221 goto done; 1222 } 1223 } 1224 while (xfer->aframes != xfer->nframes) { 1225 1226 err = uhci_non_isoc_done_sub(xfer); 1227 xfer->aframes++; 1228 1229 if (xfer->td_transfer_cache == NULL) { 1230 goto done; 1231 } 1232 } 1233 1234 if (xfer->flags_int.control_xfr && 1235 !xfer->flags_int.control_act) { 1236 1237 err = uhci_non_isoc_done_sub(xfer); 1238 } 1239 done: 1240 uhci_device_done(xfer, err); 1241 } 1242 1243 /*------------------------------------------------------------------------* 1244 * uhci_check_transfer_sub 1245 * 1246 * The main purpose of this function is to update the data-toggle 1247 * in case it is wrong. 1248 *------------------------------------------------------------------------*/ 1249 static void 1250 uhci_check_transfer_sub(struct usb_xfer *xfer) 1251 { 1252 uhci_qh_t *qh; 1253 uhci_td_t *td; 1254 uhci_td_t *td_alt_next; 1255 1256 uint32_t td_token; 1257 uint32_t td_self; 1258 1259 td = xfer->td_transfer_cache; 1260 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1261 1262 td_token = td->obj_next->td_token; 1263 td = td->alt_next; 1264 xfer->td_transfer_cache = td; 1265 td_self = td->td_self; 1266 td_alt_next = td->alt_next; 1267 1268 if (xfer->flags_int.control_xfr) 1269 goto skip; /* don't touch the DT value! */ 1270 1271 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1)))) 1272 goto skip; /* data toggle has correct value */ 1273 1274 /* 1275 * The data toggle is wrong and we need to toggle it ! 1276 */ 1277 while (1) { 1278 1279 td->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1280 usb_pc_cpu_flush(td->page_cache); 1281 1282 if (td == xfer->td_transfer_last) { 1283 /* last transfer */ 1284 break; 1285 } 1286 td = td->obj_next; 1287 1288 if (td->alt_next != td_alt_next) { 1289 /* next frame */ 1290 break; 1291 } 1292 } 1293 skip: 1294 1295 /* update the QH */ 1296 qh->qh_e_next = td_self; 1297 usb_pc_cpu_flush(qh->page_cache); 1298 1299 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1300 } 1301 1302 /*------------------------------------------------------------------------* 1303 * uhci_check_transfer 1304 * 1305 * Return values: 1306 * 0: USB transfer is not finished 1307 * Else: USB transfer is finished 1308 *------------------------------------------------------------------------*/ 1309 static uint8_t 1310 uhci_check_transfer(struct usb_xfer *xfer) 1311 { 1312 uint32_t status; 1313 uint32_t token; 1314 uhci_td_t *td; 1315 1316 DPRINTFN(16, "xfer=%p checking transfer\n", xfer); 1317 1318 if (xfer->endpoint->methods == &uhci_device_isoc_methods) { 1319 /* isochronous transfer */ 1320 1321 td = xfer->td_transfer_last; 1322 1323 usb_pc_cpu_invalidate(td->page_cache); 1324 status = le32toh(td->td_status); 1325 1326 /* check also if the first is complete */ 1327 1328 td = xfer->td_transfer_first; 1329 1330 usb_pc_cpu_invalidate(td->page_cache); 1331 status |= le32toh(td->td_status); 1332 1333 if (!(status & UHCI_TD_ACTIVE)) { 1334 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1335 goto transferred; 1336 } 1337 } else { 1338 /* non-isochronous transfer */ 1339 1340 /* 1341 * check whether there is an error somewhere 1342 * in the middle, or whether there was a short 1343 * packet (SPD and not ACTIVE) 1344 */ 1345 td = xfer->td_transfer_cache; 1346 1347 while (1) { 1348 usb_pc_cpu_invalidate(td->page_cache); 1349 status = le32toh(td->td_status); 1350 token = le32toh(td->td_token); 1351 1352 /* 1353 * if there is an active TD the transfer isn't done 1354 */ 1355 if (status & UHCI_TD_ACTIVE) { 1356 /* update cache */ 1357 xfer->td_transfer_cache = td; 1358 goto done; 1359 } 1360 /* 1361 * last transfer descriptor makes the transfer done 1362 */ 1363 if (((void *)td) == xfer->td_transfer_last) { 1364 break; 1365 } 1366 /* 1367 * any kind of error makes the transfer done 1368 */ 1369 if (status & UHCI_TD_STALLED) { 1370 break; 1371 } 1372 /* 1373 * check if we reached the last packet 1374 * or if there is a short packet: 1375 */ 1376 if ((td->td_next == htole32(UHCI_PTR_T)) || 1377 (UHCI_TD_GET_ACTLEN(status) < td->len)) { 1378 1379 if (xfer->flags_int.short_frames_ok) { 1380 /* follow alt next */ 1381 if (td->alt_next) { 1382 /* update cache */ 1383 xfer->td_transfer_cache = td; 1384 uhci_check_transfer_sub(xfer); 1385 goto done; 1386 } 1387 } 1388 /* transfer is done */ 1389 break; 1390 } 1391 td = td->obj_next; 1392 } 1393 uhci_non_isoc_done(xfer); 1394 goto transferred; 1395 } 1396 1397 done: 1398 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1399 return (0); 1400 1401 transferred: 1402 return (1); 1403 } 1404 1405 static void 1406 uhci_interrupt_poll(uhci_softc_t *sc) 1407 { 1408 struct usb_xfer *xfer; 1409 1410 repeat: 1411 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1412 /* 1413 * check if transfer is transferred 1414 */ 1415 if (uhci_check_transfer(xfer)) { 1416 /* queue has been modified */ 1417 goto repeat; 1418 } 1419 } 1420 } 1421 1422 /*------------------------------------------------------------------------* 1423 * uhci_interrupt - UHCI interrupt handler 1424 * 1425 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1426 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1427 * is present ! 1428 *------------------------------------------------------------------------*/ 1429 void 1430 uhci_interrupt(uhci_softc_t *sc) 1431 { 1432 uint32_t status; 1433 1434 USB_BUS_LOCK(&sc->sc_bus); 1435 1436 DPRINTFN(16, "real interrupt\n"); 1437 1438 #ifdef USB_DEBUG 1439 if (uhcidebug > 15) { 1440 uhci_dumpregs(sc); 1441 } 1442 #endif 1443 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS; 1444 if (status == 0) { 1445 /* the interrupt was not for us */ 1446 goto done; 1447 } 1448 if (status & (UHCI_STS_RD | UHCI_STS_HSE | 1449 UHCI_STS_HCPE | UHCI_STS_HCH)) { 1450 1451 if (status & UHCI_STS_RD) { 1452 #ifdef USB_DEBUG 1453 printf("%s: resume detect\n", 1454 __FUNCTION__); 1455 #endif 1456 } 1457 if (status & UHCI_STS_HSE) { 1458 printf("%s: host system error\n", 1459 __FUNCTION__); 1460 } 1461 if (status & UHCI_STS_HCPE) { 1462 printf("%s: host controller process error\n", 1463 __FUNCTION__); 1464 } 1465 if (status & UHCI_STS_HCH) { 1466 /* no acknowledge needed */ 1467 DPRINTF("%s: host controller halted\n", 1468 __FUNCTION__); 1469 #ifdef USB_DEBUG 1470 if (uhcidebug > 0) { 1471 uhci_dump_all(sc); 1472 } 1473 #endif 1474 } 1475 } 1476 /* get acknowledge bits */ 1477 status &= (UHCI_STS_USBINT | 1478 UHCI_STS_USBEI | 1479 UHCI_STS_RD | 1480 UHCI_STS_HSE | 1481 UHCI_STS_HCPE); 1482 1483 if (status == 0) { 1484 /* nothing to acknowledge */ 1485 goto done; 1486 } 1487 /* acknowledge interrupts */ 1488 UWRITE2(sc, UHCI_STS, status); 1489 1490 /* poll all the USB transfers */ 1491 uhci_interrupt_poll(sc); 1492 1493 done: 1494 USB_BUS_UNLOCK(&sc->sc_bus); 1495 } 1496 1497 /* 1498 * called when a request does not complete 1499 */ 1500 static void 1501 uhci_timeout(void *arg) 1502 { 1503 struct usb_xfer *xfer = arg; 1504 1505 DPRINTF("xfer=%p\n", xfer); 1506 1507 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1508 1509 /* transfer is transferred */ 1510 uhci_device_done(xfer, USB_ERR_TIMEOUT); 1511 } 1512 1513 static void 1514 uhci_do_poll(struct usb_bus *bus) 1515 { 1516 struct uhci_softc *sc = UHCI_BUS2SC(bus); 1517 1518 USB_BUS_LOCK(&sc->sc_bus); 1519 uhci_interrupt_poll(sc); 1520 USB_BUS_UNLOCK(&sc->sc_bus); 1521 } 1522 1523 static void 1524 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp) 1525 { 1526 uhci_td_t *td; 1527 uhci_td_t *td_next; 1528 uhci_td_t *td_alt_next; 1529 uint32_t average; 1530 uint32_t len_old; 1531 uint8_t shortpkt_old; 1532 uint8_t precompute; 1533 1534 td_alt_next = NULL; 1535 shortpkt_old = temp->shortpkt; 1536 len_old = temp->len; 1537 precompute = 1; 1538 1539 /* software is used to detect short incoming transfers */ 1540 1541 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) { 1542 temp->td_status |= htole32(UHCI_TD_SPD); 1543 } else { 1544 temp->td_status &= ~htole32(UHCI_TD_SPD); 1545 } 1546 1547 temp->ml.buf_offset = 0; 1548 1549 restart: 1550 1551 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1552 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average)); 1553 1554 td = temp->td; 1555 td_next = temp->td_next; 1556 1557 while (1) { 1558 1559 if (temp->len == 0) { 1560 1561 if (temp->shortpkt) { 1562 break; 1563 } 1564 /* send a Zero Length Packet, ZLP, last */ 1565 1566 temp->shortpkt = 1; 1567 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0)); 1568 average = 0; 1569 1570 } else { 1571 1572 average = temp->average; 1573 1574 if (temp->len < average) { 1575 temp->shortpkt = 1; 1576 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0)); 1577 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len)); 1578 average = temp->len; 1579 } 1580 } 1581 1582 if (td_next == NULL) { 1583 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__); 1584 } 1585 /* get next TD */ 1586 1587 td = td_next; 1588 td_next = td->obj_next; 1589 1590 /* check if we are pre-computing */ 1591 1592 if (precompute) { 1593 1594 /* update remaining length */ 1595 1596 temp->len -= average; 1597 1598 continue; 1599 } 1600 /* fill out current TD */ 1601 1602 td->td_status = temp->td_status; 1603 td->td_token = temp->td_token; 1604 1605 /* update data toggle */ 1606 1607 temp->td_token ^= htole32(UHCI_TD_SET_DT(1)); 1608 1609 if (average == 0) { 1610 1611 td->len = 0; 1612 td->td_buffer = 0; 1613 td->fix_pc = NULL; 1614 1615 } else { 1616 1617 /* update remaining length */ 1618 1619 temp->len -= average; 1620 1621 td->len = average; 1622 1623 /* fill out buffer pointer and do fixup, if any */ 1624 1625 uhci_mem_layout_fixup(&temp->ml, td); 1626 } 1627 1628 td->alt_next = td_alt_next; 1629 1630 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1631 /* we need to receive these frames one by one ! */ 1632 td->td_status |= htole32(UHCI_TD_IOC); 1633 td->td_next = htole32(UHCI_PTR_T); 1634 } else { 1635 if (td_next) { 1636 /* link the current TD with the next one */ 1637 td->td_next = td_next->td_self; 1638 } 1639 } 1640 1641 usb_pc_cpu_flush(td->page_cache); 1642 } 1643 1644 if (precompute) { 1645 precompute = 0; 1646 1647 /* setup alt next pointer, if any */ 1648 if (temp->last_frame) { 1649 td_alt_next = NULL; 1650 } else { 1651 /* we use this field internally */ 1652 td_alt_next = td_next; 1653 } 1654 1655 /* restore */ 1656 temp->shortpkt = shortpkt_old; 1657 temp->len = len_old; 1658 goto restart; 1659 } 1660 temp->td = td; 1661 temp->td_next = td_next; 1662 } 1663 1664 static uhci_td_t * 1665 uhci_setup_standard_chain(struct usb_xfer *xfer) 1666 { 1667 struct uhci_std_temp temp; 1668 uhci_td_t *td; 1669 uint32_t x; 1670 1671 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1672 xfer->address, UE_GET_ADDR(xfer->endpointno), 1673 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1674 1675 temp.average = xfer->max_frame_size; 1676 temp.max_frame_size = xfer->max_frame_size; 1677 1678 /* toggle the DMA set we are using */ 1679 xfer->flags_int.curr_dma_set ^= 1; 1680 1681 /* get next DMA set */ 1682 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1683 xfer->td_transfer_first = td; 1684 xfer->td_transfer_cache = td; 1685 1686 temp.td = NULL; 1687 temp.td_next = td; 1688 temp.last_frame = 0; 1689 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1690 1691 uhci_mem_layout_init(&temp.ml, xfer); 1692 1693 temp.td_status = 1694 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) | 1695 UHCI_TD_ACTIVE)); 1696 1697 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1698 temp.td_status |= htole32(UHCI_TD_LS); 1699 } 1700 temp.td_token = 1701 htole32(UHCI_TD_SET_ENDPT(xfer->endpointno) | 1702 UHCI_TD_SET_DEVADDR(xfer->address)); 1703 1704 if (xfer->endpoint->toggle_next) { 1705 /* DATA1 is next */ 1706 temp.td_token |= htole32(UHCI_TD_SET_DT(1)); 1707 } 1708 /* check if we should prepend a setup message */ 1709 1710 if (xfer->flags_int.control_xfr) { 1711 1712 if (xfer->flags_int.control_hdr) { 1713 1714 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1715 UHCI_TD_SET_ENDPT(0xF)); 1716 temp.td_token |= htole32(UHCI_TD_PID_SETUP | 1717 UHCI_TD_SET_DT(0)); 1718 1719 temp.len = xfer->frlengths[0]; 1720 temp.ml.buf_pc = xfer->frbuffers + 0; 1721 temp.shortpkt = temp.len ? 1 : 0; 1722 /* check for last frame */ 1723 if (xfer->nframes == 1) { 1724 /* no STATUS stage yet, SETUP is last */ 1725 if (xfer->flags_int.control_act) { 1726 temp.last_frame = 1; 1727 temp.setup_alt_next = 0; 1728 } 1729 } 1730 uhci_setup_standard_chain_sub(&temp); 1731 } 1732 x = 1; 1733 } else { 1734 x = 0; 1735 } 1736 1737 while (x != xfer->nframes) { 1738 1739 /* DATA0 / DATA1 message */ 1740 1741 temp.len = xfer->frlengths[x]; 1742 temp.ml.buf_pc = xfer->frbuffers + x; 1743 1744 x++; 1745 1746 if (x == xfer->nframes) { 1747 if (xfer->flags_int.control_xfr) { 1748 /* no STATUS stage yet, DATA is last */ 1749 if (xfer->flags_int.control_act) { 1750 temp.last_frame = 1; 1751 temp.setup_alt_next = 0; 1752 } 1753 } else { 1754 temp.last_frame = 1; 1755 temp.setup_alt_next = 0; 1756 } 1757 } 1758 /* 1759 * Keep previous data toggle, 1760 * device address and endpoint number: 1761 */ 1762 1763 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1764 UHCI_TD_SET_ENDPT(0xF) | 1765 UHCI_TD_SET_DT(1)); 1766 1767 if (temp.len == 0) { 1768 1769 /* make sure that we send an USB packet */ 1770 1771 temp.shortpkt = 0; 1772 1773 } else { 1774 1775 /* regular data transfer */ 1776 1777 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1778 } 1779 1780 /* set endpoint direction */ 1781 1782 temp.td_token |= 1783 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1784 htole32(UHCI_TD_PID_IN) : 1785 htole32(UHCI_TD_PID_OUT); 1786 1787 uhci_setup_standard_chain_sub(&temp); 1788 } 1789 1790 /* check if we should append a status stage */ 1791 1792 if (xfer->flags_int.control_xfr && 1793 !xfer->flags_int.control_act) { 1794 1795 /* 1796 * send a DATA1 message and reverse the current endpoint 1797 * direction 1798 */ 1799 1800 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) | 1801 UHCI_TD_SET_ENDPT(0xF) | 1802 UHCI_TD_SET_DT(1)); 1803 temp.td_token |= 1804 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1805 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) : 1806 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1)); 1807 1808 temp.len = 0; 1809 temp.ml.buf_pc = NULL; 1810 temp.shortpkt = 0; 1811 temp.last_frame = 1; 1812 temp.setup_alt_next = 0; 1813 1814 uhci_setup_standard_chain_sub(&temp); 1815 } 1816 td = temp.td; 1817 1818 /* Ensure that last TD is terminating: */ 1819 td->td_next = htole32(UHCI_PTR_T); 1820 1821 /* set interrupt bit */ 1822 1823 td->td_status |= htole32(UHCI_TD_IOC); 1824 1825 usb_pc_cpu_flush(td->page_cache); 1826 1827 /* must have at least one frame! */ 1828 1829 xfer->td_transfer_last = td; 1830 1831 #ifdef USB_DEBUG 1832 if (uhcidebug > 8) { 1833 DPRINTF("nexttog=%d; data before transfer:\n", 1834 xfer->endpoint->toggle_next); 1835 uhci_dump_tds(xfer->td_transfer_first); 1836 } 1837 #endif 1838 return (xfer->td_transfer_first); 1839 } 1840 1841 /* NOTE: "done" can be run two times in a row, 1842 * from close and from interrupt 1843 */ 1844 1845 static void 1846 uhci_device_done(struct usb_xfer *xfer, usb_error_t error) 1847 { 1848 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1849 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1850 uhci_qh_t *qh; 1851 1852 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1853 1854 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1855 xfer, xfer->endpoint, error); 1856 1857 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1858 if (qh) { 1859 usb_pc_cpu_invalidate(qh->page_cache); 1860 } 1861 if (xfer->flags_int.bandwidth_reclaimed) { 1862 xfer->flags_int.bandwidth_reclaimed = 0; 1863 uhci_rem_loop(sc); 1864 } 1865 if (methods == &uhci_device_bulk_methods) { 1866 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 1867 } 1868 if (methods == &uhci_device_ctrl_methods) { 1869 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1870 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 1871 } else { 1872 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 1873 } 1874 } 1875 if (methods == &uhci_device_intr_methods) { 1876 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 1877 } 1878 /* 1879 * Only finish isochronous transfers once 1880 * which will update "xfer->frlengths". 1881 */ 1882 if (xfer->td_transfer_first && 1883 xfer->td_transfer_last) { 1884 if (methods == &uhci_device_isoc_methods) { 1885 uhci_isoc_done(sc, xfer); 1886 } 1887 xfer->td_transfer_first = NULL; 1888 xfer->td_transfer_last = NULL; 1889 } 1890 /* dequeue transfer and start next transfer */ 1891 usbd_transfer_done(xfer, error); 1892 } 1893 1894 /*------------------------------------------------------------------------* 1895 * uhci bulk support 1896 *------------------------------------------------------------------------*/ 1897 static void 1898 uhci_device_bulk_open(struct usb_xfer *xfer) 1899 { 1900 return; 1901 } 1902 1903 static void 1904 uhci_device_bulk_close(struct usb_xfer *xfer) 1905 { 1906 uhci_device_done(xfer, USB_ERR_CANCELLED); 1907 } 1908 1909 static void 1910 uhci_device_bulk_enter(struct usb_xfer *xfer) 1911 { 1912 return; 1913 } 1914 1915 static void 1916 uhci_device_bulk_start(struct usb_xfer *xfer) 1917 { 1918 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1919 uhci_td_t *td; 1920 uhci_qh_t *qh; 1921 1922 /* setup TD's */ 1923 td = uhci_setup_standard_chain(xfer); 1924 1925 /* setup QH */ 1926 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1927 1928 qh->e_next = td; 1929 qh->qh_e_next = td->td_self; 1930 1931 if (xfer->xroot->udev->flags.self_suspended == 0) { 1932 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 1933 uhci_add_loop(sc); 1934 xfer->flags_int.bandwidth_reclaimed = 1; 1935 } else { 1936 usb_pc_cpu_flush(qh->page_cache); 1937 } 1938 1939 /* put transfer on interrupt queue */ 1940 uhci_transfer_intr_enqueue(xfer); 1941 } 1942 1943 static const struct usb_pipe_methods uhci_device_bulk_methods = 1944 { 1945 .open = uhci_device_bulk_open, 1946 .close = uhci_device_bulk_close, 1947 .enter = uhci_device_bulk_enter, 1948 .start = uhci_device_bulk_start, 1949 }; 1950 1951 /*------------------------------------------------------------------------* 1952 * uhci control support 1953 *------------------------------------------------------------------------*/ 1954 static void 1955 uhci_device_ctrl_open(struct usb_xfer *xfer) 1956 { 1957 return; 1958 } 1959 1960 static void 1961 uhci_device_ctrl_close(struct usb_xfer *xfer) 1962 { 1963 uhci_device_done(xfer, USB_ERR_CANCELLED); 1964 } 1965 1966 static void 1967 uhci_device_ctrl_enter(struct usb_xfer *xfer) 1968 { 1969 return; 1970 } 1971 1972 static void 1973 uhci_device_ctrl_start(struct usb_xfer *xfer) 1974 { 1975 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 1976 uhci_qh_t *qh; 1977 uhci_td_t *td; 1978 1979 /* setup TD's */ 1980 td = uhci_setup_standard_chain(xfer); 1981 1982 /* setup QH */ 1983 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1984 1985 qh->e_next = td; 1986 qh->qh_e_next = td->td_self; 1987 1988 /* 1989 * NOTE: some devices choke on bandwidth- reclamation for control 1990 * transfers 1991 */ 1992 if (xfer->xroot->udev->flags.self_suspended == 0) { 1993 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1994 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 1995 } else { 1996 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 1997 } 1998 } else { 1999 usb_pc_cpu_flush(qh->page_cache); 2000 } 2001 /* put transfer on interrupt queue */ 2002 uhci_transfer_intr_enqueue(xfer); 2003 } 2004 2005 static const struct usb_pipe_methods uhci_device_ctrl_methods = 2006 { 2007 .open = uhci_device_ctrl_open, 2008 .close = uhci_device_ctrl_close, 2009 .enter = uhci_device_ctrl_enter, 2010 .start = uhci_device_ctrl_start, 2011 }; 2012 2013 /*------------------------------------------------------------------------* 2014 * uhci interrupt support 2015 *------------------------------------------------------------------------*/ 2016 static void 2017 uhci_device_intr_open(struct usb_xfer *xfer) 2018 { 2019 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2020 uint16_t best; 2021 uint16_t bit; 2022 uint16_t x; 2023 2024 best = 0; 2025 bit = UHCI_IFRAMELIST_COUNT / 2; 2026 while (bit) { 2027 if (xfer->interval >= bit) { 2028 x = bit; 2029 best = bit; 2030 while (x & bit) { 2031 if (sc->sc_intr_stat[x] < 2032 sc->sc_intr_stat[best]) { 2033 best = x; 2034 } 2035 x++; 2036 } 2037 break; 2038 } 2039 bit >>= 1; 2040 } 2041 2042 sc->sc_intr_stat[best]++; 2043 xfer->qh_pos = best; 2044 2045 DPRINTFN(3, "best=%d interval=%d\n", 2046 best, xfer->interval); 2047 } 2048 2049 static void 2050 uhci_device_intr_close(struct usb_xfer *xfer) 2051 { 2052 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2053 2054 sc->sc_intr_stat[xfer->qh_pos]--; 2055 2056 uhci_device_done(xfer, USB_ERR_CANCELLED); 2057 } 2058 2059 static void 2060 uhci_device_intr_enter(struct usb_xfer *xfer) 2061 { 2062 return; 2063 } 2064 2065 static void 2066 uhci_device_intr_start(struct usb_xfer *xfer) 2067 { 2068 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2069 uhci_qh_t *qh; 2070 uhci_td_t *td; 2071 2072 /* setup TD's */ 2073 td = uhci_setup_standard_chain(xfer); 2074 2075 /* setup QH */ 2076 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2077 2078 qh->e_next = td; 2079 qh->qh_e_next = td->td_self; 2080 2081 if (xfer->xroot->udev->flags.self_suspended == 0) { 2082 /* enter QHs into the controller data structures */ 2083 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 2084 } else { 2085 usb_pc_cpu_flush(qh->page_cache); 2086 } 2087 2088 /* put transfer on interrupt queue */ 2089 uhci_transfer_intr_enqueue(xfer); 2090 } 2091 2092 static const struct usb_pipe_methods uhci_device_intr_methods = 2093 { 2094 .open = uhci_device_intr_open, 2095 .close = uhci_device_intr_close, 2096 .enter = uhci_device_intr_enter, 2097 .start = uhci_device_intr_start, 2098 }; 2099 2100 /*------------------------------------------------------------------------* 2101 * uhci isochronous support 2102 *------------------------------------------------------------------------*/ 2103 static void 2104 uhci_device_isoc_open(struct usb_xfer *xfer) 2105 { 2106 uhci_td_t *td; 2107 uint32_t td_token; 2108 uint8_t ds; 2109 2110 td_token = 2111 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 2112 UHCI_TD_IN(0, xfer->endpointno, xfer->address, 0) : 2113 UHCI_TD_OUT(0, xfer->endpointno, xfer->address, 0); 2114 2115 td_token = htole32(td_token); 2116 2117 /* initialize all TD's */ 2118 2119 for (ds = 0; ds != 2; ds++) { 2120 2121 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2122 2123 /* mark TD as inactive */ 2124 td->td_status = htole32(UHCI_TD_IOS); 2125 td->td_token = td_token; 2126 2127 usb_pc_cpu_flush(td->page_cache); 2128 } 2129 } 2130 } 2131 2132 static void 2133 uhci_device_isoc_close(struct usb_xfer *xfer) 2134 { 2135 uhci_device_done(xfer, USB_ERR_CANCELLED); 2136 } 2137 2138 static void 2139 uhci_device_isoc_enter(struct usb_xfer *xfer) 2140 { 2141 struct uhci_mem_layout ml; 2142 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus); 2143 uint32_t nframes; 2144 uint32_t temp; 2145 uint32_t *plen; 2146 2147 #ifdef USB_DEBUG 2148 uint8_t once = 1; 2149 2150 #endif 2151 uhci_td_t *td; 2152 uhci_td_t *td_last = NULL; 2153 uhci_td_t **pp_last; 2154 2155 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2156 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2157 2158 nframes = UREAD2(sc, UHCI_FRNUM); 2159 2160 temp = (nframes - xfer->endpoint->isoc_next) & 2161 (UHCI_VFRAMELIST_COUNT - 1); 2162 2163 if ((xfer->endpoint->is_synced == 0) || 2164 (temp < xfer->nframes)) { 2165 /* 2166 * If there is data underflow or the pipe queue is empty we 2167 * schedule the transfer a few frames ahead of the current 2168 * frame position. Else two isochronous transfers might 2169 * overlap. 2170 */ 2171 xfer->endpoint->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1); 2172 xfer->endpoint->is_synced = 1; 2173 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2174 } 2175 /* 2176 * compute how many milliseconds the insertion is ahead of the 2177 * current frame position: 2178 */ 2179 temp = (xfer->endpoint->isoc_next - nframes) & 2180 (UHCI_VFRAMELIST_COUNT - 1); 2181 2182 /* 2183 * pre-compute when the isochronous transfer will be finished: 2184 */ 2185 xfer->isoc_time_complete = 2186 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2187 xfer->nframes; 2188 2189 /* get the real number of frames */ 2190 2191 nframes = xfer->nframes; 2192 2193 uhci_mem_layout_init(&ml, xfer); 2194 2195 plen = xfer->frlengths; 2196 2197 /* toggle the DMA set we are using */ 2198 xfer->flags_int.curr_dma_set ^= 1; 2199 2200 /* get next DMA set */ 2201 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2202 xfer->td_transfer_first = td; 2203 2204 pp_last = &sc->sc_isoc_p_last[xfer->endpoint->isoc_next]; 2205 2206 /* store starting position */ 2207 2208 xfer->qh_pos = xfer->endpoint->isoc_next; 2209 2210 while (nframes--) { 2211 if (td == NULL) { 2212 panic("%s:%d: out of TD's\n", 2213 __FUNCTION__, __LINE__); 2214 } 2215 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) { 2216 pp_last = &sc->sc_isoc_p_last[0]; 2217 } 2218 if (*plen > xfer->max_frame_size) { 2219 #ifdef USB_DEBUG 2220 if (once) { 2221 once = 0; 2222 printf("%s: frame length(%d) exceeds %d " 2223 "bytes (frame truncated)\n", 2224 __FUNCTION__, *plen, 2225 xfer->max_frame_size); 2226 } 2227 #endif 2228 *plen = xfer->max_frame_size; 2229 } 2230 /* reuse td_token from last transfer */ 2231 2232 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK); 2233 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen)); 2234 2235 td->len = *plen; 2236 2237 if (td->len == 0) { 2238 /* 2239 * Do not call "uhci_mem_layout_fixup()" when the 2240 * length is zero! 2241 */ 2242 td->td_buffer = 0; 2243 td->fix_pc = NULL; 2244 2245 } else { 2246 2247 /* fill out buffer pointer and do fixup, if any */ 2248 2249 uhci_mem_layout_fixup(&ml, td); 2250 2251 } 2252 2253 /* update status */ 2254 if (nframes == 0) { 2255 td->td_status = htole32 2256 (UHCI_TD_ZERO_ACTLEN 2257 (UHCI_TD_SET_ERRCNT(0) | 2258 UHCI_TD_ACTIVE | 2259 UHCI_TD_IOS | 2260 UHCI_TD_IOC)); 2261 } else { 2262 td->td_status = htole32 2263 (UHCI_TD_ZERO_ACTLEN 2264 (UHCI_TD_SET_ERRCNT(0) | 2265 UHCI_TD_ACTIVE | 2266 UHCI_TD_IOS)); 2267 } 2268 2269 usb_pc_cpu_flush(td->page_cache); 2270 2271 #ifdef USB_DEBUG 2272 if (uhcidebug > 5) { 2273 DPRINTF("TD %d\n", nframes); 2274 uhci_dump_td(td); 2275 } 2276 #endif 2277 /* insert TD into schedule */ 2278 UHCI_APPEND_TD(td, *pp_last); 2279 pp_last++; 2280 2281 plen++; 2282 td_last = td; 2283 td = td->obj_next; 2284 } 2285 2286 xfer->td_transfer_last = td_last; 2287 2288 /* update isoc_next */ 2289 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) & 2290 (UHCI_VFRAMELIST_COUNT - 1); 2291 } 2292 2293 static void 2294 uhci_device_isoc_start(struct usb_xfer *xfer) 2295 { 2296 /* put transfer on interrupt queue */ 2297 uhci_transfer_intr_enqueue(xfer); 2298 } 2299 2300 static const struct usb_pipe_methods uhci_device_isoc_methods = 2301 { 2302 .open = uhci_device_isoc_open, 2303 .close = uhci_device_isoc_close, 2304 .enter = uhci_device_isoc_enter, 2305 .start = uhci_device_isoc_start, 2306 }; 2307 2308 /*------------------------------------------------------------------------* 2309 * uhci root control support 2310 *------------------------------------------------------------------------* 2311 * Simulate a hardware hub by handling all the necessary requests. 2312 *------------------------------------------------------------------------*/ 2313 2314 static const 2315 struct usb_device_descriptor uhci_devd = 2316 { 2317 sizeof(struct usb_device_descriptor), 2318 UDESC_DEVICE, /* type */ 2319 {0x00, 0x01}, /* USB version */ 2320 UDCLASS_HUB, /* class */ 2321 UDSUBCLASS_HUB, /* subclass */ 2322 UDPROTO_FSHUB, /* protocol */ 2323 64, /* max packet */ 2324 {0}, {0}, {0x00, 0x01}, /* device id */ 2325 1, 2, 0, /* string indicies */ 2326 1 /* # of configurations */ 2327 }; 2328 2329 static const struct uhci_config_desc uhci_confd = { 2330 .confd = { 2331 .bLength = sizeof(struct usb_config_descriptor), 2332 .bDescriptorType = UDESC_CONFIG, 2333 .wTotalLength[0] = sizeof(uhci_confd), 2334 .bNumInterface = 1, 2335 .bConfigurationValue = 1, 2336 .iConfiguration = 0, 2337 .bmAttributes = UC_SELF_POWERED, 2338 .bMaxPower = 0 /* max power */ 2339 }, 2340 .ifcd = { 2341 .bLength = sizeof(struct usb_interface_descriptor), 2342 .bDescriptorType = UDESC_INTERFACE, 2343 .bNumEndpoints = 1, 2344 .bInterfaceClass = UICLASS_HUB, 2345 .bInterfaceSubClass = UISUBCLASS_HUB, 2346 .bInterfaceProtocol = UIPROTO_FSHUB, 2347 }, 2348 .endpd = { 2349 .bLength = sizeof(struct usb_endpoint_descriptor), 2350 .bDescriptorType = UDESC_ENDPOINT, 2351 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT, 2352 .bmAttributes = UE_INTERRUPT, 2353 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2354 .bInterval = 255, 2355 }, 2356 }; 2357 2358 static const 2359 struct usb_hub_descriptor_min uhci_hubd_piix = 2360 { 2361 .bDescLength = sizeof(uhci_hubd_piix), 2362 .bDescriptorType = UDESC_HUB, 2363 .bNbrPorts = 2, 2364 .wHubCharacteristics = {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0}, 2365 .bPwrOn2PwrGood = 50, 2366 }; 2367 2368 /* 2369 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also 2370 * enables the port, and also states that SET_FEATURE(PORT_ENABLE) 2371 * should not be used by the USB subsystem. As we cannot issue a 2372 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port 2373 * will be enabled as part of the reset. 2374 * 2375 * On the VT83C572, the port cannot be successfully enabled until the 2376 * outstanding "port enable change" and "connection status change" 2377 * events have been reset. 2378 */ 2379 static usb_error_t 2380 uhci_portreset(uhci_softc_t *sc, uint16_t index) 2381 { 2382 uint16_t port; 2383 uint16_t x; 2384 uint8_t lim; 2385 2386 if (index == 1) 2387 port = UHCI_PORTSC1; 2388 else if (index == 2) 2389 port = UHCI_PORTSC2; 2390 else 2391 return (USB_ERR_IOERROR); 2392 2393 /* 2394 * Before we do anything, turn on SOF messages on the USB 2395 * BUS. Some USB devices do not cope without them! 2396 */ 2397 uhci_restart(sc); 2398 2399 x = URWMASK(UREAD2(sc, port)); 2400 UWRITE2(sc, port, x | UHCI_PORTSC_PR); 2401 2402 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2403 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 2404 2405 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n", 2406 index, UREAD2(sc, port)); 2407 2408 x = URWMASK(UREAD2(sc, port)); 2409 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2410 2411 2412 mtx_unlock(&sc->sc_bus.bus_mtx); 2413 2414 /* 2415 * This delay needs to be exactly 100us, else some USB devices 2416 * fail to attach! 2417 */ 2418 DELAY(100); 2419 2420 mtx_lock(&sc->sc_bus.bus_mtx); 2421 2422 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n", 2423 index, UREAD2(sc, port)); 2424 2425 x = URWMASK(UREAD2(sc, port)); 2426 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2427 2428 for (lim = 0; lim < 12; lim++) { 2429 2430 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2431 USB_MS_TO_TICKS(usb_port_reset_delay)); 2432 2433 x = UREAD2(sc, port); 2434 2435 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n", 2436 index, lim, x); 2437 2438 if (!(x & UHCI_PORTSC_CCS)) { 2439 /* 2440 * No device is connected (or was disconnected 2441 * during reset). Consider the port reset. 2442 * The delay must be long enough to ensure on 2443 * the initial iteration that the device 2444 * connection will have been registered. 50ms 2445 * appears to be sufficient, but 20ms is not. 2446 */ 2447 DPRINTFN(4, "uhci port %d loop %u, device detached\n", 2448 index, lim); 2449 goto done; 2450 } 2451 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) { 2452 /* 2453 * Port enabled changed and/or connection 2454 * status changed were set. Reset either or 2455 * both raised flags (by writing a 1 to that 2456 * bit), and wait again for state to settle. 2457 */ 2458 UWRITE2(sc, port, URWMASK(x) | 2459 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC))); 2460 continue; 2461 } 2462 if (x & UHCI_PORTSC_PE) { 2463 /* port is enabled */ 2464 goto done; 2465 } 2466 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE); 2467 } 2468 2469 DPRINTFN(2, "uhci port %d reset timed out\n", index); 2470 return (USB_ERR_TIMEOUT); 2471 2472 done: 2473 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n", 2474 index, UREAD2(sc, port)); 2475 2476 sc->sc_isreset = 1; 2477 return (USB_ERR_NORMAL_COMPLETION); 2478 } 2479 2480 static usb_error_t 2481 uhci_roothub_exec(struct usb_device *udev, 2482 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2483 { 2484 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 2485 const void *ptr; 2486 const char *str_ptr; 2487 uint16_t x; 2488 uint16_t port; 2489 uint16_t value; 2490 uint16_t index; 2491 uint16_t status; 2492 uint16_t change; 2493 uint16_t len; 2494 usb_error_t err; 2495 2496 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2497 2498 /* buffer reset */ 2499 ptr = (const void *)&sc->sc_hub_desc.temp; 2500 len = 0; 2501 err = 0; 2502 2503 value = UGETW(req->wValue); 2504 index = UGETW(req->wIndex); 2505 2506 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2507 "wValue=0x%04x wIndex=0x%04x\n", 2508 req->bmRequestType, req->bRequest, 2509 UGETW(req->wLength), value, index); 2510 2511 #define C(x,y) ((x) | ((y) << 8)) 2512 switch (C(req->bRequest, req->bmRequestType)) { 2513 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2514 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2515 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2516 /* 2517 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2518 * for the integrated root hub. 2519 */ 2520 break; 2521 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2522 len = 1; 2523 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2524 break; 2525 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2526 switch (value >> 8) { 2527 case UDESC_DEVICE: 2528 if ((value & 0xff) != 0) { 2529 err = USB_ERR_IOERROR; 2530 goto done; 2531 } 2532 len = sizeof(uhci_devd); 2533 ptr = (const void *)&uhci_devd; 2534 break; 2535 2536 case UDESC_CONFIG: 2537 if ((value & 0xff) != 0) { 2538 err = USB_ERR_IOERROR; 2539 goto done; 2540 } 2541 len = sizeof(uhci_confd); 2542 ptr = (const void *)&uhci_confd; 2543 break; 2544 2545 case UDESC_STRING: 2546 switch (value & 0xff) { 2547 case 0: /* Language table */ 2548 str_ptr = "\001"; 2549 break; 2550 2551 case 1: /* Vendor */ 2552 str_ptr = sc->sc_vendor; 2553 break; 2554 2555 case 2: /* Product */ 2556 str_ptr = "UHCI root HUB"; 2557 break; 2558 2559 default: 2560 str_ptr = ""; 2561 break; 2562 } 2563 2564 len = usb_make_str_desc 2565 (sc->sc_hub_desc.temp, 2566 sizeof(sc->sc_hub_desc.temp), 2567 str_ptr); 2568 break; 2569 2570 default: 2571 err = USB_ERR_IOERROR; 2572 goto done; 2573 } 2574 break; 2575 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2576 len = 1; 2577 sc->sc_hub_desc.temp[0] = 0; 2578 break; 2579 case C(UR_GET_STATUS, UT_READ_DEVICE): 2580 len = 2; 2581 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2582 break; 2583 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2584 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2585 len = 2; 2586 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2587 break; 2588 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2589 if (value >= UHCI_MAX_DEVICES) { 2590 err = USB_ERR_IOERROR; 2591 goto done; 2592 } 2593 sc->sc_addr = value; 2594 break; 2595 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2596 if ((value != 0) && (value != 1)) { 2597 err = USB_ERR_IOERROR; 2598 goto done; 2599 } 2600 sc->sc_conf = value; 2601 break; 2602 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2603 break; 2604 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2605 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2606 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2607 err = USB_ERR_IOERROR; 2608 goto done; 2609 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2610 break; 2611 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2612 break; 2613 /* Hub requests */ 2614 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2615 break; 2616 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2617 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE " 2618 "port=%d feature=%d\n", 2619 index, value); 2620 if (index == 1) 2621 port = UHCI_PORTSC1; 2622 else if (index == 2) 2623 port = UHCI_PORTSC2; 2624 else { 2625 err = USB_ERR_IOERROR; 2626 goto done; 2627 } 2628 switch (value) { 2629 case UHF_PORT_ENABLE: 2630 x = URWMASK(UREAD2(sc, port)); 2631 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE); 2632 break; 2633 case UHF_PORT_SUSPEND: 2634 x = URWMASK(UREAD2(sc, port)); 2635 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP)); 2636 break; 2637 case UHF_PORT_RESET: 2638 x = URWMASK(UREAD2(sc, port)); 2639 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR); 2640 break; 2641 case UHF_C_PORT_CONNECTION: 2642 x = URWMASK(UREAD2(sc, port)); 2643 UWRITE2(sc, port, x | UHCI_PORTSC_CSC); 2644 break; 2645 case UHF_C_PORT_ENABLE: 2646 x = URWMASK(UREAD2(sc, port)); 2647 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC); 2648 break; 2649 case UHF_C_PORT_OVER_CURRENT: 2650 x = URWMASK(UREAD2(sc, port)); 2651 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC); 2652 break; 2653 case UHF_C_PORT_RESET: 2654 sc->sc_isreset = 0; 2655 err = USB_ERR_NORMAL_COMPLETION; 2656 goto done; 2657 case UHF_C_PORT_SUSPEND: 2658 sc->sc_isresumed &= ~(1 << index); 2659 break; 2660 case UHF_PORT_CONNECTION: 2661 case UHF_PORT_OVER_CURRENT: 2662 case UHF_PORT_POWER: 2663 case UHF_PORT_LOW_SPEED: 2664 default: 2665 err = USB_ERR_IOERROR; 2666 goto done; 2667 } 2668 break; 2669 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 2670 if (index == 1) 2671 port = UHCI_PORTSC1; 2672 else if (index == 2) 2673 port = UHCI_PORTSC2; 2674 else { 2675 err = USB_ERR_IOERROR; 2676 goto done; 2677 } 2678 len = 1; 2679 sc->sc_hub_desc.temp[0] = 2680 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >> 2681 UHCI_PORTSC_LS_SHIFT); 2682 break; 2683 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2684 if ((value & 0xff) != 0) { 2685 err = USB_ERR_IOERROR; 2686 goto done; 2687 } 2688 len = sizeof(uhci_hubd_piix); 2689 ptr = (const void *)&uhci_hubd_piix; 2690 break; 2691 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2692 len = 16; 2693 memset(sc->sc_hub_desc.temp, 0, 16); 2694 break; 2695 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2696 if (index == 1) 2697 port = UHCI_PORTSC1; 2698 else if (index == 2) 2699 port = UHCI_PORTSC2; 2700 else { 2701 err = USB_ERR_IOERROR; 2702 goto done; 2703 } 2704 x = UREAD2(sc, port); 2705 status = change = 0; 2706 if (x & UHCI_PORTSC_CCS) 2707 status |= UPS_CURRENT_CONNECT_STATUS; 2708 if (x & UHCI_PORTSC_CSC) 2709 change |= UPS_C_CONNECT_STATUS; 2710 if (x & UHCI_PORTSC_PE) 2711 status |= UPS_PORT_ENABLED; 2712 if (x & UHCI_PORTSC_POEDC) 2713 change |= UPS_C_PORT_ENABLED; 2714 if (x & UHCI_PORTSC_OCI) 2715 status |= UPS_OVERCURRENT_INDICATOR; 2716 if (x & UHCI_PORTSC_OCIC) 2717 change |= UPS_C_OVERCURRENT_INDICATOR; 2718 if (x & UHCI_PORTSC_LSDA) 2719 status |= UPS_LOW_SPEED; 2720 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) { 2721 /* need to do a write back */ 2722 UWRITE2(sc, port, URWMASK(x)); 2723 2724 /* wait 20ms for resume sequence to complete */ 2725 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 2726 2727 /* clear suspend and resume detect */ 2728 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD | 2729 UHCI_PORTSC_SUSP)); 2730 2731 /* wait a little bit */ 2732 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500); 2733 2734 sc->sc_isresumed |= (1 << index); 2735 2736 } else if (x & UHCI_PORTSC_SUSP) { 2737 status |= UPS_SUSPEND; 2738 } 2739 status |= UPS_PORT_POWER; 2740 if (sc->sc_isresumed & (1 << index)) 2741 change |= UPS_C_SUSPEND; 2742 if (sc->sc_isreset) 2743 change |= UPS_C_PORT_RESET; 2744 USETW(sc->sc_hub_desc.ps.wPortStatus, status); 2745 USETW(sc->sc_hub_desc.ps.wPortChange, change); 2746 len = sizeof(sc->sc_hub_desc.ps); 2747 break; 2748 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2749 err = USB_ERR_IOERROR; 2750 goto done; 2751 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2752 break; 2753 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2754 if (index == 1) 2755 port = UHCI_PORTSC1; 2756 else if (index == 2) 2757 port = UHCI_PORTSC2; 2758 else { 2759 err = USB_ERR_IOERROR; 2760 goto done; 2761 } 2762 switch (value) { 2763 case UHF_PORT_ENABLE: 2764 x = URWMASK(UREAD2(sc, port)); 2765 UWRITE2(sc, port, x | UHCI_PORTSC_PE); 2766 break; 2767 case UHF_PORT_SUSPEND: 2768 x = URWMASK(UREAD2(sc, port)); 2769 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP); 2770 break; 2771 case UHF_PORT_RESET: 2772 err = uhci_portreset(sc, index); 2773 goto done; 2774 case UHF_PORT_POWER: 2775 /* pretend we turned on power */ 2776 err = USB_ERR_NORMAL_COMPLETION; 2777 goto done; 2778 case UHF_C_PORT_CONNECTION: 2779 case UHF_C_PORT_ENABLE: 2780 case UHF_C_PORT_OVER_CURRENT: 2781 case UHF_PORT_CONNECTION: 2782 case UHF_PORT_OVER_CURRENT: 2783 case UHF_PORT_LOW_SPEED: 2784 case UHF_C_PORT_SUSPEND: 2785 case UHF_C_PORT_RESET: 2786 default: 2787 err = USB_ERR_IOERROR; 2788 goto done; 2789 } 2790 break; 2791 default: 2792 err = USB_ERR_IOERROR; 2793 goto done; 2794 } 2795 done: 2796 *plength = len; 2797 *pptr = ptr; 2798 return (err); 2799 } 2800 2801 /* 2802 * This routine is executed periodically and simulates interrupts from 2803 * the root controller interrupt pipe for port status change: 2804 */ 2805 static void 2806 uhci_root_intr(uhci_softc_t *sc) 2807 { 2808 DPRINTFN(21, "\n"); 2809 2810 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2811 2812 sc->sc_hub_idata[0] = 0; 2813 2814 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | 2815 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2816 sc->sc_hub_idata[0] |= 1 << 1; 2817 } 2818 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | 2819 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) { 2820 sc->sc_hub_idata[0] |= 1 << 2; 2821 } 2822 2823 /* restart timer */ 2824 usb_callout_reset(&sc->sc_root_intr, hz, 2825 (void *)&uhci_root_intr, sc); 2826 2827 if (sc->sc_hub_idata[0] != 0) { 2828 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2829 sizeof(sc->sc_hub_idata)); 2830 } 2831 } 2832 2833 static void 2834 uhci_xfer_setup(struct usb_setup_params *parm) 2835 { 2836 struct usb_page_search page_info; 2837 struct usb_page_cache *pc; 2838 uhci_softc_t *sc; 2839 struct usb_xfer *xfer; 2840 void *last_obj; 2841 uint32_t ntd; 2842 uint32_t nqh; 2843 uint32_t nfixup; 2844 uint32_t n; 2845 uint16_t align; 2846 2847 sc = UHCI_BUS2SC(parm->udev->bus); 2848 xfer = parm->curr_xfer; 2849 2850 parm->hc_max_packet_size = 0x500; 2851 parm->hc_max_packet_count = 1; 2852 parm->hc_max_frame_size = 0x500; 2853 2854 /* 2855 * compute ntd and nqh 2856 */ 2857 if (parm->methods == &uhci_device_ctrl_methods) { 2858 xfer->flags_int.bdma_enable = 1; 2859 xfer->flags_int.bdma_no_post_sync = 1; 2860 2861 usbd_transfer_setup_sub(parm); 2862 2863 /* see EHCI HC driver for proof of "ntd" formula */ 2864 2865 nqh = 1; 2866 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2867 + (xfer->max_data_length / xfer->max_frame_size)); 2868 2869 } else if (parm->methods == &uhci_device_bulk_methods) { 2870 xfer->flags_int.bdma_enable = 1; 2871 xfer->flags_int.bdma_no_post_sync = 1; 2872 2873 usbd_transfer_setup_sub(parm); 2874 2875 nqh = 1; 2876 ntd = ((2 * xfer->nframes) 2877 + (xfer->max_data_length / xfer->max_frame_size)); 2878 2879 } else if (parm->methods == &uhci_device_intr_methods) { 2880 xfer->flags_int.bdma_enable = 1; 2881 xfer->flags_int.bdma_no_post_sync = 1; 2882 2883 usbd_transfer_setup_sub(parm); 2884 2885 nqh = 1; 2886 ntd = ((2 * xfer->nframes) 2887 + (xfer->max_data_length / xfer->max_frame_size)); 2888 2889 } else if (parm->methods == &uhci_device_isoc_methods) { 2890 xfer->flags_int.bdma_enable = 1; 2891 xfer->flags_int.bdma_no_post_sync = 1; 2892 2893 usbd_transfer_setup_sub(parm); 2894 2895 nqh = 0; 2896 ntd = xfer->nframes; 2897 2898 } else { 2899 2900 usbd_transfer_setup_sub(parm); 2901 2902 nqh = 0; 2903 ntd = 0; 2904 } 2905 2906 if (parm->err) { 2907 return; 2908 } 2909 /* 2910 * NOTE: the UHCI controller requires that 2911 * every packet must be contiguous on 2912 * the same USB memory page ! 2913 */ 2914 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1; 2915 2916 /* 2917 * Compute a suitable power of two alignment 2918 * for our "max_frame_size" fixup buffer(s): 2919 */ 2920 align = xfer->max_frame_size; 2921 n = 0; 2922 while (align) { 2923 align >>= 1; 2924 n++; 2925 } 2926 2927 /* check for power of two */ 2928 if (!(xfer->max_frame_size & 2929 (xfer->max_frame_size - 1))) { 2930 n--; 2931 } 2932 /* 2933 * We don't allow alignments of 2934 * less than 8 bytes: 2935 * 2936 * NOTE: Allocating using an aligment 2937 * of 1 byte has special meaning! 2938 */ 2939 if (n < 3) { 2940 n = 3; 2941 } 2942 align = (1 << n); 2943 2944 if (usbd_transfer_setup_sub_malloc( 2945 parm, &pc, xfer->max_frame_size, 2946 align, nfixup)) { 2947 parm->err = USB_ERR_NOMEM; 2948 return; 2949 } 2950 xfer->buf_fixup = pc; 2951 2952 alloc_dma_set: 2953 2954 if (parm->err) { 2955 return; 2956 } 2957 last_obj = NULL; 2958 2959 if (usbd_transfer_setup_sub_malloc( 2960 parm, &pc, sizeof(uhci_td_t), 2961 UHCI_TD_ALIGN, ntd)) { 2962 parm->err = USB_ERR_NOMEM; 2963 return; 2964 } 2965 if (parm->buf) { 2966 for (n = 0; n != ntd; n++) { 2967 uhci_td_t *td; 2968 2969 usbd_get_page(pc + n, 0, &page_info); 2970 2971 td = page_info.buffer; 2972 2973 /* init TD */ 2974 if ((parm->methods == &uhci_device_bulk_methods) || 2975 (parm->methods == &uhci_device_ctrl_methods) || 2976 (parm->methods == &uhci_device_intr_methods)) { 2977 /* set depth first bit */ 2978 td->td_self = htole32(page_info.physaddr | 2979 UHCI_PTR_TD | UHCI_PTR_VF); 2980 } else { 2981 td->td_self = htole32(page_info.physaddr | 2982 UHCI_PTR_TD); 2983 } 2984 2985 td->obj_next = last_obj; 2986 td->page_cache = pc + n; 2987 2988 last_obj = td; 2989 2990 usb_pc_cpu_flush(pc + n); 2991 } 2992 } 2993 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2994 2995 last_obj = NULL; 2996 2997 if (usbd_transfer_setup_sub_malloc( 2998 parm, &pc, sizeof(uhci_qh_t), 2999 UHCI_QH_ALIGN, nqh)) { 3000 parm->err = USB_ERR_NOMEM; 3001 return; 3002 } 3003 if (parm->buf) { 3004 for (n = 0; n != nqh; n++) { 3005 uhci_qh_t *qh; 3006 3007 usbd_get_page(pc + n, 0, &page_info); 3008 3009 qh = page_info.buffer; 3010 3011 /* init QH */ 3012 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH); 3013 qh->obj_next = last_obj; 3014 qh->page_cache = pc + n; 3015 3016 last_obj = qh; 3017 3018 usb_pc_cpu_flush(pc + n); 3019 } 3020 } 3021 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3022 3023 if (!xfer->flags_int.curr_dma_set) { 3024 xfer->flags_int.curr_dma_set = 1; 3025 goto alloc_dma_set; 3026 } 3027 } 3028 3029 static void 3030 uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3031 struct usb_endpoint *ep) 3032 { 3033 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus); 3034 3035 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3036 ep, udev->address, 3037 edesc->bEndpointAddress, udev->flags.usb_mode, 3038 sc->sc_addr); 3039 3040 if (udev->device_index != sc->sc_addr) { 3041 switch (edesc->bmAttributes & UE_XFERTYPE) { 3042 case UE_CONTROL: 3043 ep->methods = &uhci_device_ctrl_methods; 3044 break; 3045 case UE_INTERRUPT: 3046 ep->methods = &uhci_device_intr_methods; 3047 break; 3048 case UE_ISOCHRONOUS: 3049 if (udev->speed == USB_SPEED_FULL) { 3050 ep->methods = &uhci_device_isoc_methods; 3051 } 3052 break; 3053 case UE_BULK: 3054 ep->methods = &uhci_device_bulk_methods; 3055 break; 3056 default: 3057 /* do nothing */ 3058 break; 3059 } 3060 } 3061 } 3062 3063 static void 3064 uhci_xfer_unsetup(struct usb_xfer *xfer) 3065 { 3066 return; 3067 } 3068 3069 static void 3070 uhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3071 { 3072 /* 3073 * Wait until hardware has finished any possible use of the 3074 * transfer descriptor(s) and QH 3075 */ 3076 *pus = (1125); /* microseconds */ 3077 } 3078 3079 static void 3080 uhci_device_resume(struct usb_device *udev) 3081 { 3082 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3083 struct usb_xfer *xfer; 3084 const struct usb_pipe_methods *methods; 3085 uhci_qh_t *qh; 3086 3087 DPRINTF("\n"); 3088 3089 USB_BUS_LOCK(udev->bus); 3090 3091 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3092 3093 if (xfer->xroot->udev == udev) { 3094 3095 methods = xfer->endpoint->methods; 3096 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3097 3098 if (methods == &uhci_device_bulk_methods) { 3099 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last); 3100 uhci_add_loop(sc); 3101 xfer->flags_int.bandwidth_reclaimed = 1; 3102 } 3103 if (methods == &uhci_device_ctrl_methods) { 3104 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3105 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last); 3106 } else { 3107 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last); 3108 } 3109 } 3110 if (methods == &uhci_device_intr_methods) { 3111 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3112 } 3113 } 3114 } 3115 3116 USB_BUS_UNLOCK(udev->bus); 3117 3118 return; 3119 } 3120 3121 static void 3122 uhci_device_suspend(struct usb_device *udev) 3123 { 3124 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus); 3125 struct usb_xfer *xfer; 3126 const struct usb_pipe_methods *methods; 3127 uhci_qh_t *qh; 3128 3129 DPRINTF("\n"); 3130 3131 USB_BUS_LOCK(udev->bus); 3132 3133 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3134 3135 if (xfer->xroot->udev == udev) { 3136 3137 methods = xfer->endpoint->methods; 3138 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 3139 3140 if (xfer->flags_int.bandwidth_reclaimed) { 3141 xfer->flags_int.bandwidth_reclaimed = 0; 3142 uhci_rem_loop(sc); 3143 } 3144 if (methods == &uhci_device_bulk_methods) { 3145 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last); 3146 } 3147 if (methods == &uhci_device_ctrl_methods) { 3148 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 3149 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last); 3150 } else { 3151 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last); 3152 } 3153 } 3154 if (methods == &uhci_device_intr_methods) { 3155 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]); 3156 } 3157 } 3158 } 3159 3160 USB_BUS_UNLOCK(udev->bus); 3161 3162 return; 3163 } 3164 3165 static void 3166 uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3167 { 3168 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3169 3170 switch (state) { 3171 case USB_HW_POWER_SUSPEND: 3172 case USB_HW_POWER_SHUTDOWN: 3173 uhci_suspend(sc); 3174 break; 3175 case USB_HW_POWER_RESUME: 3176 uhci_resume(sc); 3177 break; 3178 default: 3179 break; 3180 } 3181 } 3182 3183 static void 3184 uhci_set_hw_power(struct usb_bus *bus) 3185 { 3186 struct uhci_softc *sc = UHCI_BUS2SC(bus); 3187 uint32_t flags; 3188 3189 DPRINTF("\n"); 3190 3191 USB_BUS_LOCK(bus); 3192 3193 flags = bus->hw_power_state; 3194 3195 /* 3196 * WARNING: Some FULL speed USB devices require periodic SOF 3197 * messages! If any USB devices are connected through the 3198 * UHCI, power save will be disabled! 3199 */ 3200 if (flags & (USB_HW_POWER_CONTROL | 3201 USB_HW_POWER_NON_ROOT_HUB | 3202 USB_HW_POWER_BULK | 3203 USB_HW_POWER_INTERRUPT | 3204 USB_HW_POWER_ISOC)) { 3205 DPRINTF("Some USB transfer is " 3206 "active on unit %u.\n", 3207 device_get_unit(sc->sc_bus.bdev)); 3208 uhci_restart(sc); 3209 } else { 3210 DPRINTF("Power save on unit %u.\n", 3211 device_get_unit(sc->sc_bus.bdev)); 3212 UHCICMD(sc, UHCI_CMD_MAXP); 3213 } 3214 3215 USB_BUS_UNLOCK(bus); 3216 3217 return; 3218 } 3219 3220 3221 static const struct usb_bus_methods uhci_bus_methods = 3222 { 3223 .endpoint_init = uhci_ep_init, 3224 .xfer_setup = uhci_xfer_setup, 3225 .xfer_unsetup = uhci_xfer_unsetup, 3226 .get_dma_delay = uhci_get_dma_delay, 3227 .device_resume = uhci_device_resume, 3228 .device_suspend = uhci_device_suspend, 3229 .set_hw_power = uhci_set_hw_power, 3230 .set_hw_power_sleep = uhci_set_hw_power_sleep, 3231 .roothub_exec = uhci_roothub_exec, 3232 .xfer_poll = uhci_do_poll, 3233 }; 3234