1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause 4 * 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart@augustsson.net) at 10 * Carlstedt Research & Technology. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _OHCIREG_H_ 35 #define _OHCIREG_H_ 36 37 /* PCI config registers */ 38 #define PCI_CBMEM 0x10 /* configuration base memory */ 39 #define PCI_INTERFACE_OHCI 0x10 40 41 /* OHCI registers */ 42 #define OHCI_REVISION 0x00 /* OHCI revision */ 43 #define OHCI_REV_LO(rev) ((rev) & 0xf) 44 #define OHCI_REV_HI(rev) (((rev)>>4) & 0xf) 45 #define OHCI_REV_LEGACY(rev) ((rev) & 0x100) 46 #define OHCI_CONTROL 0x04 47 #define OHCI_CBSR_MASK 0x00000003 /* Control/Bulk Service Ratio */ 48 #define OHCI_RATIO_1_1 0x00000000 49 #define OHCI_RATIO_1_2 0x00000001 50 #define OHCI_RATIO_1_3 0x00000002 51 #define OHCI_RATIO_1_4 0x00000003 52 #define OHCI_PLE 0x00000004 /* Periodic List Enable */ 53 #define OHCI_IE 0x00000008 /* Isochronous Enable */ 54 #define OHCI_CLE 0x00000010 /* Control List Enable */ 55 #define OHCI_BLE 0x00000020 /* Bulk List Enable */ 56 #define OHCI_HCFS_MASK 0x000000c0 /* HostControllerFunctionalStat 57 * e */ 58 #define OHCI_HCFS_RESET 0x00000000 59 #define OHCI_HCFS_RESUME 0x00000040 60 #define OHCI_HCFS_OPERATIONAL 0x00000080 61 #define OHCI_HCFS_SUSPEND 0x000000c0 62 #define OHCI_IR 0x00000100 /* Interrupt Routing */ 63 #define OHCI_RWC 0x00000200 /* Remote Wakeup Connected */ 64 #define OHCI_RWE 0x00000400 /* Remote Wakeup Enabled */ 65 #define OHCI_COMMAND_STATUS 0x08 66 #define OHCI_HCR 0x00000001 /* Host Controller Reset */ 67 #define OHCI_CLF 0x00000002 /* Control List Filled */ 68 #define OHCI_BLF 0x00000004 /* Bulk List Filled */ 69 #define OHCI_OCR 0x00000008 /* Ownership Change Request */ 70 #define OHCI_SOC_MASK 0x00030000 /* Scheduling Overrun Count */ 71 #define OHCI_INTERRUPT_STATUS 0x0c 72 #define OHCI_SO 0x00000001 /* Scheduling Overrun */ 73 #define OHCI_WDH 0x00000002 /* Writeback Done Head */ 74 #define OHCI_SF 0x00000004 /* Start of Frame */ 75 #define OHCI_RD 0x00000008 /* Resume Detected */ 76 #define OHCI_UE 0x00000010 /* Unrecoverable Error */ 77 #define OHCI_FNO 0x00000020 /* Frame Number Overflow */ 78 #define OHCI_RHSC 0x00000040 /* Root Hub Status Change */ 79 #define OHCI_OC 0x40000000 /* Ownership Change */ 80 #define OHCI_MIE 0x80000000 /* Master Interrupt Enable */ 81 #define OHCI_INTERRUPT_ENABLE 0x10 82 #define OHCI_INTERRUPT_DISABLE 0x14 83 #define OHCI_HCCA 0x18 84 #define OHCI_PERIOD_CURRENT_ED 0x1c 85 #define OHCI_CONTROL_HEAD_ED 0x20 86 #define OHCI_CONTROL_CURRENT_ED 0x24 87 #define OHCI_BULK_HEAD_ED 0x28 88 #define OHCI_BULK_CURRENT_ED 0x2c 89 #define OHCI_DONE_HEAD 0x30 90 #define OHCI_FM_INTERVAL 0x34 91 #define OHCI_GET_IVAL(s) ((s) & 0x3fff) 92 #define OHCI_GET_FSMPS(s) (((s) >> 16) & 0x7fff) 93 #define OHCI_FIT 0x80000000 94 #define OHCI_FM_REMAINING 0x38 95 #define OHCI_FM_NUMBER 0x3c 96 #define OHCI_PERIODIC_START 0x40 97 #define OHCI_LS_THRESHOLD 0x44 98 #define OHCI_RH_DESCRIPTOR_A 0x48 99 #define OHCI_GET_NDP(s) ((s) & 0xff) 100 #define OHCI_PSM 0x0100 /* Power Switching Mode */ 101 #define OHCI_NPS 0x0200 /* No Power Switching */ 102 #define OHCI_DT 0x0400 /* Device Type */ 103 #define OHCI_OCPM 0x0800 /* Overcurrent Protection Mode */ 104 #define OHCI_NOCP 0x1000 /* No Overcurrent Protection */ 105 #define OHCI_GET_POTPGT(s) ((s) >> 24) 106 #define OHCI_RH_DESCRIPTOR_B 0x4c 107 #define OHCI_RH_STATUS 0x50 108 #define OHCI_LPS 0x00000001 /* Local Power Status */ 109 #define OHCI_OCI 0x00000002 /* OverCurrent Indicator */ 110 #define OHCI_DRWE 0x00008000 /* Device Remote Wakeup Enable */ 111 #define OHCI_LPSC 0x00010000 /* Local Power Status Change */ 112 #define OHCI_CCIC 0x00020000 /* OverCurrent Indicator 113 * Change */ 114 #define OHCI_CRWE 0x80000000 /* Clear Remote Wakeup Enable */ 115 #define OHCI_RH_PORT_STATUS(n) (0x50 + ((n)*4)) /* 1 based indexing */ 116 117 #define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE) 118 #define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | \ 119 OHCI_RD | OHCI_UE | OHCI_FNO | \ 120 OHCI_RHSC | OHCI_OC) 121 #define OHCI_NORMAL_INTRS (OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC) 122 123 #define OHCI_FSMPS(i) (((i-210)*6/7) << 16) 124 #define OHCI_PERIODIC(i) ((i)*9/10) 125 126 #endif /* _OHCIREG_H_ */ 127