1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * USB Open Host Controller driver. 33 * 34 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 35 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 36 */ 37 38 #include <sys/stdint.h> 39 #include <sys/stddef.h> 40 #include <sys/param.h> 41 #include <sys/queue.h> 42 #include <sys/types.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/bus.h> 46 #include <sys/linker_set.h> 47 #include <sys/module.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <sys/condvar.h> 51 #include <sys/sysctl.h> 52 #include <sys/sx.h> 53 #include <sys/unistd.h> 54 #include <sys/callout.h> 55 #include <sys/malloc.h> 56 #include <sys/priv.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 61 #define USB_DEBUG_VAR ohcidebug 62 63 #include <dev/usb/usb_core.h> 64 #include <dev/usb/usb_debug.h> 65 #include <dev/usb/usb_busdma.h> 66 #include <dev/usb/usb_process.h> 67 #include <dev/usb/usb_transfer.h> 68 #include <dev/usb/usb_device.h> 69 #include <dev/usb/usb_hub.h> 70 #include <dev/usb/usb_util.h> 71 72 #include <dev/usb/usb_controller.h> 73 #include <dev/usb/usb_bus.h> 74 #include <dev/usb/controller/ohci.h> 75 #include <dev/usb/controller/ohcireg.h> 76 77 #define OHCI_BUS2SC(bus) \ 78 ((ohci_softc_t *)(((uint8_t *)(bus)) - \ 79 ((uint8_t *)&(((ohci_softc_t *)0)->sc_bus)))) 80 81 #ifdef USB_DEBUG 82 static int ohcidebug = 0; 83 84 SYSCTL_NODE(_hw_usb, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 85 SYSCTL_INT(_hw_usb_ohci, OID_AUTO, debug, CTLFLAG_RW, 86 &ohcidebug, 0, "ohci debug level"); 87 static void ohci_dumpregs(ohci_softc_t *); 88 static void ohci_dump_tds(ohci_td_t *); 89 static uint8_t ohci_dump_td(ohci_td_t *); 90 static void ohci_dump_ed(ohci_ed_t *); 91 static uint8_t ohci_dump_itd(ohci_itd_t *); 92 static void ohci_dump_itds(ohci_itd_t *); 93 94 #endif 95 96 #define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 97 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 98 #define OWRITE1(sc, r, x) \ 99 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 100 #define OWRITE2(sc, r, x) \ 101 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 102 #define OWRITE4(sc, r, x) \ 103 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 104 #define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 105 #define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 106 #define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 107 108 #define OHCI_INTR_ENDPT 1 109 110 extern struct usb_bus_methods ohci_bus_methods; 111 extern struct usb_pipe_methods ohci_device_bulk_methods; 112 extern struct usb_pipe_methods ohci_device_ctrl_methods; 113 extern struct usb_pipe_methods ohci_device_intr_methods; 114 extern struct usb_pipe_methods ohci_device_isoc_methods; 115 116 static void ohci_do_poll(struct usb_bus *bus); 117 static void ohci_device_done(struct usb_xfer *xfer, usb_error_t error); 118 static void ohci_timeout(void *arg); 119 static uint8_t ohci_check_transfer(struct usb_xfer *xfer); 120 static void ohci_root_intr(ohci_softc_t *sc); 121 122 struct ohci_std_temp { 123 struct usb_page_cache *pc; 124 ohci_td_t *td; 125 ohci_td_t *td_next; 126 uint32_t average; 127 uint32_t td_flags; 128 uint32_t len; 129 uint16_t max_frame_size; 130 uint8_t shortpkt; 131 uint8_t setup_alt_next; 132 uint8_t last_frame; 133 }; 134 135 static struct ohci_hcca * 136 ohci_get_hcca(ohci_softc_t *sc) 137 { 138 usb_pc_cpu_invalidate(&sc->sc_hw.hcca_pc); 139 return (sc->sc_hcca_p); 140 } 141 142 void 143 ohci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 144 { 145 struct ohci_softc *sc = OHCI_BUS2SC(bus); 146 uint32_t i; 147 148 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg, 149 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN); 150 151 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg, 152 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 153 154 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 155 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 156 157 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg, 158 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 159 160 for (i = 0; i != OHCI_NO_EDS; i++) { 161 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i, 162 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 163 } 164 } 165 166 static usb_error_t 167 ohci_controller_init(ohci_softc_t *sc) 168 { 169 struct usb_page_search buf_res; 170 uint32_t i; 171 uint32_t ctl; 172 uint32_t ival; 173 uint32_t hcr; 174 uint32_t fm; 175 uint32_t per; 176 uint32_t desca; 177 178 /* Determine in what context we are running. */ 179 ctl = OREAD4(sc, OHCI_CONTROL); 180 if (ctl & OHCI_IR) { 181 /* SMM active, request change */ 182 DPRINTF("SMM active, request owner change\n"); 183 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_OCR); 184 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 185 usb_pause_mtx(NULL, hz / 1000); 186 ctl = OREAD4(sc, OHCI_CONTROL); 187 } 188 if (ctl & OHCI_IR) { 189 device_printf(sc->sc_bus.bdev, 190 "SMM does not respond, resetting\n"); 191 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 192 goto reset; 193 } 194 } else { 195 DPRINTF("cold started\n"); 196 reset: 197 /* controller was cold started */ 198 usb_pause_mtx(NULL, 199 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 200 } 201 202 /* 203 * This reset should not be necessary according to the OHCI spec, but 204 * without it some controllers do not start. 205 */ 206 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 207 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 208 209 usb_pause_mtx(NULL, 210 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 211 212 /* we now own the host controller and the bus has been reset */ 213 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 214 215 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 216 /* nominal time for a reset is 10 us */ 217 for (i = 0; i < 10; i++) { 218 DELAY(10); 219 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 220 if (!hcr) { 221 break; 222 } 223 } 224 if (hcr) { 225 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 226 return (USB_ERR_IOERROR); 227 } 228 #ifdef USB_DEBUG 229 if (ohcidebug > 15) { 230 ohci_dumpregs(sc); 231 } 232 #endif 233 234 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 235 236 /* set up HC registers */ 237 usbd_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 238 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr); 239 240 usbd_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res); 241 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr); 242 243 usbd_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res); 244 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr); 245 246 /* disable all interrupts and then switch on all desired interrupts */ 247 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 248 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 249 /* switch on desired functional features */ 250 ctl = OREAD4(sc, OHCI_CONTROL); 251 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 252 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 253 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 254 /* And finally start it! */ 255 OWRITE4(sc, OHCI_CONTROL, ctl); 256 257 /* 258 * The controller is now OPERATIONAL. Set a some final 259 * registers that should be set earlier, but that the 260 * controller ignores when in the SUSPEND state. 261 */ 262 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 263 fm |= OHCI_FSMPS(ival) | ival; 264 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 265 per = OHCI_PERIODIC(ival); /* 90% periodic */ 266 OWRITE4(sc, OHCI_PERIODIC_START, per); 267 268 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 269 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 270 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 271 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 272 usb_pause_mtx(NULL, 273 USB_MS_TO_TICKS(OHCI_ENABLE_POWER_DELAY)); 274 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 275 276 /* 277 * The AMD756 requires a delay before re-reading the register, 278 * otherwise it will occasionally report 0 ports. 279 */ 280 sc->sc_noport = 0; 281 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) { 282 usb_pause_mtx(NULL, 283 USB_MS_TO_TICKS(OHCI_READ_DESC_DELAY)); 284 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 285 } 286 287 #ifdef USB_DEBUG 288 if (ohcidebug > 5) { 289 ohci_dumpregs(sc); 290 } 291 #endif 292 return (USB_ERR_NORMAL_COMPLETION); 293 } 294 295 static struct ohci_ed * 296 ohci_init_ed(struct usb_page_cache *pc) 297 { 298 struct usb_page_search buf_res; 299 struct ohci_ed *ed; 300 301 usbd_get_page(pc, 0, &buf_res); 302 303 ed = buf_res.buffer; 304 305 ed->ed_self = htole32(buf_res.physaddr); 306 ed->ed_flags = htole32(OHCI_ED_SKIP); 307 ed->page_cache = pc; 308 309 return (ed); 310 } 311 312 usb_error_t 313 ohci_init(ohci_softc_t *sc) 314 { 315 struct usb_page_search buf_res; 316 uint16_t i; 317 uint16_t bit; 318 uint16_t x; 319 uint16_t y; 320 321 DPRINTF("start\n"); 322 323 sc->sc_eintrs = OHCI_NORMAL_INTRS; 324 325 /* 326 * Setup all ED's 327 */ 328 329 sc->sc_ctrl_p_last = 330 ohci_init_ed(&sc->sc_hw.ctrl_start_pc); 331 332 sc->sc_bulk_p_last = 333 ohci_init_ed(&sc->sc_hw.bulk_start_pc); 334 335 sc->sc_isoc_p_last = 336 ohci_init_ed(&sc->sc_hw.isoc_start_pc); 337 338 for (i = 0; i != OHCI_NO_EDS; i++) { 339 sc->sc_intr_p_last[i] = 340 ohci_init_ed(sc->sc_hw.intr_start_pc + i); 341 } 342 343 /* 344 * the QHs are arranged to give poll intervals that are 345 * powers of 2 times 1ms 346 */ 347 bit = OHCI_NO_EDS / 2; 348 while (bit) { 349 x = bit; 350 while (x & bit) { 351 ohci_ed_t *ed_x; 352 ohci_ed_t *ed_y; 353 354 y = (x ^ bit) | (bit / 2); 355 356 /* 357 * the next QH has half the poll interval 358 */ 359 ed_x = sc->sc_intr_p_last[x]; 360 ed_y = sc->sc_intr_p_last[y]; 361 362 ed_x->next = NULL; 363 ed_x->ed_next = ed_y->ed_self; 364 365 x++; 366 } 367 bit >>= 1; 368 } 369 370 if (1) { 371 372 ohci_ed_t *ed_int; 373 ohci_ed_t *ed_isc; 374 375 ed_int = sc->sc_intr_p_last[0]; 376 ed_isc = sc->sc_isoc_p_last; 377 378 /* the last (1ms) QH */ 379 ed_int->next = ed_isc; 380 ed_int->ed_next = ed_isc->ed_self; 381 } 382 usbd_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 383 384 sc->sc_hcca_p = buf_res.buffer; 385 386 /* 387 * Fill HCCA interrupt table. The bit reversal is to get 388 * the tree set up properly to spread the interrupts. 389 */ 390 for (i = 0; i != OHCI_NO_INTRS; i++) { 391 sc->sc_hcca_p->hcca_interrupt_table[i] = 392 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self; 393 } 394 /* flush all cache into memory */ 395 396 usb_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc); 397 398 /* set up the bus struct */ 399 sc->sc_bus.methods = &ohci_bus_methods; 400 401 usb_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.bus_mtx, 0); 402 403 #ifdef USB_DEBUG 404 if (ohcidebug > 15) { 405 for (i = 0; i != OHCI_NO_EDS; i++) { 406 printf("ed#%d ", i); 407 ohci_dump_ed(sc->sc_intr_p_last[i]); 408 } 409 printf("iso "); 410 ohci_dump_ed(sc->sc_isoc_p_last); 411 } 412 #endif 413 414 sc->sc_bus.usbrev = USB_REV_1_0; 415 416 if (ohci_controller_init(sc)) { 417 return (USB_ERR_INVAL); 418 } else { 419 /* catch any lost interrupts */ 420 ohci_do_poll(&sc->sc_bus); 421 return (USB_ERR_NORMAL_COMPLETION); 422 } 423 } 424 425 /* 426 * shut down the controller when the system is going down 427 */ 428 void 429 ohci_detach(struct ohci_softc *sc) 430 { 431 USB_BUS_LOCK(&sc->sc_bus); 432 433 usb_callout_stop(&sc->sc_tmo_rhsc); 434 435 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 436 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 437 438 USB_BUS_UNLOCK(&sc->sc_bus); 439 440 /* XXX let stray task complete */ 441 usb_pause_mtx(NULL, hz / 20); 442 443 usb_callout_drain(&sc->sc_tmo_rhsc); 444 } 445 446 /* NOTE: suspend/resume is called from 447 * interrupt context and cannot sleep! 448 */ 449 void 450 ohci_suspend(ohci_softc_t *sc) 451 { 452 uint32_t ctl; 453 454 USB_BUS_LOCK(&sc->sc_bus); 455 456 #ifdef USB_DEBUG 457 DPRINTF("\n"); 458 if (ohcidebug > 2) { 459 ohci_dumpregs(sc); 460 } 461 #endif 462 463 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 464 if (sc->sc_control == 0) { 465 /* 466 * Preserve register values, in case that APM BIOS 467 * does not recover them. 468 */ 469 sc->sc_control = ctl; 470 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 471 } 472 ctl |= OHCI_HCFS_SUSPEND; 473 OWRITE4(sc, OHCI_CONTROL, ctl); 474 475 usb_pause_mtx(&sc->sc_bus.bus_mtx, 476 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 477 478 USB_BUS_UNLOCK(&sc->sc_bus); 479 } 480 481 void 482 ohci_resume(ohci_softc_t *sc) 483 { 484 uint32_t ctl; 485 486 #ifdef USB_DEBUG 487 DPRINTF("\n"); 488 if (ohcidebug > 2) { 489 ohci_dumpregs(sc); 490 } 491 #endif 492 /* some broken BIOSes never initialize the Controller chip */ 493 ohci_controller_init(sc); 494 495 USB_BUS_LOCK(&sc->sc_bus); 496 if (sc->sc_intre) { 497 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 498 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 499 } 500 if (sc->sc_control) 501 ctl = sc->sc_control; 502 else 503 ctl = OREAD4(sc, OHCI_CONTROL); 504 ctl |= OHCI_HCFS_RESUME; 505 OWRITE4(sc, OHCI_CONTROL, ctl); 506 usb_pause_mtx(&sc->sc_bus.bus_mtx, 507 USB_MS_TO_TICKS(USB_RESUME_DELAY)); 508 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 509 OWRITE4(sc, OHCI_CONTROL, ctl); 510 usb_pause_mtx(&sc->sc_bus.bus_mtx, 511 USB_MS_TO_TICKS(USB_RESUME_RECOVERY)); 512 sc->sc_control = sc->sc_intre = 0; 513 514 USB_BUS_UNLOCK(&sc->sc_bus); 515 516 /* catch any lost interrupts */ 517 ohci_do_poll(&sc->sc_bus); 518 } 519 520 #ifdef USB_DEBUG 521 static void 522 ohci_dumpregs(ohci_softc_t *sc) 523 { 524 struct ohci_hcca *hcca; 525 526 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 527 OREAD4(sc, OHCI_REVISION), 528 OREAD4(sc, OHCI_CONTROL), 529 OREAD4(sc, OHCI_COMMAND_STATUS)); 530 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 531 OREAD4(sc, OHCI_INTERRUPT_STATUS), 532 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 533 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 534 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 535 OREAD4(sc, OHCI_HCCA), 536 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 537 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 538 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 539 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 540 OREAD4(sc, OHCI_BULK_HEAD_ED), 541 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 542 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 543 OREAD4(sc, OHCI_DONE_HEAD), 544 OREAD4(sc, OHCI_FM_INTERVAL), 545 OREAD4(sc, OHCI_FM_REMAINING)); 546 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 547 OREAD4(sc, OHCI_FM_NUMBER), 548 OREAD4(sc, OHCI_PERIODIC_START), 549 OREAD4(sc, OHCI_LS_THRESHOLD)); 550 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 551 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 552 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 553 OREAD4(sc, OHCI_RH_STATUS)); 554 DPRINTF(" port1=0x%08x port2=0x%08x\n", 555 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 556 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 557 558 hcca = ohci_get_hcca(sc); 559 560 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 561 le32toh(hcca->hcca_frame_number), 562 le32toh(hcca->hcca_done_head)); 563 } 564 static void 565 ohci_dump_tds(ohci_td_t *std) 566 { 567 for (; std; std = std->obj_next) { 568 if (ohci_dump_td(std)) { 569 break; 570 } 571 } 572 } 573 574 static uint8_t 575 ohci_dump_td(ohci_td_t *std) 576 { 577 uint32_t td_flags; 578 uint8_t temp; 579 580 usb_pc_cpu_invalidate(std->page_cache); 581 582 td_flags = le32toh(std->td_flags); 583 temp = (std->td_next == 0); 584 585 printf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d " 586 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n", 587 std, le32toh(std->td_self), 588 (td_flags & OHCI_TD_R) ? "-R" : "", 589 (td_flags & OHCI_TD_OUT) ? "-OUT" : "", 590 (td_flags & OHCI_TD_IN) ? "-IN" : "", 591 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "", 592 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "", 593 OHCI_TD_GET_DI(td_flags), 594 OHCI_TD_GET_EC(td_flags), 595 OHCI_TD_GET_CC(td_flags), 596 le32toh(std->td_cbp), 597 le32toh(std->td_next), 598 le32toh(std->td_be)); 599 600 return (temp); 601 } 602 603 static uint8_t 604 ohci_dump_itd(ohci_itd_t *sitd) 605 { 606 uint32_t itd_flags; 607 uint16_t i; 608 uint8_t temp; 609 610 usb_pc_cpu_invalidate(sitd->page_cache); 611 612 itd_flags = le32toh(sitd->itd_flags); 613 temp = (sitd->itd_next == 0); 614 615 printf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n" 616 "bp0=0x%08x next=0x%08x be=0x%08x\n", 617 sitd, le32toh(sitd->itd_self), 618 OHCI_ITD_GET_SF(itd_flags), 619 OHCI_ITD_GET_DI(itd_flags), 620 OHCI_ITD_GET_FC(itd_flags), 621 OHCI_ITD_GET_CC(itd_flags), 622 le32toh(sitd->itd_bp0), 623 le32toh(sitd->itd_next), 624 le32toh(sitd->itd_be)); 625 for (i = 0; i < OHCI_ITD_NOFFSET; i++) { 626 printf("offs[%d]=0x%04x ", i, 627 (uint32_t)le16toh(sitd->itd_offset[i])); 628 } 629 printf("\n"); 630 631 return (temp); 632 } 633 634 static void 635 ohci_dump_itds(ohci_itd_t *sitd) 636 { 637 for (; sitd; sitd = sitd->obj_next) { 638 if (ohci_dump_itd(sitd)) { 639 break; 640 } 641 } 642 } 643 644 static void 645 ohci_dump_ed(ohci_ed_t *sed) 646 { 647 uint32_t ed_flags; 648 uint32_t ed_headp; 649 650 usb_pc_cpu_invalidate(sed->page_cache); 651 652 ed_flags = le32toh(sed->ed_flags); 653 ed_headp = le32toh(sed->ed_headp); 654 655 printf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n" 656 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n", 657 sed, le32toh(sed->ed_self), 658 OHCI_ED_GET_FA(ed_flags), 659 OHCI_ED_GET_EN(ed_flags), 660 OHCI_ED_GET_MAXP(ed_flags), 661 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "", 662 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "", 663 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "", 664 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "", 665 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "", 666 le32toh(sed->ed_tailp), 667 (ed_headp & OHCI_HALTED) ? "-HALTED" : "", 668 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "", 669 le32toh(sed->ed_headp), 670 le32toh(sed->ed_next)); 671 } 672 673 #endif 674 675 static void 676 ohci_transfer_intr_enqueue(struct usb_xfer *xfer) 677 { 678 /* check for early completion */ 679 if (ohci_check_transfer(xfer)) { 680 return; 681 } 682 /* put transfer on interrupt queue */ 683 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 684 685 /* start timeout, if any */ 686 if (xfer->timeout != 0) { 687 usbd_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout); 688 } 689 } 690 691 #define OHCI_APPEND_QH(sed,last) (last) = _ohci_append_qh(sed,last) 692 static ohci_ed_t * 693 _ohci_append_qh(ohci_ed_t *sed, ohci_ed_t *last) 694 { 695 DPRINTFN(11, "%p to %p\n", sed, last); 696 697 if (sed->prev != NULL) { 698 /* should not happen */ 699 DPRINTFN(0, "ED already linked!\n"); 700 return (last); 701 } 702 /* (sc->sc_bus.bus_mtx) must be locked */ 703 704 sed->next = last->next; 705 sed->ed_next = last->ed_next; 706 sed->ed_tailp = 0; 707 708 sed->prev = last; 709 710 usb_pc_cpu_flush(sed->page_cache); 711 712 /* 713 * the last->next->prev is never followed: sed->next->prev = sed; 714 */ 715 716 last->next = sed; 717 last->ed_next = sed->ed_self; 718 719 usb_pc_cpu_flush(last->page_cache); 720 721 return (sed); 722 } 723 724 #define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last) 725 static ohci_ed_t * 726 _ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last) 727 { 728 DPRINTFN(11, "%p from %p\n", sed, last); 729 730 /* (sc->sc_bus.bus_mtx) must be locked */ 731 732 /* only remove if not removed from a queue */ 733 if (sed->prev) { 734 735 sed->prev->next = sed->next; 736 sed->prev->ed_next = sed->ed_next; 737 738 usb_pc_cpu_flush(sed->prev->page_cache); 739 740 if (sed->next) { 741 sed->next->prev = sed->prev; 742 usb_pc_cpu_flush(sed->next->page_cache); 743 } 744 last = ((last == sed) ? sed->prev : last); 745 746 sed->prev = 0; 747 748 usb_pc_cpu_flush(sed->page_cache); 749 } 750 return (last); 751 } 752 753 static void 754 ohci_isoc_done(struct usb_xfer *xfer) 755 { 756 uint8_t nframes; 757 uint32_t *plen = xfer->frlengths; 758 volatile uint16_t *olen; 759 uint16_t len = 0; 760 ohci_itd_t *td = xfer->td_transfer_first; 761 762 while (1) { 763 if (td == NULL) { 764 panic("%s:%d: out of TD's\n", 765 __FUNCTION__, __LINE__); 766 } 767 #ifdef USB_DEBUG 768 if (ohcidebug > 5) { 769 DPRINTF("isoc TD\n"); 770 ohci_dump_itd(td); 771 } 772 #endif 773 usb_pc_cpu_invalidate(td->page_cache); 774 775 nframes = td->frames; 776 olen = &td->itd_offset[0]; 777 778 if (nframes > 8) { 779 nframes = 8; 780 } 781 while (nframes--) { 782 len = le16toh(*olen); 783 784 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) { 785 len = 0; 786 } else { 787 len &= ((1 << 12) - 1); 788 } 789 790 if (len > *plen) { 791 len = 0;/* invalid length */ 792 } 793 *plen = len; 794 plen++; 795 olen++; 796 } 797 798 if (((void *)td) == xfer->td_transfer_last) { 799 break; 800 } 801 td = td->obj_next; 802 } 803 804 xfer->aframes = xfer->nframes; 805 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 806 } 807 808 #ifdef USB_DEBUG 809 static const char *const 810 ohci_cc_strs[] = 811 { 812 "NO_ERROR", 813 "CRC", 814 "BIT_STUFFING", 815 "DATA_TOGGLE_MISMATCH", 816 817 "STALL", 818 "DEVICE_NOT_RESPONDING", 819 "PID_CHECK_FAILURE", 820 "UNEXPECTED_PID", 821 822 "DATA_OVERRUN", 823 "DATA_UNDERRUN", 824 "BUFFER_OVERRUN", 825 "BUFFER_UNDERRUN", 826 827 "reserved", 828 "reserved", 829 "NOT_ACCESSED", 830 "NOT_ACCESSED" 831 }; 832 833 #endif 834 835 static usb_error_t 836 ohci_non_isoc_done_sub(struct usb_xfer *xfer) 837 { 838 ohci_td_t *td; 839 ohci_td_t *td_alt_next; 840 uint32_t temp; 841 uint32_t phy_start; 842 uint32_t phy_end; 843 uint32_t td_flags; 844 uint16_t cc; 845 846 td = xfer->td_transfer_cache; 847 td_alt_next = td->alt_next; 848 td_flags = 0; 849 850 if (xfer->aframes != xfer->nframes) { 851 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 852 } 853 while (1) { 854 855 usb_pc_cpu_invalidate(td->page_cache); 856 phy_start = le32toh(td->td_cbp); 857 td_flags = le32toh(td->td_flags); 858 cc = OHCI_TD_GET_CC(td_flags); 859 860 if (phy_start) { 861 /* 862 * short transfer - compute the number of remaining 863 * bytes in the hardware buffer: 864 */ 865 phy_end = le32toh(td->td_be); 866 temp = (OHCI_PAGE(phy_start ^ phy_end) ? 867 (OHCI_PAGE_SIZE + 1) : 0x0001); 868 temp += OHCI_PAGE_OFFSET(phy_end); 869 temp -= OHCI_PAGE_OFFSET(phy_start); 870 871 if (temp > td->len) { 872 /* guard against corruption */ 873 cc = OHCI_CC_STALL; 874 } else if (xfer->aframes != xfer->nframes) { 875 /* 876 * Sum up total transfer length 877 * in "frlengths[]": 878 */ 879 xfer->frlengths[xfer->aframes] += td->len - temp; 880 } 881 } else { 882 if (xfer->aframes != xfer->nframes) { 883 /* transfer was complete */ 884 xfer->frlengths[xfer->aframes] += td->len; 885 } 886 } 887 /* Check for last transfer */ 888 if (((void *)td) == xfer->td_transfer_last) { 889 td = NULL; 890 break; 891 } 892 /* Check transfer status */ 893 if (cc) { 894 /* the transfer is finished */ 895 td = NULL; 896 break; 897 } 898 /* Check for short transfer */ 899 if (phy_start) { 900 if (xfer->flags_int.short_frames_ok) { 901 /* follow alt next */ 902 td = td->alt_next; 903 } else { 904 /* the transfer is finished */ 905 td = NULL; 906 } 907 break; 908 } 909 td = td->obj_next; 910 911 if (td->alt_next != td_alt_next) { 912 /* this USB frame is complete */ 913 break; 914 } 915 } 916 917 /* update transfer cache */ 918 919 xfer->td_transfer_cache = td; 920 921 DPRINTFN(16, "error cc=%d (%s)\n", 922 cc, ohci_cc_strs[cc]); 923 924 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION : 925 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR); 926 } 927 928 static void 929 ohci_non_isoc_done(struct usb_xfer *xfer) 930 { 931 usb_error_t err = 0; 932 933 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 934 xfer, xfer->endpoint); 935 936 #ifdef USB_DEBUG 937 if (ohcidebug > 10) { 938 ohci_dump_tds(xfer->td_transfer_first); 939 } 940 #endif 941 942 /* reset scanner */ 943 944 xfer->td_transfer_cache = xfer->td_transfer_first; 945 946 if (xfer->flags_int.control_xfr) { 947 948 if (xfer->flags_int.control_hdr) { 949 950 err = ohci_non_isoc_done_sub(xfer); 951 } 952 xfer->aframes = 1; 953 954 if (xfer->td_transfer_cache == NULL) { 955 goto done; 956 } 957 } 958 while (xfer->aframes != xfer->nframes) { 959 960 err = ohci_non_isoc_done_sub(xfer); 961 xfer->aframes++; 962 963 if (xfer->td_transfer_cache == NULL) { 964 goto done; 965 } 966 } 967 968 if (xfer->flags_int.control_xfr && 969 !xfer->flags_int.control_act) { 970 971 err = ohci_non_isoc_done_sub(xfer); 972 } 973 done: 974 ohci_device_done(xfer, err); 975 } 976 977 /*------------------------------------------------------------------------* 978 * ohci_check_transfer_sub 979 *------------------------------------------------------------------------*/ 980 static void 981 ohci_check_transfer_sub(struct usb_xfer *xfer) 982 { 983 ohci_td_t *td; 984 ohci_ed_t *ed; 985 uint32_t phy_start; 986 uint32_t td_flags; 987 uint32_t td_next; 988 uint16_t cc; 989 990 td = xfer->td_transfer_cache; 991 992 while (1) { 993 994 usb_pc_cpu_invalidate(td->page_cache); 995 phy_start = le32toh(td->td_cbp); 996 td_flags = le32toh(td->td_flags); 997 td_next = le32toh(td->td_next); 998 999 /* Check for last transfer */ 1000 if (((void *)td) == xfer->td_transfer_last) { 1001 /* the transfer is finished */ 1002 td = NULL; 1003 break; 1004 } 1005 /* Check transfer status */ 1006 cc = OHCI_TD_GET_CC(td_flags); 1007 if (cc) { 1008 /* the transfer is finished */ 1009 td = NULL; 1010 break; 1011 } 1012 /* 1013 * Check if we reached the last packet 1014 * or if there is a short packet: 1015 */ 1016 1017 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) { 1018 /* follow alt next */ 1019 td = td->alt_next; 1020 break; 1021 } 1022 td = td->obj_next; 1023 } 1024 1025 /* update transfer cache */ 1026 1027 xfer->td_transfer_cache = td; 1028 1029 if (td) { 1030 1031 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1032 1033 ed->ed_headp = td->td_self; 1034 usb_pc_cpu_flush(ed->page_cache); 1035 1036 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1037 1038 /* 1039 * Make sure that the OHCI re-scans the schedule by 1040 * writing the BLF and CLF bits: 1041 */ 1042 1043 if (xfer->xroot->udev->flags.self_suspended) { 1044 /* nothing to do */ 1045 } else if (xfer->endpoint->methods == &ohci_device_bulk_methods) { 1046 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1047 1048 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1049 } else if (xfer->endpoint->methods == &ohci_device_ctrl_methods) { 1050 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1051 1052 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1053 } 1054 } 1055 } 1056 1057 /*------------------------------------------------------------------------* 1058 * ohci_check_transfer 1059 * 1060 * Return values: 1061 * 0: USB transfer is not finished 1062 * Else: USB transfer is finished 1063 *------------------------------------------------------------------------*/ 1064 static uint8_t 1065 ohci_check_transfer(struct usb_xfer *xfer) 1066 { 1067 ohci_ed_t *ed; 1068 uint32_t ed_headp; 1069 uint32_t ed_tailp; 1070 1071 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1072 1073 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1074 1075 usb_pc_cpu_invalidate(ed->page_cache); 1076 ed_headp = le32toh(ed->ed_headp); 1077 ed_tailp = le32toh(ed->ed_tailp); 1078 1079 if ((ed_headp & OHCI_HALTED) || 1080 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) { 1081 if (xfer->endpoint->methods == &ohci_device_isoc_methods) { 1082 /* isochronous transfer */ 1083 ohci_isoc_done(xfer); 1084 } else { 1085 if (xfer->flags_int.short_frames_ok) { 1086 ohci_check_transfer_sub(xfer); 1087 if (xfer->td_transfer_cache) { 1088 /* not finished yet */ 1089 return (0); 1090 } 1091 } 1092 /* store data-toggle */ 1093 if (ed_headp & OHCI_TOGGLECARRY) { 1094 xfer->endpoint->toggle_next = 1; 1095 } else { 1096 xfer->endpoint->toggle_next = 0; 1097 } 1098 1099 /* non-isochronous transfer */ 1100 ohci_non_isoc_done(xfer); 1101 } 1102 return (1); 1103 } 1104 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1105 return (0); 1106 } 1107 1108 static void 1109 ohci_rhsc_enable(ohci_softc_t *sc) 1110 { 1111 DPRINTFN(5, "\n"); 1112 1113 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1114 1115 sc->sc_eintrs |= OHCI_RHSC; 1116 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1117 1118 /* acknowledge any RHSC interrupt */ 1119 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC); 1120 1121 ohci_root_intr(sc); 1122 } 1123 1124 static void 1125 ohci_interrupt_poll(ohci_softc_t *sc) 1126 { 1127 struct usb_xfer *xfer; 1128 1129 repeat: 1130 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1131 /* 1132 * check if transfer is transferred 1133 */ 1134 if (ohci_check_transfer(xfer)) { 1135 /* queue has been modified */ 1136 goto repeat; 1137 } 1138 } 1139 } 1140 1141 /*------------------------------------------------------------------------* 1142 * ohci_interrupt - OHCI interrupt handler 1143 * 1144 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1145 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1146 * is present ! 1147 *------------------------------------------------------------------------*/ 1148 void 1149 ohci_interrupt(ohci_softc_t *sc) 1150 { 1151 struct ohci_hcca *hcca; 1152 uint32_t status; 1153 uint32_t done; 1154 1155 USB_BUS_LOCK(&sc->sc_bus); 1156 1157 hcca = ohci_get_hcca(sc); 1158 1159 DPRINTFN(16, "real interrupt\n"); 1160 1161 #ifdef USB_DEBUG 1162 if (ohcidebug > 15) { 1163 ohci_dumpregs(sc); 1164 } 1165 #endif 1166 1167 done = le32toh(hcca->hcca_done_head); 1168 1169 /* 1170 * The LSb of done is used to inform the HC Driver that an interrupt 1171 * condition exists for both the Done list and for another event 1172 * recorded in HcInterruptStatus. On an interrupt from the HC, the 1173 * HC Driver checks the HccaDoneHead Value. If this value is 0, then 1174 * the interrupt was caused by other than the HccaDoneHead update 1175 * and the HcInterruptStatus register needs to be accessed to 1176 * determine that exact interrupt cause. If HccaDoneHead is nonzero, 1177 * then a Done list update interrupt is indicated and if the LSb of 1178 * done is nonzero, then an additional interrupt event is indicated 1179 * and HcInterruptStatus should be checked to determine its cause. 1180 */ 1181 if (done != 0) { 1182 status = 0; 1183 1184 if (done & ~OHCI_DONE_INTRS) { 1185 status |= OHCI_WDH; 1186 } 1187 if (done & OHCI_DONE_INTRS) { 1188 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1189 } 1190 hcca->hcca_done_head = 0; 1191 1192 usb_pc_cpu_flush(&sc->sc_hw.hcca_pc); 1193 } else { 1194 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH; 1195 } 1196 1197 status &= ~OHCI_MIE; 1198 if (status == 0) { 1199 /* 1200 * nothing to be done (PCI shared 1201 * interrupt) 1202 */ 1203 goto done; 1204 } 1205 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */ 1206 1207 status &= sc->sc_eintrs; 1208 if (status == 0) { 1209 goto done; 1210 } 1211 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) { 1212 #if 0 1213 if (status & OHCI_SO) { 1214 /* XXX do what */ 1215 } 1216 #endif 1217 if (status & OHCI_RD) { 1218 printf("%s: resume detect\n", __FUNCTION__); 1219 /* XXX process resume detect */ 1220 } 1221 if (status & OHCI_UE) { 1222 printf("%s: unrecoverable error, " 1223 "controller halted\n", __FUNCTION__); 1224 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1225 /* XXX what else */ 1226 } 1227 if (status & OHCI_RHSC) { 1228 /* 1229 * Disable RHSC interrupt for now, because it will be 1230 * on until the port has been reset. 1231 */ 1232 sc->sc_eintrs &= ~OHCI_RHSC; 1233 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1234 1235 ohci_root_intr(sc); 1236 1237 /* do not allow RHSC interrupts > 1 per second */ 1238 usb_callout_reset(&sc->sc_tmo_rhsc, hz, 1239 (void *)&ohci_rhsc_enable, sc); 1240 } 1241 } 1242 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO); 1243 if (status != 0) { 1244 /* Block unprocessed interrupts. XXX */ 1245 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status); 1246 sc->sc_eintrs &= ~status; 1247 printf("%s: blocking intrs 0x%x\n", 1248 __FUNCTION__, status); 1249 } 1250 /* poll all the USB transfers */ 1251 ohci_interrupt_poll(sc); 1252 1253 done: 1254 USB_BUS_UNLOCK(&sc->sc_bus); 1255 } 1256 1257 /* 1258 * called when a request does not complete 1259 */ 1260 static void 1261 ohci_timeout(void *arg) 1262 { 1263 struct usb_xfer *xfer = arg; 1264 1265 DPRINTF("xfer=%p\n", xfer); 1266 1267 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1268 1269 /* transfer is transferred */ 1270 ohci_device_done(xfer, USB_ERR_TIMEOUT); 1271 } 1272 1273 static void 1274 ohci_do_poll(struct usb_bus *bus) 1275 { 1276 struct ohci_softc *sc = OHCI_BUS2SC(bus); 1277 1278 USB_BUS_LOCK(&sc->sc_bus); 1279 ohci_interrupt_poll(sc); 1280 USB_BUS_UNLOCK(&sc->sc_bus); 1281 } 1282 1283 static void 1284 ohci_setup_standard_chain_sub(struct ohci_std_temp *temp) 1285 { 1286 struct usb_page_search buf_res; 1287 ohci_td_t *td; 1288 ohci_td_t *td_next; 1289 ohci_td_t *td_alt_next; 1290 uint32_t buf_offset; 1291 uint32_t average; 1292 uint32_t len_old; 1293 uint8_t shortpkt_old; 1294 uint8_t precompute; 1295 1296 td_alt_next = NULL; 1297 buf_offset = 0; 1298 shortpkt_old = temp->shortpkt; 1299 len_old = temp->len; 1300 precompute = 1; 1301 1302 /* software is used to detect short incoming transfers */ 1303 1304 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) { 1305 temp->td_flags |= htole32(OHCI_TD_R); 1306 } else { 1307 temp->td_flags &= ~htole32(OHCI_TD_R); 1308 } 1309 1310 restart: 1311 1312 td = temp->td; 1313 td_next = temp->td_next; 1314 1315 while (1) { 1316 1317 if (temp->len == 0) { 1318 1319 if (temp->shortpkt) { 1320 break; 1321 } 1322 /* send a Zero Length Packet, ZLP, last */ 1323 1324 temp->shortpkt = 1; 1325 average = 0; 1326 1327 } else { 1328 1329 average = temp->average; 1330 1331 if (temp->len < average) { 1332 if (temp->len % temp->max_frame_size) { 1333 temp->shortpkt = 1; 1334 } 1335 average = temp->len; 1336 } 1337 } 1338 1339 if (td_next == NULL) { 1340 panic("%s: out of OHCI transfer descriptors!", __FUNCTION__); 1341 } 1342 /* get next TD */ 1343 1344 td = td_next; 1345 td_next = td->obj_next; 1346 1347 /* check if we are pre-computing */ 1348 1349 if (precompute) { 1350 1351 /* update remaining length */ 1352 1353 temp->len -= average; 1354 1355 continue; 1356 } 1357 /* fill out current TD */ 1358 td->td_flags = temp->td_flags; 1359 1360 /* the next TD uses TOGGLE_CARRY */ 1361 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK); 1362 1363 if (average == 0) { 1364 /* 1365 * The buffer start and end phys addresses should be 1366 * 0x0 for a zero length packet. 1367 */ 1368 td->td_cbp = 0; 1369 td->td_be = 0; 1370 td->len = 0; 1371 1372 } else { 1373 1374 usbd_get_page(temp->pc, buf_offset, &buf_res); 1375 td->td_cbp = htole32(buf_res.physaddr); 1376 buf_offset += (average - 1); 1377 1378 usbd_get_page(temp->pc, buf_offset, &buf_res); 1379 td->td_be = htole32(buf_res.physaddr); 1380 buf_offset++; 1381 1382 td->len = average; 1383 1384 /* update remaining length */ 1385 1386 temp->len -= average; 1387 } 1388 1389 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1390 /* we need to receive these frames one by one ! */ 1391 td->td_flags &= htole32(~OHCI_TD_INTR_MASK); 1392 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1393 td->td_next = htole32(OHCI_TD_NEXT_END); 1394 } else { 1395 if (td_next) { 1396 /* link the current TD with the next one */ 1397 td->td_next = td_next->td_self; 1398 } 1399 } 1400 1401 td->alt_next = td_alt_next; 1402 1403 usb_pc_cpu_flush(td->page_cache); 1404 } 1405 1406 if (precompute) { 1407 precompute = 0; 1408 1409 /* setup alt next pointer, if any */ 1410 if (temp->last_frame) { 1411 /* no alternate next */ 1412 td_alt_next = NULL; 1413 } else { 1414 /* we use this field internally */ 1415 td_alt_next = td_next; 1416 } 1417 1418 /* restore */ 1419 temp->shortpkt = shortpkt_old; 1420 temp->len = len_old; 1421 goto restart; 1422 } 1423 temp->td = td; 1424 temp->td_next = td_next; 1425 } 1426 1427 static void 1428 ohci_setup_standard_chain(struct usb_xfer *xfer, ohci_ed_t **ed_last) 1429 { 1430 struct ohci_std_temp temp; 1431 struct usb_pipe_methods *methods; 1432 ohci_ed_t *ed; 1433 ohci_td_t *td; 1434 uint32_t ed_flags; 1435 uint32_t x; 1436 1437 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1438 xfer->address, UE_GET_ADDR(xfer->endpointno), 1439 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1440 1441 temp.average = xfer->max_hc_frame_size; 1442 temp.max_frame_size = xfer->max_frame_size; 1443 1444 /* toggle the DMA set we are using */ 1445 xfer->flags_int.curr_dma_set ^= 1; 1446 1447 /* get next DMA set */ 1448 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1449 1450 xfer->td_transfer_first = td; 1451 xfer->td_transfer_cache = td; 1452 1453 temp.td = NULL; 1454 temp.td_next = td; 1455 temp.last_frame = 0; 1456 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1457 1458 methods = xfer->endpoint->methods; 1459 1460 /* check if we should prepend a setup message */ 1461 1462 if (xfer->flags_int.control_xfr) { 1463 if (xfer->flags_int.control_hdr) { 1464 1465 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1466 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1467 1468 temp.len = xfer->frlengths[0]; 1469 temp.pc = xfer->frbuffers + 0; 1470 temp.shortpkt = temp.len ? 1 : 0; 1471 /* check for last frame */ 1472 if (xfer->nframes == 1) { 1473 /* no STATUS stage yet, SETUP is last */ 1474 if (xfer->flags_int.control_act) { 1475 temp.last_frame = 1; 1476 temp.setup_alt_next = 0; 1477 } 1478 } 1479 ohci_setup_standard_chain_sub(&temp); 1480 1481 /* 1482 * XXX assume that the setup message is 1483 * contained within one USB packet: 1484 */ 1485 xfer->endpoint->toggle_next = 1; 1486 } 1487 x = 1; 1488 } else { 1489 x = 0; 1490 } 1491 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR); 1492 1493 /* set data toggle */ 1494 1495 if (xfer->endpoint->toggle_next) { 1496 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1497 } else { 1498 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0); 1499 } 1500 1501 /* set endpoint direction */ 1502 1503 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 1504 temp.td_flags |= htole32(OHCI_TD_IN); 1505 } else { 1506 temp.td_flags |= htole32(OHCI_TD_OUT); 1507 } 1508 1509 while (x != xfer->nframes) { 1510 1511 /* DATA0 / DATA1 message */ 1512 1513 temp.len = xfer->frlengths[x]; 1514 temp.pc = xfer->frbuffers + x; 1515 1516 x++; 1517 1518 if (x == xfer->nframes) { 1519 if (xfer->flags_int.control_xfr) { 1520 /* no STATUS stage yet, DATA is last */ 1521 if (xfer->flags_int.control_act) { 1522 temp.last_frame = 1; 1523 temp.setup_alt_next = 0; 1524 } 1525 } else { 1526 temp.last_frame = 1; 1527 temp.setup_alt_next = 0; 1528 } 1529 } 1530 if (temp.len == 0) { 1531 1532 /* make sure that we send an USB packet */ 1533 1534 temp.shortpkt = 0; 1535 1536 } else { 1537 1538 /* regular data transfer */ 1539 1540 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1541 } 1542 1543 ohci_setup_standard_chain_sub(&temp); 1544 } 1545 1546 /* check if we should append a status stage */ 1547 1548 if (xfer->flags_int.control_xfr && 1549 !xfer->flags_int.control_act) { 1550 1551 /* 1552 * Send a DATA1 message and invert the current endpoint 1553 * direction. 1554 */ 1555 1556 /* set endpoint direction and data toggle */ 1557 1558 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 1559 temp.td_flags = htole32(OHCI_TD_OUT | 1560 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1561 } else { 1562 temp.td_flags = htole32(OHCI_TD_IN | 1563 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1564 } 1565 1566 temp.len = 0; 1567 temp.pc = NULL; 1568 temp.shortpkt = 0; 1569 temp.last_frame = 1; 1570 temp.setup_alt_next = 0; 1571 1572 ohci_setup_standard_chain_sub(&temp); 1573 } 1574 td = temp.td; 1575 1576 /* Ensure that last TD is terminating: */ 1577 td->td_next = htole32(OHCI_TD_NEXT_END); 1578 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK); 1579 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1580 1581 usb_pc_cpu_flush(td->page_cache); 1582 1583 /* must have at least one frame! */ 1584 1585 xfer->td_transfer_last = td; 1586 1587 #ifdef USB_DEBUG 1588 if (ohcidebug > 8) { 1589 DPRINTF("nexttog=%d; data before transfer:\n", 1590 xfer->endpoint->toggle_next); 1591 ohci_dump_tds(xfer->td_transfer_first); 1592 } 1593 #endif 1594 1595 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1596 1597 ed_flags = (OHCI_ED_SET_FA(xfer->address) | 1598 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpointno)) | 1599 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1600 1601 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD); 1602 1603 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1604 ed_flags |= OHCI_ED_SPEED; 1605 } 1606 ed->ed_flags = htole32(ed_flags); 1607 1608 td = xfer->td_transfer_first; 1609 1610 ed->ed_headp = td->td_self; 1611 1612 if (xfer->xroot->udev->flags.self_suspended == 0) { 1613 /* the append function will flush the endpoint descriptor */ 1614 OHCI_APPEND_QH(ed, *ed_last); 1615 1616 if (methods == &ohci_device_bulk_methods) { 1617 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1618 1619 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1620 } 1621 if (methods == &ohci_device_ctrl_methods) { 1622 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1623 1624 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1625 } 1626 } else { 1627 usb_pc_cpu_flush(ed->page_cache); 1628 } 1629 } 1630 1631 static void 1632 ohci_root_intr(ohci_softc_t *sc) 1633 { 1634 uint32_t hstatus; 1635 uint16_t i; 1636 uint16_t m; 1637 1638 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1639 1640 /* clear any old interrupt data */ 1641 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 1642 1643 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1644 DPRINTF("sc=%p hstatus=0x%08x\n", 1645 sc, hstatus); 1646 1647 /* set bits */ 1648 m = (sc->sc_noport + 1); 1649 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1650 m = (8 * sizeof(sc->sc_hub_idata)); 1651 } 1652 for (i = 1; i < m; i++) { 1653 /* pick out CHANGE bits from the status register */ 1654 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) { 1655 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1656 DPRINTF("port %d changed\n", i); 1657 } 1658 } 1659 1660 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1661 sizeof(sc->sc_hub_idata)); 1662 } 1663 1664 /* NOTE: "done" can be run two times in a row, 1665 * from close and from interrupt 1666 */ 1667 static void 1668 ohci_device_done(struct usb_xfer *xfer, usb_error_t error) 1669 { 1670 struct usb_pipe_methods *methods = xfer->endpoint->methods; 1671 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1672 ohci_ed_t *ed; 1673 1674 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1675 1676 1677 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 1678 xfer, xfer->endpoint, error); 1679 1680 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1681 if (ed) { 1682 usb_pc_cpu_invalidate(ed->page_cache); 1683 } 1684 if (methods == &ohci_device_bulk_methods) { 1685 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 1686 } 1687 if (methods == &ohci_device_ctrl_methods) { 1688 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 1689 } 1690 if (methods == &ohci_device_intr_methods) { 1691 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 1692 } 1693 if (methods == &ohci_device_isoc_methods) { 1694 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last); 1695 } 1696 xfer->td_transfer_first = NULL; 1697 xfer->td_transfer_last = NULL; 1698 1699 /* dequeue transfer and start next transfer */ 1700 usbd_transfer_done(xfer, error); 1701 } 1702 1703 /*------------------------------------------------------------------------* 1704 * ohci bulk support 1705 *------------------------------------------------------------------------*/ 1706 static void 1707 ohci_device_bulk_open(struct usb_xfer *xfer) 1708 { 1709 return; 1710 } 1711 1712 static void 1713 ohci_device_bulk_close(struct usb_xfer *xfer) 1714 { 1715 ohci_device_done(xfer, USB_ERR_CANCELLED); 1716 } 1717 1718 static void 1719 ohci_device_bulk_enter(struct usb_xfer *xfer) 1720 { 1721 return; 1722 } 1723 1724 static void 1725 ohci_device_bulk_start(struct usb_xfer *xfer) 1726 { 1727 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1728 1729 /* setup TD's and QH */ 1730 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last); 1731 1732 /* put transfer on interrupt queue */ 1733 ohci_transfer_intr_enqueue(xfer); 1734 } 1735 1736 struct usb_pipe_methods ohci_device_bulk_methods = 1737 { 1738 .open = ohci_device_bulk_open, 1739 .close = ohci_device_bulk_close, 1740 .enter = ohci_device_bulk_enter, 1741 .start = ohci_device_bulk_start, 1742 }; 1743 1744 /*------------------------------------------------------------------------* 1745 * ohci control support 1746 *------------------------------------------------------------------------*/ 1747 static void 1748 ohci_device_ctrl_open(struct usb_xfer *xfer) 1749 { 1750 return; 1751 } 1752 1753 static void 1754 ohci_device_ctrl_close(struct usb_xfer *xfer) 1755 { 1756 ohci_device_done(xfer, USB_ERR_CANCELLED); 1757 } 1758 1759 static void 1760 ohci_device_ctrl_enter(struct usb_xfer *xfer) 1761 { 1762 return; 1763 } 1764 1765 static void 1766 ohci_device_ctrl_start(struct usb_xfer *xfer) 1767 { 1768 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1769 1770 /* setup TD's and QH */ 1771 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last); 1772 1773 /* put transfer on interrupt queue */ 1774 ohci_transfer_intr_enqueue(xfer); 1775 } 1776 1777 struct usb_pipe_methods ohci_device_ctrl_methods = 1778 { 1779 .open = ohci_device_ctrl_open, 1780 .close = ohci_device_ctrl_close, 1781 .enter = ohci_device_ctrl_enter, 1782 .start = ohci_device_ctrl_start, 1783 }; 1784 1785 /*------------------------------------------------------------------------* 1786 * ohci interrupt support 1787 *------------------------------------------------------------------------*/ 1788 static void 1789 ohci_device_intr_open(struct usb_xfer *xfer) 1790 { 1791 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1792 uint16_t best; 1793 uint16_t bit; 1794 uint16_t x; 1795 1796 best = 0; 1797 bit = OHCI_NO_EDS / 2; 1798 while (bit) { 1799 if (xfer->interval >= bit) { 1800 x = bit; 1801 best = bit; 1802 while (x & bit) { 1803 if (sc->sc_intr_stat[x] < 1804 sc->sc_intr_stat[best]) { 1805 best = x; 1806 } 1807 x++; 1808 } 1809 break; 1810 } 1811 bit >>= 1; 1812 } 1813 1814 sc->sc_intr_stat[best]++; 1815 xfer->qh_pos = best; 1816 1817 DPRINTFN(3, "best=%d interval=%d\n", 1818 best, xfer->interval); 1819 } 1820 1821 static void 1822 ohci_device_intr_close(struct usb_xfer *xfer) 1823 { 1824 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1825 1826 sc->sc_intr_stat[xfer->qh_pos]--; 1827 1828 ohci_device_done(xfer, USB_ERR_CANCELLED); 1829 } 1830 1831 static void 1832 ohci_device_intr_enter(struct usb_xfer *xfer) 1833 { 1834 return; 1835 } 1836 1837 static void 1838 ohci_device_intr_start(struct usb_xfer *xfer) 1839 { 1840 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1841 1842 /* setup TD's and QH */ 1843 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 1844 1845 /* put transfer on interrupt queue */ 1846 ohci_transfer_intr_enqueue(xfer); 1847 } 1848 1849 struct usb_pipe_methods ohci_device_intr_methods = 1850 { 1851 .open = ohci_device_intr_open, 1852 .close = ohci_device_intr_close, 1853 .enter = ohci_device_intr_enter, 1854 .start = ohci_device_intr_start, 1855 }; 1856 1857 /*------------------------------------------------------------------------* 1858 * ohci isochronous support 1859 *------------------------------------------------------------------------*/ 1860 static void 1861 ohci_device_isoc_open(struct usb_xfer *xfer) 1862 { 1863 return; 1864 } 1865 1866 static void 1867 ohci_device_isoc_close(struct usb_xfer *xfer) 1868 { 1869 /**/ 1870 ohci_device_done(xfer, USB_ERR_CANCELLED); 1871 } 1872 1873 static void 1874 ohci_device_isoc_enter(struct usb_xfer *xfer) 1875 { 1876 struct usb_page_search buf_res; 1877 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1878 struct ohci_hcca *hcca; 1879 uint32_t buf_offset; 1880 uint32_t nframes; 1881 uint32_t ed_flags; 1882 uint32_t *plen; 1883 uint16_t itd_offset[OHCI_ITD_NOFFSET]; 1884 uint16_t length; 1885 uint8_t ncur; 1886 ohci_itd_t *td; 1887 ohci_itd_t *td_last = NULL; 1888 ohci_ed_t *ed; 1889 1890 hcca = ohci_get_hcca(sc); 1891 1892 nframes = le32toh(hcca->hcca_frame_number); 1893 1894 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n", 1895 xfer, xfer->endpoint->isoc_next, xfer->nframes, nframes); 1896 1897 if ((xfer->endpoint->is_synced == 0) || 1898 (((nframes - xfer->endpoint->isoc_next) & 0xFFFF) < xfer->nframes) || 1899 (((xfer->endpoint->isoc_next - nframes) & 0xFFFF) >= 128)) { 1900 /* 1901 * If there is data underflow or the pipe queue is empty we 1902 * schedule the transfer a few frames ahead of the current 1903 * frame position. Else two isochronous transfers might 1904 * overlap. 1905 */ 1906 xfer->endpoint->isoc_next = (nframes + 3) & 0xFFFF; 1907 xfer->endpoint->is_synced = 1; 1908 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1909 } 1910 /* 1911 * compute how many milliseconds the insertion is ahead of the 1912 * current frame position: 1913 */ 1914 buf_offset = ((xfer->endpoint->isoc_next - nframes) & 0xFFFF); 1915 1916 /* 1917 * pre-compute when the isochronous transfer will be finished: 1918 */ 1919 xfer->isoc_time_complete = 1920 (usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 1921 xfer->nframes); 1922 1923 /* get the real number of frames */ 1924 1925 nframes = xfer->nframes; 1926 1927 buf_offset = 0; 1928 1929 plen = xfer->frlengths; 1930 1931 /* toggle the DMA set we are using */ 1932 xfer->flags_int.curr_dma_set ^= 1; 1933 1934 /* get next DMA set */ 1935 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1936 1937 xfer->td_transfer_first = td; 1938 1939 ncur = 0; 1940 length = 0; 1941 1942 while (nframes--) { 1943 if (td == NULL) { 1944 panic("%s:%d: out of TD's\n", 1945 __FUNCTION__, __LINE__); 1946 } 1947 itd_offset[ncur] = length; 1948 buf_offset += *plen; 1949 length += *plen; 1950 plen++; 1951 ncur++; 1952 1953 if ( /* check if the ITD is full */ 1954 (ncur == OHCI_ITD_NOFFSET) || 1955 /* check if we have put more than 4K into the ITD */ 1956 (length & 0xF000) || 1957 /* check if it is the last frame */ 1958 (nframes == 0)) { 1959 1960 /* fill current ITD */ 1961 td->itd_flags = htole32( 1962 OHCI_ITD_NOCC | 1963 OHCI_ITD_SET_SF(xfer->endpoint->isoc_next) | 1964 OHCI_ITD_NOINTR | 1965 OHCI_ITD_SET_FC(ncur)); 1966 1967 td->frames = ncur; 1968 xfer->endpoint->isoc_next += ncur; 1969 1970 if (length == 0) { 1971 /* all zero */ 1972 td->itd_bp0 = 0; 1973 td->itd_be = ~0; 1974 1975 while (ncur--) { 1976 td->itd_offset[ncur] = 1977 htole16(OHCI_ITD_MK_OFFS(0)); 1978 } 1979 } else { 1980 usbd_get_page(xfer->frbuffers, buf_offset - length, &buf_res); 1981 length = OHCI_PAGE_MASK(buf_res.physaddr); 1982 buf_res.physaddr = 1983 OHCI_PAGE(buf_res.physaddr); 1984 td->itd_bp0 = htole32(buf_res.physaddr); 1985 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 1986 td->itd_be = htole32(buf_res.physaddr); 1987 1988 while (ncur--) { 1989 itd_offset[ncur] += length; 1990 itd_offset[ncur] = 1991 OHCI_ITD_MK_OFFS(itd_offset[ncur]); 1992 td->itd_offset[ncur] = 1993 htole16(itd_offset[ncur]); 1994 } 1995 } 1996 ncur = 0; 1997 length = 0; 1998 td_last = td; 1999 td = td->obj_next; 2000 2001 if (td) { 2002 /* link the last TD with the next one */ 2003 td_last->itd_next = td->itd_self; 2004 } 2005 usb_pc_cpu_flush(td_last->page_cache); 2006 } 2007 } 2008 2009 /* update the last TD */ 2010 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR); 2011 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0)); 2012 td_last->itd_next = 0; 2013 2014 usb_pc_cpu_flush(td_last->page_cache); 2015 2016 xfer->td_transfer_last = td_last; 2017 2018 #ifdef USB_DEBUG 2019 if (ohcidebug > 8) { 2020 DPRINTF("data before transfer:\n"); 2021 ohci_dump_itds(xfer->td_transfer_first); 2022 } 2023 #endif 2024 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2025 2026 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2027 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO); 2028 else 2029 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO); 2030 2031 ed_flags |= (OHCI_ED_SET_FA(xfer->address) | 2032 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpointno)) | 2033 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 2034 2035 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 2036 ed_flags |= OHCI_ED_SPEED; 2037 } 2038 ed->ed_flags = htole32(ed_flags); 2039 2040 td = xfer->td_transfer_first; 2041 2042 ed->ed_headp = td->itd_self; 2043 2044 /* isochronous transfers are not affected by suspend / resume */ 2045 /* the append function will flush the endpoint descriptor */ 2046 2047 OHCI_APPEND_QH(ed, sc->sc_isoc_p_last); 2048 } 2049 2050 static void 2051 ohci_device_isoc_start(struct usb_xfer *xfer) 2052 { 2053 /* put transfer on interrupt queue */ 2054 ohci_transfer_intr_enqueue(xfer); 2055 } 2056 2057 struct usb_pipe_methods ohci_device_isoc_methods = 2058 { 2059 .open = ohci_device_isoc_open, 2060 .close = ohci_device_isoc_close, 2061 .enter = ohci_device_isoc_enter, 2062 .start = ohci_device_isoc_start, 2063 }; 2064 2065 /*------------------------------------------------------------------------* 2066 * ohci root control support 2067 *------------------------------------------------------------------------* 2068 * Simulate a hardware hub by handling all the necessary requests. 2069 *------------------------------------------------------------------------*/ 2070 2071 static const 2072 struct usb_device_descriptor ohci_devd = 2073 { 2074 sizeof(struct usb_device_descriptor), 2075 UDESC_DEVICE, /* type */ 2076 {0x00, 0x01}, /* USB version */ 2077 UDCLASS_HUB, /* class */ 2078 UDSUBCLASS_HUB, /* subclass */ 2079 UDPROTO_FSHUB, /* protocol */ 2080 64, /* max packet */ 2081 {0}, {0}, {0x00, 0x01}, /* device id */ 2082 1, 2, 0, /* string indicies */ 2083 1 /* # of configurations */ 2084 }; 2085 2086 static const 2087 struct ohci_config_desc ohci_confd = 2088 { 2089 .confd = { 2090 .bLength = sizeof(struct usb_config_descriptor), 2091 .bDescriptorType = UDESC_CONFIG, 2092 .wTotalLength[0] = sizeof(ohci_confd), 2093 .bNumInterface = 1, 2094 .bConfigurationValue = 1, 2095 .iConfiguration = 0, 2096 .bmAttributes = UC_SELF_POWERED, 2097 .bMaxPower = 0, /* max power */ 2098 }, 2099 .ifcd = { 2100 .bLength = sizeof(struct usb_interface_descriptor), 2101 .bDescriptorType = UDESC_INTERFACE, 2102 .bNumEndpoints = 1, 2103 .bInterfaceClass = UICLASS_HUB, 2104 .bInterfaceSubClass = UISUBCLASS_HUB, 2105 .bInterfaceProtocol = UIPROTO_FSHUB, 2106 }, 2107 .endpd = { 2108 .bLength = sizeof(struct usb_endpoint_descriptor), 2109 .bDescriptorType = UDESC_ENDPOINT, 2110 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2111 .bmAttributes = UE_INTERRUPT, 2112 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */ 2113 .bInterval = 255, 2114 }, 2115 }; 2116 2117 static const 2118 struct usb_hub_descriptor ohci_hubd = 2119 { 2120 0, /* dynamic length */ 2121 UDESC_HUB, 2122 0, 2123 {0, 0}, 2124 0, 2125 0, 2126 {0}, 2127 }; 2128 2129 static usb_error_t 2130 ohci_roothub_exec(struct usb_device *udev, 2131 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2132 { 2133 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2134 const void *ptr; 2135 const char *str_ptr; 2136 uint32_t port; 2137 uint32_t v; 2138 uint16_t len; 2139 uint16_t value; 2140 uint16_t index; 2141 uint8_t l; 2142 usb_error_t err; 2143 2144 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2145 2146 /* buffer reset */ 2147 ptr = (const void *)&sc->sc_hub_desc.temp; 2148 len = 0; 2149 err = 0; 2150 2151 value = UGETW(req->wValue); 2152 index = UGETW(req->wIndex); 2153 2154 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2155 "wValue=0x%04x wIndex=0x%04x\n", 2156 req->bmRequestType, req->bRequest, 2157 UGETW(req->wLength), value, index); 2158 2159 #define C(x,y) ((x) | ((y) << 8)) 2160 switch (C(req->bRequest, req->bmRequestType)) { 2161 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2162 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2163 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2164 /* 2165 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2166 * for the integrated root hub. 2167 */ 2168 break; 2169 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2170 len = 1; 2171 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2172 break; 2173 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2174 switch (value >> 8) { 2175 case UDESC_DEVICE: 2176 if ((value & 0xff) != 0) { 2177 err = USB_ERR_IOERROR; 2178 goto done; 2179 } 2180 len = sizeof(ohci_devd); 2181 ptr = (const void *)&ohci_devd; 2182 break; 2183 2184 case UDESC_CONFIG: 2185 if ((value & 0xff) != 0) { 2186 err = USB_ERR_IOERROR; 2187 goto done; 2188 } 2189 len = sizeof(ohci_confd); 2190 ptr = (const void *)&ohci_confd; 2191 break; 2192 2193 case UDESC_STRING: 2194 switch (value & 0xff) { 2195 case 0: /* Language table */ 2196 str_ptr = "\001"; 2197 break; 2198 2199 case 1: /* Vendor */ 2200 str_ptr = sc->sc_vendor; 2201 break; 2202 2203 case 2: /* Product */ 2204 str_ptr = "OHCI root HUB"; 2205 break; 2206 2207 default: 2208 str_ptr = ""; 2209 break; 2210 } 2211 2212 len = usb_make_str_desc( 2213 sc->sc_hub_desc.temp, 2214 sizeof(sc->sc_hub_desc.temp), 2215 str_ptr); 2216 break; 2217 2218 default: 2219 err = USB_ERR_IOERROR; 2220 goto done; 2221 } 2222 break; 2223 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2224 len = 1; 2225 sc->sc_hub_desc.temp[0] = 0; 2226 break; 2227 case C(UR_GET_STATUS, UT_READ_DEVICE): 2228 len = 2; 2229 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2230 break; 2231 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2232 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2233 len = 2; 2234 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2235 break; 2236 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2237 if (value >= OHCI_MAX_DEVICES) { 2238 err = USB_ERR_IOERROR; 2239 goto done; 2240 } 2241 sc->sc_addr = value; 2242 break; 2243 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2244 if ((value != 0) && (value != 1)) { 2245 err = USB_ERR_IOERROR; 2246 goto done; 2247 } 2248 sc->sc_conf = value; 2249 break; 2250 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2251 break; 2252 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2253 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2254 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2255 err = USB_ERR_IOERROR; 2256 goto done; 2257 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2258 break; 2259 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2260 break; 2261 /* Hub requests */ 2262 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2263 break; 2264 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2265 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE " 2266 "port=%d feature=%d\n", 2267 index, value); 2268 if ((index < 1) || 2269 (index > sc->sc_noport)) { 2270 err = USB_ERR_IOERROR; 2271 goto done; 2272 } 2273 port = OHCI_RH_PORT_STATUS(index); 2274 switch (value) { 2275 case UHF_PORT_ENABLE: 2276 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2277 break; 2278 case UHF_PORT_SUSPEND: 2279 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2280 break; 2281 case UHF_PORT_POWER: 2282 /* Yes, writing to the LOW_SPEED bit clears power. */ 2283 OWRITE4(sc, port, UPS_LOW_SPEED); 2284 break; 2285 case UHF_C_PORT_CONNECTION: 2286 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2287 break; 2288 case UHF_C_PORT_ENABLE: 2289 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2290 break; 2291 case UHF_C_PORT_SUSPEND: 2292 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2293 break; 2294 case UHF_C_PORT_OVER_CURRENT: 2295 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2296 break; 2297 case UHF_C_PORT_RESET: 2298 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2299 break; 2300 default: 2301 err = USB_ERR_IOERROR; 2302 goto done; 2303 } 2304 switch (value) { 2305 case UHF_C_PORT_CONNECTION: 2306 case UHF_C_PORT_ENABLE: 2307 case UHF_C_PORT_SUSPEND: 2308 case UHF_C_PORT_OVER_CURRENT: 2309 case UHF_C_PORT_RESET: 2310 /* enable RHSC interrupt if condition is cleared. */ 2311 if ((OREAD4(sc, port) >> 16) == 0) 2312 ohci_rhsc_enable(sc); 2313 break; 2314 default: 2315 break; 2316 } 2317 break; 2318 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2319 if ((value & 0xff) != 0) { 2320 err = USB_ERR_IOERROR; 2321 goto done; 2322 } 2323 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2324 2325 sc->sc_hub_desc.hubd = ohci_hubd; 2326 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 2327 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 2328 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2329 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2330 /* XXX overcurrent */ 2331 ); 2332 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2333 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2334 2335 for (l = 0; l < sc->sc_noport; l++) { 2336 if (v & 1) { 2337 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8)); 2338 } 2339 v >>= 1; 2340 } 2341 sc->sc_hub_desc.hubd.bDescLength = 2342 8 + ((sc->sc_noport + 7) / 8); 2343 len = sc->sc_hub_desc.hubd.bDescLength; 2344 break; 2345 2346 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2347 len = 16; 2348 bzero(sc->sc_hub_desc.temp, 16); 2349 break; 2350 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2351 DPRINTFN(9, "get port status i=%d\n", 2352 index); 2353 if ((index < 1) || 2354 (index > sc->sc_noport)) { 2355 err = USB_ERR_IOERROR; 2356 goto done; 2357 } 2358 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2359 DPRINTFN(9, "port status=0x%04x\n", v); 2360 USETW(sc->sc_hub_desc.ps.wPortStatus, v); 2361 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16); 2362 len = sizeof(sc->sc_hub_desc.ps); 2363 break; 2364 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2365 err = USB_ERR_IOERROR; 2366 goto done; 2367 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2368 break; 2369 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2370 if ((index < 1) || 2371 (index > sc->sc_noport)) { 2372 err = USB_ERR_IOERROR; 2373 goto done; 2374 } 2375 port = OHCI_RH_PORT_STATUS(index); 2376 switch (value) { 2377 case UHF_PORT_ENABLE: 2378 OWRITE4(sc, port, UPS_PORT_ENABLED); 2379 break; 2380 case UHF_PORT_SUSPEND: 2381 OWRITE4(sc, port, UPS_SUSPEND); 2382 break; 2383 case UHF_PORT_RESET: 2384 DPRINTFN(6, "reset port %d\n", index); 2385 OWRITE4(sc, port, UPS_RESET); 2386 for (v = 0;; v++) { 2387 if (v < 12) { 2388 usb_pause_mtx(&sc->sc_bus.bus_mtx, 2389 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 2390 2391 if ((OREAD4(sc, port) & UPS_RESET) == 0) { 2392 break; 2393 } 2394 } else { 2395 err = USB_ERR_TIMEOUT; 2396 goto done; 2397 } 2398 } 2399 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n", 2400 index, OREAD4(sc, port)); 2401 break; 2402 case UHF_PORT_POWER: 2403 DPRINTFN(3, "set port power %d\n", index); 2404 OWRITE4(sc, port, UPS_PORT_POWER); 2405 break; 2406 default: 2407 err = USB_ERR_IOERROR; 2408 goto done; 2409 } 2410 break; 2411 default: 2412 err = USB_ERR_IOERROR; 2413 goto done; 2414 } 2415 done: 2416 *plength = len; 2417 *pptr = ptr; 2418 return (err); 2419 } 2420 2421 static void 2422 ohci_xfer_setup(struct usb_setup_params *parm) 2423 { 2424 struct usb_page_search page_info; 2425 struct usb_page_cache *pc; 2426 ohci_softc_t *sc; 2427 struct usb_xfer *xfer; 2428 void *last_obj; 2429 uint32_t ntd; 2430 uint32_t nitd; 2431 uint32_t nqh; 2432 uint32_t n; 2433 2434 sc = OHCI_BUS2SC(parm->udev->bus); 2435 xfer = parm->curr_xfer; 2436 2437 parm->hc_max_packet_size = 0x500; 2438 parm->hc_max_packet_count = 1; 2439 parm->hc_max_frame_size = OHCI_PAGE_SIZE; 2440 2441 /* 2442 * calculate ntd and nqh 2443 */ 2444 if (parm->methods == &ohci_device_ctrl_methods) { 2445 xfer->flags_int.bdma_enable = 1; 2446 2447 usbd_transfer_setup_sub(parm); 2448 2449 nitd = 0; 2450 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2451 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2452 nqh = 1; 2453 2454 } else if (parm->methods == &ohci_device_bulk_methods) { 2455 xfer->flags_int.bdma_enable = 1; 2456 2457 usbd_transfer_setup_sub(parm); 2458 2459 nitd = 0; 2460 ntd = ((2 * xfer->nframes) 2461 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2462 nqh = 1; 2463 2464 } else if (parm->methods == &ohci_device_intr_methods) { 2465 xfer->flags_int.bdma_enable = 1; 2466 2467 usbd_transfer_setup_sub(parm); 2468 2469 nitd = 0; 2470 ntd = ((2 * xfer->nframes) 2471 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2472 nqh = 1; 2473 2474 } else if (parm->methods == &ohci_device_isoc_methods) { 2475 xfer->flags_int.bdma_enable = 1; 2476 2477 usbd_transfer_setup_sub(parm); 2478 2479 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) + 2480 ((xfer->nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET) + 2481 1 /* EXTRA */ ); 2482 ntd = 0; 2483 nqh = 1; 2484 2485 } else { 2486 2487 usbd_transfer_setup_sub(parm); 2488 2489 nitd = 0; 2490 ntd = 0; 2491 nqh = 0; 2492 } 2493 2494 alloc_dma_set: 2495 2496 if (parm->err) { 2497 return; 2498 } 2499 last_obj = NULL; 2500 2501 if (usbd_transfer_setup_sub_malloc( 2502 parm, &pc, sizeof(ohci_td_t), 2503 OHCI_TD_ALIGN, ntd)) { 2504 parm->err = USB_ERR_NOMEM; 2505 return; 2506 } 2507 if (parm->buf) { 2508 for (n = 0; n != ntd; n++) { 2509 ohci_td_t *td; 2510 2511 usbd_get_page(pc + n, 0, &page_info); 2512 2513 td = page_info.buffer; 2514 2515 /* init TD */ 2516 td->td_self = htole32(page_info.physaddr); 2517 td->obj_next = last_obj; 2518 td->page_cache = pc + n; 2519 2520 last_obj = td; 2521 2522 usb_pc_cpu_flush(pc + n); 2523 } 2524 } 2525 if (usbd_transfer_setup_sub_malloc( 2526 parm, &pc, sizeof(ohci_itd_t), 2527 OHCI_ITD_ALIGN, nitd)) { 2528 parm->err = USB_ERR_NOMEM; 2529 return; 2530 } 2531 if (parm->buf) { 2532 for (n = 0; n != nitd; n++) { 2533 ohci_itd_t *itd; 2534 2535 usbd_get_page(pc + n, 0, &page_info); 2536 2537 itd = page_info.buffer; 2538 2539 /* init TD */ 2540 itd->itd_self = htole32(page_info.physaddr); 2541 itd->obj_next = last_obj; 2542 itd->page_cache = pc + n; 2543 2544 last_obj = itd; 2545 2546 usb_pc_cpu_flush(pc + n); 2547 } 2548 } 2549 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2550 2551 last_obj = NULL; 2552 2553 if (usbd_transfer_setup_sub_malloc( 2554 parm, &pc, sizeof(ohci_ed_t), 2555 OHCI_ED_ALIGN, nqh)) { 2556 parm->err = USB_ERR_NOMEM; 2557 return; 2558 } 2559 if (parm->buf) { 2560 for (n = 0; n != nqh; n++) { 2561 ohci_ed_t *ed; 2562 2563 usbd_get_page(pc + n, 0, &page_info); 2564 2565 ed = page_info.buffer; 2566 2567 /* init QH */ 2568 ed->ed_self = htole32(page_info.physaddr); 2569 ed->obj_next = last_obj; 2570 ed->page_cache = pc + n; 2571 2572 last_obj = ed; 2573 2574 usb_pc_cpu_flush(pc + n); 2575 } 2576 } 2577 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2578 2579 if (!xfer->flags_int.curr_dma_set) { 2580 xfer->flags_int.curr_dma_set = 1; 2581 goto alloc_dma_set; 2582 } 2583 } 2584 2585 static void 2586 ohci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2587 struct usb_endpoint *ep) 2588 { 2589 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2590 2591 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2592 ep, udev->address, 2593 edesc->bEndpointAddress, udev->flags.usb_mode, 2594 sc->sc_addr); 2595 2596 if (udev->flags.usb_mode != USB_MODE_HOST) { 2597 /* not supported */ 2598 return; 2599 } 2600 if (udev->device_index != sc->sc_addr) { 2601 switch (edesc->bmAttributes & UE_XFERTYPE) { 2602 case UE_CONTROL: 2603 ep->methods = &ohci_device_ctrl_methods; 2604 break; 2605 case UE_INTERRUPT: 2606 ep->methods = &ohci_device_intr_methods; 2607 break; 2608 case UE_ISOCHRONOUS: 2609 if (udev->speed == USB_SPEED_FULL) { 2610 ep->methods = &ohci_device_isoc_methods; 2611 } 2612 break; 2613 case UE_BULK: 2614 if (udev->speed != USB_SPEED_LOW) { 2615 ep->methods = &ohci_device_bulk_methods; 2616 } 2617 break; 2618 default: 2619 /* do nothing */ 2620 break; 2621 } 2622 } 2623 } 2624 2625 static void 2626 ohci_xfer_unsetup(struct usb_xfer *xfer) 2627 { 2628 return; 2629 } 2630 2631 static void 2632 ohci_get_dma_delay(struct usb_bus *bus, uint32_t *pus) 2633 { 2634 /* 2635 * Wait until hardware has finished any possible use of the 2636 * transfer descriptor(s) and QH 2637 */ 2638 *pus = (1125); /* microseconds */ 2639 } 2640 2641 static void 2642 ohci_device_resume(struct usb_device *udev) 2643 { 2644 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2645 struct usb_xfer *xfer; 2646 struct usb_pipe_methods *methods; 2647 ohci_ed_t *ed; 2648 2649 DPRINTF("\n"); 2650 2651 USB_BUS_LOCK(udev->bus); 2652 2653 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2654 2655 if (xfer->xroot->udev == udev) { 2656 2657 methods = xfer->endpoint->methods; 2658 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2659 2660 if (methods == &ohci_device_bulk_methods) { 2661 OHCI_APPEND_QH(ed, sc->sc_bulk_p_last); 2662 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2663 } 2664 if (methods == &ohci_device_ctrl_methods) { 2665 OHCI_APPEND_QH(ed, sc->sc_ctrl_p_last); 2666 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2667 } 2668 if (methods == &ohci_device_intr_methods) { 2669 OHCI_APPEND_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2670 } 2671 } 2672 } 2673 2674 USB_BUS_UNLOCK(udev->bus); 2675 2676 return; 2677 } 2678 2679 static void 2680 ohci_device_suspend(struct usb_device *udev) 2681 { 2682 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2683 struct usb_xfer *xfer; 2684 struct usb_pipe_methods *methods; 2685 ohci_ed_t *ed; 2686 2687 DPRINTF("\n"); 2688 2689 USB_BUS_LOCK(udev->bus); 2690 2691 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2692 2693 if (xfer->xroot->udev == udev) { 2694 2695 methods = xfer->endpoint->methods; 2696 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2697 2698 if (methods == &ohci_device_bulk_methods) { 2699 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 2700 } 2701 if (methods == &ohci_device_ctrl_methods) { 2702 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 2703 } 2704 if (methods == &ohci_device_intr_methods) { 2705 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2706 } 2707 } 2708 } 2709 2710 USB_BUS_UNLOCK(udev->bus); 2711 2712 return; 2713 } 2714 2715 static void 2716 ohci_set_hw_power(struct usb_bus *bus) 2717 { 2718 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2719 uint32_t temp; 2720 uint32_t flags; 2721 2722 DPRINTF("\n"); 2723 2724 USB_BUS_LOCK(bus); 2725 2726 flags = bus->hw_power_state; 2727 2728 temp = OREAD4(sc, OHCI_CONTROL); 2729 temp &= ~(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE); 2730 2731 if (flags & USB_HW_POWER_CONTROL) 2732 temp |= OHCI_CLE; 2733 2734 if (flags & USB_HW_POWER_BULK) 2735 temp |= OHCI_BLE; 2736 2737 if (flags & USB_HW_POWER_INTERRUPT) 2738 temp |= OHCI_PLE; 2739 2740 if (flags & USB_HW_POWER_ISOC) 2741 temp |= OHCI_IE | OHCI_PLE; 2742 2743 OWRITE4(sc, OHCI_CONTROL, temp); 2744 2745 USB_BUS_UNLOCK(bus); 2746 2747 return; 2748 } 2749 2750 struct usb_bus_methods ohci_bus_methods = 2751 { 2752 .endpoint_init = ohci_ep_init, 2753 .xfer_setup = ohci_xfer_setup, 2754 .xfer_unsetup = ohci_xfer_unsetup, 2755 .get_dma_delay = ohci_get_dma_delay, 2756 .device_resume = ohci_device_resume, 2757 .device_suspend = ohci_device_suspend, 2758 .set_hw_power = ohci_set_hw_power, 2759 .roothub_exec = ohci_roothub_exec, 2760 .xfer_poll = ohci_do_poll, 2761 }; 2762