1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * USB Open Host Controller driver. 33 * 34 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 35 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 36 */ 37 38 #include <dev/usb/usb.h> 39 #include <dev/usb/usb_mfunc.h> 40 #include <dev/usb/usb_error.h> 41 42 #define USB_DEBUG_VAR ohcidebug 43 44 #include <dev/usb/usb_core.h> 45 #include <dev/usb/usb_debug.h> 46 #include <dev/usb/usb_busdma.h> 47 #include <dev/usb/usb_process.h> 48 #include <dev/usb/usb_sw_transfer.h> 49 #include <dev/usb/usb_transfer.h> 50 #include <dev/usb/usb_device.h> 51 #include <dev/usb/usb_hub.h> 52 #include <dev/usb/usb_util.h> 53 54 #include <dev/usb/usb_controller.h> 55 #include <dev/usb/usb_bus.h> 56 #include <dev/usb/controller/ohci.h> 57 58 #define OHCI_BUS2SC(bus) \ 59 ((ohci_softc_t *)(((uint8_t *)(bus)) - \ 60 ((uint8_t *)&(((ohci_softc_t *)0)->sc_bus)))) 61 62 #if USB_DEBUG 63 static int ohcidebug = 0; 64 65 SYSCTL_NODE(_hw_usb2, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 66 SYSCTL_INT(_hw_usb2_ohci, OID_AUTO, debug, CTLFLAG_RW, 67 &ohcidebug, 0, "ohci debug level"); 68 static void ohci_dumpregs(ohci_softc_t *); 69 static void ohci_dump_tds(ohci_td_t *); 70 static uint8_t ohci_dump_td(ohci_td_t *); 71 static void ohci_dump_ed(ohci_ed_t *); 72 static uint8_t ohci_dump_itd(ohci_itd_t *); 73 static void ohci_dump_itds(ohci_itd_t *); 74 75 #endif 76 77 #define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \ 78 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 79 #define OWRITE1(sc, r, x) \ 80 do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 81 #define OWRITE2(sc, r, x) \ 82 do { OBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 83 #define OWRITE4(sc, r, x) \ 84 do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0) 85 #define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 86 #define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 87 #define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r))) 88 89 #define OHCI_INTR_ENDPT 1 90 91 extern struct usb2_bus_methods ohci_bus_methods; 92 extern struct usb2_pipe_methods ohci_device_bulk_methods; 93 extern struct usb2_pipe_methods ohci_device_ctrl_methods; 94 extern struct usb2_pipe_methods ohci_device_intr_methods; 95 extern struct usb2_pipe_methods ohci_device_isoc_methods; 96 extern struct usb2_pipe_methods ohci_root_ctrl_methods; 97 extern struct usb2_pipe_methods ohci_root_intr_methods; 98 99 static void ohci_root_ctrl_poll(struct ohci_softc *sc); 100 static void ohci_do_poll(struct usb2_bus *bus); 101 static void ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 102 103 static usb2_sw_transfer_func_t ohci_root_intr_done; 104 static usb2_sw_transfer_func_t ohci_root_ctrl_done; 105 static void ohci_timeout(void *arg); 106 static uint8_t ohci_check_transfer(struct usb2_xfer *xfer); 107 108 struct ohci_std_temp { 109 struct usb2_page_cache *pc; 110 ohci_td_t *td; 111 ohci_td_t *td_next; 112 uint32_t average; 113 uint32_t td_flags; 114 uint32_t len; 115 uint16_t max_frame_size; 116 uint8_t shortpkt; 117 uint8_t setup_alt_next; 118 uint8_t last_frame; 119 }; 120 121 static struct ohci_hcca * 122 ohci_get_hcca(ohci_softc_t *sc) 123 { 124 usb2_pc_cpu_invalidate(&sc->sc_hw.hcca_pc); 125 return (sc->sc_hcca_p); 126 } 127 128 void 129 ohci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 130 { 131 struct ohci_softc *sc = OHCI_BUS2SC(bus); 132 uint32_t i; 133 134 cb(bus, &sc->sc_hw.hcca_pc, &sc->sc_hw.hcca_pg, 135 sizeof(ohci_hcca_t), OHCI_HCCA_ALIGN); 136 137 cb(bus, &sc->sc_hw.ctrl_start_pc, &sc->sc_hw.ctrl_start_pg, 138 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 139 140 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg, 141 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 142 143 cb(bus, &sc->sc_hw.isoc_start_pc, &sc->sc_hw.isoc_start_pg, 144 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 145 146 for (i = 0; i != OHCI_NO_EDS; i++) { 147 cb(bus, sc->sc_hw.intr_start_pc + i, sc->sc_hw.intr_start_pg + i, 148 sizeof(ohci_ed_t), OHCI_ED_ALIGN); 149 } 150 } 151 152 static usb2_error_t 153 ohci_controller_init(ohci_softc_t *sc) 154 { 155 struct usb2_page_search buf_res; 156 uint32_t i; 157 uint32_t ctl; 158 uint32_t ival; 159 uint32_t hcr; 160 uint32_t fm; 161 uint32_t per; 162 uint32_t desca; 163 164 /* Determine in what context we are running. */ 165 ctl = OREAD4(sc, OHCI_CONTROL); 166 if (ctl & OHCI_IR) { 167 /* SMM active, request change */ 168 DPRINTF("SMM active, request owner change\n"); 169 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_OCR); 170 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) { 171 usb2_pause_mtx(NULL, hz / 1000); 172 ctl = OREAD4(sc, OHCI_CONTROL); 173 } 174 if (ctl & OHCI_IR) { 175 device_printf(sc->sc_bus.bdev, 176 "SMM does not respond, resetting\n"); 177 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 178 goto reset; 179 } 180 } else { 181 DPRINTF("cold started\n"); 182 reset: 183 /* controller was cold started */ 184 usb2_pause_mtx(NULL, 185 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 186 } 187 188 /* 189 * This reset should not be necessary according to the OHCI spec, but 190 * without it some controllers do not start. 191 */ 192 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 193 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 194 195 usb2_pause_mtx(NULL, 196 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY)); 197 198 /* we now own the host controller and the bus has been reset */ 199 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 200 201 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 202 /* nominal time for a reset is 10 us */ 203 for (i = 0; i < 10; i++) { 204 DELAY(10); 205 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 206 if (!hcr) { 207 break; 208 } 209 } 210 if (hcr) { 211 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 212 return (USB_ERR_IOERROR); 213 } 214 #if USB_DEBUG 215 if (ohcidebug > 15) { 216 ohci_dumpregs(sc); 217 } 218 #endif 219 220 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 221 222 /* set up HC registers */ 223 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 224 OWRITE4(sc, OHCI_HCCA, buf_res.physaddr); 225 226 usb2_get_page(&sc->sc_hw.ctrl_start_pc, 0, &buf_res); 227 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, buf_res.physaddr); 228 229 usb2_get_page(&sc->sc_hw.bulk_start_pc, 0, &buf_res); 230 OWRITE4(sc, OHCI_BULK_HEAD_ED, buf_res.physaddr); 231 232 /* disable all interrupts and then switch on all desired interrupts */ 233 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 234 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 235 /* switch on desired functional features */ 236 ctl = OREAD4(sc, OHCI_CONTROL); 237 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 238 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 239 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 240 /* And finally start it! */ 241 OWRITE4(sc, OHCI_CONTROL, ctl); 242 243 /* 244 * The controller is now OPERATIONAL. Set a some final 245 * registers that should be set earlier, but that the 246 * controller ignores when in the SUSPEND state. 247 */ 248 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 249 fm |= OHCI_FSMPS(ival) | ival; 250 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 251 per = OHCI_PERIODIC(ival); /* 90% periodic */ 252 OWRITE4(sc, OHCI_PERIODIC_START, per); 253 254 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 255 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 256 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 257 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 258 usb2_pause_mtx(NULL, 259 USB_MS_TO_TICKS(OHCI_ENABLE_POWER_DELAY)); 260 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 261 262 /* 263 * The AMD756 requires a delay before re-reading the register, 264 * otherwise it will occasionally report 0 ports. 265 */ 266 sc->sc_noport = 0; 267 for (i = 0; (i < 10) && (sc->sc_noport == 0); i++) { 268 usb2_pause_mtx(NULL, 269 USB_MS_TO_TICKS(OHCI_READ_DESC_DELAY)); 270 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 271 } 272 273 #if USB_DEBUG 274 if (ohcidebug > 5) { 275 ohci_dumpregs(sc); 276 } 277 #endif 278 return (USB_ERR_NORMAL_COMPLETION); 279 } 280 281 static struct ohci_ed * 282 ohci_init_ed(struct usb2_page_cache *pc) 283 { 284 struct usb2_page_search buf_res; 285 struct ohci_ed *ed; 286 287 usb2_get_page(pc, 0, &buf_res); 288 289 ed = buf_res.buffer; 290 291 ed->ed_self = htole32(buf_res.physaddr); 292 ed->ed_flags = htole32(OHCI_ED_SKIP); 293 ed->page_cache = pc; 294 295 return (ed); 296 } 297 298 usb2_error_t 299 ohci_init(ohci_softc_t *sc) 300 { 301 struct usb2_page_search buf_res; 302 uint16_t i; 303 uint16_t bit; 304 uint16_t x; 305 uint16_t y; 306 307 DPRINTF("start\n"); 308 309 sc->sc_eintrs = OHCI_NORMAL_INTRS; 310 311 /* 312 * Setup all ED's 313 */ 314 315 sc->sc_ctrl_p_last = 316 ohci_init_ed(&sc->sc_hw.ctrl_start_pc); 317 318 sc->sc_bulk_p_last = 319 ohci_init_ed(&sc->sc_hw.bulk_start_pc); 320 321 sc->sc_isoc_p_last = 322 ohci_init_ed(&sc->sc_hw.isoc_start_pc); 323 324 for (i = 0; i != OHCI_NO_EDS; i++) { 325 sc->sc_intr_p_last[i] = 326 ohci_init_ed(sc->sc_hw.intr_start_pc + i); 327 } 328 329 /* 330 * the QHs are arranged to give poll intervals that are 331 * powers of 2 times 1ms 332 */ 333 bit = OHCI_NO_EDS / 2; 334 while (bit) { 335 x = bit; 336 while (x & bit) { 337 ohci_ed_t *ed_x; 338 ohci_ed_t *ed_y; 339 340 y = (x ^ bit) | (bit / 2); 341 342 /* 343 * the next QH has half the poll interval 344 */ 345 ed_x = sc->sc_intr_p_last[x]; 346 ed_y = sc->sc_intr_p_last[y]; 347 348 ed_x->next = NULL; 349 ed_x->ed_next = ed_y->ed_self; 350 351 x++; 352 } 353 bit >>= 1; 354 } 355 356 if (1) { 357 358 ohci_ed_t *ed_int; 359 ohci_ed_t *ed_isc; 360 361 ed_int = sc->sc_intr_p_last[0]; 362 ed_isc = sc->sc_isoc_p_last; 363 364 /* the last (1ms) QH */ 365 ed_int->next = ed_isc; 366 ed_int->ed_next = ed_isc->ed_self; 367 } 368 usb2_get_page(&sc->sc_hw.hcca_pc, 0, &buf_res); 369 370 sc->sc_hcca_p = buf_res.buffer; 371 372 /* 373 * Fill HCCA interrupt table. The bit reversal is to get 374 * the tree set up properly to spread the interrupts. 375 */ 376 for (i = 0; i != OHCI_NO_INTRS; i++) { 377 sc->sc_hcca_p->hcca_interrupt_table[i] = 378 sc->sc_intr_p_last[i | (OHCI_NO_EDS / 2)]->ed_self; 379 } 380 /* flush all cache into memory */ 381 382 usb2_bus_mem_flush_all(&sc->sc_bus, &ohci_iterate_hw_softc); 383 384 /* set up the bus struct */ 385 sc->sc_bus.methods = &ohci_bus_methods; 386 387 usb2_callout_init_mtx(&sc->sc_tmo_rhsc, &sc->sc_bus.bus_mtx, 0); 388 389 #if USB_DEBUG 390 if (ohcidebug > 15) { 391 for (i = 0; i != OHCI_NO_EDS; i++) { 392 printf("ed#%d ", i); 393 ohci_dump_ed(sc->sc_intr_p_last[i]); 394 } 395 printf("iso "); 396 ohci_dump_ed(sc->sc_isoc_p_last); 397 } 398 #endif 399 400 sc->sc_bus.usbrev = USB_REV_1_0; 401 402 if (ohci_controller_init(sc)) { 403 return (USB_ERR_INVAL); 404 } else { 405 /* catch any lost interrupts */ 406 ohci_do_poll(&sc->sc_bus); 407 return (USB_ERR_NORMAL_COMPLETION); 408 } 409 } 410 411 /* 412 * shut down the controller when the system is going down 413 */ 414 void 415 ohci_detach(struct ohci_softc *sc) 416 { 417 USB_BUS_LOCK(&sc->sc_bus); 418 419 usb2_callout_stop(&sc->sc_tmo_rhsc); 420 421 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 422 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 423 424 USB_BUS_UNLOCK(&sc->sc_bus); 425 426 /* XXX let stray task complete */ 427 usb2_pause_mtx(NULL, hz / 20); 428 429 usb2_callout_drain(&sc->sc_tmo_rhsc); 430 } 431 432 /* NOTE: suspend/resume is called from 433 * interrupt context and cannot sleep! 434 */ 435 void 436 ohci_suspend(ohci_softc_t *sc) 437 { 438 uint32_t ctl; 439 440 USB_BUS_LOCK(&sc->sc_bus); 441 442 #if USB_DEBUG 443 DPRINTF("\n"); 444 if (ohcidebug > 2) { 445 ohci_dumpregs(sc); 446 } 447 #endif 448 449 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 450 if (sc->sc_control == 0) { 451 /* 452 * Preserve register values, in case that APM BIOS 453 * does not recover them. 454 */ 455 sc->sc_control = ctl; 456 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 457 } 458 ctl |= OHCI_HCFS_SUSPEND; 459 OWRITE4(sc, OHCI_CONTROL, ctl); 460 461 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 462 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 463 464 USB_BUS_UNLOCK(&sc->sc_bus); 465 } 466 467 void 468 ohci_resume(ohci_softc_t *sc) 469 { 470 uint32_t ctl; 471 472 #if USB_DEBUG 473 DPRINTF("\n"); 474 if (ohcidebug > 2) { 475 ohci_dumpregs(sc); 476 } 477 #endif 478 /* some broken BIOSes never initialize the Controller chip */ 479 ohci_controller_init(sc); 480 481 USB_BUS_LOCK(&sc->sc_bus); 482 if (sc->sc_intre) { 483 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 484 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 485 } 486 if (sc->sc_control) 487 ctl = sc->sc_control; 488 else 489 ctl = OREAD4(sc, OHCI_CONTROL); 490 ctl |= OHCI_HCFS_RESUME; 491 OWRITE4(sc, OHCI_CONTROL, ctl); 492 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 493 USB_MS_TO_TICKS(USB_RESUME_DELAY)); 494 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 495 OWRITE4(sc, OHCI_CONTROL, ctl); 496 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 497 USB_MS_TO_TICKS(USB_RESUME_RECOVERY)); 498 sc->sc_control = sc->sc_intre = 0; 499 500 USB_BUS_UNLOCK(&sc->sc_bus); 501 502 /* catch any lost interrupts */ 503 ohci_do_poll(&sc->sc_bus); 504 } 505 506 #if USB_DEBUG 507 static void 508 ohci_dumpregs(ohci_softc_t *sc) 509 { 510 struct ohci_hcca *hcca; 511 512 DPRINTF("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 513 OREAD4(sc, OHCI_REVISION), 514 OREAD4(sc, OHCI_CONTROL), 515 OREAD4(sc, OHCI_COMMAND_STATUS)); 516 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 517 OREAD4(sc, OHCI_INTERRUPT_STATUS), 518 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 519 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 520 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 521 OREAD4(sc, OHCI_HCCA), 522 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 523 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 524 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 525 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 526 OREAD4(sc, OHCI_BULK_HEAD_ED), 527 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 528 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 529 OREAD4(sc, OHCI_DONE_HEAD), 530 OREAD4(sc, OHCI_FM_INTERVAL), 531 OREAD4(sc, OHCI_FM_REMAINING)); 532 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 533 OREAD4(sc, OHCI_FM_NUMBER), 534 OREAD4(sc, OHCI_PERIODIC_START), 535 OREAD4(sc, OHCI_LS_THRESHOLD)); 536 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 537 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 538 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 539 OREAD4(sc, OHCI_RH_STATUS)); 540 DPRINTF(" port1=0x%08x port2=0x%08x\n", 541 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 542 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 543 544 hcca = ohci_get_hcca(sc); 545 546 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 547 le32toh(hcca->hcca_frame_number), 548 le32toh(hcca->hcca_done_head)); 549 } 550 static void 551 ohci_dump_tds(ohci_td_t *std) 552 { 553 for (; std; std = std->obj_next) { 554 if (ohci_dump_td(std)) { 555 break; 556 } 557 } 558 } 559 560 static uint8_t 561 ohci_dump_td(ohci_td_t *std) 562 { 563 uint32_t td_flags; 564 uint8_t temp; 565 566 usb2_pc_cpu_invalidate(std->page_cache); 567 568 td_flags = le32toh(std->td_flags); 569 temp = (std->td_next == 0); 570 571 printf("TD(%p) at 0x%08x: %s%s%s%s%s delay=%d ec=%d " 572 "cc=%d\ncbp=0x%08x next=0x%08x be=0x%08x\n", 573 std, le32toh(std->td_self), 574 (td_flags & OHCI_TD_R) ? "-R" : "", 575 (td_flags & OHCI_TD_OUT) ? "-OUT" : "", 576 (td_flags & OHCI_TD_IN) ? "-IN" : "", 577 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_1) ? "-TOG1" : "", 578 ((td_flags & OHCI_TD_TOGGLE_MASK) == OHCI_TD_TOGGLE_0) ? "-TOG0" : "", 579 OHCI_TD_GET_DI(td_flags), 580 OHCI_TD_GET_EC(td_flags), 581 OHCI_TD_GET_CC(td_flags), 582 le32toh(std->td_cbp), 583 le32toh(std->td_next), 584 le32toh(std->td_be)); 585 586 return (temp); 587 } 588 589 static uint8_t 590 ohci_dump_itd(ohci_itd_t *sitd) 591 { 592 uint32_t itd_flags; 593 uint16_t i; 594 uint8_t temp; 595 596 usb2_pc_cpu_invalidate(sitd->page_cache); 597 598 itd_flags = le32toh(sitd->itd_flags); 599 temp = (sitd->itd_next == 0); 600 601 printf("ITD(%p) at 0x%08x: sf=%d di=%d fc=%d cc=%d\n" 602 "bp0=0x%08x next=0x%08x be=0x%08x\n", 603 sitd, le32toh(sitd->itd_self), 604 OHCI_ITD_GET_SF(itd_flags), 605 OHCI_ITD_GET_DI(itd_flags), 606 OHCI_ITD_GET_FC(itd_flags), 607 OHCI_ITD_GET_CC(itd_flags), 608 le32toh(sitd->itd_bp0), 609 le32toh(sitd->itd_next), 610 le32toh(sitd->itd_be)); 611 for (i = 0; i < OHCI_ITD_NOFFSET; i++) { 612 printf("offs[%d]=0x%04x ", i, 613 (uint32_t)le16toh(sitd->itd_offset[i])); 614 } 615 printf("\n"); 616 617 return (temp); 618 } 619 620 static void 621 ohci_dump_itds(ohci_itd_t *sitd) 622 { 623 for (; sitd; sitd = sitd->obj_next) { 624 if (ohci_dump_itd(sitd)) { 625 break; 626 } 627 } 628 } 629 630 static void 631 ohci_dump_ed(ohci_ed_t *sed) 632 { 633 uint32_t ed_flags; 634 uint32_t ed_headp; 635 636 usb2_pc_cpu_invalidate(sed->page_cache); 637 638 ed_flags = le32toh(sed->ed_flags); 639 ed_headp = le32toh(sed->ed_headp); 640 641 printf("ED(%p) at 0x%08x: addr=%d endpt=%d maxp=%d flags=%s%s%s%s%s\n" 642 "tailp=0x%08x headflags=%s%s headp=0x%08x nexted=0x%08x\n", 643 sed, le32toh(sed->ed_self), 644 OHCI_ED_GET_FA(ed_flags), 645 OHCI_ED_GET_EN(ed_flags), 646 OHCI_ED_GET_MAXP(ed_flags), 647 (ed_flags & OHCI_ED_DIR_OUT) ? "-OUT" : "", 648 (ed_flags & OHCI_ED_DIR_IN) ? "-IN" : "", 649 (ed_flags & OHCI_ED_SPEED) ? "-LOWSPEED" : "", 650 (ed_flags & OHCI_ED_SKIP) ? "-SKIP" : "", 651 (ed_flags & OHCI_ED_FORMAT_ISO) ? "-ISO" : "", 652 le32toh(sed->ed_tailp), 653 (ed_headp & OHCI_HALTED) ? "-HALTED" : "", 654 (ed_headp & OHCI_TOGGLECARRY) ? "-CARRY" : "", 655 le32toh(sed->ed_headp), 656 le32toh(sed->ed_next)); 657 } 658 659 #endif 660 661 static void 662 ohci_transfer_intr_enqueue(struct usb2_xfer *xfer) 663 { 664 /* check for early completion */ 665 if (ohci_check_transfer(xfer)) { 666 return; 667 } 668 /* put transfer on interrupt queue */ 669 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 670 671 /* start timeout, if any */ 672 if (xfer->timeout != 0) { 673 usb2_transfer_timeout_ms(xfer, &ohci_timeout, xfer->timeout); 674 } 675 } 676 677 #define OHCI_APPEND_QH(sed,last) (last) = _ohci_append_qh(sed,last) 678 static ohci_ed_t * 679 _ohci_append_qh(ohci_ed_t *sed, ohci_ed_t *last) 680 { 681 DPRINTFN(11, "%p to %p\n", sed, last); 682 683 if (sed->prev != NULL) { 684 /* should not happen */ 685 DPRINTFN(0, "ED already linked!\n"); 686 return (last); 687 } 688 /* (sc->sc_bus.bus_mtx) must be locked */ 689 690 sed->next = last->next; 691 sed->ed_next = last->ed_next; 692 sed->ed_tailp = 0; 693 694 sed->prev = last; 695 696 usb2_pc_cpu_flush(sed->page_cache); 697 698 /* 699 * the last->next->prev is never followed: sed->next->prev = sed; 700 */ 701 702 last->next = sed; 703 last->ed_next = sed->ed_self; 704 705 usb2_pc_cpu_flush(last->page_cache); 706 707 return (sed); 708 } 709 710 #define OHCI_REMOVE_QH(sed,last) (last) = _ohci_remove_qh(sed,last) 711 static ohci_ed_t * 712 _ohci_remove_qh(ohci_ed_t *sed, ohci_ed_t *last) 713 { 714 DPRINTFN(11, "%p from %p\n", sed, last); 715 716 /* (sc->sc_bus.bus_mtx) must be locked */ 717 718 /* only remove if not removed from a queue */ 719 if (sed->prev) { 720 721 sed->prev->next = sed->next; 722 sed->prev->ed_next = sed->ed_next; 723 724 usb2_pc_cpu_flush(sed->prev->page_cache); 725 726 if (sed->next) { 727 sed->next->prev = sed->prev; 728 usb2_pc_cpu_flush(sed->next->page_cache); 729 } 730 last = ((last == sed) ? sed->prev : last); 731 732 sed->prev = 0; 733 734 usb2_pc_cpu_flush(sed->page_cache); 735 } 736 return (last); 737 } 738 739 static void 740 ohci_isoc_done(struct usb2_xfer *xfer) 741 { 742 uint8_t nframes; 743 uint32_t *plen = xfer->frlengths; 744 volatile uint16_t *olen; 745 uint16_t len = 0; 746 ohci_itd_t *td = xfer->td_transfer_first; 747 748 while (1) { 749 if (td == NULL) { 750 panic("%s:%d: out of TD's\n", 751 __FUNCTION__, __LINE__); 752 } 753 #if USB_DEBUG 754 if (ohcidebug > 5) { 755 DPRINTF("isoc TD\n"); 756 ohci_dump_itd(td); 757 } 758 #endif 759 usb2_pc_cpu_invalidate(td->page_cache); 760 761 nframes = td->frames; 762 olen = &td->itd_offset[0]; 763 764 if (nframes > 8) { 765 nframes = 8; 766 } 767 while (nframes--) { 768 len = le16toh(*olen); 769 770 if ((len >> 12) == OHCI_CC_NOT_ACCESSED) { 771 len = 0; 772 } else { 773 len &= ((1 << 12) - 1); 774 } 775 776 if (len > *plen) { 777 len = 0;/* invalid length */ 778 } 779 *plen = len; 780 plen++; 781 olen++; 782 } 783 784 if (((void *)td) == xfer->td_transfer_last) { 785 break; 786 } 787 td = td->obj_next; 788 } 789 790 xfer->aframes = xfer->nframes; 791 ohci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 792 } 793 794 #if USB_DEBUG 795 static const char *const 796 ohci_cc_strs[] = 797 { 798 "NO_ERROR", 799 "CRC", 800 "BIT_STUFFING", 801 "DATA_TOGGLE_MISMATCH", 802 803 "STALL", 804 "DEVICE_NOT_RESPONDING", 805 "PID_CHECK_FAILURE", 806 "UNEXPECTED_PID", 807 808 "DATA_OVERRUN", 809 "DATA_UNDERRUN", 810 "BUFFER_OVERRUN", 811 "BUFFER_UNDERRUN", 812 813 "reserved", 814 "reserved", 815 "NOT_ACCESSED", 816 "NOT_ACCESSED" 817 }; 818 819 #endif 820 821 static usb2_error_t 822 ohci_non_isoc_done_sub(struct usb2_xfer *xfer) 823 { 824 ohci_td_t *td; 825 ohci_td_t *td_alt_next; 826 uint32_t temp; 827 uint32_t phy_start; 828 uint32_t phy_end; 829 uint32_t td_flags; 830 uint16_t cc; 831 832 td = xfer->td_transfer_cache; 833 td_alt_next = td->alt_next; 834 td_flags = 0; 835 836 if (xfer->aframes != xfer->nframes) { 837 xfer->frlengths[xfer->aframes] = 0; 838 } 839 while (1) { 840 841 usb2_pc_cpu_invalidate(td->page_cache); 842 phy_start = le32toh(td->td_cbp); 843 td_flags = le32toh(td->td_flags); 844 cc = OHCI_TD_GET_CC(td_flags); 845 846 if (phy_start) { 847 /* 848 * short transfer - compute the number of remaining 849 * bytes in the hardware buffer: 850 */ 851 phy_end = le32toh(td->td_be); 852 temp = (OHCI_PAGE(phy_start ^ phy_end) ? 853 (OHCI_PAGE_SIZE + 1) : 0x0001); 854 temp += OHCI_PAGE_OFFSET(phy_end); 855 temp -= OHCI_PAGE_OFFSET(phy_start); 856 857 if (temp > td->len) { 858 /* guard against corruption */ 859 cc = OHCI_CC_STALL; 860 } else if (xfer->aframes != xfer->nframes) { 861 /* 862 * Sum up total transfer length 863 * in "frlengths[]": 864 */ 865 xfer->frlengths[xfer->aframes] += td->len - temp; 866 } 867 } else { 868 if (xfer->aframes != xfer->nframes) { 869 /* transfer was complete */ 870 xfer->frlengths[xfer->aframes] += td->len; 871 } 872 } 873 /* Check for last transfer */ 874 if (((void *)td) == xfer->td_transfer_last) { 875 td = NULL; 876 break; 877 } 878 /* Check transfer status */ 879 if (cc) { 880 /* the transfer is finished */ 881 td = NULL; 882 break; 883 } 884 /* Check for short transfer */ 885 if (phy_start) { 886 if (xfer->flags_int.short_frames_ok) { 887 /* follow alt next */ 888 td = td->alt_next; 889 } else { 890 /* the transfer is finished */ 891 td = NULL; 892 } 893 break; 894 } 895 td = td->obj_next; 896 897 if (td->alt_next != td_alt_next) { 898 /* this USB frame is complete */ 899 break; 900 } 901 } 902 903 /* update transfer cache */ 904 905 xfer->td_transfer_cache = td; 906 907 DPRINTFN(16, "error cc=%d (%s)\n", 908 cc, ohci_cc_strs[cc]); 909 910 return ((cc == 0) ? USB_ERR_NORMAL_COMPLETION : 911 (cc == OHCI_CC_STALL) ? USB_ERR_STALLED : USB_ERR_IOERROR); 912 } 913 914 static void 915 ohci_non_isoc_done(struct usb2_xfer *xfer) 916 { 917 usb2_error_t err = 0; 918 919 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 920 xfer, xfer->pipe); 921 922 #if USB_DEBUG 923 if (ohcidebug > 10) { 924 ohci_dump_tds(xfer->td_transfer_first); 925 } 926 #endif 927 928 /* reset scanner */ 929 930 xfer->td_transfer_cache = xfer->td_transfer_first; 931 932 if (xfer->flags_int.control_xfr) { 933 934 if (xfer->flags_int.control_hdr) { 935 936 err = ohci_non_isoc_done_sub(xfer); 937 } 938 xfer->aframes = 1; 939 940 if (xfer->td_transfer_cache == NULL) { 941 goto done; 942 } 943 } 944 while (xfer->aframes != xfer->nframes) { 945 946 err = ohci_non_isoc_done_sub(xfer); 947 xfer->aframes++; 948 949 if (xfer->td_transfer_cache == NULL) { 950 goto done; 951 } 952 } 953 954 if (xfer->flags_int.control_xfr && 955 !xfer->flags_int.control_act) { 956 957 err = ohci_non_isoc_done_sub(xfer); 958 } 959 done: 960 ohci_device_done(xfer, err); 961 } 962 963 /*------------------------------------------------------------------------* 964 * ohci_check_transfer_sub 965 *------------------------------------------------------------------------*/ 966 static void 967 ohci_check_transfer_sub(struct usb2_xfer *xfer) 968 { 969 ohci_td_t *td; 970 ohci_ed_t *ed; 971 uint32_t phy_start; 972 uint32_t td_flags; 973 uint32_t td_next; 974 uint16_t cc; 975 976 td = xfer->td_transfer_cache; 977 978 while (1) { 979 980 usb2_pc_cpu_invalidate(td->page_cache); 981 phy_start = le32toh(td->td_cbp); 982 td_flags = le32toh(td->td_flags); 983 td_next = le32toh(td->td_next); 984 985 /* Check for last transfer */ 986 if (((void *)td) == xfer->td_transfer_last) { 987 /* the transfer is finished */ 988 td = NULL; 989 break; 990 } 991 /* Check transfer status */ 992 cc = OHCI_TD_GET_CC(td_flags); 993 if (cc) { 994 /* the transfer is finished */ 995 td = NULL; 996 break; 997 } 998 /* 999 * Check if we reached the last packet 1000 * or if there is a short packet: 1001 */ 1002 1003 if (((td_next & (~0xF)) == OHCI_TD_NEXT_END) || phy_start) { 1004 /* follow alt next */ 1005 td = td->alt_next; 1006 break; 1007 } 1008 td = td->obj_next; 1009 } 1010 1011 /* update transfer cache */ 1012 1013 xfer->td_transfer_cache = td; 1014 1015 if (td) { 1016 1017 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1018 1019 ed->ed_headp = td->td_self; 1020 usb2_pc_cpu_flush(ed->page_cache); 1021 1022 DPRINTFN(13, "xfer=%p following alt next\n", xfer); 1023 1024 /* 1025 * Make sure that the OHCI re-scans the schedule by 1026 * writing the BLF and CLF bits: 1027 */ 1028 1029 if (xfer->xroot->udev->pwr_save.suspended) { 1030 /* nothing to do */ 1031 } else if (xfer->pipe->methods == &ohci_device_bulk_methods) { 1032 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1033 1034 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1035 } else if (xfer->pipe->methods == &ohci_device_ctrl_methods) { 1036 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1037 1038 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1039 } 1040 } 1041 } 1042 1043 /*------------------------------------------------------------------------* 1044 * ohci_check_transfer 1045 * 1046 * Return values: 1047 * 0: USB transfer is not finished 1048 * Else: USB transfer is finished 1049 *------------------------------------------------------------------------*/ 1050 static uint8_t 1051 ohci_check_transfer(struct usb2_xfer *xfer) 1052 { 1053 ohci_ed_t *ed; 1054 uint32_t ed_headp; 1055 uint32_t ed_tailp; 1056 1057 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1058 1059 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1060 1061 usb2_pc_cpu_invalidate(ed->page_cache); 1062 ed_headp = le32toh(ed->ed_headp); 1063 ed_tailp = le32toh(ed->ed_tailp); 1064 1065 if ((ed_headp & OHCI_HALTED) || 1066 (((ed_headp ^ ed_tailp) & (~0xF)) == 0)) { 1067 if (xfer->pipe->methods == &ohci_device_isoc_methods) { 1068 /* isochronous transfer */ 1069 ohci_isoc_done(xfer); 1070 } else { 1071 if (xfer->flags_int.short_frames_ok) { 1072 ohci_check_transfer_sub(xfer); 1073 if (xfer->td_transfer_cache) { 1074 /* not finished yet */ 1075 return (0); 1076 } 1077 } 1078 /* store data-toggle */ 1079 if (ed_headp & OHCI_TOGGLECARRY) { 1080 xfer->pipe->toggle_next = 1; 1081 } else { 1082 xfer->pipe->toggle_next = 0; 1083 } 1084 1085 /* non-isochronous transfer */ 1086 ohci_non_isoc_done(xfer); 1087 } 1088 return (1); 1089 } 1090 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1091 return (0); 1092 } 1093 1094 static void 1095 ohci_rhsc_enable(ohci_softc_t *sc) 1096 { 1097 DPRINTFN(5, "\n"); 1098 1099 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1100 1101 sc->sc_eintrs |= OHCI_RHSC; 1102 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1103 1104 /* acknowledge any RHSC interrupt */ 1105 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_RHSC); 1106 1107 usb2_sw_transfer(&sc->sc_root_intr, 1108 &ohci_root_intr_done); 1109 } 1110 1111 static void 1112 ohci_interrupt_poll(ohci_softc_t *sc) 1113 { 1114 struct usb2_xfer *xfer; 1115 1116 repeat: 1117 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1118 /* 1119 * check if transfer is transferred 1120 */ 1121 if (ohci_check_transfer(xfer)) { 1122 /* queue has been modified */ 1123 goto repeat; 1124 } 1125 } 1126 } 1127 1128 /*------------------------------------------------------------------------* 1129 * ohci_interrupt - OHCI interrupt handler 1130 * 1131 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1132 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1133 * is present ! 1134 *------------------------------------------------------------------------*/ 1135 void 1136 ohci_interrupt(ohci_softc_t *sc) 1137 { 1138 struct ohci_hcca *hcca; 1139 uint32_t status; 1140 uint32_t done; 1141 1142 USB_BUS_LOCK(&sc->sc_bus); 1143 1144 hcca = ohci_get_hcca(sc); 1145 1146 DPRINTFN(16, "real interrupt\n"); 1147 1148 #if USB_DEBUG 1149 if (ohcidebug > 15) { 1150 ohci_dumpregs(sc); 1151 } 1152 #endif 1153 1154 done = le32toh(hcca->hcca_done_head); 1155 1156 /* 1157 * The LSb of done is used to inform the HC Driver that an interrupt 1158 * condition exists for both the Done list and for another event 1159 * recorded in HcInterruptStatus. On an interrupt from the HC, the 1160 * HC Driver checks the HccaDoneHead Value. If this value is 0, then 1161 * the interrupt was caused by other than the HccaDoneHead update 1162 * and the HcInterruptStatus register needs to be accessed to 1163 * determine that exact interrupt cause. If HccaDoneHead is nonzero, 1164 * then a Done list update interrupt is indicated and if the LSb of 1165 * done is nonzero, then an additional interrupt event is indicated 1166 * and HcInterruptStatus should be checked to determine its cause. 1167 */ 1168 if (done != 0) { 1169 status = 0; 1170 1171 if (done & ~OHCI_DONE_INTRS) { 1172 status |= OHCI_WDH; 1173 } 1174 if (done & OHCI_DONE_INTRS) { 1175 status |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1176 } 1177 hcca->hcca_done_head = 0; 1178 1179 usb2_pc_cpu_flush(&sc->sc_hw.hcca_pc); 1180 } else { 1181 status = OREAD4(sc, OHCI_INTERRUPT_STATUS) & ~OHCI_WDH; 1182 } 1183 1184 status &= ~OHCI_MIE; 1185 if (status == 0) { 1186 /* 1187 * nothing to be done (PCI shared 1188 * interrupt) 1189 */ 1190 goto done; 1191 } 1192 OWRITE4(sc, OHCI_INTERRUPT_STATUS, status); /* Acknowledge */ 1193 1194 status &= sc->sc_eintrs; 1195 if (status == 0) { 1196 goto done; 1197 } 1198 if (status & (OHCI_SO | OHCI_RD | OHCI_UE | OHCI_RHSC)) { 1199 #if 0 1200 if (status & OHCI_SO) { 1201 /* XXX do what */ 1202 } 1203 #endif 1204 if (status & OHCI_RD) { 1205 printf("%s: resume detect\n", __FUNCTION__); 1206 /* XXX process resume detect */ 1207 } 1208 if (status & OHCI_UE) { 1209 printf("%s: unrecoverable error, " 1210 "controller halted\n", __FUNCTION__); 1211 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1212 /* XXX what else */ 1213 } 1214 if (status & OHCI_RHSC) { 1215 /* 1216 * Disable RHSC interrupt for now, because it will be 1217 * on until the port has been reset. 1218 */ 1219 sc->sc_eintrs &= ~OHCI_RHSC; 1220 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1221 1222 usb2_sw_transfer(&sc->sc_root_intr, 1223 &ohci_root_intr_done); 1224 1225 /* do not allow RHSC interrupts > 1 per second */ 1226 usb2_callout_reset(&sc->sc_tmo_rhsc, hz, 1227 (void *)&ohci_rhsc_enable, sc); 1228 } 1229 } 1230 status &= ~(OHCI_RHSC | OHCI_WDH | OHCI_SO); 1231 if (status != 0) { 1232 /* Block unprocessed interrupts. XXX */ 1233 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, status); 1234 sc->sc_eintrs &= ~status; 1235 printf("%s: blocking intrs 0x%x\n", 1236 __FUNCTION__, status); 1237 } 1238 /* poll all the USB transfers */ 1239 ohci_interrupt_poll(sc); 1240 1241 done: 1242 USB_BUS_UNLOCK(&sc->sc_bus); 1243 } 1244 1245 /* 1246 * called when a request does not complete 1247 */ 1248 static void 1249 ohci_timeout(void *arg) 1250 { 1251 struct usb2_xfer *xfer = arg; 1252 1253 DPRINTF("xfer=%p\n", xfer); 1254 1255 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1256 1257 /* transfer is transferred */ 1258 ohci_device_done(xfer, USB_ERR_TIMEOUT); 1259 } 1260 1261 static void 1262 ohci_do_poll(struct usb2_bus *bus) 1263 { 1264 struct ohci_softc *sc = OHCI_BUS2SC(bus); 1265 1266 USB_BUS_LOCK(&sc->sc_bus); 1267 ohci_interrupt_poll(sc); 1268 ohci_root_ctrl_poll(sc); 1269 USB_BUS_UNLOCK(&sc->sc_bus); 1270 } 1271 1272 static void 1273 ohci_setup_standard_chain_sub(struct ohci_std_temp *temp) 1274 { 1275 struct usb2_page_search buf_res; 1276 ohci_td_t *td; 1277 ohci_td_t *td_next; 1278 ohci_td_t *td_alt_next; 1279 uint32_t buf_offset; 1280 uint32_t average; 1281 uint32_t len_old; 1282 uint8_t shortpkt_old; 1283 uint8_t precompute; 1284 1285 td_alt_next = NULL; 1286 buf_offset = 0; 1287 shortpkt_old = temp->shortpkt; 1288 len_old = temp->len; 1289 precompute = 1; 1290 1291 /* software is used to detect short incoming transfers */ 1292 1293 if ((temp->td_flags & htole32(OHCI_TD_DP_MASK)) == htole32(OHCI_TD_IN)) { 1294 temp->td_flags |= htole32(OHCI_TD_R); 1295 } else { 1296 temp->td_flags &= ~htole32(OHCI_TD_R); 1297 } 1298 1299 restart: 1300 1301 td = temp->td; 1302 td_next = temp->td_next; 1303 1304 while (1) { 1305 1306 if (temp->len == 0) { 1307 1308 if (temp->shortpkt) { 1309 break; 1310 } 1311 /* send a Zero Length Packet, ZLP, last */ 1312 1313 temp->shortpkt = 1; 1314 average = 0; 1315 1316 } else { 1317 1318 average = temp->average; 1319 1320 if (temp->len < average) { 1321 if (temp->len % temp->max_frame_size) { 1322 temp->shortpkt = 1; 1323 } 1324 average = temp->len; 1325 } 1326 } 1327 1328 if (td_next == NULL) { 1329 panic("%s: out of OHCI transfer descriptors!", __FUNCTION__); 1330 } 1331 /* get next TD */ 1332 1333 td = td_next; 1334 td_next = td->obj_next; 1335 1336 /* check if we are pre-computing */ 1337 1338 if (precompute) { 1339 1340 /* update remaining length */ 1341 1342 temp->len -= average; 1343 1344 continue; 1345 } 1346 /* fill out current TD */ 1347 td->td_flags = temp->td_flags; 1348 1349 /* the next TD uses TOGGLE_CARRY */ 1350 temp->td_flags &= ~htole32(OHCI_TD_TOGGLE_MASK); 1351 1352 if (average == 0) { 1353 /* 1354 * The buffer start and end phys addresses should be 1355 * 0x0 for a zero length packet. 1356 */ 1357 td->td_cbp = 0; 1358 td->td_be = 0; 1359 td->len = 0; 1360 1361 } else { 1362 1363 usb2_get_page(temp->pc, buf_offset, &buf_res); 1364 td->td_cbp = htole32(buf_res.physaddr); 1365 buf_offset += (average - 1); 1366 1367 usb2_get_page(temp->pc, buf_offset, &buf_res); 1368 td->td_be = htole32(buf_res.physaddr); 1369 buf_offset++; 1370 1371 td->len = average; 1372 1373 /* update remaining length */ 1374 1375 temp->len -= average; 1376 } 1377 1378 if ((td_next == td_alt_next) && temp->setup_alt_next) { 1379 /* we need to receive these frames one by one ! */ 1380 td->td_flags &= htole32(~OHCI_TD_INTR_MASK); 1381 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1382 td->td_next = htole32(OHCI_TD_NEXT_END); 1383 } else { 1384 if (td_next) { 1385 /* link the current TD with the next one */ 1386 td->td_next = td_next->td_self; 1387 } 1388 } 1389 1390 td->alt_next = td_alt_next; 1391 1392 usb2_pc_cpu_flush(td->page_cache); 1393 } 1394 1395 if (precompute) { 1396 precompute = 0; 1397 1398 /* setup alt next pointer, if any */ 1399 if (temp->last_frame) { 1400 /* no alternate next */ 1401 td_alt_next = NULL; 1402 } else { 1403 /* we use this field internally */ 1404 td_alt_next = td_next; 1405 } 1406 1407 /* restore */ 1408 temp->shortpkt = shortpkt_old; 1409 temp->len = len_old; 1410 goto restart; 1411 } 1412 temp->td = td; 1413 temp->td_next = td_next; 1414 } 1415 1416 static void 1417 ohci_setup_standard_chain(struct usb2_xfer *xfer, ohci_ed_t **ed_last) 1418 { 1419 struct ohci_std_temp temp; 1420 struct usb2_pipe_methods *methods; 1421 ohci_ed_t *ed; 1422 ohci_td_t *td; 1423 uint32_t ed_flags; 1424 uint32_t x; 1425 1426 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1427 xfer->address, UE_GET_ADDR(xfer->endpoint), 1428 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1429 1430 temp.average = xfer->max_hc_frame_size; 1431 temp.max_frame_size = xfer->max_frame_size; 1432 1433 /* toggle the DMA set we are using */ 1434 xfer->flags_int.curr_dma_set ^= 1; 1435 1436 /* get next DMA set */ 1437 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1438 1439 xfer->td_transfer_first = td; 1440 xfer->td_transfer_cache = td; 1441 1442 temp.td = NULL; 1443 temp.td_next = td; 1444 temp.last_frame = 0; 1445 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1446 1447 methods = xfer->pipe->methods; 1448 1449 /* check if we should prepend a setup message */ 1450 1451 if (xfer->flags_int.control_xfr) { 1452 if (xfer->flags_int.control_hdr) { 1453 1454 temp.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1455 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1456 1457 temp.len = xfer->frlengths[0]; 1458 temp.pc = xfer->frbuffers + 0; 1459 temp.shortpkt = temp.len ? 1 : 0; 1460 /* check for last frame */ 1461 if (xfer->nframes == 1) { 1462 /* no STATUS stage yet, SETUP is last */ 1463 if (xfer->flags_int.control_act) { 1464 temp.last_frame = 1; 1465 temp.setup_alt_next = 0; 1466 } 1467 } 1468 ohci_setup_standard_chain_sub(&temp); 1469 1470 /* 1471 * XXX assume that the setup message is 1472 * contained within one USB packet: 1473 */ 1474 xfer->pipe->toggle_next = 1; 1475 } 1476 x = 1; 1477 } else { 1478 x = 0; 1479 } 1480 temp.td_flags = htole32(OHCI_TD_NOCC | OHCI_TD_NOINTR); 1481 1482 /* set data toggle */ 1483 1484 if (xfer->pipe->toggle_next) { 1485 temp.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1486 } else { 1487 temp.td_flags |= htole32(OHCI_TD_TOGGLE_0); 1488 } 1489 1490 /* set endpoint direction */ 1491 1492 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 1493 temp.td_flags |= htole32(OHCI_TD_IN); 1494 } else { 1495 temp.td_flags |= htole32(OHCI_TD_OUT); 1496 } 1497 1498 while (x != xfer->nframes) { 1499 1500 /* DATA0 / DATA1 message */ 1501 1502 temp.len = xfer->frlengths[x]; 1503 temp.pc = xfer->frbuffers + x; 1504 1505 x++; 1506 1507 if (x == xfer->nframes) { 1508 if (xfer->flags_int.control_xfr) { 1509 /* no STATUS stage yet, DATA is last */ 1510 if (xfer->flags_int.control_act) { 1511 temp.last_frame = 1; 1512 temp.setup_alt_next = 0; 1513 } 1514 } else { 1515 temp.last_frame = 1; 1516 temp.setup_alt_next = 0; 1517 } 1518 } 1519 if (temp.len == 0) { 1520 1521 /* make sure that we send an USB packet */ 1522 1523 temp.shortpkt = 0; 1524 1525 } else { 1526 1527 /* regular data transfer */ 1528 1529 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1530 } 1531 1532 ohci_setup_standard_chain_sub(&temp); 1533 } 1534 1535 /* check if we should append a status stage */ 1536 1537 if (xfer->flags_int.control_xfr && 1538 !xfer->flags_int.control_act) { 1539 1540 /* 1541 * Send a DATA1 message and invert the current endpoint 1542 * direction. 1543 */ 1544 1545 /* set endpoint direction and data toggle */ 1546 1547 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 1548 temp.td_flags = htole32(OHCI_TD_OUT | 1549 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1550 } else { 1551 temp.td_flags = htole32(OHCI_TD_IN | 1552 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1553 } 1554 1555 temp.len = 0; 1556 temp.pc = NULL; 1557 temp.shortpkt = 0; 1558 temp.last_frame = 1; 1559 temp.setup_alt_next = 0; 1560 1561 ohci_setup_standard_chain_sub(&temp); 1562 } 1563 td = temp.td; 1564 1565 /* Ensure that last TD is terminating: */ 1566 td->td_next = htole32(OHCI_TD_NEXT_END); 1567 td->td_flags &= ~htole32(OHCI_TD_INTR_MASK); 1568 td->td_flags |= htole32(OHCI_TD_SET_DI(1)); 1569 1570 usb2_pc_cpu_flush(td->page_cache); 1571 1572 /* must have at least one frame! */ 1573 1574 xfer->td_transfer_last = td; 1575 1576 #if USB_DEBUG 1577 if (ohcidebug > 8) { 1578 DPRINTF("nexttog=%d; data before transfer:\n", 1579 xfer->pipe->toggle_next); 1580 ohci_dump_tds(xfer->td_transfer_first); 1581 } 1582 #endif 1583 1584 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1585 1586 ed_flags = (OHCI_ED_SET_FA(xfer->address) | 1587 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) | 1588 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 1589 1590 ed_flags |= (OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD); 1591 1592 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 1593 ed_flags |= OHCI_ED_SPEED; 1594 } 1595 ed->ed_flags = htole32(ed_flags); 1596 1597 td = xfer->td_transfer_first; 1598 1599 ed->ed_headp = td->td_self; 1600 1601 if (xfer->xroot->udev->pwr_save.suspended == 0) { 1602 /* the append function will flush the endpoint descriptor */ 1603 OHCI_APPEND_QH(ed, *ed_last); 1604 1605 if (methods == &ohci_device_bulk_methods) { 1606 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1607 1608 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1609 } 1610 if (methods == &ohci_device_ctrl_methods) { 1611 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1612 1613 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1614 } 1615 } else { 1616 usb2_pc_cpu_flush(ed->page_cache); 1617 } 1618 } 1619 1620 static void 1621 ohci_root_intr_done(struct usb2_xfer *xfer, 1622 struct usb2_sw_transfer *std) 1623 { 1624 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1625 uint32_t hstatus; 1626 uint16_t i; 1627 uint16_t m; 1628 1629 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1630 1631 if (std->state != USB_SW_TR_PRE_DATA) { 1632 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1633 /* transfer transferred */ 1634 ohci_device_done(xfer, std->err); 1635 } 1636 goto done; 1637 } 1638 /* setup buffer */ 1639 std->ptr = sc->sc_hub_idata; 1640 std->len = sizeof(sc->sc_hub_idata); 1641 1642 /* clear any old interrupt data */ 1643 bzero(sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); 1644 1645 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1646 DPRINTF("sc=%p xfer=%p hstatus=0x%08x\n", 1647 sc, xfer, hstatus); 1648 1649 /* set bits */ 1650 m = (sc->sc_noport + 1); 1651 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1652 m = (8 * sizeof(sc->sc_hub_idata)); 1653 } 1654 for (i = 1; i < m; i++) { 1655 /* pick out CHANGE bits from the status register */ 1656 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) { 1657 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1658 DPRINTF("port %d changed\n", i); 1659 } 1660 } 1661 done: 1662 return; 1663 } 1664 1665 /* NOTE: "done" can be run two times in a row, 1666 * from close and from interrupt 1667 */ 1668 static void 1669 ohci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1670 { 1671 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1672 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1673 ohci_ed_t *ed; 1674 1675 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1676 1677 1678 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1679 xfer, xfer->pipe, error); 1680 1681 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1682 if (ed) { 1683 usb2_pc_cpu_invalidate(ed->page_cache); 1684 } 1685 if (methods == &ohci_device_bulk_methods) { 1686 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 1687 } 1688 if (methods == &ohci_device_ctrl_methods) { 1689 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 1690 } 1691 if (methods == &ohci_device_intr_methods) { 1692 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 1693 } 1694 if (methods == &ohci_device_isoc_methods) { 1695 OHCI_REMOVE_QH(ed, sc->sc_isoc_p_last); 1696 } 1697 xfer->td_transfer_first = NULL; 1698 xfer->td_transfer_last = NULL; 1699 1700 /* dequeue transfer and start next transfer */ 1701 usb2_transfer_done(xfer, error); 1702 } 1703 1704 /*------------------------------------------------------------------------* 1705 * ohci bulk support 1706 *------------------------------------------------------------------------*/ 1707 static void 1708 ohci_device_bulk_open(struct usb2_xfer *xfer) 1709 { 1710 return; 1711 } 1712 1713 static void 1714 ohci_device_bulk_close(struct usb2_xfer *xfer) 1715 { 1716 ohci_device_done(xfer, USB_ERR_CANCELLED); 1717 } 1718 1719 static void 1720 ohci_device_bulk_enter(struct usb2_xfer *xfer) 1721 { 1722 return; 1723 } 1724 1725 static void 1726 ohci_device_bulk_start(struct usb2_xfer *xfer) 1727 { 1728 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1729 1730 /* setup TD's and QH */ 1731 ohci_setup_standard_chain(xfer, &sc->sc_bulk_p_last); 1732 1733 /* put transfer on interrupt queue */ 1734 ohci_transfer_intr_enqueue(xfer); 1735 } 1736 1737 struct usb2_pipe_methods ohci_device_bulk_methods = 1738 { 1739 .open = ohci_device_bulk_open, 1740 .close = ohci_device_bulk_close, 1741 .enter = ohci_device_bulk_enter, 1742 .start = ohci_device_bulk_start, 1743 .enter_is_cancelable = 1, 1744 .start_is_cancelable = 1, 1745 }; 1746 1747 /*------------------------------------------------------------------------* 1748 * ohci control support 1749 *------------------------------------------------------------------------*/ 1750 static void 1751 ohci_device_ctrl_open(struct usb2_xfer *xfer) 1752 { 1753 return; 1754 } 1755 1756 static void 1757 ohci_device_ctrl_close(struct usb2_xfer *xfer) 1758 { 1759 ohci_device_done(xfer, USB_ERR_CANCELLED); 1760 } 1761 1762 static void 1763 ohci_device_ctrl_enter(struct usb2_xfer *xfer) 1764 { 1765 return; 1766 } 1767 1768 static void 1769 ohci_device_ctrl_start(struct usb2_xfer *xfer) 1770 { 1771 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1772 1773 /* setup TD's and QH */ 1774 ohci_setup_standard_chain(xfer, &sc->sc_ctrl_p_last); 1775 1776 /* put transfer on interrupt queue */ 1777 ohci_transfer_intr_enqueue(xfer); 1778 } 1779 1780 struct usb2_pipe_methods ohci_device_ctrl_methods = 1781 { 1782 .open = ohci_device_ctrl_open, 1783 .close = ohci_device_ctrl_close, 1784 .enter = ohci_device_ctrl_enter, 1785 .start = ohci_device_ctrl_start, 1786 .enter_is_cancelable = 1, 1787 .start_is_cancelable = 1, 1788 }; 1789 1790 /*------------------------------------------------------------------------* 1791 * ohci interrupt support 1792 *------------------------------------------------------------------------*/ 1793 static void 1794 ohci_device_intr_open(struct usb2_xfer *xfer) 1795 { 1796 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1797 uint16_t best; 1798 uint16_t bit; 1799 uint16_t x; 1800 1801 best = 0; 1802 bit = OHCI_NO_EDS / 2; 1803 while (bit) { 1804 if (xfer->interval >= bit) { 1805 x = bit; 1806 best = bit; 1807 while (x & bit) { 1808 if (sc->sc_intr_stat[x] < 1809 sc->sc_intr_stat[best]) { 1810 best = x; 1811 } 1812 x++; 1813 } 1814 break; 1815 } 1816 bit >>= 1; 1817 } 1818 1819 sc->sc_intr_stat[best]++; 1820 xfer->qh_pos = best; 1821 1822 DPRINTFN(3, "best=%d interval=%d\n", 1823 best, xfer->interval); 1824 } 1825 1826 static void 1827 ohci_device_intr_close(struct usb2_xfer *xfer) 1828 { 1829 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1830 1831 sc->sc_intr_stat[xfer->qh_pos]--; 1832 1833 ohci_device_done(xfer, USB_ERR_CANCELLED); 1834 } 1835 1836 static void 1837 ohci_device_intr_enter(struct usb2_xfer *xfer) 1838 { 1839 return; 1840 } 1841 1842 static void 1843 ohci_device_intr_start(struct usb2_xfer *xfer) 1844 { 1845 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1846 1847 /* setup TD's and QH */ 1848 ohci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 1849 1850 /* put transfer on interrupt queue */ 1851 ohci_transfer_intr_enqueue(xfer); 1852 } 1853 1854 struct usb2_pipe_methods ohci_device_intr_methods = 1855 { 1856 .open = ohci_device_intr_open, 1857 .close = ohci_device_intr_close, 1858 .enter = ohci_device_intr_enter, 1859 .start = ohci_device_intr_start, 1860 .enter_is_cancelable = 1, 1861 .start_is_cancelable = 1, 1862 }; 1863 1864 /*------------------------------------------------------------------------* 1865 * ohci isochronous support 1866 *------------------------------------------------------------------------*/ 1867 static void 1868 ohci_device_isoc_open(struct usb2_xfer *xfer) 1869 { 1870 return; 1871 } 1872 1873 static void 1874 ohci_device_isoc_close(struct usb2_xfer *xfer) 1875 { 1876 /**/ 1877 ohci_device_done(xfer, USB_ERR_CANCELLED); 1878 } 1879 1880 static void 1881 ohci_device_isoc_enter(struct usb2_xfer *xfer) 1882 { 1883 struct usb2_page_search buf_res; 1884 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 1885 struct ohci_hcca *hcca; 1886 uint32_t buf_offset; 1887 uint32_t nframes; 1888 uint32_t ed_flags; 1889 uint32_t *plen; 1890 uint16_t itd_offset[OHCI_ITD_NOFFSET]; 1891 uint16_t length; 1892 uint8_t ncur; 1893 ohci_itd_t *td; 1894 ohci_itd_t *td_last = NULL; 1895 ohci_ed_t *ed; 1896 1897 hcca = ohci_get_hcca(sc); 1898 1899 nframes = le32toh(hcca->hcca_frame_number); 1900 1901 DPRINTFN(6, "xfer=%p isoc_next=%u nframes=%u hcca_fn=%u\n", 1902 xfer, xfer->pipe->isoc_next, xfer->nframes, nframes); 1903 1904 if ((xfer->pipe->is_synced == 0) || 1905 (((nframes - xfer->pipe->isoc_next) & 0xFFFF) < xfer->nframes) || 1906 (((xfer->pipe->isoc_next - nframes) & 0xFFFF) >= 128)) { 1907 /* 1908 * If there is data underflow or the pipe queue is empty we 1909 * schedule the transfer a few frames ahead of the current 1910 * frame position. Else two isochronous transfers might 1911 * overlap. 1912 */ 1913 xfer->pipe->isoc_next = (nframes + 3) & 0xFFFF; 1914 xfer->pipe->is_synced = 1; 1915 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1916 } 1917 /* 1918 * compute how many milliseconds the insertion is ahead of the 1919 * current frame position: 1920 */ 1921 buf_offset = ((xfer->pipe->isoc_next - nframes) & 0xFFFF); 1922 1923 /* 1924 * pre-compute when the isochronous transfer will be finished: 1925 */ 1926 xfer->isoc_time_complete = 1927 (usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 1928 xfer->nframes); 1929 1930 /* get the real number of frames */ 1931 1932 nframes = xfer->nframes; 1933 1934 buf_offset = 0; 1935 1936 plen = xfer->frlengths; 1937 1938 /* toggle the DMA set we are using */ 1939 xfer->flags_int.curr_dma_set ^= 1; 1940 1941 /* get next DMA set */ 1942 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1943 1944 xfer->td_transfer_first = td; 1945 1946 ncur = 0; 1947 length = 0; 1948 1949 while (nframes--) { 1950 if (td == NULL) { 1951 panic("%s:%d: out of TD's\n", 1952 __FUNCTION__, __LINE__); 1953 } 1954 itd_offset[ncur] = length; 1955 buf_offset += *plen; 1956 length += *plen; 1957 plen++; 1958 ncur++; 1959 1960 if ( /* check if the ITD is full */ 1961 (ncur == OHCI_ITD_NOFFSET) || 1962 /* check if we have put more than 4K into the ITD */ 1963 (length & 0xF000) || 1964 /* check if it is the last frame */ 1965 (nframes == 0)) { 1966 1967 /* fill current ITD */ 1968 td->itd_flags = htole32( 1969 OHCI_ITD_NOCC | 1970 OHCI_ITD_SET_SF(xfer->pipe->isoc_next) | 1971 OHCI_ITD_NOINTR | 1972 OHCI_ITD_SET_FC(ncur)); 1973 1974 td->frames = ncur; 1975 xfer->pipe->isoc_next += ncur; 1976 1977 if (length == 0) { 1978 /* all zero */ 1979 td->itd_bp0 = 0; 1980 td->itd_be = ~0; 1981 1982 while (ncur--) { 1983 td->itd_offset[ncur] = 1984 htole16(OHCI_ITD_MK_OFFS(0)); 1985 } 1986 } else { 1987 usb2_get_page(xfer->frbuffers, buf_offset - length, &buf_res); 1988 length = OHCI_PAGE_MASK(buf_res.physaddr); 1989 buf_res.physaddr = 1990 OHCI_PAGE(buf_res.physaddr); 1991 td->itd_bp0 = htole32(buf_res.physaddr); 1992 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 1993 td->itd_be = htole32(buf_res.physaddr); 1994 1995 while (ncur--) { 1996 itd_offset[ncur] += length; 1997 itd_offset[ncur] = 1998 OHCI_ITD_MK_OFFS(itd_offset[ncur]); 1999 td->itd_offset[ncur] = 2000 htole16(itd_offset[ncur]); 2001 } 2002 } 2003 ncur = 0; 2004 length = 0; 2005 td_last = td; 2006 td = td->obj_next; 2007 2008 if (td) { 2009 /* link the last TD with the next one */ 2010 td_last->itd_next = td->itd_self; 2011 } 2012 usb2_pc_cpu_flush(td_last->page_cache); 2013 } 2014 } 2015 2016 /* update the last TD */ 2017 td_last->itd_flags &= ~htole32(OHCI_ITD_NOINTR); 2018 td_last->itd_flags |= htole32(OHCI_ITD_SET_DI(0)); 2019 td_last->itd_next = 0; 2020 2021 usb2_pc_cpu_flush(td_last->page_cache); 2022 2023 xfer->td_transfer_last = td_last; 2024 2025 #if USB_DEBUG 2026 if (ohcidebug > 8) { 2027 DPRINTF("data before transfer:\n"); 2028 ohci_dump_itds(xfer->td_transfer_first); 2029 } 2030 #endif 2031 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2032 2033 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) 2034 ed_flags = (OHCI_ED_DIR_IN | OHCI_ED_FORMAT_ISO); 2035 else 2036 ed_flags = (OHCI_ED_DIR_OUT | OHCI_ED_FORMAT_ISO); 2037 2038 ed_flags |= (OHCI_ED_SET_FA(xfer->address) | 2039 OHCI_ED_SET_EN(UE_GET_ADDR(xfer->endpoint)) | 2040 OHCI_ED_SET_MAXP(xfer->max_frame_size)); 2041 2042 if (xfer->xroot->udev->speed == USB_SPEED_LOW) { 2043 ed_flags |= OHCI_ED_SPEED; 2044 } 2045 ed->ed_flags = htole32(ed_flags); 2046 2047 td = xfer->td_transfer_first; 2048 2049 ed->ed_headp = td->itd_self; 2050 2051 /* isochronous transfers are not affected by suspend / resume */ 2052 /* the append function will flush the endpoint descriptor */ 2053 2054 OHCI_APPEND_QH(ed, sc->sc_isoc_p_last); 2055 } 2056 2057 static void 2058 ohci_device_isoc_start(struct usb2_xfer *xfer) 2059 { 2060 /* put transfer on interrupt queue */ 2061 ohci_transfer_intr_enqueue(xfer); 2062 } 2063 2064 struct usb2_pipe_methods ohci_device_isoc_methods = 2065 { 2066 .open = ohci_device_isoc_open, 2067 .close = ohci_device_isoc_close, 2068 .enter = ohci_device_isoc_enter, 2069 .start = ohci_device_isoc_start, 2070 .enter_is_cancelable = 1, 2071 .start_is_cancelable = 1, 2072 }; 2073 2074 /*------------------------------------------------------------------------* 2075 * ohci root control support 2076 *------------------------------------------------------------------------* 2077 * simulate a hardware hub by handling 2078 * all the necessary requests 2079 *------------------------------------------------------------------------*/ 2080 2081 static void 2082 ohci_root_ctrl_open(struct usb2_xfer *xfer) 2083 { 2084 return; 2085 } 2086 2087 static void 2088 ohci_root_ctrl_close(struct usb2_xfer *xfer) 2089 { 2090 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2091 2092 if (sc->sc_root_ctrl.xfer == xfer) { 2093 sc->sc_root_ctrl.xfer = NULL; 2094 } 2095 ohci_device_done(xfer, USB_ERR_CANCELLED); 2096 } 2097 2098 /* data structures and routines 2099 * to emulate the root hub: 2100 */ 2101 static const 2102 struct usb2_device_descriptor ohci_devd = 2103 { 2104 sizeof(struct usb2_device_descriptor), 2105 UDESC_DEVICE, /* type */ 2106 {0x00, 0x01}, /* USB version */ 2107 UDCLASS_HUB, /* class */ 2108 UDSUBCLASS_HUB, /* subclass */ 2109 UDPROTO_FSHUB, /* protocol */ 2110 64, /* max packet */ 2111 {0}, {0}, {0x00, 0x01}, /* device id */ 2112 1, 2, 0, /* string indicies */ 2113 1 /* # of configurations */ 2114 }; 2115 2116 static const 2117 struct ohci_config_desc ohci_confd = 2118 { 2119 .confd = { 2120 .bLength = sizeof(struct usb2_config_descriptor), 2121 .bDescriptorType = UDESC_CONFIG, 2122 .wTotalLength[0] = sizeof(ohci_confd), 2123 .bNumInterface = 1, 2124 .bConfigurationValue = 1, 2125 .iConfiguration = 0, 2126 .bmAttributes = UC_SELF_POWERED, 2127 .bMaxPower = 0, /* max power */ 2128 }, 2129 2130 .ifcd = { 2131 .bLength = sizeof(struct usb2_interface_descriptor), 2132 .bDescriptorType = UDESC_INTERFACE, 2133 .bNumEndpoints = 1, 2134 .bInterfaceClass = UICLASS_HUB, 2135 .bInterfaceSubClass = UISUBCLASS_HUB, 2136 .bInterfaceProtocol = UIPROTO_FSHUB, 2137 }, 2138 2139 .endpd = { 2140 .bLength = sizeof(struct usb2_endpoint_descriptor), 2141 .bDescriptorType = UDESC_ENDPOINT, 2142 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2143 .bmAttributes = UE_INTERRUPT, 2144 .wMaxPacketSize[0] = 32,/* max packet (255 ports) */ 2145 .bInterval = 255, 2146 }, 2147 }; 2148 2149 static const 2150 struct usb2_hub_descriptor ohci_hubd = 2151 { 2152 0, /* dynamic length */ 2153 UDESC_HUB, 2154 0, 2155 {0, 0}, 2156 0, 2157 0, 2158 {0}, 2159 }; 2160 2161 static void 2162 ohci_root_ctrl_enter(struct usb2_xfer *xfer) 2163 { 2164 return; 2165 } 2166 2167 static void 2168 ohci_root_ctrl_start(struct usb2_xfer *xfer) 2169 { 2170 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2171 2172 sc->sc_root_ctrl.xfer = xfer; 2173 2174 usb2_bus_roothub_exec(xfer->xroot->bus); 2175 } 2176 2177 static void 2178 ohci_root_ctrl_task(struct usb2_bus *bus) 2179 { 2180 ohci_root_ctrl_poll(OHCI_BUS2SC(bus)); 2181 } 2182 2183 static void 2184 ohci_root_ctrl_done(struct usb2_xfer *xfer, 2185 struct usb2_sw_transfer *std) 2186 { 2187 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2188 char *ptr; 2189 uint32_t port; 2190 uint32_t v; 2191 uint16_t value; 2192 uint16_t index; 2193 uint8_t l; 2194 2195 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2196 2197 if (std->state != USB_SW_TR_SETUP) { 2198 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2199 /* transfer transferred */ 2200 ohci_device_done(xfer, std->err); 2201 } 2202 goto done; 2203 } 2204 /* buffer reset */ 2205 std->ptr = sc->sc_hub_desc.temp; 2206 std->len = 0; 2207 2208 value = UGETW(std->req.wValue); 2209 index = UGETW(std->req.wIndex); 2210 2211 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2212 "wValue=0x%04x wIndex=0x%04x\n", 2213 std->req.bmRequestType, std->req.bRequest, 2214 UGETW(std->req.wLength), value, index); 2215 2216 #define C(x,y) ((x) | ((y) << 8)) 2217 switch (C(std->req.bRequest, std->req.bmRequestType)) { 2218 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2219 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2220 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2221 /* 2222 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2223 * for the integrated root hub. 2224 */ 2225 break; 2226 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2227 std->len = 1; 2228 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2229 break; 2230 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2231 switch (value >> 8) { 2232 case UDESC_DEVICE: 2233 if ((value & 0xff) != 0) { 2234 std->err = USB_ERR_IOERROR; 2235 goto done; 2236 } 2237 std->len = sizeof(ohci_devd); 2238 sc->sc_hub_desc.devd = ohci_devd; 2239 break; 2240 2241 case UDESC_CONFIG: 2242 if ((value & 0xff) != 0) { 2243 std->err = USB_ERR_IOERROR; 2244 goto done; 2245 } 2246 std->len = sizeof(ohci_confd); 2247 std->ptr = USB_ADD_BYTES(&ohci_confd, 0); 2248 break; 2249 2250 case UDESC_STRING: 2251 switch (value & 0xff) { 2252 case 0: /* Language table */ 2253 ptr = "\001"; 2254 break; 2255 2256 case 1: /* Vendor */ 2257 ptr = sc->sc_vendor; 2258 break; 2259 2260 case 2: /* Product */ 2261 ptr = "OHCI root HUB"; 2262 break; 2263 2264 default: 2265 ptr = ""; 2266 break; 2267 } 2268 2269 std->len = usb2_make_str_desc 2270 (sc->sc_hub_desc.temp, 2271 sizeof(sc->sc_hub_desc.temp), 2272 ptr); 2273 break; 2274 2275 default: 2276 std->err = USB_ERR_IOERROR; 2277 goto done; 2278 } 2279 break; 2280 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2281 std->len = 1; 2282 sc->sc_hub_desc.temp[0] = 0; 2283 break; 2284 case C(UR_GET_STATUS, UT_READ_DEVICE): 2285 std->len = 2; 2286 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 2287 break; 2288 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2289 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2290 std->len = 2; 2291 USETW(sc->sc_hub_desc.stat.wStatus, 0); 2292 break; 2293 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2294 if (value >= OHCI_MAX_DEVICES) { 2295 std->err = USB_ERR_IOERROR; 2296 goto done; 2297 } 2298 sc->sc_addr = value; 2299 break; 2300 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2301 if ((value != 0) && (value != 1)) { 2302 std->err = USB_ERR_IOERROR; 2303 goto done; 2304 } 2305 sc->sc_conf = value; 2306 break; 2307 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2308 break; 2309 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2310 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2311 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2312 std->err = USB_ERR_IOERROR; 2313 goto done; 2314 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2315 break; 2316 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2317 break; 2318 /* Hub requests */ 2319 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2320 break; 2321 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2322 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE " 2323 "port=%d feature=%d\n", 2324 index, value); 2325 if ((index < 1) || 2326 (index > sc->sc_noport)) { 2327 std->err = USB_ERR_IOERROR; 2328 goto done; 2329 } 2330 port = OHCI_RH_PORT_STATUS(index); 2331 switch (value) { 2332 case UHF_PORT_ENABLE: 2333 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2334 break; 2335 case UHF_PORT_SUSPEND: 2336 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2337 break; 2338 case UHF_PORT_POWER: 2339 /* Yes, writing to the LOW_SPEED bit clears power. */ 2340 OWRITE4(sc, port, UPS_LOW_SPEED); 2341 break; 2342 case UHF_C_PORT_CONNECTION: 2343 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2344 break; 2345 case UHF_C_PORT_ENABLE: 2346 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2347 break; 2348 case UHF_C_PORT_SUSPEND: 2349 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2350 break; 2351 case UHF_C_PORT_OVER_CURRENT: 2352 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2353 break; 2354 case UHF_C_PORT_RESET: 2355 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2356 break; 2357 default: 2358 std->err = USB_ERR_IOERROR; 2359 goto done; 2360 } 2361 switch (value) { 2362 case UHF_C_PORT_CONNECTION: 2363 case UHF_C_PORT_ENABLE: 2364 case UHF_C_PORT_SUSPEND: 2365 case UHF_C_PORT_OVER_CURRENT: 2366 case UHF_C_PORT_RESET: 2367 /* enable RHSC interrupt if condition is cleared. */ 2368 if ((OREAD4(sc, port) >> 16) == 0) 2369 ohci_rhsc_enable(sc); 2370 break; 2371 default: 2372 break; 2373 } 2374 break; 2375 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2376 if ((value & 0xff) != 0) { 2377 std->err = USB_ERR_IOERROR; 2378 goto done; 2379 } 2380 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2381 2382 sc->sc_hub_desc.hubd = ohci_hubd; 2383 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 2384 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 2385 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2386 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2387 /* XXX overcurrent */ 2388 ); 2389 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2390 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2391 2392 for (l = 0; l < sc->sc_noport; l++) { 2393 if (v & 1) { 2394 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] |= (1 << (l % 8)); 2395 } 2396 v >>= 1; 2397 } 2398 sc->sc_hub_desc.hubd.bDescLength = 2399 8 + ((sc->sc_noport + 7) / 8); 2400 std->len = sc->sc_hub_desc.hubd.bDescLength; 2401 break; 2402 2403 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2404 std->len = 16; 2405 bzero(sc->sc_hub_desc.temp, 16); 2406 break; 2407 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2408 DPRINTFN(9, "get port status i=%d\n", 2409 index); 2410 if ((index < 1) || 2411 (index > sc->sc_noport)) { 2412 std->err = USB_ERR_IOERROR; 2413 goto done; 2414 } 2415 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2416 DPRINTFN(9, "port status=0x%04x\n", v); 2417 USETW(sc->sc_hub_desc.ps.wPortStatus, v); 2418 USETW(sc->sc_hub_desc.ps.wPortChange, v >> 16); 2419 std->len = sizeof(sc->sc_hub_desc.ps); 2420 break; 2421 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2422 std->err = USB_ERR_IOERROR; 2423 goto done; 2424 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2425 break; 2426 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2427 if ((index < 1) || 2428 (index > sc->sc_noport)) { 2429 std->err = USB_ERR_IOERROR; 2430 goto done; 2431 } 2432 port = OHCI_RH_PORT_STATUS(index); 2433 switch (value) { 2434 case UHF_PORT_ENABLE: 2435 OWRITE4(sc, port, UPS_PORT_ENABLED); 2436 break; 2437 case UHF_PORT_SUSPEND: 2438 OWRITE4(sc, port, UPS_SUSPEND); 2439 break; 2440 case UHF_PORT_RESET: 2441 DPRINTFN(6, "reset port %d\n", index); 2442 OWRITE4(sc, port, UPS_RESET); 2443 for (v = 0;; v++) { 2444 if (v < 12) { 2445 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 2446 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 2447 2448 if ((OREAD4(sc, port) & UPS_RESET) == 0) { 2449 break; 2450 } 2451 } else { 2452 std->err = USB_ERR_TIMEOUT; 2453 goto done; 2454 } 2455 } 2456 DPRINTFN(9, "ohci port %d reset, status = 0x%04x\n", 2457 index, OREAD4(sc, port)); 2458 break; 2459 case UHF_PORT_POWER: 2460 DPRINTFN(3, "set port power %d\n", index); 2461 OWRITE4(sc, port, UPS_PORT_POWER); 2462 break; 2463 default: 2464 std->err = USB_ERR_IOERROR; 2465 goto done; 2466 } 2467 break; 2468 default: 2469 std->err = USB_ERR_IOERROR; 2470 goto done; 2471 } 2472 done: 2473 return; 2474 } 2475 2476 static void 2477 ohci_root_ctrl_poll(struct ohci_softc *sc) 2478 { 2479 usb2_sw_transfer(&sc->sc_root_ctrl, 2480 &ohci_root_ctrl_done); 2481 } 2482 2483 struct usb2_pipe_methods ohci_root_ctrl_methods = 2484 { 2485 .open = ohci_root_ctrl_open, 2486 .close = ohci_root_ctrl_close, 2487 .enter = ohci_root_ctrl_enter, 2488 .start = ohci_root_ctrl_start, 2489 .enter_is_cancelable = 1, 2490 .start_is_cancelable = 0, 2491 }; 2492 2493 /*------------------------------------------------------------------------* 2494 * ohci root interrupt support 2495 *------------------------------------------------------------------------*/ 2496 static void 2497 ohci_root_intr_open(struct usb2_xfer *xfer) 2498 { 2499 return; 2500 } 2501 2502 static void 2503 ohci_root_intr_close(struct usb2_xfer *xfer) 2504 { 2505 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2506 2507 if (sc->sc_root_intr.xfer == xfer) { 2508 sc->sc_root_intr.xfer = NULL; 2509 } 2510 ohci_device_done(xfer, USB_ERR_CANCELLED); 2511 } 2512 2513 static void 2514 ohci_root_intr_enter(struct usb2_xfer *xfer) 2515 { 2516 return; 2517 } 2518 2519 static void 2520 ohci_root_intr_start(struct usb2_xfer *xfer) 2521 { 2522 ohci_softc_t *sc = OHCI_BUS2SC(xfer->xroot->bus); 2523 2524 sc->sc_root_intr.xfer = xfer; 2525 } 2526 2527 struct usb2_pipe_methods ohci_root_intr_methods = 2528 { 2529 .open = ohci_root_intr_open, 2530 .close = ohci_root_intr_close, 2531 .enter = ohci_root_intr_enter, 2532 .start = ohci_root_intr_start, 2533 .enter_is_cancelable = 1, 2534 .start_is_cancelable = 1, 2535 }; 2536 2537 static void 2538 ohci_xfer_setup(struct usb2_setup_params *parm) 2539 { 2540 struct usb2_page_search page_info; 2541 struct usb2_page_cache *pc; 2542 ohci_softc_t *sc; 2543 struct usb2_xfer *xfer; 2544 void *last_obj; 2545 uint32_t ntd; 2546 uint32_t nitd; 2547 uint32_t nqh; 2548 uint32_t n; 2549 2550 sc = OHCI_BUS2SC(parm->udev->bus); 2551 xfer = parm->curr_xfer; 2552 2553 parm->hc_max_packet_size = 0x500; 2554 parm->hc_max_packet_count = 1; 2555 parm->hc_max_frame_size = OHCI_PAGE_SIZE; 2556 2557 /* 2558 * calculate ntd and nqh 2559 */ 2560 if (parm->methods == &ohci_device_ctrl_methods) { 2561 xfer->flags_int.bdma_enable = 1; 2562 2563 usb2_transfer_setup_sub(parm); 2564 2565 nitd = 0; 2566 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 2567 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2568 nqh = 1; 2569 2570 } else if (parm->methods == &ohci_device_bulk_methods) { 2571 xfer->flags_int.bdma_enable = 1; 2572 2573 usb2_transfer_setup_sub(parm); 2574 2575 nitd = 0; 2576 ntd = ((2 * xfer->nframes) 2577 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2578 nqh = 1; 2579 2580 } else if (parm->methods == &ohci_device_intr_methods) { 2581 xfer->flags_int.bdma_enable = 1; 2582 2583 usb2_transfer_setup_sub(parm); 2584 2585 nitd = 0; 2586 ntd = ((2 * xfer->nframes) 2587 + (xfer->max_data_length / xfer->max_hc_frame_size)); 2588 nqh = 1; 2589 2590 } else if (parm->methods == &ohci_device_isoc_methods) { 2591 xfer->flags_int.bdma_enable = 1; 2592 2593 usb2_transfer_setup_sub(parm); 2594 2595 nitd = ((xfer->max_data_length / OHCI_PAGE_SIZE) + 2596 ((xfer->nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET) + 2597 1 /* EXTRA */ ); 2598 ntd = 0; 2599 nqh = 1; 2600 2601 } else { 2602 2603 usb2_transfer_setup_sub(parm); 2604 2605 nitd = 0; 2606 ntd = 0; 2607 nqh = 0; 2608 } 2609 2610 alloc_dma_set: 2611 2612 if (parm->err) { 2613 return; 2614 } 2615 last_obj = NULL; 2616 2617 if (usb2_transfer_setup_sub_malloc( 2618 parm, &pc, sizeof(ohci_td_t), 2619 OHCI_TD_ALIGN, ntd)) { 2620 parm->err = USB_ERR_NOMEM; 2621 return; 2622 } 2623 if (parm->buf) { 2624 for (n = 0; n != ntd; n++) { 2625 ohci_td_t *td; 2626 2627 usb2_get_page(pc + n, 0, &page_info); 2628 2629 td = page_info.buffer; 2630 2631 /* init TD */ 2632 td->td_self = htole32(page_info.physaddr); 2633 td->obj_next = last_obj; 2634 td->page_cache = pc + n; 2635 2636 last_obj = td; 2637 2638 usb2_pc_cpu_flush(pc + n); 2639 } 2640 } 2641 if (usb2_transfer_setup_sub_malloc( 2642 parm, &pc, sizeof(ohci_itd_t), 2643 OHCI_ITD_ALIGN, nitd)) { 2644 parm->err = USB_ERR_NOMEM; 2645 return; 2646 } 2647 if (parm->buf) { 2648 for (n = 0; n != nitd; n++) { 2649 ohci_itd_t *itd; 2650 2651 usb2_get_page(pc + n, 0, &page_info); 2652 2653 itd = page_info.buffer; 2654 2655 /* init TD */ 2656 itd->itd_self = htole32(page_info.physaddr); 2657 itd->obj_next = last_obj; 2658 itd->page_cache = pc + n; 2659 2660 last_obj = itd; 2661 2662 usb2_pc_cpu_flush(pc + n); 2663 } 2664 } 2665 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 2666 2667 last_obj = NULL; 2668 2669 if (usb2_transfer_setup_sub_malloc( 2670 parm, &pc, sizeof(ohci_ed_t), 2671 OHCI_ED_ALIGN, nqh)) { 2672 parm->err = USB_ERR_NOMEM; 2673 return; 2674 } 2675 if (parm->buf) { 2676 for (n = 0; n != nqh; n++) { 2677 ohci_ed_t *ed; 2678 2679 usb2_get_page(pc + n, 0, &page_info); 2680 2681 ed = page_info.buffer; 2682 2683 /* init QH */ 2684 ed->ed_self = htole32(page_info.physaddr); 2685 ed->obj_next = last_obj; 2686 ed->page_cache = pc + n; 2687 2688 last_obj = ed; 2689 2690 usb2_pc_cpu_flush(pc + n); 2691 } 2692 } 2693 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 2694 2695 if (!xfer->flags_int.curr_dma_set) { 2696 xfer->flags_int.curr_dma_set = 1; 2697 goto alloc_dma_set; 2698 } 2699 } 2700 2701 static void 2702 ohci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2703 struct usb2_pipe *pipe) 2704 { 2705 ohci_softc_t *sc = OHCI_BUS2SC(udev->bus); 2706 2707 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2708 pipe, udev->address, 2709 edesc->bEndpointAddress, udev->flags.usb2_mode, 2710 sc->sc_addr); 2711 2712 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2713 /* not supported */ 2714 return; 2715 } 2716 if (udev->device_index == sc->sc_addr) { 2717 switch (edesc->bEndpointAddress) { 2718 case USB_CONTROL_ENDPOINT: 2719 pipe->methods = &ohci_root_ctrl_methods; 2720 break; 2721 case UE_DIR_IN | OHCI_INTR_ENDPT: 2722 pipe->methods = &ohci_root_intr_methods; 2723 break; 2724 default: 2725 /* do nothing */ 2726 break; 2727 } 2728 } else { 2729 switch (edesc->bmAttributes & UE_XFERTYPE) { 2730 case UE_CONTROL: 2731 pipe->methods = &ohci_device_ctrl_methods; 2732 break; 2733 case UE_INTERRUPT: 2734 pipe->methods = &ohci_device_intr_methods; 2735 break; 2736 case UE_ISOCHRONOUS: 2737 if (udev->speed == USB_SPEED_FULL) { 2738 pipe->methods = &ohci_device_isoc_methods; 2739 } 2740 break; 2741 case UE_BULK: 2742 if (udev->speed != USB_SPEED_LOW) { 2743 pipe->methods = &ohci_device_bulk_methods; 2744 } 2745 break; 2746 default: 2747 /* do nothing */ 2748 break; 2749 } 2750 } 2751 } 2752 2753 static void 2754 ohci_xfer_unsetup(struct usb2_xfer *xfer) 2755 { 2756 return; 2757 } 2758 2759 static void 2760 ohci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 2761 { 2762 /* 2763 * Wait until hardware has finished any possible use of the 2764 * transfer descriptor(s) and QH 2765 */ 2766 *pus = (1125); /* microseconds */ 2767 } 2768 2769 static void 2770 ohci_device_resume(struct usb2_device *udev) 2771 { 2772 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2773 struct usb2_xfer *xfer; 2774 struct usb2_pipe_methods *methods; 2775 ohci_ed_t *ed; 2776 2777 DPRINTF("\n"); 2778 2779 USB_BUS_LOCK(udev->bus); 2780 2781 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2782 2783 if (xfer->xroot->udev == udev) { 2784 2785 methods = xfer->pipe->methods; 2786 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2787 2788 if (methods == &ohci_device_bulk_methods) { 2789 OHCI_APPEND_QH(ed, sc->sc_bulk_p_last); 2790 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2791 } 2792 if (methods == &ohci_device_ctrl_methods) { 2793 OHCI_APPEND_QH(ed, sc->sc_ctrl_p_last); 2794 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2795 } 2796 if (methods == &ohci_device_intr_methods) { 2797 OHCI_APPEND_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2798 } 2799 } 2800 } 2801 2802 USB_BUS_UNLOCK(udev->bus); 2803 2804 return; 2805 } 2806 2807 static void 2808 ohci_device_suspend(struct usb2_device *udev) 2809 { 2810 struct ohci_softc *sc = OHCI_BUS2SC(udev->bus); 2811 struct usb2_xfer *xfer; 2812 struct usb2_pipe_methods *methods; 2813 ohci_ed_t *ed; 2814 2815 DPRINTF("\n"); 2816 2817 USB_BUS_LOCK(udev->bus); 2818 2819 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2820 2821 if (xfer->xroot->udev == udev) { 2822 2823 methods = xfer->pipe->methods; 2824 ed = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2825 2826 if (methods == &ohci_device_bulk_methods) { 2827 OHCI_REMOVE_QH(ed, sc->sc_bulk_p_last); 2828 } 2829 if (methods == &ohci_device_ctrl_methods) { 2830 OHCI_REMOVE_QH(ed, sc->sc_ctrl_p_last); 2831 } 2832 if (methods == &ohci_device_intr_methods) { 2833 OHCI_REMOVE_QH(ed, sc->sc_intr_p_last[xfer->qh_pos]); 2834 } 2835 } 2836 } 2837 2838 USB_BUS_UNLOCK(udev->bus); 2839 2840 return; 2841 } 2842 2843 static void 2844 ohci_set_hw_power(struct usb2_bus *bus) 2845 { 2846 struct ohci_softc *sc = OHCI_BUS2SC(bus); 2847 uint32_t temp; 2848 uint32_t flags; 2849 2850 DPRINTF("\n"); 2851 2852 USB_BUS_LOCK(bus); 2853 2854 flags = bus->hw_power_state; 2855 2856 temp = OREAD4(sc, OHCI_CONTROL); 2857 temp &= ~(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE); 2858 2859 if (flags & USB_HW_POWER_CONTROL) 2860 temp |= OHCI_CLE; 2861 2862 if (flags & USB_HW_POWER_BULK) 2863 temp |= OHCI_BLE; 2864 2865 if (flags & USB_HW_POWER_INTERRUPT) 2866 temp |= OHCI_PLE; 2867 2868 if (flags & USB_HW_POWER_ISOC) 2869 temp |= OHCI_IE | OHCI_PLE; 2870 2871 OWRITE4(sc, OHCI_CONTROL, temp); 2872 2873 USB_BUS_UNLOCK(bus); 2874 2875 return; 2876 } 2877 2878 struct usb2_bus_methods ohci_bus_methods = 2879 { 2880 .pipe_init = ohci_pipe_init, 2881 .xfer_setup = ohci_xfer_setup, 2882 .xfer_unsetup = ohci_xfer_unsetup, 2883 .get_dma_delay = ohci_get_dma_delay, 2884 .device_resume = ohci_device_resume, 2885 .device_suspend = ohci_device_suspend, 2886 .set_hw_power = ohci_set_hw_power, 2887 .roothub_exec = ohci_root_ctrl_task, 2888 }; 2889