1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * Copyright (c) 2018 Andrew Turner <andrew@FreeBSD.org> 4 * All rights reserved. 5 * 6 * This software was developed by SRI International and the University of 7 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 8 * ("CTSRD"), as part of the DARPA CRASH research programme. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * Allwinner USB Dual-Role Device (DRD) controller 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/rman.h> 43 #include <sys/kernel.h> 44 #include <sys/condvar.h> 45 #include <sys/module.h> 46 47 #include <machine/bus.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <dev/usb/usb.h> 53 #include <dev/usb/usbdi.h> 54 55 #include <dev/usb/usb_core.h> 56 #include <dev/usb/usb_busdma.h> 57 #include <dev/usb/usb_process.h> 58 #include <dev/usb/usb_util.h> 59 60 #include <dev/usb/usb_controller.h> 61 #include <dev/usb/usb_bus.h> 62 #include <dev/usb/controller/musb_otg.h> 63 64 #include <dev/extres/clk/clk.h> 65 #include <dev/extres/hwreset/hwreset.h> 66 #include <dev/extres/phy/phy.h> 67 #include <dev/extres/phy/phy_usb.h> 68 69 #ifdef __arm__ 70 #include <arm/allwinner/aw_machdep.h> 71 #include <arm/allwinner/a10_sramc.h> 72 #endif 73 74 #define DRD_EP_MAX 5 75 #define DRD_EP_MAX_H3 4 76 77 #define MUSB2_REG_AWIN_VEND0 0x0043 78 #define VEND0_PIO_MODE 0 79 80 #if defined(__arm__) 81 #define bs_parent_space(bs) ((bs)->bs_parent) 82 typedef bus_space_tag_t awusb_bs_tag; 83 #elif defined(__aarch64__) 84 #define bs_parent_space(bs) (bs) 85 typedef void * awusb_bs_tag; 86 #endif 87 88 #define AWUSB_OKAY 0x01 89 #define AWUSB_NO_CONFDATA 0x02 90 static struct ofw_compat_data compat_data[] = { 91 { "allwinner,sun4i-a10-musb", AWUSB_OKAY }, 92 { "allwinner,sun6i-a31-musb", AWUSB_OKAY }, 93 { "allwinner,sun8i-a33-musb", AWUSB_OKAY | AWUSB_NO_CONFDATA }, 94 { "allwinner,sun8i-h3-musb", AWUSB_OKAY | AWUSB_NO_CONFDATA }, 95 { NULL, 0 } 96 }; 97 98 static const struct musb_otg_ep_cfg musbotg_ep_allwinner[] = { 99 { 100 .ep_end = DRD_EP_MAX, 101 .ep_fifosz_shift = 9, 102 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_512, 103 }, 104 { 105 .ep_end = -1, 106 }, 107 }; 108 109 static const struct musb_otg_ep_cfg musbotg_ep_allwinner_h3[] = { 110 { 111 .ep_end = DRD_EP_MAX_H3, 112 .ep_fifosz_shift = 9, 113 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_512, 114 }, 115 { 116 .ep_end = -1, 117 }, 118 }; 119 120 struct awusbdrd_softc { 121 struct musbotg_softc sc; 122 struct resource *res[2]; 123 clk_t clk; 124 hwreset_t reset; 125 phy_t phy; 126 struct bus_space bs; 127 int flags; 128 }; 129 130 static struct resource_spec awusbdrd_spec[] = { 131 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 132 { SYS_RES_IRQ, 0, RF_ACTIVE }, 133 { -1, 0 } 134 }; 135 136 #define REMAPFLAG 0x8000 137 #define REGDECL(a, b) [(a)] = ((b) | REMAPFLAG) 138 139 /* Allwinner USB DRD register mappings */ 140 static const uint16_t awusbdrd_regmap[] = { 141 REGDECL(MUSB2_REG_EPFIFO(0), 0x0000), 142 REGDECL(MUSB2_REG_EPFIFO(1), 0x0004), 143 REGDECL(MUSB2_REG_EPFIFO(2), 0x0008), 144 REGDECL(MUSB2_REG_EPFIFO(3), 0x000c), 145 REGDECL(MUSB2_REG_EPFIFO(4), 0x0010), 146 REGDECL(MUSB2_REG_EPFIFO(5), 0x0014), 147 REGDECL(MUSB2_REG_POWER, 0x0040), 148 REGDECL(MUSB2_REG_DEVCTL, 0x0041), 149 REGDECL(MUSB2_REG_EPINDEX, 0x0042), 150 REGDECL(MUSB2_REG_INTTX, 0x0044), 151 REGDECL(MUSB2_REG_INTRX, 0x0046), 152 REGDECL(MUSB2_REG_INTTXE, 0x0048), 153 REGDECL(MUSB2_REG_INTRXE, 0x004a), 154 REGDECL(MUSB2_REG_INTUSB, 0x004c), 155 REGDECL(MUSB2_REG_INTUSBE, 0x0050), 156 REGDECL(MUSB2_REG_FRAME, 0x0054), 157 REGDECL(MUSB2_REG_TESTMODE, 0x007c), 158 REGDECL(MUSB2_REG_TXMAXP, 0x0080), 159 REGDECL(MUSB2_REG_TXCSRL, 0x0082), 160 REGDECL(MUSB2_REG_TXCSRH, 0x0083), 161 REGDECL(MUSB2_REG_RXMAXP, 0x0084), 162 REGDECL(MUSB2_REG_RXCSRL, 0x0086), 163 REGDECL(MUSB2_REG_RXCSRH, 0x0087), 164 REGDECL(MUSB2_REG_RXCOUNT, 0x0088), 165 REGDECL(MUSB2_REG_TXTI, 0x008c), 166 REGDECL(MUSB2_REG_TXNAKLIMIT, 0x008d), 167 REGDECL(MUSB2_REG_RXNAKLIMIT, 0x008f), 168 REGDECL(MUSB2_REG_RXTI, 0x008e), 169 REGDECL(MUSB2_REG_TXFIFOSZ, 0x0090), 170 REGDECL(MUSB2_REG_TXFIFOADD, 0x0092), 171 REGDECL(MUSB2_REG_RXFIFOSZ, 0x0094), 172 REGDECL(MUSB2_REG_RXFIFOADD, 0x0096), 173 REGDECL(MUSB2_REG_FADDR, 0x0098), 174 REGDECL(MUSB2_REG_TXFADDR(0), 0x0098), 175 REGDECL(MUSB2_REG_TXHADDR(0), 0x009a), 176 REGDECL(MUSB2_REG_TXHUBPORT(0), 0x009b), 177 REGDECL(MUSB2_REG_RXFADDR(0), 0x009c), 178 REGDECL(MUSB2_REG_RXHADDR(0), 0x009e), 179 REGDECL(MUSB2_REG_RXHUBPORT(0), 0x009f), 180 REGDECL(MUSB2_REG_TXFADDR(1), 0x0098), 181 REGDECL(MUSB2_REG_TXHADDR(1), 0x009a), 182 REGDECL(MUSB2_REG_TXHUBPORT(1), 0x009b), 183 REGDECL(MUSB2_REG_RXFADDR(1), 0x009c), 184 REGDECL(MUSB2_REG_RXHADDR(1), 0x009e), 185 REGDECL(MUSB2_REG_RXHUBPORT(1), 0x009f), 186 REGDECL(MUSB2_REG_TXFADDR(2), 0x0098), 187 REGDECL(MUSB2_REG_TXHADDR(2), 0x009a), 188 REGDECL(MUSB2_REG_TXHUBPORT(2), 0x009b), 189 REGDECL(MUSB2_REG_RXFADDR(2), 0x009c), 190 REGDECL(MUSB2_REG_RXHADDR(2), 0x009e), 191 REGDECL(MUSB2_REG_RXHUBPORT(2), 0x009f), 192 REGDECL(MUSB2_REG_TXFADDR(3), 0x0098), 193 REGDECL(MUSB2_REG_TXHADDR(3), 0x009a), 194 REGDECL(MUSB2_REG_TXHUBPORT(3), 0x009b), 195 REGDECL(MUSB2_REG_RXFADDR(3), 0x009c), 196 REGDECL(MUSB2_REG_RXHADDR(3), 0x009e), 197 REGDECL(MUSB2_REG_RXHUBPORT(3), 0x009f), 198 REGDECL(MUSB2_REG_TXFADDR(4), 0x0098), 199 REGDECL(MUSB2_REG_TXHADDR(4), 0x009a), 200 REGDECL(MUSB2_REG_TXHUBPORT(4), 0x009b), 201 REGDECL(MUSB2_REG_RXFADDR(4), 0x009c), 202 REGDECL(MUSB2_REG_RXHADDR(4), 0x009e), 203 REGDECL(MUSB2_REG_RXHUBPORT(4), 0x009f), 204 REGDECL(MUSB2_REG_TXFADDR(5), 0x0098), 205 REGDECL(MUSB2_REG_TXHADDR(5), 0x009a), 206 REGDECL(MUSB2_REG_TXHUBPORT(5), 0x009b), 207 REGDECL(MUSB2_REG_RXFADDR(5), 0x009c), 208 REGDECL(MUSB2_REG_RXHADDR(5), 0x009e), 209 REGDECL(MUSB2_REG_RXHUBPORT(5), 0x009f), 210 REGDECL(MUSB2_REG_CONFDATA, 0x00c0), 211 }; 212 213 static bus_size_t 214 awusbdrd_reg(bus_size_t o) 215 { 216 bus_size_t v; 217 218 KASSERT(o < nitems(awusbdrd_regmap), 219 ("%s: Invalid register %#lx", __func__, o)); 220 if (o >= nitems(awusbdrd_regmap)) 221 return (o); 222 223 v = awusbdrd_regmap[o]; 224 225 KASSERT((v & REMAPFLAG) != 0, ("%s: reg %#lx not in regmap", 226 __func__, o)); 227 228 return (v & ~REMAPFLAG); 229 } 230 231 static int 232 awusbdrd_filt(bus_size_t o) 233 { 234 switch (o) { 235 case MUSB2_REG_MISC: 236 case MUSB2_REG_RXDBDIS: 237 case MUSB2_REG_TXDBDIS: 238 return (1); 239 default: 240 return (0); 241 } 242 } 243 244 static uint8_t 245 awusbdrd_bs_r_1(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o) 246 { 247 struct bus_space *bs = t; 248 249 switch (o) { 250 case MUSB2_REG_HWVERS: 251 return (0); /* no known equivalent */ 252 } 253 254 return (bus_space_read_1(bs_parent_space(bs), h, awusbdrd_reg(o))); 255 } 256 257 static uint8_t 258 awusbdrd_bs_r_1_noconf(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o) 259 { 260 261 /* 262 * There is no confdata register on some SoCs, return the same 263 * magic value as Linux. 264 */ 265 if (o == MUSB2_REG_CONFDATA) 266 return (0xde); 267 268 return (awusbdrd_bs_r_1(t, h, o)); 269 } 270 271 272 static uint16_t 273 awusbdrd_bs_r_2(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o) 274 { 275 struct bus_space *bs = t; 276 277 if (awusbdrd_filt(o) != 0) 278 return (0); 279 return bus_space_read_2(bs_parent_space(bs), h, awusbdrd_reg(o)); 280 } 281 282 static void 283 awusbdrd_bs_w_1(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o, 284 uint8_t v) 285 { 286 struct bus_space *bs = t; 287 288 if (awusbdrd_filt(o) != 0) 289 return; 290 291 bus_space_write_1(bs_parent_space(bs), h, awusbdrd_reg(o), v); 292 } 293 294 static void 295 awusbdrd_bs_w_2(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o, 296 uint16_t v) 297 { 298 struct bus_space *bs = t; 299 300 if (awusbdrd_filt(o) != 0) 301 return; 302 303 bus_space_write_2(bs_parent_space(bs), h, awusbdrd_reg(o), v); 304 } 305 306 static void 307 awusbdrd_bs_rm_1(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o, 308 uint8_t *d, bus_size_t c) 309 { 310 struct bus_space *bs = t; 311 312 bus_space_read_multi_1(bs_parent_space(bs), h, awusbdrd_reg(o), d, c); 313 } 314 315 static void 316 awusbdrd_bs_rm_4(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o, 317 uint32_t *d, bus_size_t c) 318 { 319 struct bus_space *bs = t; 320 321 bus_space_read_multi_4(bs_parent_space(bs), h, awusbdrd_reg(o), d, c); 322 } 323 324 static void 325 awusbdrd_bs_wm_1(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o, 326 const uint8_t *d, bus_size_t c) 327 { 328 struct bus_space *bs = t; 329 330 if (awusbdrd_filt(o) != 0) 331 return; 332 333 bus_space_write_multi_1(bs_parent_space(bs), h, awusbdrd_reg(o), d, c); 334 } 335 336 static void 337 awusbdrd_bs_wm_4(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o, 338 const uint32_t *d, bus_size_t c) 339 { 340 struct bus_space *bs = t; 341 342 if (awusbdrd_filt(o) != 0) 343 return; 344 345 bus_space_write_multi_4(bs_parent_space(bs), h, awusbdrd_reg(o), d, c); 346 } 347 348 static void 349 awusbdrd_intr(void *arg) 350 { 351 struct awusbdrd_softc *sc = arg; 352 uint8_t intusb; 353 uint16_t inttx, intrx; 354 355 intusb = MUSB2_READ_1(&sc->sc, MUSB2_REG_INTUSB); 356 inttx = MUSB2_READ_2(&sc->sc, MUSB2_REG_INTTX); 357 intrx = MUSB2_READ_2(&sc->sc, MUSB2_REG_INTRX); 358 if (intusb == 0 && inttx == 0 && intrx == 0) 359 return; 360 361 if (intusb) 362 MUSB2_WRITE_1(&sc->sc, MUSB2_REG_INTUSB, intusb); 363 if (inttx) 364 MUSB2_WRITE_2(&sc->sc, MUSB2_REG_INTTX, inttx); 365 if (intrx) 366 MUSB2_WRITE_2(&sc->sc, MUSB2_REG_INTRX, intrx); 367 368 musbotg_interrupt(arg, intrx, inttx, intusb); 369 } 370 371 static int 372 awusbdrd_probe(device_t dev) 373 { 374 if (!ofw_bus_status_okay(dev)) 375 return (ENXIO); 376 377 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 378 return (ENXIO); 379 380 device_set_desc(dev, "Allwinner USB DRD"); 381 return (BUS_PROBE_DEFAULT); 382 } 383 384 static int 385 awusbdrd_attach(device_t dev) 386 { 387 char usb_mode[24]; 388 struct awusbdrd_softc *sc; 389 uint8_t musb_mode; 390 int phy_mode; 391 int error; 392 393 sc = device_get_softc(dev); 394 sc->flags = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 395 396 error = bus_alloc_resources(dev, awusbdrd_spec, sc->res); 397 if (error != 0) 398 return (error); 399 400 musb_mode = MUSB2_HOST_MODE; /* default */ 401 phy_mode = PHY_USB_MODE_HOST; 402 if (OF_getprop(ofw_bus_get_node(dev), "dr_mode", 403 &usb_mode, sizeof(usb_mode)) > 0) { 404 usb_mode[sizeof(usb_mode) - 1] = 0; 405 if (strcasecmp(usb_mode, "host") == 0) { 406 musb_mode = MUSB2_HOST_MODE; 407 phy_mode = PHY_USB_MODE_HOST; 408 } else if (strcasecmp(usb_mode, "peripheral") == 0) { 409 musb_mode = MUSB2_DEVICE_MODE; 410 phy_mode = PHY_USB_MODE_DEVICE; 411 } else if (strcasecmp(usb_mode, "otg") == 0) { 412 /* 413 * XXX phy has PHY_USB_MODE_OTG, but MUSB does not have 414 * it. It's not clear how to propagate mode changes 415 * from phy layer (that detects them) to MUSB. 416 */ 417 musb_mode = MUSB2_DEVICE_MODE; 418 phy_mode = PHY_USB_MODE_DEVICE; 419 } else { 420 device_printf(dev, "Invalid FDT dr_mode: %s\n", 421 usb_mode); 422 } 423 } 424 425 /* AHB gate clock is required */ 426 error = clk_get_by_ofw_index(dev, 0, 0, &sc->clk); 427 if (error != 0) 428 goto fail; 429 430 /* AHB reset is only present on some SoCs */ 431 (void)hwreset_get_by_ofw_idx(dev, 0, 0, &sc->reset); 432 433 /* Enable clocks */ 434 error = clk_enable(sc->clk); 435 if (error != 0) { 436 device_printf(dev, "failed to enable clock: %d\n", error); 437 goto fail; 438 } 439 if (sc->reset != NULL) { 440 error = hwreset_deassert(sc->reset); 441 if (error != 0) { 442 device_printf(dev, "failed to de-assert reset: %d\n", 443 error); 444 goto fail; 445 } 446 } 447 448 /* XXX not sure if this is universally needed. */ 449 (void)phy_get_by_ofw_name(dev, 0, "usb", &sc->phy); 450 if (sc->phy != NULL) { 451 device_printf(dev, "setting phy mode %d\n", phy_mode); 452 if (musb_mode == MUSB2_HOST_MODE) { 453 error = phy_enable(sc->phy); 454 if (error != 0) { 455 device_printf(dev, "Could not enable phy\n"); 456 goto fail; 457 } 458 } 459 error = phy_usb_set_mode(sc->phy, phy_mode); 460 if (error != 0) { 461 device_printf(dev, "Could not set phy mode\n"); 462 goto fail; 463 } 464 } 465 466 sc->sc.sc_bus.parent = dev; 467 sc->sc.sc_bus.devices = sc->sc.sc_devices; 468 sc->sc.sc_bus.devices_max = MUSB2_MAX_DEVICES; 469 sc->sc.sc_bus.dma_bits = 32; 470 471 error = usb_bus_mem_alloc_all(&sc->sc.sc_bus, USB_GET_DMA_TAG(dev), 472 NULL); 473 if (error != 0) { 474 error = ENOMEM; 475 goto fail; 476 } 477 478 #if defined(__arm__) 479 sc->bs.bs_parent = rman_get_bustag(sc->res[0]); 480 #elif defined(__aarch64__) 481 sc->bs.bs_cookie = rman_get_bustag(sc->res[0]); 482 #endif 483 484 if ((sc->flags & AWUSB_NO_CONFDATA) == AWUSB_NO_CONFDATA) 485 sc->bs.bs_r_1 = awusbdrd_bs_r_1_noconf; 486 else 487 sc->bs.bs_r_1 = awusbdrd_bs_r_1; 488 sc->bs.bs_r_2 = awusbdrd_bs_r_2; 489 sc->bs.bs_w_1 = awusbdrd_bs_w_1; 490 sc->bs.bs_w_2 = awusbdrd_bs_w_2; 491 sc->bs.bs_rm_1 = awusbdrd_bs_rm_1; 492 sc->bs.bs_rm_4 = awusbdrd_bs_rm_4; 493 sc->bs.bs_wm_1 = awusbdrd_bs_wm_1; 494 sc->bs.bs_wm_4 = awusbdrd_bs_wm_4; 495 496 sc->sc.sc_io_tag = &sc->bs; 497 sc->sc.sc_io_hdl = rman_get_bushandle(sc->res[0]); 498 sc->sc.sc_io_size = rman_get_size(sc->res[0]); 499 500 sc->sc.sc_bus.bdev = device_add_child(dev, "usbus", -1); 501 if (sc->sc.sc_bus.bdev == NULL) { 502 error = ENXIO; 503 goto fail; 504 } 505 device_set_ivars(sc->sc.sc_bus.bdev, &sc->sc.sc_bus); 506 sc->sc.sc_id = 0; 507 sc->sc.sc_platform_data = sc; 508 sc->sc.sc_mode = musb_mode; 509 if (ofw_bus_is_compatible(dev, "allwinner,sun8i-h3-musb")) { 510 sc->sc.sc_ep_cfg = musbotg_ep_allwinner_h3; 511 sc->sc.sc_ep_max = DRD_EP_MAX_H3; 512 } else { 513 sc->sc.sc_ep_cfg = musbotg_ep_allwinner; 514 sc->sc.sc_ep_max = DRD_EP_MAX; 515 } 516 517 error = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_BIO, 518 NULL, awusbdrd_intr, sc, &sc->sc.sc_intr_hdl); 519 if (error != 0) 520 goto fail; 521 522 /* Enable PIO mode */ 523 bus_write_1(sc->res[0], MUSB2_REG_AWIN_VEND0, VEND0_PIO_MODE); 524 525 #ifdef __arm__ 526 /* Map SRAMD area to USB0 (sun4i/sun7i only) */ 527 switch (allwinner_soc_family()) { 528 case ALLWINNERSOC_SUN4I: 529 case ALLWINNERSOC_SUN7I: 530 a10_map_to_otg(); 531 break; 532 } 533 #endif 534 535 error = musbotg_init(&sc->sc); 536 if (error != 0) 537 goto fail; 538 539 error = device_probe_and_attach(sc->sc.sc_bus.bdev); 540 if (error != 0) 541 goto fail; 542 543 musbotg_vbus_interrupt(&sc->sc, 1); /* XXX VBUS */ 544 545 return (0); 546 547 fail: 548 if (sc->phy != NULL) { 549 if (musb_mode == MUSB2_HOST_MODE) 550 (void)phy_disable(sc->phy); 551 phy_release(sc->phy); 552 } 553 if (sc->reset != NULL) { 554 hwreset_assert(sc->reset); 555 hwreset_release(sc->reset); 556 } 557 if (sc->clk != NULL) 558 clk_release(sc->clk); 559 bus_release_resources(dev, awusbdrd_spec, sc->res); 560 return (error); 561 } 562 563 static int 564 awusbdrd_detach(device_t dev) 565 { 566 struct awusbdrd_softc *sc; 567 device_t bdev; 568 int error; 569 570 sc = device_get_softc(dev); 571 572 if (sc->sc.sc_bus.bdev != NULL) { 573 bdev = sc->sc.sc_bus.bdev; 574 device_detach(bdev); 575 device_delete_child(dev, bdev); 576 } 577 578 musbotg_uninit(&sc->sc); 579 error = bus_teardown_intr(dev, sc->res[1], sc->sc.sc_intr_hdl); 580 if (error != 0) 581 return (error); 582 583 usb_bus_mem_free_all(&sc->sc.sc_bus, NULL); 584 585 if (sc->phy != NULL) { 586 if (sc->sc.sc_mode == MUSB2_HOST_MODE) 587 phy_disable(sc->phy); 588 phy_release(sc->phy); 589 } 590 if (sc->reset != NULL) { 591 if (hwreset_assert(sc->reset) != 0) 592 device_printf(dev, "failed to assert reset\n"); 593 hwreset_release(sc->reset); 594 } 595 if (sc->clk != NULL) 596 clk_release(sc->clk); 597 598 bus_release_resources(dev, awusbdrd_spec, sc->res); 599 600 device_delete_children(dev); 601 602 return (0); 603 } 604 605 static device_method_t awusbdrd_methods[] = { 606 /* Device interface */ 607 DEVMETHOD(device_probe, awusbdrd_probe), 608 DEVMETHOD(device_attach, awusbdrd_attach), 609 DEVMETHOD(device_detach, awusbdrd_detach), 610 DEVMETHOD(device_suspend, bus_generic_suspend), 611 DEVMETHOD(device_resume, bus_generic_resume), 612 DEVMETHOD(device_shutdown, bus_generic_shutdown), 613 614 DEVMETHOD_END 615 }; 616 617 static driver_t awusbdrd_driver = { 618 .name = "musbotg", 619 .methods = awusbdrd_methods, 620 .size = sizeof(struct awusbdrd_softc), 621 }; 622 623 DRIVER_MODULE(musbotg, simplebus, awusbdrd_driver, 0, 0); 624 MODULE_DEPEND(musbotg, usb, 1, 1, 1); 625