1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * Copyright (c) 2018 Andrew Turner <andrew@FreeBSD.org> 4 * All rights reserved. 5 * 6 * This software was developed by SRI International and the University of 7 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 8 * ("CTSRD"), as part of the DARPA CRASH research programme. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * Allwinner USB Dual-Role Device (DRD) controller 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/rman.h> 40 #include <sys/kernel.h> 41 #include <sys/condvar.h> 42 #include <sys/module.h> 43 44 #include <machine/bus.h> 45 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <dev/usb/usb.h> 50 #include <dev/usb/usbdi.h> 51 52 #include <dev/usb/usb_core.h> 53 #include <dev/usb/usb_busdma.h> 54 #include <dev/usb/usb_process.h> 55 #include <dev/usb/usb_util.h> 56 57 #include <dev/usb/usb_controller.h> 58 #include <dev/usb/usb_bus.h> 59 #include <dev/usb/controller/musb_otg.h> 60 61 #include <dev/clk/clk.h> 62 #include <dev/hwreset/hwreset.h> 63 #include <dev/phy/phy.h> 64 #include <dev/phy/phy_usb.h> 65 66 #ifdef __arm__ 67 #include <arm/allwinner/aw_machdep.h> 68 #include <arm/allwinner/a10_sramc.h> 69 #endif 70 71 #define DRD_EP_MAX 5 72 #define DRD_EP_MAX_H3 4 73 74 #define MUSB2_REG_AWIN_VEND0 0x0043 75 #define VEND0_PIO_MODE 0 76 77 #if defined(__arm__) 78 #define bs_parent_space(bs) ((bs)->bs_parent) 79 typedef bus_space_tag_t awusb_bs_tag; 80 #elif defined(__aarch64__) 81 #define bs_parent_space(bs) (bs) 82 typedef void * awusb_bs_tag; 83 #endif 84 85 #define AWUSB_OKAY 0x01 86 #define AWUSB_NO_CONFDATA 0x02 87 static struct ofw_compat_data compat_data[] = { 88 { "allwinner,sun4i-a10-musb", AWUSB_OKAY }, 89 { "allwinner,sun6i-a31-musb", AWUSB_OKAY }, 90 { "allwinner,sun8i-a33-musb", AWUSB_OKAY | AWUSB_NO_CONFDATA }, 91 { "allwinner,sun8i-h3-musb", AWUSB_OKAY | AWUSB_NO_CONFDATA }, 92 { NULL, 0 } 93 }; 94 95 static const struct musb_otg_ep_cfg musbotg_ep_allwinner[] = { 96 { 97 .ep_end = DRD_EP_MAX, 98 .ep_fifosz_shift = 9, 99 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_512, 100 }, 101 { 102 .ep_end = -1, 103 }, 104 }; 105 106 static const struct musb_otg_ep_cfg musbotg_ep_allwinner_h3[] = { 107 { 108 .ep_end = DRD_EP_MAX_H3, 109 .ep_fifosz_shift = 9, 110 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_512, 111 }, 112 { 113 .ep_end = -1, 114 }, 115 }; 116 117 struct awusbdrd_softc { 118 struct musbotg_softc sc; 119 struct resource *res[2]; 120 clk_t clk; 121 hwreset_t reset; 122 phy_t phy; 123 struct bus_space bs; 124 int flags; 125 }; 126 127 static struct resource_spec awusbdrd_spec[] = { 128 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 129 { SYS_RES_IRQ, 0, RF_ACTIVE }, 130 { -1, 0 } 131 }; 132 133 #define REMAPFLAG 0x8000 134 #define REGDECL(a, b) [(a)] = ((b) | REMAPFLAG) 135 136 /* Allwinner USB DRD register mappings */ 137 static const uint16_t awusbdrd_regmap[] = { 138 REGDECL(MUSB2_REG_EPFIFO(0), 0x0000), 139 REGDECL(MUSB2_REG_EPFIFO(1), 0x0004), 140 REGDECL(MUSB2_REG_EPFIFO(2), 0x0008), 141 REGDECL(MUSB2_REG_EPFIFO(3), 0x000c), 142 REGDECL(MUSB2_REG_EPFIFO(4), 0x0010), 143 REGDECL(MUSB2_REG_EPFIFO(5), 0x0014), 144 REGDECL(MUSB2_REG_POWER, 0x0040), 145 REGDECL(MUSB2_REG_DEVCTL, 0x0041), 146 REGDECL(MUSB2_REG_EPINDEX, 0x0042), 147 REGDECL(MUSB2_REG_INTTX, 0x0044), 148 REGDECL(MUSB2_REG_INTRX, 0x0046), 149 REGDECL(MUSB2_REG_INTTXE, 0x0048), 150 REGDECL(MUSB2_REG_INTRXE, 0x004a), 151 REGDECL(MUSB2_REG_INTUSB, 0x004c), 152 REGDECL(MUSB2_REG_INTUSBE, 0x0050), 153 REGDECL(MUSB2_REG_FRAME, 0x0054), 154 REGDECL(MUSB2_REG_TESTMODE, 0x007c), 155 REGDECL(MUSB2_REG_TXMAXP, 0x0080), 156 REGDECL(MUSB2_REG_TXCSRL, 0x0082), 157 REGDECL(MUSB2_REG_TXCSRH, 0x0083), 158 REGDECL(MUSB2_REG_RXMAXP, 0x0084), 159 REGDECL(MUSB2_REG_RXCSRL, 0x0086), 160 REGDECL(MUSB2_REG_RXCSRH, 0x0087), 161 REGDECL(MUSB2_REG_RXCOUNT, 0x0088), 162 REGDECL(MUSB2_REG_TXTI, 0x008c), 163 REGDECL(MUSB2_REG_TXNAKLIMIT, 0x008d), 164 REGDECL(MUSB2_REG_RXNAKLIMIT, 0x008f), 165 REGDECL(MUSB2_REG_RXTI, 0x008e), 166 REGDECL(MUSB2_REG_TXFIFOSZ, 0x0090), 167 REGDECL(MUSB2_REG_TXFIFOADD, 0x0092), 168 REGDECL(MUSB2_REG_RXFIFOSZ, 0x0094), 169 REGDECL(MUSB2_REG_RXFIFOADD, 0x0096), 170 REGDECL(MUSB2_REG_FADDR, 0x0098), 171 REGDECL(MUSB2_REG_TXFADDR(0), 0x0098), 172 REGDECL(MUSB2_REG_TXHADDR(0), 0x009a), 173 REGDECL(MUSB2_REG_TXHUBPORT(0), 0x009b), 174 REGDECL(MUSB2_REG_RXFADDR(0), 0x009c), 175 REGDECL(MUSB2_REG_RXHADDR(0), 0x009e), 176 REGDECL(MUSB2_REG_RXHUBPORT(0), 0x009f), 177 REGDECL(MUSB2_REG_TXFADDR(1), 0x0098), 178 REGDECL(MUSB2_REG_TXHADDR(1), 0x009a), 179 REGDECL(MUSB2_REG_TXHUBPORT(1), 0x009b), 180 REGDECL(MUSB2_REG_RXFADDR(1), 0x009c), 181 REGDECL(MUSB2_REG_RXHADDR(1), 0x009e), 182 REGDECL(MUSB2_REG_RXHUBPORT(1), 0x009f), 183 REGDECL(MUSB2_REG_TXFADDR(2), 0x0098), 184 REGDECL(MUSB2_REG_TXHADDR(2), 0x009a), 185 REGDECL(MUSB2_REG_TXHUBPORT(2), 0x009b), 186 REGDECL(MUSB2_REG_RXFADDR(2), 0x009c), 187 REGDECL(MUSB2_REG_RXHADDR(2), 0x009e), 188 REGDECL(MUSB2_REG_RXHUBPORT(2), 0x009f), 189 REGDECL(MUSB2_REG_TXFADDR(3), 0x0098), 190 REGDECL(MUSB2_REG_TXHADDR(3), 0x009a), 191 REGDECL(MUSB2_REG_TXHUBPORT(3), 0x009b), 192 REGDECL(MUSB2_REG_RXFADDR(3), 0x009c), 193 REGDECL(MUSB2_REG_RXHADDR(3), 0x009e), 194 REGDECL(MUSB2_REG_RXHUBPORT(3), 0x009f), 195 REGDECL(MUSB2_REG_TXFADDR(4), 0x0098), 196 REGDECL(MUSB2_REG_TXHADDR(4), 0x009a), 197 REGDECL(MUSB2_REG_TXHUBPORT(4), 0x009b), 198 REGDECL(MUSB2_REG_RXFADDR(4), 0x009c), 199 REGDECL(MUSB2_REG_RXHADDR(4), 0x009e), 200 REGDECL(MUSB2_REG_RXHUBPORT(4), 0x009f), 201 REGDECL(MUSB2_REG_TXFADDR(5), 0x0098), 202 REGDECL(MUSB2_REG_TXHADDR(5), 0x009a), 203 REGDECL(MUSB2_REG_TXHUBPORT(5), 0x009b), 204 REGDECL(MUSB2_REG_RXFADDR(5), 0x009c), 205 REGDECL(MUSB2_REG_RXHADDR(5), 0x009e), 206 REGDECL(MUSB2_REG_RXHUBPORT(5), 0x009f), 207 REGDECL(MUSB2_REG_CONFDATA, 0x00c0), 208 }; 209 210 static bus_size_t 211 awusbdrd_reg(bus_size_t o) 212 { 213 bus_size_t v; 214 215 KASSERT(o < nitems(awusbdrd_regmap), 216 ("%s: Invalid register %#lx", __func__, o)); 217 if (o >= nitems(awusbdrd_regmap)) 218 return (o); 219 220 v = awusbdrd_regmap[o]; 221 222 KASSERT((v & REMAPFLAG) != 0, ("%s: reg %#lx not in regmap", 223 __func__, o)); 224 225 return (v & ~REMAPFLAG); 226 } 227 228 static int 229 awusbdrd_filt(bus_size_t o) 230 { 231 switch (o) { 232 case MUSB2_REG_MISC: 233 case MUSB2_REG_RXDBDIS: 234 case MUSB2_REG_TXDBDIS: 235 return (1); 236 default: 237 return (0); 238 } 239 } 240 241 static uint8_t 242 awusbdrd_bs_r_1(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o) 243 { 244 struct bus_space *bs = t; 245 246 switch (o) { 247 case MUSB2_REG_HWVERS: 248 return (0); /* no known equivalent */ 249 } 250 251 return (bus_space_read_1(bs_parent_space(bs), h, awusbdrd_reg(o))); 252 } 253 254 static uint8_t 255 awusbdrd_bs_r_1_noconf(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o) 256 { 257 258 /* 259 * There is no confdata register on some SoCs, return the same 260 * magic value as Linux. 261 */ 262 if (o == MUSB2_REG_CONFDATA) 263 return (0xde); 264 265 return (awusbdrd_bs_r_1(t, h, o)); 266 } 267 268 269 static uint16_t 270 awusbdrd_bs_r_2(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o) 271 { 272 struct bus_space *bs = t; 273 274 if (awusbdrd_filt(o) != 0) 275 return (0); 276 return bus_space_read_2(bs_parent_space(bs), h, awusbdrd_reg(o)); 277 } 278 279 static void 280 awusbdrd_bs_w_1(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o, 281 uint8_t v) 282 { 283 struct bus_space *bs = t; 284 285 if (awusbdrd_filt(o) != 0) 286 return; 287 288 bus_space_write_1(bs_parent_space(bs), h, awusbdrd_reg(o), v); 289 } 290 291 static void 292 awusbdrd_bs_w_2(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o, 293 uint16_t v) 294 { 295 struct bus_space *bs = t; 296 297 if (awusbdrd_filt(o) != 0) 298 return; 299 300 bus_space_write_2(bs_parent_space(bs), h, awusbdrd_reg(o), v); 301 } 302 303 static void 304 awusbdrd_bs_rm_1(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o, 305 uint8_t *d, bus_size_t c) 306 { 307 struct bus_space *bs = t; 308 309 bus_space_read_multi_1(bs_parent_space(bs), h, awusbdrd_reg(o), d, c); 310 } 311 312 static void 313 awusbdrd_bs_rm_4(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o, 314 uint32_t *d, bus_size_t c) 315 { 316 struct bus_space *bs = t; 317 318 bus_space_read_multi_4(bs_parent_space(bs), h, awusbdrd_reg(o), d, c); 319 } 320 321 static void 322 awusbdrd_bs_wm_1(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o, 323 const uint8_t *d, bus_size_t c) 324 { 325 struct bus_space *bs = t; 326 327 if (awusbdrd_filt(o) != 0) 328 return; 329 330 bus_space_write_multi_1(bs_parent_space(bs), h, awusbdrd_reg(o), d, c); 331 } 332 333 static void 334 awusbdrd_bs_wm_4(awusb_bs_tag t, bus_space_handle_t h, bus_size_t o, 335 const uint32_t *d, bus_size_t c) 336 { 337 struct bus_space *bs = t; 338 339 if (awusbdrd_filt(o) != 0) 340 return; 341 342 bus_space_write_multi_4(bs_parent_space(bs), h, awusbdrd_reg(o), d, c); 343 } 344 345 static void 346 awusbdrd_intr(void *arg) 347 { 348 struct awusbdrd_softc *sc = arg; 349 uint8_t intusb; 350 uint16_t inttx, intrx; 351 352 intusb = MUSB2_READ_1(&sc->sc, MUSB2_REG_INTUSB); 353 inttx = MUSB2_READ_2(&sc->sc, MUSB2_REG_INTTX); 354 intrx = MUSB2_READ_2(&sc->sc, MUSB2_REG_INTRX); 355 if (intusb == 0 && inttx == 0 && intrx == 0) 356 return; 357 358 if (intusb) 359 MUSB2_WRITE_1(&sc->sc, MUSB2_REG_INTUSB, intusb); 360 if (inttx) 361 MUSB2_WRITE_2(&sc->sc, MUSB2_REG_INTTX, inttx); 362 if (intrx) 363 MUSB2_WRITE_2(&sc->sc, MUSB2_REG_INTRX, intrx); 364 365 musbotg_interrupt(arg, intrx, inttx, intusb); 366 } 367 368 static int 369 awusbdrd_probe(device_t dev) 370 { 371 if (!ofw_bus_status_okay(dev)) 372 return (ENXIO); 373 374 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 375 return (ENXIO); 376 377 device_set_desc(dev, "Allwinner USB DRD"); 378 return (BUS_PROBE_DEFAULT); 379 } 380 381 static int 382 awusbdrd_attach(device_t dev) 383 { 384 char usb_mode[24]; 385 struct awusbdrd_softc *sc; 386 uint8_t musb_mode; 387 int phy_mode; 388 int error; 389 390 sc = device_get_softc(dev); 391 sc->flags = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 392 393 error = bus_alloc_resources(dev, awusbdrd_spec, sc->res); 394 if (error != 0) 395 return (error); 396 397 musb_mode = MUSB2_HOST_MODE; /* default */ 398 phy_mode = PHY_USB_MODE_HOST; 399 if (OF_getprop(ofw_bus_get_node(dev), "dr_mode", 400 &usb_mode, sizeof(usb_mode)) > 0) { 401 usb_mode[sizeof(usb_mode) - 1] = 0; 402 if (strcasecmp(usb_mode, "host") == 0) { 403 musb_mode = MUSB2_HOST_MODE; 404 phy_mode = PHY_USB_MODE_HOST; 405 } else if (strcasecmp(usb_mode, "peripheral") == 0) { 406 musb_mode = MUSB2_DEVICE_MODE; 407 phy_mode = PHY_USB_MODE_DEVICE; 408 } else if (strcasecmp(usb_mode, "otg") == 0) { 409 /* 410 * XXX phy has PHY_USB_MODE_OTG, but MUSB does not have 411 * it. It's not clear how to propagate mode changes 412 * from phy layer (that detects them) to MUSB. 413 */ 414 musb_mode = MUSB2_DEVICE_MODE; 415 phy_mode = PHY_USB_MODE_DEVICE; 416 } else { 417 device_printf(dev, "Invalid FDT dr_mode: %s\n", 418 usb_mode); 419 } 420 } 421 422 /* AHB gate clock is required */ 423 error = clk_get_by_ofw_index(dev, 0, 0, &sc->clk); 424 if (error != 0) 425 goto fail; 426 427 /* AHB reset is only present on some SoCs */ 428 (void)hwreset_get_by_ofw_idx(dev, 0, 0, &sc->reset); 429 430 /* Enable clocks */ 431 error = clk_enable(sc->clk); 432 if (error != 0) { 433 device_printf(dev, "failed to enable clock: %d\n", error); 434 goto fail; 435 } 436 if (sc->reset != NULL) { 437 error = hwreset_deassert(sc->reset); 438 if (error != 0) { 439 device_printf(dev, "failed to de-assert reset: %d\n", 440 error); 441 goto fail; 442 } 443 } 444 445 /* XXX not sure if this is universally needed. */ 446 (void)phy_get_by_ofw_name(dev, 0, "usb", &sc->phy); 447 if (sc->phy != NULL) { 448 device_printf(dev, "setting phy mode %d\n", phy_mode); 449 if (musb_mode == MUSB2_HOST_MODE) { 450 error = phy_enable(sc->phy); 451 if (error != 0) { 452 device_printf(dev, "Could not enable phy\n"); 453 goto fail; 454 } 455 } 456 error = phy_usb_set_mode(sc->phy, phy_mode); 457 if (error != 0) { 458 device_printf(dev, "Could not set phy mode\n"); 459 goto fail; 460 } 461 } 462 463 sc->sc.sc_bus.parent = dev; 464 sc->sc.sc_bus.devices = sc->sc.sc_devices; 465 sc->sc.sc_bus.devices_max = MUSB2_MAX_DEVICES; 466 sc->sc.sc_bus.dma_bits = 32; 467 468 error = usb_bus_mem_alloc_all(&sc->sc.sc_bus, USB_GET_DMA_TAG(dev), 469 NULL); 470 if (error != 0) { 471 error = ENOMEM; 472 goto fail; 473 } 474 475 #if defined(__arm__) 476 sc->bs.bs_parent = rman_get_bustag(sc->res[0]); 477 #elif defined(__aarch64__) 478 sc->bs.bs_cookie = rman_get_bustag(sc->res[0]); 479 #endif 480 481 if ((sc->flags & AWUSB_NO_CONFDATA) == AWUSB_NO_CONFDATA) 482 sc->bs.bs_r_1 = awusbdrd_bs_r_1_noconf; 483 else 484 sc->bs.bs_r_1 = awusbdrd_bs_r_1; 485 sc->bs.bs_r_2 = awusbdrd_bs_r_2; 486 sc->bs.bs_w_1 = awusbdrd_bs_w_1; 487 sc->bs.bs_w_2 = awusbdrd_bs_w_2; 488 sc->bs.bs_rm_1 = awusbdrd_bs_rm_1; 489 sc->bs.bs_rm_4 = awusbdrd_bs_rm_4; 490 sc->bs.bs_wm_1 = awusbdrd_bs_wm_1; 491 sc->bs.bs_wm_4 = awusbdrd_bs_wm_4; 492 493 sc->sc.sc_io_tag = &sc->bs; 494 sc->sc.sc_io_hdl = rman_get_bushandle(sc->res[0]); 495 sc->sc.sc_io_size = rman_get_size(sc->res[0]); 496 497 sc->sc.sc_bus.bdev = device_add_child(dev, "usbus", -1); 498 if (sc->sc.sc_bus.bdev == NULL) { 499 error = ENXIO; 500 goto fail; 501 } 502 device_set_ivars(sc->sc.sc_bus.bdev, &sc->sc.sc_bus); 503 sc->sc.sc_id = 0; 504 sc->sc.sc_platform_data = sc; 505 sc->sc.sc_mode = musb_mode; 506 if (ofw_bus_is_compatible(dev, "allwinner,sun8i-h3-musb")) { 507 sc->sc.sc_ep_cfg = musbotg_ep_allwinner_h3; 508 sc->sc.sc_ep_max = DRD_EP_MAX_H3; 509 } else { 510 sc->sc.sc_ep_cfg = musbotg_ep_allwinner; 511 sc->sc.sc_ep_max = DRD_EP_MAX; 512 } 513 514 error = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_BIO, 515 NULL, awusbdrd_intr, sc, &sc->sc.sc_intr_hdl); 516 if (error != 0) 517 goto fail; 518 519 /* Enable PIO mode */ 520 bus_write_1(sc->res[0], MUSB2_REG_AWIN_VEND0, VEND0_PIO_MODE); 521 522 #ifdef __arm__ 523 /* Map SRAMD area to USB0 (sun4i/sun7i only) */ 524 switch (allwinner_soc_family()) { 525 case ALLWINNERSOC_SUN4I: 526 case ALLWINNERSOC_SUN7I: 527 a10_map_to_otg(); 528 break; 529 } 530 #endif 531 532 error = musbotg_init(&sc->sc); 533 if (error != 0) 534 goto fail; 535 536 error = device_probe_and_attach(sc->sc.sc_bus.bdev); 537 if (error != 0) 538 goto fail; 539 540 musbotg_vbus_interrupt(&sc->sc, 1); /* XXX VBUS */ 541 542 return (0); 543 544 fail: 545 if (sc->phy != NULL) { 546 if (musb_mode == MUSB2_HOST_MODE) 547 (void)phy_disable(sc->phy); 548 phy_release(sc->phy); 549 } 550 if (sc->reset != NULL) { 551 hwreset_assert(sc->reset); 552 hwreset_release(sc->reset); 553 } 554 if (sc->clk != NULL) 555 clk_release(sc->clk); 556 bus_release_resources(dev, awusbdrd_spec, sc->res); 557 return (error); 558 } 559 560 static int 561 awusbdrd_detach(device_t dev) 562 { 563 struct awusbdrd_softc *sc; 564 device_t bdev; 565 int error; 566 567 sc = device_get_softc(dev); 568 569 if (sc->sc.sc_bus.bdev != NULL) { 570 bdev = sc->sc.sc_bus.bdev; 571 device_detach(bdev); 572 device_delete_child(dev, bdev); 573 } 574 575 musbotg_uninit(&sc->sc); 576 error = bus_teardown_intr(dev, sc->res[1], sc->sc.sc_intr_hdl); 577 if (error != 0) 578 return (error); 579 580 usb_bus_mem_free_all(&sc->sc.sc_bus, NULL); 581 582 if (sc->phy != NULL) { 583 if (sc->sc.sc_mode == MUSB2_HOST_MODE) 584 phy_disable(sc->phy); 585 phy_release(sc->phy); 586 } 587 if (sc->reset != NULL) { 588 if (hwreset_assert(sc->reset) != 0) 589 device_printf(dev, "failed to assert reset\n"); 590 hwreset_release(sc->reset); 591 } 592 if (sc->clk != NULL) 593 clk_release(sc->clk); 594 595 bus_release_resources(dev, awusbdrd_spec, sc->res); 596 597 device_delete_children(dev); 598 599 return (0); 600 } 601 602 static device_method_t awusbdrd_methods[] = { 603 /* Device interface */ 604 DEVMETHOD(device_probe, awusbdrd_probe), 605 DEVMETHOD(device_attach, awusbdrd_attach), 606 DEVMETHOD(device_detach, awusbdrd_detach), 607 DEVMETHOD(device_suspend, bus_generic_suspend), 608 DEVMETHOD(device_resume, bus_generic_resume), 609 DEVMETHOD(device_shutdown, bus_generic_shutdown), 610 611 DEVMETHOD_END 612 }; 613 614 static driver_t awusbdrd_driver = { 615 .name = "musbotg", 616 .methods = awusbdrd_methods, 617 .size = sizeof(struct awusbdrd_softc), 618 }; 619 620 DRIVER_MODULE(musbotg, simplebus, awusbdrd_driver, 0, 0); 621 MODULE_DEPEND(musbotg, usb, 1, 1, 1); 622