1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip 29 * at their homepage. 30 */ 31 32 /* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39 #ifdef USB_GLOBAL_INCLUDE_FILE 40 #include USB_GLOBAL_INCLUDE_FILE 41 #else 42 #include <sys/stdint.h> 43 #include <sys/stddef.h> 44 #include <sys/param.h> 45 #include <sys/queue.h> 46 #include <sys/types.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/module.h> 51 #include <sys/lock.h> 52 #include <sys/mutex.h> 53 #include <sys/condvar.h> 54 #include <sys/sysctl.h> 55 #include <sys/sx.h> 56 #include <sys/unistd.h> 57 #include <sys/callout.h> 58 #include <sys/malloc.h> 59 #include <sys/priv.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 64 #define USB_DEBUG_VAR musbotgdebug 65 66 #include <dev/usb/usb_core.h> 67 #include <dev/usb/usb_debug.h> 68 #include <dev/usb/usb_busdma.h> 69 #include <dev/usb/usb_process.h> 70 #include <dev/usb/usb_transfer.h> 71 #include <dev/usb/usb_device.h> 72 #include <dev/usb/usb_hub.h> 73 #include <dev/usb/usb_util.h> 74 75 #include <dev/usb/usb_controller.h> 76 #include <dev/usb/usb_bus.h> 77 #endif /* USB_GLOBAL_INCLUDE_FILE */ 78 79 #include <dev/usb/controller/musb_otg.h> 80 81 #define MUSBOTG_INTR_ENDPT 1 82 83 #define MUSBOTG_BUS2SC(bus) \ 84 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 85 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 86 87 #define MUSBOTG_PC2SC(pc) \ 88 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 89 90 #ifdef USB_DEBUG 91 static int musbotgdebug = 0; 92 93 static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 94 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RW, 95 &musbotgdebug, 0, "Debug level"); 96 #endif 97 98 #define MAX_NAK_TO 16 99 100 /* prototypes */ 101 102 static const struct usb_bus_methods musbotg_bus_methods; 103 static const struct usb_pipe_methods musbotg_device_bulk_methods; 104 static const struct usb_pipe_methods musbotg_device_ctrl_methods; 105 static const struct usb_pipe_methods musbotg_device_intr_methods; 106 static const struct usb_pipe_methods musbotg_device_isoc_methods; 107 108 /* Control transfers: Device mode */ 109 static musbotg_cmd_t musbotg_dev_ctrl_setup_rx; 110 static musbotg_cmd_t musbotg_dev_ctrl_data_rx; 111 static musbotg_cmd_t musbotg_dev_ctrl_data_tx; 112 static musbotg_cmd_t musbotg_dev_ctrl_status; 113 114 /* Control transfers: Host mode */ 115 static musbotg_cmd_t musbotg_host_ctrl_setup_tx; 116 static musbotg_cmd_t musbotg_host_ctrl_data_rx; 117 static musbotg_cmd_t musbotg_host_ctrl_data_tx; 118 static musbotg_cmd_t musbotg_host_ctrl_status_rx; 119 static musbotg_cmd_t musbotg_host_ctrl_status_tx; 120 121 /* Bulk, Interrupt, Isochronous: Device mode */ 122 static musbotg_cmd_t musbotg_dev_data_rx; 123 static musbotg_cmd_t musbotg_dev_data_tx; 124 125 /* Bulk, Interrupt, Isochronous: Host mode */ 126 static musbotg_cmd_t musbotg_host_data_rx; 127 static musbotg_cmd_t musbotg_host_data_tx; 128 129 static void musbotg_device_done(struct usb_xfer *, usb_error_t); 130 static void musbotg_do_poll(struct usb_bus *); 131 static void musbotg_standard_done(struct usb_xfer *); 132 static void musbotg_interrupt_poll(struct musbotg_softc *); 133 static void musbotg_root_intr(struct musbotg_softc *); 134 static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td, uint8_t); 135 static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td); 136 static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on); 137 138 /* 139 * Here is a configuration that the chip supports. 140 */ 141 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = { 142 143 [0] = { 144 .max_in_frame_size = 64,/* fixed */ 145 .max_out_frame_size = 64, /* fixed */ 146 .is_simplex = 1, 147 .support_control = 1, 148 } 149 }; 150 151 static int 152 musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td, uint8_t is_tx) 153 { 154 int ch; 155 int ep; 156 157 ep = td->ep_no; 158 159 /* In device mode each EP got its own channel */ 160 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 161 musbotg_ep_int_set(sc, ep, 1); 162 return (ep); 163 } 164 165 /* 166 * All control transactions go through EP0 167 */ 168 if (ep == 0) { 169 if (sc->sc_channel_mask & (1 << 0)) 170 return (-1); 171 sc->sc_channel_mask |= (1 << 0); 172 musbotg_ep_int_set(sc, ep, 1); 173 return (0); 174 } 175 176 for (ch = sc->sc_ep_max; ch != 0; ch--) { 177 if (sc->sc_channel_mask & (1 << ch)) 178 continue; 179 180 /* check FIFO size requirement */ 181 if (is_tx) { 182 if (td->max_frame_size > 183 sc->sc_hw_ep_profile[ch].max_in_frame_size) 184 continue; 185 } else { 186 if (td->max_frame_size > 187 sc->sc_hw_ep_profile[ch].max_out_frame_size) 188 continue; 189 } 190 sc->sc_channel_mask |= (1 << ch); 191 musbotg_ep_int_set(sc, ch, 1); 192 return (ch); 193 } 194 195 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask); 196 197 return (-1); 198 } 199 200 static void 201 musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td) 202 { 203 204 DPRINTFN(1, "ep_no=%d\n", td->channel); 205 206 if (sc->sc_mode == MUSB2_DEVICE_MODE) 207 return; 208 209 if (td == NULL) 210 return; 211 if (td->channel == -1) 212 return; 213 214 musbotg_ep_int_set(sc, td->channel, 0); 215 sc->sc_channel_mask &= ~(1 << td->channel); 216 217 td->channel = -1; 218 } 219 220 static void 221 musbotg_get_hw_ep_profile(struct usb_device *udev, 222 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 223 { 224 struct musbotg_softc *sc; 225 226 sc = MUSBOTG_BUS2SC(udev->bus); 227 228 if (ep_addr == 0) { 229 /* control endpoint */ 230 *ppf = musbotg_ep_profile; 231 } else if (ep_addr <= sc->sc_ep_max) { 232 /* other endpoints */ 233 *ppf = sc->sc_hw_ep_profile + ep_addr; 234 } else { 235 *ppf = NULL; 236 } 237 } 238 239 static void 240 musbotg_clocks_on(struct musbotg_softc *sc) 241 { 242 if (sc->sc_flags.clocks_off && 243 sc->sc_flags.port_powered) { 244 245 DPRINTFN(4, "\n"); 246 247 if (sc->sc_clocks_on) { 248 (sc->sc_clocks_on) (sc->sc_clocks_arg); 249 } 250 sc->sc_flags.clocks_off = 0; 251 252 /* XXX enable Transceiver */ 253 } 254 } 255 256 static void 257 musbotg_clocks_off(struct musbotg_softc *sc) 258 { 259 if (!sc->sc_flags.clocks_off) { 260 261 DPRINTFN(4, "\n"); 262 263 /* XXX disable Transceiver */ 264 265 if (sc->sc_clocks_off) { 266 (sc->sc_clocks_off) (sc->sc_clocks_arg); 267 } 268 sc->sc_flags.clocks_off = 1; 269 } 270 } 271 272 static void 273 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 274 { 275 uint8_t temp; 276 277 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 278 if (on) 279 temp |= MUSB2_MASK_SOFTC; 280 else 281 temp &= ~MUSB2_MASK_SOFTC; 282 283 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 284 } 285 286 static void 287 musbotg_pull_up(struct musbotg_softc *sc) 288 { 289 /* pullup D+, if possible */ 290 291 if (!sc->sc_flags.d_pulled_up && 292 sc->sc_flags.port_powered) { 293 sc->sc_flags.d_pulled_up = 1; 294 musbotg_pull_common(sc, 1); 295 } 296 } 297 298 static void 299 musbotg_pull_down(struct musbotg_softc *sc) 300 { 301 /* pulldown D+, if possible */ 302 303 if (sc->sc_flags.d_pulled_up) { 304 sc->sc_flags.d_pulled_up = 0; 305 musbotg_pull_common(sc, 0); 306 } 307 } 308 309 static void 310 musbotg_suspend_host(struct musbotg_softc *sc) 311 { 312 uint8_t temp; 313 314 if (sc->sc_flags.status_suspend) { 315 return; 316 } 317 318 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 319 temp |= MUSB2_MASK_SUSPMODE; 320 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 321 sc->sc_flags.status_suspend = 1; 322 } 323 324 static void 325 musbotg_wakeup_host(struct musbotg_softc *sc) 326 { 327 uint8_t temp; 328 329 if (!(sc->sc_flags.status_suspend)) { 330 return; 331 } 332 333 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 334 temp &= ~MUSB2_MASK_SUSPMODE; 335 temp |= MUSB2_MASK_RESUME; 336 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 337 338 /* wait 20 milliseconds */ 339 /* Wait for reset to complete. */ 340 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 341 342 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 343 temp &= ~MUSB2_MASK_RESUME; 344 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 345 346 sc->sc_flags.status_suspend = 0; 347 } 348 349 static void 350 musbotg_wakeup_peer(struct musbotg_softc *sc) 351 { 352 uint8_t temp; 353 354 if (!(sc->sc_flags.status_suspend)) { 355 return; 356 } 357 358 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 359 temp |= MUSB2_MASK_RESUME; 360 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 361 362 /* wait 8 milliseconds */ 363 /* Wait for reset to complete. */ 364 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 365 366 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 367 temp &= ~MUSB2_MASK_RESUME; 368 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 369 } 370 371 static void 372 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 373 { 374 DPRINTFN(4, "addr=%d\n", addr); 375 addr &= 0x7F; 376 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 377 } 378 379 static uint8_t 380 musbotg_dev_ctrl_setup_rx(struct musbotg_td *td) 381 { 382 struct musbotg_softc *sc; 383 struct usb_device_request req; 384 uint16_t count; 385 uint8_t csr; 386 387 /* get pointer to softc */ 388 sc = MUSBOTG_PC2SC(td->pc); 389 390 if (td->channel == -1) 391 td->channel = musbotg_channel_alloc(sc, td, 0); 392 393 /* EP0 is busy, wait */ 394 if (td->channel == -1) 395 return (1); 396 397 DPRINTFN(1, "ep_no=%d\n", td->channel); 398 399 /* select endpoint 0 */ 400 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 401 402 /* read out FIFO status */ 403 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 404 405 DPRINTFN(4, "csr=0x%02x\n", csr); 406 407 /* 408 * NOTE: If DATAEND is set we should not call the 409 * callback, hence the status stage is not complete. 410 */ 411 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 412 /* do not stall at this point */ 413 td->did_stall = 1; 414 /* wait for interrupt */ 415 DPRINTFN(0, "CSR0 DATAEND\n"); 416 goto not_complete; 417 } 418 419 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 420 /* clear SENTSTALL */ 421 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 422 /* get latest status */ 423 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 424 /* update EP0 state */ 425 sc->sc_ep0_busy = 0; 426 } 427 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 428 /* clear SETUPEND */ 429 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 430 MUSB2_MASK_CSR0L_SETUPEND_CLR); 431 /* get latest status */ 432 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 433 /* update EP0 state */ 434 sc->sc_ep0_busy = 0; 435 } 436 if (sc->sc_ep0_busy) { 437 DPRINTFN(0, "EP0 BUSY\n"); 438 goto not_complete; 439 } 440 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 441 goto not_complete; 442 } 443 /* clear did stall flag */ 444 td->did_stall = 0; 445 /* get the packet byte count */ 446 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 447 448 /* verify data length */ 449 if (count != td->remainder) { 450 DPRINTFN(0, "Invalid SETUP packet " 451 "length, %d bytes\n", count); 452 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 453 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 454 goto not_complete; 455 } 456 if (count != sizeof(req)) { 457 DPRINTFN(0, "Unsupported SETUP packet " 458 "length, %d bytes\n", count); 459 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 460 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 461 goto not_complete; 462 } 463 /* receive data */ 464 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 465 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 466 467 /* copy data into real buffer */ 468 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 469 470 td->offset = sizeof(req); 471 td->remainder = 0; 472 473 /* set pending command */ 474 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 475 476 /* we need set stall or dataend after this */ 477 sc->sc_ep0_busy = 1; 478 479 /* sneak peek the set address */ 480 if ((req.bmRequestType == UT_WRITE_DEVICE) && 481 (req.bRequest == UR_SET_ADDRESS)) { 482 sc->sc_dv_addr = req.wValue[0] & 0x7F; 483 } else { 484 sc->sc_dv_addr = 0xFF; 485 } 486 487 musbotg_channel_free(sc, td); 488 return (0); /* complete */ 489 490 not_complete: 491 /* abort any ongoing transfer */ 492 if (!td->did_stall) { 493 DPRINTFN(4, "stalling\n"); 494 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 495 MUSB2_MASK_CSR0L_SENDSTALL); 496 td->did_stall = 1; 497 } 498 return (1); /* not complete */ 499 } 500 501 static uint8_t 502 musbotg_host_ctrl_setup_tx(struct musbotg_td *td) 503 { 504 struct musbotg_softc *sc; 505 struct usb_device_request req; 506 uint8_t csr, csrh; 507 508 /* get pointer to softc */ 509 sc = MUSBOTG_PC2SC(td->pc); 510 511 if (td->channel == -1) 512 td->channel = musbotg_channel_alloc(sc, td, 1); 513 514 /* EP0 is busy, wait */ 515 if (td->channel == -1) 516 return (1); 517 518 DPRINTFN(1, "ep_no=%d\n", td->channel); 519 520 /* select endpoint 0 */ 521 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 522 523 /* read out FIFO status */ 524 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 525 DPRINTFN(4, "csr=0x%02x\n", csr); 526 527 /* Not ready yet yet */ 528 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 529 return (1); 530 531 /* Failed */ 532 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 533 MUSB2_MASK_CSR0L_ERROR)) 534 { 535 /* Clear status bit */ 536 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 537 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 538 td->error = 1; 539 } 540 541 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 542 DPRINTFN(1, "NAK timeout\n"); 543 544 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 545 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 546 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 547 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 548 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 549 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 550 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 551 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 552 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 553 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 554 } 555 } 556 557 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 558 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 559 560 td->error = 1; 561 } 562 563 if (td->error) { 564 musbotg_channel_free(sc, td); 565 return (0); 566 } 567 568 /* Fifo is not empty and there is no NAK timeout */ 569 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 570 return (1); 571 572 /* check if we are complete */ 573 if (td->remainder == 0) { 574 /* we are complete */ 575 musbotg_channel_free(sc, td); 576 return (0); 577 } 578 579 /* copy data into real buffer */ 580 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 581 582 /* send data */ 583 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 584 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 585 586 /* update offset and remainder */ 587 td->offset += sizeof(req); 588 td->remainder -= sizeof(req); 589 590 591 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 592 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 593 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 594 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 595 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 596 597 /* write command */ 598 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 599 MUSB2_MASK_CSR0L_TXPKTRDY | 600 MUSB2_MASK_CSR0L_SETUPPKT); 601 602 /* Just to be consistent, not used above */ 603 td->transaction_started = 1; 604 605 return (1); /* in progress */ 606 } 607 608 /* Control endpoint only data handling functions (RX/TX/SYNC) */ 609 610 static uint8_t 611 musbotg_dev_ctrl_data_rx(struct musbotg_td *td) 612 { 613 struct usb_page_search buf_res; 614 struct musbotg_softc *sc; 615 uint16_t count; 616 uint8_t csr; 617 uint8_t got_short; 618 619 /* get pointer to softc */ 620 sc = MUSBOTG_PC2SC(td->pc); 621 622 /* select endpoint 0 */ 623 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 624 625 /* check if a command is pending */ 626 if (sc->sc_ep0_cmd) { 627 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 628 sc->sc_ep0_cmd = 0; 629 } 630 /* read out FIFO status */ 631 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 632 633 DPRINTFN(4, "csr=0x%02x\n", csr); 634 635 got_short = 0; 636 637 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 638 MUSB2_MASK_CSR0L_SENTSTALL)) { 639 if (td->remainder == 0) { 640 /* 641 * We are actually complete and have 642 * received the next SETUP 643 */ 644 DPRINTFN(4, "faking complete\n"); 645 return (0); /* complete */ 646 } 647 /* 648 * USB Host Aborted the transfer. 649 */ 650 td->error = 1; 651 return (0); /* complete */ 652 } 653 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 654 return (1); /* not complete */ 655 } 656 /* get the packet byte count */ 657 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 658 659 /* verify the packet byte count */ 660 if (count != td->max_frame_size) { 661 if (count < td->max_frame_size) { 662 /* we have a short packet */ 663 td->short_pkt = 1; 664 got_short = 1; 665 } else { 666 /* invalid USB packet */ 667 td->error = 1; 668 return (0); /* we are complete */ 669 } 670 } 671 /* verify the packet byte count */ 672 if (count > td->remainder) { 673 /* invalid USB packet */ 674 td->error = 1; 675 return (0); /* we are complete */ 676 } 677 while (count > 0) { 678 uint32_t temp; 679 680 usbd_get_page(td->pc, td->offset, &buf_res); 681 682 /* get correct length */ 683 if (buf_res.length > count) { 684 buf_res.length = count; 685 } 686 /* check for unaligned memory address */ 687 if (USB_P2U(buf_res.buffer) & 3) { 688 689 temp = count & ~3; 690 691 if (temp) { 692 /* receive data 4 bytes at a time */ 693 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 694 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 695 temp / 4); 696 } 697 temp = count & 3; 698 if (temp) { 699 /* receive data 1 byte at a time */ 700 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 701 MUSB2_REG_EPFIFO(0), 702 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 703 } 704 usbd_copy_in(td->pc, td->offset, 705 sc->sc_bounce_buf, count); 706 707 /* update offset and remainder */ 708 td->offset += count; 709 td->remainder -= count; 710 break; 711 } 712 /* check if we can optimise */ 713 if (buf_res.length >= 4) { 714 715 /* receive data 4 bytes at a time */ 716 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 717 MUSB2_REG_EPFIFO(0), buf_res.buffer, 718 buf_res.length / 4); 719 720 temp = buf_res.length & ~3; 721 722 /* update counters */ 723 count -= temp; 724 td->offset += temp; 725 td->remainder -= temp; 726 continue; 727 } 728 /* receive data */ 729 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 730 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 731 732 /* update counters */ 733 count -= buf_res.length; 734 td->offset += buf_res.length; 735 td->remainder -= buf_res.length; 736 } 737 738 /* check if we are complete */ 739 if ((td->remainder == 0) || got_short) { 740 if (td->short_pkt) { 741 /* we are complete */ 742 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 743 return (0); 744 } 745 /* else need to receive a zero length packet */ 746 } 747 /* write command - need more data */ 748 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 749 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 750 return (1); /* not complete */ 751 } 752 753 static uint8_t 754 musbotg_dev_ctrl_data_tx(struct musbotg_td *td) 755 { 756 struct usb_page_search buf_res; 757 struct musbotg_softc *sc; 758 uint16_t count; 759 uint8_t csr; 760 761 /* get pointer to softc */ 762 sc = MUSBOTG_PC2SC(td->pc); 763 764 /* select endpoint 0 */ 765 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 766 767 /* check if a command is pending */ 768 if (sc->sc_ep0_cmd) { 769 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 770 sc->sc_ep0_cmd = 0; 771 } 772 /* read out FIFO status */ 773 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 774 775 DPRINTFN(4, "csr=0x%02x\n", csr); 776 777 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 778 MUSB2_MASK_CSR0L_SENTSTALL)) { 779 /* 780 * The current transfer was aborted 781 * by the USB Host 782 */ 783 td->error = 1; 784 return (0); /* complete */ 785 } 786 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 787 return (1); /* not complete */ 788 } 789 count = td->max_frame_size; 790 if (td->remainder < count) { 791 /* we have a short packet */ 792 td->short_pkt = 1; 793 count = td->remainder; 794 } 795 while (count > 0) { 796 uint32_t temp; 797 798 usbd_get_page(td->pc, td->offset, &buf_res); 799 800 /* get correct length */ 801 if (buf_res.length > count) { 802 buf_res.length = count; 803 } 804 /* check for unaligned memory address */ 805 if (USB_P2U(buf_res.buffer) & 3) { 806 807 usbd_copy_out(td->pc, td->offset, 808 sc->sc_bounce_buf, count); 809 810 temp = count & ~3; 811 812 if (temp) { 813 /* transmit data 4 bytes at a time */ 814 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 815 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 816 temp / 4); 817 } 818 temp = count & 3; 819 if (temp) { 820 /* receive data 1 byte at a time */ 821 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 822 MUSB2_REG_EPFIFO(0), 823 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 824 } 825 /* update offset and remainder */ 826 td->offset += count; 827 td->remainder -= count; 828 break; 829 } 830 /* check if we can optimise */ 831 if (buf_res.length >= 4) { 832 833 /* transmit data 4 bytes at a time */ 834 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 835 MUSB2_REG_EPFIFO(0), buf_res.buffer, 836 buf_res.length / 4); 837 838 temp = buf_res.length & ~3; 839 840 /* update counters */ 841 count -= temp; 842 td->offset += temp; 843 td->remainder -= temp; 844 continue; 845 } 846 /* transmit data */ 847 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 848 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 849 850 /* update counters */ 851 count -= buf_res.length; 852 td->offset += buf_res.length; 853 td->remainder -= buf_res.length; 854 } 855 856 /* check remainder */ 857 if (td->remainder == 0) { 858 if (td->short_pkt) { 859 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 860 return (0); /* complete */ 861 } 862 /* else we need to transmit a short packet */ 863 } 864 /* write command */ 865 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 866 MUSB2_MASK_CSR0L_TXPKTRDY); 867 868 return (1); /* not complete */ 869 } 870 871 static uint8_t 872 musbotg_host_ctrl_data_rx(struct musbotg_td *td) 873 { 874 struct usb_page_search buf_res; 875 struct musbotg_softc *sc; 876 uint16_t count; 877 uint8_t csr; 878 uint8_t got_short; 879 880 /* get pointer to softc */ 881 sc = MUSBOTG_PC2SC(td->pc); 882 883 if (td->channel == -1) 884 td->channel = musbotg_channel_alloc(sc, td, 0); 885 886 /* EP0 is busy, wait */ 887 if (td->channel == -1) 888 return (1); 889 890 DPRINTFN(1, "ep_no=%d\n", td->channel); 891 892 /* select endpoint 0 */ 893 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 894 895 /* read out FIFO status */ 896 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 897 898 DPRINTFN(4, "csr=0x%02x\n", csr); 899 900 got_short = 0; 901 if (!td->transaction_started) { 902 td->transaction_started = 1; 903 904 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 905 906 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 907 td->dev_addr); 908 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 909 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 910 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 911 912 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 913 MUSB2_MASK_CSR0L_REQPKT); 914 915 return (1); 916 } 917 918 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 919 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 920 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 921 922 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 923 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 924 925 td->error = 1; 926 } 927 928 /* Failed */ 929 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 930 MUSB2_MASK_CSR0L_ERROR)) 931 { 932 /* Clear status bit */ 933 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 934 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 935 td->error = 1; 936 } 937 938 if (td->error) { 939 musbotg_channel_free(sc, td); 940 return (0); /* we are complete */ 941 } 942 943 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) 944 return (1); /* not yet */ 945 946 /* get the packet byte count */ 947 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 948 949 /* verify the packet byte count */ 950 if (count != td->max_frame_size) { 951 if (count < td->max_frame_size) { 952 /* we have a short packet */ 953 td->short_pkt = 1; 954 got_short = 1; 955 } else { 956 /* invalid USB packet */ 957 td->error = 1; 958 musbotg_channel_free(sc, td); 959 return (0); /* we are complete */ 960 } 961 } 962 /* verify the packet byte count */ 963 if (count > td->remainder) { 964 /* invalid USB packet */ 965 td->error = 1; 966 musbotg_channel_free(sc, td); 967 return (0); /* we are complete */ 968 } 969 while (count > 0) { 970 uint32_t temp; 971 972 usbd_get_page(td->pc, td->offset, &buf_res); 973 974 /* get correct length */ 975 if (buf_res.length > count) { 976 buf_res.length = count; 977 } 978 /* check for unaligned memory address */ 979 if (USB_P2U(buf_res.buffer) & 3) { 980 981 temp = count & ~3; 982 983 if (temp) { 984 /* receive data 4 bytes at a time */ 985 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 986 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 987 temp / 4); 988 } 989 temp = count & 3; 990 if (temp) { 991 /* receive data 1 byte at a time */ 992 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 993 MUSB2_REG_EPFIFO(0), 994 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 995 } 996 usbd_copy_in(td->pc, td->offset, 997 sc->sc_bounce_buf, count); 998 999 /* update offset and remainder */ 1000 td->offset += count; 1001 td->remainder -= count; 1002 break; 1003 } 1004 /* check if we can optimise */ 1005 if (buf_res.length >= 4) { 1006 1007 /* receive data 4 bytes at a time */ 1008 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1009 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1010 buf_res.length / 4); 1011 1012 temp = buf_res.length & ~3; 1013 1014 /* update counters */ 1015 count -= temp; 1016 td->offset += temp; 1017 td->remainder -= temp; 1018 continue; 1019 } 1020 /* receive data */ 1021 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1022 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 1023 1024 /* update counters */ 1025 count -= buf_res.length; 1026 td->offset += buf_res.length; 1027 td->remainder -= buf_res.length; 1028 } 1029 1030 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY; 1031 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1032 1033 /* check if we are complete */ 1034 if ((td->remainder == 0) || got_short) { 1035 if (td->short_pkt) { 1036 /* we are complete */ 1037 1038 musbotg_channel_free(sc, td); 1039 return (0); 1040 } 1041 /* else need to receive a zero length packet */ 1042 } 1043 1044 td->transaction_started = 1; 1045 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1046 MUSB2_MASK_CSR0L_REQPKT); 1047 1048 return (1); /* not complete */ 1049 } 1050 1051 static uint8_t 1052 musbotg_host_ctrl_data_tx(struct musbotg_td *td) 1053 { 1054 struct usb_page_search buf_res; 1055 struct musbotg_softc *sc; 1056 uint16_t count; 1057 uint8_t csr, csrh; 1058 1059 /* get pointer to softc */ 1060 sc = MUSBOTG_PC2SC(td->pc); 1061 1062 if (td->channel == -1) 1063 td->channel = musbotg_channel_alloc(sc, td, 1); 1064 1065 /* No free EPs */ 1066 if (td->channel == -1) 1067 return (1); 1068 1069 DPRINTFN(1, "ep_no=%d\n", td->channel); 1070 1071 /* select endpoint */ 1072 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1073 1074 /* read out FIFO status */ 1075 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1076 DPRINTFN(4, "csr=0x%02x\n", csr); 1077 1078 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1079 MUSB2_MASK_CSR0L_ERROR)) { 1080 /* clear status bits */ 1081 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1082 td->error = 1; 1083 } 1084 1085 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) { 1086 1087 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1088 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1089 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1090 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1091 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1092 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1093 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1094 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1095 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1096 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1097 } 1098 } 1099 1100 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1101 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1102 1103 td->error = 1; 1104 } 1105 1106 1107 if (td->error) { 1108 musbotg_channel_free(sc, td); 1109 return (0); /* complete */ 1110 } 1111 1112 /* 1113 * Wait while FIFO is empty. 1114 * Do not flush it because it will cause transactions 1115 * with size more then packet size. It might upset 1116 * some devices 1117 */ 1118 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) 1119 return (1); 1120 1121 /* Packet still being processed */ 1122 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1123 return (1); 1124 1125 if (td->transaction_started) { 1126 /* check remainder */ 1127 if (td->remainder == 0) { 1128 if (td->short_pkt) { 1129 musbotg_channel_free(sc, td); 1130 return (0); /* complete */ 1131 } 1132 /* else we need to transmit a short packet */ 1133 } 1134 1135 /* We're not complete - more transactions required */ 1136 td->transaction_started = 0; 1137 } 1138 1139 /* check for short packet */ 1140 count = td->max_frame_size; 1141 if (td->remainder < count) { 1142 /* we have a short packet */ 1143 td->short_pkt = 1; 1144 count = td->remainder; 1145 } 1146 1147 while (count > 0) { 1148 uint32_t temp; 1149 1150 usbd_get_page(td->pc, td->offset, &buf_res); 1151 1152 /* get correct length */ 1153 if (buf_res.length > count) { 1154 buf_res.length = count; 1155 } 1156 /* check for unaligned memory address */ 1157 if (USB_P2U(buf_res.buffer) & 3) { 1158 1159 usbd_copy_out(td->pc, td->offset, 1160 sc->sc_bounce_buf, count); 1161 1162 temp = count & ~3; 1163 1164 if (temp) { 1165 /* transmit data 4 bytes at a time */ 1166 bus_space_write_multi_4(sc->sc_io_tag, 1167 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), 1168 sc->sc_bounce_buf, temp / 4); 1169 } 1170 temp = count & 3; 1171 if (temp) { 1172 /* receive data 1 byte at a time */ 1173 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1174 MUSB2_REG_EPFIFO(0), 1175 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1176 } 1177 /* update offset and remainder */ 1178 td->offset += count; 1179 td->remainder -= count; 1180 break; 1181 } 1182 /* check if we can optimise */ 1183 if (buf_res.length >= 4) { 1184 1185 /* transmit data 4 bytes at a time */ 1186 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1187 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1188 buf_res.length / 4); 1189 1190 temp = buf_res.length & ~3; 1191 1192 /* update counters */ 1193 count -= temp; 1194 td->offset += temp; 1195 td->remainder -= temp; 1196 continue; 1197 } 1198 /* transmit data */ 1199 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1200 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1201 buf_res.length); 1202 1203 /* update counters */ 1204 count -= buf_res.length; 1205 td->offset += buf_res.length; 1206 td->remainder -= buf_res.length; 1207 } 1208 1209 /* Function address */ 1210 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1211 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1212 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1213 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1214 1215 /* TX NAK timeout */ 1216 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1217 1218 /* write command */ 1219 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1220 MUSB2_MASK_CSR0L_TXPKTRDY); 1221 1222 td->transaction_started = 1; 1223 1224 return (1); /* not complete */ 1225 } 1226 1227 static uint8_t 1228 musbotg_dev_ctrl_status(struct musbotg_td *td) 1229 { 1230 struct musbotg_softc *sc; 1231 uint8_t csr; 1232 1233 /* get pointer to softc */ 1234 sc = MUSBOTG_PC2SC(td->pc); 1235 1236 /* select endpoint 0 */ 1237 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1238 1239 if (sc->sc_ep0_busy) { 1240 sc->sc_ep0_busy = 0; 1241 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 1242 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 1243 sc->sc_ep0_cmd = 0; 1244 } 1245 /* read out FIFO status */ 1246 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1247 1248 DPRINTFN(4, "csr=0x%02x\n", csr); 1249 1250 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 1251 /* wait for interrupt */ 1252 return (1); /* not complete */ 1253 } 1254 if (sc->sc_dv_addr != 0xFF) { 1255 /* write function address */ 1256 musbotg_set_address(sc, sc->sc_dv_addr); 1257 } 1258 1259 musbotg_channel_free(sc, td); 1260 return (0); /* complete */ 1261 } 1262 1263 static uint8_t 1264 musbotg_host_ctrl_status_rx(struct musbotg_td *td) 1265 { 1266 struct musbotg_softc *sc; 1267 uint8_t csr, csrh; 1268 1269 /* get pointer to softc */ 1270 sc = MUSBOTG_PC2SC(td->pc); 1271 1272 if (td->channel == -1) 1273 td->channel = musbotg_channel_alloc(sc, td, 0); 1274 1275 /* EP0 is busy, wait */ 1276 if (td->channel == -1) 1277 return (1); 1278 1279 DPRINTFN(1, "ep_no=%d\n", td->channel); 1280 1281 /* select endpoint 0 */ 1282 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1283 1284 if (!td->transaction_started) { 1285 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 1286 td->dev_addr); 1287 1288 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 1289 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 1290 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1291 1292 /* RX NAK timeout */ 1293 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1294 1295 td->transaction_started = 1; 1296 1297 /* Disable PING */ 1298 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1299 csrh |= MUSB2_MASK_CSR0H_PING_DIS; 1300 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1301 1302 /* write command */ 1303 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1304 MUSB2_MASK_CSR0L_STATUSPKT | 1305 MUSB2_MASK_CSR0L_REQPKT); 1306 1307 return (1); /* Just started */ 1308 1309 } 1310 1311 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1312 1313 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr); 1314 1315 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) { 1316 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1317 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 1318 musbotg_channel_free(sc, td); 1319 return (0); /* complete */ 1320 } 1321 1322 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1323 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT | 1324 MUSB2_MASK_CSR0L_REQPKT); 1325 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1326 1327 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1328 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1329 td->error = 1; 1330 } 1331 1332 /* Failed */ 1333 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1334 MUSB2_MASK_CSR0L_ERROR)) 1335 { 1336 /* Clear status bit */ 1337 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1338 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1339 td->error = 1; 1340 } 1341 1342 if (td->error) { 1343 musbotg_channel_free(sc, td); 1344 return (0); 1345 } 1346 1347 return (1); /* Not ready yet */ 1348 } 1349 1350 static uint8_t 1351 musbotg_host_ctrl_status_tx(struct musbotg_td *td) 1352 { 1353 struct musbotg_softc *sc; 1354 uint8_t csr; 1355 1356 /* get pointer to softc */ 1357 sc = MUSBOTG_PC2SC(td->pc); 1358 1359 if (td->channel == -1) 1360 td->channel = musbotg_channel_alloc(sc, td, 1); 1361 1362 /* EP0 is busy, wait */ 1363 if (td->channel == -1) 1364 return (1); 1365 1366 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started, 1367 td->dev_addr,td->haddr,td->hport, td->transfer_type); 1368 1369 /* select endpoint 0 */ 1370 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1371 1372 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1373 DPRINTFN(4, "csr=0x%02x\n", csr); 1374 1375 /* Not yet */ 1376 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1377 return (1); 1378 1379 /* Failed */ 1380 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1381 MUSB2_MASK_CSR0L_ERROR)) 1382 { 1383 /* Clear status bit */ 1384 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1385 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1386 td->error = 1; 1387 musbotg_channel_free(sc, td); 1388 return (0); /* complete */ 1389 } 1390 1391 if (td->transaction_started) { 1392 musbotg_channel_free(sc, td); 1393 return (0); /* complete */ 1394 } 1395 1396 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS); 1397 1398 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1399 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1400 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1401 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1402 1403 /* TX NAK timeout */ 1404 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1405 1406 td->transaction_started = 1; 1407 1408 /* write command */ 1409 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1410 MUSB2_MASK_CSR0L_STATUSPKT | 1411 MUSB2_MASK_CSR0L_TXPKTRDY); 1412 1413 return (1); /* wait for interrupt */ 1414 } 1415 1416 static uint8_t 1417 musbotg_dev_data_rx(struct musbotg_td *td) 1418 { 1419 struct usb_page_search buf_res; 1420 struct musbotg_softc *sc; 1421 uint16_t count; 1422 uint8_t csr; 1423 uint8_t to; 1424 uint8_t got_short; 1425 1426 to = 8; /* don't loop forever! */ 1427 got_short = 0; 1428 1429 /* get pointer to softc */ 1430 sc = MUSBOTG_PC2SC(td->pc); 1431 1432 if (td->channel == -1) 1433 td->channel = musbotg_channel_alloc(sc, td, 0); 1434 1435 /* EP0 is busy, wait */ 1436 if (td->channel == -1) 1437 return (1); 1438 1439 /* select endpoint */ 1440 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1441 1442 repeat: 1443 /* read out FIFO status */ 1444 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1445 1446 DPRINTFN(4, "csr=0x%02x\n", csr); 1447 1448 /* clear overrun */ 1449 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 1450 /* make sure we don't clear "RXPKTRDY" */ 1451 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1452 MUSB2_MASK_CSRL_RXPKTRDY); 1453 } 1454 1455 /* check status */ 1456 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) 1457 return (1); /* not complete */ 1458 1459 /* get the packet byte count */ 1460 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1461 1462 DPRINTFN(4, "count=0x%04x\n", count); 1463 1464 /* 1465 * Check for short or invalid packet: 1466 */ 1467 if (count != td->max_frame_size) { 1468 if (count < td->max_frame_size) { 1469 /* we have a short packet */ 1470 td->short_pkt = 1; 1471 got_short = 1; 1472 } else { 1473 /* invalid USB packet */ 1474 td->error = 1; 1475 musbotg_channel_free(sc, td); 1476 return (0); /* we are complete */ 1477 } 1478 } 1479 /* verify the packet byte count */ 1480 if (count > td->remainder) { 1481 /* invalid USB packet */ 1482 td->error = 1; 1483 musbotg_channel_free(sc, td); 1484 return (0); /* we are complete */ 1485 } 1486 while (count > 0) { 1487 uint32_t temp; 1488 1489 usbd_get_page(td->pc, td->offset, &buf_res); 1490 1491 /* get correct length */ 1492 if (buf_res.length > count) { 1493 buf_res.length = count; 1494 } 1495 /* check for unaligned memory address */ 1496 if (USB_P2U(buf_res.buffer) & 3) { 1497 1498 temp = count & ~3; 1499 1500 if (temp) { 1501 /* receive data 4 bytes at a time */ 1502 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1503 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1504 temp / 4); 1505 } 1506 temp = count & 3; 1507 if (temp) { 1508 /* receive data 1 byte at a time */ 1509 bus_space_read_multi_1(sc->sc_io_tag, 1510 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1511 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1512 } 1513 usbd_copy_in(td->pc, td->offset, 1514 sc->sc_bounce_buf, count); 1515 1516 /* update offset and remainder */ 1517 td->offset += count; 1518 td->remainder -= count; 1519 break; 1520 } 1521 /* check if we can optimise */ 1522 if (buf_res.length >= 4) { 1523 1524 /* receive data 4 bytes at a time */ 1525 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1526 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1527 buf_res.length / 4); 1528 1529 temp = buf_res.length & ~3; 1530 1531 /* update counters */ 1532 count -= temp; 1533 td->offset += temp; 1534 td->remainder -= temp; 1535 continue; 1536 } 1537 /* receive data */ 1538 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1539 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1540 buf_res.length); 1541 1542 /* update counters */ 1543 count -= buf_res.length; 1544 td->offset += buf_res.length; 1545 td->remainder -= buf_res.length; 1546 } 1547 1548 /* clear status bits */ 1549 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1550 1551 /* check if we are complete */ 1552 if ((td->remainder == 0) || got_short) { 1553 if (td->short_pkt) { 1554 /* we are complete */ 1555 musbotg_channel_free(sc, td); 1556 return (0); 1557 } 1558 /* else need to receive a zero length packet */ 1559 } 1560 if (--to) { 1561 goto repeat; 1562 } 1563 return (1); /* not complete */ 1564 } 1565 1566 static uint8_t 1567 musbotg_dev_data_tx(struct musbotg_td *td) 1568 { 1569 struct usb_page_search buf_res; 1570 struct musbotg_softc *sc; 1571 uint16_t count; 1572 uint8_t csr; 1573 uint8_t to; 1574 1575 to = 8; /* don't loop forever! */ 1576 1577 /* get pointer to softc */ 1578 sc = MUSBOTG_PC2SC(td->pc); 1579 1580 if (td->channel == -1) 1581 td->channel = musbotg_channel_alloc(sc, td, 1); 1582 1583 /* EP0 is busy, wait */ 1584 if (td->channel == -1) 1585 return (1); 1586 1587 /* select endpoint */ 1588 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1589 1590 repeat: 1591 1592 /* read out FIFO status */ 1593 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1594 1595 DPRINTFN(4, "csr=0x%02x\n", csr); 1596 1597 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 1598 MUSB2_MASK_CSRL_TXUNDERRUN)) { 1599 /* clear status bits */ 1600 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1601 } 1602 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 1603 return (1); /* not complete */ 1604 } 1605 /* check for short packet */ 1606 count = td->max_frame_size; 1607 if (td->remainder < count) { 1608 /* we have a short packet */ 1609 td->short_pkt = 1; 1610 count = td->remainder; 1611 } 1612 while (count > 0) { 1613 uint32_t temp; 1614 1615 usbd_get_page(td->pc, td->offset, &buf_res); 1616 1617 /* get correct length */ 1618 if (buf_res.length > count) { 1619 buf_res.length = count; 1620 } 1621 /* check for unaligned memory address */ 1622 if (USB_P2U(buf_res.buffer) & 3) { 1623 1624 usbd_copy_out(td->pc, td->offset, 1625 sc->sc_bounce_buf, count); 1626 1627 temp = count & ~3; 1628 1629 if (temp) { 1630 /* transmit data 4 bytes at a time */ 1631 bus_space_write_multi_4(sc->sc_io_tag, 1632 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1633 sc->sc_bounce_buf, temp / 4); 1634 } 1635 temp = count & 3; 1636 if (temp) { 1637 /* receive data 1 byte at a time */ 1638 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1639 MUSB2_REG_EPFIFO(td->channel), 1640 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1641 } 1642 /* update offset and remainder */ 1643 td->offset += count; 1644 td->remainder -= count; 1645 break; 1646 } 1647 /* check if we can optimise */ 1648 if (buf_res.length >= 4) { 1649 1650 /* transmit data 4 bytes at a time */ 1651 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1652 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1653 buf_res.length / 4); 1654 1655 temp = buf_res.length & ~3; 1656 1657 /* update counters */ 1658 count -= temp; 1659 td->offset += temp; 1660 td->remainder -= temp; 1661 continue; 1662 } 1663 /* transmit data */ 1664 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1665 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1666 buf_res.length); 1667 1668 /* update counters */ 1669 count -= buf_res.length; 1670 td->offset += buf_res.length; 1671 td->remainder -= buf_res.length; 1672 } 1673 1674 /* Max packet size */ 1675 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); 1676 1677 /* write command */ 1678 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1679 MUSB2_MASK_CSRL_TXPKTRDY); 1680 1681 /* check remainder */ 1682 if (td->remainder == 0) { 1683 if (td->short_pkt) { 1684 musbotg_channel_free(sc, td); 1685 return (0); /* complete */ 1686 } 1687 /* else we need to transmit a short packet */ 1688 } 1689 if (--to) { 1690 goto repeat; 1691 } 1692 return (1); /* not complete */ 1693 } 1694 1695 static uint8_t 1696 musbotg_host_data_rx(struct musbotg_td *td) 1697 { 1698 struct usb_page_search buf_res; 1699 struct musbotg_softc *sc; 1700 uint16_t count; 1701 uint8_t csr, csrh; 1702 uint8_t to; 1703 uint8_t got_short; 1704 1705 /* get pointer to softc */ 1706 sc = MUSBOTG_PC2SC(td->pc); 1707 1708 if (td->channel == -1) 1709 td->channel = musbotg_channel_alloc(sc, td, 0); 1710 1711 /* No free EPs */ 1712 if (td->channel == -1) 1713 return (1); 1714 1715 DPRINTFN(1, "ep_no=%d\n", td->channel); 1716 1717 to = 8; /* don't loop forever! */ 1718 got_short = 0; 1719 1720 /* select endpoint */ 1721 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1722 1723 repeat: 1724 /* read out FIFO status */ 1725 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1726 DPRINTFN(4, "csr=0x%02x\n", csr); 1727 1728 if (!td->transaction_started) { 1729 /* Function address */ 1730 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel), 1731 td->dev_addr); 1732 1733 /* SPLIT transaction */ 1734 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel), 1735 td->haddr); 1736 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel), 1737 td->hport); 1738 1739 /* RX NAK timeout */ 1740 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) 1741 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0); 1742 else 1743 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1744 1745 /* Protocol, speed, device endpoint */ 1746 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1747 1748 /* Max packet size */ 1749 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet); 1750 1751 /* Data Toggle */ 1752 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1753 DPRINTFN(4, "csrh=0x%02x\n", csrh); 1754 1755 csrh |= MUSB2_MASK_CSRH_RXDT_WREN; 1756 if (td->toggle) 1757 csrh |= MUSB2_MASK_CSRH_RXDT_VAL; 1758 else 1759 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1760 1761 /* Set data toggle */ 1762 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1763 1764 /* write command */ 1765 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1766 MUSB2_MASK_CSRL_RXREQPKT); 1767 1768 td->transaction_started = 1; 1769 return (1); 1770 } 1771 1772 /* clear NAK timeout */ 1773 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1774 DPRINTFN(4, "NAK Timeout\n"); 1775 if (csr & MUSB2_MASK_CSRL_RXREQPKT) { 1776 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1777 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1778 1779 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1780 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1781 } 1782 1783 td->error = 1; 1784 } 1785 1786 if (csr & MUSB2_MASK_CSRL_RXERROR) { 1787 DPRINTFN(4, "RXERROR\n"); 1788 td->error = 1; 1789 } 1790 1791 if (csr & MUSB2_MASK_CSRL_RXSTALL) { 1792 DPRINTFN(4, "RXSTALL\n"); 1793 td->error = 1; 1794 } 1795 1796 if (td->error) { 1797 musbotg_channel_free(sc, td); 1798 return (0); /* we are complete */ 1799 } 1800 1801 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 1802 /* No data available yet */ 1803 return (1); 1804 } 1805 1806 td->toggle ^= 1; 1807 /* get the packet byte count */ 1808 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1809 DPRINTFN(4, "count=0x%04x\n", count); 1810 1811 /* 1812 * Check for short or invalid packet: 1813 */ 1814 if (count != td->max_frame_size) { 1815 if (count < td->max_frame_size) { 1816 /* we have a short packet */ 1817 td->short_pkt = 1; 1818 got_short = 1; 1819 } else { 1820 /* invalid USB packet */ 1821 td->error = 1; 1822 musbotg_channel_free(sc, td); 1823 return (0); /* we are complete */ 1824 } 1825 } 1826 1827 /* verify the packet byte count */ 1828 if (count > td->remainder) { 1829 /* invalid USB packet */ 1830 td->error = 1; 1831 musbotg_channel_free(sc, td); 1832 return (0); /* we are complete */ 1833 } 1834 1835 while (count > 0) { 1836 uint32_t temp; 1837 1838 usbd_get_page(td->pc, td->offset, &buf_res); 1839 1840 /* get correct length */ 1841 if (buf_res.length > count) { 1842 buf_res.length = count; 1843 } 1844 /* check for unaligned memory address */ 1845 if (USB_P2U(buf_res.buffer) & 3) { 1846 1847 temp = count & ~3; 1848 1849 if (temp) { 1850 /* receive data 4 bytes at a time */ 1851 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1852 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1853 temp / 4); 1854 } 1855 temp = count & 3; 1856 if (temp) { 1857 /* receive data 1 byte at a time */ 1858 bus_space_read_multi_1(sc->sc_io_tag, 1859 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1860 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1861 } 1862 usbd_copy_in(td->pc, td->offset, 1863 sc->sc_bounce_buf, count); 1864 1865 /* update offset and remainder */ 1866 td->offset += count; 1867 td->remainder -= count; 1868 break; 1869 } 1870 /* check if we can optimise */ 1871 if (buf_res.length >= 4) { 1872 1873 /* receive data 4 bytes at a time */ 1874 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1875 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1876 buf_res.length / 4); 1877 1878 temp = buf_res.length & ~3; 1879 1880 /* update counters */ 1881 count -= temp; 1882 td->offset += temp; 1883 td->remainder -= temp; 1884 continue; 1885 } 1886 /* receive data */ 1887 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1888 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1889 buf_res.length); 1890 1891 /* update counters */ 1892 count -= buf_res.length; 1893 td->offset += buf_res.length; 1894 td->remainder -= buf_res.length; 1895 } 1896 1897 /* clear status bits */ 1898 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1899 1900 /* check if we are complete */ 1901 if ((td->remainder == 0) || got_short) { 1902 if (td->short_pkt) { 1903 /* we are complete */ 1904 musbotg_channel_free(sc, td); 1905 return (0); 1906 } 1907 /* else need to receive a zero length packet */ 1908 } 1909 1910 /* Reset transaction state and restart */ 1911 td->transaction_started = 0; 1912 1913 if (--to) 1914 goto repeat; 1915 1916 return (1); /* not complete */ 1917 } 1918 1919 static uint8_t 1920 musbotg_host_data_tx(struct musbotg_td *td) 1921 { 1922 struct usb_page_search buf_res; 1923 struct musbotg_softc *sc; 1924 uint16_t count; 1925 uint8_t csr, csrh; 1926 1927 /* get pointer to softc */ 1928 sc = MUSBOTG_PC2SC(td->pc); 1929 1930 if (td->channel == -1) 1931 td->channel = musbotg_channel_alloc(sc, td, 1); 1932 1933 /* No free EPs */ 1934 if (td->channel == -1) 1935 return (1); 1936 1937 DPRINTFN(1, "ep_no=%d\n", td->channel); 1938 1939 /* select endpoint */ 1940 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1941 1942 /* read out FIFO status */ 1943 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1944 DPRINTFN(4, "csr=0x%02x\n", csr); 1945 1946 if (csr & (MUSB2_MASK_CSRL_TXSTALLED | 1947 MUSB2_MASK_CSRL_TXERROR)) { 1948 /* clear status bits */ 1949 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1950 td->error = 1; 1951 musbotg_channel_free(sc, td); 1952 return (0); /* complete */ 1953 } 1954 1955 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 1956 /* 1957 * Flush TX FIFO before clearing NAK TO 1958 */ 1959 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1960 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1961 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1962 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1963 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1964 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1965 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1966 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1967 } 1968 } 1969 1970 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 1971 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1972 1973 td->error = 1; 1974 musbotg_channel_free(sc, td); 1975 return (0); /* complete */ 1976 } 1977 1978 /* 1979 * Wait while FIFO is empty. 1980 * Do not flush it because it will cause transactions 1981 * with size more then packet size. It might upset 1982 * some devices 1983 */ 1984 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) 1985 return (1); 1986 1987 /* Packet still being processed */ 1988 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) 1989 return (1); 1990 1991 if (td->transaction_started) { 1992 /* check remainder */ 1993 if (td->remainder == 0) { 1994 if (td->short_pkt) { 1995 musbotg_channel_free(sc, td); 1996 return (0); /* complete */ 1997 } 1998 /* else we need to transmit a short packet */ 1999 } 2000 2001 /* We're not complete - more transactions required */ 2002 td->transaction_started = 0; 2003 } 2004 2005 /* check for short packet */ 2006 count = td->max_frame_size; 2007 if (td->remainder < count) { 2008 /* we have a short packet */ 2009 td->short_pkt = 1; 2010 count = td->remainder; 2011 } 2012 2013 while (count > 0) { 2014 uint32_t temp; 2015 2016 usbd_get_page(td->pc, td->offset, &buf_res); 2017 2018 /* get correct length */ 2019 if (buf_res.length > count) { 2020 buf_res.length = count; 2021 } 2022 /* check for unaligned memory address */ 2023 if (USB_P2U(buf_res.buffer) & 3) { 2024 2025 usbd_copy_out(td->pc, td->offset, 2026 sc->sc_bounce_buf, count); 2027 2028 temp = count & ~3; 2029 2030 if (temp) { 2031 /* transmit data 4 bytes at a time */ 2032 bus_space_write_multi_4(sc->sc_io_tag, 2033 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 2034 sc->sc_bounce_buf, temp / 4); 2035 } 2036 temp = count & 3; 2037 if (temp) { 2038 /* receive data 1 byte at a time */ 2039 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2040 MUSB2_REG_EPFIFO(td->channel), 2041 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 2042 } 2043 /* update offset and remainder */ 2044 td->offset += count; 2045 td->remainder -= count; 2046 break; 2047 } 2048 /* check if we can optimise */ 2049 if (buf_res.length >= 4) { 2050 2051 /* transmit data 4 bytes at a time */ 2052 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 2053 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2054 buf_res.length / 4); 2055 2056 temp = buf_res.length & ~3; 2057 2058 /* update counters */ 2059 count -= temp; 2060 td->offset += temp; 2061 td->remainder -= temp; 2062 continue; 2063 } 2064 /* transmit data */ 2065 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2066 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2067 buf_res.length); 2068 2069 /* update counters */ 2070 count -= buf_res.length; 2071 td->offset += buf_res.length; 2072 td->remainder -= buf_res.length; 2073 } 2074 2075 /* Function address */ 2076 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel), 2077 td->dev_addr); 2078 2079 /* SPLIT transaction */ 2080 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel), 2081 td->haddr); 2082 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel), 2083 td->hport); 2084 2085 /* TX NAK timeout */ 2086 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) 2087 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0); 2088 else 2089 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 2090 2091 /* Protocol, speed, device endpoint */ 2092 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 2093 2094 /* Max packet size */ 2095 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); 2096 2097 if (!td->transaction_started) { 2098 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 2099 DPRINTFN(4, "csrh=0x%02x\n", csrh); 2100 2101 csrh |= MUSB2_MASK_CSRH_TXDT_WREN; 2102 if (td->toggle) 2103 csrh |= MUSB2_MASK_CSRH_TXDT_VAL; 2104 else 2105 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2106 2107 /* Set data toggle */ 2108 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 2109 } 2110 2111 /* write command */ 2112 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2113 MUSB2_MASK_CSRL_TXPKTRDY); 2114 2115 /* Update Data Toggle */ 2116 td->toggle ^= 1; 2117 td->transaction_started = 1; 2118 2119 return (1); /* not complete */ 2120 } 2121 2122 static uint8_t 2123 musbotg_xfer_do_fifo(struct usb_xfer *xfer) 2124 { 2125 struct musbotg_softc *sc; 2126 struct musbotg_td *td; 2127 2128 DPRINTFN(8, "\n"); 2129 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2130 2131 td = xfer->td_transfer_cache; 2132 while (1) { 2133 2134 if ((td->func) (td)) { 2135 /* operation in progress */ 2136 break; 2137 } 2138 2139 if (((void *)td) == xfer->td_transfer_last) { 2140 goto done; 2141 } 2142 if (td->error) { 2143 goto done; 2144 } else if (td->remainder > 0) { 2145 /* 2146 * We had a short transfer. If there is no alternate 2147 * next, stop processing ! 2148 */ 2149 if (!td->alt_next) { 2150 goto done; 2151 } 2152 } 2153 /* 2154 * Fetch the next transfer descriptor and transfer 2155 * some flags to the next transfer descriptor 2156 */ 2157 td = td->obj_next; 2158 xfer->td_transfer_cache = td; 2159 } 2160 2161 return (1); /* not complete */ 2162 done: 2163 /* compute all actual lengths */ 2164 musbotg_standard_done(xfer); 2165 2166 return (0); /* complete */ 2167 } 2168 2169 static void 2170 musbotg_interrupt_poll(struct musbotg_softc *sc) 2171 { 2172 struct usb_xfer *xfer; 2173 2174 repeat: 2175 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2176 if (!musbotg_xfer_do_fifo(xfer)) { 2177 /* queue has been modified */ 2178 goto repeat; 2179 } 2180 } 2181 } 2182 2183 void 2184 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 2185 { 2186 DPRINTFN(4, "vbus = %u\n", is_on); 2187 2188 USB_BUS_LOCK(&sc->sc_bus); 2189 if (is_on) { 2190 if (!sc->sc_flags.status_vbus) { 2191 sc->sc_flags.status_vbus = 1; 2192 2193 /* complete root HUB interrupt endpoint */ 2194 musbotg_root_intr(sc); 2195 } 2196 } else { 2197 if (sc->sc_flags.status_vbus) { 2198 sc->sc_flags.status_vbus = 0; 2199 sc->sc_flags.status_bus_reset = 0; 2200 sc->sc_flags.status_suspend = 0; 2201 sc->sc_flags.change_suspend = 0; 2202 sc->sc_flags.change_connect = 1; 2203 2204 /* complete root HUB interrupt endpoint */ 2205 musbotg_root_intr(sc); 2206 } 2207 } 2208 2209 USB_BUS_UNLOCK(&sc->sc_bus); 2210 } 2211 2212 void 2213 musbotg_connect_interrupt(struct musbotg_softc *sc) 2214 { 2215 USB_BUS_LOCK(&sc->sc_bus); 2216 sc->sc_flags.change_connect = 1; 2217 2218 /* complete root HUB interrupt endpoint */ 2219 musbotg_root_intr(sc); 2220 USB_BUS_UNLOCK(&sc->sc_bus); 2221 } 2222 2223 void 2224 musbotg_interrupt(struct musbotg_softc *sc, 2225 uint16_t rxstat, uint16_t txstat, uint8_t stat) 2226 { 2227 uint16_t rx_status; 2228 uint16_t tx_status; 2229 uint8_t usb_status; 2230 uint8_t temp; 2231 uint8_t to = 2; 2232 2233 USB_BUS_LOCK(&sc->sc_bus); 2234 2235 repeat: 2236 2237 /* read all interrupt registers */ 2238 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 2239 2240 /* read all FIFO interrupts */ 2241 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 2242 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 2243 rx_status |= rxstat; 2244 tx_status |= txstat; 2245 usb_status |= stat; 2246 2247 /* Clear platform flags after first time */ 2248 rxstat = 0; 2249 txstat = 0; 2250 stat = 0; 2251 2252 /* check for any bus state change interrupts */ 2253 2254 if (usb_status & (MUSB2_MASK_IRESET | 2255 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 2256 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 2257 2258 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 2259 2260 if (usb_status & MUSB2_MASK_IRESET) { 2261 2262 /* set correct state */ 2263 sc->sc_flags.status_bus_reset = 1; 2264 sc->sc_flags.status_suspend = 0; 2265 sc->sc_flags.change_suspend = 0; 2266 sc->sc_flags.change_connect = 1; 2267 2268 /* determine line speed */ 2269 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 2270 if (temp & MUSB2_MASK_HSMODE) 2271 sc->sc_flags.status_high_speed = 1; 2272 else 2273 sc->sc_flags.status_high_speed = 0; 2274 2275 /* 2276 * After reset all interrupts are on and we need to 2277 * turn them off! 2278 */ 2279 temp = MUSB2_MASK_IRESET; 2280 /* disable resume interrupt */ 2281 temp &= ~MUSB2_MASK_IRESUME; 2282 /* enable suspend interrupt */ 2283 temp |= MUSB2_MASK_ISUSP; 2284 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2285 /* disable TX and RX interrupts */ 2286 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 2287 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 2288 } 2289 /* 2290 * If RXRSM and RXSUSP is set at the same time we interpret 2291 * that like RESUME. Resume is set when there is at least 3 2292 * milliseconds of inactivity on the USB BUS. 2293 */ 2294 if (usb_status & MUSB2_MASK_IRESUME) { 2295 if (sc->sc_flags.status_suspend) { 2296 sc->sc_flags.status_suspend = 0; 2297 sc->sc_flags.change_suspend = 1; 2298 2299 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2300 /* disable resume interrupt */ 2301 temp &= ~MUSB2_MASK_IRESUME; 2302 /* enable suspend interrupt */ 2303 temp |= MUSB2_MASK_ISUSP; 2304 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2305 } 2306 } else if (usb_status & MUSB2_MASK_ISUSP) { 2307 if (!sc->sc_flags.status_suspend) { 2308 sc->sc_flags.status_suspend = 1; 2309 sc->sc_flags.change_suspend = 1; 2310 2311 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2312 /* disable suspend interrupt */ 2313 temp &= ~MUSB2_MASK_ISUSP; 2314 /* enable resume interrupt */ 2315 temp |= MUSB2_MASK_IRESUME; 2316 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2317 } 2318 } 2319 if (usb_status & 2320 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) 2321 sc->sc_flags.change_connect = 1; 2322 2323 /* 2324 * Host Mode: There is no IRESET so assume bus is 2325 * always in reset state once device is connected. 2326 */ 2327 if (sc->sc_mode == MUSB2_HOST_MODE) { 2328 if (usb_status & MUSB2_MASK_ICONN) 2329 sc->sc_flags.status_bus_reset = 1; 2330 if (usb_status & MUSB2_MASK_IDISC) 2331 sc->sc_flags.status_bus_reset = 0; 2332 } 2333 2334 /* complete root HUB interrupt endpoint */ 2335 musbotg_root_intr(sc); 2336 } 2337 /* check for any endpoint interrupts */ 2338 2339 if (rx_status || tx_status) { 2340 DPRINTFN(4, "real endpoint interrupt " 2341 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 2342 } 2343 /* poll one time regardless of FIFO status */ 2344 2345 musbotg_interrupt_poll(sc); 2346 2347 if (--to) 2348 goto repeat; 2349 2350 USB_BUS_UNLOCK(&sc->sc_bus); 2351 } 2352 2353 static void 2354 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 2355 { 2356 struct musbotg_td *td; 2357 2358 /* get current Transfer Descriptor */ 2359 td = temp->td_next; 2360 temp->td = td; 2361 2362 /* prepare for next TD */ 2363 temp->td_next = td->obj_next; 2364 2365 /* fill out the Transfer Descriptor */ 2366 td->func = temp->func; 2367 td->pc = temp->pc; 2368 td->offset = temp->offset; 2369 td->remainder = temp->len; 2370 td->error = 0; 2371 td->transaction_started = 0; 2372 td->did_stall = temp->did_stall; 2373 td->short_pkt = temp->short_pkt; 2374 td->alt_next = temp->setup_alt_next; 2375 td->channel = temp->channel; 2376 td->dev_addr = temp->dev_addr; 2377 td->haddr = temp->haddr; 2378 td->hport = temp->hport; 2379 td->transfer_type = temp->transfer_type; 2380 } 2381 2382 static void 2383 musbotg_setup_standard_chain(struct usb_xfer *xfer) 2384 { 2385 struct musbotg_std_temp temp; 2386 struct musbotg_softc *sc; 2387 struct musbotg_td *td; 2388 uint32_t x; 2389 uint8_t ep_no; 2390 uint8_t xfer_type; 2391 enum usb_dev_speed speed; 2392 int tx; 2393 int dev_addr; 2394 2395 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2396 xfer->address, UE_GET_ADDR(xfer->endpointno), 2397 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2398 2399 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2400 ep_no = (xfer->endpointno & UE_ADDR); 2401 2402 temp.max_frame_size = xfer->max_frame_size; 2403 2404 td = xfer->td_start[0]; 2405 xfer->td_transfer_first = td; 2406 xfer->td_transfer_cache = td; 2407 2408 /* setup temp */ 2409 dev_addr = xfer->address; 2410 2411 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 2412 2413 temp.pc = NULL; 2414 temp.td = NULL; 2415 temp.td_next = xfer->td_start[0]; 2416 temp.offset = 0; 2417 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 2418 xfer->flags_int.isochronous_xfr; 2419 temp.did_stall = !xfer->flags_int.control_stall; 2420 temp.channel = -1; 2421 temp.dev_addr = dev_addr; 2422 temp.haddr = xfer->xroot->udev->hs_hub_addr; 2423 temp.hport = xfer->xroot->udev->hs_port_no; 2424 2425 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2426 speed = usbd_get_speed(xfer->xroot->udev); 2427 2428 switch (speed) { 2429 case USB_SPEED_LOW: 2430 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO; 2431 break; 2432 case USB_SPEED_FULL: 2433 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS; 2434 break; 2435 case USB_SPEED_HIGH: 2436 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS; 2437 break; 2438 default: 2439 temp.transfer_type = 0; 2440 DPRINTFN(-1, "Invalid USB speed: %d\n", speed); 2441 break; 2442 } 2443 2444 switch (xfer_type) { 2445 case UE_CONTROL: 2446 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL; 2447 break; 2448 case UE_ISOCHRONOUS: 2449 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC; 2450 break; 2451 case UE_BULK: 2452 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK; 2453 break; 2454 case UE_INTERRUPT: 2455 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR; 2456 break; 2457 default: 2458 DPRINTFN(-1, "Invalid USB transfer type: %d\n", 2459 xfer_type); 2460 break; 2461 } 2462 2463 temp.transfer_type |= ep_no; 2464 td->toggle = xfer->endpoint->toggle_next; 2465 } 2466 2467 /* check if we should prepend a setup message */ 2468 2469 if (xfer->flags_int.control_xfr) { 2470 if (xfer->flags_int.control_hdr) { 2471 2472 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) 2473 temp.func = &musbotg_dev_ctrl_setup_rx; 2474 else 2475 temp.func = &musbotg_host_ctrl_setup_tx; 2476 2477 temp.len = xfer->frlengths[0]; 2478 temp.pc = xfer->frbuffers + 0; 2479 temp.short_pkt = temp.len ? 1 : 0; 2480 2481 musbotg_setup_standard_chain_sub(&temp); 2482 } 2483 x = 1; 2484 } else { 2485 x = 0; 2486 } 2487 2488 tx = 0; 2489 2490 if (x != xfer->nframes) { 2491 if (xfer->endpointno & UE_DIR_IN) 2492 tx = 1; 2493 2494 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2495 tx = !tx; 2496 2497 if (tx) { 2498 if (xfer->flags_int.control_xfr) 2499 temp.func = &musbotg_host_ctrl_data_tx; 2500 else 2501 temp.func = &musbotg_host_data_tx; 2502 } else { 2503 if (xfer->flags_int.control_xfr) 2504 temp.func = &musbotg_host_ctrl_data_rx; 2505 else 2506 temp.func = &musbotg_host_data_rx; 2507 } 2508 2509 } else { 2510 if (tx) { 2511 if (xfer->flags_int.control_xfr) 2512 temp.func = &musbotg_dev_ctrl_data_tx; 2513 else 2514 temp.func = &musbotg_dev_data_tx; 2515 } else { 2516 if (xfer->flags_int.control_xfr) 2517 temp.func = &musbotg_dev_ctrl_data_rx; 2518 else 2519 temp.func = &musbotg_dev_data_rx; 2520 } 2521 } 2522 2523 /* setup "pc" pointer */ 2524 temp.pc = xfer->frbuffers + x; 2525 } 2526 while (x != xfer->nframes) { 2527 2528 /* DATA0 / DATA1 message */ 2529 2530 temp.len = xfer->frlengths[x]; 2531 2532 x++; 2533 2534 if (x == xfer->nframes) { 2535 if (xfer->flags_int.control_xfr) { 2536 if (xfer->flags_int.control_act) { 2537 temp.setup_alt_next = 0; 2538 } 2539 } else { 2540 temp.setup_alt_next = 0; 2541 } 2542 } 2543 if (temp.len == 0) { 2544 2545 /* make sure that we send an USB packet */ 2546 2547 temp.short_pkt = 0; 2548 2549 } else { 2550 2551 if (xfer->flags_int.isochronous_xfr) { 2552 /* isochronous data transfer */ 2553 /* don't force short */ 2554 temp.short_pkt = 1; 2555 } else { 2556 /* regular data transfer */ 2557 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 2558 } 2559 } 2560 2561 musbotg_setup_standard_chain_sub(&temp); 2562 2563 if (xfer->flags_int.isochronous_xfr) { 2564 temp.offset += temp.len; 2565 } else { 2566 /* get next Page Cache pointer */ 2567 temp.pc = xfer->frbuffers + x; 2568 } 2569 } 2570 2571 /* check for control transfer */ 2572 if (xfer->flags_int.control_xfr) { 2573 2574 /* always setup a valid "pc" pointer for status and sync */ 2575 temp.pc = xfer->frbuffers + 0; 2576 temp.len = 0; 2577 temp.short_pkt = 0; 2578 temp.setup_alt_next = 0; 2579 2580 /* check if we should append a status stage */ 2581 if (!xfer->flags_int.control_act) { 2582 /* 2583 * Send a DATA1 message and invert the current 2584 * endpoint direction. 2585 */ 2586 if (sc->sc_mode == MUSB2_DEVICE_MODE) 2587 temp.func = &musbotg_dev_ctrl_status; 2588 else { 2589 if (xfer->endpointno & UE_DIR_IN) 2590 temp.func = musbotg_host_ctrl_status_tx; 2591 else 2592 temp.func = musbotg_host_ctrl_status_rx; 2593 } 2594 musbotg_setup_standard_chain_sub(&temp); 2595 } 2596 } 2597 /* must have at least one frame! */ 2598 td = temp.td; 2599 xfer->td_transfer_last = td; 2600 } 2601 2602 static void 2603 musbotg_timeout(void *arg) 2604 { 2605 struct usb_xfer *xfer = arg; 2606 2607 DPRINTFN(1, "xfer=%p\n", xfer); 2608 2609 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2610 2611 /* transfer is transferred */ 2612 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 2613 } 2614 2615 static void 2616 musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on) 2617 { 2618 uint16_t temp; 2619 2620 /* 2621 * Only enable the endpoint interrupt when we are 2622 * actually waiting for data, hence we are dealing 2623 * with level triggered interrupts ! 2624 */ 2625 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on); 2626 2627 if (channel == -1) 2628 return; 2629 2630 if (channel == 0) { 2631 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2632 if (on) 2633 temp |= MUSB2_MASK_EPINT(0); 2634 else 2635 temp &= ~MUSB2_MASK_EPINT(0); 2636 2637 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2638 } else { 2639 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 2640 if (on) 2641 temp |= MUSB2_MASK_EPINT(channel); 2642 else 2643 temp &= ~MUSB2_MASK_EPINT(channel); 2644 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 2645 2646 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2647 if (on) 2648 temp |= MUSB2_MASK_EPINT(channel); 2649 else 2650 temp &= ~MUSB2_MASK_EPINT(channel); 2651 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2652 } 2653 2654 if (sc->sc_ep_int_set) 2655 sc->sc_ep_int_set(sc, channel, on); 2656 } 2657 2658 static void 2659 musbotg_start_standard_chain(struct usb_xfer *xfer) 2660 { 2661 DPRINTFN(8, "\n"); 2662 2663 /* poll one time */ 2664 if (musbotg_xfer_do_fifo(xfer)) { 2665 2666 DPRINTFN(14, "enabled interrupts on endpoint\n"); 2667 2668 /* put transfer on interrupt queue */ 2669 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2670 2671 /* start timeout, if any */ 2672 if (xfer->timeout != 0) { 2673 usbd_transfer_timeout_ms(xfer, 2674 &musbotg_timeout, xfer->timeout); 2675 } 2676 } 2677 } 2678 2679 static void 2680 musbotg_root_intr(struct musbotg_softc *sc) 2681 { 2682 DPRINTFN(8, "\n"); 2683 2684 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2685 2686 /* set port bit */ 2687 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 2688 2689 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2690 sizeof(sc->sc_hub_idata)); 2691 } 2692 2693 static usb_error_t 2694 musbotg_standard_done_sub(struct usb_xfer *xfer) 2695 { 2696 struct musbotg_td *td; 2697 uint32_t len; 2698 uint8_t error; 2699 2700 DPRINTFN(8, "\n"); 2701 2702 td = xfer->td_transfer_cache; 2703 2704 do { 2705 len = td->remainder; 2706 2707 xfer->endpoint->toggle_next = td->toggle; 2708 2709 if (xfer->aframes != xfer->nframes) { 2710 /* 2711 * Verify the length and subtract 2712 * the remainder from "frlengths[]": 2713 */ 2714 if (len > xfer->frlengths[xfer->aframes]) { 2715 td->error = 1; 2716 } else { 2717 xfer->frlengths[xfer->aframes] -= len; 2718 } 2719 } 2720 /* Check for transfer error */ 2721 if (td->error) { 2722 /* the transfer is finished */ 2723 error = 1; 2724 td = NULL; 2725 break; 2726 } 2727 /* Check for short transfer */ 2728 if (len > 0) { 2729 if (xfer->flags_int.short_frames_ok || 2730 xfer->flags_int.isochronous_xfr) { 2731 /* follow alt next */ 2732 if (td->alt_next) { 2733 td = td->obj_next; 2734 } else { 2735 td = NULL; 2736 } 2737 } else { 2738 /* the transfer is finished */ 2739 td = NULL; 2740 } 2741 error = 0; 2742 break; 2743 } 2744 td = td->obj_next; 2745 2746 /* this USB frame is complete */ 2747 error = 0; 2748 break; 2749 2750 } while (0); 2751 2752 /* update transfer cache */ 2753 2754 xfer->td_transfer_cache = td; 2755 2756 return (error ? 2757 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 2758 } 2759 2760 static void 2761 musbotg_standard_done(struct usb_xfer *xfer) 2762 { 2763 usb_error_t err = 0; 2764 2765 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n", 2766 xfer, xfer->endpoint); 2767 2768 /* reset scanner */ 2769 2770 xfer->td_transfer_cache = xfer->td_transfer_first; 2771 2772 if (xfer->flags_int.control_xfr) { 2773 2774 if (xfer->flags_int.control_hdr) { 2775 2776 err = musbotg_standard_done_sub(xfer); 2777 } 2778 xfer->aframes = 1; 2779 2780 if (xfer->td_transfer_cache == NULL) { 2781 goto done; 2782 } 2783 } 2784 while (xfer->aframes != xfer->nframes) { 2785 2786 err = musbotg_standard_done_sub(xfer); 2787 xfer->aframes++; 2788 2789 if (xfer->td_transfer_cache == NULL) { 2790 goto done; 2791 } 2792 } 2793 2794 if (xfer->flags_int.control_xfr && 2795 !xfer->flags_int.control_act) { 2796 2797 err = musbotg_standard_done_sub(xfer); 2798 } 2799 done: 2800 musbotg_device_done(xfer, err); 2801 } 2802 2803 /*------------------------------------------------------------------------* 2804 * musbotg_device_done 2805 * 2806 * NOTE: this function can be called more than one time on the 2807 * same USB transfer! 2808 *------------------------------------------------------------------------*/ 2809 static void 2810 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error) 2811 { 2812 struct musbotg_td *td; 2813 struct musbotg_softc *sc; 2814 2815 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2816 2817 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n", 2818 xfer, xfer->endpoint, error); 2819 2820 DPRINTFN(14, "disabled interrupts on endpoint\n"); 2821 2822 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2823 td = xfer->td_transfer_cache; 2824 2825 if (td && (td->channel != -1)) 2826 musbotg_channel_free(sc, td); 2827 2828 /* dequeue transfer and start next transfer */ 2829 usbd_transfer_done(xfer, error); 2830 } 2831 2832 static void 2833 musbotg_xfer_stall(struct usb_xfer *xfer) 2834 { 2835 musbotg_device_done(xfer, USB_ERR_STALLED); 2836 } 2837 2838 static void 2839 musbotg_set_stall(struct usb_device *udev, 2840 struct usb_endpoint *ep, uint8_t *did_stall) 2841 { 2842 struct musbotg_softc *sc; 2843 uint8_t ep_no; 2844 2845 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2846 2847 DPRINTFN(4, "endpoint=%p\n", ep); 2848 2849 /* set FORCESTALL */ 2850 sc = MUSBOTG_BUS2SC(udev->bus); 2851 2852 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 2853 2854 /* select endpoint */ 2855 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2856 2857 if (ep->edesc->bEndpointAddress & UE_DIR_IN) { 2858 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2859 MUSB2_MASK_CSRL_TXSENDSTALL); 2860 } else { 2861 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2862 MUSB2_MASK_CSRL_RXSENDSTALL); 2863 } 2864 } 2865 2866 static void 2867 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 2868 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 2869 { 2870 uint16_t mps; 2871 uint16_t temp; 2872 uint8_t csr; 2873 2874 if (ep_type == UE_CONTROL) { 2875 /* clearing stall is not needed */ 2876 return; 2877 } 2878 /* select endpoint */ 2879 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2880 2881 /* compute max frame size */ 2882 mps = wMaxPacket & 0x7FF; 2883 switch ((wMaxPacket >> 11) & 3) { 2884 case 1: 2885 mps *= 2; 2886 break; 2887 case 2: 2888 mps *= 3; 2889 break; 2890 default: 2891 break; 2892 } 2893 2894 if (ep_dir == UE_DIR_IN) { 2895 2896 temp = 0; 2897 2898 /* Configure endpoint */ 2899 switch (ep_type) { 2900 case UE_INTERRUPT: 2901 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2902 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2903 MUSB2_MASK_CSRH_TXMODE | temp); 2904 break; 2905 case UE_ISOCHRONOUS: 2906 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2907 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2908 MUSB2_MASK_CSRH_TXMODE | 2909 MUSB2_MASK_CSRH_TXISO | temp); 2910 break; 2911 case UE_BULK: 2912 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2913 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2914 MUSB2_MASK_CSRH_TXMODE | temp); 2915 break; 2916 default: 2917 break; 2918 } 2919 2920 /* Need to flush twice in case of double bufring */ 2921 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2922 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2923 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2924 MUSB2_MASK_CSRL_TXFFLUSH); 2925 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2926 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2927 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2928 MUSB2_MASK_CSRL_TXFFLUSH); 2929 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2930 } 2931 } 2932 /* reset data toggle */ 2933 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2934 MUSB2_MASK_CSRL_TXDT_CLR); 2935 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2936 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2937 2938 /* set double/single buffering */ 2939 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 2940 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 2941 max_in_frame_size / 2)) { 2942 /* double buffer */ 2943 temp &= ~(1 << ep_no); 2944 } else { 2945 /* single buffer */ 2946 temp |= (1 << ep_no); 2947 } 2948 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 2949 2950 /* clear sent stall */ 2951 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 2952 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2953 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2954 } 2955 } else { 2956 2957 temp = 0; 2958 2959 /* Configure endpoint */ 2960 switch (ep_type) { 2961 case UE_INTERRUPT: 2962 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2963 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2964 MUSB2_MASK_CSRH_RXNYET | temp); 2965 break; 2966 case UE_ISOCHRONOUS: 2967 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2968 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2969 MUSB2_MASK_CSRH_RXNYET | 2970 MUSB2_MASK_CSRH_RXISO | temp); 2971 break; 2972 case UE_BULK: 2973 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2974 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 2975 break; 2976 default: 2977 break; 2978 } 2979 2980 /* Need to flush twice in case of double bufring */ 2981 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2982 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2983 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2984 MUSB2_MASK_CSRL_RXFFLUSH); 2985 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2986 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2987 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2988 MUSB2_MASK_CSRL_RXFFLUSH); 2989 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2990 } 2991 } 2992 /* reset data toggle */ 2993 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2994 MUSB2_MASK_CSRL_RXDT_CLR); 2995 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 2996 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2997 2998 /* set double/single buffering */ 2999 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 3000 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 3001 max_out_frame_size / 2)) { 3002 /* double buffer */ 3003 temp &= ~(1 << ep_no); 3004 } else { 3005 /* single buffer */ 3006 temp |= (1 << ep_no); 3007 } 3008 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 3009 3010 /* clear sent stall */ 3011 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 3012 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 3013 } 3014 } 3015 } 3016 3017 static void 3018 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3019 { 3020 struct musbotg_softc *sc; 3021 struct usb_endpoint_descriptor *ed; 3022 3023 DPRINTFN(4, "endpoint=%p\n", ep); 3024 3025 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3026 3027 /* check mode */ 3028 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3029 /* not supported */ 3030 return; 3031 } 3032 /* get softc */ 3033 sc = MUSBOTG_BUS2SC(udev->bus); 3034 3035 /* get endpoint descriptor */ 3036 ed = ep->edesc; 3037 3038 /* reset endpoint */ 3039 musbotg_clear_stall_sub(sc, 3040 UGETW(ed->wMaxPacketSize), 3041 (ed->bEndpointAddress & UE_ADDR), 3042 (ed->bmAttributes & UE_XFERTYPE), 3043 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3044 } 3045 3046 usb_error_t 3047 musbotg_init(struct musbotg_softc *sc) 3048 { 3049 struct usb_hw_ep_profile *pf; 3050 uint16_t offset; 3051 uint8_t nrx; 3052 uint8_t ntx; 3053 uint8_t temp; 3054 uint8_t fsize; 3055 uint8_t frx; 3056 uint8_t ftx; 3057 uint8_t dynfifo; 3058 3059 DPRINTFN(1, "start\n"); 3060 3061 /* set up the bus structure */ 3062 sc->sc_bus.usbrev = USB_REV_2_0; 3063 sc->sc_bus.methods = &musbotg_bus_methods; 3064 3065 USB_BUS_LOCK(&sc->sc_bus); 3066 3067 /* turn on clocks */ 3068 3069 if (sc->sc_clocks_on) { 3070 (sc->sc_clocks_on) (sc->sc_clocks_arg); 3071 } 3072 3073 /* wait a little for things to stabilise */ 3074 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 3075 3076 /* disable all interrupts */ 3077 3078 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3079 DPRINTF("pre-DEVCTL=0x%02x\n", temp); 3080 3081 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3082 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3083 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3084 3085 /* disable pullup */ 3086 3087 musbotg_pull_common(sc, 0); 3088 3089 /* wait a little bit (10ms) */ 3090 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3091 3092 3093 /* disable double packet buffering */ 3094 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 3095 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 3096 3097 /* enable HighSpeed and ISO Update flags */ 3098 3099 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 3100 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 3101 3102 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 3103 /* clear Session bit, if set */ 3104 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3105 temp &= ~MUSB2_MASK_SESS; 3106 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3107 } else { 3108 /* Enter session for Host mode */ 3109 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3110 temp |= MUSB2_MASK_SESS; 3111 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3112 } 3113 3114 /* wait a little for things to stabilise */ 3115 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 3116 3117 DPRINTF("DEVCTL=0x%02x\n", temp); 3118 3119 /* disable testmode */ 3120 3121 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 3122 3123 /* set default value */ 3124 3125 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 3126 3127 /* select endpoint index 0 */ 3128 3129 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 3130 3131 /* read out number of endpoints */ 3132 3133 nrx = 3134 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 3135 3136 ntx = 3137 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 3138 3139 /* these numbers exclude the control endpoint */ 3140 3141 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 3142 3143 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 3144 if (sc->sc_ep_max == 0) { 3145 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 3146 } 3147 /* read out configuration data */ 3148 3149 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 3150 3151 DPRINTFN(2, "Config Data: 0x%02x\n", 3152 sc->sc_conf_data); 3153 3154 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 3155 3156 if (dynfifo) { 3157 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, " 3158 "assuming 16Kbytes of FIFO RAM\n"); 3159 } 3160 3161 DPRINTFN(2, "HW version: 0x%04x\n", 3162 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 3163 3164 /* initialise endpoint profiles */ 3165 3166 offset = 0; 3167 3168 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 3169 pf = sc->sc_hw_ep_profile + temp; 3170 3171 /* select endpoint */ 3172 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 3173 3174 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 3175 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16; 3176 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 3177 3178 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 3179 temp, ftx, frx, dynfifo); 3180 3181 if (dynfifo) { 3182 if (frx && (temp <= nrx)) { 3183 if (temp == 1) { 3184 frx = 12; /* 4K */ 3185 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 3186 MUSB2_VAL_FIFOSZ_4096 | 3187 MUSB2_MASK_FIFODB); 3188 } else if (temp < 8) { 3189 frx = 10; /* 1K */ 3190 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 3191 MUSB2_VAL_FIFOSZ_512 | 3192 MUSB2_MASK_FIFODB); 3193 } else { 3194 frx = 7; /* 128 bytes */ 3195 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 3196 MUSB2_VAL_FIFOSZ_128); 3197 } 3198 3199 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD, 3200 offset >> 3); 3201 3202 offset += (1 << frx); 3203 } 3204 if (ftx && (temp <= ntx)) { 3205 if (temp == 1) { 3206 ftx = 12; /* 4K */ 3207 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 3208 MUSB2_VAL_FIFOSZ_4096 | 3209 MUSB2_MASK_FIFODB); 3210 } else if (temp < 8) { 3211 ftx = 10; /* 1K */ 3212 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 3213 MUSB2_VAL_FIFOSZ_512 | 3214 MUSB2_MASK_FIFODB); 3215 } else { 3216 ftx = 7; /* 128 bytes */ 3217 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 3218 MUSB2_VAL_FIFOSZ_128); 3219 } 3220 3221 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD, 3222 offset >> 3); 3223 3224 offset += (1 << ftx); 3225 } 3226 } 3227 3228 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 3229 pf->max_in_frame_size = 1 << ftx; 3230 pf->max_out_frame_size = 1 << frx; 3231 pf->is_simplex = 0; /* duplex */ 3232 pf->support_multi_buffer = 1; 3233 pf->support_bulk = 1; 3234 pf->support_interrupt = 1; 3235 pf->support_isochronous = 1; 3236 pf->support_in = 1; 3237 pf->support_out = 1; 3238 } else if (frx && (temp <= nrx)) { 3239 pf->max_out_frame_size = 1 << frx; 3240 pf->max_in_frame_size = 0; 3241 pf->is_simplex = 1; /* simplex */ 3242 pf->support_multi_buffer = 1; 3243 pf->support_bulk = 1; 3244 pf->support_interrupt = 1; 3245 pf->support_isochronous = 1; 3246 pf->support_out = 1; 3247 } else if (ftx && (temp <= ntx)) { 3248 pf->max_in_frame_size = 1 << ftx; 3249 pf->max_out_frame_size = 0; 3250 pf->is_simplex = 1; /* simplex */ 3251 pf->support_multi_buffer = 1; 3252 pf->support_bulk = 1; 3253 pf->support_interrupt = 1; 3254 pf->support_isochronous = 1; 3255 pf->support_in = 1; 3256 } 3257 } 3258 3259 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset); 3260 3261 /* turn on default interrupts */ 3262 3263 if (sc->sc_mode == MUSB2_HOST_MODE) 3264 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff); 3265 else 3266 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 3267 MUSB2_MASK_IRESET); 3268 3269 musbotg_clocks_off(sc); 3270 3271 USB_BUS_UNLOCK(&sc->sc_bus); 3272 3273 /* catch any lost interrupts */ 3274 3275 musbotg_do_poll(&sc->sc_bus); 3276 3277 return (0); /* success */ 3278 } 3279 3280 void 3281 musbotg_uninit(struct musbotg_softc *sc) 3282 { 3283 USB_BUS_LOCK(&sc->sc_bus); 3284 3285 /* disable all interrupts */ 3286 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3287 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3288 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3289 3290 sc->sc_flags.port_powered = 0; 3291 sc->sc_flags.status_vbus = 0; 3292 sc->sc_flags.status_bus_reset = 0; 3293 sc->sc_flags.status_suspend = 0; 3294 sc->sc_flags.change_suspend = 0; 3295 sc->sc_flags.change_connect = 1; 3296 3297 musbotg_pull_down(sc); 3298 musbotg_clocks_off(sc); 3299 USB_BUS_UNLOCK(&sc->sc_bus); 3300 } 3301 3302 static void 3303 musbotg_do_poll(struct usb_bus *bus) 3304 { 3305 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 3306 3307 USB_BUS_LOCK(&sc->sc_bus); 3308 musbotg_interrupt_poll(sc); 3309 USB_BUS_UNLOCK(&sc->sc_bus); 3310 } 3311 3312 /*------------------------------------------------------------------------* 3313 * musbotg bulk support 3314 *------------------------------------------------------------------------*/ 3315 static void 3316 musbotg_device_bulk_open(struct usb_xfer *xfer) 3317 { 3318 return; 3319 } 3320 3321 static void 3322 musbotg_device_bulk_close(struct usb_xfer *xfer) 3323 { 3324 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3325 } 3326 3327 static void 3328 musbotg_device_bulk_enter(struct usb_xfer *xfer) 3329 { 3330 return; 3331 } 3332 3333 static void 3334 musbotg_device_bulk_start(struct usb_xfer *xfer) 3335 { 3336 /* setup TDs */ 3337 musbotg_setup_standard_chain(xfer); 3338 musbotg_start_standard_chain(xfer); 3339 } 3340 3341 static const struct usb_pipe_methods musbotg_device_bulk_methods = 3342 { 3343 .open = musbotg_device_bulk_open, 3344 .close = musbotg_device_bulk_close, 3345 .enter = musbotg_device_bulk_enter, 3346 .start = musbotg_device_bulk_start, 3347 }; 3348 3349 /*------------------------------------------------------------------------* 3350 * musbotg control support 3351 *------------------------------------------------------------------------*/ 3352 static void 3353 musbotg_device_ctrl_open(struct usb_xfer *xfer) 3354 { 3355 return; 3356 } 3357 3358 static void 3359 musbotg_device_ctrl_close(struct usb_xfer *xfer) 3360 { 3361 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3362 } 3363 3364 static void 3365 musbotg_device_ctrl_enter(struct usb_xfer *xfer) 3366 { 3367 return; 3368 } 3369 3370 static void 3371 musbotg_device_ctrl_start(struct usb_xfer *xfer) 3372 { 3373 /* setup TDs */ 3374 musbotg_setup_standard_chain(xfer); 3375 musbotg_start_standard_chain(xfer); 3376 } 3377 3378 static const struct usb_pipe_methods musbotg_device_ctrl_methods = 3379 { 3380 .open = musbotg_device_ctrl_open, 3381 .close = musbotg_device_ctrl_close, 3382 .enter = musbotg_device_ctrl_enter, 3383 .start = musbotg_device_ctrl_start, 3384 }; 3385 3386 /*------------------------------------------------------------------------* 3387 * musbotg interrupt support 3388 *------------------------------------------------------------------------*/ 3389 static void 3390 musbotg_device_intr_open(struct usb_xfer *xfer) 3391 { 3392 return; 3393 } 3394 3395 static void 3396 musbotg_device_intr_close(struct usb_xfer *xfer) 3397 { 3398 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3399 } 3400 3401 static void 3402 musbotg_device_intr_enter(struct usb_xfer *xfer) 3403 { 3404 return; 3405 } 3406 3407 static void 3408 musbotg_device_intr_start(struct usb_xfer *xfer) 3409 { 3410 /* setup TDs */ 3411 musbotg_setup_standard_chain(xfer); 3412 musbotg_start_standard_chain(xfer); 3413 } 3414 3415 static const struct usb_pipe_methods musbotg_device_intr_methods = 3416 { 3417 .open = musbotg_device_intr_open, 3418 .close = musbotg_device_intr_close, 3419 .enter = musbotg_device_intr_enter, 3420 .start = musbotg_device_intr_start, 3421 }; 3422 3423 /*------------------------------------------------------------------------* 3424 * musbotg full speed isochronous support 3425 *------------------------------------------------------------------------*/ 3426 static void 3427 musbotg_device_isoc_open(struct usb_xfer *xfer) 3428 { 3429 return; 3430 } 3431 3432 static void 3433 musbotg_device_isoc_close(struct usb_xfer *xfer) 3434 { 3435 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3436 } 3437 3438 static void 3439 musbotg_device_isoc_enter(struct usb_xfer *xfer) 3440 { 3441 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 3442 uint32_t temp; 3443 uint32_t nframes; 3444 uint32_t fs_frames; 3445 3446 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 3447 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3448 3449 /* get the current frame index */ 3450 3451 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 3452 3453 /* 3454 * check if the frame index is within the window where the frames 3455 * will be inserted 3456 */ 3457 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME; 3458 3459 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 3460 fs_frames = (xfer->nframes + 7) / 8; 3461 } else { 3462 fs_frames = xfer->nframes; 3463 } 3464 3465 if ((xfer->endpoint->is_synced == 0) || 3466 (temp < fs_frames)) { 3467 /* 3468 * If there is data underflow or the pipe queue is 3469 * empty we schedule the transfer a few frames ahead 3470 * of the current frame position. Else two isochronous 3471 * transfers might overlap. 3472 */ 3473 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 3474 xfer->endpoint->is_synced = 1; 3475 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next); 3476 } 3477 /* 3478 * compute how many milliseconds the insertion is ahead of the 3479 * current frame position: 3480 */ 3481 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME; 3482 3483 /* 3484 * pre-compute when the isochronous transfer will be finished: 3485 */ 3486 xfer->isoc_time_complete = 3487 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 3488 fs_frames; 3489 3490 /* compute frame number for next insertion */ 3491 xfer->endpoint->isoc_next += fs_frames; 3492 3493 /* setup TDs */ 3494 musbotg_setup_standard_chain(xfer); 3495 } 3496 3497 static void 3498 musbotg_device_isoc_start(struct usb_xfer *xfer) 3499 { 3500 /* start TD chain */ 3501 musbotg_start_standard_chain(xfer); 3502 } 3503 3504 static const struct usb_pipe_methods musbotg_device_isoc_methods = 3505 { 3506 .open = musbotg_device_isoc_open, 3507 .close = musbotg_device_isoc_close, 3508 .enter = musbotg_device_isoc_enter, 3509 .start = musbotg_device_isoc_start, 3510 }; 3511 3512 /*------------------------------------------------------------------------* 3513 * musbotg root control support 3514 *------------------------------------------------------------------------* 3515 * Simulate a hardware HUB by handling all the necessary requests. 3516 *------------------------------------------------------------------------*/ 3517 3518 static const struct usb_device_descriptor musbotg_devd = { 3519 .bLength = sizeof(struct usb_device_descriptor), 3520 .bDescriptorType = UDESC_DEVICE, 3521 .bcdUSB = {0x00, 0x02}, 3522 .bDeviceClass = UDCLASS_HUB, 3523 .bDeviceSubClass = UDSUBCLASS_HUB, 3524 .bDeviceProtocol = UDPROTO_HSHUBSTT, 3525 .bMaxPacketSize = 64, 3526 .bcdDevice = {0x00, 0x01}, 3527 .iManufacturer = 1, 3528 .iProduct = 2, 3529 .bNumConfigurations = 1, 3530 }; 3531 3532 static const struct usb_device_qualifier musbotg_odevd = { 3533 .bLength = sizeof(struct usb_device_qualifier), 3534 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 3535 .bcdUSB = {0x00, 0x02}, 3536 .bDeviceClass = UDCLASS_HUB, 3537 .bDeviceSubClass = UDSUBCLASS_HUB, 3538 .bDeviceProtocol = UDPROTO_FSHUB, 3539 .bMaxPacketSize0 = 0, 3540 .bNumConfigurations = 0, 3541 }; 3542 3543 static const struct musbotg_config_desc musbotg_confd = { 3544 .confd = { 3545 .bLength = sizeof(struct usb_config_descriptor), 3546 .bDescriptorType = UDESC_CONFIG, 3547 .wTotalLength[0] = sizeof(musbotg_confd), 3548 .bNumInterface = 1, 3549 .bConfigurationValue = 1, 3550 .iConfiguration = 0, 3551 .bmAttributes = UC_SELF_POWERED, 3552 .bMaxPower = 0, 3553 }, 3554 .ifcd = { 3555 .bLength = sizeof(struct usb_interface_descriptor), 3556 .bDescriptorType = UDESC_INTERFACE, 3557 .bNumEndpoints = 1, 3558 .bInterfaceClass = UICLASS_HUB, 3559 .bInterfaceSubClass = UISUBCLASS_HUB, 3560 .bInterfaceProtocol = 0, 3561 }, 3562 .endpd = { 3563 .bLength = sizeof(struct usb_endpoint_descriptor), 3564 .bDescriptorType = UDESC_ENDPOINT, 3565 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 3566 .bmAttributes = UE_INTERRUPT, 3567 .wMaxPacketSize[0] = 8, 3568 .bInterval = 255, 3569 }, 3570 }; 3571 3572 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3573 3574 static const struct usb_hub_descriptor_min musbotg_hubd = { 3575 .bDescLength = sizeof(musbotg_hubd), 3576 .bDescriptorType = UDESC_HUB, 3577 .bNbrPorts = 1, 3578 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 3579 .bPwrOn2PwrGood = 50, 3580 .bHubContrCurrent = 0, 3581 .DeviceRemovable = {0}, /* port is removable */ 3582 }; 3583 3584 #define STRING_VENDOR \ 3585 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s" 3586 3587 #define STRING_PRODUCT \ 3588 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 3589 3590 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 3591 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 3592 3593 static usb_error_t 3594 musbotg_roothub_exec(struct usb_device *udev, 3595 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3596 { 3597 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 3598 const void *ptr; 3599 uint16_t len; 3600 uint16_t value; 3601 uint16_t index; 3602 uint8_t reg; 3603 usb_error_t err; 3604 3605 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3606 3607 /* buffer reset */ 3608 ptr = (const void *)&sc->sc_hub_temp; 3609 len = 0; 3610 err = 0; 3611 3612 value = UGETW(req->wValue); 3613 index = UGETW(req->wIndex); 3614 3615 /* demultiplex the control request */ 3616 3617 switch (req->bmRequestType) { 3618 case UT_READ_DEVICE: 3619 switch (req->bRequest) { 3620 case UR_GET_DESCRIPTOR: 3621 goto tr_handle_get_descriptor; 3622 case UR_GET_CONFIG: 3623 goto tr_handle_get_config; 3624 case UR_GET_STATUS: 3625 goto tr_handle_get_status; 3626 default: 3627 goto tr_stalled; 3628 } 3629 break; 3630 3631 case UT_WRITE_DEVICE: 3632 switch (req->bRequest) { 3633 case UR_SET_ADDRESS: 3634 goto tr_handle_set_address; 3635 case UR_SET_CONFIG: 3636 goto tr_handle_set_config; 3637 case UR_CLEAR_FEATURE: 3638 goto tr_valid; /* nop */ 3639 case UR_SET_DESCRIPTOR: 3640 goto tr_valid; /* nop */ 3641 case UR_SET_FEATURE: 3642 default: 3643 goto tr_stalled; 3644 } 3645 break; 3646 3647 case UT_WRITE_ENDPOINT: 3648 switch (req->bRequest) { 3649 case UR_CLEAR_FEATURE: 3650 switch (UGETW(req->wValue)) { 3651 case UF_ENDPOINT_HALT: 3652 goto tr_handle_clear_halt; 3653 case UF_DEVICE_REMOTE_WAKEUP: 3654 goto tr_handle_clear_wakeup; 3655 default: 3656 goto tr_stalled; 3657 } 3658 break; 3659 case UR_SET_FEATURE: 3660 switch (UGETW(req->wValue)) { 3661 case UF_ENDPOINT_HALT: 3662 goto tr_handle_set_halt; 3663 case UF_DEVICE_REMOTE_WAKEUP: 3664 goto tr_handle_set_wakeup; 3665 default: 3666 goto tr_stalled; 3667 } 3668 break; 3669 case UR_SYNCH_FRAME: 3670 goto tr_valid; /* nop */ 3671 default: 3672 goto tr_stalled; 3673 } 3674 break; 3675 3676 case UT_READ_ENDPOINT: 3677 switch (req->bRequest) { 3678 case UR_GET_STATUS: 3679 goto tr_handle_get_ep_status; 3680 default: 3681 goto tr_stalled; 3682 } 3683 break; 3684 3685 case UT_WRITE_INTERFACE: 3686 switch (req->bRequest) { 3687 case UR_SET_INTERFACE: 3688 goto tr_handle_set_interface; 3689 case UR_CLEAR_FEATURE: 3690 goto tr_valid; /* nop */ 3691 case UR_SET_FEATURE: 3692 default: 3693 goto tr_stalled; 3694 } 3695 break; 3696 3697 case UT_READ_INTERFACE: 3698 switch (req->bRequest) { 3699 case UR_GET_INTERFACE: 3700 goto tr_handle_get_interface; 3701 case UR_GET_STATUS: 3702 goto tr_handle_get_iface_status; 3703 default: 3704 goto tr_stalled; 3705 } 3706 break; 3707 3708 case UT_WRITE_CLASS_INTERFACE: 3709 case UT_WRITE_VENDOR_INTERFACE: 3710 /* XXX forward */ 3711 break; 3712 3713 case UT_READ_CLASS_INTERFACE: 3714 case UT_READ_VENDOR_INTERFACE: 3715 /* XXX forward */ 3716 break; 3717 3718 case UT_WRITE_CLASS_DEVICE: 3719 switch (req->bRequest) { 3720 case UR_CLEAR_FEATURE: 3721 goto tr_valid; 3722 case UR_SET_DESCRIPTOR: 3723 case UR_SET_FEATURE: 3724 break; 3725 default: 3726 goto tr_stalled; 3727 } 3728 break; 3729 3730 case UT_WRITE_CLASS_OTHER: 3731 switch (req->bRequest) { 3732 case UR_CLEAR_FEATURE: 3733 goto tr_handle_clear_port_feature; 3734 case UR_SET_FEATURE: 3735 goto tr_handle_set_port_feature; 3736 case UR_CLEAR_TT_BUFFER: 3737 case UR_RESET_TT: 3738 case UR_STOP_TT: 3739 goto tr_valid; 3740 3741 default: 3742 goto tr_stalled; 3743 } 3744 break; 3745 3746 case UT_READ_CLASS_OTHER: 3747 switch (req->bRequest) { 3748 case UR_GET_TT_STATE: 3749 goto tr_handle_get_tt_state; 3750 case UR_GET_STATUS: 3751 goto tr_handle_get_port_status; 3752 default: 3753 goto tr_stalled; 3754 } 3755 break; 3756 3757 case UT_READ_CLASS_DEVICE: 3758 switch (req->bRequest) { 3759 case UR_GET_DESCRIPTOR: 3760 goto tr_handle_get_class_descriptor; 3761 case UR_GET_STATUS: 3762 goto tr_handle_get_class_status; 3763 3764 default: 3765 goto tr_stalled; 3766 } 3767 break; 3768 default: 3769 goto tr_stalled; 3770 } 3771 goto tr_valid; 3772 3773 tr_handle_get_descriptor: 3774 switch (value >> 8) { 3775 case UDESC_DEVICE: 3776 if (value & 0xff) { 3777 goto tr_stalled; 3778 } 3779 len = sizeof(musbotg_devd); 3780 ptr = (const void *)&musbotg_devd; 3781 goto tr_valid; 3782 case UDESC_DEVICE_QUALIFIER: 3783 if (value & 0xff) { 3784 goto tr_stalled; 3785 } 3786 len = sizeof(musbotg_odevd); 3787 ptr = (const void *)&musbotg_odevd; 3788 goto tr_valid; 3789 case UDESC_CONFIG: 3790 if (value & 0xff) { 3791 goto tr_stalled; 3792 } 3793 len = sizeof(musbotg_confd); 3794 ptr = (const void *)&musbotg_confd; 3795 goto tr_valid; 3796 case UDESC_STRING: 3797 switch (value & 0xff) { 3798 case 0: /* Language table */ 3799 len = sizeof(usb_string_lang_en); 3800 ptr = (const void *)&usb_string_lang_en; 3801 goto tr_valid; 3802 3803 case 1: /* Vendor */ 3804 len = sizeof(musbotg_vendor); 3805 ptr = (const void *)&musbotg_vendor; 3806 goto tr_valid; 3807 3808 case 2: /* Product */ 3809 len = sizeof(musbotg_product); 3810 ptr = (const void *)&musbotg_product; 3811 goto tr_valid; 3812 default: 3813 break; 3814 } 3815 break; 3816 default: 3817 goto tr_stalled; 3818 } 3819 goto tr_stalled; 3820 3821 tr_handle_get_config: 3822 len = 1; 3823 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 3824 goto tr_valid; 3825 3826 tr_handle_get_status: 3827 len = 2; 3828 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 3829 goto tr_valid; 3830 3831 tr_handle_set_address: 3832 if (value & 0xFF00) { 3833 goto tr_stalled; 3834 } 3835 sc->sc_rt_addr = value; 3836 goto tr_valid; 3837 3838 tr_handle_set_config: 3839 if (value >= 2) { 3840 goto tr_stalled; 3841 } 3842 sc->sc_conf = value; 3843 goto tr_valid; 3844 3845 tr_handle_get_interface: 3846 len = 1; 3847 sc->sc_hub_temp.wValue[0] = 0; 3848 goto tr_valid; 3849 3850 tr_handle_get_tt_state: 3851 tr_handle_get_class_status: 3852 tr_handle_get_iface_status: 3853 tr_handle_get_ep_status: 3854 len = 2; 3855 USETW(sc->sc_hub_temp.wValue, 0); 3856 goto tr_valid; 3857 3858 tr_handle_set_halt: 3859 tr_handle_set_interface: 3860 tr_handle_set_wakeup: 3861 tr_handle_clear_wakeup: 3862 tr_handle_clear_halt: 3863 goto tr_valid; 3864 3865 tr_handle_clear_port_feature: 3866 if (index != 1) { 3867 goto tr_stalled; 3868 } 3869 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 3870 3871 switch (value) { 3872 case UHF_PORT_SUSPEND: 3873 if (sc->sc_mode == MUSB2_HOST_MODE) 3874 musbotg_wakeup_host(sc); 3875 else 3876 musbotg_wakeup_peer(sc); 3877 break; 3878 3879 case UHF_PORT_ENABLE: 3880 sc->sc_flags.port_enabled = 0; 3881 break; 3882 3883 case UHF_C_PORT_ENABLE: 3884 sc->sc_flags.change_enabled = 0; 3885 break; 3886 3887 case UHF_C_PORT_OVER_CURRENT: 3888 sc->sc_flags.change_over_current = 0; 3889 break; 3890 3891 case UHF_C_PORT_RESET: 3892 sc->sc_flags.change_reset = 0; 3893 break; 3894 3895 case UHF_PORT_TEST: 3896 case UHF_PORT_INDICATOR: 3897 /* nops */ 3898 break; 3899 3900 case UHF_PORT_POWER: 3901 sc->sc_flags.port_powered = 0; 3902 musbotg_pull_down(sc); 3903 musbotg_clocks_off(sc); 3904 break; 3905 case UHF_C_PORT_CONNECTION: 3906 sc->sc_flags.change_connect = 0; 3907 break; 3908 case UHF_C_PORT_SUSPEND: 3909 sc->sc_flags.change_suspend = 0; 3910 break; 3911 default: 3912 err = USB_ERR_IOERROR; 3913 goto done; 3914 } 3915 goto tr_valid; 3916 3917 tr_handle_set_port_feature: 3918 if (index != 1) { 3919 goto tr_stalled; 3920 } 3921 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 3922 3923 switch (value) { 3924 case UHF_PORT_ENABLE: 3925 sc->sc_flags.port_enabled = 1; 3926 break; 3927 case UHF_PORT_SUSPEND: 3928 if (sc->sc_mode == MUSB2_HOST_MODE) 3929 musbotg_suspend_host(sc); 3930 break; 3931 3932 case UHF_PORT_RESET: 3933 if (sc->sc_mode == MUSB2_HOST_MODE) { 3934 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3935 reg |= MUSB2_MASK_RESET; 3936 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3937 3938 /* Wait for 20 msec */ 3939 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5); 3940 3941 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3942 reg &= ~MUSB2_MASK_RESET; 3943 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3944 3945 /* determine line speed */ 3946 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3947 if (reg & MUSB2_MASK_HSMODE) 3948 sc->sc_flags.status_high_speed = 1; 3949 else 3950 sc->sc_flags.status_high_speed = 0; 3951 3952 sc->sc_flags.change_reset = 1; 3953 } else 3954 err = USB_ERR_IOERROR; 3955 break; 3956 3957 case UHF_PORT_TEST: 3958 case UHF_PORT_INDICATOR: 3959 /* nops */ 3960 break; 3961 case UHF_PORT_POWER: 3962 sc->sc_flags.port_powered = 1; 3963 break; 3964 default: 3965 err = USB_ERR_IOERROR; 3966 goto done; 3967 } 3968 goto tr_valid; 3969 3970 tr_handle_get_port_status: 3971 3972 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 3973 3974 if (index != 1) { 3975 goto tr_stalled; 3976 } 3977 if (sc->sc_flags.status_vbus) { 3978 musbotg_clocks_on(sc); 3979 musbotg_pull_up(sc); 3980 } else { 3981 musbotg_pull_down(sc); 3982 musbotg_clocks_off(sc); 3983 } 3984 3985 /* Select Device Side Mode */ 3986 if (sc->sc_mode == MUSB2_DEVICE_MODE) 3987 value = UPS_PORT_MODE_DEVICE; 3988 else 3989 value = 0; 3990 3991 if (sc->sc_flags.status_high_speed) { 3992 value |= UPS_HIGH_SPEED; 3993 } 3994 if (sc->sc_flags.port_powered) { 3995 value |= UPS_PORT_POWER; 3996 } 3997 if (sc->sc_flags.port_enabled) { 3998 value |= UPS_PORT_ENABLED; 3999 } 4000 4001 if (sc->sc_flags.port_over_current) 4002 value |= UPS_OVERCURRENT_INDICATOR; 4003 4004 if (sc->sc_flags.status_vbus && 4005 sc->sc_flags.status_bus_reset) { 4006 value |= UPS_CURRENT_CONNECT_STATUS; 4007 } 4008 if (sc->sc_flags.status_suspend) { 4009 value |= UPS_SUSPEND; 4010 } 4011 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4012 4013 value = 0; 4014 4015 if (sc->sc_flags.change_connect) { 4016 value |= UPS_C_CONNECT_STATUS; 4017 4018 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 4019 if (sc->sc_flags.status_vbus && 4020 sc->sc_flags.status_bus_reset) { 4021 /* reset EP0 state */ 4022 sc->sc_ep0_busy = 0; 4023 sc->sc_ep0_cmd = 0; 4024 } 4025 } 4026 } 4027 if (sc->sc_flags.change_suspend) 4028 value |= UPS_C_SUSPEND; 4029 if (sc->sc_flags.change_reset) 4030 value |= UPS_C_PORT_RESET; 4031 if (sc->sc_flags.change_over_current) 4032 value |= UPS_C_OVERCURRENT_INDICATOR; 4033 4034 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4035 len = sizeof(sc->sc_hub_temp.ps); 4036 goto tr_valid; 4037 4038 tr_handle_get_class_descriptor: 4039 if (value & 0xFF) { 4040 goto tr_stalled; 4041 } 4042 ptr = (const void *)&musbotg_hubd; 4043 len = sizeof(musbotg_hubd); 4044 goto tr_valid; 4045 4046 tr_stalled: 4047 err = USB_ERR_STALLED; 4048 tr_valid: 4049 done: 4050 *plength = len; 4051 *pptr = ptr; 4052 return (err); 4053 } 4054 4055 static void 4056 musbotg_xfer_setup(struct usb_setup_params *parm) 4057 { 4058 struct musbotg_softc *sc; 4059 struct usb_xfer *xfer; 4060 void *last_obj; 4061 uint32_t ntd; 4062 uint32_t n; 4063 uint8_t ep_no; 4064 4065 sc = MUSBOTG_BUS2SC(parm->udev->bus); 4066 xfer = parm->curr_xfer; 4067 4068 /* 4069 * NOTE: This driver does not use any of the parameters that 4070 * are computed from the following values. Just set some 4071 * reasonable dummies: 4072 */ 4073 parm->hc_max_packet_size = 0x400; 4074 parm->hc_max_frame_size = 0xc00; 4075 4076 if ((parm->methods == &musbotg_device_isoc_methods) || 4077 (parm->methods == &musbotg_device_intr_methods)) 4078 parm->hc_max_packet_count = 3; 4079 else 4080 parm->hc_max_packet_count = 1; 4081 4082 usbd_transfer_setup_sub(parm); 4083 4084 /* 4085 * compute maximum number of TDs 4086 */ 4087 if (parm->methods == &musbotg_device_ctrl_methods) { 4088 4089 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 4090 4091 } else if (parm->methods == &musbotg_device_bulk_methods) { 4092 4093 ntd = xfer->nframes + 1 /* SYNC */ ; 4094 4095 } else if (parm->methods == &musbotg_device_intr_methods) { 4096 4097 ntd = xfer->nframes + 1 /* SYNC */ ; 4098 4099 } else if (parm->methods == &musbotg_device_isoc_methods) { 4100 4101 ntd = xfer->nframes + 1 /* SYNC */ ; 4102 4103 } else { 4104 4105 ntd = 0; 4106 } 4107 4108 /* 4109 * check if "usbd_transfer_setup_sub" set an error 4110 */ 4111 if (parm->err) { 4112 return; 4113 } 4114 /* 4115 * allocate transfer descriptors 4116 */ 4117 last_obj = NULL; 4118 4119 ep_no = xfer->endpointno & UE_ADDR; 4120 4121 /* 4122 * Check for a valid endpoint profile in USB device mode: 4123 */ 4124 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4125 const struct usb_hw_ep_profile *pf; 4126 4127 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4128 4129 if (pf == NULL) { 4130 /* should not happen */ 4131 parm->err = USB_ERR_INVAL; 4132 return; 4133 } 4134 } 4135 4136 /* align data */ 4137 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4138 4139 for (n = 0; n != ntd; n++) { 4140 4141 struct musbotg_td *td; 4142 4143 if (parm->buf) { 4144 4145 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4146 4147 /* init TD */ 4148 td->max_frame_size = xfer->max_frame_size; 4149 td->reg_max_packet = xfer->max_packet_size | 4150 ((xfer->max_packet_count - 1) << 11); 4151 td->ep_no = ep_no; 4152 td->obj_next = last_obj; 4153 4154 last_obj = td; 4155 } 4156 parm->size[0] += sizeof(*td); 4157 } 4158 4159 xfer->td_start[0] = last_obj; 4160 } 4161 4162 static void 4163 musbotg_xfer_unsetup(struct usb_xfer *xfer) 4164 { 4165 return; 4166 } 4167 4168 static void 4169 musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4170 { 4171 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4172 4173 if (sc->sc_mode == MUSB2_HOST_MODE) 4174 *pus = 2000; /* microseconds */ 4175 else 4176 *pus = 0; 4177 } 4178 4179 static void 4180 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4181 struct usb_endpoint *ep) 4182 { 4183 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4184 4185 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 4186 ep, udev->address, 4187 edesc->bEndpointAddress, udev->flags.usb_mode, 4188 sc->sc_rt_addr); 4189 4190 if (udev->device_index != sc->sc_rt_addr) { 4191 switch (edesc->bmAttributes & UE_XFERTYPE) { 4192 case UE_CONTROL: 4193 ep->methods = &musbotg_device_ctrl_methods; 4194 break; 4195 case UE_INTERRUPT: 4196 ep->methods = &musbotg_device_intr_methods; 4197 break; 4198 case UE_ISOCHRONOUS: 4199 ep->methods = &musbotg_device_isoc_methods; 4200 break; 4201 case UE_BULK: 4202 ep->methods = &musbotg_device_bulk_methods; 4203 break; 4204 default: 4205 /* do nothing */ 4206 break; 4207 } 4208 } 4209 } 4210 4211 static void 4212 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4213 { 4214 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 4215 4216 switch (state) { 4217 case USB_HW_POWER_SUSPEND: 4218 musbotg_uninit(sc); 4219 break; 4220 case USB_HW_POWER_SHUTDOWN: 4221 musbotg_uninit(sc); 4222 break; 4223 case USB_HW_POWER_RESUME: 4224 musbotg_init(sc); 4225 break; 4226 default: 4227 break; 4228 } 4229 } 4230 4231 static const struct usb_bus_methods musbotg_bus_methods = 4232 { 4233 .endpoint_init = &musbotg_ep_init, 4234 .get_dma_delay = &musbotg_get_dma_delay, 4235 .xfer_setup = &musbotg_xfer_setup, 4236 .xfer_unsetup = &musbotg_xfer_unsetup, 4237 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 4238 .xfer_stall = &musbotg_xfer_stall, 4239 .set_stall = &musbotg_set_stall, 4240 .clear_stall = &musbotg_clear_stall, 4241 .roothub_exec = &musbotg_roothub_exec, 4242 .xfer_poll = &musbotg_do_poll, 4243 .set_hw_power_sleep = &musbotg_set_hw_power_sleep, 4244 }; 4245