1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Thanks to Mentor Graphics for providing a reference driver for this USB chip 31 * at their homepage. 32 */ 33 34 /* 35 * This file contains the driver for the Mentor Graphics Inventra USB 36 * 2.0 High Speed Dual-Role controller. 37 * 38 */ 39 40 #ifdef USB_GLOBAL_INCLUDE_FILE 41 #include USB_GLOBAL_INCLUDE_FILE 42 #else 43 #include <sys/stdint.h> 44 #include <sys/stddef.h> 45 #include <sys/param.h> 46 #include <sys/queue.h> 47 #include <sys/types.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/bus.h> 51 #include <sys/module.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/condvar.h> 55 #include <sys/sysctl.h> 56 #include <sys/sx.h> 57 #include <sys/unistd.h> 58 #include <sys/callout.h> 59 #include <sys/malloc.h> 60 #include <sys/priv.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 65 #define USB_DEBUG_VAR musbotgdebug 66 67 #include <dev/usb/usb_core.h> 68 #include <dev/usb/usb_debug.h> 69 #include <dev/usb/usb_busdma.h> 70 #include <dev/usb/usb_process.h> 71 #include <dev/usb/usb_transfer.h> 72 #include <dev/usb/usb_device.h> 73 #include <dev/usb/usb_hub.h> 74 #include <dev/usb/usb_util.h> 75 76 #include <dev/usb/usb_controller.h> 77 #include <dev/usb/usb_bus.h> 78 #endif /* USB_GLOBAL_INCLUDE_FILE */ 79 80 #include <dev/usb/controller/musb_otg.h> 81 82 #define MUSBOTG_INTR_ENDPT 1 83 84 #define MUSBOTG_BUS2SC(bus) \ 85 __containerof(bus, struct musbotg_softc, sc_bus) 86 87 #define MUSBOTG_PC2SC(pc) \ 88 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 89 90 #ifdef USB_DEBUG 91 static int musbotgdebug = 0; 92 93 static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 94 "USB musbotg"); 95 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RWTUN, 96 &musbotgdebug, 0, "Debug level"); 97 #endif 98 99 #define MAX_NAK_TO 16 100 101 /* prototypes */ 102 103 static const struct usb_bus_methods musbotg_bus_methods; 104 static const struct usb_pipe_methods musbotg_device_bulk_methods; 105 static const struct usb_pipe_methods musbotg_device_ctrl_methods; 106 static const struct usb_pipe_methods musbotg_device_intr_methods; 107 static const struct usb_pipe_methods musbotg_device_isoc_methods; 108 109 /* Control transfers: Device mode */ 110 static musbotg_cmd_t musbotg_dev_ctrl_setup_rx; 111 static musbotg_cmd_t musbotg_dev_ctrl_data_rx; 112 static musbotg_cmd_t musbotg_dev_ctrl_data_tx; 113 static musbotg_cmd_t musbotg_dev_ctrl_status; 114 115 /* Control transfers: Host mode */ 116 static musbotg_cmd_t musbotg_host_ctrl_setup_tx; 117 static musbotg_cmd_t musbotg_host_ctrl_data_rx; 118 static musbotg_cmd_t musbotg_host_ctrl_data_tx; 119 static musbotg_cmd_t musbotg_host_ctrl_status_rx; 120 static musbotg_cmd_t musbotg_host_ctrl_status_tx; 121 122 /* Bulk, Interrupt, Isochronous: Device mode */ 123 static musbotg_cmd_t musbotg_dev_data_rx; 124 static musbotg_cmd_t musbotg_dev_data_tx; 125 126 /* Bulk, Interrupt, Isochronous: Host mode */ 127 static musbotg_cmd_t musbotg_host_data_rx; 128 static musbotg_cmd_t musbotg_host_data_tx; 129 130 static void musbotg_device_done(struct usb_xfer *, usb_error_t); 131 static void musbotg_do_poll(struct usb_bus *); 132 static void musbotg_standard_done(struct usb_xfer *); 133 static void musbotg_interrupt_poll(struct musbotg_softc *); 134 static void musbotg_root_intr(struct musbotg_softc *); 135 static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td, uint8_t); 136 static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td); 137 static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on); 138 139 /* 140 * Here is a configuration that the chip supports. 141 */ 142 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = { 143 [0] = { 144 .max_in_frame_size = 64,/* fixed */ 145 .max_out_frame_size = 64, /* fixed */ 146 .is_simplex = 1, 147 .support_control = 1, 148 } 149 }; 150 151 static const struct musb_otg_ep_cfg musbotg_ep_default[] = { 152 { 153 .ep_end = 1, 154 .ep_fifosz_shift = 12, 155 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_4096 | MUSB2_MASK_FIFODB, 156 }, 157 { 158 .ep_end = 7, 159 .ep_fifosz_shift = 10, 160 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_512 | MUSB2_MASK_FIFODB, 161 }, 162 { 163 .ep_end = 15, 164 .ep_fifosz_shift = 7, 165 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_128, 166 }, 167 { 168 .ep_end = -1, 169 }, 170 }; 171 172 static int 173 musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td, uint8_t is_tx) 174 { 175 int ch; 176 int ep; 177 178 ep = td->ep_no; 179 180 /* In device mode each EP got its own channel */ 181 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 182 musbotg_ep_int_set(sc, ep, 1); 183 return (ep); 184 } 185 186 /* 187 * All control transactions go through EP0 188 */ 189 if (ep == 0) { 190 if (sc->sc_channel_mask & (1 << 0)) 191 return (-1); 192 sc->sc_channel_mask |= (1 << 0); 193 musbotg_ep_int_set(sc, ep, 1); 194 return (0); 195 } 196 197 for (ch = sc->sc_ep_max; ch != 0; ch--) { 198 if (sc->sc_channel_mask & (1 << ch)) 199 continue; 200 201 /* check FIFO size requirement */ 202 if (is_tx) { 203 if (td->max_frame_size > 204 sc->sc_hw_ep_profile[ch].max_in_frame_size) 205 continue; 206 } else { 207 if (td->max_frame_size > 208 sc->sc_hw_ep_profile[ch].max_out_frame_size) 209 continue; 210 } 211 sc->sc_channel_mask |= (1 << ch); 212 musbotg_ep_int_set(sc, ch, 1); 213 return (ch); 214 } 215 216 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask); 217 218 return (-1); 219 } 220 221 static void 222 musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td) 223 { 224 225 DPRINTFN(1, "ep_no=%d\n", td->channel); 226 227 if (sc->sc_mode == MUSB2_DEVICE_MODE) 228 return; 229 230 if (td == NULL) 231 return; 232 if (td->channel == -1) 233 return; 234 235 musbotg_ep_int_set(sc, td->channel, 0); 236 sc->sc_channel_mask &= ~(1 << td->channel); 237 238 td->channel = -1; 239 } 240 241 static void 242 musbotg_get_hw_ep_profile(struct usb_device *udev, 243 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 244 { 245 struct musbotg_softc *sc; 246 247 sc = MUSBOTG_BUS2SC(udev->bus); 248 249 if (ep_addr == 0) { 250 /* control endpoint */ 251 *ppf = musbotg_ep_profile; 252 } else if (ep_addr <= sc->sc_ep_max) { 253 /* other endpoints */ 254 *ppf = sc->sc_hw_ep_profile + ep_addr; 255 } else { 256 *ppf = NULL; 257 } 258 } 259 260 static void 261 musbotg_clocks_on(struct musbotg_softc *sc) 262 { 263 if (sc->sc_flags.clocks_off && 264 sc->sc_flags.port_powered) { 265 DPRINTFN(4, "\n"); 266 267 if (sc->sc_clocks_on) { 268 (sc->sc_clocks_on) (sc->sc_clocks_arg); 269 } 270 sc->sc_flags.clocks_off = 0; 271 272 /* XXX enable Transceiver */ 273 } 274 } 275 276 static void 277 musbotg_clocks_off(struct musbotg_softc *sc) 278 { 279 if (!sc->sc_flags.clocks_off) { 280 DPRINTFN(4, "\n"); 281 282 /* XXX disable Transceiver */ 283 284 if (sc->sc_clocks_off) { 285 (sc->sc_clocks_off) (sc->sc_clocks_arg); 286 } 287 sc->sc_flags.clocks_off = 1; 288 } 289 } 290 291 static void 292 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 293 { 294 uint8_t temp; 295 296 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 297 if (on) 298 temp |= MUSB2_MASK_SOFTC; 299 else 300 temp &= ~MUSB2_MASK_SOFTC; 301 302 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 303 } 304 305 static void 306 musbotg_pull_up(struct musbotg_softc *sc) 307 { 308 /* pullup D+, if possible */ 309 310 if (!sc->sc_flags.d_pulled_up && 311 sc->sc_flags.port_powered) { 312 sc->sc_flags.d_pulled_up = 1; 313 musbotg_pull_common(sc, 1); 314 } 315 } 316 317 static void 318 musbotg_pull_down(struct musbotg_softc *sc) 319 { 320 /* pulldown D+, if possible */ 321 322 if (sc->sc_flags.d_pulled_up) { 323 sc->sc_flags.d_pulled_up = 0; 324 musbotg_pull_common(sc, 0); 325 } 326 } 327 328 static void 329 musbotg_suspend_host(struct musbotg_softc *sc) 330 { 331 uint8_t temp; 332 333 if (sc->sc_flags.status_suspend) { 334 return; 335 } 336 337 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 338 temp |= MUSB2_MASK_SUSPMODE; 339 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 340 sc->sc_flags.status_suspend = 1; 341 } 342 343 static void 344 musbotg_wakeup_host(struct musbotg_softc *sc) 345 { 346 uint8_t temp; 347 348 if (!(sc->sc_flags.status_suspend)) { 349 return; 350 } 351 352 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 353 temp &= ~MUSB2_MASK_SUSPMODE; 354 temp |= MUSB2_MASK_RESUME; 355 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 356 357 /* wait 20 milliseconds */ 358 /* Wait for reset to complete. */ 359 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 360 361 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 362 temp &= ~MUSB2_MASK_RESUME; 363 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 364 365 sc->sc_flags.status_suspend = 0; 366 } 367 368 static void 369 musbotg_wakeup_peer(struct musbotg_softc *sc) 370 { 371 uint8_t temp; 372 373 if (!(sc->sc_flags.status_suspend)) { 374 return; 375 } 376 377 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 378 temp |= MUSB2_MASK_RESUME; 379 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 380 381 /* wait 8 milliseconds */ 382 /* Wait for reset to complete. */ 383 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 384 385 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 386 temp &= ~MUSB2_MASK_RESUME; 387 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 388 } 389 390 static void 391 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 392 { 393 DPRINTFN(4, "addr=%d\n", addr); 394 addr &= 0x7F; 395 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 396 } 397 398 static uint8_t 399 musbotg_dev_ctrl_setup_rx(struct musbotg_td *td) 400 { 401 struct musbotg_softc *sc; 402 struct usb_device_request req; 403 uint16_t count; 404 uint8_t csr; 405 406 /* get pointer to softc */ 407 sc = MUSBOTG_PC2SC(td->pc); 408 409 if (td->channel == -1) 410 td->channel = musbotg_channel_alloc(sc, td, 0); 411 412 /* EP0 is busy, wait */ 413 if (td->channel == -1) 414 return (1); 415 416 DPRINTFN(1, "ep_no=%d\n", td->channel); 417 418 /* select endpoint 0 */ 419 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 420 421 /* read out FIFO status */ 422 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 423 424 DPRINTFN(4, "csr=0x%02x\n", csr); 425 426 /* 427 * NOTE: If DATAEND is set we should not call the 428 * callback, hence the status stage is not complete. 429 */ 430 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 431 /* do not stall at this point */ 432 td->did_stall = 1; 433 /* wait for interrupt */ 434 DPRINTFN(1, "CSR0 DATAEND\n"); 435 goto not_complete; 436 } 437 438 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 439 /* clear SENTSTALL */ 440 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 441 /* get latest status */ 442 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 443 /* update EP0 state */ 444 sc->sc_ep0_busy = 0; 445 } 446 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 447 /* clear SETUPEND */ 448 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 449 MUSB2_MASK_CSR0L_SETUPEND_CLR); 450 /* get latest status */ 451 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 452 /* update EP0 state */ 453 sc->sc_ep0_busy = 0; 454 } 455 if (sc->sc_ep0_busy) { 456 DPRINTFN(1, "EP0 BUSY\n"); 457 goto not_complete; 458 } 459 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 460 goto not_complete; 461 } 462 /* get the packet byte count */ 463 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 464 465 /* verify data length */ 466 if (count != td->remainder) { 467 DPRINTFN(1, "Invalid SETUP packet " 468 "length, %d bytes\n", count); 469 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 470 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 471 /* don't clear stall */ 472 td->did_stall = 1; 473 goto not_complete; 474 } 475 if (count != sizeof(req)) { 476 DPRINTFN(1, "Unsupported SETUP packet " 477 "length, %d bytes\n", count); 478 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 479 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 480 /* don't clear stall */ 481 td->did_stall = 1; 482 goto not_complete; 483 } 484 /* clear did stall flag */ 485 td->did_stall = 0; 486 487 /* receive data */ 488 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 489 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 490 491 /* copy data into real buffer */ 492 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 493 494 td->offset = sizeof(req); 495 td->remainder = 0; 496 497 /* set pending command */ 498 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 499 500 /* we need set stall or dataend after this */ 501 sc->sc_ep0_busy = 1; 502 503 /* sneak peek the set address */ 504 if ((req.bmRequestType == UT_WRITE_DEVICE) && 505 (req.bRequest == UR_SET_ADDRESS)) { 506 sc->sc_dv_addr = req.wValue[0] & 0x7F; 507 } else { 508 sc->sc_dv_addr = 0xFF; 509 } 510 511 musbotg_channel_free(sc, td); 512 return (0); /* complete */ 513 514 not_complete: 515 /* abort any ongoing transfer */ 516 if (!td->did_stall) { 517 DPRINTFN(4, "stalling\n"); 518 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 519 MUSB2_MASK_CSR0L_SENDSTALL); 520 td->did_stall = 1; 521 } 522 return (1); /* not complete */ 523 } 524 525 static uint8_t 526 musbotg_host_ctrl_setup_tx(struct musbotg_td *td) 527 { 528 struct musbotg_softc *sc; 529 struct usb_device_request req; 530 uint8_t csr, csrh; 531 532 /* get pointer to softc */ 533 sc = MUSBOTG_PC2SC(td->pc); 534 535 if (td->channel == -1) 536 td->channel = musbotg_channel_alloc(sc, td, 1); 537 538 /* EP0 is busy, wait */ 539 if (td->channel == -1) 540 return (1); 541 542 DPRINTFN(1, "ep_no=%d\n", td->channel); 543 544 /* select endpoint 0 */ 545 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 546 547 /* read out FIFO status */ 548 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 549 DPRINTFN(4, "csr=0x%02x\n", csr); 550 551 /* Not ready yet yet */ 552 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 553 return (1); 554 555 /* Failed */ 556 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 557 MUSB2_MASK_CSR0L_ERROR)) 558 { 559 /* Clear status bit */ 560 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 561 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 562 td->error = 1; 563 } 564 565 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 566 DPRINTFN(1, "NAK timeout\n"); 567 568 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 569 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 570 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 571 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 572 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 573 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 574 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 575 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 576 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 577 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 578 } 579 } 580 581 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 582 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 583 584 td->error = 1; 585 } 586 587 if (td->error) { 588 musbotg_channel_free(sc, td); 589 return (0); 590 } 591 592 /* Fifo is not empty and there is no NAK timeout */ 593 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 594 return (1); 595 596 /* check if we are complete */ 597 if (td->remainder == 0) { 598 /* we are complete */ 599 musbotg_channel_free(sc, td); 600 return (0); 601 } 602 603 /* copy data into real buffer */ 604 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 605 606 /* send data */ 607 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 608 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 609 610 /* update offset and remainder */ 611 td->offset += sizeof(req); 612 td->remainder -= sizeof(req); 613 614 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 615 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 616 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 617 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 618 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 619 620 /* write command */ 621 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 622 MUSB2_MASK_CSR0L_TXPKTRDY | 623 MUSB2_MASK_CSR0L_SETUPPKT); 624 625 /* Just to be consistent, not used above */ 626 td->transaction_started = 1; 627 628 return (1); /* in progress */ 629 } 630 631 /* Control endpoint only data handling functions (RX/TX/SYNC) */ 632 633 static uint8_t 634 musbotg_dev_ctrl_data_rx(struct musbotg_td *td) 635 { 636 struct usb_page_search buf_res; 637 struct musbotg_softc *sc; 638 uint16_t count; 639 uint8_t csr; 640 uint8_t got_short; 641 642 /* get pointer to softc */ 643 sc = MUSBOTG_PC2SC(td->pc); 644 645 /* select endpoint 0 */ 646 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 647 648 /* check if a command is pending */ 649 if (sc->sc_ep0_cmd) { 650 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 651 sc->sc_ep0_cmd = 0; 652 } 653 /* read out FIFO status */ 654 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 655 656 DPRINTFN(4, "csr=0x%02x\n", csr); 657 658 got_short = 0; 659 660 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 661 MUSB2_MASK_CSR0L_SENTSTALL)) { 662 if (td->remainder == 0) { 663 /* 664 * We are actually complete and have 665 * received the next SETUP 666 */ 667 DPRINTFN(4, "faking complete\n"); 668 return (0); /* complete */ 669 } 670 /* 671 * USB Host Aborted the transfer. 672 */ 673 td->error = 1; 674 return (0); /* complete */ 675 } 676 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 677 return (1); /* not complete */ 678 } 679 /* get the packet byte count */ 680 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 681 682 /* verify the packet byte count */ 683 if (count != td->max_frame_size) { 684 if (count < td->max_frame_size) { 685 /* we have a short packet */ 686 td->short_pkt = 1; 687 got_short = 1; 688 } else { 689 /* invalid USB packet */ 690 td->error = 1; 691 return (0); /* we are complete */ 692 } 693 } 694 /* verify the packet byte count */ 695 if (count > td->remainder) { 696 /* invalid USB packet */ 697 td->error = 1; 698 return (0); /* we are complete */ 699 } 700 while (count > 0) { 701 uint32_t temp; 702 703 usbd_get_page(td->pc, td->offset, &buf_res); 704 705 /* get correct length */ 706 if (buf_res.length > count) { 707 buf_res.length = count; 708 } 709 /* check for unaligned memory address */ 710 if (USB_P2U(buf_res.buffer) & 3) { 711 temp = count & ~3; 712 713 if (temp) { 714 /* receive data 4 bytes at a time */ 715 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 716 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 717 temp / 4); 718 } 719 temp = count & 3; 720 if (temp) { 721 /* receive data 1 byte at a time */ 722 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 723 MUSB2_REG_EPFIFO(0), 724 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 725 } 726 usbd_copy_in(td->pc, td->offset, 727 sc->sc_bounce_buf, count); 728 729 /* update offset and remainder */ 730 td->offset += count; 731 td->remainder -= count; 732 break; 733 } 734 /* check if we can optimise */ 735 if (buf_res.length >= 4) { 736 /* receive data 4 bytes at a time */ 737 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 738 MUSB2_REG_EPFIFO(0), buf_res.buffer, 739 buf_res.length / 4); 740 741 temp = buf_res.length & ~3; 742 743 /* update counters */ 744 count -= temp; 745 td->offset += temp; 746 td->remainder -= temp; 747 continue; 748 } 749 /* receive data */ 750 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 751 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 752 753 /* update counters */ 754 count -= buf_res.length; 755 td->offset += buf_res.length; 756 td->remainder -= buf_res.length; 757 } 758 759 /* check if we are complete */ 760 if ((td->remainder == 0) || got_short) { 761 if (td->short_pkt) { 762 /* we are complete */ 763 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 764 return (0); 765 } 766 /* else need to receive a zero length packet */ 767 } 768 /* write command - need more data */ 769 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 770 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 771 return (1); /* not complete */ 772 } 773 774 static uint8_t 775 musbotg_dev_ctrl_data_tx(struct musbotg_td *td) 776 { 777 struct usb_page_search buf_res; 778 struct musbotg_softc *sc; 779 uint16_t count; 780 uint8_t csr; 781 782 /* get pointer to softc */ 783 sc = MUSBOTG_PC2SC(td->pc); 784 785 /* select endpoint 0 */ 786 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 787 788 /* check if a command is pending */ 789 if (sc->sc_ep0_cmd) { 790 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 791 sc->sc_ep0_cmd = 0; 792 } 793 /* read out FIFO status */ 794 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 795 796 DPRINTFN(4, "csr=0x%02x\n", csr); 797 798 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 799 MUSB2_MASK_CSR0L_SENTSTALL)) { 800 /* 801 * The current transfer was aborted 802 * by the USB Host 803 */ 804 td->error = 1; 805 return (0); /* complete */ 806 } 807 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 808 return (1); /* not complete */ 809 } 810 count = td->max_frame_size; 811 if (td->remainder < count) { 812 /* we have a short packet */ 813 td->short_pkt = 1; 814 count = td->remainder; 815 } 816 while (count > 0) { 817 uint32_t temp; 818 819 usbd_get_page(td->pc, td->offset, &buf_res); 820 821 /* get correct length */ 822 if (buf_res.length > count) { 823 buf_res.length = count; 824 } 825 /* check for unaligned memory address */ 826 if (USB_P2U(buf_res.buffer) & 3) { 827 usbd_copy_out(td->pc, td->offset, 828 sc->sc_bounce_buf, count); 829 830 temp = count & ~3; 831 832 if (temp) { 833 /* transmit data 4 bytes at a time */ 834 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 835 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 836 temp / 4); 837 } 838 temp = count & 3; 839 if (temp) { 840 /* receive data 1 byte at a time */ 841 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 842 MUSB2_REG_EPFIFO(0), 843 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 844 } 845 /* update offset and remainder */ 846 td->offset += count; 847 td->remainder -= count; 848 break; 849 } 850 /* check if we can optimise */ 851 if (buf_res.length >= 4) { 852 /* transmit data 4 bytes at a time */ 853 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 854 MUSB2_REG_EPFIFO(0), buf_res.buffer, 855 buf_res.length / 4); 856 857 temp = buf_res.length & ~3; 858 859 /* update counters */ 860 count -= temp; 861 td->offset += temp; 862 td->remainder -= temp; 863 continue; 864 } 865 /* transmit data */ 866 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 867 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 868 869 /* update counters */ 870 count -= buf_res.length; 871 td->offset += buf_res.length; 872 td->remainder -= buf_res.length; 873 } 874 875 /* check remainder */ 876 if (td->remainder == 0) { 877 if (td->short_pkt) { 878 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 879 return (0); /* complete */ 880 } 881 /* else we need to transmit a short packet */ 882 } 883 /* write command */ 884 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 885 MUSB2_MASK_CSR0L_TXPKTRDY); 886 887 return (1); /* not complete */ 888 } 889 890 static uint8_t 891 musbotg_host_ctrl_data_rx(struct musbotg_td *td) 892 { 893 struct usb_page_search buf_res; 894 struct musbotg_softc *sc; 895 uint16_t count; 896 uint8_t csr; 897 uint8_t got_short; 898 899 /* get pointer to softc */ 900 sc = MUSBOTG_PC2SC(td->pc); 901 902 if (td->channel == -1) 903 td->channel = musbotg_channel_alloc(sc, td, 0); 904 905 /* EP0 is busy, wait */ 906 if (td->channel == -1) 907 return (1); 908 909 DPRINTFN(1, "ep_no=%d\n", td->channel); 910 911 /* select endpoint 0 */ 912 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 913 914 /* read out FIFO status */ 915 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 916 917 DPRINTFN(4, "csr=0x%02x\n", csr); 918 919 got_short = 0; 920 if (!td->transaction_started) { 921 td->transaction_started = 1; 922 923 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 924 925 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 926 td->dev_addr); 927 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 928 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 929 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 930 931 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 932 MUSB2_MASK_CSR0L_REQPKT); 933 934 return (1); 935 } 936 937 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 938 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 939 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 940 941 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 942 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 943 944 td->error = 1; 945 } 946 947 /* Failed */ 948 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 949 MUSB2_MASK_CSR0L_ERROR)) 950 { 951 /* Clear status bit */ 952 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 953 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 954 td->error = 1; 955 } 956 957 if (td->error) { 958 musbotg_channel_free(sc, td); 959 return (0); /* we are complete */ 960 } 961 962 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) 963 return (1); /* not yet */ 964 965 /* get the packet byte count */ 966 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 967 968 /* verify the packet byte count */ 969 if (count != td->max_frame_size) { 970 if (count < td->max_frame_size) { 971 /* we have a short packet */ 972 td->short_pkt = 1; 973 got_short = 1; 974 } else { 975 /* invalid USB packet */ 976 td->error = 1; 977 musbotg_channel_free(sc, td); 978 return (0); /* we are complete */ 979 } 980 } 981 /* verify the packet byte count */ 982 if (count > td->remainder) { 983 /* invalid USB packet */ 984 td->error = 1; 985 musbotg_channel_free(sc, td); 986 return (0); /* we are complete */ 987 } 988 while (count > 0) { 989 uint32_t temp; 990 991 usbd_get_page(td->pc, td->offset, &buf_res); 992 993 /* get correct length */ 994 if (buf_res.length > count) { 995 buf_res.length = count; 996 } 997 /* check for unaligned memory address */ 998 if (USB_P2U(buf_res.buffer) & 3) { 999 temp = count & ~3; 1000 1001 if (temp) { 1002 /* receive data 4 bytes at a time */ 1003 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1004 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 1005 temp / 4); 1006 } 1007 temp = count & 3; 1008 if (temp) { 1009 /* receive data 1 byte at a time */ 1010 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1011 MUSB2_REG_EPFIFO(0), 1012 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 1013 } 1014 usbd_copy_in(td->pc, td->offset, 1015 sc->sc_bounce_buf, count); 1016 1017 /* update offset and remainder */ 1018 td->offset += count; 1019 td->remainder -= count; 1020 break; 1021 } 1022 /* check if we can optimise */ 1023 if (buf_res.length >= 4) { 1024 /* receive data 4 bytes at a time */ 1025 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1026 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1027 buf_res.length / 4); 1028 1029 temp = buf_res.length & ~3; 1030 1031 /* update counters */ 1032 count -= temp; 1033 td->offset += temp; 1034 td->remainder -= temp; 1035 continue; 1036 } 1037 /* receive data */ 1038 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1039 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 1040 1041 /* update counters */ 1042 count -= buf_res.length; 1043 td->offset += buf_res.length; 1044 td->remainder -= buf_res.length; 1045 } 1046 1047 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY; 1048 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1049 1050 /* check if we are complete */ 1051 if ((td->remainder == 0) || got_short) { 1052 if (td->short_pkt) { 1053 /* we are complete */ 1054 1055 musbotg_channel_free(sc, td); 1056 return (0); 1057 } 1058 /* else need to receive a zero length packet */ 1059 } 1060 1061 td->transaction_started = 1; 1062 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1063 MUSB2_MASK_CSR0L_REQPKT); 1064 1065 return (1); /* not complete */ 1066 } 1067 1068 static uint8_t 1069 musbotg_host_ctrl_data_tx(struct musbotg_td *td) 1070 { 1071 struct usb_page_search buf_res; 1072 struct musbotg_softc *sc; 1073 uint16_t count; 1074 uint8_t csr, csrh; 1075 1076 /* get pointer to softc */ 1077 sc = MUSBOTG_PC2SC(td->pc); 1078 1079 if (td->channel == -1) 1080 td->channel = musbotg_channel_alloc(sc, td, 1); 1081 1082 /* No free EPs */ 1083 if (td->channel == -1) 1084 return (1); 1085 1086 DPRINTFN(1, "ep_no=%d\n", td->channel); 1087 1088 /* select endpoint */ 1089 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1090 1091 /* read out FIFO status */ 1092 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1093 DPRINTFN(4, "csr=0x%02x\n", csr); 1094 1095 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1096 MUSB2_MASK_CSR0L_ERROR)) { 1097 /* clear status bits */ 1098 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1099 td->error = 1; 1100 } 1101 1102 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) { 1103 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1104 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1105 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1106 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1107 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1108 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1109 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1110 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1111 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1112 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1113 } 1114 } 1115 1116 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1117 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1118 1119 td->error = 1; 1120 } 1121 1122 if (td->error) { 1123 musbotg_channel_free(sc, td); 1124 return (0); /* complete */ 1125 } 1126 1127 /* 1128 * Wait while FIFO is empty. 1129 * Do not flush it because it will cause transactions 1130 * with size more then packet size. It might upset 1131 * some devices 1132 */ 1133 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) 1134 return (1); 1135 1136 /* Packet still being processed */ 1137 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1138 return (1); 1139 1140 if (td->transaction_started) { 1141 /* check remainder */ 1142 if (td->remainder == 0) { 1143 if (td->short_pkt) { 1144 musbotg_channel_free(sc, td); 1145 return (0); /* complete */ 1146 } 1147 /* else we need to transmit a short packet */ 1148 } 1149 1150 /* We're not complete - more transactions required */ 1151 td->transaction_started = 0; 1152 } 1153 1154 /* check for short packet */ 1155 count = td->max_frame_size; 1156 if (td->remainder < count) { 1157 /* we have a short packet */ 1158 td->short_pkt = 1; 1159 count = td->remainder; 1160 } 1161 1162 while (count > 0) { 1163 uint32_t temp; 1164 1165 usbd_get_page(td->pc, td->offset, &buf_res); 1166 1167 /* get correct length */ 1168 if (buf_res.length > count) { 1169 buf_res.length = count; 1170 } 1171 /* check for unaligned memory address */ 1172 if (USB_P2U(buf_res.buffer) & 3) { 1173 usbd_copy_out(td->pc, td->offset, 1174 sc->sc_bounce_buf, count); 1175 1176 temp = count & ~3; 1177 1178 if (temp) { 1179 /* transmit data 4 bytes at a time */ 1180 bus_space_write_multi_4(sc->sc_io_tag, 1181 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), 1182 sc->sc_bounce_buf, temp / 4); 1183 } 1184 temp = count & 3; 1185 if (temp) { 1186 /* receive data 1 byte at a time */ 1187 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1188 MUSB2_REG_EPFIFO(0), 1189 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1190 } 1191 /* update offset and remainder */ 1192 td->offset += count; 1193 td->remainder -= count; 1194 break; 1195 } 1196 /* check if we can optimise */ 1197 if (buf_res.length >= 4) { 1198 /* transmit data 4 bytes at a time */ 1199 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1200 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1201 buf_res.length / 4); 1202 1203 temp = buf_res.length & ~3; 1204 1205 /* update counters */ 1206 count -= temp; 1207 td->offset += temp; 1208 td->remainder -= temp; 1209 continue; 1210 } 1211 /* transmit data */ 1212 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1213 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1214 buf_res.length); 1215 1216 /* update counters */ 1217 count -= buf_res.length; 1218 td->offset += buf_res.length; 1219 td->remainder -= buf_res.length; 1220 } 1221 1222 /* Function address */ 1223 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1224 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1225 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1226 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1227 1228 /* TX NAK timeout */ 1229 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1230 1231 /* write command */ 1232 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1233 MUSB2_MASK_CSR0L_TXPKTRDY); 1234 1235 td->transaction_started = 1; 1236 1237 return (1); /* not complete */ 1238 } 1239 1240 static uint8_t 1241 musbotg_dev_ctrl_status(struct musbotg_td *td) 1242 { 1243 struct musbotg_softc *sc; 1244 uint8_t csr; 1245 1246 /* get pointer to softc */ 1247 sc = MUSBOTG_PC2SC(td->pc); 1248 1249 /* select endpoint 0 */ 1250 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1251 1252 if (sc->sc_ep0_busy) { 1253 sc->sc_ep0_busy = 0; 1254 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 1255 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 1256 sc->sc_ep0_cmd = 0; 1257 } 1258 /* read out FIFO status */ 1259 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1260 1261 DPRINTFN(4, "csr=0x%02x\n", csr); 1262 1263 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 1264 /* wait for interrupt */ 1265 return (1); /* not complete */ 1266 } 1267 if (sc->sc_dv_addr != 0xFF) { 1268 /* write function address */ 1269 musbotg_set_address(sc, sc->sc_dv_addr); 1270 } 1271 1272 musbotg_channel_free(sc, td); 1273 return (0); /* complete */ 1274 } 1275 1276 static uint8_t 1277 musbotg_host_ctrl_status_rx(struct musbotg_td *td) 1278 { 1279 struct musbotg_softc *sc; 1280 uint8_t csr, csrh; 1281 1282 /* get pointer to softc */ 1283 sc = MUSBOTG_PC2SC(td->pc); 1284 1285 if (td->channel == -1) 1286 td->channel = musbotg_channel_alloc(sc, td, 0); 1287 1288 /* EP0 is busy, wait */ 1289 if (td->channel == -1) 1290 return (1); 1291 1292 DPRINTFN(1, "ep_no=%d\n", td->channel); 1293 1294 /* select endpoint 0 */ 1295 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1296 1297 if (!td->transaction_started) { 1298 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 1299 td->dev_addr); 1300 1301 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 1302 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 1303 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1304 1305 /* RX NAK timeout */ 1306 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1307 1308 td->transaction_started = 1; 1309 1310 /* Disable PING */ 1311 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1312 csrh |= MUSB2_MASK_CSR0H_PING_DIS; 1313 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1314 1315 /* write command */ 1316 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1317 MUSB2_MASK_CSR0L_STATUSPKT | 1318 MUSB2_MASK_CSR0L_REQPKT); 1319 1320 return (1); /* Just started */ 1321 } 1322 1323 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1324 1325 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr); 1326 1327 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) { 1328 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1329 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 1330 musbotg_channel_free(sc, td); 1331 return (0); /* complete */ 1332 } 1333 1334 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1335 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT | 1336 MUSB2_MASK_CSR0L_REQPKT); 1337 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1338 1339 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1340 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1341 td->error = 1; 1342 } 1343 1344 /* Failed */ 1345 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1346 MUSB2_MASK_CSR0L_ERROR)) 1347 { 1348 /* Clear status bit */ 1349 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1350 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1351 td->error = 1; 1352 } 1353 1354 if (td->error) { 1355 musbotg_channel_free(sc, td); 1356 return (0); 1357 } 1358 1359 return (1); /* Not ready yet */ 1360 } 1361 1362 static uint8_t 1363 musbotg_host_ctrl_status_tx(struct musbotg_td *td) 1364 { 1365 struct musbotg_softc *sc; 1366 uint8_t csr; 1367 1368 /* get pointer to softc */ 1369 sc = MUSBOTG_PC2SC(td->pc); 1370 1371 if (td->channel == -1) 1372 td->channel = musbotg_channel_alloc(sc, td, 1); 1373 1374 /* EP0 is busy, wait */ 1375 if (td->channel == -1) 1376 return (1); 1377 1378 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started, 1379 td->dev_addr,td->haddr,td->hport, td->transfer_type); 1380 1381 /* select endpoint 0 */ 1382 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1383 1384 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1385 DPRINTFN(4, "csr=0x%02x\n", csr); 1386 1387 /* Not yet */ 1388 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1389 return (1); 1390 1391 /* Failed */ 1392 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1393 MUSB2_MASK_CSR0L_ERROR)) 1394 { 1395 /* Clear status bit */ 1396 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1397 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1398 td->error = 1; 1399 musbotg_channel_free(sc, td); 1400 return (0); /* complete */ 1401 } 1402 1403 if (td->transaction_started) { 1404 musbotg_channel_free(sc, td); 1405 return (0); /* complete */ 1406 } 1407 1408 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS); 1409 1410 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1411 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1412 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1413 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1414 1415 /* TX NAK timeout */ 1416 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1417 1418 td->transaction_started = 1; 1419 1420 /* write command */ 1421 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1422 MUSB2_MASK_CSR0L_STATUSPKT | 1423 MUSB2_MASK_CSR0L_TXPKTRDY); 1424 1425 return (1); /* wait for interrupt */ 1426 } 1427 1428 static uint8_t 1429 musbotg_dev_data_rx(struct musbotg_td *td) 1430 { 1431 struct usb_page_search buf_res; 1432 struct musbotg_softc *sc; 1433 uint16_t count; 1434 uint8_t csr; 1435 uint8_t to; 1436 uint8_t got_short; 1437 1438 to = 8; /* don't loop forever! */ 1439 got_short = 0; 1440 1441 /* get pointer to softc */ 1442 sc = MUSBOTG_PC2SC(td->pc); 1443 1444 if (td->channel == -1) 1445 td->channel = musbotg_channel_alloc(sc, td, 0); 1446 1447 /* EP0 is busy, wait */ 1448 if (td->channel == -1) 1449 return (1); 1450 1451 /* select endpoint */ 1452 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1453 1454 repeat: 1455 /* read out FIFO status */ 1456 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1457 1458 DPRINTFN(4, "csr=0x%02x\n", csr); 1459 1460 /* clear overrun */ 1461 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 1462 /* make sure we don't clear "RXPKTRDY" */ 1463 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1464 MUSB2_MASK_CSRL_RXPKTRDY); 1465 } 1466 1467 /* check status */ 1468 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) 1469 return (1); /* not complete */ 1470 1471 /* get the packet byte count */ 1472 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1473 1474 DPRINTFN(4, "count=0x%04x\n", count); 1475 1476 /* 1477 * Check for short or invalid packet: 1478 */ 1479 if (count != td->max_frame_size) { 1480 if (count < td->max_frame_size) { 1481 /* we have a short packet */ 1482 td->short_pkt = 1; 1483 got_short = 1; 1484 } else { 1485 /* invalid USB packet */ 1486 td->error = 1; 1487 musbotg_channel_free(sc, td); 1488 return (0); /* we are complete */ 1489 } 1490 } 1491 /* verify the packet byte count */ 1492 if (count > td->remainder) { 1493 /* invalid USB packet */ 1494 td->error = 1; 1495 musbotg_channel_free(sc, td); 1496 return (0); /* we are complete */ 1497 } 1498 while (count > 0) { 1499 uint32_t temp; 1500 1501 usbd_get_page(td->pc, td->offset, &buf_res); 1502 1503 /* get correct length */ 1504 if (buf_res.length > count) { 1505 buf_res.length = count; 1506 } 1507 /* check for unaligned memory address */ 1508 if (USB_P2U(buf_res.buffer) & 3) { 1509 temp = count & ~3; 1510 1511 if (temp) { 1512 /* receive data 4 bytes at a time */ 1513 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1514 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1515 temp / 4); 1516 } 1517 temp = count & 3; 1518 if (temp) { 1519 /* receive data 1 byte at a time */ 1520 bus_space_read_multi_1(sc->sc_io_tag, 1521 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1522 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1523 } 1524 usbd_copy_in(td->pc, td->offset, 1525 sc->sc_bounce_buf, count); 1526 1527 /* update offset and remainder */ 1528 td->offset += count; 1529 td->remainder -= count; 1530 break; 1531 } 1532 /* check if we can optimise */ 1533 if (buf_res.length >= 4) { 1534 /* receive data 4 bytes at a time */ 1535 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1536 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1537 buf_res.length / 4); 1538 1539 temp = buf_res.length & ~3; 1540 1541 /* update counters */ 1542 count -= temp; 1543 td->offset += temp; 1544 td->remainder -= temp; 1545 continue; 1546 } 1547 /* receive data */ 1548 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1549 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1550 buf_res.length); 1551 1552 /* update counters */ 1553 count -= buf_res.length; 1554 td->offset += buf_res.length; 1555 td->remainder -= buf_res.length; 1556 } 1557 1558 /* clear status bits */ 1559 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1560 1561 /* check if we are complete */ 1562 if ((td->remainder == 0) || got_short) { 1563 if (td->short_pkt) { 1564 /* we are complete */ 1565 musbotg_channel_free(sc, td); 1566 return (0); 1567 } 1568 /* else need to receive a zero length packet */ 1569 } 1570 if (--to) { 1571 goto repeat; 1572 } 1573 return (1); /* not complete */ 1574 } 1575 1576 static uint8_t 1577 musbotg_dev_data_tx(struct musbotg_td *td) 1578 { 1579 struct usb_page_search buf_res; 1580 struct musbotg_softc *sc; 1581 uint16_t count; 1582 uint8_t csr; 1583 uint8_t to; 1584 1585 to = 8; /* don't loop forever! */ 1586 1587 /* get pointer to softc */ 1588 sc = MUSBOTG_PC2SC(td->pc); 1589 1590 if (td->channel == -1) 1591 td->channel = musbotg_channel_alloc(sc, td, 1); 1592 1593 /* EP0 is busy, wait */ 1594 if (td->channel == -1) 1595 return (1); 1596 1597 /* select endpoint */ 1598 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1599 1600 repeat: 1601 1602 /* read out FIFO status */ 1603 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1604 1605 DPRINTFN(4, "csr=0x%02x\n", csr); 1606 1607 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 1608 MUSB2_MASK_CSRL_TXUNDERRUN)) { 1609 /* clear status bits */ 1610 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1611 } 1612 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 1613 return (1); /* not complete */ 1614 } 1615 /* check for short packet */ 1616 count = td->max_frame_size; 1617 if (td->remainder < count) { 1618 /* we have a short packet */ 1619 td->short_pkt = 1; 1620 count = td->remainder; 1621 } 1622 while (count > 0) { 1623 uint32_t temp; 1624 1625 usbd_get_page(td->pc, td->offset, &buf_res); 1626 1627 /* get correct length */ 1628 if (buf_res.length > count) { 1629 buf_res.length = count; 1630 } 1631 /* check for unaligned memory address */ 1632 if (USB_P2U(buf_res.buffer) & 3) { 1633 usbd_copy_out(td->pc, td->offset, 1634 sc->sc_bounce_buf, count); 1635 1636 temp = count & ~3; 1637 1638 if (temp) { 1639 /* transmit data 4 bytes at a time */ 1640 bus_space_write_multi_4(sc->sc_io_tag, 1641 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1642 sc->sc_bounce_buf, temp / 4); 1643 } 1644 temp = count & 3; 1645 if (temp) { 1646 /* receive data 1 byte at a time */ 1647 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1648 MUSB2_REG_EPFIFO(td->channel), 1649 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1650 } 1651 /* update offset and remainder */ 1652 td->offset += count; 1653 td->remainder -= count; 1654 break; 1655 } 1656 /* check if we can optimise */ 1657 if (buf_res.length >= 4) { 1658 /* transmit data 4 bytes at a time */ 1659 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1660 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1661 buf_res.length / 4); 1662 1663 temp = buf_res.length & ~3; 1664 1665 /* update counters */ 1666 count -= temp; 1667 td->offset += temp; 1668 td->remainder -= temp; 1669 continue; 1670 } 1671 /* transmit data */ 1672 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1673 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1674 buf_res.length); 1675 1676 /* update counters */ 1677 count -= buf_res.length; 1678 td->offset += buf_res.length; 1679 td->remainder -= buf_res.length; 1680 } 1681 1682 /* Max packet size */ 1683 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); 1684 1685 /* write command */ 1686 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1687 MUSB2_MASK_CSRL_TXPKTRDY); 1688 1689 /* check remainder */ 1690 if (td->remainder == 0) { 1691 if (td->short_pkt) { 1692 musbotg_channel_free(sc, td); 1693 return (0); /* complete */ 1694 } 1695 /* else we need to transmit a short packet */ 1696 } 1697 if (--to) { 1698 goto repeat; 1699 } 1700 return (1); /* not complete */ 1701 } 1702 1703 static uint8_t 1704 musbotg_host_data_rx(struct musbotg_td *td) 1705 { 1706 struct usb_page_search buf_res; 1707 struct musbotg_softc *sc; 1708 uint16_t count; 1709 uint8_t csr, csrh; 1710 uint8_t to; 1711 uint8_t got_short; 1712 1713 /* get pointer to softc */ 1714 sc = MUSBOTG_PC2SC(td->pc); 1715 1716 if (td->channel == -1) 1717 td->channel = musbotg_channel_alloc(sc, td, 0); 1718 1719 /* No free EPs */ 1720 if (td->channel == -1) 1721 return (1); 1722 1723 DPRINTFN(1, "ep_no=%d\n", td->channel); 1724 1725 to = 8; /* don't loop forever! */ 1726 got_short = 0; 1727 1728 /* select endpoint */ 1729 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1730 1731 repeat: 1732 /* read out FIFO status */ 1733 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1734 DPRINTFN(4, "csr=0x%02x\n", csr); 1735 1736 if (!td->transaction_started) { 1737 /* Function address */ 1738 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel), 1739 td->dev_addr); 1740 1741 /* SPLIT transaction */ 1742 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel), 1743 td->haddr); 1744 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel), 1745 td->hport); 1746 1747 /* RX NAK timeout */ 1748 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) 1749 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0); 1750 else 1751 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1752 1753 /* Protocol, speed, device endpoint */ 1754 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1755 1756 /* Max packet size */ 1757 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet); 1758 1759 /* Data Toggle */ 1760 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1761 DPRINTFN(4, "csrh=0x%02x\n", csrh); 1762 1763 csrh |= MUSB2_MASK_CSRH_RXDT_WREN; 1764 if (td->toggle) 1765 csrh |= MUSB2_MASK_CSRH_RXDT_VAL; 1766 else 1767 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1768 1769 /* Set data toggle */ 1770 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1771 1772 /* write command */ 1773 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1774 MUSB2_MASK_CSRL_RXREQPKT); 1775 1776 td->transaction_started = 1; 1777 return (1); 1778 } 1779 1780 /* clear NAK timeout */ 1781 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1782 DPRINTFN(4, "NAK Timeout\n"); 1783 if (csr & MUSB2_MASK_CSRL_RXREQPKT) { 1784 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1785 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1786 1787 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1788 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1789 } 1790 1791 td->error = 1; 1792 } 1793 1794 if (csr & MUSB2_MASK_CSRL_RXERROR) { 1795 DPRINTFN(4, "RXERROR\n"); 1796 td->error = 1; 1797 } 1798 1799 if (csr & MUSB2_MASK_CSRL_RXSTALL) { 1800 DPRINTFN(4, "RXSTALL\n"); 1801 td->error = 1; 1802 } 1803 1804 if (td->error) { 1805 musbotg_channel_free(sc, td); 1806 return (0); /* we are complete */ 1807 } 1808 1809 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 1810 /* No data available yet */ 1811 return (1); 1812 } 1813 1814 td->toggle ^= 1; 1815 /* get the packet byte count */ 1816 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1817 DPRINTFN(4, "count=0x%04x\n", count); 1818 1819 /* 1820 * Check for short or invalid packet: 1821 */ 1822 if (count != td->max_frame_size) { 1823 if (count < td->max_frame_size) { 1824 /* we have a short packet */ 1825 td->short_pkt = 1; 1826 got_short = 1; 1827 } else { 1828 /* invalid USB packet */ 1829 td->error = 1; 1830 musbotg_channel_free(sc, td); 1831 return (0); /* we are complete */ 1832 } 1833 } 1834 1835 /* verify the packet byte count */ 1836 if (count > td->remainder) { 1837 /* invalid USB packet */ 1838 td->error = 1; 1839 musbotg_channel_free(sc, td); 1840 return (0); /* we are complete */ 1841 } 1842 1843 while (count > 0) { 1844 uint32_t temp; 1845 1846 usbd_get_page(td->pc, td->offset, &buf_res); 1847 1848 /* get correct length */ 1849 if (buf_res.length > count) { 1850 buf_res.length = count; 1851 } 1852 /* check for unaligned memory address */ 1853 if (USB_P2U(buf_res.buffer) & 3) { 1854 temp = count & ~3; 1855 1856 if (temp) { 1857 /* receive data 4 bytes at a time */ 1858 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1859 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1860 temp / 4); 1861 } 1862 temp = count & 3; 1863 if (temp) { 1864 /* receive data 1 byte at a time */ 1865 bus_space_read_multi_1(sc->sc_io_tag, 1866 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1867 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1868 } 1869 usbd_copy_in(td->pc, td->offset, 1870 sc->sc_bounce_buf, count); 1871 1872 /* update offset and remainder */ 1873 td->offset += count; 1874 td->remainder -= count; 1875 break; 1876 } 1877 /* check if we can optimise */ 1878 if (buf_res.length >= 4) { 1879 /* receive data 4 bytes at a time */ 1880 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1881 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1882 buf_res.length / 4); 1883 1884 temp = buf_res.length & ~3; 1885 1886 /* update counters */ 1887 count -= temp; 1888 td->offset += temp; 1889 td->remainder -= temp; 1890 continue; 1891 } 1892 /* receive data */ 1893 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1894 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1895 buf_res.length); 1896 1897 /* update counters */ 1898 count -= buf_res.length; 1899 td->offset += buf_res.length; 1900 td->remainder -= buf_res.length; 1901 } 1902 1903 /* clear status bits */ 1904 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1905 1906 /* check if we are complete */ 1907 if ((td->remainder == 0) || got_short) { 1908 if (td->short_pkt) { 1909 /* we are complete */ 1910 musbotg_channel_free(sc, td); 1911 return (0); 1912 } 1913 /* else need to receive a zero length packet */ 1914 } 1915 1916 /* Reset transaction state and restart */ 1917 td->transaction_started = 0; 1918 1919 if (--to) 1920 goto repeat; 1921 1922 return (1); /* not complete */ 1923 } 1924 1925 static uint8_t 1926 musbotg_host_data_tx(struct musbotg_td *td) 1927 { 1928 struct usb_page_search buf_res; 1929 struct musbotg_softc *sc; 1930 uint16_t count; 1931 uint8_t csr, csrh; 1932 1933 /* get pointer to softc */ 1934 sc = MUSBOTG_PC2SC(td->pc); 1935 1936 if (td->channel == -1) 1937 td->channel = musbotg_channel_alloc(sc, td, 1); 1938 1939 /* No free EPs */ 1940 if (td->channel == -1) 1941 return (1); 1942 1943 DPRINTFN(1, "ep_no=%d\n", td->channel); 1944 1945 /* select endpoint */ 1946 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1947 1948 /* read out FIFO status */ 1949 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1950 DPRINTFN(4, "csr=0x%02x\n", csr); 1951 1952 if (csr & (MUSB2_MASK_CSRL_TXSTALLED | 1953 MUSB2_MASK_CSRL_TXERROR)) { 1954 /* clear status bits */ 1955 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1956 td->error = 1; 1957 musbotg_channel_free(sc, td); 1958 return (0); /* complete */ 1959 } 1960 1961 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 1962 /* 1963 * Flush TX FIFO before clearing NAK TO 1964 */ 1965 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1966 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1967 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1968 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1969 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1970 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1971 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1972 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1973 } 1974 } 1975 1976 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 1977 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1978 1979 td->error = 1; 1980 musbotg_channel_free(sc, td); 1981 return (0); /* complete */ 1982 } 1983 1984 /* 1985 * Wait while FIFO is empty. 1986 * Do not flush it because it will cause transactions 1987 * with size more then packet size. It might upset 1988 * some devices 1989 */ 1990 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) 1991 return (1); 1992 1993 /* Packet still being processed */ 1994 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) 1995 return (1); 1996 1997 if (td->transaction_started) { 1998 /* check remainder */ 1999 if (td->remainder == 0) { 2000 if (td->short_pkt) { 2001 musbotg_channel_free(sc, td); 2002 return (0); /* complete */ 2003 } 2004 /* else we need to transmit a short packet */ 2005 } 2006 2007 /* We're not complete - more transactions required */ 2008 td->transaction_started = 0; 2009 } 2010 2011 /* check for short packet */ 2012 count = td->max_frame_size; 2013 if (td->remainder < count) { 2014 /* we have a short packet */ 2015 td->short_pkt = 1; 2016 count = td->remainder; 2017 } 2018 2019 while (count > 0) { 2020 uint32_t temp; 2021 2022 usbd_get_page(td->pc, td->offset, &buf_res); 2023 2024 /* get correct length */ 2025 if (buf_res.length > count) { 2026 buf_res.length = count; 2027 } 2028 /* check for unaligned memory address */ 2029 if (USB_P2U(buf_res.buffer) & 3) { 2030 usbd_copy_out(td->pc, td->offset, 2031 sc->sc_bounce_buf, count); 2032 2033 temp = count & ~3; 2034 2035 if (temp) { 2036 /* transmit data 4 bytes at a time */ 2037 bus_space_write_multi_4(sc->sc_io_tag, 2038 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 2039 sc->sc_bounce_buf, temp / 4); 2040 } 2041 temp = count & 3; 2042 if (temp) { 2043 /* receive data 1 byte at a time */ 2044 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2045 MUSB2_REG_EPFIFO(td->channel), 2046 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 2047 } 2048 /* update offset and remainder */ 2049 td->offset += count; 2050 td->remainder -= count; 2051 break; 2052 } 2053 /* check if we can optimise */ 2054 if (buf_res.length >= 4) { 2055 /* transmit data 4 bytes at a time */ 2056 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 2057 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2058 buf_res.length / 4); 2059 2060 temp = buf_res.length & ~3; 2061 2062 /* update counters */ 2063 count -= temp; 2064 td->offset += temp; 2065 td->remainder -= temp; 2066 continue; 2067 } 2068 /* transmit data */ 2069 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2070 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2071 buf_res.length); 2072 2073 /* update counters */ 2074 count -= buf_res.length; 2075 td->offset += buf_res.length; 2076 td->remainder -= buf_res.length; 2077 } 2078 2079 /* Function address */ 2080 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel), 2081 td->dev_addr); 2082 2083 /* SPLIT transaction */ 2084 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel), 2085 td->haddr); 2086 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel), 2087 td->hport); 2088 2089 /* TX NAK timeout */ 2090 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) 2091 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0); 2092 else 2093 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 2094 2095 /* Protocol, speed, device endpoint */ 2096 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 2097 2098 /* Max packet size */ 2099 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); 2100 2101 if (!td->transaction_started) { 2102 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 2103 DPRINTFN(4, "csrh=0x%02x\n", csrh); 2104 2105 csrh |= MUSB2_MASK_CSRH_TXDT_WREN; 2106 if (td->toggle) 2107 csrh |= MUSB2_MASK_CSRH_TXDT_VAL; 2108 else 2109 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2110 2111 /* Set data toggle */ 2112 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 2113 } 2114 2115 /* write command */ 2116 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2117 MUSB2_MASK_CSRL_TXPKTRDY); 2118 2119 /* Update Data Toggle */ 2120 td->toggle ^= 1; 2121 td->transaction_started = 1; 2122 2123 return (1); /* not complete */ 2124 } 2125 2126 static uint8_t 2127 musbotg_xfer_do_fifo(struct usb_xfer *xfer) 2128 { 2129 struct musbotg_td *td; 2130 2131 DPRINTFN(8, "\n"); 2132 td = xfer->td_transfer_cache; 2133 while (1) { 2134 if ((td->func) (td)) { 2135 /* operation in progress */ 2136 break; 2137 } 2138 2139 if (((void *)td) == xfer->td_transfer_last) { 2140 goto done; 2141 } 2142 if (td->error) { 2143 goto done; 2144 } else if (td->remainder > 0) { 2145 /* 2146 * We had a short transfer. If there is no alternate 2147 * next, stop processing ! 2148 */ 2149 if (!td->alt_next) { 2150 goto done; 2151 } 2152 } 2153 /* 2154 * Fetch the next transfer descriptor and transfer 2155 * some flags to the next transfer descriptor 2156 */ 2157 td = td->obj_next; 2158 xfer->td_transfer_cache = td; 2159 } 2160 2161 return (1); /* not complete */ 2162 done: 2163 /* compute all actual lengths */ 2164 musbotg_standard_done(xfer); 2165 2166 return (0); /* complete */ 2167 } 2168 2169 static void 2170 musbotg_interrupt_poll(struct musbotg_softc *sc) 2171 { 2172 struct usb_xfer *xfer; 2173 2174 repeat: 2175 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2176 if (!musbotg_xfer_do_fifo(xfer)) { 2177 /* queue has been modified */ 2178 goto repeat; 2179 } 2180 } 2181 } 2182 2183 void 2184 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 2185 { 2186 DPRINTFN(4, "vbus = %u\n", is_on); 2187 2188 USB_BUS_LOCK(&sc->sc_bus); 2189 if (is_on) { 2190 if (!sc->sc_flags.status_vbus) { 2191 sc->sc_flags.status_vbus = 1; 2192 2193 /* complete root HUB interrupt endpoint */ 2194 musbotg_root_intr(sc); 2195 } 2196 } else { 2197 if (sc->sc_flags.status_vbus) { 2198 sc->sc_flags.status_vbus = 0; 2199 sc->sc_flags.status_bus_reset = 0; 2200 sc->sc_flags.status_suspend = 0; 2201 sc->sc_flags.change_suspend = 0; 2202 sc->sc_flags.change_connect = 1; 2203 2204 /* complete root HUB interrupt endpoint */ 2205 musbotg_root_intr(sc); 2206 } 2207 } 2208 2209 USB_BUS_UNLOCK(&sc->sc_bus); 2210 } 2211 2212 void 2213 musbotg_connect_interrupt(struct musbotg_softc *sc) 2214 { 2215 USB_BUS_LOCK(&sc->sc_bus); 2216 sc->sc_flags.change_connect = 1; 2217 2218 /* complete root HUB interrupt endpoint */ 2219 musbotg_root_intr(sc); 2220 USB_BUS_UNLOCK(&sc->sc_bus); 2221 } 2222 2223 void 2224 musbotg_interrupt(struct musbotg_softc *sc, 2225 uint16_t rxstat, uint16_t txstat, uint8_t stat) 2226 { 2227 uint16_t rx_status; 2228 uint16_t tx_status; 2229 uint8_t usb_status; 2230 uint8_t temp; 2231 uint8_t to = 2; 2232 2233 USB_BUS_LOCK(&sc->sc_bus); 2234 2235 repeat: 2236 2237 /* read all interrupt registers */ 2238 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 2239 2240 /* read all FIFO interrupts */ 2241 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 2242 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 2243 rx_status |= rxstat; 2244 tx_status |= txstat; 2245 usb_status |= stat; 2246 2247 /* Clear platform flags after first time */ 2248 rxstat = 0; 2249 txstat = 0; 2250 stat = 0; 2251 2252 /* check for any bus state change interrupts */ 2253 2254 if (usb_status & (MUSB2_MASK_IRESET | 2255 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 2256 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC | 2257 MUSB2_MASK_IVBUSERR)) { 2258 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 2259 2260 if (usb_status & MUSB2_MASK_IRESET) { 2261 /* set correct state */ 2262 sc->sc_flags.status_bus_reset = 1; 2263 sc->sc_flags.status_suspend = 0; 2264 sc->sc_flags.change_suspend = 0; 2265 sc->sc_flags.change_connect = 1; 2266 2267 /* determine line speed */ 2268 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 2269 if (temp & MUSB2_MASK_HSMODE) 2270 sc->sc_flags.status_high_speed = 1; 2271 else 2272 sc->sc_flags.status_high_speed = 0; 2273 2274 /* 2275 * After reset all interrupts are on and we need to 2276 * turn them off! 2277 */ 2278 temp = MUSB2_MASK_IRESET; 2279 /* disable resume interrupt */ 2280 temp &= ~MUSB2_MASK_IRESUME; 2281 /* enable suspend interrupt */ 2282 temp |= MUSB2_MASK_ISUSP; 2283 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2284 /* disable TX and RX interrupts */ 2285 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 2286 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 2287 } 2288 /* 2289 * If RXRSM and RXSUSP is set at the same time we interpret 2290 * that like RESUME. Resume is set when there is at least 3 2291 * milliseconds of inactivity on the USB BUS. 2292 */ 2293 if (usb_status & MUSB2_MASK_IRESUME) { 2294 if (sc->sc_flags.status_suspend) { 2295 sc->sc_flags.status_suspend = 0; 2296 sc->sc_flags.change_suspend = 1; 2297 2298 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2299 /* disable resume interrupt */ 2300 temp &= ~MUSB2_MASK_IRESUME; 2301 /* enable suspend interrupt */ 2302 temp |= MUSB2_MASK_ISUSP; 2303 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2304 } 2305 } else if (usb_status & MUSB2_MASK_ISUSP) { 2306 if (!sc->sc_flags.status_suspend) { 2307 sc->sc_flags.status_suspend = 1; 2308 sc->sc_flags.change_suspend = 1; 2309 2310 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2311 /* disable suspend interrupt */ 2312 temp &= ~MUSB2_MASK_ISUSP; 2313 /* enable resume interrupt */ 2314 temp |= MUSB2_MASK_IRESUME; 2315 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2316 } 2317 } 2318 if (usb_status & 2319 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) 2320 sc->sc_flags.change_connect = 1; 2321 2322 /* 2323 * Host Mode: There is no IRESET so assume bus is 2324 * always in reset state once device is connected. 2325 */ 2326 if (sc->sc_mode == MUSB2_HOST_MODE) { 2327 /* check for VBUS error in USB host mode */ 2328 if (usb_status & MUSB2_MASK_IVBUSERR) { 2329 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 2330 temp |= MUSB2_MASK_SESS; 2331 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 2332 } 2333 if (usb_status & MUSB2_MASK_ICONN) 2334 sc->sc_flags.status_bus_reset = 1; 2335 if (usb_status & MUSB2_MASK_IDISC) 2336 sc->sc_flags.status_bus_reset = 0; 2337 } 2338 2339 /* complete root HUB interrupt endpoint */ 2340 musbotg_root_intr(sc); 2341 } 2342 /* check for any endpoint interrupts */ 2343 2344 if (rx_status || tx_status) { 2345 DPRINTFN(4, "real endpoint interrupt " 2346 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 2347 } 2348 /* poll one time regardless of FIFO status */ 2349 2350 musbotg_interrupt_poll(sc); 2351 2352 if (--to) 2353 goto repeat; 2354 2355 USB_BUS_UNLOCK(&sc->sc_bus); 2356 } 2357 2358 static void 2359 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 2360 { 2361 struct musbotg_td *td; 2362 2363 /* get current Transfer Descriptor */ 2364 td = temp->td_next; 2365 temp->td = td; 2366 2367 /* prepare for next TD */ 2368 temp->td_next = td->obj_next; 2369 2370 /* fill out the Transfer Descriptor */ 2371 td->func = temp->func; 2372 td->pc = temp->pc; 2373 td->offset = temp->offset; 2374 td->remainder = temp->len; 2375 td->error = 0; 2376 td->transaction_started = 0; 2377 td->did_stall = temp->did_stall; 2378 td->short_pkt = temp->short_pkt; 2379 td->alt_next = temp->setup_alt_next; 2380 td->channel = temp->channel; 2381 td->dev_addr = temp->dev_addr; 2382 td->haddr = temp->haddr; 2383 td->hport = temp->hport; 2384 td->transfer_type = temp->transfer_type; 2385 } 2386 2387 static void 2388 musbotg_setup_standard_chain(struct usb_xfer *xfer) 2389 { 2390 struct musbotg_std_temp temp; 2391 struct musbotg_softc *sc; 2392 struct musbotg_td *td; 2393 uint32_t x; 2394 uint8_t ep_no; 2395 uint8_t xfer_type; 2396 enum usb_dev_speed speed; 2397 int tx; 2398 int dev_addr; 2399 2400 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2401 xfer->address, UE_GET_ADDR(xfer->endpointno), 2402 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2403 2404 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2405 ep_no = (xfer->endpointno & UE_ADDR); 2406 2407 temp.max_frame_size = xfer->max_frame_size; 2408 2409 td = xfer->td_start[0]; 2410 xfer->td_transfer_first = td; 2411 xfer->td_transfer_cache = td; 2412 2413 /* setup temp */ 2414 dev_addr = xfer->address; 2415 2416 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 2417 2418 temp.pc = NULL; 2419 temp.td = NULL; 2420 temp.td_next = xfer->td_start[0]; 2421 temp.offset = 0; 2422 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 2423 xfer->flags_int.isochronous_xfr; 2424 temp.did_stall = !xfer->flags_int.control_stall; 2425 temp.channel = -1; 2426 temp.dev_addr = dev_addr; 2427 temp.haddr = xfer->xroot->udev->hs_hub_addr; 2428 temp.hport = xfer->xroot->udev->hs_port_no; 2429 2430 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2431 speed = usbd_get_speed(xfer->xroot->udev); 2432 2433 switch (speed) { 2434 case USB_SPEED_LOW: 2435 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO; 2436 break; 2437 case USB_SPEED_FULL: 2438 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS; 2439 break; 2440 case USB_SPEED_HIGH: 2441 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS; 2442 break; 2443 default: 2444 temp.transfer_type = 0; 2445 DPRINTFN(-1, "Invalid USB speed: %d\n", speed); 2446 break; 2447 } 2448 2449 switch (xfer_type) { 2450 case UE_CONTROL: 2451 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL; 2452 break; 2453 case UE_ISOCHRONOUS: 2454 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC; 2455 break; 2456 case UE_BULK: 2457 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK; 2458 break; 2459 case UE_INTERRUPT: 2460 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR; 2461 break; 2462 default: 2463 DPRINTFN(-1, "Invalid USB transfer type: %d\n", 2464 xfer_type); 2465 break; 2466 } 2467 2468 temp.transfer_type |= ep_no; 2469 td->toggle = xfer->endpoint->toggle_next; 2470 } 2471 2472 /* check if we should prepend a setup message */ 2473 2474 if (xfer->flags_int.control_xfr) { 2475 if (xfer->flags_int.control_hdr) { 2476 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) 2477 temp.func = &musbotg_dev_ctrl_setup_rx; 2478 else 2479 temp.func = &musbotg_host_ctrl_setup_tx; 2480 2481 temp.len = xfer->frlengths[0]; 2482 temp.pc = xfer->frbuffers + 0; 2483 temp.short_pkt = temp.len ? 1 : 0; 2484 2485 musbotg_setup_standard_chain_sub(&temp); 2486 } 2487 x = 1; 2488 } else { 2489 x = 0; 2490 } 2491 2492 tx = 0; 2493 2494 if (x != xfer->nframes) { 2495 if (xfer->endpointno & UE_DIR_IN) 2496 tx = 1; 2497 2498 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2499 tx = !tx; 2500 2501 if (tx) { 2502 if (xfer->flags_int.control_xfr) 2503 temp.func = &musbotg_host_ctrl_data_tx; 2504 else 2505 temp.func = &musbotg_host_data_tx; 2506 } else { 2507 if (xfer->flags_int.control_xfr) 2508 temp.func = &musbotg_host_ctrl_data_rx; 2509 else 2510 temp.func = &musbotg_host_data_rx; 2511 } 2512 2513 } else { 2514 if (tx) { 2515 if (xfer->flags_int.control_xfr) 2516 temp.func = &musbotg_dev_ctrl_data_tx; 2517 else 2518 temp.func = &musbotg_dev_data_tx; 2519 } else { 2520 if (xfer->flags_int.control_xfr) 2521 temp.func = &musbotg_dev_ctrl_data_rx; 2522 else 2523 temp.func = &musbotg_dev_data_rx; 2524 } 2525 } 2526 2527 /* setup "pc" pointer */ 2528 temp.pc = xfer->frbuffers + x; 2529 } 2530 while (x != xfer->nframes) { 2531 /* DATA0 / DATA1 message */ 2532 2533 temp.len = xfer->frlengths[x]; 2534 2535 x++; 2536 2537 if (x == xfer->nframes) { 2538 if (xfer->flags_int.control_xfr) { 2539 if (xfer->flags_int.control_act) { 2540 temp.setup_alt_next = 0; 2541 } 2542 } else { 2543 temp.setup_alt_next = 0; 2544 } 2545 } 2546 if (temp.len == 0) { 2547 /* make sure that we send an USB packet */ 2548 2549 temp.short_pkt = 0; 2550 2551 } else { 2552 if (xfer->flags_int.isochronous_xfr) { 2553 /* isochronous data transfer */ 2554 /* don't force short */ 2555 temp.short_pkt = 1; 2556 } else { 2557 /* regular data transfer */ 2558 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 2559 } 2560 } 2561 2562 musbotg_setup_standard_chain_sub(&temp); 2563 2564 if (xfer->flags_int.isochronous_xfr) { 2565 temp.offset += temp.len; 2566 } else { 2567 /* get next Page Cache pointer */ 2568 temp.pc = xfer->frbuffers + x; 2569 } 2570 } 2571 2572 /* check for control transfer */ 2573 if (xfer->flags_int.control_xfr) { 2574 /* always setup a valid "pc" pointer for status and sync */ 2575 temp.pc = xfer->frbuffers + 0; 2576 temp.len = 0; 2577 temp.short_pkt = 0; 2578 temp.setup_alt_next = 0; 2579 2580 /* check if we should append a status stage */ 2581 if (!xfer->flags_int.control_act) { 2582 /* 2583 * Send a DATA1 message and invert the current 2584 * endpoint direction. 2585 */ 2586 if (sc->sc_mode == MUSB2_DEVICE_MODE) 2587 temp.func = &musbotg_dev_ctrl_status; 2588 else { 2589 if (xfer->endpointno & UE_DIR_IN) 2590 temp.func = musbotg_host_ctrl_status_tx; 2591 else 2592 temp.func = musbotg_host_ctrl_status_rx; 2593 } 2594 musbotg_setup_standard_chain_sub(&temp); 2595 } 2596 } 2597 /* must have at least one frame! */ 2598 td = temp.td; 2599 xfer->td_transfer_last = td; 2600 } 2601 2602 static void 2603 musbotg_timeout(void *arg) 2604 { 2605 struct usb_xfer *xfer = arg; 2606 2607 DPRINTFN(1, "xfer=%p\n", xfer); 2608 2609 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2610 2611 /* transfer is transferred */ 2612 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 2613 } 2614 2615 static void 2616 musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on) 2617 { 2618 uint16_t temp; 2619 2620 /* 2621 * Only enable the endpoint interrupt when we are 2622 * actually waiting for data, hence we are dealing 2623 * with level triggered interrupts ! 2624 */ 2625 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on); 2626 2627 if (channel == -1) 2628 return; 2629 2630 if (channel == 0) { 2631 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2632 if (on) 2633 temp |= MUSB2_MASK_EPINT(0); 2634 else 2635 temp &= ~MUSB2_MASK_EPINT(0); 2636 2637 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2638 } else { 2639 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 2640 if (on) 2641 temp |= MUSB2_MASK_EPINT(channel); 2642 else 2643 temp &= ~MUSB2_MASK_EPINT(channel); 2644 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 2645 2646 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2647 if (on) 2648 temp |= MUSB2_MASK_EPINT(channel); 2649 else 2650 temp &= ~MUSB2_MASK_EPINT(channel); 2651 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2652 } 2653 2654 if (sc->sc_ep_int_set) 2655 sc->sc_ep_int_set(sc, channel, on); 2656 } 2657 2658 static void 2659 musbotg_start_standard_chain(struct usb_xfer *xfer) 2660 { 2661 DPRINTFN(8, "\n"); 2662 2663 /* poll one time */ 2664 if (musbotg_xfer_do_fifo(xfer)) { 2665 DPRINTFN(14, "enabled interrupts on endpoint\n"); 2666 2667 /* put transfer on interrupt queue */ 2668 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2669 2670 /* start timeout, if any */ 2671 if (xfer->timeout != 0) { 2672 usbd_transfer_timeout_ms(xfer, 2673 &musbotg_timeout, xfer->timeout); 2674 } 2675 } 2676 } 2677 2678 static void 2679 musbotg_root_intr(struct musbotg_softc *sc) 2680 { 2681 DPRINTFN(8, "\n"); 2682 2683 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2684 2685 /* set port bit */ 2686 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 2687 2688 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2689 sizeof(sc->sc_hub_idata)); 2690 } 2691 2692 static usb_error_t 2693 musbotg_standard_done_sub(struct usb_xfer *xfer) 2694 { 2695 struct musbotg_td *td; 2696 uint32_t len; 2697 uint8_t error; 2698 2699 DPRINTFN(8, "\n"); 2700 2701 td = xfer->td_transfer_cache; 2702 2703 do { 2704 len = td->remainder; 2705 2706 xfer->endpoint->toggle_next = td->toggle; 2707 2708 if (xfer->aframes != xfer->nframes) { 2709 /* 2710 * Verify the length and subtract 2711 * the remainder from "frlengths[]": 2712 */ 2713 if (len > xfer->frlengths[xfer->aframes]) { 2714 td->error = 1; 2715 } else { 2716 xfer->frlengths[xfer->aframes] -= len; 2717 } 2718 } 2719 /* Check for transfer error */ 2720 if (td->error) { 2721 /* the transfer is finished */ 2722 error = 1; 2723 td = NULL; 2724 break; 2725 } 2726 /* Check for short transfer */ 2727 if (len > 0) { 2728 if (xfer->flags_int.short_frames_ok || 2729 xfer->flags_int.isochronous_xfr) { 2730 /* follow alt next */ 2731 if (td->alt_next) { 2732 td = td->obj_next; 2733 } else { 2734 td = NULL; 2735 } 2736 } else { 2737 /* the transfer is finished */ 2738 td = NULL; 2739 } 2740 error = 0; 2741 break; 2742 } 2743 td = td->obj_next; 2744 2745 /* this USB frame is complete */ 2746 error = 0; 2747 break; 2748 2749 } while (0); 2750 2751 /* update transfer cache */ 2752 2753 xfer->td_transfer_cache = td; 2754 2755 return (error ? 2756 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 2757 } 2758 2759 static void 2760 musbotg_standard_done(struct usb_xfer *xfer) 2761 { 2762 usb_error_t err = 0; 2763 2764 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n", 2765 xfer, xfer->endpoint); 2766 2767 /* reset scanner */ 2768 2769 xfer->td_transfer_cache = xfer->td_transfer_first; 2770 2771 if (xfer->flags_int.control_xfr) { 2772 if (xfer->flags_int.control_hdr) { 2773 err = musbotg_standard_done_sub(xfer); 2774 } 2775 xfer->aframes = 1; 2776 2777 if (xfer->td_transfer_cache == NULL) { 2778 goto done; 2779 } 2780 } 2781 while (xfer->aframes != xfer->nframes) { 2782 err = musbotg_standard_done_sub(xfer); 2783 xfer->aframes++; 2784 2785 if (xfer->td_transfer_cache == NULL) { 2786 goto done; 2787 } 2788 } 2789 2790 if (xfer->flags_int.control_xfr && 2791 !xfer->flags_int.control_act) { 2792 err = musbotg_standard_done_sub(xfer); 2793 } 2794 done: 2795 musbotg_device_done(xfer, err); 2796 } 2797 2798 /*------------------------------------------------------------------------* 2799 * musbotg_device_done 2800 * 2801 * NOTE: this function can be called more than one time on the 2802 * same USB transfer! 2803 *------------------------------------------------------------------------*/ 2804 static void 2805 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error) 2806 { 2807 struct musbotg_td *td; 2808 struct musbotg_softc *sc; 2809 2810 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2811 2812 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n", 2813 xfer, xfer->endpoint, error); 2814 2815 DPRINTFN(14, "disabled interrupts on endpoint\n"); 2816 2817 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2818 td = xfer->td_transfer_cache; 2819 2820 if (td && (td->channel != -1)) 2821 musbotg_channel_free(sc, td); 2822 2823 /* dequeue transfer and start next transfer */ 2824 usbd_transfer_done(xfer, error); 2825 } 2826 2827 static void 2828 musbotg_xfer_stall(struct usb_xfer *xfer) 2829 { 2830 musbotg_device_done(xfer, USB_ERR_STALLED); 2831 } 2832 2833 static void 2834 musbotg_set_stall(struct usb_device *udev, 2835 struct usb_endpoint *ep, uint8_t *did_stall) 2836 { 2837 struct musbotg_softc *sc; 2838 uint8_t ep_no; 2839 2840 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2841 2842 DPRINTFN(4, "endpoint=%p\n", ep); 2843 2844 /* set FORCESTALL */ 2845 sc = MUSBOTG_BUS2SC(udev->bus); 2846 2847 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 2848 2849 /* select endpoint */ 2850 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2851 2852 if (ep->edesc->bEndpointAddress & UE_DIR_IN) { 2853 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2854 MUSB2_MASK_CSRL_TXSENDSTALL); 2855 } else { 2856 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2857 MUSB2_MASK_CSRL_RXSENDSTALL); 2858 } 2859 } 2860 2861 static void 2862 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 2863 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 2864 { 2865 uint16_t mps; 2866 uint16_t temp; 2867 uint8_t csr; 2868 2869 if (ep_type == UE_CONTROL) { 2870 /* clearing stall is not needed */ 2871 return; 2872 } 2873 /* select endpoint */ 2874 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2875 2876 /* compute max frame size */ 2877 mps = wMaxPacket & 0x7FF; 2878 switch ((wMaxPacket >> 11) & 3) { 2879 case 1: 2880 mps *= 2; 2881 break; 2882 case 2: 2883 mps *= 3; 2884 break; 2885 default: 2886 break; 2887 } 2888 2889 if (ep_dir == UE_DIR_IN) { 2890 temp = 0; 2891 2892 /* Configure endpoint */ 2893 switch (ep_type) { 2894 case UE_INTERRUPT: 2895 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2896 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2897 MUSB2_MASK_CSRH_TXMODE | temp); 2898 break; 2899 case UE_ISOCHRONOUS: 2900 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2901 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2902 MUSB2_MASK_CSRH_TXMODE | 2903 MUSB2_MASK_CSRH_TXISO | temp); 2904 break; 2905 case UE_BULK: 2906 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2907 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2908 MUSB2_MASK_CSRH_TXMODE | temp); 2909 break; 2910 default: 2911 break; 2912 } 2913 2914 /* Need to flush twice in case of double bufring */ 2915 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2916 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2917 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2918 MUSB2_MASK_CSRL_TXFFLUSH); 2919 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2920 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2921 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2922 MUSB2_MASK_CSRL_TXFFLUSH); 2923 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2924 } 2925 } 2926 /* reset data toggle */ 2927 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2928 MUSB2_MASK_CSRL_TXDT_CLR); 2929 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2930 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2931 2932 /* set double/single buffering */ 2933 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 2934 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 2935 max_in_frame_size / 2)) { 2936 /* double buffer */ 2937 temp &= ~(1 << ep_no); 2938 } else { 2939 /* single buffer */ 2940 temp |= (1 << ep_no); 2941 } 2942 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 2943 2944 /* clear sent stall */ 2945 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 2946 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2947 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2948 } 2949 } else { 2950 temp = 0; 2951 2952 /* Configure endpoint */ 2953 switch (ep_type) { 2954 case UE_INTERRUPT: 2955 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2956 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2957 MUSB2_MASK_CSRH_RXNYET | temp); 2958 break; 2959 case UE_ISOCHRONOUS: 2960 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2961 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2962 MUSB2_MASK_CSRH_RXNYET | 2963 MUSB2_MASK_CSRH_RXISO | temp); 2964 break; 2965 case UE_BULK: 2966 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2967 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 2968 break; 2969 default: 2970 break; 2971 } 2972 2973 /* Need to flush twice in case of double bufring */ 2974 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2975 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2976 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2977 MUSB2_MASK_CSRL_RXFFLUSH); 2978 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2979 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2980 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2981 MUSB2_MASK_CSRL_RXFFLUSH); 2982 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2983 } 2984 } 2985 /* reset data toggle */ 2986 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2987 MUSB2_MASK_CSRL_RXDT_CLR); 2988 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 2989 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2990 2991 /* set double/single buffering */ 2992 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 2993 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 2994 max_out_frame_size / 2)) { 2995 /* double buffer */ 2996 temp &= ~(1 << ep_no); 2997 } else { 2998 /* single buffer */ 2999 temp |= (1 << ep_no); 3000 } 3001 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 3002 3003 /* clear sent stall */ 3004 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 3005 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 3006 } 3007 } 3008 } 3009 3010 static void 3011 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3012 { 3013 struct musbotg_softc *sc; 3014 struct usb_endpoint_descriptor *ed; 3015 3016 DPRINTFN(4, "endpoint=%p\n", ep); 3017 3018 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3019 3020 /* check mode */ 3021 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3022 /* not supported */ 3023 return; 3024 } 3025 /* get softc */ 3026 sc = MUSBOTG_BUS2SC(udev->bus); 3027 3028 /* get endpoint descriptor */ 3029 ed = ep->edesc; 3030 3031 /* reset endpoint */ 3032 musbotg_clear_stall_sub(sc, 3033 UGETW(ed->wMaxPacketSize), 3034 (ed->bEndpointAddress & UE_ADDR), 3035 (ed->bmAttributes & UE_XFERTYPE), 3036 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3037 } 3038 3039 usb_error_t 3040 musbotg_init(struct musbotg_softc *sc) 3041 { 3042 const struct musb_otg_ep_cfg *cfg; 3043 struct usb_hw_ep_profile *pf; 3044 int i; 3045 uint16_t offset; 3046 uint8_t nrx; 3047 uint8_t ntx; 3048 uint8_t temp; 3049 uint8_t fsize; 3050 uint8_t frx; 3051 uint8_t ftx; 3052 uint8_t dynfifo; 3053 3054 DPRINTFN(1, "start\n"); 3055 3056 /* set up the bus structure */ 3057 sc->sc_bus.usbrev = USB_REV_2_0; 3058 sc->sc_bus.methods = &musbotg_bus_methods; 3059 3060 /* Set a default endpoint configuration */ 3061 if (sc->sc_ep_cfg == NULL) 3062 sc->sc_ep_cfg = musbotg_ep_default; 3063 3064 USB_BUS_LOCK(&sc->sc_bus); 3065 3066 /* turn on clocks */ 3067 3068 if (sc->sc_clocks_on) { 3069 (sc->sc_clocks_on) (sc->sc_clocks_arg); 3070 } 3071 3072 /* wait a little for things to stabilise */ 3073 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 3074 3075 /* disable all interrupts */ 3076 3077 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3078 DPRINTF("pre-DEVCTL=0x%02x\n", temp); 3079 3080 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3081 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3082 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3083 3084 /* disable pullup */ 3085 3086 musbotg_pull_common(sc, 0); 3087 3088 /* wait a little bit (10ms) */ 3089 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3090 3091 /* disable double packet buffering */ 3092 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 3093 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 3094 3095 /* enable HighSpeed and ISO Update flags */ 3096 3097 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 3098 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 3099 3100 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 3101 /* clear Session bit, if set */ 3102 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3103 temp &= ~MUSB2_MASK_SESS; 3104 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3105 } else { 3106 /* Enter session for Host mode */ 3107 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3108 temp |= MUSB2_MASK_SESS; 3109 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3110 } 3111 3112 /* wait a little for things to stabilise */ 3113 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 3114 3115 DPRINTF("DEVCTL=0x%02x\n", temp); 3116 3117 /* disable testmode */ 3118 3119 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 3120 3121 /* set default value */ 3122 3123 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 3124 3125 /* select endpoint index 0 */ 3126 3127 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 3128 3129 if (sc->sc_ep_max == 0) { 3130 /* read out number of endpoints */ 3131 3132 nrx = 3133 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 3134 3135 ntx = 3136 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 3137 3138 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 3139 } else { 3140 nrx = ntx = sc->sc_ep_max; 3141 } 3142 3143 /* these numbers exclude the control endpoint */ 3144 3145 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 3146 3147 if (sc->sc_ep_max == 0) { 3148 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 3149 } 3150 /* read out configuration data */ 3151 3152 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 3153 3154 DPRINTFN(2, "Config Data: 0x%02x\n", 3155 sc->sc_conf_data); 3156 3157 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 3158 3159 if (dynfifo) { 3160 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, " 3161 "assuming 16Kbytes of FIFO RAM\n"); 3162 } 3163 3164 DPRINTFN(2, "HW version: 0x%04x\n", 3165 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 3166 3167 /* initialise endpoint profiles */ 3168 3169 offset = 0; 3170 3171 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 3172 pf = sc->sc_hw_ep_profile + temp; 3173 3174 /* select endpoint */ 3175 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 3176 3177 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 3178 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16; 3179 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 3180 3181 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 3182 temp, ftx, frx, dynfifo); 3183 3184 if (dynfifo) { 3185 if (frx && (temp <= nrx)) { 3186 for (i = 0; sc->sc_ep_cfg[i].ep_end >= 0; i++) { 3187 cfg = &sc->sc_ep_cfg[i]; 3188 if (temp <= cfg->ep_end) { 3189 frx = cfg->ep_fifosz_shift; 3190 MUSB2_WRITE_1(sc, 3191 MUSB2_REG_RXFIFOSZ, 3192 cfg->ep_fifosz_reg); 3193 break; 3194 } 3195 } 3196 3197 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD, 3198 offset >> 3); 3199 3200 offset += (1 << frx); 3201 } 3202 if (ftx && (temp <= ntx)) { 3203 for (i = 0; sc->sc_ep_cfg[i].ep_end >= 0; i++) { 3204 cfg = &sc->sc_ep_cfg[i]; 3205 if (temp <= cfg->ep_end) { 3206 ftx = cfg->ep_fifosz_shift; 3207 MUSB2_WRITE_1(sc, 3208 MUSB2_REG_TXFIFOSZ, 3209 cfg->ep_fifosz_reg); 3210 break; 3211 } 3212 } 3213 3214 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD, 3215 offset >> 3); 3216 3217 offset += (1 << ftx); 3218 } 3219 } 3220 3221 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 3222 pf->max_in_frame_size = 1 << ftx; 3223 pf->max_out_frame_size = 1 << frx; 3224 pf->is_simplex = 0; /* duplex */ 3225 pf->support_multi_buffer = 1; 3226 pf->support_bulk = 1; 3227 pf->support_interrupt = 1; 3228 pf->support_isochronous = 1; 3229 pf->support_in = 1; 3230 pf->support_out = 1; 3231 } else if (frx && (temp <= nrx)) { 3232 pf->max_out_frame_size = 1 << frx; 3233 pf->max_in_frame_size = 0; 3234 pf->is_simplex = 1; /* simplex */ 3235 pf->support_multi_buffer = 1; 3236 pf->support_bulk = 1; 3237 pf->support_interrupt = 1; 3238 pf->support_isochronous = 1; 3239 pf->support_out = 1; 3240 } else if (ftx && (temp <= ntx)) { 3241 pf->max_in_frame_size = 1 << ftx; 3242 pf->max_out_frame_size = 0; 3243 pf->is_simplex = 1; /* simplex */ 3244 pf->support_multi_buffer = 1; 3245 pf->support_bulk = 1; 3246 pf->support_interrupt = 1; 3247 pf->support_isochronous = 1; 3248 pf->support_in = 1; 3249 } 3250 } 3251 3252 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset); 3253 3254 /* turn on default interrupts */ 3255 3256 if (sc->sc_mode == MUSB2_HOST_MODE) 3257 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff); 3258 else 3259 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 3260 MUSB2_MASK_IRESET); 3261 3262 musbotg_clocks_off(sc); 3263 3264 USB_BUS_UNLOCK(&sc->sc_bus); 3265 3266 /* catch any lost interrupts */ 3267 3268 musbotg_do_poll(&sc->sc_bus); 3269 3270 return (0); /* success */ 3271 } 3272 3273 void 3274 musbotg_uninit(struct musbotg_softc *sc) 3275 { 3276 USB_BUS_LOCK(&sc->sc_bus); 3277 3278 /* disable all interrupts */ 3279 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3280 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3281 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3282 3283 sc->sc_flags.port_powered = 0; 3284 sc->sc_flags.status_vbus = 0; 3285 sc->sc_flags.status_bus_reset = 0; 3286 sc->sc_flags.status_suspend = 0; 3287 sc->sc_flags.change_suspend = 0; 3288 sc->sc_flags.change_connect = 1; 3289 3290 musbotg_pull_down(sc); 3291 musbotg_clocks_off(sc); 3292 USB_BUS_UNLOCK(&sc->sc_bus); 3293 } 3294 3295 static void 3296 musbotg_do_poll(struct usb_bus *bus) 3297 { 3298 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 3299 3300 USB_BUS_LOCK(&sc->sc_bus); 3301 musbotg_interrupt_poll(sc); 3302 USB_BUS_UNLOCK(&sc->sc_bus); 3303 } 3304 3305 /*------------------------------------------------------------------------* 3306 * musbotg bulk support 3307 *------------------------------------------------------------------------*/ 3308 static void 3309 musbotg_device_bulk_open(struct usb_xfer *xfer) 3310 { 3311 return; 3312 } 3313 3314 static void 3315 musbotg_device_bulk_close(struct usb_xfer *xfer) 3316 { 3317 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3318 } 3319 3320 static void 3321 musbotg_device_bulk_enter(struct usb_xfer *xfer) 3322 { 3323 return; 3324 } 3325 3326 static void 3327 musbotg_device_bulk_start(struct usb_xfer *xfer) 3328 { 3329 /* setup TDs */ 3330 musbotg_setup_standard_chain(xfer); 3331 musbotg_start_standard_chain(xfer); 3332 } 3333 3334 static const struct usb_pipe_methods musbotg_device_bulk_methods = 3335 { 3336 .open = musbotg_device_bulk_open, 3337 .close = musbotg_device_bulk_close, 3338 .enter = musbotg_device_bulk_enter, 3339 .start = musbotg_device_bulk_start, 3340 }; 3341 3342 /*------------------------------------------------------------------------* 3343 * musbotg control support 3344 *------------------------------------------------------------------------*/ 3345 static void 3346 musbotg_device_ctrl_open(struct usb_xfer *xfer) 3347 { 3348 return; 3349 } 3350 3351 static void 3352 musbotg_device_ctrl_close(struct usb_xfer *xfer) 3353 { 3354 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3355 } 3356 3357 static void 3358 musbotg_device_ctrl_enter(struct usb_xfer *xfer) 3359 { 3360 return; 3361 } 3362 3363 static void 3364 musbotg_device_ctrl_start(struct usb_xfer *xfer) 3365 { 3366 /* setup TDs */ 3367 musbotg_setup_standard_chain(xfer); 3368 musbotg_start_standard_chain(xfer); 3369 } 3370 3371 static const struct usb_pipe_methods musbotg_device_ctrl_methods = 3372 { 3373 .open = musbotg_device_ctrl_open, 3374 .close = musbotg_device_ctrl_close, 3375 .enter = musbotg_device_ctrl_enter, 3376 .start = musbotg_device_ctrl_start, 3377 }; 3378 3379 /*------------------------------------------------------------------------* 3380 * musbotg interrupt support 3381 *------------------------------------------------------------------------*/ 3382 static void 3383 musbotg_device_intr_open(struct usb_xfer *xfer) 3384 { 3385 return; 3386 } 3387 3388 static void 3389 musbotg_device_intr_close(struct usb_xfer *xfer) 3390 { 3391 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3392 } 3393 3394 static void 3395 musbotg_device_intr_enter(struct usb_xfer *xfer) 3396 { 3397 return; 3398 } 3399 3400 static void 3401 musbotg_device_intr_start(struct usb_xfer *xfer) 3402 { 3403 /* setup TDs */ 3404 musbotg_setup_standard_chain(xfer); 3405 musbotg_start_standard_chain(xfer); 3406 } 3407 3408 static const struct usb_pipe_methods musbotg_device_intr_methods = 3409 { 3410 .open = musbotg_device_intr_open, 3411 .close = musbotg_device_intr_close, 3412 .enter = musbotg_device_intr_enter, 3413 .start = musbotg_device_intr_start, 3414 }; 3415 3416 /*------------------------------------------------------------------------* 3417 * musbotg full speed isochronous support 3418 *------------------------------------------------------------------------*/ 3419 static void 3420 musbotg_device_isoc_open(struct usb_xfer *xfer) 3421 { 3422 return; 3423 } 3424 3425 static void 3426 musbotg_device_isoc_close(struct usb_xfer *xfer) 3427 { 3428 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3429 } 3430 3431 static void 3432 musbotg_device_isoc_enter(struct usb_xfer *xfer) 3433 { 3434 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 3435 uint32_t nframes; 3436 3437 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 3438 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3439 3440 /* get the current frame index */ 3441 3442 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 3443 3444 if (usbd_xfer_get_isochronous_start_frame( 3445 xfer, nframes, 0, 1, MUSB2_MASK_FRAME, NULL)) 3446 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next); 3447 3448 /* setup TDs */ 3449 musbotg_setup_standard_chain(xfer); 3450 } 3451 3452 static void 3453 musbotg_device_isoc_start(struct usb_xfer *xfer) 3454 { 3455 /* start TD chain */ 3456 musbotg_start_standard_chain(xfer); 3457 } 3458 3459 static const struct usb_pipe_methods musbotg_device_isoc_methods = 3460 { 3461 .open = musbotg_device_isoc_open, 3462 .close = musbotg_device_isoc_close, 3463 .enter = musbotg_device_isoc_enter, 3464 .start = musbotg_device_isoc_start, 3465 }; 3466 3467 /*------------------------------------------------------------------------* 3468 * musbotg root control support 3469 *------------------------------------------------------------------------* 3470 * Simulate a hardware HUB by handling all the necessary requests. 3471 *------------------------------------------------------------------------*/ 3472 3473 static const struct usb_device_descriptor musbotg_devd = { 3474 .bLength = sizeof(struct usb_device_descriptor), 3475 .bDescriptorType = UDESC_DEVICE, 3476 .bcdUSB = {0x00, 0x02}, 3477 .bDeviceClass = UDCLASS_HUB, 3478 .bDeviceSubClass = UDSUBCLASS_HUB, 3479 .bDeviceProtocol = UDPROTO_HSHUBSTT, 3480 .bMaxPacketSize = 64, 3481 .bcdDevice = {0x00, 0x01}, 3482 .iManufacturer = 1, 3483 .iProduct = 2, 3484 .bNumConfigurations = 1, 3485 }; 3486 3487 static const struct usb_device_qualifier musbotg_odevd = { 3488 .bLength = sizeof(struct usb_device_qualifier), 3489 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 3490 .bcdUSB = {0x00, 0x02}, 3491 .bDeviceClass = UDCLASS_HUB, 3492 .bDeviceSubClass = UDSUBCLASS_HUB, 3493 .bDeviceProtocol = UDPROTO_FSHUB, 3494 .bMaxPacketSize0 = 0, 3495 .bNumConfigurations = 0, 3496 }; 3497 3498 static const struct musbotg_config_desc musbotg_confd = { 3499 .confd = { 3500 .bLength = sizeof(struct usb_config_descriptor), 3501 .bDescriptorType = UDESC_CONFIG, 3502 .wTotalLength[0] = sizeof(musbotg_confd), 3503 .bNumInterface = 1, 3504 .bConfigurationValue = 1, 3505 .iConfiguration = 0, 3506 .bmAttributes = UC_SELF_POWERED, 3507 .bMaxPower = 0, 3508 }, 3509 .ifcd = { 3510 .bLength = sizeof(struct usb_interface_descriptor), 3511 .bDescriptorType = UDESC_INTERFACE, 3512 .bNumEndpoints = 1, 3513 .bInterfaceClass = UICLASS_HUB, 3514 .bInterfaceSubClass = UISUBCLASS_HUB, 3515 .bInterfaceProtocol = 0, 3516 }, 3517 .endpd = { 3518 .bLength = sizeof(struct usb_endpoint_descriptor), 3519 .bDescriptorType = UDESC_ENDPOINT, 3520 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 3521 .bmAttributes = UE_INTERRUPT, 3522 .wMaxPacketSize[0] = 8, 3523 .bInterval = 255, 3524 }, 3525 }; 3526 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3527 3528 static const struct usb_hub_descriptor_min musbotg_hubd = { 3529 .bDescLength = sizeof(musbotg_hubd), 3530 .bDescriptorType = UDESC_HUB, 3531 .bNbrPorts = 1, 3532 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 3533 .bPwrOn2PwrGood = 50, 3534 .bHubContrCurrent = 0, 3535 .DeviceRemovable = {0}, /* port is removable */ 3536 }; 3537 3538 #define STRING_VENDOR \ 3539 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s" 3540 3541 #define STRING_PRODUCT \ 3542 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 3543 3544 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 3545 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 3546 3547 static usb_error_t 3548 musbotg_roothub_exec(struct usb_device *udev, 3549 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3550 { 3551 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 3552 const void *ptr; 3553 uint16_t len; 3554 uint16_t value; 3555 uint16_t index; 3556 uint8_t reg; 3557 usb_error_t err; 3558 3559 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3560 3561 /* buffer reset */ 3562 ptr = (const void *)&sc->sc_hub_temp; 3563 len = 0; 3564 err = 0; 3565 3566 value = UGETW(req->wValue); 3567 index = UGETW(req->wIndex); 3568 3569 /* demultiplex the control request */ 3570 3571 switch (req->bmRequestType) { 3572 case UT_READ_DEVICE: 3573 switch (req->bRequest) { 3574 case UR_GET_DESCRIPTOR: 3575 goto tr_handle_get_descriptor; 3576 case UR_GET_CONFIG: 3577 goto tr_handle_get_config; 3578 case UR_GET_STATUS: 3579 goto tr_handle_get_status; 3580 default: 3581 goto tr_stalled; 3582 } 3583 break; 3584 3585 case UT_WRITE_DEVICE: 3586 switch (req->bRequest) { 3587 case UR_SET_ADDRESS: 3588 goto tr_handle_set_address; 3589 case UR_SET_CONFIG: 3590 goto tr_handle_set_config; 3591 case UR_CLEAR_FEATURE: 3592 goto tr_valid; /* nop */ 3593 case UR_SET_DESCRIPTOR: 3594 goto tr_valid; /* nop */ 3595 case UR_SET_FEATURE: 3596 default: 3597 goto tr_stalled; 3598 } 3599 break; 3600 3601 case UT_WRITE_ENDPOINT: 3602 switch (req->bRequest) { 3603 case UR_CLEAR_FEATURE: 3604 switch (UGETW(req->wValue)) { 3605 case UF_ENDPOINT_HALT: 3606 goto tr_handle_clear_halt; 3607 case UF_DEVICE_REMOTE_WAKEUP: 3608 goto tr_handle_clear_wakeup; 3609 default: 3610 goto tr_stalled; 3611 } 3612 break; 3613 case UR_SET_FEATURE: 3614 switch (UGETW(req->wValue)) { 3615 case UF_ENDPOINT_HALT: 3616 goto tr_handle_set_halt; 3617 case UF_DEVICE_REMOTE_WAKEUP: 3618 goto tr_handle_set_wakeup; 3619 default: 3620 goto tr_stalled; 3621 } 3622 break; 3623 case UR_SYNCH_FRAME: 3624 goto tr_valid; /* nop */ 3625 default: 3626 goto tr_stalled; 3627 } 3628 break; 3629 3630 case UT_READ_ENDPOINT: 3631 switch (req->bRequest) { 3632 case UR_GET_STATUS: 3633 goto tr_handle_get_ep_status; 3634 default: 3635 goto tr_stalled; 3636 } 3637 break; 3638 3639 case UT_WRITE_INTERFACE: 3640 switch (req->bRequest) { 3641 case UR_SET_INTERFACE: 3642 goto tr_handle_set_interface; 3643 case UR_CLEAR_FEATURE: 3644 goto tr_valid; /* nop */ 3645 case UR_SET_FEATURE: 3646 default: 3647 goto tr_stalled; 3648 } 3649 break; 3650 3651 case UT_READ_INTERFACE: 3652 switch (req->bRequest) { 3653 case UR_GET_INTERFACE: 3654 goto tr_handle_get_interface; 3655 case UR_GET_STATUS: 3656 goto tr_handle_get_iface_status; 3657 default: 3658 goto tr_stalled; 3659 } 3660 break; 3661 3662 case UT_WRITE_CLASS_INTERFACE: 3663 case UT_WRITE_VENDOR_INTERFACE: 3664 /* XXX forward */ 3665 break; 3666 3667 case UT_READ_CLASS_INTERFACE: 3668 case UT_READ_VENDOR_INTERFACE: 3669 /* XXX forward */ 3670 break; 3671 3672 case UT_WRITE_CLASS_DEVICE: 3673 switch (req->bRequest) { 3674 case UR_CLEAR_FEATURE: 3675 goto tr_valid; 3676 case UR_SET_DESCRIPTOR: 3677 case UR_SET_FEATURE: 3678 break; 3679 default: 3680 goto tr_stalled; 3681 } 3682 break; 3683 3684 case UT_WRITE_CLASS_OTHER: 3685 switch (req->bRequest) { 3686 case UR_CLEAR_FEATURE: 3687 goto tr_handle_clear_port_feature; 3688 case UR_SET_FEATURE: 3689 goto tr_handle_set_port_feature; 3690 case UR_CLEAR_TT_BUFFER: 3691 case UR_RESET_TT: 3692 case UR_STOP_TT: 3693 goto tr_valid; 3694 3695 default: 3696 goto tr_stalled; 3697 } 3698 break; 3699 3700 case UT_READ_CLASS_OTHER: 3701 switch (req->bRequest) { 3702 case UR_GET_TT_STATE: 3703 goto tr_handle_get_tt_state; 3704 case UR_GET_STATUS: 3705 goto tr_handle_get_port_status; 3706 default: 3707 goto tr_stalled; 3708 } 3709 break; 3710 3711 case UT_READ_CLASS_DEVICE: 3712 switch (req->bRequest) { 3713 case UR_GET_DESCRIPTOR: 3714 goto tr_handle_get_class_descriptor; 3715 case UR_GET_STATUS: 3716 goto tr_handle_get_class_status; 3717 3718 default: 3719 goto tr_stalled; 3720 } 3721 break; 3722 default: 3723 goto tr_stalled; 3724 } 3725 goto tr_valid; 3726 3727 tr_handle_get_descriptor: 3728 switch (value >> 8) { 3729 case UDESC_DEVICE: 3730 if (value & 0xff) { 3731 goto tr_stalled; 3732 } 3733 len = sizeof(musbotg_devd); 3734 ptr = (const void *)&musbotg_devd; 3735 goto tr_valid; 3736 case UDESC_DEVICE_QUALIFIER: 3737 if (value & 0xff) { 3738 goto tr_stalled; 3739 } 3740 len = sizeof(musbotg_odevd); 3741 ptr = (const void *)&musbotg_odevd; 3742 goto tr_valid; 3743 case UDESC_CONFIG: 3744 if (value & 0xff) { 3745 goto tr_stalled; 3746 } 3747 len = sizeof(musbotg_confd); 3748 ptr = (const void *)&musbotg_confd; 3749 goto tr_valid; 3750 case UDESC_STRING: 3751 switch (value & 0xff) { 3752 case 0: /* Language table */ 3753 len = sizeof(usb_string_lang_en); 3754 ptr = (const void *)&usb_string_lang_en; 3755 goto tr_valid; 3756 3757 case 1: /* Vendor */ 3758 len = sizeof(musbotg_vendor); 3759 ptr = (const void *)&musbotg_vendor; 3760 goto tr_valid; 3761 3762 case 2: /* Product */ 3763 len = sizeof(musbotg_product); 3764 ptr = (const void *)&musbotg_product; 3765 goto tr_valid; 3766 default: 3767 break; 3768 } 3769 break; 3770 default: 3771 goto tr_stalled; 3772 } 3773 goto tr_stalled; 3774 3775 tr_handle_get_config: 3776 len = 1; 3777 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 3778 goto tr_valid; 3779 3780 tr_handle_get_status: 3781 len = 2; 3782 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 3783 goto tr_valid; 3784 3785 tr_handle_set_address: 3786 if (value & 0xFF00) { 3787 goto tr_stalled; 3788 } 3789 sc->sc_rt_addr = value; 3790 goto tr_valid; 3791 3792 tr_handle_set_config: 3793 if (value >= 2) { 3794 goto tr_stalled; 3795 } 3796 sc->sc_conf = value; 3797 goto tr_valid; 3798 3799 tr_handle_get_interface: 3800 len = 1; 3801 sc->sc_hub_temp.wValue[0] = 0; 3802 goto tr_valid; 3803 3804 tr_handle_get_tt_state: 3805 tr_handle_get_class_status: 3806 tr_handle_get_iface_status: 3807 tr_handle_get_ep_status: 3808 len = 2; 3809 USETW(sc->sc_hub_temp.wValue, 0); 3810 goto tr_valid; 3811 3812 tr_handle_set_halt: 3813 tr_handle_set_interface: 3814 tr_handle_set_wakeup: 3815 tr_handle_clear_wakeup: 3816 tr_handle_clear_halt: 3817 goto tr_valid; 3818 3819 tr_handle_clear_port_feature: 3820 if (index != 1) { 3821 goto tr_stalled; 3822 } 3823 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 3824 3825 switch (value) { 3826 case UHF_PORT_SUSPEND: 3827 if (sc->sc_mode == MUSB2_HOST_MODE) 3828 musbotg_wakeup_host(sc); 3829 else 3830 musbotg_wakeup_peer(sc); 3831 break; 3832 3833 case UHF_PORT_ENABLE: 3834 sc->sc_flags.port_enabled = 0; 3835 break; 3836 3837 case UHF_C_PORT_ENABLE: 3838 sc->sc_flags.change_enabled = 0; 3839 break; 3840 3841 case UHF_C_PORT_OVER_CURRENT: 3842 sc->sc_flags.change_over_current = 0; 3843 break; 3844 3845 case UHF_C_PORT_RESET: 3846 sc->sc_flags.change_reset = 0; 3847 break; 3848 3849 case UHF_PORT_TEST: 3850 case UHF_PORT_INDICATOR: 3851 /* nops */ 3852 break; 3853 3854 case UHF_PORT_POWER: 3855 sc->sc_flags.port_powered = 0; 3856 musbotg_pull_down(sc); 3857 musbotg_clocks_off(sc); 3858 break; 3859 case UHF_C_PORT_CONNECTION: 3860 sc->sc_flags.change_connect = 0; 3861 break; 3862 case UHF_C_PORT_SUSPEND: 3863 sc->sc_flags.change_suspend = 0; 3864 break; 3865 default: 3866 err = USB_ERR_IOERROR; 3867 goto done; 3868 } 3869 goto tr_valid; 3870 3871 tr_handle_set_port_feature: 3872 if (index != 1) { 3873 goto tr_stalled; 3874 } 3875 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 3876 3877 switch (value) { 3878 case UHF_PORT_ENABLE: 3879 sc->sc_flags.port_enabled = 1; 3880 break; 3881 case UHF_PORT_SUSPEND: 3882 if (sc->sc_mode == MUSB2_HOST_MODE) 3883 musbotg_suspend_host(sc); 3884 break; 3885 3886 case UHF_PORT_RESET: 3887 if (sc->sc_mode == MUSB2_HOST_MODE) { 3888 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3889 reg |= MUSB2_MASK_RESET; 3890 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3891 3892 /* Wait for 20 msec */ 3893 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5); 3894 3895 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3896 reg &= ~MUSB2_MASK_RESET; 3897 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3898 3899 /* determine line speed */ 3900 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3901 if (reg & MUSB2_MASK_HSMODE) 3902 sc->sc_flags.status_high_speed = 1; 3903 else 3904 sc->sc_flags.status_high_speed = 0; 3905 3906 sc->sc_flags.change_reset = 1; 3907 } else 3908 err = USB_ERR_IOERROR; 3909 break; 3910 3911 case UHF_PORT_TEST: 3912 case UHF_PORT_INDICATOR: 3913 /* nops */ 3914 break; 3915 case UHF_PORT_POWER: 3916 sc->sc_flags.port_powered = 1; 3917 break; 3918 default: 3919 err = USB_ERR_IOERROR; 3920 goto done; 3921 } 3922 goto tr_valid; 3923 3924 tr_handle_get_port_status: 3925 3926 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 3927 3928 if (index != 1) { 3929 goto tr_stalled; 3930 } 3931 if (sc->sc_flags.status_vbus) { 3932 musbotg_clocks_on(sc); 3933 musbotg_pull_up(sc); 3934 } else { 3935 musbotg_pull_down(sc); 3936 musbotg_clocks_off(sc); 3937 } 3938 3939 /* Select Device Side Mode */ 3940 if (sc->sc_mode == MUSB2_DEVICE_MODE) 3941 value = UPS_PORT_MODE_DEVICE; 3942 else 3943 value = 0; 3944 3945 if (sc->sc_flags.status_high_speed) { 3946 value |= UPS_HIGH_SPEED; 3947 } 3948 if (sc->sc_flags.port_powered) { 3949 value |= UPS_PORT_POWER; 3950 } 3951 if (sc->sc_flags.port_enabled) { 3952 value |= UPS_PORT_ENABLED; 3953 } 3954 3955 if (sc->sc_flags.port_over_current) 3956 value |= UPS_OVERCURRENT_INDICATOR; 3957 3958 if (sc->sc_flags.status_vbus && 3959 sc->sc_flags.status_bus_reset) { 3960 value |= UPS_CURRENT_CONNECT_STATUS; 3961 } 3962 if (sc->sc_flags.status_suspend) { 3963 value |= UPS_SUSPEND; 3964 } 3965 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 3966 3967 value = 0; 3968 3969 if (sc->sc_flags.change_connect) { 3970 value |= UPS_C_CONNECT_STATUS; 3971 3972 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 3973 if (sc->sc_flags.status_vbus && 3974 sc->sc_flags.status_bus_reset) { 3975 /* reset EP0 state */ 3976 sc->sc_ep0_busy = 0; 3977 sc->sc_ep0_cmd = 0; 3978 } 3979 } 3980 } 3981 if (sc->sc_flags.change_suspend) 3982 value |= UPS_C_SUSPEND; 3983 if (sc->sc_flags.change_reset) 3984 value |= UPS_C_PORT_RESET; 3985 if (sc->sc_flags.change_over_current) 3986 value |= UPS_C_OVERCURRENT_INDICATOR; 3987 3988 USETW(sc->sc_hub_temp.ps.wPortChange, value); 3989 len = sizeof(sc->sc_hub_temp.ps); 3990 goto tr_valid; 3991 3992 tr_handle_get_class_descriptor: 3993 if (value & 0xFF) { 3994 goto tr_stalled; 3995 } 3996 ptr = (const void *)&musbotg_hubd; 3997 len = sizeof(musbotg_hubd); 3998 goto tr_valid; 3999 4000 tr_stalled: 4001 err = USB_ERR_STALLED; 4002 tr_valid: 4003 done: 4004 *plength = len; 4005 *pptr = ptr; 4006 return (err); 4007 } 4008 4009 static void 4010 musbotg_xfer_setup(struct usb_setup_params *parm) 4011 { 4012 struct usb_xfer *xfer; 4013 void *last_obj; 4014 uint32_t ntd; 4015 uint32_t n; 4016 uint8_t ep_no; 4017 4018 xfer = parm->curr_xfer; 4019 4020 /* 4021 * NOTE: This driver does not use any of the parameters that 4022 * are computed from the following values. Just set some 4023 * reasonable dummies: 4024 */ 4025 parm->hc_max_packet_size = 0x400; 4026 parm->hc_max_frame_size = 0xc00; 4027 4028 if ((parm->methods == &musbotg_device_isoc_methods) || 4029 (parm->methods == &musbotg_device_intr_methods)) 4030 parm->hc_max_packet_count = 3; 4031 else 4032 parm->hc_max_packet_count = 1; 4033 4034 usbd_transfer_setup_sub(parm); 4035 4036 /* 4037 * compute maximum number of TDs 4038 */ 4039 if (parm->methods == &musbotg_device_ctrl_methods) { 4040 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 4041 4042 } else if (parm->methods == &musbotg_device_bulk_methods) { 4043 ntd = xfer->nframes + 1 /* SYNC */ ; 4044 4045 } else if (parm->methods == &musbotg_device_intr_methods) { 4046 ntd = xfer->nframes + 1 /* SYNC */ ; 4047 4048 } else if (parm->methods == &musbotg_device_isoc_methods) { 4049 ntd = xfer->nframes + 1 /* SYNC */ ; 4050 4051 } else { 4052 ntd = 0; 4053 } 4054 4055 /* 4056 * check if "usbd_transfer_setup_sub" set an error 4057 */ 4058 if (parm->err) { 4059 return; 4060 } 4061 /* 4062 * allocate transfer descriptors 4063 */ 4064 last_obj = NULL; 4065 4066 ep_no = xfer->endpointno & UE_ADDR; 4067 4068 /* 4069 * Check for a valid endpoint profile in USB device mode: 4070 */ 4071 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4072 const struct usb_hw_ep_profile *pf; 4073 4074 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4075 4076 if (pf == NULL) { 4077 /* should not happen */ 4078 parm->err = USB_ERR_INVAL; 4079 return; 4080 } 4081 } 4082 4083 /* align data */ 4084 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4085 4086 for (n = 0; n != ntd; n++) { 4087 struct musbotg_td *td; 4088 4089 if (parm->buf) { 4090 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4091 4092 /* init TD */ 4093 td->max_frame_size = xfer->max_frame_size; 4094 td->reg_max_packet = xfer->max_packet_size | 4095 ((xfer->max_packet_count - 1) << 11); 4096 td->ep_no = ep_no; 4097 td->obj_next = last_obj; 4098 4099 last_obj = td; 4100 } 4101 parm->size[0] += sizeof(*td); 4102 } 4103 4104 xfer->td_start[0] = last_obj; 4105 } 4106 4107 static void 4108 musbotg_xfer_unsetup(struct usb_xfer *xfer) 4109 { 4110 return; 4111 } 4112 4113 static void 4114 musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4115 { 4116 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4117 4118 if (sc->sc_mode == MUSB2_HOST_MODE) 4119 *pus = 2000; /* microseconds */ 4120 else 4121 *pus = 0; 4122 } 4123 4124 static void 4125 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4126 struct usb_endpoint *ep) 4127 { 4128 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4129 4130 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 4131 ep, udev->address, 4132 edesc->bEndpointAddress, udev->flags.usb_mode, 4133 sc->sc_rt_addr); 4134 4135 if (udev->device_index != sc->sc_rt_addr) { 4136 switch (edesc->bmAttributes & UE_XFERTYPE) { 4137 case UE_CONTROL: 4138 ep->methods = &musbotg_device_ctrl_methods; 4139 break; 4140 case UE_INTERRUPT: 4141 ep->methods = &musbotg_device_intr_methods; 4142 break; 4143 case UE_ISOCHRONOUS: 4144 ep->methods = &musbotg_device_isoc_methods; 4145 break; 4146 case UE_BULK: 4147 ep->methods = &musbotg_device_bulk_methods; 4148 break; 4149 default: 4150 /* do nothing */ 4151 break; 4152 } 4153 } 4154 } 4155 4156 static void 4157 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4158 { 4159 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 4160 4161 switch (state) { 4162 case USB_HW_POWER_SUSPEND: 4163 musbotg_uninit(sc); 4164 break; 4165 case USB_HW_POWER_SHUTDOWN: 4166 musbotg_uninit(sc); 4167 break; 4168 case USB_HW_POWER_RESUME: 4169 musbotg_init(sc); 4170 break; 4171 default: 4172 break; 4173 } 4174 } 4175 4176 static const struct usb_bus_methods musbotg_bus_methods = 4177 { 4178 .endpoint_init = &musbotg_ep_init, 4179 .get_dma_delay = &musbotg_get_dma_delay, 4180 .xfer_setup = &musbotg_xfer_setup, 4181 .xfer_unsetup = &musbotg_xfer_unsetup, 4182 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 4183 .xfer_stall = &musbotg_xfer_stall, 4184 .set_stall = &musbotg_set_stall, 4185 .clear_stall = &musbotg_clear_stall, 4186 .roothub_exec = &musbotg_roothub_exec, 4187 .xfer_poll = &musbotg_do_poll, 4188 .set_hw_power_sleep = &musbotg_set_hw_power_sleep, 4189 }; 4190