1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip 29 * at their homepage. 30 */ 31 32 /* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39 #ifdef USB_GLOBAL_INCLUDE_FILE 40 #include USB_GLOBAL_INCLUDE_FILE 41 #else 42 #include <sys/stdint.h> 43 #include <sys/stddef.h> 44 #include <sys/param.h> 45 #include <sys/queue.h> 46 #include <sys/types.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/module.h> 51 #include <sys/lock.h> 52 #include <sys/mutex.h> 53 #include <sys/condvar.h> 54 #include <sys/sysctl.h> 55 #include <sys/sx.h> 56 #include <sys/unistd.h> 57 #include <sys/callout.h> 58 #include <sys/malloc.h> 59 #include <sys/priv.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 64 #define USB_DEBUG_VAR musbotgdebug 65 66 #include <dev/usb/usb_core.h> 67 #include <dev/usb/usb_debug.h> 68 #include <dev/usb/usb_busdma.h> 69 #include <dev/usb/usb_process.h> 70 #include <dev/usb/usb_transfer.h> 71 #include <dev/usb/usb_device.h> 72 #include <dev/usb/usb_hub.h> 73 #include <dev/usb/usb_util.h> 74 75 #include <dev/usb/usb_controller.h> 76 #include <dev/usb/usb_bus.h> 77 #endif /* USB_GLOBAL_INCLUDE_FILE */ 78 79 #include <dev/usb/controller/musb_otg.h> 80 81 #define MUSBOTG_INTR_ENDPT 1 82 83 #define MUSBOTG_BUS2SC(bus) \ 84 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 85 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 86 87 #define MUSBOTG_PC2SC(pc) \ 88 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 89 90 #ifdef USB_DEBUG 91 static int musbotgdebug = 0; 92 93 static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 94 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RW, 95 &musbotgdebug, 0, "Debug level"); 96 #endif 97 98 #define MAX_NAK_TO 16 99 100 /* prototypes */ 101 102 struct usb_bus_methods musbotg_bus_methods; 103 struct usb_pipe_methods musbotg_device_bulk_methods; 104 struct usb_pipe_methods musbotg_device_ctrl_methods; 105 struct usb_pipe_methods musbotg_device_intr_methods; 106 struct usb_pipe_methods musbotg_device_isoc_methods; 107 108 /* Control transfers: Device mode */ 109 static musbotg_cmd_t musbotg_dev_ctrl_setup_rx; 110 static musbotg_cmd_t musbotg_dev_ctrl_data_rx; 111 static musbotg_cmd_t musbotg_dev_ctrl_data_tx; 112 static musbotg_cmd_t musbotg_dev_ctrl_status; 113 114 /* Control transfers: Host mode */ 115 static musbotg_cmd_t musbotg_host_ctrl_setup_tx; 116 static musbotg_cmd_t musbotg_host_ctrl_data_rx; 117 static musbotg_cmd_t musbotg_host_ctrl_data_tx; 118 static musbotg_cmd_t musbotg_host_ctrl_status_rx; 119 static musbotg_cmd_t musbotg_host_ctrl_status_tx; 120 121 /* Bulk, Interrupt, Isochronous: Device mode */ 122 static musbotg_cmd_t musbotg_dev_data_rx; 123 static musbotg_cmd_t musbotg_dev_data_tx; 124 125 /* Bulk, Interrupt, Isochronous: Host mode */ 126 static musbotg_cmd_t musbotg_host_data_rx; 127 static musbotg_cmd_t musbotg_host_data_tx; 128 129 static void musbotg_device_done(struct usb_xfer *, usb_error_t); 130 static void musbotg_do_poll(struct usb_bus *); 131 static void musbotg_standard_done(struct usb_xfer *); 132 static void musbotg_interrupt_poll(struct musbotg_softc *); 133 static void musbotg_root_intr(struct musbotg_softc *); 134 static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td); 135 static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td); 136 static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on); 137 138 /* 139 * Here is a configuration that the chip supports. 140 */ 141 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = { 142 143 [0] = { 144 .max_in_frame_size = 64,/* fixed */ 145 .max_out_frame_size = 64, /* fixed */ 146 .is_simplex = 1, 147 .support_control = 1, 148 } 149 }; 150 151 static int 152 musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td) 153 { 154 int ch; 155 int ep; 156 157 ep = td->ep_no; 158 159 /* In device mode each EP got its own channel */ 160 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 161 musbotg_ep_int_set(sc, ep, 1); 162 return (ep); 163 } 164 165 /* 166 * All control transactions go through EP0 167 */ 168 if (ep == 0) { 169 if (sc->sc_channel_mask & (1 << 0)) 170 return (-1); 171 sc->sc_channel_mask |= (1 << 0); 172 musbotg_ep_int_set(sc, ep, 1); 173 return (0); 174 } 175 176 for (ch = 1; ch < MUSB2_EP_MAX; ch++) { 177 if (!(sc->sc_channel_mask & (1 << ch))) { 178 sc->sc_channel_mask |= (1 << ch); 179 musbotg_ep_int_set(sc, ch, 1); 180 return (ch); 181 } 182 } 183 184 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask); 185 186 return (-1); 187 } 188 189 static void 190 musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td) 191 { 192 193 DPRINTFN(1, "ep_no=%d\n", td->channel); 194 195 if (sc->sc_mode == MUSB2_DEVICE_MODE) 196 return; 197 198 if (td == NULL) 199 return; 200 if (td->channel == -1) 201 return; 202 203 musbotg_ep_int_set(sc, td->channel, 0); 204 sc->sc_channel_mask &= ~(1 << td->channel); 205 206 td->channel = -1; 207 } 208 209 static void 210 musbotg_get_hw_ep_profile(struct usb_device *udev, 211 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 212 { 213 struct musbotg_softc *sc; 214 215 sc = MUSBOTG_BUS2SC(udev->bus); 216 217 if (ep_addr == 0) { 218 /* control endpoint */ 219 *ppf = musbotg_ep_profile; 220 } else if (ep_addr <= sc->sc_ep_max) { 221 /* other endpoints */ 222 *ppf = sc->sc_hw_ep_profile + ep_addr; 223 } else { 224 *ppf = NULL; 225 } 226 } 227 228 static void 229 musbotg_clocks_on(struct musbotg_softc *sc) 230 { 231 if (sc->sc_flags.clocks_off && 232 sc->sc_flags.port_powered) { 233 234 DPRINTFN(4, "\n"); 235 236 if (sc->sc_clocks_on) { 237 (sc->sc_clocks_on) (sc->sc_clocks_arg); 238 } 239 sc->sc_flags.clocks_off = 0; 240 241 /* XXX enable Transceiver */ 242 } 243 } 244 245 static void 246 musbotg_clocks_off(struct musbotg_softc *sc) 247 { 248 if (!sc->sc_flags.clocks_off) { 249 250 DPRINTFN(4, "\n"); 251 252 /* XXX disable Transceiver */ 253 254 if (sc->sc_clocks_off) { 255 (sc->sc_clocks_off) (sc->sc_clocks_arg); 256 } 257 sc->sc_flags.clocks_off = 1; 258 } 259 } 260 261 static void 262 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 263 { 264 uint8_t temp; 265 266 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 267 if (on) 268 temp |= MUSB2_MASK_SOFTC; 269 else 270 temp &= ~MUSB2_MASK_SOFTC; 271 272 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 273 } 274 275 static void 276 musbotg_pull_up(struct musbotg_softc *sc) 277 { 278 /* pullup D+, if possible */ 279 280 if (!sc->sc_flags.d_pulled_up && 281 sc->sc_flags.port_powered) { 282 sc->sc_flags.d_pulled_up = 1; 283 musbotg_pull_common(sc, 1); 284 } 285 } 286 287 static void 288 musbotg_pull_down(struct musbotg_softc *sc) 289 { 290 /* pulldown D+, if possible */ 291 292 if (sc->sc_flags.d_pulled_up) { 293 sc->sc_flags.d_pulled_up = 0; 294 musbotg_pull_common(sc, 0); 295 } 296 } 297 298 static void 299 musbotg_suspend_host(struct musbotg_softc *sc) 300 { 301 uint8_t temp; 302 303 if (sc->sc_flags.status_suspend) { 304 return; 305 } 306 307 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 308 temp |= MUSB2_MASK_SUSPMODE; 309 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 310 sc->sc_flags.status_suspend = 1; 311 } 312 313 static void 314 musbotg_wakeup_host(struct musbotg_softc *sc) 315 { 316 uint8_t temp; 317 318 if (!(sc->sc_flags.status_suspend)) { 319 return; 320 } 321 322 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 323 temp &= ~MUSB2_MASK_SUSPMODE; 324 temp |= MUSB2_MASK_RESUME; 325 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 326 327 /* wait 20 milliseconds */ 328 /* Wait for reset to complete. */ 329 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 330 331 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 332 temp &= ~MUSB2_MASK_RESUME; 333 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 334 335 sc->sc_flags.status_suspend = 0; 336 } 337 338 static void 339 musbotg_wakeup_peer(struct musbotg_softc *sc) 340 { 341 uint8_t temp; 342 343 if (!(sc->sc_flags.status_suspend)) { 344 return; 345 } 346 347 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 348 temp |= MUSB2_MASK_RESUME; 349 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 350 351 /* wait 8 milliseconds */ 352 /* Wait for reset to complete. */ 353 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 354 355 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 356 temp &= ~MUSB2_MASK_RESUME; 357 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 358 } 359 360 static void 361 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 362 { 363 DPRINTFN(4, "addr=%d\n", addr); 364 addr &= 0x7F; 365 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 366 } 367 368 static uint8_t 369 musbotg_dev_ctrl_setup_rx(struct musbotg_td *td) 370 { 371 struct musbotg_softc *sc; 372 struct usb_device_request req; 373 uint16_t count; 374 uint8_t csr; 375 376 /* get pointer to softc */ 377 sc = MUSBOTG_PC2SC(td->pc); 378 379 if (td->channel == -1) 380 td->channel = musbotg_channel_alloc(sc, td); 381 382 /* EP0 is busy, wait */ 383 if (td->channel == -1) 384 return (1); 385 386 DPRINTFN(1, "ep_no=%d\n", td->channel); 387 388 /* select endpoint 0 */ 389 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 390 391 /* read out FIFO status */ 392 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 393 394 DPRINTFN(4, "csr=0x%02x\n", csr); 395 396 /* 397 * NOTE: If DATAEND is set we should not call the 398 * callback, hence the status stage is not complete. 399 */ 400 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 401 /* do not stall at this point */ 402 td->did_stall = 1; 403 /* wait for interrupt */ 404 DPRINTFN(0, "CSR0 DATAEND\n"); 405 goto not_complete; 406 } 407 408 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 409 /* clear SENTSTALL */ 410 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 411 /* get latest status */ 412 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 413 /* update EP0 state */ 414 sc->sc_ep0_busy = 0; 415 } 416 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 417 /* clear SETUPEND */ 418 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 419 MUSB2_MASK_CSR0L_SETUPEND_CLR); 420 /* get latest status */ 421 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 422 /* update EP0 state */ 423 sc->sc_ep0_busy = 0; 424 } 425 if (sc->sc_ep0_busy) { 426 DPRINTFN(0, "EP0 BUSY\n"); 427 goto not_complete; 428 } 429 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 430 goto not_complete; 431 } 432 /* clear did stall flag */ 433 td->did_stall = 0; 434 /* get the packet byte count */ 435 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 436 437 /* verify data length */ 438 if (count != td->remainder) { 439 DPRINTFN(0, "Invalid SETUP packet " 440 "length, %d bytes\n", count); 441 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 442 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 443 goto not_complete; 444 } 445 if (count != sizeof(req)) { 446 DPRINTFN(0, "Unsupported SETUP packet " 447 "length, %d bytes\n", count); 448 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 449 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 450 goto not_complete; 451 } 452 /* receive data */ 453 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 454 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 455 456 /* copy data into real buffer */ 457 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 458 459 td->offset = sizeof(req); 460 td->remainder = 0; 461 462 /* set pending command */ 463 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 464 465 /* we need set stall or dataend after this */ 466 sc->sc_ep0_busy = 1; 467 468 /* sneak peek the set address */ 469 if ((req.bmRequestType == UT_WRITE_DEVICE) && 470 (req.bRequest == UR_SET_ADDRESS)) { 471 sc->sc_dv_addr = req.wValue[0] & 0x7F; 472 } else { 473 sc->sc_dv_addr = 0xFF; 474 } 475 476 musbotg_channel_free(sc, td); 477 return (0); /* complete */ 478 479 not_complete: 480 /* abort any ongoing transfer */ 481 if (!td->did_stall) { 482 DPRINTFN(4, "stalling\n"); 483 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 484 MUSB2_MASK_CSR0L_SENDSTALL); 485 td->did_stall = 1; 486 } 487 return (1); /* not complete */ 488 } 489 490 static uint8_t 491 musbotg_host_ctrl_setup_tx(struct musbotg_td *td) 492 { 493 struct musbotg_softc *sc; 494 struct usb_device_request req; 495 uint8_t csr, csrh; 496 497 /* get pointer to softc */ 498 sc = MUSBOTG_PC2SC(td->pc); 499 500 if (td->channel == -1) 501 td->channel = musbotg_channel_alloc(sc, td); 502 503 /* EP0 is busy, wait */ 504 if (td->channel == -1) 505 return (1); 506 507 DPRINTFN(1, "ep_no=%d\n", td->channel); 508 509 /* select endpoint 0 */ 510 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 511 512 /* read out FIFO status */ 513 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 514 DPRINTFN(4, "csr=0x%02x\n", csr); 515 516 /* Not ready yet yet */ 517 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 518 return (1); 519 520 /* Failed */ 521 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 522 MUSB2_MASK_CSR0L_ERROR)) 523 { 524 /* Clear status bit */ 525 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 526 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 527 td->error = 1; 528 } 529 530 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 531 DPRINTFN(1, "NAK timeout\n"); 532 533 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 534 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 535 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 536 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 537 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 538 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 539 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 540 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 541 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 542 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 543 } 544 } 545 546 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 547 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 548 549 td->error = 1; 550 } 551 552 if (td->error) { 553 musbotg_channel_free(sc, td); 554 return (0); 555 } 556 557 /* Fifo is not empty and there is no NAK timeout */ 558 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 559 return (1); 560 561 /* check if we are complete */ 562 if (td->remainder == 0) { 563 /* we are complete */ 564 musbotg_channel_free(sc, td); 565 return (0); 566 } 567 568 /* copy data into real buffer */ 569 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 570 571 /* send data */ 572 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 573 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 574 575 /* update offset and remainder */ 576 td->offset += sizeof(req); 577 td->remainder -= sizeof(req); 578 579 580 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 581 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 582 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 583 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 584 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 585 586 /* write command */ 587 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 588 MUSB2_MASK_CSR0L_TXPKTRDY | 589 MUSB2_MASK_CSR0L_SETUPPKT); 590 591 /* Just to be consistent, not used above */ 592 td->transaction_started = 1; 593 594 return (1); /* in progress */ 595 } 596 597 /* Control endpoint only data handling functions (RX/TX/SYNC) */ 598 599 static uint8_t 600 musbotg_dev_ctrl_data_rx(struct musbotg_td *td) 601 { 602 struct usb_page_search buf_res; 603 struct musbotg_softc *sc; 604 uint16_t count; 605 uint8_t csr; 606 uint8_t got_short; 607 608 /* get pointer to softc */ 609 sc = MUSBOTG_PC2SC(td->pc); 610 611 /* select endpoint 0 */ 612 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 613 614 /* check if a command is pending */ 615 if (sc->sc_ep0_cmd) { 616 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 617 sc->sc_ep0_cmd = 0; 618 } 619 /* read out FIFO status */ 620 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 621 622 DPRINTFN(4, "csr=0x%02x\n", csr); 623 624 got_short = 0; 625 626 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 627 MUSB2_MASK_CSR0L_SENTSTALL)) { 628 if (td->remainder == 0) { 629 /* 630 * We are actually complete and have 631 * received the next SETUP 632 */ 633 DPRINTFN(4, "faking complete\n"); 634 return (0); /* complete */ 635 } 636 /* 637 * USB Host Aborted the transfer. 638 */ 639 td->error = 1; 640 return (0); /* complete */ 641 } 642 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 643 return (1); /* not complete */ 644 } 645 /* get the packet byte count */ 646 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 647 648 /* verify the packet byte count */ 649 if (count != td->max_frame_size) { 650 if (count < td->max_frame_size) { 651 /* we have a short packet */ 652 td->short_pkt = 1; 653 got_short = 1; 654 } else { 655 /* invalid USB packet */ 656 td->error = 1; 657 return (0); /* we are complete */ 658 } 659 } 660 /* verify the packet byte count */ 661 if (count > td->remainder) { 662 /* invalid USB packet */ 663 td->error = 1; 664 return (0); /* we are complete */ 665 } 666 while (count > 0) { 667 uint32_t temp; 668 669 usbd_get_page(td->pc, td->offset, &buf_res); 670 671 /* get correct length */ 672 if (buf_res.length > count) { 673 buf_res.length = count; 674 } 675 /* check for unaligned memory address */ 676 if (USB_P2U(buf_res.buffer) & 3) { 677 678 temp = count & ~3; 679 680 if (temp) { 681 /* receive data 4 bytes at a time */ 682 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 683 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 684 temp / 4); 685 } 686 temp = count & 3; 687 if (temp) { 688 /* receive data 1 byte at a time */ 689 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 690 MUSB2_REG_EPFIFO(0), 691 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 692 } 693 usbd_copy_in(td->pc, td->offset, 694 sc->sc_bounce_buf, count); 695 696 /* update offset and remainder */ 697 td->offset += count; 698 td->remainder -= count; 699 break; 700 } 701 /* check if we can optimise */ 702 if (buf_res.length >= 4) { 703 704 /* receive data 4 bytes at a time */ 705 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 706 MUSB2_REG_EPFIFO(0), buf_res.buffer, 707 buf_res.length / 4); 708 709 temp = buf_res.length & ~3; 710 711 /* update counters */ 712 count -= temp; 713 td->offset += temp; 714 td->remainder -= temp; 715 continue; 716 } 717 /* receive data */ 718 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 719 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 720 721 /* update counters */ 722 count -= buf_res.length; 723 td->offset += buf_res.length; 724 td->remainder -= buf_res.length; 725 } 726 727 /* check if we are complete */ 728 if ((td->remainder == 0) || got_short) { 729 if (td->short_pkt) { 730 /* we are complete */ 731 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 732 return (0); 733 } 734 /* else need to receive a zero length packet */ 735 } 736 /* write command - need more data */ 737 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 738 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 739 return (1); /* not complete */ 740 } 741 742 static uint8_t 743 musbotg_dev_ctrl_data_tx(struct musbotg_td *td) 744 { 745 struct usb_page_search buf_res; 746 struct musbotg_softc *sc; 747 uint16_t count; 748 uint8_t csr; 749 750 /* get pointer to softc */ 751 sc = MUSBOTG_PC2SC(td->pc); 752 753 /* select endpoint 0 */ 754 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 755 756 /* check if a command is pending */ 757 if (sc->sc_ep0_cmd) { 758 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 759 sc->sc_ep0_cmd = 0; 760 } 761 /* read out FIFO status */ 762 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 763 764 DPRINTFN(4, "csr=0x%02x\n", csr); 765 766 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 767 MUSB2_MASK_CSR0L_SENTSTALL)) { 768 /* 769 * The current transfer was aborted 770 * by the USB Host 771 */ 772 td->error = 1; 773 return (0); /* complete */ 774 } 775 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 776 return (1); /* not complete */ 777 } 778 count = td->max_frame_size; 779 if (td->remainder < count) { 780 /* we have a short packet */ 781 td->short_pkt = 1; 782 count = td->remainder; 783 } 784 while (count > 0) { 785 uint32_t temp; 786 787 usbd_get_page(td->pc, td->offset, &buf_res); 788 789 /* get correct length */ 790 if (buf_res.length > count) { 791 buf_res.length = count; 792 } 793 /* check for unaligned memory address */ 794 if (USB_P2U(buf_res.buffer) & 3) { 795 796 usbd_copy_out(td->pc, td->offset, 797 sc->sc_bounce_buf, count); 798 799 temp = count & ~3; 800 801 if (temp) { 802 /* transmit data 4 bytes at a time */ 803 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 804 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 805 temp / 4); 806 } 807 temp = count & 3; 808 if (temp) { 809 /* receive data 1 byte at a time */ 810 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 811 MUSB2_REG_EPFIFO(0), 812 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 813 } 814 /* update offset and remainder */ 815 td->offset += count; 816 td->remainder -= count; 817 break; 818 } 819 /* check if we can optimise */ 820 if (buf_res.length >= 4) { 821 822 /* transmit data 4 bytes at a time */ 823 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 824 MUSB2_REG_EPFIFO(0), buf_res.buffer, 825 buf_res.length / 4); 826 827 temp = buf_res.length & ~3; 828 829 /* update counters */ 830 count -= temp; 831 td->offset += temp; 832 td->remainder -= temp; 833 continue; 834 } 835 /* transmit data */ 836 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 837 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 838 839 /* update counters */ 840 count -= buf_res.length; 841 td->offset += buf_res.length; 842 td->remainder -= buf_res.length; 843 } 844 845 /* check remainder */ 846 if (td->remainder == 0) { 847 if (td->short_pkt) { 848 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 849 return (0); /* complete */ 850 } 851 /* else we need to transmit a short packet */ 852 } 853 /* write command */ 854 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 855 MUSB2_MASK_CSR0L_TXPKTRDY); 856 857 return (1); /* not complete */ 858 } 859 860 static uint8_t 861 musbotg_host_ctrl_data_rx(struct musbotg_td *td) 862 { 863 struct usb_page_search buf_res; 864 struct musbotg_softc *sc; 865 uint16_t count; 866 uint8_t csr; 867 uint8_t got_short; 868 869 /* get pointer to softc */ 870 sc = MUSBOTG_PC2SC(td->pc); 871 872 if (td->channel == -1) 873 td->channel = musbotg_channel_alloc(sc, td); 874 875 /* EP0 is busy, wait */ 876 if (td->channel == -1) 877 return (1); 878 879 DPRINTFN(1, "ep_no=%d\n", td->channel); 880 881 /* select endpoint 0 */ 882 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 883 884 /* read out FIFO status */ 885 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 886 887 DPRINTFN(4, "csr=0x%02x\n", csr); 888 889 got_short = 0; 890 if (!td->transaction_started) { 891 td->transaction_started = 1; 892 893 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 894 895 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 896 td->dev_addr); 897 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 898 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 899 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 900 901 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 902 MUSB2_MASK_CSR0L_REQPKT); 903 904 return (1); 905 } 906 907 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 908 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 909 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 910 911 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 912 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 913 914 td->error = 1; 915 } 916 917 /* Failed */ 918 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 919 MUSB2_MASK_CSR0L_ERROR)) 920 { 921 /* Clear status bit */ 922 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 923 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 924 td->error = 1; 925 } 926 927 if (td->error) { 928 musbotg_channel_free(sc, td); 929 return (0); /* we are complete */ 930 } 931 932 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) 933 return (1); /* not yet */ 934 935 /* get the packet byte count */ 936 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 937 938 /* verify the packet byte count */ 939 if (count != td->max_frame_size) { 940 if (count < td->max_frame_size) { 941 /* we have a short packet */ 942 td->short_pkt = 1; 943 got_short = 1; 944 } else { 945 /* invalid USB packet */ 946 td->error = 1; 947 musbotg_channel_free(sc, td); 948 return (0); /* we are complete */ 949 } 950 } 951 /* verify the packet byte count */ 952 if (count > td->remainder) { 953 /* invalid USB packet */ 954 td->error = 1; 955 musbotg_channel_free(sc, td); 956 return (0); /* we are complete */ 957 } 958 while (count > 0) { 959 uint32_t temp; 960 961 usbd_get_page(td->pc, td->offset, &buf_res); 962 963 /* get correct length */ 964 if (buf_res.length > count) { 965 buf_res.length = count; 966 } 967 /* check for unaligned memory address */ 968 if (USB_P2U(buf_res.buffer) & 3) { 969 970 temp = count & ~3; 971 972 if (temp) { 973 /* receive data 4 bytes at a time */ 974 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 975 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 976 temp / 4); 977 } 978 temp = count & 3; 979 if (temp) { 980 /* receive data 1 byte at a time */ 981 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 982 MUSB2_REG_EPFIFO(0), 983 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 984 } 985 usbd_copy_in(td->pc, td->offset, 986 sc->sc_bounce_buf, count); 987 988 /* update offset and remainder */ 989 td->offset += count; 990 td->remainder -= count; 991 break; 992 } 993 /* check if we can optimise */ 994 if (buf_res.length >= 4) { 995 996 /* receive data 4 bytes at a time */ 997 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 998 MUSB2_REG_EPFIFO(0), buf_res.buffer, 999 buf_res.length / 4); 1000 1001 temp = buf_res.length & ~3; 1002 1003 /* update counters */ 1004 count -= temp; 1005 td->offset += temp; 1006 td->remainder -= temp; 1007 continue; 1008 } 1009 /* receive data */ 1010 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1011 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 1012 1013 /* update counters */ 1014 count -= buf_res.length; 1015 td->offset += buf_res.length; 1016 td->remainder -= buf_res.length; 1017 } 1018 1019 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY; 1020 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1021 1022 /* check if we are complete */ 1023 if ((td->remainder == 0) || got_short) { 1024 if (td->short_pkt) { 1025 /* we are complete */ 1026 1027 musbotg_channel_free(sc, td); 1028 return (0); 1029 } 1030 /* else need to receive a zero length packet */ 1031 } 1032 1033 td->transaction_started = 1; 1034 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1035 MUSB2_MASK_CSR0L_REQPKT); 1036 1037 return (1); /* not complete */ 1038 } 1039 1040 static uint8_t 1041 musbotg_host_ctrl_data_tx(struct musbotg_td *td) 1042 { 1043 struct usb_page_search buf_res; 1044 struct musbotg_softc *sc; 1045 uint16_t count; 1046 uint8_t csr, csrh; 1047 1048 /* get pointer to softc */ 1049 sc = MUSBOTG_PC2SC(td->pc); 1050 1051 if (td->channel == -1) 1052 td->channel = musbotg_channel_alloc(sc, td); 1053 1054 /* No free EPs */ 1055 if (td->channel == -1) 1056 return (1); 1057 1058 DPRINTFN(1, "ep_no=%d\n", td->channel); 1059 1060 /* select endpoint */ 1061 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1062 1063 /* read out FIFO status */ 1064 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1065 DPRINTFN(4, "csr=0x%02x\n", csr); 1066 1067 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1068 MUSB2_MASK_CSR0L_ERROR)) { 1069 /* clear status bits */ 1070 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1071 td->error = 1; 1072 } 1073 1074 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) { 1075 1076 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1077 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1078 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1079 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1080 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1081 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1082 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1083 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1084 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1085 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1086 } 1087 } 1088 1089 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1090 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1091 1092 td->error = 1; 1093 } 1094 1095 1096 if (td->error) { 1097 musbotg_channel_free(sc, td); 1098 return (0); /* complete */ 1099 } 1100 1101 /* 1102 * Wait while FIFO is empty. 1103 * Do not flush it because it will cause transactions 1104 * with size more then packet size. It might upset 1105 * some devices 1106 */ 1107 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) 1108 return (1); 1109 1110 /* Packet still being processed */ 1111 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1112 return (1); 1113 1114 if (td->transaction_started) { 1115 /* check remainder */ 1116 if (td->remainder == 0) { 1117 if (td->short_pkt) { 1118 musbotg_channel_free(sc, td); 1119 return (0); /* complete */ 1120 } 1121 /* else we need to transmit a short packet */ 1122 } 1123 1124 /* We're not complete - more transactions required */ 1125 td->transaction_started = 0; 1126 } 1127 1128 /* check for short packet */ 1129 count = td->max_frame_size; 1130 if (td->remainder < count) { 1131 /* we have a short packet */ 1132 td->short_pkt = 1; 1133 count = td->remainder; 1134 } 1135 1136 while (count > 0) { 1137 uint32_t temp; 1138 1139 usbd_get_page(td->pc, td->offset, &buf_res); 1140 1141 /* get correct length */ 1142 if (buf_res.length > count) { 1143 buf_res.length = count; 1144 } 1145 /* check for unaligned memory address */ 1146 if (USB_P2U(buf_res.buffer) & 3) { 1147 1148 usbd_copy_out(td->pc, td->offset, 1149 sc->sc_bounce_buf, count); 1150 1151 temp = count & ~3; 1152 1153 if (temp) { 1154 /* transmit data 4 bytes at a time */ 1155 bus_space_write_multi_4(sc->sc_io_tag, 1156 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), 1157 sc->sc_bounce_buf, temp / 4); 1158 } 1159 temp = count & 3; 1160 if (temp) { 1161 /* receive data 1 byte at a time */ 1162 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1163 MUSB2_REG_EPFIFO(0), 1164 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1165 } 1166 /* update offset and remainder */ 1167 td->offset += count; 1168 td->remainder -= count; 1169 break; 1170 } 1171 /* check if we can optimise */ 1172 if (buf_res.length >= 4) { 1173 1174 /* transmit data 4 bytes at a time */ 1175 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1176 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1177 buf_res.length / 4); 1178 1179 temp = buf_res.length & ~3; 1180 1181 /* update counters */ 1182 count -= temp; 1183 td->offset += temp; 1184 td->remainder -= temp; 1185 continue; 1186 } 1187 /* transmit data */ 1188 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1189 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1190 buf_res.length); 1191 1192 /* update counters */ 1193 count -= buf_res.length; 1194 td->offset += buf_res.length; 1195 td->remainder -= buf_res.length; 1196 } 1197 1198 /* Function address */ 1199 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1200 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1201 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1202 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1203 1204 /* TX NAK timeout */ 1205 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1206 1207 /* write command */ 1208 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1209 MUSB2_MASK_CSR0L_TXPKTRDY); 1210 1211 td->transaction_started = 1; 1212 1213 return (1); /* not complete */ 1214 } 1215 1216 static uint8_t 1217 musbotg_dev_ctrl_status(struct musbotg_td *td) 1218 { 1219 struct musbotg_softc *sc; 1220 uint8_t csr; 1221 1222 /* get pointer to softc */ 1223 sc = MUSBOTG_PC2SC(td->pc); 1224 1225 /* select endpoint 0 */ 1226 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1227 1228 if (sc->sc_ep0_busy) { 1229 sc->sc_ep0_busy = 0; 1230 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 1231 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 1232 sc->sc_ep0_cmd = 0; 1233 } 1234 /* read out FIFO status */ 1235 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1236 1237 DPRINTFN(4, "csr=0x%02x\n", csr); 1238 1239 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 1240 /* wait for interrupt */ 1241 return (1); /* not complete */ 1242 } 1243 if (sc->sc_dv_addr != 0xFF) { 1244 /* write function address */ 1245 musbotg_set_address(sc, sc->sc_dv_addr); 1246 } 1247 1248 musbotg_channel_free(sc, td); 1249 return (0); /* complete */ 1250 } 1251 1252 static uint8_t 1253 musbotg_host_ctrl_status_rx(struct musbotg_td *td) 1254 { 1255 struct musbotg_softc *sc; 1256 uint8_t csr, csrh; 1257 1258 /* get pointer to softc */ 1259 sc = MUSBOTG_PC2SC(td->pc); 1260 1261 if (td->channel == -1) 1262 td->channel = musbotg_channel_alloc(sc, td); 1263 1264 /* EP0 is busy, wait */ 1265 if (td->channel == -1) 1266 return (1); 1267 1268 DPRINTFN(1, "ep_no=%d\n", td->channel); 1269 1270 /* select endpoint 0 */ 1271 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1272 1273 if (!td->transaction_started) { 1274 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 1275 td->dev_addr); 1276 1277 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 1278 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 1279 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1280 1281 /* RX NAK timeout */ 1282 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1283 1284 td->transaction_started = 1; 1285 1286 /* Disable PING */ 1287 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1288 csrh |= MUSB2_MASK_CSR0H_PING_DIS; 1289 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1290 1291 /* write command */ 1292 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1293 MUSB2_MASK_CSR0L_STATUSPKT | 1294 MUSB2_MASK_CSR0L_REQPKT); 1295 1296 return (1); /* Just started */ 1297 1298 } 1299 1300 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1301 1302 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr); 1303 1304 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) { 1305 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1306 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 1307 musbotg_channel_free(sc, td); 1308 return (0); /* complete */ 1309 } 1310 1311 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1312 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT | 1313 MUSB2_MASK_CSR0L_REQPKT); 1314 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1315 1316 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1317 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1318 td->error = 1; 1319 } 1320 1321 /* Failed */ 1322 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1323 MUSB2_MASK_CSR0L_ERROR)) 1324 { 1325 /* Clear status bit */ 1326 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1327 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1328 td->error = 1; 1329 } 1330 1331 if (td->error) { 1332 musbotg_channel_free(sc, td); 1333 return (0); 1334 } 1335 1336 return (1); /* Not ready yet */ 1337 } 1338 1339 static uint8_t 1340 musbotg_host_ctrl_status_tx(struct musbotg_td *td) 1341 { 1342 struct musbotg_softc *sc; 1343 uint8_t csr; 1344 1345 /* get pointer to softc */ 1346 sc = MUSBOTG_PC2SC(td->pc); 1347 1348 if (td->channel == -1) 1349 td->channel = musbotg_channel_alloc(sc, td); 1350 1351 /* EP0 is busy, wait */ 1352 if (td->channel == -1) 1353 return (1); 1354 1355 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started, 1356 td->dev_addr,td->haddr,td->hport, td->transfer_type); 1357 1358 /* select endpoint 0 */ 1359 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1360 1361 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1362 DPRINTFN(4, "csr=0x%02x\n", csr); 1363 1364 /* Not yet */ 1365 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1366 return (1); 1367 1368 /* Failed */ 1369 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1370 MUSB2_MASK_CSR0L_ERROR)) 1371 { 1372 /* Clear status bit */ 1373 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1374 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1375 td->error = 1; 1376 musbotg_channel_free(sc, td); 1377 return (0); /* complete */ 1378 } 1379 1380 if (td->transaction_started) { 1381 musbotg_channel_free(sc, td); 1382 return (0); /* complete */ 1383 } 1384 1385 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS); 1386 1387 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1388 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1389 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1390 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1391 1392 /* TX NAK timeout */ 1393 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1394 1395 td->transaction_started = 1; 1396 1397 /* write command */ 1398 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1399 MUSB2_MASK_CSR0L_STATUSPKT | 1400 MUSB2_MASK_CSR0L_TXPKTRDY); 1401 1402 return (1); /* wait for interrupt */ 1403 } 1404 1405 static uint8_t 1406 musbotg_dev_data_rx(struct musbotg_td *td) 1407 { 1408 struct usb_page_search buf_res; 1409 struct musbotg_softc *sc; 1410 uint16_t count; 1411 uint8_t csr; 1412 uint8_t to; 1413 uint8_t got_short; 1414 1415 to = 8; /* don't loop forever! */ 1416 got_short = 0; 1417 1418 /* get pointer to softc */ 1419 sc = MUSBOTG_PC2SC(td->pc); 1420 1421 if (td->channel == -1) 1422 td->channel = musbotg_channel_alloc(sc, td); 1423 1424 /* EP0 is busy, wait */ 1425 if (td->channel == -1) 1426 return (1); 1427 1428 /* select endpoint */ 1429 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1430 1431 repeat: 1432 /* read out FIFO status */ 1433 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1434 1435 DPRINTFN(4, "csr=0x%02x\n", csr); 1436 1437 /* clear overrun */ 1438 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 1439 /* make sure we don't clear "RXPKTRDY" */ 1440 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1441 MUSB2_MASK_CSRL_RXPKTRDY); 1442 } 1443 1444 /* check status */ 1445 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) 1446 return (1); /* not complete */ 1447 1448 /* get the packet byte count */ 1449 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1450 1451 DPRINTFN(4, "count=0x%04x\n", count); 1452 1453 /* 1454 * Check for short or invalid packet: 1455 */ 1456 if (count != td->max_frame_size) { 1457 if (count < td->max_frame_size) { 1458 /* we have a short packet */ 1459 td->short_pkt = 1; 1460 got_short = 1; 1461 } else { 1462 /* invalid USB packet */ 1463 td->error = 1; 1464 musbotg_channel_free(sc, td); 1465 return (0); /* we are complete */ 1466 } 1467 } 1468 /* verify the packet byte count */ 1469 if (count > td->remainder) { 1470 /* invalid USB packet */ 1471 td->error = 1; 1472 musbotg_channel_free(sc, td); 1473 return (0); /* we are complete */ 1474 } 1475 while (count > 0) { 1476 uint32_t temp; 1477 1478 usbd_get_page(td->pc, td->offset, &buf_res); 1479 1480 /* get correct length */ 1481 if (buf_res.length > count) { 1482 buf_res.length = count; 1483 } 1484 /* check for unaligned memory address */ 1485 if (USB_P2U(buf_res.buffer) & 3) { 1486 1487 temp = count & ~3; 1488 1489 if (temp) { 1490 /* receive data 4 bytes at a time */ 1491 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1492 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1493 temp / 4); 1494 } 1495 temp = count & 3; 1496 if (temp) { 1497 /* receive data 1 byte at a time */ 1498 bus_space_read_multi_1(sc->sc_io_tag, 1499 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1500 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1501 } 1502 usbd_copy_in(td->pc, td->offset, 1503 sc->sc_bounce_buf, count); 1504 1505 /* update offset and remainder */ 1506 td->offset += count; 1507 td->remainder -= count; 1508 break; 1509 } 1510 /* check if we can optimise */ 1511 if (buf_res.length >= 4) { 1512 1513 /* receive data 4 bytes at a time */ 1514 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1515 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1516 buf_res.length / 4); 1517 1518 temp = buf_res.length & ~3; 1519 1520 /* update counters */ 1521 count -= temp; 1522 td->offset += temp; 1523 td->remainder -= temp; 1524 continue; 1525 } 1526 /* receive data */ 1527 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1528 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1529 buf_res.length); 1530 1531 /* update counters */ 1532 count -= buf_res.length; 1533 td->offset += buf_res.length; 1534 td->remainder -= buf_res.length; 1535 } 1536 1537 /* clear status bits */ 1538 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1539 1540 /* check if we are complete */ 1541 if ((td->remainder == 0) || got_short) { 1542 if (td->short_pkt) { 1543 /* we are complete */ 1544 musbotg_channel_free(sc, td); 1545 return (0); 1546 } 1547 /* else need to receive a zero length packet */ 1548 } 1549 if (--to) { 1550 goto repeat; 1551 } 1552 return (1); /* not complete */ 1553 } 1554 1555 static uint8_t 1556 musbotg_dev_data_tx(struct musbotg_td *td) 1557 { 1558 struct usb_page_search buf_res; 1559 struct musbotg_softc *sc; 1560 uint16_t count; 1561 uint8_t csr; 1562 uint8_t to; 1563 1564 to = 8; /* don't loop forever! */ 1565 1566 /* get pointer to softc */ 1567 sc = MUSBOTG_PC2SC(td->pc); 1568 1569 if (td->channel == -1) 1570 td->channel = musbotg_channel_alloc(sc, td); 1571 1572 /* EP0 is busy, wait */ 1573 if (td->channel == -1) 1574 return (1); 1575 1576 /* select endpoint */ 1577 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1578 1579 repeat: 1580 1581 /* read out FIFO status */ 1582 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1583 1584 DPRINTFN(4, "csr=0x%02x\n", csr); 1585 1586 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 1587 MUSB2_MASK_CSRL_TXUNDERRUN)) { 1588 /* clear status bits */ 1589 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1590 } 1591 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 1592 return (1); /* not complete */ 1593 } 1594 /* check for short packet */ 1595 count = td->max_frame_size; 1596 if (td->remainder < count) { 1597 /* we have a short packet */ 1598 td->short_pkt = 1; 1599 count = td->remainder; 1600 } 1601 while (count > 0) { 1602 uint32_t temp; 1603 1604 usbd_get_page(td->pc, td->offset, &buf_res); 1605 1606 /* get correct length */ 1607 if (buf_res.length > count) { 1608 buf_res.length = count; 1609 } 1610 /* check for unaligned memory address */ 1611 if (USB_P2U(buf_res.buffer) & 3) { 1612 1613 usbd_copy_out(td->pc, td->offset, 1614 sc->sc_bounce_buf, count); 1615 1616 temp = count & ~3; 1617 1618 if (temp) { 1619 /* transmit data 4 bytes at a time */ 1620 bus_space_write_multi_4(sc->sc_io_tag, 1621 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1622 sc->sc_bounce_buf, temp / 4); 1623 } 1624 temp = count & 3; 1625 if (temp) { 1626 /* receive data 1 byte at a time */ 1627 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1628 MUSB2_REG_EPFIFO(td->channel), 1629 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1630 } 1631 /* update offset and remainder */ 1632 td->offset += count; 1633 td->remainder -= count; 1634 break; 1635 } 1636 /* check if we can optimise */ 1637 if (buf_res.length >= 4) { 1638 1639 /* transmit data 4 bytes at a time */ 1640 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1641 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1642 buf_res.length / 4); 1643 1644 temp = buf_res.length & ~3; 1645 1646 /* update counters */ 1647 count -= temp; 1648 td->offset += temp; 1649 td->remainder -= temp; 1650 continue; 1651 } 1652 /* transmit data */ 1653 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1654 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1655 buf_res.length); 1656 1657 /* update counters */ 1658 count -= buf_res.length; 1659 td->offset += buf_res.length; 1660 td->remainder -= buf_res.length; 1661 } 1662 1663 /* Max packet size */ 1664 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, td->max_packet); 1665 1666 /* write command */ 1667 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1668 MUSB2_MASK_CSRL_TXPKTRDY); 1669 1670 /* check remainder */ 1671 if (td->remainder == 0) { 1672 if (td->short_pkt) { 1673 musbotg_channel_free(sc, td); 1674 return (0); /* complete */ 1675 } 1676 /* else we need to transmit a short packet */ 1677 } 1678 if (--to) { 1679 goto repeat; 1680 } 1681 return (1); /* not complete */ 1682 } 1683 1684 static uint8_t 1685 musbotg_host_data_rx(struct musbotg_td *td) 1686 { 1687 struct usb_page_search buf_res; 1688 struct musbotg_softc *sc; 1689 uint16_t count; 1690 uint8_t csr, csrh; 1691 uint8_t to; 1692 uint8_t got_short; 1693 1694 /* get pointer to softc */ 1695 sc = MUSBOTG_PC2SC(td->pc); 1696 1697 if (td->channel == -1) 1698 td->channel = musbotg_channel_alloc(sc, td); 1699 1700 /* No free EPs */ 1701 if (td->channel == -1) 1702 return (1); 1703 1704 DPRINTFN(1, "ep_no=%d\n", td->channel); 1705 1706 to = 8; /* don't loop forever! */ 1707 got_short = 0; 1708 1709 /* select endpoint */ 1710 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1711 1712 repeat: 1713 /* read out FIFO status */ 1714 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1715 DPRINTFN(4, "csr=0x%02x\n", csr); 1716 1717 if (!td->transaction_started) { 1718 /* Function address */ 1719 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel), 1720 td->dev_addr); 1721 1722 /* SPLIT transaction */ 1723 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel), 1724 td->haddr); 1725 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel), 1726 td->hport); 1727 1728 /* RX NAK timeout */ 1729 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1730 1731 /* Protocol, speed, device endpoint */ 1732 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1733 1734 /* Max packet size */ 1735 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, td->max_packet); 1736 1737 /* Data Toggle */ 1738 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1739 DPRINTFN(4, "csrh=0x%02x\n", csrh); 1740 1741 csrh |= MUSB2_MASK_CSRH_RXDT_WREN; 1742 if (td->toggle) 1743 csrh |= MUSB2_MASK_CSRH_RXDT_VAL; 1744 else 1745 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1746 1747 /* Set data toggle */ 1748 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1749 1750 /* write command */ 1751 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1752 MUSB2_MASK_CSRL_RXREQPKT); 1753 1754 td->transaction_started = 1; 1755 return (1); 1756 } 1757 1758 /* clear NAK timeout */ 1759 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1760 DPRINTFN(4, "NAK Timeout\n"); 1761 if (csr & MUSB2_MASK_CSRL_RXREQPKT) { 1762 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1763 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1764 1765 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1766 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1767 } 1768 1769 td->error = 1; 1770 } 1771 1772 if (csr & MUSB2_MASK_CSRL_RXERROR) { 1773 DPRINTFN(4, "RXERROR\n"); 1774 td->error = 1; 1775 } 1776 1777 if (csr & MUSB2_MASK_CSRL_RXSTALL) { 1778 DPRINTFN(4, "RXSTALL\n"); 1779 td->error = 1; 1780 } 1781 1782 if (td->error) { 1783 musbotg_channel_free(sc, td); 1784 return (0); /* we are complete */ 1785 } 1786 1787 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 1788 /* No data available yet */ 1789 return (1); 1790 } 1791 1792 td->toggle ^= 1; 1793 /* get the packet byte count */ 1794 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1795 DPRINTFN(4, "count=0x%04x\n", count); 1796 1797 /* 1798 * Check for short or invalid packet: 1799 */ 1800 if (count != td->max_frame_size) { 1801 if (count < td->max_frame_size) { 1802 /* we have a short packet */ 1803 td->short_pkt = 1; 1804 got_short = 1; 1805 } else { 1806 /* invalid USB packet */ 1807 td->error = 1; 1808 musbotg_channel_free(sc, td); 1809 return (0); /* we are complete */ 1810 } 1811 } 1812 1813 /* verify the packet byte count */ 1814 if (count > td->remainder) { 1815 /* invalid USB packet */ 1816 td->error = 1; 1817 musbotg_channel_free(sc, td); 1818 return (0); /* we are complete */ 1819 } 1820 1821 while (count > 0) { 1822 uint32_t temp; 1823 1824 usbd_get_page(td->pc, td->offset, &buf_res); 1825 1826 /* get correct length */ 1827 if (buf_res.length > count) { 1828 buf_res.length = count; 1829 } 1830 /* check for unaligned memory address */ 1831 if (USB_P2U(buf_res.buffer) & 3) { 1832 1833 temp = count & ~3; 1834 1835 if (temp) { 1836 /* receive data 4 bytes at a time */ 1837 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1838 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1839 temp / 4); 1840 } 1841 temp = count & 3; 1842 if (temp) { 1843 /* receive data 1 byte at a time */ 1844 bus_space_read_multi_1(sc->sc_io_tag, 1845 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1846 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1847 } 1848 usbd_copy_in(td->pc, td->offset, 1849 sc->sc_bounce_buf, count); 1850 1851 /* update offset and remainder */ 1852 td->offset += count; 1853 td->remainder -= count; 1854 break; 1855 } 1856 /* check if we can optimise */ 1857 if (buf_res.length >= 4) { 1858 1859 /* receive data 4 bytes at a time */ 1860 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1861 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1862 buf_res.length / 4); 1863 1864 temp = buf_res.length & ~3; 1865 1866 /* update counters */ 1867 count -= temp; 1868 td->offset += temp; 1869 td->remainder -= temp; 1870 continue; 1871 } 1872 /* receive data */ 1873 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1874 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1875 buf_res.length); 1876 1877 /* update counters */ 1878 count -= buf_res.length; 1879 td->offset += buf_res.length; 1880 td->remainder -= buf_res.length; 1881 } 1882 1883 /* clear status bits */ 1884 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1885 1886 /* check if we are complete */ 1887 if ((td->remainder == 0) || got_short) { 1888 if (td->short_pkt) { 1889 /* we are complete */ 1890 musbotg_channel_free(sc, td); 1891 return (0); 1892 } 1893 /* else need to receive a zero length packet */ 1894 } 1895 1896 /* Reset transaction state and restart */ 1897 td->transaction_started = 0; 1898 1899 if (--to) 1900 goto repeat; 1901 1902 return (1); /* not complete */ 1903 } 1904 1905 static uint8_t 1906 musbotg_host_data_tx(struct musbotg_td *td) 1907 { 1908 struct usb_page_search buf_res; 1909 struct musbotg_softc *sc; 1910 uint16_t count; 1911 uint8_t csr, csrh; 1912 1913 /* get pointer to softc */ 1914 sc = MUSBOTG_PC2SC(td->pc); 1915 1916 if (td->channel == -1) 1917 td->channel = musbotg_channel_alloc(sc, td); 1918 1919 /* No free EPs */ 1920 if (td->channel == -1) 1921 return (1); 1922 1923 DPRINTFN(1, "ep_no=%d\n", td->channel); 1924 1925 /* select endpoint */ 1926 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1927 1928 /* read out FIFO status */ 1929 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1930 DPRINTFN(4, "csr=0x%02x\n", csr); 1931 1932 if (csr & (MUSB2_MASK_CSRL_TXSTALLED | 1933 MUSB2_MASK_CSRL_TXERROR)) { 1934 /* clear status bits */ 1935 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1936 td->error = 1; 1937 musbotg_channel_free(sc, td); 1938 return (0); /* complete */ 1939 } 1940 1941 if (csr & MUSB2_MASK_CSRL_TXNAKTO ) { 1942 /* 1943 * Flush TX FIFO before clearing NAK TO 1944 */ 1945 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1946 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1947 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1948 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1949 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1950 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1951 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1952 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1953 } 1954 } 1955 1956 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 1957 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1958 1959 td->error = 1; 1960 musbotg_channel_free(sc, td); 1961 return (0); /* complete */ 1962 } 1963 1964 /* 1965 * Wait while FIFO is empty. 1966 * Do not flush it because it will cause transactions 1967 * with size more then packet size. It might upset 1968 * some devices 1969 */ 1970 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) 1971 return (1); 1972 1973 /* Packet still being processed */ 1974 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) 1975 return (1); 1976 1977 if (td->transaction_started) { 1978 /* check remainder */ 1979 if (td->remainder == 0) { 1980 if (td->short_pkt) { 1981 musbotg_channel_free(sc, td); 1982 return (0); /* complete */ 1983 } 1984 /* else we need to transmit a short packet */ 1985 } 1986 1987 /* We're not complete - more transactions required */ 1988 td->transaction_started = 0; 1989 } 1990 1991 /* check for short packet */ 1992 count = td->max_frame_size; 1993 if (td->remainder < count) { 1994 /* we have a short packet */ 1995 td->short_pkt = 1; 1996 count = td->remainder; 1997 } 1998 1999 while (count > 0) { 2000 uint32_t temp; 2001 2002 usbd_get_page(td->pc, td->offset, &buf_res); 2003 2004 /* get correct length */ 2005 if (buf_res.length > count) { 2006 buf_res.length = count; 2007 } 2008 /* check for unaligned memory address */ 2009 if (USB_P2U(buf_res.buffer) & 3) { 2010 2011 usbd_copy_out(td->pc, td->offset, 2012 sc->sc_bounce_buf, count); 2013 2014 temp = count & ~3; 2015 2016 if (temp) { 2017 /* transmit data 4 bytes at a time */ 2018 bus_space_write_multi_4(sc->sc_io_tag, 2019 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 2020 sc->sc_bounce_buf, temp / 4); 2021 } 2022 temp = count & 3; 2023 if (temp) { 2024 /* receive data 1 byte at a time */ 2025 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2026 MUSB2_REG_EPFIFO(td->channel), 2027 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 2028 } 2029 /* update offset and remainder */ 2030 td->offset += count; 2031 td->remainder -= count; 2032 break; 2033 } 2034 /* check if we can optimise */ 2035 if (buf_res.length >= 4) { 2036 2037 /* transmit data 4 bytes at a time */ 2038 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 2039 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2040 buf_res.length / 4); 2041 2042 temp = buf_res.length & ~3; 2043 2044 /* update counters */ 2045 count -= temp; 2046 td->offset += temp; 2047 td->remainder -= temp; 2048 continue; 2049 } 2050 /* transmit data */ 2051 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2052 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2053 buf_res.length); 2054 2055 /* update counters */ 2056 count -= buf_res.length; 2057 td->offset += buf_res.length; 2058 td->remainder -= buf_res.length; 2059 } 2060 2061 /* Function address */ 2062 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel), 2063 td->dev_addr); 2064 2065 /* SPLIT transaction */ 2066 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel), 2067 td->haddr); 2068 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel), 2069 td->hport); 2070 2071 /* TX NAK timeout */ 2072 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 2073 2074 /* Protocol, speed, device endpoint */ 2075 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 2076 2077 /* Max packet size */ 2078 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, td->max_packet); 2079 2080 if (!td->transaction_started) { 2081 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 2082 DPRINTFN(4, "csrh=0x%02x\n", csrh); 2083 2084 csrh |= MUSB2_MASK_CSRH_TXDT_WREN; 2085 if (td->toggle) 2086 csrh |= MUSB2_MASK_CSRH_TXDT_VAL; 2087 else 2088 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2089 2090 /* Set data toggle */ 2091 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 2092 } 2093 2094 /* write command */ 2095 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2096 MUSB2_MASK_CSRL_TXPKTRDY); 2097 2098 /* Update Data Toggle */ 2099 td->toggle ^= 1; 2100 td->transaction_started = 1; 2101 2102 return (1); /* not complete */ 2103 } 2104 2105 static uint8_t 2106 musbotg_xfer_do_fifo(struct usb_xfer *xfer) 2107 { 2108 struct musbotg_softc *sc; 2109 struct musbotg_td *td; 2110 2111 DPRINTFN(8, "\n"); 2112 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2113 2114 td = xfer->td_transfer_cache; 2115 while (1) { 2116 2117 if ((td->func) (td)) { 2118 /* operation in progress */ 2119 break; 2120 } 2121 2122 if (((void *)td) == xfer->td_transfer_last) { 2123 goto done; 2124 } 2125 if (td->error) { 2126 goto done; 2127 } else if (td->remainder > 0) { 2128 /* 2129 * We had a short transfer. If there is no alternate 2130 * next, stop processing ! 2131 */ 2132 if (!td->alt_next) { 2133 goto done; 2134 } 2135 } 2136 /* 2137 * Fetch the next transfer descriptor and transfer 2138 * some flags to the next transfer descriptor 2139 */ 2140 td = td->obj_next; 2141 xfer->td_transfer_cache = td; 2142 } 2143 2144 return (1); /* not complete */ 2145 done: 2146 /* compute all actual lengths */ 2147 musbotg_standard_done(xfer); 2148 2149 return (0); /* complete */ 2150 } 2151 2152 static void 2153 musbotg_interrupt_poll(struct musbotg_softc *sc) 2154 { 2155 struct usb_xfer *xfer; 2156 2157 repeat: 2158 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2159 if (!musbotg_xfer_do_fifo(xfer)) { 2160 /* queue has been modified */ 2161 goto repeat; 2162 } 2163 } 2164 } 2165 2166 void 2167 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 2168 { 2169 DPRINTFN(4, "vbus = %u\n", is_on); 2170 2171 USB_BUS_LOCK(&sc->sc_bus); 2172 if (is_on) { 2173 if (!sc->sc_flags.status_vbus) { 2174 sc->sc_flags.status_vbus = 1; 2175 2176 /* complete root HUB interrupt endpoint */ 2177 musbotg_root_intr(sc); 2178 } 2179 } else { 2180 if (sc->sc_flags.status_vbus) { 2181 sc->sc_flags.status_vbus = 0; 2182 sc->sc_flags.status_bus_reset = 0; 2183 sc->sc_flags.status_suspend = 0; 2184 sc->sc_flags.change_suspend = 0; 2185 sc->sc_flags.change_connect = 1; 2186 2187 /* complete root HUB interrupt endpoint */ 2188 musbotg_root_intr(sc); 2189 } 2190 } 2191 2192 USB_BUS_UNLOCK(&sc->sc_bus); 2193 } 2194 2195 void 2196 musbotg_connect_interrupt(struct musbotg_softc *sc) 2197 { 2198 USB_BUS_LOCK(&sc->sc_bus); 2199 sc->sc_flags.change_connect = 1; 2200 2201 /* complete root HUB interrupt endpoint */ 2202 musbotg_root_intr(sc); 2203 USB_BUS_UNLOCK(&sc->sc_bus); 2204 } 2205 2206 void 2207 musbotg_interrupt(struct musbotg_softc *sc, 2208 uint16_t rxstat, uint16_t txstat, uint8_t stat) 2209 { 2210 uint16_t rx_status; 2211 uint16_t tx_status; 2212 uint8_t usb_status; 2213 uint8_t temp; 2214 uint8_t to = 2; 2215 2216 USB_BUS_LOCK(&sc->sc_bus); 2217 2218 repeat: 2219 2220 /* read all interrupt registers */ 2221 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 2222 2223 /* read all FIFO interrupts */ 2224 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 2225 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 2226 rx_status |= rxstat; 2227 tx_status |= txstat; 2228 usb_status |= stat; 2229 2230 /* Clear platform flags after first time */ 2231 rxstat = 0; 2232 txstat = 0; 2233 stat = 0; 2234 2235 /* check for any bus state change interrupts */ 2236 2237 if (usb_status & (MUSB2_MASK_IRESET | 2238 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 2239 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 2240 2241 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 2242 2243 if (usb_status & MUSB2_MASK_IRESET) { 2244 2245 /* set correct state */ 2246 sc->sc_flags.status_bus_reset = 1; 2247 sc->sc_flags.status_suspend = 0; 2248 sc->sc_flags.change_suspend = 0; 2249 sc->sc_flags.change_connect = 1; 2250 2251 /* determine line speed */ 2252 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 2253 if (temp & MUSB2_MASK_HSMODE) 2254 sc->sc_flags.status_high_speed = 1; 2255 else 2256 sc->sc_flags.status_high_speed = 0; 2257 2258 /* 2259 * After reset all interrupts are on and we need to 2260 * turn them off! 2261 */ 2262 temp = MUSB2_MASK_IRESET; 2263 /* disable resume interrupt */ 2264 temp &= ~MUSB2_MASK_IRESUME; 2265 /* enable suspend interrupt */ 2266 temp |= MUSB2_MASK_ISUSP; 2267 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2268 /* disable TX and RX interrupts */ 2269 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 2270 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 2271 } 2272 /* 2273 * If RXRSM and RXSUSP is set at the same time we interpret 2274 * that like RESUME. Resume is set when there is at least 3 2275 * milliseconds of inactivity on the USB BUS. 2276 */ 2277 if (usb_status & MUSB2_MASK_IRESUME) { 2278 if (sc->sc_flags.status_suspend) { 2279 sc->sc_flags.status_suspend = 0; 2280 sc->sc_flags.change_suspend = 1; 2281 2282 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2283 /* disable resume interrupt */ 2284 temp &= ~MUSB2_MASK_IRESUME; 2285 /* enable suspend interrupt */ 2286 temp |= MUSB2_MASK_ISUSP; 2287 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2288 } 2289 } else if (usb_status & MUSB2_MASK_ISUSP) { 2290 if (!sc->sc_flags.status_suspend) { 2291 sc->sc_flags.status_suspend = 1; 2292 sc->sc_flags.change_suspend = 1; 2293 2294 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2295 /* disable suspend interrupt */ 2296 temp &= ~MUSB2_MASK_ISUSP; 2297 /* enable resume interrupt */ 2298 temp |= MUSB2_MASK_IRESUME; 2299 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2300 } 2301 } 2302 if (usb_status & 2303 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) 2304 sc->sc_flags.change_connect = 1; 2305 2306 /* 2307 * Host Mode: There is no IRESET so assume bus is 2308 * always in reset state once device is connected. 2309 */ 2310 if (sc->sc_mode == MUSB2_HOST_MODE) { 2311 if (usb_status & MUSB2_MASK_ICONN) 2312 sc->sc_flags.status_bus_reset = 1; 2313 if (usb_status & MUSB2_MASK_IDISC) 2314 sc->sc_flags.status_bus_reset = 0; 2315 } 2316 2317 /* complete root HUB interrupt endpoint */ 2318 musbotg_root_intr(sc); 2319 } 2320 /* check for any endpoint interrupts */ 2321 2322 if (rx_status || tx_status) { 2323 DPRINTFN(4, "real endpoint interrupt " 2324 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 2325 } 2326 /* poll one time regardless of FIFO status */ 2327 2328 musbotg_interrupt_poll(sc); 2329 2330 if (--to) 2331 goto repeat; 2332 2333 USB_BUS_UNLOCK(&sc->sc_bus); 2334 } 2335 2336 static void 2337 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 2338 { 2339 struct musbotg_td *td; 2340 2341 /* get current Transfer Descriptor */ 2342 td = temp->td_next; 2343 temp->td = td; 2344 2345 /* prepare for next TD */ 2346 temp->td_next = td->obj_next; 2347 2348 /* fill out the Transfer Descriptor */ 2349 td->func = temp->func; 2350 td->pc = temp->pc; 2351 td->offset = temp->offset; 2352 td->remainder = temp->len; 2353 td->error = 0; 2354 td->transaction_started = 0; 2355 td->did_stall = temp->did_stall; 2356 td->short_pkt = temp->short_pkt; 2357 td->alt_next = temp->setup_alt_next; 2358 td->channel = temp->channel; 2359 td->dev_addr = temp->dev_addr; 2360 td->haddr = temp->haddr; 2361 td->hport = temp->hport; 2362 td->transfer_type = temp->transfer_type; 2363 } 2364 2365 static void 2366 musbotg_setup_standard_chain(struct usb_xfer *xfer) 2367 { 2368 struct musbotg_std_temp temp; 2369 struct musbotg_softc *sc; 2370 struct musbotg_td *td; 2371 uint32_t x; 2372 uint8_t ep_no; 2373 uint8_t xfer_type; 2374 enum usb_dev_speed speed; 2375 int tx; 2376 int dev_addr; 2377 2378 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2379 xfer->address, UE_GET_ADDR(xfer->endpointno), 2380 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2381 2382 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2383 ep_no = (xfer->endpointno & UE_ADDR); 2384 2385 temp.max_frame_size = xfer->max_frame_size; 2386 2387 td = xfer->td_start[0]; 2388 xfer->td_transfer_first = td; 2389 xfer->td_transfer_cache = td; 2390 2391 /* setup temp */ 2392 dev_addr = xfer->address; 2393 2394 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 2395 2396 temp.pc = NULL; 2397 temp.td = NULL; 2398 temp.td_next = xfer->td_start[0]; 2399 temp.offset = 0; 2400 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 2401 temp.did_stall = !xfer->flags_int.control_stall; 2402 temp.channel = -1; 2403 temp.dev_addr = dev_addr; 2404 temp.haddr = xfer->xroot->udev->hs_hub_addr; 2405 temp.hport = xfer->xroot->udev->hs_port_no; 2406 2407 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2408 speed = usbd_get_speed(xfer->xroot->udev); 2409 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 2410 2411 switch (speed) { 2412 case USB_SPEED_LOW: 2413 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO; 2414 break; 2415 case USB_SPEED_FULL: 2416 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS; 2417 break; 2418 case USB_SPEED_HIGH: 2419 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS; 2420 break; 2421 default: 2422 temp.transfer_type = 0; 2423 DPRINTFN(-1, "Invalid USB speed: %d\n", speed); 2424 break; 2425 } 2426 2427 switch (xfer_type) { 2428 case UE_CONTROL: 2429 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL; 2430 break; 2431 case UE_ISOCHRONOUS: 2432 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC; 2433 break; 2434 case UE_BULK: 2435 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK; 2436 break; 2437 case UE_INTERRUPT: 2438 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR; 2439 break; 2440 default: 2441 DPRINTFN(-1, "Invalid USB transfer type: %d\n", 2442 xfer_type); 2443 break; 2444 } 2445 2446 temp.transfer_type |= ep_no; 2447 td->max_packet = xfer->max_packet_size; 2448 td->toggle = xfer->endpoint->toggle_next; 2449 } 2450 2451 /* check if we should prepend a setup message */ 2452 2453 if (xfer->flags_int.control_xfr) { 2454 if (xfer->flags_int.control_hdr) { 2455 2456 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) 2457 temp.func = &musbotg_dev_ctrl_setup_rx; 2458 else 2459 temp.func = &musbotg_host_ctrl_setup_tx; 2460 2461 temp.len = xfer->frlengths[0]; 2462 temp.pc = xfer->frbuffers + 0; 2463 temp.short_pkt = temp.len ? 1 : 0; 2464 2465 musbotg_setup_standard_chain_sub(&temp); 2466 } 2467 x = 1; 2468 } else { 2469 x = 0; 2470 } 2471 2472 if (x != xfer->nframes) { 2473 tx = 0; 2474 2475 if (xfer->endpointno & UE_DIR_IN) 2476 tx = 1; 2477 2478 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2479 tx = !tx; 2480 2481 if (tx) { 2482 if (xfer->flags_int.control_xfr) 2483 temp.func = &musbotg_host_ctrl_data_tx; 2484 else 2485 temp.func = &musbotg_host_data_tx; 2486 } else { 2487 if (xfer->flags_int.control_xfr) 2488 temp.func = &musbotg_host_ctrl_data_rx; 2489 else 2490 temp.func = &musbotg_host_data_rx; 2491 } 2492 2493 } else { 2494 if (tx) { 2495 if (xfer->flags_int.control_xfr) 2496 temp.func = &musbotg_dev_ctrl_data_tx; 2497 else 2498 temp.func = &musbotg_dev_data_tx; 2499 } else { 2500 if (xfer->flags_int.control_xfr) 2501 temp.func = &musbotg_dev_ctrl_data_rx; 2502 else 2503 temp.func = &musbotg_dev_data_rx; 2504 } 2505 } 2506 2507 /* setup "pc" pointer */ 2508 temp.pc = xfer->frbuffers + x; 2509 } 2510 while (x != xfer->nframes) { 2511 2512 /* DATA0 / DATA1 message */ 2513 2514 temp.len = xfer->frlengths[x]; 2515 2516 x++; 2517 2518 if (x == xfer->nframes) { 2519 if (xfer->flags_int.control_xfr) { 2520 if (xfer->flags_int.control_act) { 2521 temp.setup_alt_next = 0; 2522 } 2523 } else { 2524 temp.setup_alt_next = 0; 2525 } 2526 } 2527 if (temp.len == 0) { 2528 2529 /* make sure that we send an USB packet */ 2530 2531 temp.short_pkt = 0; 2532 2533 } else { 2534 2535 /* regular data transfer */ 2536 2537 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 2538 } 2539 2540 musbotg_setup_standard_chain_sub(&temp); 2541 2542 if (xfer->flags_int.isochronous_xfr) { 2543 temp.offset += temp.len; 2544 } else { 2545 /* get next Page Cache pointer */ 2546 temp.pc = xfer->frbuffers + x; 2547 } 2548 } 2549 2550 /* check for control transfer */ 2551 if (xfer->flags_int.control_xfr) { 2552 2553 /* always setup a valid "pc" pointer for status and sync */ 2554 temp.pc = xfer->frbuffers + 0; 2555 temp.len = 0; 2556 temp.short_pkt = 0; 2557 temp.setup_alt_next = 0; 2558 2559 /* check if we should append a status stage */ 2560 if (!xfer->flags_int.control_act) { 2561 /* 2562 * Send a DATA1 message and invert the current 2563 * endpoint direction. 2564 */ 2565 if (sc->sc_mode == MUSB2_DEVICE_MODE) 2566 temp.func = &musbotg_dev_ctrl_status; 2567 else { 2568 if (xfer->endpointno & UE_DIR_IN) 2569 temp.func = musbotg_host_ctrl_status_tx; 2570 else 2571 temp.func = musbotg_host_ctrl_status_rx; 2572 } 2573 musbotg_setup_standard_chain_sub(&temp); 2574 } 2575 } 2576 /* must have at least one frame! */ 2577 td = temp.td; 2578 xfer->td_transfer_last = td; 2579 } 2580 2581 static void 2582 musbotg_timeout(void *arg) 2583 { 2584 struct usb_xfer *xfer = arg; 2585 2586 DPRINTFN(1, "xfer=%p\n", xfer); 2587 2588 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2589 2590 /* transfer is transferred */ 2591 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 2592 } 2593 2594 static void 2595 musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on) 2596 { 2597 uint16_t temp; 2598 2599 /* 2600 * Only enable the endpoint interrupt when we are 2601 * actually waiting for data, hence we are dealing 2602 * with level triggered interrupts ! 2603 */ 2604 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on); 2605 2606 if (channel == -1) 2607 return; 2608 2609 if (channel == 0) { 2610 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2611 if (on) 2612 temp |= MUSB2_MASK_EPINT(0); 2613 else 2614 temp &= ~MUSB2_MASK_EPINT(0); 2615 2616 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2617 } else { 2618 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 2619 if (on) 2620 temp |= MUSB2_MASK_EPINT(channel); 2621 else 2622 temp &= ~MUSB2_MASK_EPINT(channel); 2623 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 2624 2625 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2626 if (on) 2627 temp |= MUSB2_MASK_EPINT(channel); 2628 else 2629 temp &= ~MUSB2_MASK_EPINT(channel); 2630 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2631 } 2632 2633 if (sc->sc_ep_int_set) 2634 sc->sc_ep_int_set(sc, channel, on); 2635 } 2636 2637 static void 2638 musbotg_start_standard_chain(struct usb_xfer *xfer) 2639 { 2640 DPRINTFN(8, "\n"); 2641 2642 /* poll one time */ 2643 if (musbotg_xfer_do_fifo(xfer)) { 2644 2645 DPRINTFN(14, "enabled interrupts on endpoint\n"); 2646 2647 /* put transfer on interrupt queue */ 2648 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2649 2650 /* start timeout, if any */ 2651 if (xfer->timeout != 0) { 2652 usbd_transfer_timeout_ms(xfer, 2653 &musbotg_timeout, xfer->timeout); 2654 } 2655 } 2656 } 2657 2658 static void 2659 musbotg_root_intr(struct musbotg_softc *sc) 2660 { 2661 DPRINTFN(8, "\n"); 2662 2663 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2664 2665 /* set port bit */ 2666 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 2667 2668 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2669 sizeof(sc->sc_hub_idata)); 2670 } 2671 2672 static usb_error_t 2673 musbotg_standard_done_sub(struct usb_xfer *xfer) 2674 { 2675 struct musbotg_td *td; 2676 uint32_t len; 2677 uint8_t error; 2678 2679 DPRINTFN(8, "\n"); 2680 2681 td = xfer->td_transfer_cache; 2682 2683 do { 2684 len = td->remainder; 2685 2686 xfer->endpoint->toggle_next = td->toggle; 2687 2688 if (xfer->aframes != xfer->nframes) { 2689 /* 2690 * Verify the length and subtract 2691 * the remainder from "frlengths[]": 2692 */ 2693 if (len > xfer->frlengths[xfer->aframes]) { 2694 td->error = 1; 2695 } else { 2696 xfer->frlengths[xfer->aframes] -= len; 2697 } 2698 } 2699 /* Check for transfer error */ 2700 if (td->error) { 2701 /* the transfer is finished */ 2702 error = 1; 2703 td = NULL; 2704 break; 2705 } 2706 /* Check for short transfer */ 2707 if (len > 0) { 2708 if (xfer->flags_int.short_frames_ok) { 2709 /* follow alt next */ 2710 if (td->alt_next) { 2711 td = td->obj_next; 2712 } else { 2713 td = NULL; 2714 } 2715 } else { 2716 /* the transfer is finished */ 2717 td = NULL; 2718 } 2719 error = 0; 2720 break; 2721 } 2722 td = td->obj_next; 2723 2724 /* this USB frame is complete */ 2725 error = 0; 2726 break; 2727 2728 } while (0); 2729 2730 /* update transfer cache */ 2731 2732 xfer->td_transfer_cache = td; 2733 2734 return (error ? 2735 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 2736 } 2737 2738 static void 2739 musbotg_standard_done(struct usb_xfer *xfer) 2740 { 2741 usb_error_t err = 0; 2742 2743 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n", 2744 xfer, xfer->endpoint); 2745 2746 /* reset scanner */ 2747 2748 xfer->td_transfer_cache = xfer->td_transfer_first; 2749 2750 if (xfer->flags_int.control_xfr) { 2751 2752 if (xfer->flags_int.control_hdr) { 2753 2754 err = musbotg_standard_done_sub(xfer); 2755 } 2756 xfer->aframes = 1; 2757 2758 if (xfer->td_transfer_cache == NULL) { 2759 goto done; 2760 } 2761 } 2762 while (xfer->aframes != xfer->nframes) { 2763 2764 err = musbotg_standard_done_sub(xfer); 2765 xfer->aframes++; 2766 2767 if (xfer->td_transfer_cache == NULL) { 2768 goto done; 2769 } 2770 } 2771 2772 if (xfer->flags_int.control_xfr && 2773 !xfer->flags_int.control_act) { 2774 2775 err = musbotg_standard_done_sub(xfer); 2776 } 2777 done: 2778 musbotg_device_done(xfer, err); 2779 } 2780 2781 /*------------------------------------------------------------------------* 2782 * musbotg_device_done 2783 * 2784 * NOTE: this function can be called more than one time on the 2785 * same USB transfer! 2786 *------------------------------------------------------------------------*/ 2787 static void 2788 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error) 2789 { 2790 struct musbotg_td *td; 2791 struct musbotg_softc *sc; 2792 2793 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2794 2795 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n", 2796 xfer, xfer->endpoint, error); 2797 2798 DPRINTFN(14, "disabled interrupts on endpoint\n"); 2799 2800 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2801 td = xfer->td_transfer_cache; 2802 2803 if (td && (td->channel != -1)) 2804 musbotg_channel_free(sc, td); 2805 2806 /* dequeue transfer and start next transfer */ 2807 usbd_transfer_done(xfer, error); 2808 } 2809 2810 static void 2811 musbotg_xfer_stall(struct usb_xfer *xfer) 2812 { 2813 musbotg_device_done(xfer, USB_ERR_STALLED); 2814 } 2815 2816 static void 2817 musbotg_set_stall(struct usb_device *udev, 2818 struct usb_endpoint *ep, uint8_t *did_stall) 2819 { 2820 struct musbotg_softc *sc; 2821 uint8_t ep_no; 2822 2823 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2824 2825 DPRINTFN(4, "endpoint=%p\n", ep); 2826 2827 /* set FORCESTALL */ 2828 sc = MUSBOTG_BUS2SC(udev->bus); 2829 2830 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 2831 2832 /* select endpoint */ 2833 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2834 2835 if (ep->edesc->bEndpointAddress & UE_DIR_IN) { 2836 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2837 MUSB2_MASK_CSRL_TXSENDSTALL); 2838 } else { 2839 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2840 MUSB2_MASK_CSRL_RXSENDSTALL); 2841 } 2842 } 2843 2844 static void 2845 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 2846 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 2847 { 2848 uint16_t mps; 2849 uint16_t temp; 2850 uint8_t csr; 2851 2852 if (ep_type == UE_CONTROL) { 2853 /* clearing stall is not needed */ 2854 return; 2855 } 2856 /* select endpoint */ 2857 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2858 2859 /* compute max frame size */ 2860 mps = wMaxPacket & 0x7FF; 2861 switch ((wMaxPacket >> 11) & 3) { 2862 case 1: 2863 mps *= 2; 2864 break; 2865 case 2: 2866 mps *= 3; 2867 break; 2868 default: 2869 break; 2870 } 2871 2872 if (ep_dir == UE_DIR_IN) { 2873 2874 temp = 0; 2875 2876 /* Configure endpoint */ 2877 switch (ep_type) { 2878 case UE_INTERRUPT: 2879 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2880 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2881 MUSB2_MASK_CSRH_TXMODE | temp); 2882 break; 2883 case UE_ISOCHRONOUS: 2884 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2885 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2886 MUSB2_MASK_CSRH_TXMODE | 2887 MUSB2_MASK_CSRH_TXISO | temp); 2888 break; 2889 case UE_BULK: 2890 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2891 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2892 MUSB2_MASK_CSRH_TXMODE | temp); 2893 break; 2894 default: 2895 break; 2896 } 2897 2898 /* Need to flush twice in case of double bufring */ 2899 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2900 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2901 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2902 MUSB2_MASK_CSRL_TXFFLUSH); 2903 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2904 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2905 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2906 MUSB2_MASK_CSRL_TXFFLUSH); 2907 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2908 } 2909 } 2910 /* reset data toggle */ 2911 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2912 MUSB2_MASK_CSRL_TXDT_CLR); 2913 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2914 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2915 2916 /* set double/single buffering */ 2917 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 2918 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 2919 max_in_frame_size / 2)) { 2920 /* double buffer */ 2921 temp &= ~(1 << ep_no); 2922 } else { 2923 /* single buffer */ 2924 temp |= (1 << ep_no); 2925 } 2926 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 2927 2928 /* clear sent stall */ 2929 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 2930 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2931 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2932 } 2933 } else { 2934 2935 temp = 0; 2936 2937 /* Configure endpoint */ 2938 switch (ep_type) { 2939 case UE_INTERRUPT: 2940 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2941 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2942 MUSB2_MASK_CSRH_RXNYET | temp); 2943 break; 2944 case UE_ISOCHRONOUS: 2945 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2946 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2947 MUSB2_MASK_CSRH_RXNYET | 2948 MUSB2_MASK_CSRH_RXISO | temp); 2949 break; 2950 case UE_BULK: 2951 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2952 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 2953 break; 2954 default: 2955 break; 2956 } 2957 2958 /* Need to flush twice in case of double bufring */ 2959 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2960 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2961 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2962 MUSB2_MASK_CSRL_RXFFLUSH); 2963 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2964 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2965 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2966 MUSB2_MASK_CSRL_RXFFLUSH); 2967 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2968 } 2969 } 2970 /* reset data toggle */ 2971 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2972 MUSB2_MASK_CSRL_RXDT_CLR); 2973 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 2974 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2975 2976 /* set double/single buffering */ 2977 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 2978 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 2979 max_out_frame_size / 2)) { 2980 /* double buffer */ 2981 temp &= ~(1 << ep_no); 2982 } else { 2983 /* single buffer */ 2984 temp |= (1 << ep_no); 2985 } 2986 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 2987 2988 /* clear sent stall */ 2989 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 2990 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 2991 } 2992 } 2993 } 2994 2995 static void 2996 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 2997 { 2998 struct musbotg_softc *sc; 2999 struct usb_endpoint_descriptor *ed; 3000 3001 DPRINTFN(4, "endpoint=%p\n", ep); 3002 3003 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3004 3005 /* check mode */ 3006 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3007 /* not supported */ 3008 return; 3009 } 3010 /* get softc */ 3011 sc = MUSBOTG_BUS2SC(udev->bus); 3012 3013 /* get endpoint descriptor */ 3014 ed = ep->edesc; 3015 3016 /* reset endpoint */ 3017 musbotg_clear_stall_sub(sc, 3018 UGETW(ed->wMaxPacketSize), 3019 (ed->bEndpointAddress & UE_ADDR), 3020 (ed->bmAttributes & UE_XFERTYPE), 3021 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3022 } 3023 3024 usb_error_t 3025 musbotg_init(struct musbotg_softc *sc) 3026 { 3027 struct usb_hw_ep_profile *pf; 3028 uint16_t offset; 3029 uint8_t nrx; 3030 uint8_t ntx; 3031 uint8_t temp; 3032 uint8_t fsize; 3033 uint8_t frx; 3034 uint8_t ftx; 3035 uint8_t dynfifo; 3036 3037 DPRINTFN(1, "start\n"); 3038 3039 /* set up the bus structure */ 3040 sc->sc_bus.usbrev = USB_REV_2_0; 3041 sc->sc_bus.methods = &musbotg_bus_methods; 3042 3043 USB_BUS_LOCK(&sc->sc_bus); 3044 3045 /* turn on clocks */ 3046 3047 if (sc->sc_clocks_on) { 3048 (sc->sc_clocks_on) (sc->sc_clocks_arg); 3049 } 3050 3051 /* wait a little for things to stabilise */ 3052 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 3053 3054 /* disable all interrupts */ 3055 3056 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3057 DPRINTF("pre-DEVCTL=0x%02x\n", temp); 3058 3059 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3060 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3061 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3062 3063 /* disable pullup */ 3064 3065 musbotg_pull_common(sc, 0); 3066 3067 /* wait a little bit (10ms) */ 3068 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3069 3070 3071 /* disable double packet buffering */ 3072 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 3073 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 3074 3075 /* enable HighSpeed and ISO Update flags */ 3076 3077 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 3078 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 3079 3080 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 3081 /* clear Session bit, if set */ 3082 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3083 temp &= ~MUSB2_MASK_SESS; 3084 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3085 } else { 3086 /* Enter session for Host mode */ 3087 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3088 temp |= MUSB2_MASK_SESS; 3089 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3090 } 3091 3092 /* wait a little for things to stabilise */ 3093 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 3094 3095 DPRINTF("DEVCTL=0x%02x\n", temp); 3096 3097 /* disable testmode */ 3098 3099 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 3100 3101 /* set default value */ 3102 3103 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 3104 3105 /* select endpoint index 0 */ 3106 3107 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 3108 3109 /* read out number of endpoints */ 3110 3111 nrx = 3112 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 3113 3114 ntx = 3115 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 3116 3117 /* these numbers exclude the control endpoint */ 3118 3119 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 3120 3121 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 3122 if (sc->sc_ep_max == 0) { 3123 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 3124 } 3125 /* read out configuration data */ 3126 3127 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 3128 3129 DPRINTFN(2, "Config Data: 0x%02x\n", 3130 sc->sc_conf_data); 3131 3132 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 3133 3134 if (dynfifo) { 3135 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, " 3136 "assuming 16Kbytes of FIFO RAM\n"); 3137 } 3138 3139 DPRINTFN(2, "HW version: 0x%04x\n", 3140 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 3141 3142 /* initialise endpoint profiles */ 3143 3144 offset = 0; 3145 3146 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 3147 pf = sc->sc_hw_ep_profile + temp; 3148 3149 /* select endpoint */ 3150 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 3151 3152 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 3153 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16; 3154 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 3155 3156 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 3157 temp, ftx, frx, dynfifo); 3158 3159 if (dynfifo) { 3160 if (frx && (temp <= nrx)) { 3161 if (temp < 8) { 3162 frx = 10; /* 1K */ 3163 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 3164 MUSB2_VAL_FIFOSZ_512 | 3165 MUSB2_MASK_FIFODB); 3166 } else { 3167 frx = 7; /* 128 bytes */ 3168 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 3169 MUSB2_VAL_FIFOSZ_128); 3170 } 3171 3172 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD, 3173 offset >> 3); 3174 3175 offset += (1 << frx); 3176 } 3177 if (ftx && (temp <= ntx)) { 3178 if (temp < 8) { 3179 ftx = 10; /* 1K */ 3180 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 3181 MUSB2_VAL_FIFOSZ_512 | 3182 MUSB2_MASK_FIFODB); 3183 } else { 3184 ftx = 7; /* 128 bytes */ 3185 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 3186 MUSB2_VAL_FIFOSZ_128); 3187 } 3188 3189 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD, 3190 offset >> 3); 3191 3192 offset += (1 << ftx); 3193 } 3194 } 3195 3196 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 3197 pf->max_in_frame_size = 1 << ftx; 3198 pf->max_out_frame_size = 1 << frx; 3199 pf->is_simplex = 0; /* duplex */ 3200 pf->support_multi_buffer = 1; 3201 pf->support_bulk = 1; 3202 pf->support_interrupt = 1; 3203 pf->support_isochronous = 1; 3204 pf->support_in = 1; 3205 pf->support_out = 1; 3206 } else if (frx && (temp <= nrx)) { 3207 pf->max_out_frame_size = 1 << frx; 3208 pf->is_simplex = 1; /* simplex */ 3209 pf->support_multi_buffer = 1; 3210 pf->support_bulk = 1; 3211 pf->support_interrupt = 1; 3212 pf->support_isochronous = 1; 3213 pf->support_out = 1; 3214 } else if (ftx && (temp <= ntx)) { 3215 pf->max_in_frame_size = 1 << ftx; 3216 pf->is_simplex = 1; /* simplex */ 3217 pf->support_multi_buffer = 1; 3218 pf->support_bulk = 1; 3219 pf->support_interrupt = 1; 3220 pf->support_isochronous = 1; 3221 pf->support_in = 1; 3222 } 3223 } 3224 3225 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset); 3226 3227 /* turn on default interrupts */ 3228 3229 if (sc->sc_mode == MUSB2_HOST_MODE) 3230 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff); 3231 else 3232 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 3233 MUSB2_MASK_IRESET); 3234 3235 musbotg_clocks_off(sc); 3236 3237 USB_BUS_UNLOCK(&sc->sc_bus); 3238 3239 /* catch any lost interrupts */ 3240 3241 musbotg_do_poll(&sc->sc_bus); 3242 3243 return (0); /* success */ 3244 } 3245 3246 void 3247 musbotg_uninit(struct musbotg_softc *sc) 3248 { 3249 USB_BUS_LOCK(&sc->sc_bus); 3250 3251 /* disable all interrupts */ 3252 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3253 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3254 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3255 3256 sc->sc_flags.port_powered = 0; 3257 sc->sc_flags.status_vbus = 0; 3258 sc->sc_flags.status_bus_reset = 0; 3259 sc->sc_flags.status_suspend = 0; 3260 sc->sc_flags.change_suspend = 0; 3261 sc->sc_flags.change_connect = 1; 3262 3263 musbotg_pull_down(sc); 3264 musbotg_clocks_off(sc); 3265 USB_BUS_UNLOCK(&sc->sc_bus); 3266 } 3267 3268 static void 3269 musbotg_suspend(struct musbotg_softc *sc) 3270 { 3271 /* TODO */ 3272 } 3273 3274 static void 3275 musbotg_resume(struct musbotg_softc *sc) 3276 { 3277 /* TODO */ 3278 } 3279 3280 static void 3281 musbotg_do_poll(struct usb_bus *bus) 3282 { 3283 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 3284 3285 USB_BUS_LOCK(&sc->sc_bus); 3286 musbotg_interrupt_poll(sc); 3287 USB_BUS_UNLOCK(&sc->sc_bus); 3288 } 3289 3290 /*------------------------------------------------------------------------* 3291 * musbotg bulk support 3292 *------------------------------------------------------------------------*/ 3293 static void 3294 musbotg_device_bulk_open(struct usb_xfer *xfer) 3295 { 3296 return; 3297 } 3298 3299 static void 3300 musbotg_device_bulk_close(struct usb_xfer *xfer) 3301 { 3302 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3303 } 3304 3305 static void 3306 musbotg_device_bulk_enter(struct usb_xfer *xfer) 3307 { 3308 return; 3309 } 3310 3311 static void 3312 musbotg_device_bulk_start(struct usb_xfer *xfer) 3313 { 3314 /* setup TDs */ 3315 musbotg_setup_standard_chain(xfer); 3316 musbotg_start_standard_chain(xfer); 3317 } 3318 3319 struct usb_pipe_methods musbotg_device_bulk_methods = 3320 { 3321 .open = musbotg_device_bulk_open, 3322 .close = musbotg_device_bulk_close, 3323 .enter = musbotg_device_bulk_enter, 3324 .start = musbotg_device_bulk_start, 3325 }; 3326 3327 /*------------------------------------------------------------------------* 3328 * musbotg control support 3329 *------------------------------------------------------------------------*/ 3330 static void 3331 musbotg_device_ctrl_open(struct usb_xfer *xfer) 3332 { 3333 return; 3334 } 3335 3336 static void 3337 musbotg_device_ctrl_close(struct usb_xfer *xfer) 3338 { 3339 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3340 } 3341 3342 static void 3343 musbotg_device_ctrl_enter(struct usb_xfer *xfer) 3344 { 3345 return; 3346 } 3347 3348 static void 3349 musbotg_device_ctrl_start(struct usb_xfer *xfer) 3350 { 3351 /* setup TDs */ 3352 musbotg_setup_standard_chain(xfer); 3353 musbotg_start_standard_chain(xfer); 3354 } 3355 3356 struct usb_pipe_methods musbotg_device_ctrl_methods = 3357 { 3358 .open = musbotg_device_ctrl_open, 3359 .close = musbotg_device_ctrl_close, 3360 .enter = musbotg_device_ctrl_enter, 3361 .start = musbotg_device_ctrl_start, 3362 }; 3363 3364 /*------------------------------------------------------------------------* 3365 * musbotg interrupt support 3366 *------------------------------------------------------------------------*/ 3367 static void 3368 musbotg_device_intr_open(struct usb_xfer *xfer) 3369 { 3370 return; 3371 } 3372 3373 static void 3374 musbotg_device_intr_close(struct usb_xfer *xfer) 3375 { 3376 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3377 } 3378 3379 static void 3380 musbotg_device_intr_enter(struct usb_xfer *xfer) 3381 { 3382 return; 3383 } 3384 3385 static void 3386 musbotg_device_intr_start(struct usb_xfer *xfer) 3387 { 3388 /* setup TDs */ 3389 musbotg_setup_standard_chain(xfer); 3390 musbotg_start_standard_chain(xfer); 3391 } 3392 3393 struct usb_pipe_methods musbotg_device_intr_methods = 3394 { 3395 .open = musbotg_device_intr_open, 3396 .close = musbotg_device_intr_close, 3397 .enter = musbotg_device_intr_enter, 3398 .start = musbotg_device_intr_start, 3399 }; 3400 3401 /*------------------------------------------------------------------------* 3402 * musbotg full speed isochronous support 3403 *------------------------------------------------------------------------*/ 3404 static void 3405 musbotg_device_isoc_open(struct usb_xfer *xfer) 3406 { 3407 return; 3408 } 3409 3410 static void 3411 musbotg_device_isoc_close(struct usb_xfer *xfer) 3412 { 3413 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3414 } 3415 3416 static void 3417 musbotg_device_isoc_enter(struct usb_xfer *xfer) 3418 { 3419 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 3420 uint32_t temp; 3421 uint32_t nframes; 3422 uint32_t fs_frames; 3423 3424 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 3425 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3426 3427 /* get the current frame index */ 3428 3429 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 3430 3431 /* 3432 * check if the frame index is within the window where the frames 3433 * will be inserted 3434 */ 3435 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME; 3436 3437 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 3438 fs_frames = (xfer->nframes + 7) / 8; 3439 } else { 3440 fs_frames = xfer->nframes; 3441 } 3442 3443 if ((xfer->endpoint->is_synced == 0) || 3444 (temp < fs_frames)) { 3445 /* 3446 * If there is data underflow or the pipe queue is 3447 * empty we schedule the transfer a few frames ahead 3448 * of the current frame position. Else two isochronous 3449 * transfers might overlap. 3450 */ 3451 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 3452 xfer->endpoint->is_synced = 1; 3453 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next); 3454 } 3455 /* 3456 * compute how many milliseconds the insertion is ahead of the 3457 * current frame position: 3458 */ 3459 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME; 3460 3461 /* 3462 * pre-compute when the isochronous transfer will be finished: 3463 */ 3464 xfer->isoc_time_complete = 3465 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 3466 fs_frames; 3467 3468 /* compute frame number for next insertion */ 3469 xfer->endpoint->isoc_next += fs_frames; 3470 3471 /* setup TDs */ 3472 musbotg_setup_standard_chain(xfer); 3473 } 3474 3475 static void 3476 musbotg_device_isoc_start(struct usb_xfer *xfer) 3477 { 3478 /* start TD chain */ 3479 musbotg_start_standard_chain(xfer); 3480 } 3481 3482 struct usb_pipe_methods musbotg_device_isoc_methods = 3483 { 3484 .open = musbotg_device_isoc_open, 3485 .close = musbotg_device_isoc_close, 3486 .enter = musbotg_device_isoc_enter, 3487 .start = musbotg_device_isoc_start, 3488 }; 3489 3490 /*------------------------------------------------------------------------* 3491 * musbotg root control support 3492 *------------------------------------------------------------------------* 3493 * Simulate a hardware HUB by handling all the necessary requests. 3494 *------------------------------------------------------------------------*/ 3495 3496 static const struct usb_device_descriptor musbotg_devd = { 3497 .bLength = sizeof(struct usb_device_descriptor), 3498 .bDescriptorType = UDESC_DEVICE, 3499 .bcdUSB = {0x00, 0x02}, 3500 .bDeviceClass = UDCLASS_HUB, 3501 .bDeviceSubClass = UDSUBCLASS_HUB, 3502 .bDeviceProtocol = UDPROTO_HSHUBSTT, 3503 .bMaxPacketSize = 64, 3504 .bcdDevice = {0x00, 0x01}, 3505 .iManufacturer = 1, 3506 .iProduct = 2, 3507 .bNumConfigurations = 1, 3508 }; 3509 3510 static const struct usb_device_qualifier musbotg_odevd = { 3511 .bLength = sizeof(struct usb_device_qualifier), 3512 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 3513 .bcdUSB = {0x00, 0x02}, 3514 .bDeviceClass = UDCLASS_HUB, 3515 .bDeviceSubClass = UDSUBCLASS_HUB, 3516 .bDeviceProtocol = UDPROTO_FSHUB, 3517 .bMaxPacketSize0 = 0, 3518 .bNumConfigurations = 0, 3519 }; 3520 3521 static const struct musbotg_config_desc musbotg_confd = { 3522 .confd = { 3523 .bLength = sizeof(struct usb_config_descriptor), 3524 .bDescriptorType = UDESC_CONFIG, 3525 .wTotalLength[0] = sizeof(musbotg_confd), 3526 .bNumInterface = 1, 3527 .bConfigurationValue = 1, 3528 .iConfiguration = 0, 3529 .bmAttributes = UC_SELF_POWERED, 3530 .bMaxPower = 0, 3531 }, 3532 .ifcd = { 3533 .bLength = sizeof(struct usb_interface_descriptor), 3534 .bDescriptorType = UDESC_INTERFACE, 3535 .bNumEndpoints = 1, 3536 .bInterfaceClass = UICLASS_HUB, 3537 .bInterfaceSubClass = UISUBCLASS_HUB, 3538 .bInterfaceProtocol = 0, 3539 }, 3540 .endpd = { 3541 .bLength = sizeof(struct usb_endpoint_descriptor), 3542 .bDescriptorType = UDESC_ENDPOINT, 3543 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 3544 .bmAttributes = UE_INTERRUPT, 3545 .wMaxPacketSize[0] = 8, 3546 .bInterval = 255, 3547 }, 3548 }; 3549 3550 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3551 3552 static const struct usb_hub_descriptor_min musbotg_hubd = { 3553 .bDescLength = sizeof(musbotg_hubd), 3554 .bDescriptorType = UDESC_HUB, 3555 .bNbrPorts = 1, 3556 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 3557 .bPwrOn2PwrGood = 50, 3558 .bHubContrCurrent = 0, 3559 .DeviceRemovable = {0}, /* port is removable */ 3560 }; 3561 3562 #define STRING_VENDOR \ 3563 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s" 3564 3565 #define STRING_PRODUCT \ 3566 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 3567 3568 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 3569 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 3570 3571 static usb_error_t 3572 musbotg_roothub_exec(struct usb_device *udev, 3573 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3574 { 3575 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 3576 const void *ptr; 3577 uint16_t len; 3578 uint16_t value; 3579 uint16_t index; 3580 uint8_t reg; 3581 usb_error_t err; 3582 3583 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3584 3585 /* buffer reset */ 3586 ptr = (const void *)&sc->sc_hub_temp; 3587 len = 0; 3588 err = 0; 3589 3590 value = UGETW(req->wValue); 3591 index = UGETW(req->wIndex); 3592 3593 /* demultiplex the control request */ 3594 3595 switch (req->bmRequestType) { 3596 case UT_READ_DEVICE: 3597 switch (req->bRequest) { 3598 case UR_GET_DESCRIPTOR: 3599 goto tr_handle_get_descriptor; 3600 case UR_GET_CONFIG: 3601 goto tr_handle_get_config; 3602 case UR_GET_STATUS: 3603 goto tr_handle_get_status; 3604 default: 3605 goto tr_stalled; 3606 } 3607 break; 3608 3609 case UT_WRITE_DEVICE: 3610 switch (req->bRequest) { 3611 case UR_SET_ADDRESS: 3612 goto tr_handle_set_address; 3613 case UR_SET_CONFIG: 3614 goto tr_handle_set_config; 3615 case UR_CLEAR_FEATURE: 3616 goto tr_valid; /* nop */ 3617 case UR_SET_DESCRIPTOR: 3618 goto tr_valid; /* nop */ 3619 case UR_SET_FEATURE: 3620 default: 3621 goto tr_stalled; 3622 } 3623 break; 3624 3625 case UT_WRITE_ENDPOINT: 3626 switch (req->bRequest) { 3627 case UR_CLEAR_FEATURE: 3628 switch (UGETW(req->wValue)) { 3629 case UF_ENDPOINT_HALT: 3630 goto tr_handle_clear_halt; 3631 case UF_DEVICE_REMOTE_WAKEUP: 3632 goto tr_handle_clear_wakeup; 3633 default: 3634 goto tr_stalled; 3635 } 3636 break; 3637 case UR_SET_FEATURE: 3638 switch (UGETW(req->wValue)) { 3639 case UF_ENDPOINT_HALT: 3640 goto tr_handle_set_halt; 3641 case UF_DEVICE_REMOTE_WAKEUP: 3642 goto tr_handle_set_wakeup; 3643 default: 3644 goto tr_stalled; 3645 } 3646 break; 3647 case UR_SYNCH_FRAME: 3648 goto tr_valid; /* nop */ 3649 default: 3650 goto tr_stalled; 3651 } 3652 break; 3653 3654 case UT_READ_ENDPOINT: 3655 switch (req->bRequest) { 3656 case UR_GET_STATUS: 3657 goto tr_handle_get_ep_status; 3658 default: 3659 goto tr_stalled; 3660 } 3661 break; 3662 3663 case UT_WRITE_INTERFACE: 3664 switch (req->bRequest) { 3665 case UR_SET_INTERFACE: 3666 goto tr_handle_set_interface; 3667 case UR_CLEAR_FEATURE: 3668 goto tr_valid; /* nop */ 3669 case UR_SET_FEATURE: 3670 default: 3671 goto tr_stalled; 3672 } 3673 break; 3674 3675 case UT_READ_INTERFACE: 3676 switch (req->bRequest) { 3677 case UR_GET_INTERFACE: 3678 goto tr_handle_get_interface; 3679 case UR_GET_STATUS: 3680 goto tr_handle_get_iface_status; 3681 default: 3682 goto tr_stalled; 3683 } 3684 break; 3685 3686 case UT_WRITE_CLASS_INTERFACE: 3687 case UT_WRITE_VENDOR_INTERFACE: 3688 /* XXX forward */ 3689 break; 3690 3691 case UT_READ_CLASS_INTERFACE: 3692 case UT_READ_VENDOR_INTERFACE: 3693 /* XXX forward */ 3694 break; 3695 3696 case UT_WRITE_CLASS_DEVICE: 3697 switch (req->bRequest) { 3698 case UR_CLEAR_FEATURE: 3699 goto tr_valid; 3700 case UR_SET_DESCRIPTOR: 3701 case UR_SET_FEATURE: 3702 break; 3703 default: 3704 goto tr_stalled; 3705 } 3706 break; 3707 3708 case UT_WRITE_CLASS_OTHER: 3709 switch (req->bRequest) { 3710 case UR_CLEAR_FEATURE: 3711 goto tr_handle_clear_port_feature; 3712 case UR_SET_FEATURE: 3713 goto tr_handle_set_port_feature; 3714 case UR_CLEAR_TT_BUFFER: 3715 case UR_RESET_TT: 3716 case UR_STOP_TT: 3717 goto tr_valid; 3718 3719 default: 3720 goto tr_stalled; 3721 } 3722 break; 3723 3724 case UT_READ_CLASS_OTHER: 3725 switch (req->bRequest) { 3726 case UR_GET_TT_STATE: 3727 goto tr_handle_get_tt_state; 3728 case UR_GET_STATUS: 3729 goto tr_handle_get_port_status; 3730 default: 3731 goto tr_stalled; 3732 } 3733 break; 3734 3735 case UT_READ_CLASS_DEVICE: 3736 switch (req->bRequest) { 3737 case UR_GET_DESCRIPTOR: 3738 goto tr_handle_get_class_descriptor; 3739 case UR_GET_STATUS: 3740 goto tr_handle_get_class_status; 3741 3742 default: 3743 goto tr_stalled; 3744 } 3745 break; 3746 default: 3747 goto tr_stalled; 3748 } 3749 goto tr_valid; 3750 3751 tr_handle_get_descriptor: 3752 switch (value >> 8) { 3753 case UDESC_DEVICE: 3754 if (value & 0xff) { 3755 goto tr_stalled; 3756 } 3757 len = sizeof(musbotg_devd); 3758 ptr = (const void *)&musbotg_devd; 3759 goto tr_valid; 3760 case UDESC_CONFIG: 3761 if (value & 0xff) { 3762 goto tr_stalled; 3763 } 3764 len = sizeof(musbotg_confd); 3765 ptr = (const void *)&musbotg_confd; 3766 goto tr_valid; 3767 case UDESC_STRING: 3768 switch (value & 0xff) { 3769 case 0: /* Language table */ 3770 len = sizeof(usb_string_lang_en); 3771 ptr = (const void *)&usb_string_lang_en; 3772 goto tr_valid; 3773 3774 case 1: /* Vendor */ 3775 len = sizeof(musbotg_vendor); 3776 ptr = (const void *)&musbotg_vendor; 3777 goto tr_valid; 3778 3779 case 2: /* Product */ 3780 len = sizeof(musbotg_product); 3781 ptr = (const void *)&musbotg_product; 3782 goto tr_valid; 3783 default: 3784 break; 3785 } 3786 break; 3787 default: 3788 goto tr_stalled; 3789 } 3790 goto tr_stalled; 3791 3792 tr_handle_get_config: 3793 len = 1; 3794 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 3795 goto tr_valid; 3796 3797 tr_handle_get_status: 3798 len = 2; 3799 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 3800 goto tr_valid; 3801 3802 tr_handle_set_address: 3803 if (value & 0xFF00) { 3804 goto tr_stalled; 3805 } 3806 sc->sc_rt_addr = value; 3807 goto tr_valid; 3808 3809 tr_handle_set_config: 3810 if (value >= 2) { 3811 goto tr_stalled; 3812 } 3813 sc->sc_conf = value; 3814 goto tr_valid; 3815 3816 tr_handle_get_interface: 3817 len = 1; 3818 sc->sc_hub_temp.wValue[0] = 0; 3819 goto tr_valid; 3820 3821 tr_handle_get_tt_state: 3822 tr_handle_get_class_status: 3823 tr_handle_get_iface_status: 3824 tr_handle_get_ep_status: 3825 len = 2; 3826 USETW(sc->sc_hub_temp.wValue, 0); 3827 goto tr_valid; 3828 3829 tr_handle_set_halt: 3830 tr_handle_set_interface: 3831 tr_handle_set_wakeup: 3832 tr_handle_clear_wakeup: 3833 tr_handle_clear_halt: 3834 goto tr_valid; 3835 3836 tr_handle_clear_port_feature: 3837 if (index != 1) { 3838 goto tr_stalled; 3839 } 3840 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 3841 3842 switch (value) { 3843 case UHF_PORT_SUSPEND: 3844 if (sc->sc_mode == MUSB2_HOST_MODE) 3845 musbotg_wakeup_host(sc); 3846 else 3847 musbotg_wakeup_peer(sc); 3848 break; 3849 3850 case UHF_PORT_ENABLE: 3851 sc->sc_flags.port_enabled = 0; 3852 break; 3853 3854 case UHF_C_PORT_ENABLE: 3855 sc->sc_flags.change_enabled = 0; 3856 break; 3857 3858 case UHF_C_PORT_OVER_CURRENT: 3859 sc->sc_flags.change_over_current = 0; 3860 break; 3861 3862 case UHF_C_PORT_RESET: 3863 sc->sc_flags.change_reset = 0; 3864 break; 3865 3866 case UHF_PORT_TEST: 3867 case UHF_PORT_INDICATOR: 3868 /* nops */ 3869 break; 3870 3871 case UHF_PORT_POWER: 3872 sc->sc_flags.port_powered = 0; 3873 musbotg_pull_down(sc); 3874 musbotg_clocks_off(sc); 3875 break; 3876 case UHF_C_PORT_CONNECTION: 3877 sc->sc_flags.change_connect = 0; 3878 break; 3879 case UHF_C_PORT_SUSPEND: 3880 sc->sc_flags.change_suspend = 0; 3881 break; 3882 default: 3883 err = USB_ERR_IOERROR; 3884 goto done; 3885 } 3886 goto tr_valid; 3887 3888 tr_handle_set_port_feature: 3889 if (index != 1) { 3890 goto tr_stalled; 3891 } 3892 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 3893 3894 switch (value) { 3895 case UHF_PORT_ENABLE: 3896 sc->sc_flags.port_enabled = 1; 3897 break; 3898 case UHF_PORT_SUSPEND: 3899 if (sc->sc_mode == MUSB2_HOST_MODE) 3900 musbotg_suspend_host(sc); 3901 break; 3902 3903 case UHF_PORT_RESET: 3904 if (sc->sc_mode == MUSB2_HOST_MODE) { 3905 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3906 reg |= MUSB2_MASK_RESET; 3907 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3908 3909 /* Wait for 20 msec */ 3910 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5); 3911 3912 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3913 reg &= ~MUSB2_MASK_RESET; 3914 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3915 3916 /* determine line speed */ 3917 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3918 if (reg & MUSB2_MASK_HSMODE) 3919 sc->sc_flags.status_high_speed = 1; 3920 else 3921 sc->sc_flags.status_high_speed = 0; 3922 3923 sc->sc_flags.change_reset = 1; 3924 } else 3925 err = USB_ERR_IOERROR; 3926 break; 3927 3928 case UHF_PORT_TEST: 3929 case UHF_PORT_INDICATOR: 3930 /* nops */ 3931 break; 3932 case UHF_PORT_POWER: 3933 sc->sc_flags.port_powered = 1; 3934 break; 3935 default: 3936 err = USB_ERR_IOERROR; 3937 goto done; 3938 } 3939 goto tr_valid; 3940 3941 tr_handle_get_port_status: 3942 3943 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 3944 3945 if (index != 1) { 3946 goto tr_stalled; 3947 } 3948 if (sc->sc_flags.status_vbus) { 3949 musbotg_clocks_on(sc); 3950 musbotg_pull_up(sc); 3951 } else { 3952 musbotg_pull_down(sc); 3953 musbotg_clocks_off(sc); 3954 } 3955 3956 /* Select Device Side Mode */ 3957 if (sc->sc_mode == MUSB2_DEVICE_MODE) 3958 value = UPS_PORT_MODE_DEVICE; 3959 else 3960 value = 0; 3961 3962 if (sc->sc_flags.status_high_speed) { 3963 value |= UPS_HIGH_SPEED; 3964 } 3965 if (sc->sc_flags.port_powered) { 3966 value |= UPS_PORT_POWER; 3967 } 3968 if (sc->sc_flags.port_enabled) { 3969 value |= UPS_PORT_ENABLED; 3970 } 3971 3972 if (sc->sc_flags.port_over_current) 3973 value |= UPS_OVERCURRENT_INDICATOR; 3974 3975 if (sc->sc_flags.status_vbus && 3976 sc->sc_flags.status_bus_reset) { 3977 value |= UPS_CURRENT_CONNECT_STATUS; 3978 } 3979 if (sc->sc_flags.status_suspend) { 3980 value |= UPS_SUSPEND; 3981 } 3982 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 3983 3984 value = 0; 3985 3986 if (sc->sc_flags.change_connect) { 3987 value |= UPS_C_CONNECT_STATUS; 3988 3989 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 3990 if (sc->sc_flags.status_vbus && 3991 sc->sc_flags.status_bus_reset) { 3992 /* reset EP0 state */ 3993 sc->sc_ep0_busy = 0; 3994 sc->sc_ep0_cmd = 0; 3995 } 3996 } 3997 } 3998 if (sc->sc_flags.change_suspend) 3999 value |= UPS_C_SUSPEND; 4000 if (sc->sc_flags.change_reset) 4001 value |= UPS_C_PORT_RESET; 4002 if (sc->sc_flags.change_over_current) 4003 value |= UPS_C_OVERCURRENT_INDICATOR; 4004 4005 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4006 len = sizeof(sc->sc_hub_temp.ps); 4007 goto tr_valid; 4008 4009 tr_handle_get_class_descriptor: 4010 if (value & 0xFF) { 4011 goto tr_stalled; 4012 } 4013 ptr = (const void *)&musbotg_hubd; 4014 len = sizeof(musbotg_hubd); 4015 goto tr_valid; 4016 4017 tr_stalled: 4018 err = USB_ERR_STALLED; 4019 tr_valid: 4020 done: 4021 *plength = len; 4022 *pptr = ptr; 4023 return (err); 4024 } 4025 4026 static void 4027 musbotg_xfer_setup(struct usb_setup_params *parm) 4028 { 4029 const struct usb_hw_ep_profile *pf; 4030 struct musbotg_softc *sc; 4031 struct usb_xfer *xfer; 4032 void *last_obj; 4033 uint32_t ntd; 4034 uint32_t n; 4035 uint8_t ep_no; 4036 4037 sc = MUSBOTG_BUS2SC(parm->udev->bus); 4038 xfer = parm->curr_xfer; 4039 4040 /* 4041 * NOTE: This driver does not use any of the parameters that 4042 * are computed from the following values. Just set some 4043 * reasonable dummies: 4044 */ 4045 parm->hc_max_packet_size = 0x400; 4046 parm->hc_max_frame_size = 0x400; 4047 4048 if ((parm->methods == &musbotg_device_isoc_methods) || 4049 (parm->methods == &musbotg_device_intr_methods)) 4050 parm->hc_max_packet_count = 3; 4051 else 4052 parm->hc_max_packet_count = 1; 4053 4054 usbd_transfer_setup_sub(parm); 4055 4056 /* 4057 * compute maximum number of TDs 4058 */ 4059 if (parm->methods == &musbotg_device_ctrl_methods) { 4060 4061 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 4062 4063 } else if (parm->methods == &musbotg_device_bulk_methods) { 4064 4065 ntd = xfer->nframes + 1 /* SYNC */ ; 4066 4067 } else if (parm->methods == &musbotg_device_intr_methods) { 4068 4069 ntd = xfer->nframes + 1 /* SYNC */ ; 4070 4071 } else if (parm->methods == &musbotg_device_isoc_methods) { 4072 4073 ntd = xfer->nframes + 1 /* SYNC */ ; 4074 4075 } else { 4076 4077 ntd = 0; 4078 } 4079 4080 /* 4081 * check if "usbd_transfer_setup_sub" set an error 4082 */ 4083 if (parm->err) { 4084 return; 4085 } 4086 /* 4087 * allocate transfer descriptors 4088 */ 4089 last_obj = NULL; 4090 4091 /* 4092 * get profile stuff 4093 */ 4094 if (ntd) { 4095 4096 ep_no = xfer->endpointno & UE_ADDR; 4097 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4098 4099 if (pf == NULL) { 4100 /* should not happen */ 4101 parm->err = USB_ERR_INVAL; 4102 return; 4103 } 4104 } else { 4105 ep_no = 0; 4106 pf = NULL; 4107 } 4108 4109 /* align data */ 4110 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4111 4112 for (n = 0; n != ntd; n++) { 4113 4114 struct musbotg_td *td; 4115 4116 if (parm->buf) { 4117 4118 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4119 4120 /* init TD */ 4121 td->max_frame_size = xfer->max_frame_size; 4122 td->ep_no = ep_no; 4123 td->obj_next = last_obj; 4124 4125 last_obj = td; 4126 } 4127 parm->size[0] += sizeof(*td); 4128 } 4129 4130 xfer->td_start[0] = last_obj; 4131 } 4132 4133 static void 4134 musbotg_xfer_unsetup(struct usb_xfer *xfer) 4135 { 4136 return; 4137 } 4138 4139 static void 4140 musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4141 { 4142 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4143 4144 if (sc->sc_mode == MUSB2_HOST_MODE) 4145 *pus = 2000; /* microseconds */ 4146 else 4147 *pus = 0; 4148 } 4149 4150 static void 4151 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4152 struct usb_endpoint *ep) 4153 { 4154 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4155 4156 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 4157 ep, udev->address, 4158 edesc->bEndpointAddress, udev->flags.usb_mode, 4159 sc->sc_rt_addr); 4160 4161 if (udev->device_index != sc->sc_rt_addr) { 4162 switch (edesc->bmAttributes & UE_XFERTYPE) { 4163 case UE_CONTROL: 4164 ep->methods = &musbotg_device_ctrl_methods; 4165 break; 4166 case UE_INTERRUPT: 4167 ep->methods = &musbotg_device_intr_methods; 4168 break; 4169 case UE_ISOCHRONOUS: 4170 ep->methods = &musbotg_device_isoc_methods; 4171 break; 4172 case UE_BULK: 4173 ep->methods = &musbotg_device_bulk_methods; 4174 break; 4175 default: 4176 /* do nothing */ 4177 break; 4178 } 4179 } 4180 } 4181 4182 static void 4183 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4184 { 4185 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 4186 4187 switch (state) { 4188 case USB_HW_POWER_SUSPEND: 4189 musbotg_suspend(sc); 4190 break; 4191 case USB_HW_POWER_SHUTDOWN: 4192 musbotg_uninit(sc); 4193 break; 4194 case USB_HW_POWER_RESUME: 4195 musbotg_resume(sc); 4196 break; 4197 default: 4198 break; 4199 } 4200 } 4201 4202 struct usb_bus_methods musbotg_bus_methods = 4203 { 4204 .endpoint_init = &musbotg_ep_init, 4205 .get_dma_delay = &musbotg_get_dma_delay, 4206 .xfer_setup = &musbotg_xfer_setup, 4207 .xfer_unsetup = &musbotg_xfer_unsetup, 4208 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 4209 .xfer_stall = &musbotg_xfer_stall, 4210 .set_stall = &musbotg_set_stall, 4211 .clear_stall = &musbotg_clear_stall, 4212 .roothub_exec = &musbotg_roothub_exec, 4213 .xfer_poll = &musbotg_do_poll, 4214 .set_hw_power_sleep = &musbotg_set_hw_power_sleep, 4215 }; 4216