1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Thanks to Mentor Graphics for providing a reference driver for this 29 * USB chip at their homepage. 30 */ 31 32 /* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39 #include <dev/usb/usb.h> 40 #include <dev/usb/usb_mfunc.h> 41 #include <dev/usb/usb_error.h> 42 #include <dev/usb/usb_defs.h> 43 44 #define USB_DEBUG_VAR musbotgdebug 45 46 #include <dev/usb/usb_core.h> 47 #include <dev/usb/usb_debug.h> 48 #include <dev/usb/usb_busdma.h> 49 #include <dev/usb/usb_process.h> 50 #include <dev/usb/usb_sw_transfer.h> 51 #include <dev/usb/usb_transfer.h> 52 #include <dev/usb/usb_device.h> 53 #include <dev/usb/usb_hub.h> 54 #include <dev/usb/usb_util.h> 55 56 #include <dev/usb/usb_controller.h> 57 #include <dev/usb/usb_bus.h> 58 #include <dev/usb/controller/musb_otg.h> 59 60 #define MUSBOTG_INTR_ENDPT 1 61 62 #define MUSBOTG_BUS2SC(bus) \ 63 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 64 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 65 66 #define MUSBOTG_PC2SC(pc) \ 67 MUSBOTG_BUS2SC((pc)->tag_parent->info->bus) 68 69 #if USB_DEBUG 70 static int musbotgdebug = 0; 71 72 SYSCTL_NODE(_hw_usb2, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 73 SYSCTL_INT(_hw_usb2_musbotg, OID_AUTO, debug, CTLFLAG_RW, 74 &musbotgdebug, 0, "Debug level"); 75 #endif 76 77 /* prototypes */ 78 79 struct usb2_bus_methods musbotg_bus_methods; 80 struct usb2_pipe_methods musbotg_device_bulk_methods; 81 struct usb2_pipe_methods musbotg_device_ctrl_methods; 82 struct usb2_pipe_methods musbotg_device_intr_methods; 83 struct usb2_pipe_methods musbotg_device_isoc_methods; 84 struct usb2_pipe_methods musbotg_root_ctrl_methods; 85 struct usb2_pipe_methods musbotg_root_intr_methods; 86 87 static musbotg_cmd_t musbotg_setup_rx; 88 static musbotg_cmd_t musbotg_setup_data_rx; 89 static musbotg_cmd_t musbotg_setup_data_tx; 90 static musbotg_cmd_t musbotg_setup_status; 91 static musbotg_cmd_t musbotg_data_rx; 92 static musbotg_cmd_t musbotg_data_tx; 93 static void musbotg_device_done(struct usb2_xfer *, usb2_error_t); 94 static void musbotg_do_poll(struct usb2_bus *); 95 static void musbotg_root_ctrl_poll(struct musbotg_softc *); 96 static void musbotg_standard_done(struct usb2_xfer *); 97 static void musbotg_interrupt_poll(struct musbotg_softc *); 98 99 static usb2_sw_transfer_func_t musbotg_root_intr_done; 100 static usb2_sw_transfer_func_t musbotg_root_ctrl_done; 101 102 /* 103 * Here is a configuration that the chip supports. 104 */ 105 static const struct usb2_hw_ep_profile musbotg_ep_profile[1] = { 106 107 [0] = { 108 .max_in_frame_size = 64,/* fixed */ 109 .max_out_frame_size = 64, /* fixed */ 110 .is_simplex = 1, 111 .support_control = 1, 112 } 113 }; 114 115 static void 116 musbotg_get_hw_ep_profile(struct usb2_device *udev, 117 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 118 { 119 struct musbotg_softc *sc; 120 121 sc = MUSBOTG_BUS2SC(udev->bus); 122 123 if (ep_addr == 0) { 124 /* control endpoint */ 125 *ppf = musbotg_ep_profile; 126 } else if (ep_addr <= sc->sc_ep_max) { 127 /* other endpoints */ 128 *ppf = sc->sc_hw_ep_profile + ep_addr; 129 } else { 130 *ppf = NULL; 131 } 132 } 133 134 static void 135 musbotg_clocks_on(struct musbotg_softc *sc) 136 { 137 if (sc->sc_flags.clocks_off && 138 sc->sc_flags.port_powered) { 139 140 DPRINTFN(4, "\n"); 141 142 if (sc->sc_clocks_on) { 143 (sc->sc_clocks_on) (sc->sc_clocks_arg); 144 } 145 sc->sc_flags.clocks_off = 0; 146 147 /* XXX enable Transceiver */ 148 } 149 } 150 151 static void 152 musbotg_clocks_off(struct musbotg_softc *sc) 153 { 154 if (!sc->sc_flags.clocks_off) { 155 156 DPRINTFN(4, "\n"); 157 158 /* XXX disable Transceiver */ 159 160 if (sc->sc_clocks_off) { 161 (sc->sc_clocks_off) (sc->sc_clocks_arg); 162 } 163 sc->sc_flags.clocks_off = 1; 164 } 165 } 166 167 static void 168 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 169 { 170 uint8_t temp; 171 172 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 173 if (on) 174 temp |= MUSB2_MASK_SOFTC; 175 else 176 temp &= ~MUSB2_MASK_SOFTC; 177 178 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 179 } 180 181 static void 182 musbotg_pull_up(struct musbotg_softc *sc) 183 { 184 /* pullup D+, if possible */ 185 186 if (!sc->sc_flags.d_pulled_up && 187 sc->sc_flags.port_powered) { 188 sc->sc_flags.d_pulled_up = 1; 189 musbotg_pull_common(sc, 1); 190 } 191 } 192 193 static void 194 musbotg_pull_down(struct musbotg_softc *sc) 195 { 196 /* pulldown D+, if possible */ 197 198 if (sc->sc_flags.d_pulled_up) { 199 sc->sc_flags.d_pulled_up = 0; 200 musbotg_pull_common(sc, 0); 201 } 202 } 203 204 static void 205 musbotg_wakeup_peer(struct usb2_xfer *xfer) 206 { 207 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 208 uint8_t temp; 209 210 if (!(sc->sc_flags.status_suspend)) { 211 return; 212 } 213 214 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 215 temp |= MUSB2_MASK_RESUME; 216 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 217 218 /* wait 8 milliseconds */ 219 /* Wait for reset to complete. */ 220 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 221 222 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 223 temp &= ~MUSB2_MASK_RESUME; 224 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 225 } 226 227 static void 228 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 229 { 230 DPRINTFN(4, "addr=%d\n", addr); 231 addr &= 0x7F; 232 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 233 } 234 235 static uint8_t 236 musbotg_setup_rx(struct musbotg_td *td) 237 { 238 struct musbotg_softc *sc; 239 struct usb2_device_request req; 240 uint16_t count; 241 uint8_t csr; 242 243 /* get pointer to softc */ 244 sc = MUSBOTG_PC2SC(td->pc); 245 246 /* select endpoint 0 */ 247 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 248 249 /* read out FIFO status */ 250 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 251 252 DPRINTFN(4, "csr=0x%02x\n", csr); 253 254 /* 255 * NOTE: If DATAEND is set we should not call the 256 * callback, hence the status stage is not complete. 257 */ 258 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 259 /* wait for interrupt */ 260 goto not_complete; 261 } 262 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 263 /* clear SENTSTALL */ 264 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 265 /* get latest status */ 266 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 267 /* update EP0 state */ 268 sc->sc_ep0_busy = 0; 269 } 270 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 271 /* clear SETUPEND */ 272 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 273 MUSB2_MASK_CSR0L_SETUPEND_CLR); 274 /* get latest status */ 275 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 276 /* update EP0 state */ 277 sc->sc_ep0_busy = 0; 278 } 279 if (sc->sc_ep0_busy) { 280 /* abort any ongoing transfer */ 281 if (!td->did_stall) { 282 DPRINTFN(4, "stalling\n"); 283 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 284 MUSB2_MASK_CSR0L_SENDSTALL); 285 td->did_stall = 1; 286 } 287 goto not_complete; 288 } 289 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 290 goto not_complete; 291 } 292 /* get the packet byte count */ 293 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 294 295 /* verify data length */ 296 if (count != td->remainder) { 297 DPRINTFN(0, "Invalid SETUP packet " 298 "length, %d bytes\n", count); 299 goto not_complete; 300 } 301 if (count != sizeof(req)) { 302 DPRINTFN(0, "Unsupported SETUP packet " 303 "length, %d bytes\n", count); 304 goto not_complete; 305 } 306 /* receive data */ 307 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 308 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 309 310 /* copy data into real buffer */ 311 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 312 313 td->offset = sizeof(req); 314 td->remainder = 0; 315 316 /* set pending command */ 317 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 318 319 /* we need set stall or dataend after this */ 320 sc->sc_ep0_busy = 1; 321 322 /* sneak peek the set address */ 323 if ((req.bmRequestType == UT_WRITE_DEVICE) && 324 (req.bRequest == UR_SET_ADDRESS)) { 325 sc->sc_dv_addr = req.wValue[0] & 0x7F; 326 } else { 327 sc->sc_dv_addr = 0xFF; 328 } 329 return (0); /* complete */ 330 331 not_complete: 332 return (1); /* not complete */ 333 } 334 335 /* Control endpoint only data handling functions (RX/TX/SYNC) */ 336 337 static uint8_t 338 musbotg_setup_data_rx(struct musbotg_td *td) 339 { 340 struct usb2_page_search buf_res; 341 struct musbotg_softc *sc; 342 uint16_t count; 343 uint8_t csr; 344 uint8_t got_short; 345 346 /* get pointer to softc */ 347 sc = MUSBOTG_PC2SC(td->pc); 348 349 /* select endpoint 0 */ 350 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 351 352 /* check if a command is pending */ 353 if (sc->sc_ep0_cmd) { 354 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 355 sc->sc_ep0_cmd = 0; 356 } 357 /* read out FIFO status */ 358 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 359 360 DPRINTFN(4, "csr=0x%02x\n", csr); 361 362 got_short = 0; 363 364 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 365 MUSB2_MASK_CSR0L_SENTSTALL)) { 366 if (td->remainder == 0) { 367 /* 368 * We are actually complete and have 369 * received the next SETUP 370 */ 371 DPRINTFN(4, "faking complete\n"); 372 return (0); /* complete */ 373 } 374 /* 375 * USB Host Aborted the transfer. 376 */ 377 td->error = 1; 378 return (0); /* complete */ 379 } 380 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 381 return (1); /* not complete */ 382 } 383 /* get the packet byte count */ 384 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 385 386 /* verify the packet byte count */ 387 if (count != td->max_frame_size) { 388 if (count < td->max_frame_size) { 389 /* we have a short packet */ 390 td->short_pkt = 1; 391 got_short = 1; 392 } else { 393 /* invalid USB packet */ 394 td->error = 1; 395 return (0); /* we are complete */ 396 } 397 } 398 /* verify the packet byte count */ 399 if (count > td->remainder) { 400 /* invalid USB packet */ 401 td->error = 1; 402 return (0); /* we are complete */ 403 } 404 while (count > 0) { 405 uint32_t temp; 406 407 usb2_get_page(td->pc, td->offset, &buf_res); 408 409 /* get correct length */ 410 if (buf_res.length > count) { 411 buf_res.length = count; 412 } 413 /* check for unaligned memory address */ 414 if (USB_P2U(buf_res.buffer) & 3) { 415 416 temp = count & ~3; 417 418 if (temp) { 419 /* receive data 4 bytes at a time */ 420 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 421 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 422 temp / 4); 423 } 424 temp = count & 3; 425 if (temp) { 426 /* receive data 1 byte at a time */ 427 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 428 MUSB2_REG_EPFIFO(0), 429 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 430 } 431 usb2_copy_in(td->pc, td->offset, 432 sc->sc_bounce_buf, count); 433 434 /* update offset and remainder */ 435 td->offset += count; 436 td->remainder -= count; 437 break; 438 } 439 /* check if we can optimise */ 440 if (buf_res.length >= 4) { 441 442 /* receive data 4 bytes at a time */ 443 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 444 MUSB2_REG_EPFIFO(0), buf_res.buffer, 445 buf_res.length / 4); 446 447 temp = buf_res.length & ~3; 448 449 /* update counters */ 450 count -= temp; 451 td->offset += temp; 452 td->remainder -= temp; 453 continue; 454 } 455 /* receive data */ 456 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 457 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 458 459 /* update counters */ 460 count -= buf_res.length; 461 td->offset += buf_res.length; 462 td->remainder -= buf_res.length; 463 } 464 465 /* check if we are complete */ 466 if ((td->remainder == 0) || got_short) { 467 if (td->short_pkt) { 468 /* we are complete */ 469 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 470 return (0); 471 } 472 /* else need to receive a zero length packet */ 473 } 474 /* write command - need more data */ 475 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 476 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 477 return (1); /* not complete */ 478 } 479 480 static uint8_t 481 musbotg_setup_data_tx(struct musbotg_td *td) 482 { 483 struct usb2_page_search buf_res; 484 struct musbotg_softc *sc; 485 uint16_t count; 486 uint8_t csr; 487 488 /* get pointer to softc */ 489 sc = MUSBOTG_PC2SC(td->pc); 490 491 /* select endpoint 0 */ 492 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 493 494 /* check if a command is pending */ 495 if (sc->sc_ep0_cmd) { 496 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 497 sc->sc_ep0_cmd = 0; 498 } 499 /* read out FIFO status */ 500 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 501 502 DPRINTFN(4, "csr=0x%02x\n", csr); 503 504 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 505 MUSB2_MASK_CSR0L_SENTSTALL)) { 506 /* 507 * The current transfer was aborted 508 * by the USB Host 509 */ 510 td->error = 1; 511 return (0); /* complete */ 512 } 513 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 514 return (1); /* not complete */ 515 } 516 count = td->max_frame_size; 517 if (td->remainder < count) { 518 /* we have a short packet */ 519 td->short_pkt = 1; 520 count = td->remainder; 521 } 522 while (count > 0) { 523 uint32_t temp; 524 525 usb2_get_page(td->pc, td->offset, &buf_res); 526 527 /* get correct length */ 528 if (buf_res.length > count) { 529 buf_res.length = count; 530 } 531 /* check for unaligned memory address */ 532 if (USB_P2U(buf_res.buffer) & 3) { 533 534 usb2_copy_out(td->pc, td->offset, 535 sc->sc_bounce_buf, count); 536 537 temp = count & ~3; 538 539 if (temp) { 540 /* transmit data 4 bytes at a time */ 541 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 542 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 543 temp / 4); 544 } 545 temp = count & 3; 546 if (temp) { 547 /* receive data 1 byte at a time */ 548 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 549 MUSB2_REG_EPFIFO(0), 550 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 551 } 552 /* update offset and remainder */ 553 td->offset += count; 554 td->remainder -= count; 555 break; 556 } 557 /* check if we can optimise */ 558 if (buf_res.length >= 4) { 559 560 /* transmit data 4 bytes at a time */ 561 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 562 MUSB2_REG_EPFIFO(0), buf_res.buffer, 563 buf_res.length / 4); 564 565 temp = buf_res.length & ~3; 566 567 /* update counters */ 568 count -= temp; 569 td->offset += temp; 570 td->remainder -= temp; 571 continue; 572 } 573 /* transmit data */ 574 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 575 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 576 577 /* update counters */ 578 count -= buf_res.length; 579 td->offset += buf_res.length; 580 td->remainder -= buf_res.length; 581 } 582 583 /* check remainder */ 584 if (td->remainder == 0) { 585 if (td->short_pkt) { 586 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 587 return (0); /* complete */ 588 } 589 /* else we need to transmit a short packet */ 590 } 591 /* write command */ 592 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 593 MUSB2_MASK_CSR0L_TXPKTRDY); 594 595 return (1); /* not complete */ 596 } 597 598 static uint8_t 599 musbotg_setup_status(struct musbotg_td *td) 600 { 601 struct musbotg_softc *sc; 602 uint8_t csr; 603 604 /* get pointer to softc */ 605 sc = MUSBOTG_PC2SC(td->pc); 606 607 /* select endpoint 0 */ 608 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 609 610 if (sc->sc_ep0_busy) { 611 sc->sc_ep0_busy = 0; 612 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 613 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 614 sc->sc_ep0_cmd = 0; 615 } 616 /* read out FIFO status */ 617 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 618 619 DPRINTFN(4, "csr=0x%02x\n", csr); 620 621 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 622 /* wait for interrupt */ 623 return (1); /* not complete */ 624 } 625 if (sc->sc_dv_addr != 0xFF) { 626 /* write function address */ 627 musbotg_set_address(sc, sc->sc_dv_addr); 628 } 629 return (0); /* complete */ 630 } 631 632 static uint8_t 633 musbotg_data_rx(struct musbotg_td *td) 634 { 635 struct usb2_page_search buf_res; 636 struct musbotg_softc *sc; 637 uint16_t count; 638 uint8_t csr; 639 uint8_t to; 640 uint8_t got_short; 641 642 to = 8; /* don't loop forever! */ 643 got_short = 0; 644 645 /* get pointer to softc */ 646 sc = MUSBOTG_PC2SC(td->pc); 647 648 /* select endpoint */ 649 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 650 651 repeat: 652 /* read out FIFO status */ 653 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 654 655 DPRINTFN(4, "csr=0x%02x\n", csr); 656 657 /* clear overrun */ 658 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 659 /* make sure we don't clear "RXPKTRDY" */ 660 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 661 MUSB2_MASK_CSRL_RXPKTRDY); 662 } 663 /* check status */ 664 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 665 return (1); /* not complete */ 666 } 667 /* get the packet byte count */ 668 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 669 670 DPRINTFN(4, "count=0x%04x\n", count); 671 672 /* 673 * Check for short or invalid packet: 674 */ 675 if (count != td->max_frame_size) { 676 if (count < td->max_frame_size) { 677 /* we have a short packet */ 678 td->short_pkt = 1; 679 got_short = 1; 680 } else { 681 /* invalid USB packet */ 682 td->error = 1; 683 return (0); /* we are complete */ 684 } 685 } 686 /* verify the packet byte count */ 687 if (count > td->remainder) { 688 /* invalid USB packet */ 689 td->error = 1; 690 return (0); /* we are complete */ 691 } 692 while (count > 0) { 693 uint32_t temp; 694 695 usb2_get_page(td->pc, td->offset, &buf_res); 696 697 /* get correct length */ 698 if (buf_res.length > count) { 699 buf_res.length = count; 700 } 701 /* check for unaligned memory address */ 702 if (USB_P2U(buf_res.buffer) & 3) { 703 704 temp = count & ~3; 705 706 if (temp) { 707 /* receive data 4 bytes at a time */ 708 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 709 MUSB2_REG_EPFIFO(td->ep_no), sc->sc_bounce_buf, 710 temp / 4); 711 } 712 temp = count & 3; 713 if (temp) { 714 /* receive data 1 byte at a time */ 715 bus_space_read_multi_1(sc->sc_io_tag, 716 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 717 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 718 } 719 usb2_copy_in(td->pc, td->offset, 720 sc->sc_bounce_buf, count); 721 722 /* update offset and remainder */ 723 td->offset += count; 724 td->remainder -= count; 725 break; 726 } 727 /* check if we can optimise */ 728 if (buf_res.length >= 4) { 729 730 /* receive data 4 bytes at a time */ 731 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 732 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 733 buf_res.length / 4); 734 735 temp = buf_res.length & ~3; 736 737 /* update counters */ 738 count -= temp; 739 td->offset += temp; 740 td->remainder -= temp; 741 continue; 742 } 743 /* receive data */ 744 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 745 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 746 buf_res.length); 747 748 /* update counters */ 749 count -= buf_res.length; 750 td->offset += buf_res.length; 751 td->remainder -= buf_res.length; 752 } 753 754 /* clear status bits */ 755 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 756 757 /* check if we are complete */ 758 if ((td->remainder == 0) || got_short) { 759 if (td->short_pkt) { 760 /* we are complete */ 761 return (0); 762 } 763 /* else need to receive a zero length packet */ 764 } 765 if (--to) { 766 goto repeat; 767 } 768 return (1); /* not complete */ 769 } 770 771 static uint8_t 772 musbotg_data_tx(struct musbotg_td *td) 773 { 774 struct usb2_page_search buf_res; 775 struct musbotg_softc *sc; 776 uint16_t count; 777 uint8_t csr; 778 uint8_t to; 779 780 to = 8; /* don't loop forever! */ 781 782 /* get pointer to softc */ 783 sc = MUSBOTG_PC2SC(td->pc); 784 785 /* select endpoint */ 786 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 787 788 repeat: 789 790 /* read out FIFO status */ 791 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 792 793 DPRINTFN(4, "csr=0x%02x\n", csr); 794 795 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 796 MUSB2_MASK_CSRL_TXUNDERRUN)) { 797 /* clear status bits */ 798 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 799 } 800 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 801 return (1); /* not complete */ 802 } 803 /* check for short packet */ 804 count = td->max_frame_size; 805 if (td->remainder < count) { 806 /* we have a short packet */ 807 td->short_pkt = 1; 808 count = td->remainder; 809 } 810 while (count > 0) { 811 uint32_t temp; 812 813 usb2_get_page(td->pc, td->offset, &buf_res); 814 815 /* get correct length */ 816 if (buf_res.length > count) { 817 buf_res.length = count; 818 } 819 /* check for unaligned memory address */ 820 if (USB_P2U(buf_res.buffer) & 3) { 821 822 usb2_copy_out(td->pc, td->offset, 823 sc->sc_bounce_buf, count); 824 825 temp = count & ~3; 826 827 if (temp) { 828 /* transmit data 4 bytes at a time */ 829 bus_space_write_multi_4(sc->sc_io_tag, 830 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 831 sc->sc_bounce_buf, temp / 4); 832 } 833 temp = count & 3; 834 if (temp) { 835 /* receive data 1 byte at a time */ 836 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 837 MUSB2_REG_EPFIFO(td->ep_no), 838 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 839 } 840 /* update offset and remainder */ 841 td->offset += count; 842 td->remainder -= count; 843 break; 844 } 845 /* check if we can optimise */ 846 if (buf_res.length >= 4) { 847 848 /* transmit data 4 bytes at a time */ 849 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 850 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 851 buf_res.length / 4); 852 853 temp = buf_res.length & ~3; 854 855 /* update counters */ 856 count -= temp; 857 td->offset += temp; 858 td->remainder -= temp; 859 continue; 860 } 861 /* transmit data */ 862 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 863 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 864 buf_res.length); 865 866 /* update counters */ 867 count -= buf_res.length; 868 td->offset += buf_res.length; 869 td->remainder -= buf_res.length; 870 } 871 872 /* write command */ 873 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 874 MUSB2_MASK_CSRL_TXPKTRDY); 875 876 /* check remainder */ 877 if (td->remainder == 0) { 878 if (td->short_pkt) { 879 return (0); /* complete */ 880 } 881 /* else we need to transmit a short packet */ 882 } 883 if (--to) { 884 goto repeat; 885 } 886 return (1); /* not complete */ 887 } 888 889 static uint8_t 890 musbotg_xfer_do_fifo(struct usb2_xfer *xfer) 891 { 892 struct musbotg_softc *sc; 893 struct musbotg_td *td; 894 895 DPRINTFN(8, "\n"); 896 897 td = xfer->td_transfer_cache; 898 while (1) { 899 if ((td->func) (td)) { 900 /* operation in progress */ 901 break; 902 } 903 if (((void *)td) == xfer->td_transfer_last) { 904 goto done; 905 } 906 if (td->error) { 907 goto done; 908 } else if (td->remainder > 0) { 909 /* 910 * We had a short transfer. If there is no alternate 911 * next, stop processing ! 912 */ 913 if (!td->alt_next) { 914 goto done; 915 } 916 } 917 /* 918 * Fetch the next transfer descriptor and transfer 919 * some flags to the next transfer descriptor 920 */ 921 td = td->obj_next; 922 xfer->td_transfer_cache = td; 923 } 924 return (1); /* not complete */ 925 926 done: 927 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 928 929 /* compute all actual lengths */ 930 931 musbotg_standard_done(xfer); 932 933 return (0); /* complete */ 934 } 935 936 static void 937 musbotg_interrupt_poll(struct musbotg_softc *sc) 938 { 939 struct usb2_xfer *xfer; 940 941 repeat: 942 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 943 if (!musbotg_xfer_do_fifo(xfer)) { 944 /* queue has been modified */ 945 goto repeat; 946 } 947 } 948 } 949 950 void 951 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 952 { 953 DPRINTFN(4, "vbus = %u\n", is_on); 954 955 USB_BUS_LOCK(&sc->sc_bus); 956 if (is_on) { 957 if (!sc->sc_flags.status_vbus) { 958 sc->sc_flags.status_vbus = 1; 959 960 /* complete root HUB interrupt endpoint */ 961 962 usb2_sw_transfer(&sc->sc_root_intr, 963 &musbotg_root_intr_done); 964 } 965 } else { 966 if (sc->sc_flags.status_vbus) { 967 sc->sc_flags.status_vbus = 0; 968 sc->sc_flags.status_bus_reset = 0; 969 sc->sc_flags.status_suspend = 0; 970 sc->sc_flags.change_suspend = 0; 971 sc->sc_flags.change_connect = 1; 972 973 /* complete root HUB interrupt endpoint */ 974 975 usb2_sw_transfer(&sc->sc_root_intr, 976 &musbotg_root_intr_done); 977 } 978 } 979 980 USB_BUS_UNLOCK(&sc->sc_bus); 981 } 982 983 void 984 musbotg_interrupt(struct musbotg_softc *sc) 985 { 986 uint16_t rx_status; 987 uint16_t tx_status; 988 uint8_t usb_status; 989 uint8_t temp; 990 uint8_t to = 2; 991 992 USB_BUS_LOCK(&sc->sc_bus); 993 994 repeat: 995 996 /* read all interrupt registers */ 997 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 998 999 /* read all FIFO interrupts */ 1000 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 1001 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 1002 1003 /* check for any bus state change interrupts */ 1004 1005 if (usb_status & (MUSB2_MASK_IRESET | 1006 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP)) { 1007 1008 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 1009 1010 if (usb_status & MUSB2_MASK_IRESET) { 1011 1012 /* set correct state */ 1013 sc->sc_flags.status_bus_reset = 1; 1014 sc->sc_flags.status_suspend = 0; 1015 sc->sc_flags.change_suspend = 0; 1016 sc->sc_flags.change_connect = 1; 1017 1018 /* determine line speed */ 1019 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 1020 if (temp & MUSB2_MASK_HSMODE) 1021 sc->sc_flags.status_high_speed = 1; 1022 else 1023 sc->sc_flags.status_high_speed = 0; 1024 1025 /* 1026 * After reset all interrupts are on and we need to 1027 * turn them off! 1028 */ 1029 temp = MUSB2_MASK_IRESET; 1030 /* disable resume interrupt */ 1031 temp &= ~MUSB2_MASK_IRESUME; 1032 /* enable suspend interrupt */ 1033 temp |= MUSB2_MASK_ISUSP; 1034 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1035 /* disable TX and RX interrupts */ 1036 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1037 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1038 } 1039 /* 1040 * If RXRSM and RXSUSP is set at the same time we interpret 1041 * that like RESUME. Resume is set when there is at least 3 1042 * milliseconds of inactivity on the USB BUS. 1043 */ 1044 if (usb_status & MUSB2_MASK_IRESUME) { 1045 if (sc->sc_flags.status_suspend) { 1046 sc->sc_flags.status_suspend = 0; 1047 sc->sc_flags.change_suspend = 1; 1048 1049 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1050 /* disable resume interrupt */ 1051 temp &= ~MUSB2_MASK_IRESUME; 1052 /* enable suspend interrupt */ 1053 temp |= MUSB2_MASK_ISUSP; 1054 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1055 } 1056 } else if (usb_status & MUSB2_MASK_ISUSP) { 1057 if (!sc->sc_flags.status_suspend) { 1058 sc->sc_flags.status_suspend = 1; 1059 sc->sc_flags.change_suspend = 1; 1060 1061 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1062 /* disable suspend interrupt */ 1063 temp &= ~MUSB2_MASK_ISUSP; 1064 /* enable resume interrupt */ 1065 temp |= MUSB2_MASK_IRESUME; 1066 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1067 } 1068 } 1069 /* complete root HUB interrupt endpoint */ 1070 1071 usb2_sw_transfer(&sc->sc_root_intr, 1072 &musbotg_root_intr_done); 1073 } 1074 /* check for any endpoint interrupts */ 1075 1076 if (rx_status || tx_status) { 1077 DPRINTFN(4, "real endpoint interrupt " 1078 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 1079 } 1080 /* poll one time regardless of FIFO status */ 1081 1082 musbotg_interrupt_poll(sc); 1083 1084 if (--to) 1085 goto repeat; 1086 1087 USB_BUS_UNLOCK(&sc->sc_bus); 1088 } 1089 1090 static void 1091 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 1092 { 1093 struct musbotg_td *td; 1094 1095 /* get current Transfer Descriptor */ 1096 td = temp->td_next; 1097 temp->td = td; 1098 1099 /* prepare for next TD */ 1100 temp->td_next = td->obj_next; 1101 1102 /* fill out the Transfer Descriptor */ 1103 td->func = temp->func; 1104 td->pc = temp->pc; 1105 td->offset = temp->offset; 1106 td->remainder = temp->len; 1107 td->error = 0; 1108 td->did_stall = 0; 1109 td->short_pkt = temp->short_pkt; 1110 td->alt_next = temp->setup_alt_next; 1111 } 1112 1113 static void 1114 musbotg_setup_standard_chain(struct usb2_xfer *xfer) 1115 { 1116 struct musbotg_std_temp temp; 1117 struct musbotg_softc *sc; 1118 struct musbotg_td *td; 1119 uint32_t x; 1120 uint8_t ep_no; 1121 1122 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1123 xfer->address, UE_GET_ADDR(xfer->endpoint), 1124 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1125 1126 temp.max_frame_size = xfer->max_frame_size; 1127 1128 td = xfer->td_start[0]; 1129 xfer->td_transfer_first = td; 1130 xfer->td_transfer_cache = td; 1131 1132 /* setup temp */ 1133 1134 temp.td = NULL; 1135 temp.td_next = xfer->td_start[0]; 1136 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1137 temp.offset = 0; 1138 1139 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1140 ep_no = (xfer->endpoint & UE_ADDR); 1141 1142 /* check if we should prepend a setup message */ 1143 1144 if (xfer->flags_int.control_xfr) { 1145 if (xfer->flags_int.control_hdr) { 1146 1147 temp.func = &musbotg_setup_rx; 1148 temp.len = xfer->frlengths[0]; 1149 temp.pc = xfer->frbuffers + 0; 1150 temp.short_pkt = temp.len ? 1 : 0; 1151 1152 musbotg_setup_standard_chain_sub(&temp); 1153 } 1154 x = 1; 1155 } else { 1156 x = 0; 1157 } 1158 1159 if (x != xfer->nframes) { 1160 if (xfer->endpoint & UE_DIR_IN) { 1161 if (xfer->flags_int.control_xfr) 1162 temp.func = &musbotg_setup_data_tx; 1163 else 1164 temp.func = &musbotg_data_tx; 1165 } else { 1166 if (xfer->flags_int.control_xfr) 1167 temp.func = &musbotg_setup_data_rx; 1168 else 1169 temp.func = &musbotg_data_rx; 1170 } 1171 1172 /* setup "pc" pointer */ 1173 temp.pc = xfer->frbuffers + x; 1174 } 1175 while (x != xfer->nframes) { 1176 1177 /* DATA0 / DATA1 message */ 1178 1179 temp.len = xfer->frlengths[x]; 1180 1181 x++; 1182 1183 if (x == xfer->nframes) { 1184 temp.setup_alt_next = 0; 1185 } 1186 if (temp.len == 0) { 1187 1188 /* make sure that we send an USB packet */ 1189 1190 temp.short_pkt = 0; 1191 1192 } else { 1193 1194 /* regular data transfer */ 1195 1196 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1197 } 1198 1199 musbotg_setup_standard_chain_sub(&temp); 1200 1201 if (xfer->flags_int.isochronous_xfr) { 1202 temp.offset += temp.len; 1203 } else { 1204 /* get next Page Cache pointer */ 1205 temp.pc = xfer->frbuffers + x; 1206 } 1207 } 1208 1209 /* always setup a valid "pc" pointer for status and sync */ 1210 temp.pc = xfer->frbuffers + 0; 1211 1212 /* check if we should append a status stage */ 1213 1214 if (xfer->flags_int.control_xfr && 1215 !xfer->flags_int.control_act) { 1216 1217 /* 1218 * Send a DATA1 message and invert the current 1219 * endpoint direction. 1220 */ 1221 temp.func = &musbotg_setup_status; 1222 temp.len = 0; 1223 temp.short_pkt = 0; 1224 1225 musbotg_setup_standard_chain_sub(&temp); 1226 } 1227 /* must have at least one frame! */ 1228 td = temp.td; 1229 xfer->td_transfer_last = td; 1230 } 1231 1232 static void 1233 musbotg_timeout(void *arg) 1234 { 1235 struct usb2_xfer *xfer = arg; 1236 1237 DPRINTFN(1, "xfer=%p\n", xfer); 1238 1239 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1240 1241 /* transfer is transferred */ 1242 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 1243 } 1244 1245 static void 1246 musbotg_ep_int_set(struct usb2_xfer *xfer, uint8_t on) 1247 { 1248 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1249 uint16_t temp; 1250 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1251 1252 /* 1253 * Only enable the endpoint interrupt when we are 1254 * actually waiting for data, hence we are dealing 1255 * with level triggered interrupts ! 1256 */ 1257 if (ep_no == 0) { 1258 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1259 if (on) 1260 temp |= MUSB2_MASK_EPINT(0); 1261 else 1262 temp &= ~MUSB2_MASK_EPINT(0); 1263 1264 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1265 } else { 1266 if (USB_GET_DATA_ISREAD(xfer)) { 1267 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 1268 if (on) 1269 temp |= MUSB2_MASK_EPINT(ep_no); 1270 else 1271 temp &= ~MUSB2_MASK_EPINT(ep_no); 1272 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 1273 1274 } else { 1275 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1276 if (on) 1277 temp |= MUSB2_MASK_EPINT(ep_no); 1278 else 1279 temp &= ~MUSB2_MASK_EPINT(ep_no); 1280 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1281 } 1282 } 1283 } 1284 1285 static void 1286 musbotg_start_standard_chain(struct usb2_xfer *xfer) 1287 { 1288 DPRINTFN(8, "\n"); 1289 1290 /* poll one time */ 1291 if (musbotg_xfer_do_fifo(xfer)) { 1292 1293 musbotg_ep_int_set(xfer, 1); 1294 1295 DPRINTFN(14, "enabled interrupts on endpoint\n"); 1296 1297 /* put transfer on interrupt queue */ 1298 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1299 1300 /* start timeout, if any */ 1301 if (xfer->timeout != 0) { 1302 usb2_transfer_timeout_ms(xfer, 1303 &musbotg_timeout, xfer->timeout); 1304 } 1305 } 1306 } 1307 1308 static void 1309 musbotg_root_intr_done(struct usb2_xfer *xfer, 1310 struct usb2_sw_transfer *std) 1311 { 1312 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1313 1314 DPRINTFN(8, "\n"); 1315 1316 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1317 1318 if (std->state != USB_SW_TR_PRE_DATA) { 1319 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1320 /* transfer transferred */ 1321 musbotg_device_done(xfer, std->err); 1322 } 1323 goto done; 1324 } 1325 /* setup buffer */ 1326 std->ptr = sc->sc_hub_idata; 1327 std->len = sizeof(sc->sc_hub_idata); 1328 1329 /* set port bit */ 1330 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1331 1332 done: 1333 return; 1334 } 1335 1336 static usb2_error_t 1337 musbotg_standard_done_sub(struct usb2_xfer *xfer) 1338 { 1339 struct musbotg_td *td; 1340 uint32_t len; 1341 uint8_t error; 1342 1343 DPRINTFN(8, "\n"); 1344 1345 td = xfer->td_transfer_cache; 1346 1347 do { 1348 len = td->remainder; 1349 1350 if (xfer->aframes != xfer->nframes) { 1351 /* 1352 * Verify the length and subtract 1353 * the remainder from "frlengths[]": 1354 */ 1355 if (len > xfer->frlengths[xfer->aframes]) { 1356 td->error = 1; 1357 } else { 1358 xfer->frlengths[xfer->aframes] -= len; 1359 } 1360 } 1361 /* Check for transfer error */ 1362 if (td->error) { 1363 /* the transfer is finished */ 1364 error = 1; 1365 td = NULL; 1366 break; 1367 } 1368 /* Check for short transfer */ 1369 if (len > 0) { 1370 if (xfer->flags_int.short_frames_ok) { 1371 /* follow alt next */ 1372 if (td->alt_next) { 1373 td = td->obj_next; 1374 } else { 1375 td = NULL; 1376 } 1377 } else { 1378 /* the transfer is finished */ 1379 td = NULL; 1380 } 1381 error = 0; 1382 break; 1383 } 1384 td = td->obj_next; 1385 1386 /* this USB frame is complete */ 1387 error = 0; 1388 break; 1389 1390 } while (0); 1391 1392 /* update transfer cache */ 1393 1394 xfer->td_transfer_cache = td; 1395 1396 return (error ? 1397 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1398 } 1399 1400 static void 1401 musbotg_standard_done(struct usb2_xfer *xfer) 1402 { 1403 usb2_error_t err = 0; 1404 1405 DPRINTFN(12, "xfer=%p pipe=%p transfer done\n", 1406 xfer, xfer->pipe); 1407 1408 /* reset scanner */ 1409 1410 xfer->td_transfer_cache = xfer->td_transfer_first; 1411 1412 if (xfer->flags_int.control_xfr) { 1413 1414 if (xfer->flags_int.control_hdr) { 1415 1416 err = musbotg_standard_done_sub(xfer); 1417 } 1418 xfer->aframes = 1; 1419 1420 if (xfer->td_transfer_cache == NULL) { 1421 goto done; 1422 } 1423 } 1424 while (xfer->aframes != xfer->nframes) { 1425 1426 err = musbotg_standard_done_sub(xfer); 1427 xfer->aframes++; 1428 1429 if (xfer->td_transfer_cache == NULL) { 1430 goto done; 1431 } 1432 } 1433 1434 if (xfer->flags_int.control_xfr && 1435 !xfer->flags_int.control_act) { 1436 1437 err = musbotg_standard_done_sub(xfer); 1438 } 1439 done: 1440 musbotg_device_done(xfer, err); 1441 } 1442 1443 /*------------------------------------------------------------------------* 1444 * musbotg_device_done 1445 * 1446 * NOTE: this function can be called more than one time on the 1447 * same USB transfer! 1448 *------------------------------------------------------------------------*/ 1449 static void 1450 musbotg_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1451 { 1452 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1453 1454 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1455 xfer, xfer->pipe, error); 1456 1457 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1458 1459 musbotg_ep_int_set(xfer, 0); 1460 1461 DPRINTFN(14, "disabled interrupts on endpoint\n"); 1462 } 1463 /* dequeue transfer and start next transfer */ 1464 usb2_transfer_done(xfer, error); 1465 } 1466 1467 static void 1468 musbotg_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1469 struct usb2_pipe *pipe) 1470 { 1471 struct musbotg_softc *sc; 1472 uint8_t ep_no; 1473 1474 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1475 1476 DPRINTFN(4, "pipe=%p\n", pipe); 1477 1478 if (xfer) { 1479 /* cancel any ongoing transfers */ 1480 musbotg_device_done(xfer, USB_ERR_STALLED); 1481 } 1482 /* set FORCESTALL */ 1483 sc = MUSBOTG_BUS2SC(udev->bus); 1484 1485 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1486 1487 /* select endpoint */ 1488 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1489 1490 if (pipe->edesc->bEndpointAddress & UE_DIR_IN) { 1491 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1492 MUSB2_MASK_CSRL_TXSENDSTALL); 1493 } else { 1494 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1495 MUSB2_MASK_CSRL_RXSENDSTALL); 1496 } 1497 } 1498 1499 static void 1500 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 1501 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1502 { 1503 uint16_t mps; 1504 uint16_t temp; 1505 uint8_t csr; 1506 1507 if (ep_type == UE_CONTROL) { 1508 /* clearing stall is not needed */ 1509 return; 1510 } 1511 /* select endpoint */ 1512 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1513 1514 /* compute max frame size */ 1515 mps = wMaxPacket & 0x7FF; 1516 switch ((wMaxPacket >> 11) & 3) { 1517 case 1: 1518 mps *= 2; 1519 break; 1520 case 2: 1521 mps *= 3; 1522 break; 1523 default: 1524 break; 1525 } 1526 1527 if (ep_dir == UE_DIR_IN) { 1528 1529 temp = 0; 1530 1531 /* Configure endpoint */ 1532 switch (ep_type) { 1533 case UE_INTERRUPT: 1534 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1535 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1536 MUSB2_MASK_CSRH_TXMODE | temp); 1537 break; 1538 case UE_ISOCHRONOUS: 1539 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1540 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1541 MUSB2_MASK_CSRH_TXMODE | 1542 MUSB2_MASK_CSRH_TXISO | temp); 1543 break; 1544 case UE_BULK: 1545 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1546 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1547 MUSB2_MASK_CSRH_TXMODE | temp); 1548 break; 1549 default: 1550 break; 1551 } 1552 1553 /* Need to flush twice in case of double bufring */ 1554 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1555 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1556 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1557 MUSB2_MASK_CSRL_TXFFLUSH); 1558 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1559 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1560 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1561 MUSB2_MASK_CSRL_TXFFLUSH); 1562 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1563 } 1564 } 1565 /* reset data toggle */ 1566 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1567 MUSB2_MASK_CSRL_TXDT_CLR); 1568 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1569 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1570 1571 /* set double/single buffering */ 1572 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 1573 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1574 max_in_frame_size / 2)) { 1575 /* double buffer */ 1576 temp &= ~(1 << ep_no); 1577 } else { 1578 /* single buffer */ 1579 temp |= (1 << ep_no); 1580 } 1581 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 1582 1583 /* clear sent stall */ 1584 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 1585 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1586 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1587 } 1588 } else { 1589 1590 temp = 0; 1591 1592 /* Configure endpoint */ 1593 switch (ep_type) { 1594 case UE_INTERRUPT: 1595 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1596 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1597 MUSB2_MASK_CSRH_RXNYET | temp); 1598 break; 1599 case UE_ISOCHRONOUS: 1600 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1601 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1602 MUSB2_MASK_CSRH_RXNYET | 1603 MUSB2_MASK_CSRH_RXISO | temp); 1604 break; 1605 case UE_BULK: 1606 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1607 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 1608 break; 1609 default: 1610 break; 1611 } 1612 1613 /* Need to flush twice in case of double bufring */ 1614 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1615 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1616 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1617 MUSB2_MASK_CSRL_RXFFLUSH); 1618 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1619 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1620 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1621 MUSB2_MASK_CSRL_RXFFLUSH); 1622 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1623 } 1624 } 1625 /* reset data toggle */ 1626 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1627 MUSB2_MASK_CSRL_RXDT_CLR); 1628 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1629 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1630 1631 /* set double/single buffering */ 1632 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 1633 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1634 max_out_frame_size / 2)) { 1635 /* double buffer */ 1636 temp &= ~(1 << ep_no); 1637 } else { 1638 /* single buffer */ 1639 temp |= (1 << ep_no); 1640 } 1641 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 1642 1643 /* clear sent stall */ 1644 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 1645 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1646 } 1647 } 1648 } 1649 1650 static void 1651 musbotg_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1652 { 1653 struct musbotg_softc *sc; 1654 struct usb2_endpoint_descriptor *ed; 1655 1656 DPRINTFN(4, "pipe=%p\n", pipe); 1657 1658 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1659 1660 /* check mode */ 1661 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1662 /* not supported */ 1663 return; 1664 } 1665 /* get softc */ 1666 sc = MUSBOTG_BUS2SC(udev->bus); 1667 1668 /* get endpoint descriptor */ 1669 ed = pipe->edesc; 1670 1671 /* reset endpoint */ 1672 musbotg_clear_stall_sub(sc, 1673 UGETW(ed->wMaxPacketSize), 1674 (ed->bEndpointAddress & UE_ADDR), 1675 (ed->bmAttributes & UE_XFERTYPE), 1676 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1677 } 1678 1679 usb2_error_t 1680 musbotg_init(struct musbotg_softc *sc) 1681 { 1682 struct usb2_hw_ep_profile *pf; 1683 uint8_t nrx; 1684 uint8_t ntx; 1685 uint8_t temp; 1686 uint8_t fsize; 1687 uint8_t frx; 1688 uint8_t ftx; 1689 1690 DPRINTFN(1, "start\n"); 1691 1692 /* set up the bus structure */ 1693 sc->sc_bus.usbrev = USB_REV_2_0; 1694 sc->sc_bus.methods = &musbotg_bus_methods; 1695 1696 USB_BUS_LOCK(&sc->sc_bus); 1697 1698 /* turn on clocks */ 1699 1700 if (sc->sc_clocks_on) { 1701 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1702 } 1703 /* wait a little for things to stabilise */ 1704 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1705 1706 /* disable all interrupts */ 1707 1708 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1709 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1710 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1711 1712 /* disable pullup */ 1713 1714 musbotg_pull_common(sc, 0); 1715 1716 /* wait a little bit (10ms) */ 1717 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1718 1719 /* disable double packet buffering */ 1720 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 1721 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 1722 1723 /* enable HighSpeed and ISO Update flags */ 1724 1725 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 1726 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 1727 1728 /* clear Session bit, if set */ 1729 1730 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 1731 temp &= ~MUSB2_MASK_SESS; 1732 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 1733 1734 DPRINTF("DEVCTL=0x%02x\n", temp); 1735 1736 /* disable testmode */ 1737 1738 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 1739 1740 /* set default value */ 1741 1742 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 1743 1744 /* select endpoint index 0 */ 1745 1746 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1747 1748 /* read out number of endpoints */ 1749 1750 nrx = 1751 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 1752 1753 ntx = 1754 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 1755 1756 /* these numbers exclude the control endpoint */ 1757 1758 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 1759 1760 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 1761 if (sc->sc_ep_max == 0) { 1762 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 1763 } 1764 /* read out configuration data */ 1765 1766 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 1767 1768 DPRINTFN(2, "Config Data: 0x%02x\n", 1769 sc->sc_conf_data); 1770 1771 DPRINTFN(2, "HW version: 0x%04x\n", 1772 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 1773 1774 /* initialise endpoint profiles */ 1775 1776 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 1777 pf = sc->sc_hw_ep_profile + temp; 1778 1779 /* select endpoint */ 1780 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 1781 1782 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 1783 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;; 1784 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 1785 1786 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u\n", 1787 temp, pf->max_in_frame_size, 1788 pf->max_out_frame_size); 1789 1790 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 1791 pf->max_in_frame_size = 1 << ftx; 1792 pf->max_out_frame_size = 1 << frx; 1793 pf->is_simplex = 0; /* duplex */ 1794 pf->support_multi_buffer = 1; 1795 pf->support_bulk = 1; 1796 pf->support_interrupt = 1; 1797 pf->support_isochronous = 1; 1798 pf->support_in = 1; 1799 pf->support_out = 1; 1800 } else if (frx && (temp <= nrx)) { 1801 pf->max_out_frame_size = 1 << frx; 1802 pf->is_simplex = 1; /* simplex */ 1803 pf->support_multi_buffer = 1; 1804 pf->support_bulk = 1; 1805 pf->support_interrupt = 1; 1806 pf->support_isochronous = 1; 1807 pf->support_out = 1; 1808 } else if (ftx && (temp <= ntx)) { 1809 pf->max_in_frame_size = 1 << ftx; 1810 pf->is_simplex = 1; /* simplex */ 1811 pf->support_multi_buffer = 1; 1812 pf->support_bulk = 1; 1813 pf->support_interrupt = 1; 1814 pf->support_isochronous = 1; 1815 pf->support_in = 1; 1816 } 1817 } 1818 1819 /* turn on default interrupts */ 1820 1821 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 1822 MUSB2_MASK_IRESET); 1823 1824 musbotg_clocks_off(sc); 1825 1826 USB_BUS_UNLOCK(&sc->sc_bus); 1827 1828 /* catch any lost interrupts */ 1829 1830 musbotg_do_poll(&sc->sc_bus); 1831 1832 return (0); /* success */ 1833 } 1834 1835 void 1836 musbotg_uninit(struct musbotg_softc *sc) 1837 { 1838 USB_BUS_LOCK(&sc->sc_bus); 1839 1840 /* disable all interrupts */ 1841 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1842 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1843 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1844 1845 sc->sc_flags.port_powered = 0; 1846 sc->sc_flags.status_vbus = 0; 1847 sc->sc_flags.status_bus_reset = 0; 1848 sc->sc_flags.status_suspend = 0; 1849 sc->sc_flags.change_suspend = 0; 1850 sc->sc_flags.change_connect = 1; 1851 1852 musbotg_pull_down(sc); 1853 musbotg_clocks_off(sc); 1854 USB_BUS_UNLOCK(&sc->sc_bus); 1855 } 1856 1857 void 1858 musbotg_suspend(struct musbotg_softc *sc) 1859 { 1860 return; 1861 } 1862 1863 void 1864 musbotg_resume(struct musbotg_softc *sc) 1865 { 1866 return; 1867 } 1868 1869 static void 1870 musbotg_do_poll(struct usb2_bus *bus) 1871 { 1872 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 1873 1874 USB_BUS_LOCK(&sc->sc_bus); 1875 musbotg_interrupt_poll(sc); 1876 musbotg_root_ctrl_poll(sc); 1877 USB_BUS_UNLOCK(&sc->sc_bus); 1878 } 1879 1880 /*------------------------------------------------------------------------* 1881 * musbotg bulk support 1882 *------------------------------------------------------------------------*/ 1883 static void 1884 musbotg_device_bulk_open(struct usb2_xfer *xfer) 1885 { 1886 return; 1887 } 1888 1889 static void 1890 musbotg_device_bulk_close(struct usb2_xfer *xfer) 1891 { 1892 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1893 } 1894 1895 static void 1896 musbotg_device_bulk_enter(struct usb2_xfer *xfer) 1897 { 1898 return; 1899 } 1900 1901 static void 1902 musbotg_device_bulk_start(struct usb2_xfer *xfer) 1903 { 1904 /* setup TDs */ 1905 musbotg_setup_standard_chain(xfer); 1906 musbotg_start_standard_chain(xfer); 1907 } 1908 1909 struct usb2_pipe_methods musbotg_device_bulk_methods = 1910 { 1911 .open = musbotg_device_bulk_open, 1912 .close = musbotg_device_bulk_close, 1913 .enter = musbotg_device_bulk_enter, 1914 .start = musbotg_device_bulk_start, 1915 .enter_is_cancelable = 1, 1916 .start_is_cancelable = 1, 1917 }; 1918 1919 /*------------------------------------------------------------------------* 1920 * musbotg control support 1921 *------------------------------------------------------------------------*/ 1922 static void 1923 musbotg_device_ctrl_open(struct usb2_xfer *xfer) 1924 { 1925 return; 1926 } 1927 1928 static void 1929 musbotg_device_ctrl_close(struct usb2_xfer *xfer) 1930 { 1931 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1932 } 1933 1934 static void 1935 musbotg_device_ctrl_enter(struct usb2_xfer *xfer) 1936 { 1937 return; 1938 } 1939 1940 static void 1941 musbotg_device_ctrl_start(struct usb2_xfer *xfer) 1942 { 1943 /* setup TDs */ 1944 musbotg_setup_standard_chain(xfer); 1945 musbotg_start_standard_chain(xfer); 1946 } 1947 1948 struct usb2_pipe_methods musbotg_device_ctrl_methods = 1949 { 1950 .open = musbotg_device_ctrl_open, 1951 .close = musbotg_device_ctrl_close, 1952 .enter = musbotg_device_ctrl_enter, 1953 .start = musbotg_device_ctrl_start, 1954 .enter_is_cancelable = 1, 1955 .start_is_cancelable = 1, 1956 }; 1957 1958 /*------------------------------------------------------------------------* 1959 * musbotg interrupt support 1960 *------------------------------------------------------------------------*/ 1961 static void 1962 musbotg_device_intr_open(struct usb2_xfer *xfer) 1963 { 1964 return; 1965 } 1966 1967 static void 1968 musbotg_device_intr_close(struct usb2_xfer *xfer) 1969 { 1970 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1971 } 1972 1973 static void 1974 musbotg_device_intr_enter(struct usb2_xfer *xfer) 1975 { 1976 return; 1977 } 1978 1979 static void 1980 musbotg_device_intr_start(struct usb2_xfer *xfer) 1981 { 1982 /* setup TDs */ 1983 musbotg_setup_standard_chain(xfer); 1984 musbotg_start_standard_chain(xfer); 1985 } 1986 1987 struct usb2_pipe_methods musbotg_device_intr_methods = 1988 { 1989 .open = musbotg_device_intr_open, 1990 .close = musbotg_device_intr_close, 1991 .enter = musbotg_device_intr_enter, 1992 .start = musbotg_device_intr_start, 1993 .enter_is_cancelable = 1, 1994 .start_is_cancelable = 1, 1995 }; 1996 1997 /*------------------------------------------------------------------------* 1998 * musbotg full speed isochronous support 1999 *------------------------------------------------------------------------*/ 2000 static void 2001 musbotg_device_isoc_open(struct usb2_xfer *xfer) 2002 { 2003 return; 2004 } 2005 2006 static void 2007 musbotg_device_isoc_close(struct usb2_xfer *xfer) 2008 { 2009 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2010 } 2011 2012 static void 2013 musbotg_device_isoc_enter(struct usb2_xfer *xfer) 2014 { 2015 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2016 uint32_t temp; 2017 uint32_t nframes; 2018 uint32_t fs_frames; 2019 2020 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 2021 xfer, xfer->pipe->isoc_next, xfer->nframes); 2022 2023 /* get the current frame index */ 2024 2025 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 2026 2027 /* 2028 * check if the frame index is within the window where the frames 2029 * will be inserted 2030 */ 2031 temp = (nframes - xfer->pipe->isoc_next) & MUSB2_MASK_FRAME; 2032 2033 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2034 fs_frames = (xfer->nframes + 7) / 8; 2035 } else { 2036 fs_frames = xfer->nframes; 2037 } 2038 2039 if ((xfer->pipe->is_synced == 0) || 2040 (temp < fs_frames)) { 2041 /* 2042 * If there is data underflow or the pipe queue is 2043 * empty we schedule the transfer a few frames ahead 2044 * of the current frame position. Else two isochronous 2045 * transfers might overlap. 2046 */ 2047 xfer->pipe->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 2048 xfer->pipe->is_synced = 1; 2049 DPRINTFN(2, "start next=%d\n", xfer->pipe->isoc_next); 2050 } 2051 /* 2052 * compute how many milliseconds the insertion is ahead of the 2053 * current frame position: 2054 */ 2055 temp = (xfer->pipe->isoc_next - nframes) & MUSB2_MASK_FRAME; 2056 2057 /* 2058 * pre-compute when the isochronous transfer will be finished: 2059 */ 2060 xfer->isoc_time_complete = 2061 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2062 fs_frames; 2063 2064 /* compute frame number for next insertion */ 2065 xfer->pipe->isoc_next += fs_frames; 2066 2067 /* setup TDs */ 2068 musbotg_setup_standard_chain(xfer); 2069 } 2070 2071 static void 2072 musbotg_device_isoc_start(struct usb2_xfer *xfer) 2073 { 2074 /* start TD chain */ 2075 musbotg_start_standard_chain(xfer); 2076 } 2077 2078 struct usb2_pipe_methods musbotg_device_isoc_methods = 2079 { 2080 .open = musbotg_device_isoc_open, 2081 .close = musbotg_device_isoc_close, 2082 .enter = musbotg_device_isoc_enter, 2083 .start = musbotg_device_isoc_start, 2084 .enter_is_cancelable = 1, 2085 .start_is_cancelable = 1, 2086 }; 2087 2088 /*------------------------------------------------------------------------* 2089 * musbotg root control support 2090 *------------------------------------------------------------------------* 2091 * simulate a hardware HUB by handling 2092 * all the necessary requests 2093 *------------------------------------------------------------------------*/ 2094 static void 2095 musbotg_root_ctrl_open(struct usb2_xfer *xfer) 2096 { 2097 return; 2098 } 2099 2100 static void 2101 musbotg_root_ctrl_close(struct usb2_xfer *xfer) 2102 { 2103 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2104 2105 if (sc->sc_root_ctrl.xfer == xfer) { 2106 sc->sc_root_ctrl.xfer = NULL; 2107 } 2108 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2109 } 2110 2111 /* 2112 * USB descriptors for the virtual Root HUB: 2113 */ 2114 2115 static const struct usb2_device_descriptor musbotg_devd = { 2116 .bLength = sizeof(struct usb2_device_descriptor), 2117 .bDescriptorType = UDESC_DEVICE, 2118 .bcdUSB = {0x00, 0x02}, 2119 .bDeviceClass = UDCLASS_HUB, 2120 .bDeviceSubClass = UDSUBCLASS_HUB, 2121 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2122 .bMaxPacketSize = 64, 2123 .bcdDevice = {0x00, 0x01}, 2124 .iManufacturer = 1, 2125 .iProduct = 2, 2126 .bNumConfigurations = 1, 2127 }; 2128 2129 static const struct usb2_device_qualifier musbotg_odevd = { 2130 .bLength = sizeof(struct usb2_device_qualifier), 2131 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 2132 .bcdUSB = {0x00, 0x02}, 2133 .bDeviceClass = UDCLASS_HUB, 2134 .bDeviceSubClass = UDSUBCLASS_HUB, 2135 .bDeviceProtocol = UDPROTO_FSHUB, 2136 .bMaxPacketSize0 = 0, 2137 .bNumConfigurations = 0, 2138 }; 2139 2140 static const struct musbotg_config_desc musbotg_confd = { 2141 .confd = { 2142 .bLength = sizeof(struct usb2_config_descriptor), 2143 .bDescriptorType = UDESC_CONFIG, 2144 .wTotalLength[0] = sizeof(musbotg_confd), 2145 .bNumInterface = 1, 2146 .bConfigurationValue = 1, 2147 .iConfiguration = 0, 2148 .bmAttributes = UC_SELF_POWERED, 2149 .bMaxPower = 0, 2150 }, 2151 .ifcd = { 2152 .bLength = sizeof(struct usb2_interface_descriptor), 2153 .bDescriptorType = UDESC_INTERFACE, 2154 .bNumEndpoints = 1, 2155 .bInterfaceClass = UICLASS_HUB, 2156 .bInterfaceSubClass = UISUBCLASS_HUB, 2157 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2158 }, 2159 2160 .endpd = { 2161 .bLength = sizeof(struct usb2_endpoint_descriptor), 2162 .bDescriptorType = UDESC_ENDPOINT, 2163 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 2164 .bmAttributes = UE_INTERRUPT, 2165 .wMaxPacketSize[0] = 8, 2166 .bInterval = 255, 2167 }, 2168 }; 2169 2170 static const struct usb2_hub_descriptor_min musbotg_hubd = { 2171 .bDescLength = sizeof(musbotg_hubd), 2172 .bDescriptorType = UDESC_HUB, 2173 .bNbrPorts = 1, 2174 .wHubCharacteristics[0] = 2175 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 2176 .wHubCharacteristics[1] = 2177 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 16, 2178 .bPwrOn2PwrGood = 50, 2179 .bHubContrCurrent = 0, 2180 .DeviceRemovable = {0}, /* port is removable */ 2181 }; 2182 2183 #define STRING_LANG \ 2184 0x09, 0x04, /* American English */ 2185 2186 #define STRING_VENDOR \ 2187 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \ 2188 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0 2189 2190 #define STRING_PRODUCT \ 2191 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 2192 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 2193 'U', 0, 'B', 0, 2194 2195 USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab); 2196 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 2197 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 2198 2199 static void 2200 musbotg_root_ctrl_enter(struct usb2_xfer *xfer) 2201 { 2202 return; 2203 } 2204 2205 static void 2206 musbotg_root_ctrl_start(struct usb2_xfer *xfer) 2207 { 2208 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2209 2210 sc->sc_root_ctrl.xfer = xfer; 2211 2212 usb2_bus_roothub_exec(xfer->xroot->bus); 2213 } 2214 2215 static void 2216 musbotg_root_ctrl_task(struct usb2_bus *bus) 2217 { 2218 musbotg_root_ctrl_poll(MUSBOTG_BUS2SC(bus)); 2219 } 2220 2221 static void 2222 musbotg_root_ctrl_done(struct usb2_xfer *xfer, 2223 struct usb2_sw_transfer *std) 2224 { 2225 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2226 uint16_t value; 2227 uint16_t index; 2228 2229 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2230 2231 if (std->state != USB_SW_TR_SETUP) { 2232 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2233 /* transfer transferred */ 2234 musbotg_device_done(xfer, std->err); 2235 } 2236 goto done; 2237 } 2238 /* buffer reset */ 2239 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 2240 std->len = 0; 2241 2242 value = UGETW(std->req.wValue); 2243 index = UGETW(std->req.wIndex); 2244 2245 /* demultiplex the control request */ 2246 2247 switch (std->req.bmRequestType) { 2248 case UT_READ_DEVICE: 2249 switch (std->req.bRequest) { 2250 case UR_GET_DESCRIPTOR: 2251 goto tr_handle_get_descriptor; 2252 case UR_GET_CONFIG: 2253 goto tr_handle_get_config; 2254 case UR_GET_STATUS: 2255 goto tr_handle_get_status; 2256 default: 2257 goto tr_stalled; 2258 } 2259 break; 2260 2261 case UT_WRITE_DEVICE: 2262 switch (std->req.bRequest) { 2263 case UR_SET_ADDRESS: 2264 goto tr_handle_set_address; 2265 case UR_SET_CONFIG: 2266 goto tr_handle_set_config; 2267 case UR_CLEAR_FEATURE: 2268 goto tr_valid; /* nop */ 2269 case UR_SET_DESCRIPTOR: 2270 goto tr_valid; /* nop */ 2271 case UR_SET_FEATURE: 2272 default: 2273 goto tr_stalled; 2274 } 2275 break; 2276 2277 case UT_WRITE_ENDPOINT: 2278 switch (std->req.bRequest) { 2279 case UR_CLEAR_FEATURE: 2280 switch (UGETW(std->req.wValue)) { 2281 case UF_ENDPOINT_HALT: 2282 goto tr_handle_clear_halt; 2283 case UF_DEVICE_REMOTE_WAKEUP: 2284 goto tr_handle_clear_wakeup; 2285 default: 2286 goto tr_stalled; 2287 } 2288 break; 2289 case UR_SET_FEATURE: 2290 switch (UGETW(std->req.wValue)) { 2291 case UF_ENDPOINT_HALT: 2292 goto tr_handle_set_halt; 2293 case UF_DEVICE_REMOTE_WAKEUP: 2294 goto tr_handle_set_wakeup; 2295 default: 2296 goto tr_stalled; 2297 } 2298 break; 2299 case UR_SYNCH_FRAME: 2300 goto tr_valid; /* nop */ 2301 default: 2302 goto tr_stalled; 2303 } 2304 break; 2305 2306 case UT_READ_ENDPOINT: 2307 switch (std->req.bRequest) { 2308 case UR_GET_STATUS: 2309 goto tr_handle_get_ep_status; 2310 default: 2311 goto tr_stalled; 2312 } 2313 break; 2314 2315 case UT_WRITE_INTERFACE: 2316 switch (std->req.bRequest) { 2317 case UR_SET_INTERFACE: 2318 goto tr_handle_set_interface; 2319 case UR_CLEAR_FEATURE: 2320 goto tr_valid; /* nop */ 2321 case UR_SET_FEATURE: 2322 default: 2323 goto tr_stalled; 2324 } 2325 break; 2326 2327 case UT_READ_INTERFACE: 2328 switch (std->req.bRequest) { 2329 case UR_GET_INTERFACE: 2330 goto tr_handle_get_interface; 2331 case UR_GET_STATUS: 2332 goto tr_handle_get_iface_status; 2333 default: 2334 goto tr_stalled; 2335 } 2336 break; 2337 2338 case UT_WRITE_CLASS_INTERFACE: 2339 case UT_WRITE_VENDOR_INTERFACE: 2340 /* XXX forward */ 2341 break; 2342 2343 case UT_READ_CLASS_INTERFACE: 2344 case UT_READ_VENDOR_INTERFACE: 2345 /* XXX forward */ 2346 break; 2347 2348 case UT_WRITE_CLASS_DEVICE: 2349 switch (std->req.bRequest) { 2350 case UR_CLEAR_FEATURE: 2351 goto tr_valid; 2352 case UR_SET_DESCRIPTOR: 2353 case UR_SET_FEATURE: 2354 break; 2355 default: 2356 goto tr_stalled; 2357 } 2358 break; 2359 2360 case UT_WRITE_CLASS_OTHER: 2361 switch (std->req.bRequest) { 2362 case UR_CLEAR_FEATURE: 2363 goto tr_handle_clear_port_feature; 2364 case UR_SET_FEATURE: 2365 goto tr_handle_set_port_feature; 2366 case UR_CLEAR_TT_BUFFER: 2367 case UR_RESET_TT: 2368 case UR_STOP_TT: 2369 goto tr_valid; 2370 2371 default: 2372 goto tr_stalled; 2373 } 2374 break; 2375 2376 case UT_READ_CLASS_OTHER: 2377 switch (std->req.bRequest) { 2378 case UR_GET_TT_STATE: 2379 goto tr_handle_get_tt_state; 2380 case UR_GET_STATUS: 2381 goto tr_handle_get_port_status; 2382 default: 2383 goto tr_stalled; 2384 } 2385 break; 2386 2387 case UT_READ_CLASS_DEVICE: 2388 switch (std->req.bRequest) { 2389 case UR_GET_DESCRIPTOR: 2390 goto tr_handle_get_class_descriptor; 2391 case UR_GET_STATUS: 2392 goto tr_handle_get_class_status; 2393 2394 default: 2395 goto tr_stalled; 2396 } 2397 break; 2398 default: 2399 goto tr_stalled; 2400 } 2401 goto tr_valid; 2402 2403 tr_handle_get_descriptor: 2404 switch (value >> 8) { 2405 case UDESC_DEVICE: 2406 if (value & 0xff) { 2407 goto tr_stalled; 2408 } 2409 std->len = sizeof(musbotg_devd); 2410 std->ptr = USB_ADD_BYTES(&musbotg_devd, 0); 2411 goto tr_valid; 2412 case UDESC_CONFIG: 2413 if (value & 0xff) { 2414 goto tr_stalled; 2415 } 2416 std->len = sizeof(musbotg_confd); 2417 std->ptr = USB_ADD_BYTES(&musbotg_confd, 0); 2418 goto tr_valid; 2419 case UDESC_STRING: 2420 switch (value & 0xff) { 2421 case 0: /* Language table */ 2422 std->len = sizeof(musbotg_langtab); 2423 std->ptr = USB_ADD_BYTES(&musbotg_langtab, 0); 2424 goto tr_valid; 2425 2426 case 1: /* Vendor */ 2427 std->len = sizeof(musbotg_vendor); 2428 std->ptr = USB_ADD_BYTES(&musbotg_vendor, 0); 2429 goto tr_valid; 2430 2431 case 2: /* Product */ 2432 std->len = sizeof(musbotg_product); 2433 std->ptr = USB_ADD_BYTES(&musbotg_product, 0); 2434 goto tr_valid; 2435 default: 2436 break; 2437 } 2438 break; 2439 default: 2440 goto tr_stalled; 2441 } 2442 goto tr_stalled; 2443 2444 tr_handle_get_config: 2445 std->len = 1; 2446 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2447 goto tr_valid; 2448 2449 tr_handle_get_status: 2450 std->len = 2; 2451 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2452 goto tr_valid; 2453 2454 tr_handle_set_address: 2455 if (value & 0xFF00) { 2456 goto tr_stalled; 2457 } 2458 sc->sc_rt_addr = value; 2459 goto tr_valid; 2460 2461 tr_handle_set_config: 2462 if (value >= 2) { 2463 goto tr_stalled; 2464 } 2465 sc->sc_conf = value; 2466 goto tr_valid; 2467 2468 tr_handle_get_interface: 2469 std->len = 1; 2470 sc->sc_hub_temp.wValue[0] = 0; 2471 goto tr_valid; 2472 2473 tr_handle_get_tt_state: 2474 tr_handle_get_class_status: 2475 tr_handle_get_iface_status: 2476 tr_handle_get_ep_status: 2477 std->len = 2; 2478 USETW(sc->sc_hub_temp.wValue, 0); 2479 goto tr_valid; 2480 2481 tr_handle_set_halt: 2482 tr_handle_set_interface: 2483 tr_handle_set_wakeup: 2484 tr_handle_clear_wakeup: 2485 tr_handle_clear_halt: 2486 goto tr_valid; 2487 2488 tr_handle_clear_port_feature: 2489 if (index != 1) { 2490 goto tr_stalled; 2491 } 2492 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2493 2494 switch (value) { 2495 case UHF_PORT_SUSPEND: 2496 musbotg_wakeup_peer(xfer); 2497 break; 2498 2499 case UHF_PORT_ENABLE: 2500 sc->sc_flags.port_enabled = 0; 2501 break; 2502 2503 case UHF_PORT_TEST: 2504 case UHF_PORT_INDICATOR: 2505 case UHF_C_PORT_ENABLE: 2506 case UHF_C_PORT_OVER_CURRENT: 2507 case UHF_C_PORT_RESET: 2508 /* nops */ 2509 break; 2510 case UHF_PORT_POWER: 2511 sc->sc_flags.port_powered = 0; 2512 musbotg_pull_down(sc); 2513 musbotg_clocks_off(sc); 2514 break; 2515 case UHF_C_PORT_CONNECTION: 2516 sc->sc_flags.change_connect = 0; 2517 break; 2518 case UHF_C_PORT_SUSPEND: 2519 sc->sc_flags.change_suspend = 0; 2520 break; 2521 default: 2522 std->err = USB_ERR_IOERROR; 2523 goto done; 2524 } 2525 goto tr_valid; 2526 2527 tr_handle_set_port_feature: 2528 if (index != 1) { 2529 goto tr_stalled; 2530 } 2531 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 2532 2533 switch (value) { 2534 case UHF_PORT_ENABLE: 2535 sc->sc_flags.port_enabled = 1; 2536 break; 2537 case UHF_PORT_SUSPEND: 2538 case UHF_PORT_RESET: 2539 case UHF_PORT_TEST: 2540 case UHF_PORT_INDICATOR: 2541 /* nops */ 2542 break; 2543 case UHF_PORT_POWER: 2544 sc->sc_flags.port_powered = 1; 2545 break; 2546 default: 2547 std->err = USB_ERR_IOERROR; 2548 goto done; 2549 } 2550 goto tr_valid; 2551 2552 tr_handle_get_port_status: 2553 2554 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 2555 2556 if (index != 1) { 2557 goto tr_stalled; 2558 } 2559 if (sc->sc_flags.status_vbus) { 2560 musbotg_clocks_on(sc); 2561 musbotg_pull_up(sc); 2562 } else { 2563 musbotg_pull_down(sc); 2564 musbotg_clocks_off(sc); 2565 } 2566 2567 /* Select Device Side Mode */ 2568 value = UPS_PORT_MODE_DEVICE; 2569 2570 if (sc->sc_flags.status_high_speed) { 2571 value |= UPS_HIGH_SPEED; 2572 } 2573 if (sc->sc_flags.port_powered) { 2574 value |= UPS_PORT_POWER; 2575 } 2576 if (sc->sc_flags.port_enabled) { 2577 value |= UPS_PORT_ENABLED; 2578 } 2579 if (sc->sc_flags.status_vbus && 2580 sc->sc_flags.status_bus_reset) { 2581 value |= UPS_CURRENT_CONNECT_STATUS; 2582 } 2583 if (sc->sc_flags.status_suspend) { 2584 value |= UPS_SUSPEND; 2585 } 2586 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2587 2588 value = 0; 2589 2590 if (sc->sc_flags.change_connect) { 2591 value |= UPS_C_CONNECT_STATUS; 2592 2593 if (sc->sc_flags.status_vbus && 2594 sc->sc_flags.status_bus_reset) { 2595 /* reset EP0 state */ 2596 sc->sc_ep0_busy = 0; 2597 sc->sc_ep0_cmd = 0; 2598 } 2599 } 2600 if (sc->sc_flags.change_suspend) { 2601 value |= UPS_C_SUSPEND; 2602 } 2603 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2604 std->len = sizeof(sc->sc_hub_temp.ps); 2605 goto tr_valid; 2606 2607 tr_handle_get_class_descriptor: 2608 if (value & 0xFF) { 2609 goto tr_stalled; 2610 } 2611 std->ptr = USB_ADD_BYTES(&musbotg_hubd, 0); 2612 std->len = sizeof(musbotg_hubd); 2613 goto tr_valid; 2614 2615 tr_stalled: 2616 std->err = USB_ERR_STALLED; 2617 tr_valid: 2618 done: 2619 return; 2620 } 2621 2622 static void 2623 musbotg_root_ctrl_poll(struct musbotg_softc *sc) 2624 { 2625 usb2_sw_transfer(&sc->sc_root_ctrl, 2626 &musbotg_root_ctrl_done); 2627 } 2628 2629 struct usb2_pipe_methods musbotg_root_ctrl_methods = 2630 { 2631 .open = musbotg_root_ctrl_open, 2632 .close = musbotg_root_ctrl_close, 2633 .enter = musbotg_root_ctrl_enter, 2634 .start = musbotg_root_ctrl_start, 2635 .enter_is_cancelable = 1, 2636 .start_is_cancelable = 0, 2637 }; 2638 2639 /*------------------------------------------------------------------------* 2640 * musbotg root interrupt support 2641 *------------------------------------------------------------------------*/ 2642 static void 2643 musbotg_root_intr_open(struct usb2_xfer *xfer) 2644 { 2645 return; 2646 } 2647 2648 static void 2649 musbotg_root_intr_close(struct usb2_xfer *xfer) 2650 { 2651 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2652 2653 if (sc->sc_root_intr.xfer == xfer) { 2654 sc->sc_root_intr.xfer = NULL; 2655 } 2656 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2657 } 2658 2659 static void 2660 musbotg_root_intr_enter(struct usb2_xfer *xfer) 2661 { 2662 return; 2663 } 2664 2665 static void 2666 musbotg_root_intr_start(struct usb2_xfer *xfer) 2667 { 2668 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2669 2670 sc->sc_root_intr.xfer = xfer; 2671 } 2672 2673 struct usb2_pipe_methods musbotg_root_intr_methods = 2674 { 2675 .open = musbotg_root_intr_open, 2676 .close = musbotg_root_intr_close, 2677 .enter = musbotg_root_intr_enter, 2678 .start = musbotg_root_intr_start, 2679 .enter_is_cancelable = 1, 2680 .start_is_cancelable = 1, 2681 }; 2682 2683 static void 2684 musbotg_xfer_setup(struct usb2_setup_params *parm) 2685 { 2686 const struct usb2_hw_ep_profile *pf; 2687 struct musbotg_softc *sc; 2688 struct usb2_xfer *xfer; 2689 void *last_obj; 2690 uint32_t ntd; 2691 uint32_t n; 2692 uint8_t ep_no; 2693 2694 sc = MUSBOTG_BUS2SC(parm->udev->bus); 2695 xfer = parm->curr_xfer; 2696 2697 /* 2698 * NOTE: This driver does not use any of the parameters that 2699 * are computed from the following values. Just set some 2700 * reasonable dummies: 2701 */ 2702 parm->hc_max_packet_size = 0x400; 2703 parm->hc_max_frame_size = 0x400; 2704 2705 if ((parm->methods == &musbotg_device_isoc_methods) || 2706 (parm->methods == &musbotg_device_intr_methods)) 2707 parm->hc_max_packet_count = 3; 2708 else 2709 parm->hc_max_packet_count = 1; 2710 2711 usb2_transfer_setup_sub(parm); 2712 2713 /* 2714 * compute maximum number of TDs 2715 */ 2716 if (parm->methods == &musbotg_device_ctrl_methods) { 2717 2718 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 2719 2720 } else if (parm->methods == &musbotg_device_bulk_methods) { 2721 2722 ntd = xfer->nframes + 1 /* SYNC */ ; 2723 2724 } else if (parm->methods == &musbotg_device_intr_methods) { 2725 2726 ntd = xfer->nframes + 1 /* SYNC */ ; 2727 2728 } else if (parm->methods == &musbotg_device_isoc_methods) { 2729 2730 ntd = xfer->nframes + 1 /* SYNC */ ; 2731 2732 } else { 2733 2734 ntd = 0; 2735 } 2736 2737 /* 2738 * check if "usb2_transfer_setup_sub" set an error 2739 */ 2740 if (parm->err) { 2741 return; 2742 } 2743 /* 2744 * allocate transfer descriptors 2745 */ 2746 last_obj = NULL; 2747 2748 /* 2749 * get profile stuff 2750 */ 2751 if (ntd) { 2752 2753 ep_no = xfer->endpoint & UE_ADDR; 2754 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 2755 2756 if (pf == NULL) { 2757 /* should not happen */ 2758 parm->err = USB_ERR_INVAL; 2759 return; 2760 } 2761 } else { 2762 ep_no = 0; 2763 pf = NULL; 2764 } 2765 2766 /* align data */ 2767 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2768 2769 for (n = 0; n != ntd; n++) { 2770 2771 struct musbotg_td *td; 2772 2773 if (parm->buf) { 2774 2775 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2776 2777 /* init TD */ 2778 td->max_frame_size = xfer->max_frame_size; 2779 td->ep_no = ep_no; 2780 td->obj_next = last_obj; 2781 2782 last_obj = td; 2783 } 2784 parm->size[0] += sizeof(*td); 2785 } 2786 2787 xfer->td_start[0] = last_obj; 2788 } 2789 2790 static void 2791 musbotg_xfer_unsetup(struct usb2_xfer *xfer) 2792 { 2793 return; 2794 } 2795 2796 static void 2797 musbotg_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2798 struct usb2_pipe *pipe) 2799 { 2800 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 2801 2802 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2803 pipe, udev->address, 2804 edesc->bEndpointAddress, udev->flags.usb2_mode, 2805 sc->sc_rt_addr); 2806 2807 if (udev->device_index == sc->sc_rt_addr) { 2808 2809 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2810 /* not supported */ 2811 return; 2812 } 2813 switch (edesc->bEndpointAddress) { 2814 case USB_CONTROL_ENDPOINT: 2815 pipe->methods = &musbotg_root_ctrl_methods; 2816 break; 2817 case UE_DIR_IN | MUSBOTG_INTR_ENDPT: 2818 pipe->methods = &musbotg_root_intr_methods; 2819 break; 2820 default: 2821 /* do nothing */ 2822 break; 2823 } 2824 } else { 2825 2826 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2827 /* not supported */ 2828 return; 2829 } 2830 if ((udev->speed != USB_SPEED_FULL) && 2831 (udev->speed != USB_SPEED_HIGH)) { 2832 /* not supported */ 2833 return; 2834 } 2835 switch (edesc->bmAttributes & UE_XFERTYPE) { 2836 case UE_CONTROL: 2837 pipe->methods = &musbotg_device_ctrl_methods; 2838 break; 2839 case UE_INTERRUPT: 2840 pipe->methods = &musbotg_device_intr_methods; 2841 break; 2842 case UE_ISOCHRONOUS: 2843 pipe->methods = &musbotg_device_isoc_methods; 2844 break; 2845 case UE_BULK: 2846 pipe->methods = &musbotg_device_bulk_methods; 2847 break; 2848 default: 2849 /* do nothing */ 2850 break; 2851 } 2852 } 2853 } 2854 2855 struct usb2_bus_methods musbotg_bus_methods = 2856 { 2857 .pipe_init = &musbotg_pipe_init, 2858 .xfer_setup = &musbotg_xfer_setup, 2859 .xfer_unsetup = &musbotg_xfer_unsetup, 2860 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 2861 .set_stall = &musbotg_set_stall, 2862 .clear_stall = &musbotg_clear_stall, 2863 .roothub_exec = &musbotg_root_ctrl_task, 2864 }; 2865