1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Thanks to Mentor Graphics for providing a reference driver for this 29 * USB chip at their homepage. 30 */ 31 32 /* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39 #include <dev/usb/usb.h> 40 #include <dev/usb/usb_mfunc.h> 41 #include <dev/usb/usb_error.h> 42 #include <dev/usb/usb_defs.h> 43 44 #define USB_DEBUG_VAR musbotgdebug 45 46 #include <dev/usb/usb_core.h> 47 #include <dev/usb/usb_debug.h> 48 #include <dev/usb/usb_busdma.h> 49 #include <dev/usb/usb_process.h> 50 #include <dev/usb/usb_sw_transfer.h> 51 #include <dev/usb/usb_transfer.h> 52 #include <dev/usb/usb_device.h> 53 #include <dev/usb/usb_hub.h> 54 #include <dev/usb/usb_util.h> 55 56 #include <dev/usb/usb_controller.h> 57 #include <dev/usb/usb_bus.h> 58 #include <dev/usb/controller/musb_otg.h> 59 60 #define MUSBOTG_INTR_ENDPT 1 61 62 #define MUSBOTG_BUS2SC(bus) \ 63 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 64 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 65 66 #define MUSBOTG_PC2SC(pc) \ 67 MUSBOTG_BUS2SC((pc)->tag_parent->info->bus) 68 69 #if USB_DEBUG 70 static int musbotgdebug = 0; 71 72 SYSCTL_NODE(_hw_usb2, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 73 SYSCTL_INT(_hw_usb2_musbotg, OID_AUTO, debug, CTLFLAG_RW, 74 &musbotgdebug, 0, "Debug level"); 75 #endif 76 77 /* prototypes */ 78 79 struct usb2_bus_methods musbotg_bus_methods; 80 struct usb2_pipe_methods musbotg_device_bulk_methods; 81 struct usb2_pipe_methods musbotg_device_ctrl_methods; 82 struct usb2_pipe_methods musbotg_device_intr_methods; 83 struct usb2_pipe_methods musbotg_device_isoc_methods; 84 struct usb2_pipe_methods musbotg_root_ctrl_methods; 85 struct usb2_pipe_methods musbotg_root_intr_methods; 86 87 static musbotg_cmd_t musbotg_setup_rx; 88 static musbotg_cmd_t musbotg_setup_data_rx; 89 static musbotg_cmd_t musbotg_setup_data_tx; 90 static musbotg_cmd_t musbotg_setup_status; 91 static musbotg_cmd_t musbotg_data_rx; 92 static musbotg_cmd_t musbotg_data_tx; 93 static void musbotg_device_done(struct usb2_xfer *, usb2_error_t); 94 static void musbotg_do_poll(struct usb2_bus *); 95 static void musbotg_root_ctrl_poll(struct musbotg_softc *); 96 static void musbotg_standard_done(struct usb2_xfer *); 97 static void musbotg_interrupt_poll(struct musbotg_softc *); 98 99 static usb2_sw_transfer_func_t musbotg_root_intr_done; 100 static usb2_sw_transfer_func_t musbotg_root_ctrl_done; 101 102 /* 103 * Here is a configuration that the chip supports. 104 */ 105 static const struct usb2_hw_ep_profile musbotg_ep_profile[1] = { 106 107 [0] = { 108 .max_in_frame_size = 64,/* fixed */ 109 .max_out_frame_size = 64, /* fixed */ 110 .is_simplex = 1, 111 .support_control = 1, 112 } 113 }; 114 115 static void 116 musbotg_get_hw_ep_profile(struct usb2_device *udev, 117 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 118 { 119 struct musbotg_softc *sc; 120 121 sc = MUSBOTG_BUS2SC(udev->bus); 122 123 if (ep_addr == 0) { 124 /* control endpoint */ 125 *ppf = musbotg_ep_profile; 126 } else if (ep_addr <= sc->sc_ep_max) { 127 /* other endpoints */ 128 *ppf = sc->sc_hw_ep_profile + ep_addr; 129 } else { 130 *ppf = NULL; 131 } 132 } 133 134 static void 135 musbotg_clocks_on(struct musbotg_softc *sc) 136 { 137 if (sc->sc_flags.clocks_off && 138 sc->sc_flags.port_powered) { 139 140 DPRINTFN(4, "\n"); 141 142 if (sc->sc_clocks_on) { 143 (sc->sc_clocks_on) (sc->sc_clocks_arg); 144 } 145 sc->sc_flags.clocks_off = 0; 146 147 /* XXX enable Transceiver */ 148 } 149 } 150 151 static void 152 musbotg_clocks_off(struct musbotg_softc *sc) 153 { 154 if (!sc->sc_flags.clocks_off) { 155 156 DPRINTFN(4, "\n"); 157 158 /* XXX disable Transceiver */ 159 160 if (sc->sc_clocks_off) { 161 (sc->sc_clocks_off) (sc->sc_clocks_arg); 162 } 163 sc->sc_flags.clocks_off = 1; 164 } 165 } 166 167 static void 168 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 169 { 170 uint8_t temp; 171 172 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 173 if (on) 174 temp |= MUSB2_MASK_SOFTC; 175 else 176 temp &= ~MUSB2_MASK_SOFTC; 177 178 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 179 } 180 181 static void 182 musbotg_pull_up(struct musbotg_softc *sc) 183 { 184 /* pullup D+, if possible */ 185 186 if (!sc->sc_flags.d_pulled_up && 187 sc->sc_flags.port_powered) { 188 sc->sc_flags.d_pulled_up = 1; 189 musbotg_pull_common(sc, 1); 190 } 191 } 192 193 static void 194 musbotg_pull_down(struct musbotg_softc *sc) 195 { 196 /* pulldown D+, if possible */ 197 198 if (sc->sc_flags.d_pulled_up) { 199 sc->sc_flags.d_pulled_up = 0; 200 musbotg_pull_common(sc, 0); 201 } 202 } 203 204 static void 205 musbotg_wakeup_peer(struct usb2_xfer *xfer) 206 { 207 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 208 uint8_t temp; 209 uint8_t use_polling; 210 211 if (!(sc->sc_flags.status_suspend)) { 212 return; 213 } 214 use_polling = mtx_owned(xfer->xroot->xfer_mtx) ? 1 : 0; 215 216 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 217 temp |= MUSB2_MASK_RESUME; 218 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 219 220 /* wait 8 milliseconds */ 221 if (use_polling) { 222 /* polling */ 223 DELAY(8000); 224 } else { 225 /* Wait for reset to complete. */ 226 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 227 } 228 229 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 230 temp &= ~MUSB2_MASK_RESUME; 231 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 232 } 233 234 static void 235 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 236 { 237 DPRINTFN(4, "addr=%d\n", addr); 238 addr &= 0x7F; 239 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 240 } 241 242 static uint8_t 243 musbotg_setup_rx(struct musbotg_td *td) 244 { 245 struct musbotg_softc *sc; 246 struct usb2_device_request req; 247 uint16_t count; 248 uint8_t csr; 249 250 /* get pointer to softc */ 251 sc = MUSBOTG_PC2SC(td->pc); 252 253 /* select endpoint 0 */ 254 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 255 256 /* read out FIFO status */ 257 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 258 259 DPRINTFN(4, "csr=0x%02x\n", csr); 260 261 /* 262 * NOTE: If DATAEND is set we should not call the 263 * callback, hence the status stage is not complete. 264 */ 265 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 266 /* wait for interrupt */ 267 goto not_complete; 268 } 269 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 270 /* clear SENTSTALL */ 271 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 272 /* get latest status */ 273 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 274 /* update EP0 state */ 275 sc->sc_ep0_busy = 0; 276 } 277 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 278 /* clear SETUPEND */ 279 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 280 MUSB2_MASK_CSR0L_SETUPEND_CLR); 281 /* get latest status */ 282 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 283 /* update EP0 state */ 284 sc->sc_ep0_busy = 0; 285 } 286 if (sc->sc_ep0_busy) { 287 /* abort any ongoing transfer */ 288 if (!td->did_stall) { 289 DPRINTFN(4, "stalling\n"); 290 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 291 MUSB2_MASK_CSR0L_SENDSTALL); 292 td->did_stall = 1; 293 } 294 goto not_complete; 295 } 296 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 297 goto not_complete; 298 } 299 /* get the packet byte count */ 300 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 301 302 /* verify data length */ 303 if (count != td->remainder) { 304 DPRINTFN(0, "Invalid SETUP packet " 305 "length, %d bytes\n", count); 306 goto not_complete; 307 } 308 if (count != sizeof(req)) { 309 DPRINTFN(0, "Unsupported SETUP packet " 310 "length, %d bytes\n", count); 311 goto not_complete; 312 } 313 /* receive data */ 314 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 315 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 316 317 /* copy data into real buffer */ 318 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 319 320 td->offset = sizeof(req); 321 td->remainder = 0; 322 323 /* set pending command */ 324 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 325 326 /* we need set stall or dataend after this */ 327 sc->sc_ep0_busy = 1; 328 329 /* sneak peek the set address */ 330 if ((req.bmRequestType == UT_WRITE_DEVICE) && 331 (req.bRequest == UR_SET_ADDRESS)) { 332 sc->sc_dv_addr = req.wValue[0] & 0x7F; 333 } else { 334 sc->sc_dv_addr = 0xFF; 335 } 336 return (0); /* complete */ 337 338 not_complete: 339 return (1); /* not complete */ 340 } 341 342 /* Control endpoint only data handling functions (RX/TX/SYNC) */ 343 344 static uint8_t 345 musbotg_setup_data_rx(struct musbotg_td *td) 346 { 347 struct usb2_page_search buf_res; 348 struct musbotg_softc *sc; 349 uint16_t count; 350 uint8_t csr; 351 uint8_t got_short; 352 353 /* get pointer to softc */ 354 sc = MUSBOTG_PC2SC(td->pc); 355 356 /* select endpoint 0 */ 357 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 358 359 /* check if a command is pending */ 360 if (sc->sc_ep0_cmd) { 361 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 362 sc->sc_ep0_cmd = 0; 363 } 364 /* read out FIFO status */ 365 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 366 367 DPRINTFN(4, "csr=0x%02x\n", csr); 368 369 got_short = 0; 370 371 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 372 MUSB2_MASK_CSR0L_SENTSTALL)) { 373 if (td->remainder == 0) { 374 /* 375 * We are actually complete and have 376 * received the next SETUP 377 */ 378 DPRINTFN(4, "faking complete\n"); 379 return (0); /* complete */ 380 } 381 /* 382 * USB Host Aborted the transfer. 383 */ 384 td->error = 1; 385 return (0); /* complete */ 386 } 387 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 388 return (1); /* not complete */ 389 } 390 /* get the packet byte count */ 391 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 392 393 /* verify the packet byte count */ 394 if (count != td->max_frame_size) { 395 if (count < td->max_frame_size) { 396 /* we have a short packet */ 397 td->short_pkt = 1; 398 got_short = 1; 399 } else { 400 /* invalid USB packet */ 401 td->error = 1; 402 return (0); /* we are complete */ 403 } 404 } 405 /* verify the packet byte count */ 406 if (count > td->remainder) { 407 /* invalid USB packet */ 408 td->error = 1; 409 return (0); /* we are complete */ 410 } 411 while (count > 0) { 412 uint32_t temp; 413 414 usb2_get_page(td->pc, td->offset, &buf_res); 415 416 /* get correct length */ 417 if (buf_res.length > count) { 418 buf_res.length = count; 419 } 420 /* check for unaligned memory address */ 421 if (USB_P2U(buf_res.buffer) & 3) { 422 423 temp = count & ~3; 424 425 if (temp) { 426 /* receive data 4 bytes at a time */ 427 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 428 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 429 temp / 4); 430 } 431 temp = count & 3; 432 if (temp) { 433 /* receive data 1 byte at a time */ 434 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 435 MUSB2_REG_EPFIFO(0), 436 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 437 } 438 usb2_copy_in(td->pc, td->offset, 439 sc->sc_bounce_buf, count); 440 441 /* update offset and remainder */ 442 td->offset += count; 443 td->remainder -= count; 444 break; 445 } 446 /* check if we can optimise */ 447 if (buf_res.length >= 4) { 448 449 /* receive data 4 bytes at a time */ 450 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 451 MUSB2_REG_EPFIFO(0), buf_res.buffer, 452 buf_res.length / 4); 453 454 temp = buf_res.length & ~3; 455 456 /* update counters */ 457 count -= temp; 458 td->offset += temp; 459 td->remainder -= temp; 460 continue; 461 } 462 /* receive data */ 463 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 464 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 465 466 /* update counters */ 467 count -= buf_res.length; 468 td->offset += buf_res.length; 469 td->remainder -= buf_res.length; 470 } 471 472 /* check if we are complete */ 473 if ((td->remainder == 0) || got_short) { 474 if (td->short_pkt) { 475 /* we are complete */ 476 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 477 return (0); 478 } 479 /* else need to receive a zero length packet */ 480 } 481 /* write command - need more data */ 482 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 483 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 484 return (1); /* not complete */ 485 } 486 487 static uint8_t 488 musbotg_setup_data_tx(struct musbotg_td *td) 489 { 490 struct usb2_page_search buf_res; 491 struct musbotg_softc *sc; 492 uint16_t count; 493 uint8_t csr; 494 495 /* get pointer to softc */ 496 sc = MUSBOTG_PC2SC(td->pc); 497 498 /* select endpoint 0 */ 499 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 500 501 /* check if a command is pending */ 502 if (sc->sc_ep0_cmd) { 503 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 504 sc->sc_ep0_cmd = 0; 505 } 506 /* read out FIFO status */ 507 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 508 509 DPRINTFN(4, "csr=0x%02x\n", csr); 510 511 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 512 MUSB2_MASK_CSR0L_SENTSTALL)) { 513 /* 514 * The current transfer was aborted 515 * by the USB Host 516 */ 517 td->error = 1; 518 return (0); /* complete */ 519 } 520 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 521 return (1); /* not complete */ 522 } 523 count = td->max_frame_size; 524 if (td->remainder < count) { 525 /* we have a short packet */ 526 td->short_pkt = 1; 527 count = td->remainder; 528 } 529 while (count > 0) { 530 uint32_t temp; 531 532 usb2_get_page(td->pc, td->offset, &buf_res); 533 534 /* get correct length */ 535 if (buf_res.length > count) { 536 buf_res.length = count; 537 } 538 /* check for unaligned memory address */ 539 if (USB_P2U(buf_res.buffer) & 3) { 540 541 usb2_copy_out(td->pc, td->offset, 542 sc->sc_bounce_buf, count); 543 544 temp = count & ~3; 545 546 if (temp) { 547 /* transmit data 4 bytes at a time */ 548 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 549 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 550 temp / 4); 551 } 552 temp = count & 3; 553 if (temp) { 554 /* receive data 1 byte at a time */ 555 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 556 MUSB2_REG_EPFIFO(0), 557 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 558 } 559 /* update offset and remainder */ 560 td->offset += count; 561 td->remainder -= count; 562 break; 563 } 564 /* check if we can optimise */ 565 if (buf_res.length >= 4) { 566 567 /* transmit data 4 bytes at a time */ 568 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 569 MUSB2_REG_EPFIFO(0), buf_res.buffer, 570 buf_res.length / 4); 571 572 temp = buf_res.length & ~3; 573 574 /* update counters */ 575 count -= temp; 576 td->offset += temp; 577 td->remainder -= temp; 578 continue; 579 } 580 /* transmit data */ 581 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 582 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 583 584 /* update counters */ 585 count -= buf_res.length; 586 td->offset += buf_res.length; 587 td->remainder -= buf_res.length; 588 } 589 590 /* check remainder */ 591 if (td->remainder == 0) { 592 if (td->short_pkt) { 593 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 594 return (0); /* complete */ 595 } 596 /* else we need to transmit a short packet */ 597 } 598 /* write command */ 599 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 600 MUSB2_MASK_CSR0L_TXPKTRDY); 601 602 return (1); /* not complete */ 603 } 604 605 static uint8_t 606 musbotg_setup_status(struct musbotg_td *td) 607 { 608 struct musbotg_softc *sc; 609 uint8_t csr; 610 611 /* get pointer to softc */ 612 sc = MUSBOTG_PC2SC(td->pc); 613 614 /* select endpoint 0 */ 615 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 616 617 if (sc->sc_ep0_busy) { 618 sc->sc_ep0_busy = 0; 619 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 620 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 621 sc->sc_ep0_cmd = 0; 622 } 623 /* read out FIFO status */ 624 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 625 626 DPRINTFN(4, "csr=0x%02x\n", csr); 627 628 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 629 /* wait for interrupt */ 630 return (1); /* not complete */ 631 } 632 if (sc->sc_dv_addr != 0xFF) { 633 /* write function address */ 634 musbotg_set_address(sc, sc->sc_dv_addr); 635 } 636 return (0); /* complete */ 637 } 638 639 static uint8_t 640 musbotg_data_rx(struct musbotg_td *td) 641 { 642 struct usb2_page_search buf_res; 643 struct musbotg_softc *sc; 644 uint16_t count; 645 uint8_t csr; 646 uint8_t to; 647 uint8_t got_short; 648 649 to = 8; /* don't loop forever! */ 650 got_short = 0; 651 652 /* get pointer to softc */ 653 sc = MUSBOTG_PC2SC(td->pc); 654 655 /* select endpoint */ 656 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 657 658 repeat: 659 /* read out FIFO status */ 660 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 661 662 DPRINTFN(4, "csr=0x%02x\n", csr); 663 664 /* clear overrun */ 665 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 666 /* make sure we don't clear "RXPKTRDY" */ 667 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 668 MUSB2_MASK_CSRL_RXPKTRDY); 669 } 670 /* check status */ 671 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 672 return (1); /* not complete */ 673 } 674 /* get the packet byte count */ 675 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 676 677 DPRINTFN(4, "count=0x%04x\n", count); 678 679 /* 680 * Check for short or invalid packet: 681 */ 682 if (count != td->max_frame_size) { 683 if (count < td->max_frame_size) { 684 /* we have a short packet */ 685 td->short_pkt = 1; 686 got_short = 1; 687 } else { 688 /* invalid USB packet */ 689 td->error = 1; 690 return (0); /* we are complete */ 691 } 692 } 693 /* verify the packet byte count */ 694 if (count > td->remainder) { 695 /* invalid USB packet */ 696 td->error = 1; 697 return (0); /* we are complete */ 698 } 699 while (count > 0) { 700 uint32_t temp; 701 702 usb2_get_page(td->pc, td->offset, &buf_res); 703 704 /* get correct length */ 705 if (buf_res.length > count) { 706 buf_res.length = count; 707 } 708 /* check for unaligned memory address */ 709 if (USB_P2U(buf_res.buffer) & 3) { 710 711 temp = count & ~3; 712 713 if (temp) { 714 /* receive data 4 bytes at a time */ 715 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 716 MUSB2_REG_EPFIFO(td->ep_no), sc->sc_bounce_buf, 717 temp / 4); 718 } 719 temp = count & 3; 720 if (temp) { 721 /* receive data 1 byte at a time */ 722 bus_space_read_multi_1(sc->sc_io_tag, 723 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 724 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 725 } 726 usb2_copy_in(td->pc, td->offset, 727 sc->sc_bounce_buf, count); 728 729 /* update offset and remainder */ 730 td->offset += count; 731 td->remainder -= count; 732 break; 733 } 734 /* check if we can optimise */ 735 if (buf_res.length >= 4) { 736 737 /* receive data 4 bytes at a time */ 738 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 739 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 740 buf_res.length / 4); 741 742 temp = buf_res.length & ~3; 743 744 /* update counters */ 745 count -= temp; 746 td->offset += temp; 747 td->remainder -= temp; 748 continue; 749 } 750 /* receive data */ 751 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 752 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 753 buf_res.length); 754 755 /* update counters */ 756 count -= buf_res.length; 757 td->offset += buf_res.length; 758 td->remainder -= buf_res.length; 759 } 760 761 /* clear status bits */ 762 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 763 764 /* check if we are complete */ 765 if ((td->remainder == 0) || got_short) { 766 if (td->short_pkt) { 767 /* we are complete */ 768 return (0); 769 } 770 /* else need to receive a zero length packet */ 771 } 772 if (--to) { 773 goto repeat; 774 } 775 return (1); /* not complete */ 776 } 777 778 static uint8_t 779 musbotg_data_tx(struct musbotg_td *td) 780 { 781 struct usb2_page_search buf_res; 782 struct musbotg_softc *sc; 783 uint16_t count; 784 uint8_t csr; 785 uint8_t to; 786 787 to = 8; /* don't loop forever! */ 788 789 /* get pointer to softc */ 790 sc = MUSBOTG_PC2SC(td->pc); 791 792 /* select endpoint */ 793 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no); 794 795 repeat: 796 797 /* read out FIFO status */ 798 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 799 800 DPRINTFN(4, "csr=0x%02x\n", csr); 801 802 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 803 MUSB2_MASK_CSRL_TXUNDERRUN)) { 804 /* clear status bits */ 805 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 806 } 807 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 808 return (1); /* not complete */ 809 } 810 /* check for short packet */ 811 count = td->max_frame_size; 812 if (td->remainder < count) { 813 /* we have a short packet */ 814 td->short_pkt = 1; 815 count = td->remainder; 816 } 817 while (count > 0) { 818 uint32_t temp; 819 820 usb2_get_page(td->pc, td->offset, &buf_res); 821 822 /* get correct length */ 823 if (buf_res.length > count) { 824 buf_res.length = count; 825 } 826 /* check for unaligned memory address */ 827 if (USB_P2U(buf_res.buffer) & 3) { 828 829 usb2_copy_out(td->pc, td->offset, 830 sc->sc_bounce_buf, count); 831 832 temp = count & ~3; 833 834 if (temp) { 835 /* transmit data 4 bytes at a time */ 836 bus_space_write_multi_4(sc->sc_io_tag, 837 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no), 838 sc->sc_bounce_buf, temp / 4); 839 } 840 temp = count & 3; 841 if (temp) { 842 /* receive data 1 byte at a time */ 843 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 844 MUSB2_REG_EPFIFO(td->ep_no), 845 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 846 } 847 /* update offset and remainder */ 848 td->offset += count; 849 td->remainder -= count; 850 break; 851 } 852 /* check if we can optimise */ 853 if (buf_res.length >= 4) { 854 855 /* transmit data 4 bytes at a time */ 856 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 857 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 858 buf_res.length / 4); 859 860 temp = buf_res.length & ~3; 861 862 /* update counters */ 863 count -= temp; 864 td->offset += temp; 865 td->remainder -= temp; 866 continue; 867 } 868 /* transmit data */ 869 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 870 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer, 871 buf_res.length); 872 873 /* update counters */ 874 count -= buf_res.length; 875 td->offset += buf_res.length; 876 td->remainder -= buf_res.length; 877 } 878 879 /* write command */ 880 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 881 MUSB2_MASK_CSRL_TXPKTRDY); 882 883 /* check remainder */ 884 if (td->remainder == 0) { 885 if (td->short_pkt) { 886 return (0); /* complete */ 887 } 888 /* else we need to transmit a short packet */ 889 } 890 if (--to) { 891 goto repeat; 892 } 893 return (1); /* not complete */ 894 } 895 896 static uint8_t 897 musbotg_xfer_do_fifo(struct usb2_xfer *xfer) 898 { 899 struct musbotg_softc *sc; 900 struct musbotg_td *td; 901 902 DPRINTFN(8, "\n"); 903 904 td = xfer->td_transfer_cache; 905 while (1) { 906 if ((td->func) (td)) { 907 /* operation in progress */ 908 break; 909 } 910 if (((void *)td) == xfer->td_transfer_last) { 911 goto done; 912 } 913 if (td->error) { 914 goto done; 915 } else if (td->remainder > 0) { 916 /* 917 * We had a short transfer. If there is no alternate 918 * next, stop processing ! 919 */ 920 if (!td->alt_next) { 921 goto done; 922 } 923 } 924 /* 925 * Fetch the next transfer descriptor and transfer 926 * some flags to the next transfer descriptor 927 */ 928 td = td->obj_next; 929 xfer->td_transfer_cache = td; 930 } 931 return (1); /* not complete */ 932 933 done: 934 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 935 936 /* compute all actual lengths */ 937 938 musbotg_standard_done(xfer); 939 940 return (0); /* complete */ 941 } 942 943 static void 944 musbotg_interrupt_poll(struct musbotg_softc *sc) 945 { 946 struct usb2_xfer *xfer; 947 948 repeat: 949 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 950 if (!musbotg_xfer_do_fifo(xfer)) { 951 /* queue has been modified */ 952 goto repeat; 953 } 954 } 955 } 956 957 void 958 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 959 { 960 DPRINTFN(4, "vbus = %u\n", is_on); 961 962 USB_BUS_LOCK(&sc->sc_bus); 963 if (is_on) { 964 if (!sc->sc_flags.status_vbus) { 965 sc->sc_flags.status_vbus = 1; 966 967 /* complete root HUB interrupt endpoint */ 968 969 usb2_sw_transfer(&sc->sc_root_intr, 970 &musbotg_root_intr_done); 971 } 972 } else { 973 if (sc->sc_flags.status_vbus) { 974 sc->sc_flags.status_vbus = 0; 975 sc->sc_flags.status_bus_reset = 0; 976 sc->sc_flags.status_suspend = 0; 977 sc->sc_flags.change_suspend = 0; 978 sc->sc_flags.change_connect = 1; 979 980 /* complete root HUB interrupt endpoint */ 981 982 usb2_sw_transfer(&sc->sc_root_intr, 983 &musbotg_root_intr_done); 984 } 985 } 986 987 USB_BUS_UNLOCK(&sc->sc_bus); 988 } 989 990 void 991 musbotg_interrupt(struct musbotg_softc *sc) 992 { 993 uint16_t rx_status; 994 uint16_t tx_status; 995 uint8_t usb_status; 996 uint8_t temp; 997 uint8_t to = 2; 998 999 USB_BUS_LOCK(&sc->sc_bus); 1000 1001 repeat: 1002 1003 /* read all interrupt registers */ 1004 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 1005 1006 /* read all FIFO interrupts */ 1007 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 1008 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 1009 1010 /* check for any bus state change interrupts */ 1011 1012 if (usb_status & (MUSB2_MASK_IRESET | 1013 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP)) { 1014 1015 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 1016 1017 if (usb_status & MUSB2_MASK_IRESET) { 1018 1019 /* set correct state */ 1020 sc->sc_flags.status_bus_reset = 1; 1021 sc->sc_flags.status_suspend = 0; 1022 sc->sc_flags.change_suspend = 0; 1023 sc->sc_flags.change_connect = 1; 1024 1025 /* determine line speed */ 1026 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 1027 if (temp & MUSB2_MASK_HSMODE) 1028 sc->sc_flags.status_high_speed = 1; 1029 else 1030 sc->sc_flags.status_high_speed = 0; 1031 1032 /* 1033 * After reset all interrupts are on and we need to 1034 * turn them off! 1035 */ 1036 temp = MUSB2_MASK_IRESET; 1037 /* disable resume interrupt */ 1038 temp &= ~MUSB2_MASK_IRESUME; 1039 /* enable suspend interrupt */ 1040 temp |= MUSB2_MASK_ISUSP; 1041 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1042 /* disable TX and RX interrupts */ 1043 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1044 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1045 } 1046 /* 1047 * If RXRSM and RXSUSP is set at the same time we interpret 1048 * that like RESUME. Resume is set when there is at least 3 1049 * milliseconds of inactivity on the USB BUS. 1050 */ 1051 if (usb_status & MUSB2_MASK_IRESUME) { 1052 if (sc->sc_flags.status_suspend) { 1053 sc->sc_flags.status_suspend = 0; 1054 sc->sc_flags.change_suspend = 1; 1055 1056 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1057 /* disable resume interrupt */ 1058 temp &= ~MUSB2_MASK_IRESUME; 1059 /* enable suspend interrupt */ 1060 temp |= MUSB2_MASK_ISUSP; 1061 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1062 } 1063 } else if (usb_status & MUSB2_MASK_ISUSP) { 1064 if (!sc->sc_flags.status_suspend) { 1065 sc->sc_flags.status_suspend = 1; 1066 sc->sc_flags.change_suspend = 1; 1067 1068 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 1069 /* disable suspend interrupt */ 1070 temp &= ~MUSB2_MASK_ISUSP; 1071 /* enable resume interrupt */ 1072 temp |= MUSB2_MASK_IRESUME; 1073 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 1074 } 1075 } 1076 /* complete root HUB interrupt endpoint */ 1077 1078 usb2_sw_transfer(&sc->sc_root_intr, 1079 &musbotg_root_intr_done); 1080 } 1081 /* check for any endpoint interrupts */ 1082 1083 if (rx_status || tx_status) { 1084 DPRINTFN(4, "real endpoint interrupt " 1085 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 1086 } 1087 /* poll one time regardless of FIFO status */ 1088 1089 musbotg_interrupt_poll(sc); 1090 1091 if (--to) 1092 goto repeat; 1093 1094 USB_BUS_UNLOCK(&sc->sc_bus); 1095 } 1096 1097 static void 1098 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 1099 { 1100 struct musbotg_td *td; 1101 1102 /* get current Transfer Descriptor */ 1103 td = temp->td_next; 1104 temp->td = td; 1105 1106 /* prepare for next TD */ 1107 temp->td_next = td->obj_next; 1108 1109 /* fill out the Transfer Descriptor */ 1110 td->func = temp->func; 1111 td->pc = temp->pc; 1112 td->offset = temp->offset; 1113 td->remainder = temp->len; 1114 td->error = 0; 1115 td->did_stall = 0; 1116 td->short_pkt = temp->short_pkt; 1117 td->alt_next = temp->setup_alt_next; 1118 } 1119 1120 static void 1121 musbotg_setup_standard_chain(struct usb2_xfer *xfer) 1122 { 1123 struct musbotg_std_temp temp; 1124 struct musbotg_softc *sc; 1125 struct musbotg_td *td; 1126 uint32_t x; 1127 uint8_t ep_no; 1128 1129 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1130 xfer->address, UE_GET_ADDR(xfer->endpoint), 1131 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1132 1133 temp.max_frame_size = xfer->max_frame_size; 1134 1135 td = xfer->td_start[0]; 1136 xfer->td_transfer_first = td; 1137 xfer->td_transfer_cache = td; 1138 1139 /* setup temp */ 1140 1141 temp.td = NULL; 1142 temp.td_next = xfer->td_start[0]; 1143 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1144 temp.offset = 0; 1145 1146 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1147 ep_no = (xfer->endpoint & UE_ADDR); 1148 1149 /* check if we should prepend a setup message */ 1150 1151 if (xfer->flags_int.control_xfr) { 1152 if (xfer->flags_int.control_hdr) { 1153 1154 temp.func = &musbotg_setup_rx; 1155 temp.len = xfer->frlengths[0]; 1156 temp.pc = xfer->frbuffers + 0; 1157 temp.short_pkt = temp.len ? 1 : 0; 1158 1159 musbotg_setup_standard_chain_sub(&temp); 1160 } 1161 x = 1; 1162 } else { 1163 x = 0; 1164 } 1165 1166 if (x != xfer->nframes) { 1167 if (xfer->endpoint & UE_DIR_IN) { 1168 if (xfer->flags_int.control_xfr) 1169 temp.func = &musbotg_setup_data_tx; 1170 else 1171 temp.func = &musbotg_data_tx; 1172 } else { 1173 if (xfer->flags_int.control_xfr) 1174 temp.func = &musbotg_setup_data_rx; 1175 else 1176 temp.func = &musbotg_data_rx; 1177 } 1178 1179 /* setup "pc" pointer */ 1180 temp.pc = xfer->frbuffers + x; 1181 } 1182 while (x != xfer->nframes) { 1183 1184 /* DATA0 / DATA1 message */ 1185 1186 temp.len = xfer->frlengths[x]; 1187 1188 x++; 1189 1190 if (x == xfer->nframes) { 1191 temp.setup_alt_next = 0; 1192 } 1193 if (temp.len == 0) { 1194 1195 /* make sure that we send an USB packet */ 1196 1197 temp.short_pkt = 0; 1198 1199 } else { 1200 1201 /* regular data transfer */ 1202 1203 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1204 } 1205 1206 musbotg_setup_standard_chain_sub(&temp); 1207 1208 if (xfer->flags_int.isochronous_xfr) { 1209 temp.offset += temp.len; 1210 } else { 1211 /* get next Page Cache pointer */ 1212 temp.pc = xfer->frbuffers + x; 1213 } 1214 } 1215 1216 /* always setup a valid "pc" pointer for status and sync */ 1217 temp.pc = xfer->frbuffers + 0; 1218 1219 /* check if we should append a status stage */ 1220 1221 if (xfer->flags_int.control_xfr && 1222 !xfer->flags_int.control_act) { 1223 1224 /* 1225 * Send a DATA1 message and invert the current 1226 * endpoint direction. 1227 */ 1228 temp.func = &musbotg_setup_status; 1229 temp.len = 0; 1230 temp.short_pkt = 0; 1231 1232 musbotg_setup_standard_chain_sub(&temp); 1233 } 1234 /* must have at least one frame! */ 1235 td = temp.td; 1236 xfer->td_transfer_last = td; 1237 } 1238 1239 static void 1240 musbotg_timeout(void *arg) 1241 { 1242 struct usb2_xfer *xfer = arg; 1243 1244 DPRINTFN(1, "xfer=%p\n", xfer); 1245 1246 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1247 1248 /* transfer is transferred */ 1249 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 1250 } 1251 1252 static void 1253 musbotg_ep_int_set(struct usb2_xfer *xfer, uint8_t on) 1254 { 1255 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1256 uint16_t temp; 1257 uint8_t ep_no = xfer->endpoint & UE_ADDR; 1258 1259 /* 1260 * Only enable the endpoint interrupt when we are 1261 * actually waiting for data, hence we are dealing 1262 * with level triggered interrupts ! 1263 */ 1264 if (ep_no == 0) { 1265 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1266 if (on) 1267 temp |= MUSB2_MASK_EPINT(0); 1268 else 1269 temp &= ~MUSB2_MASK_EPINT(0); 1270 1271 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1272 } else { 1273 if (USB_GET_DATA_ISREAD(xfer)) { 1274 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 1275 if (on) 1276 temp |= MUSB2_MASK_EPINT(ep_no); 1277 else 1278 temp &= ~MUSB2_MASK_EPINT(ep_no); 1279 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 1280 1281 } else { 1282 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 1283 if (on) 1284 temp |= MUSB2_MASK_EPINT(ep_no); 1285 else 1286 temp &= ~MUSB2_MASK_EPINT(ep_no); 1287 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 1288 } 1289 } 1290 } 1291 1292 static void 1293 musbotg_start_standard_chain(struct usb2_xfer *xfer) 1294 { 1295 DPRINTFN(8, "\n"); 1296 1297 /* poll one time */ 1298 if (musbotg_xfer_do_fifo(xfer)) { 1299 1300 musbotg_ep_int_set(xfer, 1); 1301 1302 DPRINTFN(14, "enabled interrupts on endpoint\n"); 1303 1304 /* put transfer on interrupt queue */ 1305 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1306 1307 /* start timeout, if any */ 1308 if (xfer->timeout != 0) { 1309 usb2_transfer_timeout_ms(xfer, 1310 &musbotg_timeout, xfer->timeout); 1311 } 1312 } 1313 } 1314 1315 static void 1316 musbotg_root_intr_done(struct usb2_xfer *xfer, 1317 struct usb2_sw_transfer *std) 1318 { 1319 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 1320 1321 DPRINTFN(8, "\n"); 1322 1323 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1324 1325 if (std->state != USB_SW_TR_PRE_DATA) { 1326 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1327 /* transfer transferred */ 1328 musbotg_device_done(xfer, std->err); 1329 } 1330 goto done; 1331 } 1332 /* setup buffer */ 1333 std->ptr = sc->sc_hub_idata; 1334 std->len = sizeof(sc->sc_hub_idata); 1335 1336 /* set port bit */ 1337 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1338 1339 done: 1340 return; 1341 } 1342 1343 static usb2_error_t 1344 musbotg_standard_done_sub(struct usb2_xfer *xfer) 1345 { 1346 struct musbotg_td *td; 1347 uint32_t len; 1348 uint8_t error; 1349 1350 DPRINTFN(8, "\n"); 1351 1352 td = xfer->td_transfer_cache; 1353 1354 do { 1355 len = td->remainder; 1356 1357 if (xfer->aframes != xfer->nframes) { 1358 /* 1359 * Verify the length and subtract 1360 * the remainder from "frlengths[]": 1361 */ 1362 if (len > xfer->frlengths[xfer->aframes]) { 1363 td->error = 1; 1364 } else { 1365 xfer->frlengths[xfer->aframes] -= len; 1366 } 1367 } 1368 /* Check for transfer error */ 1369 if (td->error) { 1370 /* the transfer is finished */ 1371 error = 1; 1372 td = NULL; 1373 break; 1374 } 1375 /* Check for short transfer */ 1376 if (len > 0) { 1377 if (xfer->flags_int.short_frames_ok) { 1378 /* follow alt next */ 1379 if (td->alt_next) { 1380 td = td->obj_next; 1381 } else { 1382 td = NULL; 1383 } 1384 } else { 1385 /* the transfer is finished */ 1386 td = NULL; 1387 } 1388 error = 0; 1389 break; 1390 } 1391 td = td->obj_next; 1392 1393 /* this USB frame is complete */ 1394 error = 0; 1395 break; 1396 1397 } while (0); 1398 1399 /* update transfer cache */ 1400 1401 xfer->td_transfer_cache = td; 1402 1403 return (error ? 1404 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1405 } 1406 1407 static void 1408 musbotg_standard_done(struct usb2_xfer *xfer) 1409 { 1410 usb2_error_t err = 0; 1411 1412 DPRINTFN(12, "xfer=%p pipe=%p transfer done\n", 1413 xfer, xfer->pipe); 1414 1415 /* reset scanner */ 1416 1417 xfer->td_transfer_cache = xfer->td_transfer_first; 1418 1419 if (xfer->flags_int.control_xfr) { 1420 1421 if (xfer->flags_int.control_hdr) { 1422 1423 err = musbotg_standard_done_sub(xfer); 1424 } 1425 xfer->aframes = 1; 1426 1427 if (xfer->td_transfer_cache == NULL) { 1428 goto done; 1429 } 1430 } 1431 while (xfer->aframes != xfer->nframes) { 1432 1433 err = musbotg_standard_done_sub(xfer); 1434 xfer->aframes++; 1435 1436 if (xfer->td_transfer_cache == NULL) { 1437 goto done; 1438 } 1439 } 1440 1441 if (xfer->flags_int.control_xfr && 1442 !xfer->flags_int.control_act) { 1443 1444 err = musbotg_standard_done_sub(xfer); 1445 } 1446 done: 1447 musbotg_device_done(xfer, err); 1448 } 1449 1450 /*------------------------------------------------------------------------* 1451 * musbotg_device_done 1452 * 1453 * NOTE: this function can be called more than one time on the 1454 * same USB transfer! 1455 *------------------------------------------------------------------------*/ 1456 static void 1457 musbotg_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1458 { 1459 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1460 1461 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1462 xfer, xfer->pipe, error); 1463 1464 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1465 1466 musbotg_ep_int_set(xfer, 0); 1467 1468 DPRINTFN(14, "disabled interrupts on endpoint\n"); 1469 } 1470 /* dequeue transfer and start next transfer */ 1471 usb2_transfer_done(xfer, error); 1472 } 1473 1474 static void 1475 musbotg_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1476 struct usb2_pipe *pipe) 1477 { 1478 struct musbotg_softc *sc; 1479 uint8_t ep_no; 1480 1481 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1482 1483 DPRINTFN(4, "pipe=%p\n", pipe); 1484 1485 if (xfer) { 1486 /* cancel any ongoing transfers */ 1487 musbotg_device_done(xfer, USB_ERR_STALLED); 1488 } 1489 /* set FORCESTALL */ 1490 sc = MUSBOTG_BUS2SC(udev->bus); 1491 1492 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1493 1494 /* select endpoint */ 1495 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1496 1497 if (pipe->edesc->bEndpointAddress & UE_DIR_IN) { 1498 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1499 MUSB2_MASK_CSRL_TXSENDSTALL); 1500 } else { 1501 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1502 MUSB2_MASK_CSRL_RXSENDSTALL); 1503 } 1504 } 1505 1506 static void 1507 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 1508 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1509 { 1510 uint16_t mps; 1511 uint16_t temp; 1512 uint8_t csr; 1513 1514 if (ep_type == UE_CONTROL) { 1515 /* clearing stall is not needed */ 1516 return; 1517 } 1518 /* select endpoint */ 1519 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 1520 1521 /* compute max frame size */ 1522 mps = wMaxPacket & 0x7FF; 1523 switch ((wMaxPacket >> 11) & 3) { 1524 case 1: 1525 mps *= 2; 1526 break; 1527 case 2: 1528 mps *= 3; 1529 break; 1530 default: 1531 break; 1532 } 1533 1534 if (ep_dir == UE_DIR_IN) { 1535 1536 temp = 0; 1537 1538 /* Configure endpoint */ 1539 switch (ep_type) { 1540 case UE_INTERRUPT: 1541 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1542 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1543 MUSB2_MASK_CSRH_TXMODE | temp); 1544 break; 1545 case UE_ISOCHRONOUS: 1546 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1547 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1548 MUSB2_MASK_CSRH_TXMODE | 1549 MUSB2_MASK_CSRH_TXISO | temp); 1550 break; 1551 case UE_BULK: 1552 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket); 1553 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 1554 MUSB2_MASK_CSRH_TXMODE | temp); 1555 break; 1556 default: 1557 break; 1558 } 1559 1560 /* Need to flush twice in case of double bufring */ 1561 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1562 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1563 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1564 MUSB2_MASK_CSRL_TXFFLUSH); 1565 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1566 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1567 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1568 MUSB2_MASK_CSRL_TXFFLUSH); 1569 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1570 } 1571 } 1572 /* reset data toggle */ 1573 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1574 MUSB2_MASK_CSRL_TXDT_CLR); 1575 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1576 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1577 1578 /* set double/single buffering */ 1579 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 1580 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1581 max_in_frame_size / 2)) { 1582 /* double buffer */ 1583 temp &= ~(1 << ep_no); 1584 } else { 1585 /* single buffer */ 1586 temp |= (1 << ep_no); 1587 } 1588 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 1589 1590 /* clear sent stall */ 1591 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 1592 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1593 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1594 } 1595 } else { 1596 1597 temp = 0; 1598 1599 /* Configure endpoint */ 1600 switch (ep_type) { 1601 case UE_INTERRUPT: 1602 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1603 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1604 MUSB2_MASK_CSRH_RXNYET | temp); 1605 break; 1606 case UE_ISOCHRONOUS: 1607 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1608 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 1609 MUSB2_MASK_CSRH_RXNYET | 1610 MUSB2_MASK_CSRH_RXISO | temp); 1611 break; 1612 case UE_BULK: 1613 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket); 1614 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 1615 break; 1616 default: 1617 break; 1618 } 1619 1620 /* Need to flush twice in case of double bufring */ 1621 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1622 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1623 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1624 MUSB2_MASK_CSRL_RXFFLUSH); 1625 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1626 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 1627 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1628 MUSB2_MASK_CSRL_RXFFLUSH); 1629 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1630 } 1631 } 1632 /* reset data toggle */ 1633 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1634 MUSB2_MASK_CSRL_RXDT_CLR); 1635 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1636 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1637 1638 /* set double/single buffering */ 1639 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 1640 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 1641 max_out_frame_size / 2)) { 1642 /* double buffer */ 1643 temp &= ~(1 << ep_no); 1644 } else { 1645 /* single buffer */ 1646 temp |= (1 << ep_no); 1647 } 1648 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 1649 1650 /* clear sent stall */ 1651 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 1652 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1653 } 1654 } 1655 } 1656 1657 static void 1658 musbotg_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1659 { 1660 struct musbotg_softc *sc; 1661 struct usb2_endpoint_descriptor *ed; 1662 1663 DPRINTFN(4, "pipe=%p\n", pipe); 1664 1665 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1666 1667 /* check mode */ 1668 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1669 /* not supported */ 1670 return; 1671 } 1672 /* get softc */ 1673 sc = MUSBOTG_BUS2SC(udev->bus); 1674 1675 /* get endpoint descriptor */ 1676 ed = pipe->edesc; 1677 1678 /* reset endpoint */ 1679 musbotg_clear_stall_sub(sc, 1680 UGETW(ed->wMaxPacketSize), 1681 (ed->bEndpointAddress & UE_ADDR), 1682 (ed->bmAttributes & UE_XFERTYPE), 1683 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1684 } 1685 1686 usb2_error_t 1687 musbotg_init(struct musbotg_softc *sc) 1688 { 1689 struct usb2_hw_ep_profile *pf; 1690 uint8_t nrx; 1691 uint8_t ntx; 1692 uint8_t temp; 1693 uint8_t fsize; 1694 uint8_t frx; 1695 uint8_t ftx; 1696 1697 DPRINTFN(1, "start\n"); 1698 1699 /* set up the bus structure */ 1700 sc->sc_bus.usbrev = USB_REV_2_0; 1701 sc->sc_bus.methods = &musbotg_bus_methods; 1702 1703 USB_BUS_LOCK(&sc->sc_bus); 1704 1705 /* turn on clocks */ 1706 1707 if (sc->sc_clocks_on) { 1708 (sc->sc_clocks_on) (sc->sc_clocks_arg); 1709 } 1710 /* wait a little for things to stabilise */ 1711 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1712 1713 /* disable all interrupts */ 1714 1715 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1716 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1717 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1718 1719 /* disable pullup */ 1720 1721 musbotg_pull_common(sc, 0); 1722 1723 /* wait a little bit (10ms) */ 1724 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1725 1726 /* disable double packet buffering */ 1727 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 1728 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 1729 1730 /* enable HighSpeed and ISO Update flags */ 1731 1732 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 1733 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 1734 1735 /* clear Session bit, if set */ 1736 1737 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 1738 temp &= ~MUSB2_MASK_SESS; 1739 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 1740 1741 DPRINTF("DEVCTL=0x%02x\n", temp); 1742 1743 /* disable testmode */ 1744 1745 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 1746 1747 /* set default value */ 1748 1749 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 1750 1751 /* select endpoint index 0 */ 1752 1753 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1754 1755 /* read out number of endpoints */ 1756 1757 nrx = 1758 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 1759 1760 ntx = 1761 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 1762 1763 /* these numbers exclude the control endpoint */ 1764 1765 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 1766 1767 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 1768 if (sc->sc_ep_max == 0) { 1769 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 1770 } 1771 /* read out configuration data */ 1772 1773 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 1774 1775 DPRINTFN(2, "Config Data: 0x%02x\n", 1776 sc->sc_conf_data); 1777 1778 DPRINTFN(2, "HW version: 0x%04x\n", 1779 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 1780 1781 /* initialise endpoint profiles */ 1782 1783 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 1784 pf = sc->sc_hw_ep_profile + temp; 1785 1786 /* select endpoint */ 1787 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 1788 1789 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 1790 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;; 1791 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 1792 1793 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u\n", 1794 temp, pf->max_in_frame_size, 1795 pf->max_out_frame_size); 1796 1797 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 1798 pf->max_in_frame_size = 1 << ftx; 1799 pf->max_out_frame_size = 1 << frx; 1800 pf->is_simplex = 0; /* duplex */ 1801 pf->support_multi_buffer = 1; 1802 pf->support_bulk = 1; 1803 pf->support_interrupt = 1; 1804 pf->support_isochronous = 1; 1805 pf->support_in = 1; 1806 pf->support_out = 1; 1807 } else if (frx && (temp <= nrx)) { 1808 pf->max_out_frame_size = 1 << frx; 1809 pf->is_simplex = 1; /* simplex */ 1810 pf->support_multi_buffer = 1; 1811 pf->support_bulk = 1; 1812 pf->support_interrupt = 1; 1813 pf->support_isochronous = 1; 1814 pf->support_out = 1; 1815 } else if (ftx && (temp <= ntx)) { 1816 pf->max_in_frame_size = 1 << ftx; 1817 pf->is_simplex = 1; /* simplex */ 1818 pf->support_multi_buffer = 1; 1819 pf->support_bulk = 1; 1820 pf->support_interrupt = 1; 1821 pf->support_isochronous = 1; 1822 pf->support_in = 1; 1823 } 1824 } 1825 1826 /* turn on default interrupts */ 1827 1828 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 1829 MUSB2_MASK_IRESET); 1830 1831 musbotg_clocks_off(sc); 1832 1833 USB_BUS_UNLOCK(&sc->sc_bus); 1834 1835 /* catch any lost interrupts */ 1836 1837 musbotg_do_poll(&sc->sc_bus); 1838 1839 return (0); /* success */ 1840 } 1841 1842 void 1843 musbotg_uninit(struct musbotg_softc *sc) 1844 { 1845 USB_BUS_LOCK(&sc->sc_bus); 1846 1847 /* disable all interrupts */ 1848 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 1849 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 1850 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 1851 1852 sc->sc_flags.port_powered = 0; 1853 sc->sc_flags.status_vbus = 0; 1854 sc->sc_flags.status_bus_reset = 0; 1855 sc->sc_flags.status_suspend = 0; 1856 sc->sc_flags.change_suspend = 0; 1857 sc->sc_flags.change_connect = 1; 1858 1859 musbotg_pull_down(sc); 1860 musbotg_clocks_off(sc); 1861 USB_BUS_UNLOCK(&sc->sc_bus); 1862 } 1863 1864 void 1865 musbotg_suspend(struct musbotg_softc *sc) 1866 { 1867 return; 1868 } 1869 1870 void 1871 musbotg_resume(struct musbotg_softc *sc) 1872 { 1873 return; 1874 } 1875 1876 static void 1877 musbotg_do_poll(struct usb2_bus *bus) 1878 { 1879 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 1880 1881 USB_BUS_LOCK(&sc->sc_bus); 1882 musbotg_interrupt_poll(sc); 1883 musbotg_root_ctrl_poll(sc); 1884 USB_BUS_UNLOCK(&sc->sc_bus); 1885 } 1886 1887 /*------------------------------------------------------------------------* 1888 * musbotg bulk support 1889 *------------------------------------------------------------------------*/ 1890 static void 1891 musbotg_device_bulk_open(struct usb2_xfer *xfer) 1892 { 1893 return; 1894 } 1895 1896 static void 1897 musbotg_device_bulk_close(struct usb2_xfer *xfer) 1898 { 1899 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1900 } 1901 1902 static void 1903 musbotg_device_bulk_enter(struct usb2_xfer *xfer) 1904 { 1905 return; 1906 } 1907 1908 static void 1909 musbotg_device_bulk_start(struct usb2_xfer *xfer) 1910 { 1911 /* setup TDs */ 1912 musbotg_setup_standard_chain(xfer); 1913 musbotg_start_standard_chain(xfer); 1914 } 1915 1916 struct usb2_pipe_methods musbotg_device_bulk_methods = 1917 { 1918 .open = musbotg_device_bulk_open, 1919 .close = musbotg_device_bulk_close, 1920 .enter = musbotg_device_bulk_enter, 1921 .start = musbotg_device_bulk_start, 1922 .enter_is_cancelable = 1, 1923 .start_is_cancelable = 1, 1924 }; 1925 1926 /*------------------------------------------------------------------------* 1927 * musbotg control support 1928 *------------------------------------------------------------------------*/ 1929 static void 1930 musbotg_device_ctrl_open(struct usb2_xfer *xfer) 1931 { 1932 return; 1933 } 1934 1935 static void 1936 musbotg_device_ctrl_close(struct usb2_xfer *xfer) 1937 { 1938 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1939 } 1940 1941 static void 1942 musbotg_device_ctrl_enter(struct usb2_xfer *xfer) 1943 { 1944 return; 1945 } 1946 1947 static void 1948 musbotg_device_ctrl_start(struct usb2_xfer *xfer) 1949 { 1950 /* setup TDs */ 1951 musbotg_setup_standard_chain(xfer); 1952 musbotg_start_standard_chain(xfer); 1953 } 1954 1955 struct usb2_pipe_methods musbotg_device_ctrl_methods = 1956 { 1957 .open = musbotg_device_ctrl_open, 1958 .close = musbotg_device_ctrl_close, 1959 .enter = musbotg_device_ctrl_enter, 1960 .start = musbotg_device_ctrl_start, 1961 .enter_is_cancelable = 1, 1962 .start_is_cancelable = 1, 1963 }; 1964 1965 /*------------------------------------------------------------------------* 1966 * musbotg interrupt support 1967 *------------------------------------------------------------------------*/ 1968 static void 1969 musbotg_device_intr_open(struct usb2_xfer *xfer) 1970 { 1971 return; 1972 } 1973 1974 static void 1975 musbotg_device_intr_close(struct usb2_xfer *xfer) 1976 { 1977 musbotg_device_done(xfer, USB_ERR_CANCELLED); 1978 } 1979 1980 static void 1981 musbotg_device_intr_enter(struct usb2_xfer *xfer) 1982 { 1983 return; 1984 } 1985 1986 static void 1987 musbotg_device_intr_start(struct usb2_xfer *xfer) 1988 { 1989 /* setup TDs */ 1990 musbotg_setup_standard_chain(xfer); 1991 musbotg_start_standard_chain(xfer); 1992 } 1993 1994 struct usb2_pipe_methods musbotg_device_intr_methods = 1995 { 1996 .open = musbotg_device_intr_open, 1997 .close = musbotg_device_intr_close, 1998 .enter = musbotg_device_intr_enter, 1999 .start = musbotg_device_intr_start, 2000 .enter_is_cancelable = 1, 2001 .start_is_cancelable = 1, 2002 }; 2003 2004 /*------------------------------------------------------------------------* 2005 * musbotg full speed isochronous support 2006 *------------------------------------------------------------------------*/ 2007 static void 2008 musbotg_device_isoc_open(struct usb2_xfer *xfer) 2009 { 2010 return; 2011 } 2012 2013 static void 2014 musbotg_device_isoc_close(struct usb2_xfer *xfer) 2015 { 2016 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2017 } 2018 2019 static void 2020 musbotg_device_isoc_enter(struct usb2_xfer *xfer) 2021 { 2022 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2023 uint32_t temp; 2024 uint32_t nframes; 2025 uint32_t fs_frames; 2026 2027 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 2028 xfer, xfer->pipe->isoc_next, xfer->nframes); 2029 2030 /* get the current frame index */ 2031 2032 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 2033 2034 /* 2035 * check if the frame index is within the window where the frames 2036 * will be inserted 2037 */ 2038 temp = (nframes - xfer->pipe->isoc_next) & MUSB2_MASK_FRAME; 2039 2040 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2041 fs_frames = (xfer->nframes + 7) / 8; 2042 } else { 2043 fs_frames = xfer->nframes; 2044 } 2045 2046 if ((xfer->pipe->is_synced == 0) || 2047 (temp < fs_frames)) { 2048 /* 2049 * If there is data underflow or the pipe queue is 2050 * empty we schedule the transfer a few frames ahead 2051 * of the current frame position. Else two isochronous 2052 * transfers might overlap. 2053 */ 2054 xfer->pipe->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 2055 xfer->pipe->is_synced = 1; 2056 DPRINTFN(2, "start next=%d\n", xfer->pipe->isoc_next); 2057 } 2058 /* 2059 * compute how many milliseconds the insertion is ahead of the 2060 * current frame position: 2061 */ 2062 temp = (xfer->pipe->isoc_next - nframes) & MUSB2_MASK_FRAME; 2063 2064 /* 2065 * pre-compute when the isochronous transfer will be finished: 2066 */ 2067 xfer->isoc_time_complete = 2068 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 2069 fs_frames; 2070 2071 /* compute frame number for next insertion */ 2072 xfer->pipe->isoc_next += fs_frames; 2073 2074 /* setup TDs */ 2075 musbotg_setup_standard_chain(xfer); 2076 } 2077 2078 static void 2079 musbotg_device_isoc_start(struct usb2_xfer *xfer) 2080 { 2081 /* start TD chain */ 2082 musbotg_start_standard_chain(xfer); 2083 } 2084 2085 struct usb2_pipe_methods musbotg_device_isoc_methods = 2086 { 2087 .open = musbotg_device_isoc_open, 2088 .close = musbotg_device_isoc_close, 2089 .enter = musbotg_device_isoc_enter, 2090 .start = musbotg_device_isoc_start, 2091 .enter_is_cancelable = 1, 2092 .start_is_cancelable = 1, 2093 }; 2094 2095 /*------------------------------------------------------------------------* 2096 * musbotg root control support 2097 *------------------------------------------------------------------------* 2098 * simulate a hardware HUB by handling 2099 * all the necessary requests 2100 *------------------------------------------------------------------------*/ 2101 static void 2102 musbotg_root_ctrl_open(struct usb2_xfer *xfer) 2103 { 2104 return; 2105 } 2106 2107 static void 2108 musbotg_root_ctrl_close(struct usb2_xfer *xfer) 2109 { 2110 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2111 2112 if (sc->sc_root_ctrl.xfer == xfer) { 2113 sc->sc_root_ctrl.xfer = NULL; 2114 } 2115 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2116 } 2117 2118 /* 2119 * USB descriptors for the virtual Root HUB: 2120 */ 2121 2122 static const struct usb2_device_descriptor musbotg_devd = { 2123 .bLength = sizeof(struct usb2_device_descriptor), 2124 .bDescriptorType = UDESC_DEVICE, 2125 .bcdUSB = {0x00, 0x02}, 2126 .bDeviceClass = UDCLASS_HUB, 2127 .bDeviceSubClass = UDSUBCLASS_HUB, 2128 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2129 .bMaxPacketSize = 64, 2130 .bcdDevice = {0x00, 0x01}, 2131 .iManufacturer = 1, 2132 .iProduct = 2, 2133 .bNumConfigurations = 1, 2134 }; 2135 2136 static const struct usb2_device_qualifier musbotg_odevd = { 2137 .bLength = sizeof(struct usb2_device_qualifier), 2138 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 2139 .bcdUSB = {0x00, 0x02}, 2140 .bDeviceClass = UDCLASS_HUB, 2141 .bDeviceSubClass = UDSUBCLASS_HUB, 2142 .bDeviceProtocol = UDPROTO_FSHUB, 2143 .bMaxPacketSize0 = 0, 2144 .bNumConfigurations = 0, 2145 }; 2146 2147 static const struct musbotg_config_desc musbotg_confd = { 2148 .confd = { 2149 .bLength = sizeof(struct usb2_config_descriptor), 2150 .bDescriptorType = UDESC_CONFIG, 2151 .wTotalLength[0] = sizeof(musbotg_confd), 2152 .bNumInterface = 1, 2153 .bConfigurationValue = 1, 2154 .iConfiguration = 0, 2155 .bmAttributes = UC_SELF_POWERED, 2156 .bMaxPower = 0, 2157 }, 2158 .ifcd = { 2159 .bLength = sizeof(struct usb2_interface_descriptor), 2160 .bDescriptorType = UDESC_INTERFACE, 2161 .bNumEndpoints = 1, 2162 .bInterfaceClass = UICLASS_HUB, 2163 .bInterfaceSubClass = UISUBCLASS_HUB, 2164 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2165 }, 2166 2167 .endpd = { 2168 .bLength = sizeof(struct usb2_endpoint_descriptor), 2169 .bDescriptorType = UDESC_ENDPOINT, 2170 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 2171 .bmAttributes = UE_INTERRUPT, 2172 .wMaxPacketSize[0] = 8, 2173 .bInterval = 255, 2174 }, 2175 }; 2176 2177 static const struct usb2_hub_descriptor_min musbotg_hubd = { 2178 .bDescLength = sizeof(musbotg_hubd), 2179 .bDescriptorType = UDESC_HUB, 2180 .bNbrPorts = 1, 2181 .wHubCharacteristics[0] = 2182 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 2183 .wHubCharacteristics[1] = 2184 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 16, 2185 .bPwrOn2PwrGood = 50, 2186 .bHubContrCurrent = 0, 2187 .DeviceRemovable = {0}, /* port is removable */ 2188 }; 2189 2190 #define STRING_LANG \ 2191 0x09, 0x04, /* American English */ 2192 2193 #define STRING_VENDOR \ 2194 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \ 2195 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0 2196 2197 #define STRING_PRODUCT \ 2198 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 2199 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 2200 'U', 0, 'B', 0, 2201 2202 USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab); 2203 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 2204 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 2205 2206 static void 2207 musbotg_root_ctrl_enter(struct usb2_xfer *xfer) 2208 { 2209 return; 2210 } 2211 2212 static void 2213 musbotg_root_ctrl_start(struct usb2_xfer *xfer) 2214 { 2215 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2216 2217 sc->sc_root_ctrl.xfer = xfer; 2218 2219 usb2_bus_roothub_exec(xfer->xroot->bus); 2220 } 2221 2222 static void 2223 musbotg_root_ctrl_task(struct usb2_bus *bus) 2224 { 2225 musbotg_root_ctrl_poll(MUSBOTG_BUS2SC(bus)); 2226 } 2227 2228 static void 2229 musbotg_root_ctrl_done(struct usb2_xfer *xfer, 2230 struct usb2_sw_transfer *std) 2231 { 2232 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2233 uint16_t value; 2234 uint16_t index; 2235 uint8_t use_polling; 2236 2237 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2238 2239 if (std->state != USB_SW_TR_SETUP) { 2240 if (std->state == USB_SW_TR_PRE_CALLBACK) { 2241 /* transfer transferred */ 2242 musbotg_device_done(xfer, std->err); 2243 } 2244 goto done; 2245 } 2246 /* buffer reset */ 2247 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 2248 std->len = 0; 2249 2250 value = UGETW(std->req.wValue); 2251 index = UGETW(std->req.wIndex); 2252 2253 use_polling = mtx_owned(xfer->xroot->xfer_mtx) ? 1 : 0; 2254 2255 /* demultiplex the control request */ 2256 2257 switch (std->req.bmRequestType) { 2258 case UT_READ_DEVICE: 2259 switch (std->req.bRequest) { 2260 case UR_GET_DESCRIPTOR: 2261 goto tr_handle_get_descriptor; 2262 case UR_GET_CONFIG: 2263 goto tr_handle_get_config; 2264 case UR_GET_STATUS: 2265 goto tr_handle_get_status; 2266 default: 2267 goto tr_stalled; 2268 } 2269 break; 2270 2271 case UT_WRITE_DEVICE: 2272 switch (std->req.bRequest) { 2273 case UR_SET_ADDRESS: 2274 goto tr_handle_set_address; 2275 case UR_SET_CONFIG: 2276 goto tr_handle_set_config; 2277 case UR_CLEAR_FEATURE: 2278 goto tr_valid; /* nop */ 2279 case UR_SET_DESCRIPTOR: 2280 goto tr_valid; /* nop */ 2281 case UR_SET_FEATURE: 2282 default: 2283 goto tr_stalled; 2284 } 2285 break; 2286 2287 case UT_WRITE_ENDPOINT: 2288 switch (std->req.bRequest) { 2289 case UR_CLEAR_FEATURE: 2290 switch (UGETW(std->req.wValue)) { 2291 case UF_ENDPOINT_HALT: 2292 goto tr_handle_clear_halt; 2293 case UF_DEVICE_REMOTE_WAKEUP: 2294 goto tr_handle_clear_wakeup; 2295 default: 2296 goto tr_stalled; 2297 } 2298 break; 2299 case UR_SET_FEATURE: 2300 switch (UGETW(std->req.wValue)) { 2301 case UF_ENDPOINT_HALT: 2302 goto tr_handle_set_halt; 2303 case UF_DEVICE_REMOTE_WAKEUP: 2304 goto tr_handle_set_wakeup; 2305 default: 2306 goto tr_stalled; 2307 } 2308 break; 2309 case UR_SYNCH_FRAME: 2310 goto tr_valid; /* nop */ 2311 default: 2312 goto tr_stalled; 2313 } 2314 break; 2315 2316 case UT_READ_ENDPOINT: 2317 switch (std->req.bRequest) { 2318 case UR_GET_STATUS: 2319 goto tr_handle_get_ep_status; 2320 default: 2321 goto tr_stalled; 2322 } 2323 break; 2324 2325 case UT_WRITE_INTERFACE: 2326 switch (std->req.bRequest) { 2327 case UR_SET_INTERFACE: 2328 goto tr_handle_set_interface; 2329 case UR_CLEAR_FEATURE: 2330 goto tr_valid; /* nop */ 2331 case UR_SET_FEATURE: 2332 default: 2333 goto tr_stalled; 2334 } 2335 break; 2336 2337 case UT_READ_INTERFACE: 2338 switch (std->req.bRequest) { 2339 case UR_GET_INTERFACE: 2340 goto tr_handle_get_interface; 2341 case UR_GET_STATUS: 2342 goto tr_handle_get_iface_status; 2343 default: 2344 goto tr_stalled; 2345 } 2346 break; 2347 2348 case UT_WRITE_CLASS_INTERFACE: 2349 case UT_WRITE_VENDOR_INTERFACE: 2350 /* XXX forward */ 2351 break; 2352 2353 case UT_READ_CLASS_INTERFACE: 2354 case UT_READ_VENDOR_INTERFACE: 2355 /* XXX forward */ 2356 break; 2357 2358 case UT_WRITE_CLASS_DEVICE: 2359 switch (std->req.bRequest) { 2360 case UR_CLEAR_FEATURE: 2361 goto tr_valid; 2362 case UR_SET_DESCRIPTOR: 2363 case UR_SET_FEATURE: 2364 break; 2365 default: 2366 goto tr_stalled; 2367 } 2368 break; 2369 2370 case UT_WRITE_CLASS_OTHER: 2371 switch (std->req.bRequest) { 2372 case UR_CLEAR_FEATURE: 2373 goto tr_handle_clear_port_feature; 2374 case UR_SET_FEATURE: 2375 goto tr_handle_set_port_feature; 2376 case UR_CLEAR_TT_BUFFER: 2377 case UR_RESET_TT: 2378 case UR_STOP_TT: 2379 goto tr_valid; 2380 2381 default: 2382 goto tr_stalled; 2383 } 2384 break; 2385 2386 case UT_READ_CLASS_OTHER: 2387 switch (std->req.bRequest) { 2388 case UR_GET_TT_STATE: 2389 goto tr_handle_get_tt_state; 2390 case UR_GET_STATUS: 2391 goto tr_handle_get_port_status; 2392 default: 2393 goto tr_stalled; 2394 } 2395 break; 2396 2397 case UT_READ_CLASS_DEVICE: 2398 switch (std->req.bRequest) { 2399 case UR_GET_DESCRIPTOR: 2400 goto tr_handle_get_class_descriptor; 2401 case UR_GET_STATUS: 2402 goto tr_handle_get_class_status; 2403 2404 default: 2405 goto tr_stalled; 2406 } 2407 break; 2408 default: 2409 goto tr_stalled; 2410 } 2411 goto tr_valid; 2412 2413 tr_handle_get_descriptor: 2414 switch (value >> 8) { 2415 case UDESC_DEVICE: 2416 if (value & 0xff) { 2417 goto tr_stalled; 2418 } 2419 std->len = sizeof(musbotg_devd); 2420 std->ptr = USB_ADD_BYTES(&musbotg_devd, 0); 2421 goto tr_valid; 2422 case UDESC_CONFIG: 2423 if (value & 0xff) { 2424 goto tr_stalled; 2425 } 2426 std->len = sizeof(musbotg_confd); 2427 std->ptr = USB_ADD_BYTES(&musbotg_confd, 0); 2428 goto tr_valid; 2429 case UDESC_STRING: 2430 switch (value & 0xff) { 2431 case 0: /* Language table */ 2432 std->len = sizeof(musbotg_langtab); 2433 std->ptr = USB_ADD_BYTES(&musbotg_langtab, 0); 2434 goto tr_valid; 2435 2436 case 1: /* Vendor */ 2437 std->len = sizeof(musbotg_vendor); 2438 std->ptr = USB_ADD_BYTES(&musbotg_vendor, 0); 2439 goto tr_valid; 2440 2441 case 2: /* Product */ 2442 std->len = sizeof(musbotg_product); 2443 std->ptr = USB_ADD_BYTES(&musbotg_product, 0); 2444 goto tr_valid; 2445 default: 2446 break; 2447 } 2448 break; 2449 default: 2450 goto tr_stalled; 2451 } 2452 goto tr_stalled; 2453 2454 tr_handle_get_config: 2455 std->len = 1; 2456 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2457 goto tr_valid; 2458 2459 tr_handle_get_status: 2460 std->len = 2; 2461 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2462 goto tr_valid; 2463 2464 tr_handle_set_address: 2465 if (value & 0xFF00) { 2466 goto tr_stalled; 2467 } 2468 sc->sc_rt_addr = value; 2469 goto tr_valid; 2470 2471 tr_handle_set_config: 2472 if (value >= 2) { 2473 goto tr_stalled; 2474 } 2475 sc->sc_conf = value; 2476 goto tr_valid; 2477 2478 tr_handle_get_interface: 2479 std->len = 1; 2480 sc->sc_hub_temp.wValue[0] = 0; 2481 goto tr_valid; 2482 2483 tr_handle_get_tt_state: 2484 tr_handle_get_class_status: 2485 tr_handle_get_iface_status: 2486 tr_handle_get_ep_status: 2487 std->len = 2; 2488 USETW(sc->sc_hub_temp.wValue, 0); 2489 goto tr_valid; 2490 2491 tr_handle_set_halt: 2492 tr_handle_set_interface: 2493 tr_handle_set_wakeup: 2494 tr_handle_clear_wakeup: 2495 tr_handle_clear_halt: 2496 goto tr_valid; 2497 2498 tr_handle_clear_port_feature: 2499 if (index != 1) { 2500 goto tr_stalled; 2501 } 2502 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2503 2504 switch (value) { 2505 case UHF_PORT_SUSPEND: 2506 musbotg_wakeup_peer(xfer); 2507 break; 2508 2509 case UHF_PORT_ENABLE: 2510 sc->sc_flags.port_enabled = 0; 2511 break; 2512 2513 case UHF_PORT_TEST: 2514 case UHF_PORT_INDICATOR: 2515 case UHF_C_PORT_ENABLE: 2516 case UHF_C_PORT_OVER_CURRENT: 2517 case UHF_C_PORT_RESET: 2518 /* nops */ 2519 break; 2520 case UHF_PORT_POWER: 2521 sc->sc_flags.port_powered = 0; 2522 musbotg_pull_down(sc); 2523 musbotg_clocks_off(sc); 2524 break; 2525 case UHF_C_PORT_CONNECTION: 2526 sc->sc_flags.change_connect = 0; 2527 break; 2528 case UHF_C_PORT_SUSPEND: 2529 sc->sc_flags.change_suspend = 0; 2530 break; 2531 default: 2532 std->err = USB_ERR_IOERROR; 2533 goto done; 2534 } 2535 goto tr_valid; 2536 2537 tr_handle_set_port_feature: 2538 if (index != 1) { 2539 goto tr_stalled; 2540 } 2541 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 2542 2543 switch (value) { 2544 case UHF_PORT_ENABLE: 2545 sc->sc_flags.port_enabled = 1; 2546 break; 2547 case UHF_PORT_SUSPEND: 2548 case UHF_PORT_RESET: 2549 case UHF_PORT_TEST: 2550 case UHF_PORT_INDICATOR: 2551 /* nops */ 2552 break; 2553 case UHF_PORT_POWER: 2554 sc->sc_flags.port_powered = 1; 2555 break; 2556 default: 2557 std->err = USB_ERR_IOERROR; 2558 goto done; 2559 } 2560 goto tr_valid; 2561 2562 tr_handle_get_port_status: 2563 2564 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 2565 2566 if (index != 1) { 2567 goto tr_stalled; 2568 } 2569 if (sc->sc_flags.status_vbus) { 2570 musbotg_clocks_on(sc); 2571 musbotg_pull_up(sc); 2572 } else { 2573 musbotg_pull_down(sc); 2574 musbotg_clocks_off(sc); 2575 } 2576 2577 /* Select Device Side Mode */ 2578 value = UPS_PORT_MODE_DEVICE; 2579 2580 if (sc->sc_flags.status_high_speed) { 2581 value |= UPS_HIGH_SPEED; 2582 } 2583 if (sc->sc_flags.port_powered) { 2584 value |= UPS_PORT_POWER; 2585 } 2586 if (sc->sc_flags.port_enabled) { 2587 value |= UPS_PORT_ENABLED; 2588 } 2589 if (sc->sc_flags.status_vbus && 2590 sc->sc_flags.status_bus_reset) { 2591 value |= UPS_CURRENT_CONNECT_STATUS; 2592 } 2593 if (sc->sc_flags.status_suspend) { 2594 value |= UPS_SUSPEND; 2595 } 2596 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2597 2598 value = 0; 2599 2600 if (sc->sc_flags.change_connect) { 2601 value |= UPS_C_CONNECT_STATUS; 2602 2603 if (sc->sc_flags.status_vbus && 2604 sc->sc_flags.status_bus_reset) { 2605 /* reset EP0 state */ 2606 sc->sc_ep0_busy = 0; 2607 sc->sc_ep0_cmd = 0; 2608 } 2609 } 2610 if (sc->sc_flags.change_suspend) { 2611 value |= UPS_C_SUSPEND; 2612 } 2613 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2614 std->len = sizeof(sc->sc_hub_temp.ps); 2615 goto tr_valid; 2616 2617 tr_handle_get_class_descriptor: 2618 if (value & 0xFF) { 2619 goto tr_stalled; 2620 } 2621 std->ptr = USB_ADD_BYTES(&musbotg_hubd, 0); 2622 std->len = sizeof(musbotg_hubd); 2623 goto tr_valid; 2624 2625 tr_stalled: 2626 std->err = USB_ERR_STALLED; 2627 tr_valid: 2628 done: 2629 return; 2630 } 2631 2632 static void 2633 musbotg_root_ctrl_poll(struct musbotg_softc *sc) 2634 { 2635 usb2_sw_transfer(&sc->sc_root_ctrl, 2636 &musbotg_root_ctrl_done); 2637 } 2638 2639 struct usb2_pipe_methods musbotg_root_ctrl_methods = 2640 { 2641 .open = musbotg_root_ctrl_open, 2642 .close = musbotg_root_ctrl_close, 2643 .enter = musbotg_root_ctrl_enter, 2644 .start = musbotg_root_ctrl_start, 2645 .enter_is_cancelable = 1, 2646 .start_is_cancelable = 0, 2647 }; 2648 2649 /*------------------------------------------------------------------------* 2650 * musbotg root interrupt support 2651 *------------------------------------------------------------------------*/ 2652 static void 2653 musbotg_root_intr_open(struct usb2_xfer *xfer) 2654 { 2655 return; 2656 } 2657 2658 static void 2659 musbotg_root_intr_close(struct usb2_xfer *xfer) 2660 { 2661 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2662 2663 if (sc->sc_root_intr.xfer == xfer) { 2664 sc->sc_root_intr.xfer = NULL; 2665 } 2666 musbotg_device_done(xfer, USB_ERR_CANCELLED); 2667 } 2668 2669 static void 2670 musbotg_root_intr_enter(struct usb2_xfer *xfer) 2671 { 2672 return; 2673 } 2674 2675 static void 2676 musbotg_root_intr_start(struct usb2_xfer *xfer) 2677 { 2678 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2679 2680 sc->sc_root_intr.xfer = xfer; 2681 } 2682 2683 struct usb2_pipe_methods musbotg_root_intr_methods = 2684 { 2685 .open = musbotg_root_intr_open, 2686 .close = musbotg_root_intr_close, 2687 .enter = musbotg_root_intr_enter, 2688 .start = musbotg_root_intr_start, 2689 .enter_is_cancelable = 1, 2690 .start_is_cancelable = 1, 2691 }; 2692 2693 static void 2694 musbotg_xfer_setup(struct usb2_setup_params *parm) 2695 { 2696 const struct usb2_hw_ep_profile *pf; 2697 struct musbotg_softc *sc; 2698 struct usb2_xfer *xfer; 2699 void *last_obj; 2700 uint32_t ntd; 2701 uint32_t n; 2702 uint8_t ep_no; 2703 2704 sc = MUSBOTG_BUS2SC(parm->udev->bus); 2705 xfer = parm->curr_xfer; 2706 2707 /* 2708 * NOTE: This driver does not use any of the parameters that 2709 * are computed from the following values. Just set some 2710 * reasonable dummies: 2711 */ 2712 parm->hc_max_packet_size = 0x400; 2713 parm->hc_max_frame_size = 0x400; 2714 2715 if ((parm->methods == &musbotg_device_isoc_methods) || 2716 (parm->methods == &musbotg_device_intr_methods)) 2717 parm->hc_max_packet_count = 3; 2718 else 2719 parm->hc_max_packet_count = 1; 2720 2721 usb2_transfer_setup_sub(parm); 2722 2723 /* 2724 * compute maximum number of TDs 2725 */ 2726 if (parm->methods == &musbotg_device_ctrl_methods) { 2727 2728 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 2729 2730 } else if (parm->methods == &musbotg_device_bulk_methods) { 2731 2732 ntd = xfer->nframes + 1 /* SYNC */ ; 2733 2734 } else if (parm->methods == &musbotg_device_intr_methods) { 2735 2736 ntd = xfer->nframes + 1 /* SYNC */ ; 2737 2738 } else if (parm->methods == &musbotg_device_isoc_methods) { 2739 2740 ntd = xfer->nframes + 1 /* SYNC */ ; 2741 2742 } else { 2743 2744 ntd = 0; 2745 } 2746 2747 /* 2748 * check if "usb2_transfer_setup_sub" set an error 2749 */ 2750 if (parm->err) { 2751 return; 2752 } 2753 /* 2754 * allocate transfer descriptors 2755 */ 2756 last_obj = NULL; 2757 2758 /* 2759 * get profile stuff 2760 */ 2761 if (ntd) { 2762 2763 ep_no = xfer->endpoint & UE_ADDR; 2764 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 2765 2766 if (pf == NULL) { 2767 /* should not happen */ 2768 parm->err = USB_ERR_INVAL; 2769 return; 2770 } 2771 } else { 2772 ep_no = 0; 2773 pf = NULL; 2774 } 2775 2776 /* align data */ 2777 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2778 2779 for (n = 0; n != ntd; n++) { 2780 2781 struct musbotg_td *td; 2782 2783 if (parm->buf) { 2784 2785 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2786 2787 /* init TD */ 2788 td->max_frame_size = xfer->max_frame_size; 2789 td->ep_no = ep_no; 2790 td->obj_next = last_obj; 2791 2792 last_obj = td; 2793 } 2794 parm->size[0] += sizeof(*td); 2795 } 2796 2797 xfer->td_start[0] = last_obj; 2798 } 2799 2800 static void 2801 musbotg_xfer_unsetup(struct usb2_xfer *xfer) 2802 { 2803 return; 2804 } 2805 2806 static void 2807 musbotg_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2808 struct usb2_pipe *pipe) 2809 { 2810 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 2811 2812 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2813 pipe, udev->address, 2814 edesc->bEndpointAddress, udev->flags.usb2_mode, 2815 sc->sc_rt_addr); 2816 2817 if (udev->device_index == sc->sc_rt_addr) { 2818 2819 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2820 /* not supported */ 2821 return; 2822 } 2823 switch (edesc->bEndpointAddress) { 2824 case USB_CONTROL_ENDPOINT: 2825 pipe->methods = &musbotg_root_ctrl_methods; 2826 break; 2827 case UE_DIR_IN | MUSBOTG_INTR_ENDPT: 2828 pipe->methods = &musbotg_root_intr_methods; 2829 break; 2830 default: 2831 /* do nothing */ 2832 break; 2833 } 2834 } else { 2835 2836 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2837 /* not supported */ 2838 return; 2839 } 2840 if ((udev->speed != USB_SPEED_FULL) && 2841 (udev->speed != USB_SPEED_HIGH)) { 2842 /* not supported */ 2843 return; 2844 } 2845 switch (edesc->bmAttributes & UE_XFERTYPE) { 2846 case UE_CONTROL: 2847 pipe->methods = &musbotg_device_ctrl_methods; 2848 break; 2849 case UE_INTERRUPT: 2850 pipe->methods = &musbotg_device_intr_methods; 2851 break; 2852 case UE_ISOCHRONOUS: 2853 pipe->methods = &musbotg_device_isoc_methods; 2854 break; 2855 case UE_BULK: 2856 pipe->methods = &musbotg_device_bulk_methods; 2857 break; 2858 default: 2859 /* do nothing */ 2860 break; 2861 } 2862 } 2863 } 2864 2865 struct usb2_bus_methods musbotg_bus_methods = 2866 { 2867 .pipe_init = &musbotg_pipe_init, 2868 .xfer_setup = &musbotg_xfer_setup, 2869 .xfer_unsetup = &musbotg_xfer_unsetup, 2870 .do_poll = &musbotg_do_poll, 2871 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 2872 .set_stall = &musbotg_set_stall, 2873 .clear_stall = &musbotg_clear_stall, 2874 .roothub_exec = &musbotg_root_ctrl_task, 2875 }; 2876