xref: /freebsd/sys/dev/usb/controller/musb_otg.c (revision 13de33a5dc2304b13d595d75d48c51793958474f)
1 /* $FreeBSD$ */
2 /*-
3  * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 /*
28  * Thanks to Mentor Graphics for providing a reference driver for this USB chip
29  * at their homepage.
30  */
31 
32 /*
33  * This file contains the driver for the Mentor Graphics Inventra USB
34  * 2.0 High Speed Dual-Role controller.
35  *
36  * NOTE: The current implementation only supports Device Side Mode!
37  */
38 
39 #ifdef USB_GLOBAL_INCLUDE_FILE
40 #include USB_GLOBAL_INCLUDE_FILE
41 #else
42 #include <sys/stdint.h>
43 #include <sys/stddef.h>
44 #include <sys/param.h>
45 #include <sys/queue.h>
46 #include <sys/types.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/bus.h>
50 #include <sys/module.h>
51 #include <sys/lock.h>
52 #include <sys/mutex.h>
53 #include <sys/condvar.h>
54 #include <sys/sysctl.h>
55 #include <sys/sx.h>
56 #include <sys/unistd.h>
57 #include <sys/callout.h>
58 #include <sys/malloc.h>
59 #include <sys/priv.h>
60 
61 #include <dev/usb/usb.h>
62 #include <dev/usb/usbdi.h>
63 
64 #define	USB_DEBUG_VAR musbotgdebug
65 
66 #include <dev/usb/usb_core.h>
67 #include <dev/usb/usb_debug.h>
68 #include <dev/usb/usb_busdma.h>
69 #include <dev/usb/usb_process.h>
70 #include <dev/usb/usb_transfer.h>
71 #include <dev/usb/usb_device.h>
72 #include <dev/usb/usb_hub.h>
73 #include <dev/usb/usb_util.h>
74 
75 #include <dev/usb/usb_controller.h>
76 #include <dev/usb/usb_bus.h>
77 #endif			/* USB_GLOBAL_INCLUDE_FILE */
78 
79 #include <dev/usb/controller/musb_otg.h>
80 
81 #define	MUSBOTG_INTR_ENDPT 1
82 
83 #define	MUSBOTG_BUS2SC(bus) \
84    ((struct musbotg_softc *)(((uint8_t *)(bus)) - \
85    USB_P2U(&(((struct musbotg_softc *)0)->sc_bus))))
86 
87 #define	MUSBOTG_PC2SC(pc) \
88    MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
89 
90 #ifdef USB_DEBUG
91 static int musbotgdebug = 0;
92 
93 static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg");
94 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RW,
95     &musbotgdebug, 0, "Debug level");
96 #endif
97 
98 #define	MAX_NAK_TO	16
99 
100 /* prototypes */
101 
102 struct usb_bus_methods musbotg_bus_methods;
103 struct usb_pipe_methods musbotg_device_bulk_methods;
104 struct usb_pipe_methods musbotg_device_ctrl_methods;
105 struct usb_pipe_methods musbotg_device_intr_methods;
106 struct usb_pipe_methods musbotg_device_isoc_methods;
107 
108 /* Control transfers: Device mode */
109 static musbotg_cmd_t musbotg_dev_ctrl_setup_rx;
110 static musbotg_cmd_t musbotg_dev_ctrl_data_rx;
111 static musbotg_cmd_t musbotg_dev_ctrl_data_tx;
112 static musbotg_cmd_t musbotg_dev_ctrl_status;
113 
114 /* Control transfers: Host mode */
115 static musbotg_cmd_t musbotg_host_ctrl_setup_tx;
116 static musbotg_cmd_t musbotg_host_ctrl_data_rx;
117 static musbotg_cmd_t musbotg_host_ctrl_data_tx;
118 static musbotg_cmd_t musbotg_host_ctrl_status_rx;
119 static musbotg_cmd_t musbotg_host_ctrl_status_tx;
120 
121 /* Bulk, Interrupt, Isochronous: Device mode */
122 static musbotg_cmd_t musbotg_dev_data_rx;
123 static musbotg_cmd_t musbotg_dev_data_tx;
124 
125 /* Bulk, Interrupt, Isochronous: Host mode */
126 static musbotg_cmd_t musbotg_host_data_rx;
127 static musbotg_cmd_t musbotg_host_data_tx;
128 
129 static void	musbotg_device_done(struct usb_xfer *, usb_error_t);
130 static void	musbotg_do_poll(struct usb_bus *);
131 static void	musbotg_standard_done(struct usb_xfer *);
132 static void	musbotg_interrupt_poll(struct musbotg_softc *);
133 static void	musbotg_root_intr(struct musbotg_softc *);
134 static int	musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td);
135 static void	musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td);
136 static void	musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on);
137 
138 /*
139  * Here is a configuration that the chip supports.
140  */
141 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = {
142 
143 	[0] = {
144 		.max_in_frame_size = 64,/* fixed */
145 		.max_out_frame_size = 64,	/* fixed */
146 		.is_simplex = 1,
147 		.support_control = 1,
148 	}
149 };
150 
151 static int
152 musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td)
153 {
154 	int ch;
155 	int ep;
156 
157 	ep = td->ep_no;
158 
159 	/* In device mode each EP got its own channel */
160 	if (sc->sc_mode == MUSB2_DEVICE_MODE) {
161 		musbotg_ep_int_set(sc, ep, 1);
162 		return (ep);
163 	}
164 
165 	/*
166 	 * All control transactions go through EP0
167 	 */
168 	if (ep == 0) {
169 		if (sc->sc_channel_mask & (1 << 0))
170 			return (-1);
171 		sc->sc_channel_mask |= (1 << 0);
172 		musbotg_ep_int_set(sc, ep, 1);
173 		return (0);
174 	}
175 
176 	for (ch = 1; ch < MUSB2_EP_MAX; ch++) {
177 		if (!(sc->sc_channel_mask & (1 << ch))) {
178 			sc->sc_channel_mask |= (1 << ch);
179 			musbotg_ep_int_set(sc, ch, 1);
180 			return (ch);
181 		}
182 	}
183 
184 	DPRINTFN(-1, "No available channels. Mask: %04x\n",  sc->sc_channel_mask);
185 
186 	return (-1);
187 }
188 
189 static void
190 musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td)
191 {
192 
193 	DPRINTFN(1, "ep_no=%d\n", td->channel);
194 
195 	if (sc->sc_mode == MUSB2_DEVICE_MODE)
196 		return;
197 
198 	if (td == NULL)
199 		return;
200 	if (td->channel == -1)
201 		return;
202 
203 	musbotg_ep_int_set(sc, td->channel, 0);
204 	sc->sc_channel_mask &= ~(1 << td->channel);
205 
206 	td->channel = -1;
207 }
208 
209 static void
210 musbotg_get_hw_ep_profile(struct usb_device *udev,
211     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
212 {
213 	struct musbotg_softc *sc;
214 
215 	sc = MUSBOTG_BUS2SC(udev->bus);
216 
217 	if (ep_addr == 0) {
218 		/* control endpoint */
219 		*ppf = musbotg_ep_profile;
220 	} else if (ep_addr <= sc->sc_ep_max) {
221 		/* other endpoints */
222 		*ppf = sc->sc_hw_ep_profile + ep_addr;
223 	} else {
224 		*ppf = NULL;
225 	}
226 }
227 
228 static void
229 musbotg_clocks_on(struct musbotg_softc *sc)
230 {
231 	if (sc->sc_flags.clocks_off &&
232 	    sc->sc_flags.port_powered) {
233 
234 		DPRINTFN(4, "\n");
235 
236 		if (sc->sc_clocks_on) {
237 			(sc->sc_clocks_on) (sc->sc_clocks_arg);
238 		}
239 		sc->sc_flags.clocks_off = 0;
240 
241 		/* XXX enable Transceiver */
242 	}
243 }
244 
245 static void
246 musbotg_clocks_off(struct musbotg_softc *sc)
247 {
248 	if (!sc->sc_flags.clocks_off) {
249 
250 		DPRINTFN(4, "\n");
251 
252 		/* XXX disable Transceiver */
253 
254 		if (sc->sc_clocks_off) {
255 			(sc->sc_clocks_off) (sc->sc_clocks_arg);
256 		}
257 		sc->sc_flags.clocks_off = 1;
258 	}
259 }
260 
261 static void
262 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
263 {
264 	uint8_t temp;
265 
266 	temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
267 	if (on)
268 		temp |= MUSB2_MASK_SOFTC;
269 	else
270 		temp &= ~MUSB2_MASK_SOFTC;
271 
272 	MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
273 }
274 
275 static void
276 musbotg_pull_up(struct musbotg_softc *sc)
277 {
278 	/* pullup D+, if possible */
279 
280 	if (!sc->sc_flags.d_pulled_up &&
281 	    sc->sc_flags.port_powered) {
282 		sc->sc_flags.d_pulled_up = 1;
283 		musbotg_pull_common(sc, 1);
284 	}
285 }
286 
287 static void
288 musbotg_pull_down(struct musbotg_softc *sc)
289 {
290 	/* pulldown D+, if possible */
291 
292 	if (sc->sc_flags.d_pulled_up) {
293 		sc->sc_flags.d_pulled_up = 0;
294 		musbotg_pull_common(sc, 0);
295 	}
296 }
297 
298 static void
299 musbotg_suspend_host(struct musbotg_softc *sc)
300 {
301 	uint8_t temp;
302 
303 	if (sc->sc_flags.status_suspend) {
304 		return;
305 	}
306 
307 	temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
308 	temp |= MUSB2_MASK_SUSPMODE;
309 	MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
310 	sc->sc_flags.status_suspend = 1;
311 }
312 
313 static void
314 musbotg_wakeup_host(struct musbotg_softc *sc)
315 {
316 	uint8_t temp;
317 
318 	if (!(sc->sc_flags.status_suspend)) {
319 		return;
320 	}
321 
322 	temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
323 	temp &= ~MUSB2_MASK_SUSPMODE;
324 	temp |= MUSB2_MASK_RESUME;
325 	MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
326 
327 	/* wait 20 milliseconds */
328 	/* Wait for reset to complete. */
329 	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
330 
331 	temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
332 	temp &= ~MUSB2_MASK_RESUME;
333 	MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
334 
335 	sc->sc_flags.status_suspend = 0;
336 }
337 
338 static void
339 musbotg_wakeup_peer(struct musbotg_softc *sc)
340 {
341 	uint8_t temp;
342 
343 	if (!(sc->sc_flags.status_suspend)) {
344 		return;
345 	}
346 
347 	temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
348 	temp |= MUSB2_MASK_RESUME;
349 	MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
350 
351 	/* wait 8 milliseconds */
352 	/* Wait for reset to complete. */
353 	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
354 
355 	temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
356 	temp &= ~MUSB2_MASK_RESUME;
357 	MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
358 }
359 
360 static void
361 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
362 {
363 	DPRINTFN(4, "addr=%d\n", addr);
364 	addr &= 0x7F;
365 	MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr);
366 }
367 
368 static uint8_t
369 musbotg_dev_ctrl_setup_rx(struct musbotg_td *td)
370 {
371 	struct musbotg_softc *sc;
372 	struct usb_device_request req;
373 	uint16_t count;
374 	uint8_t csr;
375 
376 	/* get pointer to softc */
377 	sc = MUSBOTG_PC2SC(td->pc);
378 
379 	if (td->channel == -1)
380 		td->channel = musbotg_channel_alloc(sc, td);
381 
382 	/* EP0 is busy, wait */
383 	if (td->channel == -1)
384 		return (1);
385 
386 	DPRINTFN(1, "ep_no=%d\n", td->channel);
387 
388 	/* select endpoint 0 */
389 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
390 
391 	/* read out FIFO status */
392 	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
393 
394 	DPRINTFN(4, "csr=0x%02x\n", csr);
395 
396 	/*
397 	 * NOTE: If DATAEND is set we should not call the
398 	 * callback, hence the status stage is not complete.
399 	 */
400 	if (csr & MUSB2_MASK_CSR0L_DATAEND) {
401 		/* do not stall at this point */
402 		td->did_stall = 1;
403 		/* wait for interrupt */
404 		DPRINTFN(0, "CSR0 DATAEND\n");
405 		goto not_complete;
406 	}
407 
408 	if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
409 		/* clear SENTSTALL */
410 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
411 		/* get latest status */
412 		csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
413 		/* update EP0 state */
414 		sc->sc_ep0_busy = 0;
415 	}
416 	if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
417 		/* clear SETUPEND */
418 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
419 		    MUSB2_MASK_CSR0L_SETUPEND_CLR);
420 		/* get latest status */
421 		csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
422 		/* update EP0 state */
423 		sc->sc_ep0_busy = 0;
424 	}
425 	if (sc->sc_ep0_busy) {
426 		DPRINTFN(0, "EP0 BUSY\n");
427 		goto not_complete;
428 	}
429 	if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
430 		goto not_complete;
431 	}
432 	/* clear did stall flag */
433 	td->did_stall = 0;
434 	/* get the packet byte count */
435 	count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
436 
437 	/* verify data length */
438 	if (count != td->remainder) {
439 		DPRINTFN(0, "Invalid SETUP packet "
440 		    "length, %d bytes\n", count);
441 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
442 		      MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
443 		goto not_complete;
444 	}
445 	if (count != sizeof(req)) {
446 		DPRINTFN(0, "Unsupported SETUP packet "
447 		    "length, %d bytes\n", count);
448 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
449 		      MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
450 		goto not_complete;
451 	}
452 	/* receive data */
453 	bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
454 	    MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
455 
456 	/* copy data into real buffer */
457 	usbd_copy_in(td->pc, 0, &req, sizeof(req));
458 
459 	td->offset = sizeof(req);
460 	td->remainder = 0;
461 
462 	/* set pending command */
463 	sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
464 
465 	/* we need set stall or dataend after this */
466 	sc->sc_ep0_busy = 1;
467 
468 	/* sneak peek the set address */
469 	if ((req.bmRequestType == UT_WRITE_DEVICE) &&
470 	    (req.bRequest == UR_SET_ADDRESS)) {
471 		sc->sc_dv_addr = req.wValue[0] & 0x7F;
472 	} else {
473 		sc->sc_dv_addr = 0xFF;
474 	}
475 
476 	musbotg_channel_free(sc, td);
477 	return (0);			/* complete */
478 
479 not_complete:
480 	/* abort any ongoing transfer */
481 	if (!td->did_stall) {
482 		DPRINTFN(4, "stalling\n");
483 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
484 		    MUSB2_MASK_CSR0L_SENDSTALL);
485 		td->did_stall = 1;
486 	}
487 	return (1);			/* not complete */
488 }
489 
490 static uint8_t
491 musbotg_host_ctrl_setup_tx(struct musbotg_td *td)
492 {
493 	struct musbotg_softc *sc;
494 	struct usb_device_request req;
495 	uint8_t csr, csrh;
496 
497 	/* get pointer to softc */
498 	sc = MUSBOTG_PC2SC(td->pc);
499 
500 	if (td->channel == -1)
501 		td->channel = musbotg_channel_alloc(sc, td);
502 
503 	/* EP0 is busy, wait */
504 	if (td->channel == -1)
505 		return (1);
506 
507 	DPRINTFN(1, "ep_no=%d\n", td->channel);
508 
509 	/* select endpoint 0 */
510 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
511 
512 	/* read out FIFO status */
513 	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
514 	DPRINTFN(4, "csr=0x%02x\n", csr);
515 
516 	/* Not ready yet yet */
517 	if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
518 		return (1);
519 
520 	/* Failed */
521 	if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
522 	    MUSB2_MASK_CSR0L_ERROR))
523 	{
524 		/* Clear status bit */
525 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
526 		DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
527 		td->error = 1;
528 	}
529 
530 	if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
531 		DPRINTFN(1, "NAK timeout\n");
532 
533 		if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
534 			csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
535 			csrh |= MUSB2_MASK_CSR0H_FFLUSH;
536 			MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
537 			csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
538 			if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
539 				csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
540 				csrh |= MUSB2_MASK_CSR0H_FFLUSH;
541 				MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
542 				csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
543 			}
544 		}
545 
546 		csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
547 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
548 
549 		td->error = 1;
550 	}
551 
552 	if (td->error) {
553 		musbotg_channel_free(sc, td);
554 		return (0);
555 	}
556 
557 	/* Fifo is not empty and there is no NAK timeout */
558 	if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
559 		return (1);
560 
561 	/* check if we are complete */
562 	if (td->remainder == 0) {
563 		/* we are complete */
564 		musbotg_channel_free(sc, td);
565 		return (0);
566 	}
567 
568 	/* copy data into real buffer */
569 	usbd_copy_out(td->pc, 0, &req, sizeof(req));
570 
571 	/* send data */
572 	bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
573 	    MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
574 
575 	/* update offset and remainder */
576 	td->offset += sizeof(req);
577 	td->remainder -= sizeof(req);
578 
579 
580 	MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
581 	MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
582 	MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
583 	MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
584 	MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
585 
586 	/* write command */
587 	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
588 	    MUSB2_MASK_CSR0L_TXPKTRDY |
589 	    MUSB2_MASK_CSR0L_SETUPPKT);
590 
591 	/* Just to be consistent, not used above */
592 	td->transaction_started = 1;
593 
594 	return (1);			/* in progress */
595 }
596 
597 /* Control endpoint only data handling functions (RX/TX/SYNC) */
598 
599 static uint8_t
600 musbotg_dev_ctrl_data_rx(struct musbotg_td *td)
601 {
602 	struct usb_page_search buf_res;
603 	struct musbotg_softc *sc;
604 	uint16_t count;
605 	uint8_t csr;
606 	uint8_t got_short;
607 
608 	/* get pointer to softc */
609 	sc = MUSBOTG_PC2SC(td->pc);
610 
611 	/* select endpoint 0 */
612 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
613 
614 	/* check if a command is pending */
615 	if (sc->sc_ep0_cmd) {
616 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
617 		sc->sc_ep0_cmd = 0;
618 	}
619 	/* read out FIFO status */
620 	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
621 
622 	DPRINTFN(4, "csr=0x%02x\n", csr);
623 
624 	got_short = 0;
625 
626 	if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
627 	    MUSB2_MASK_CSR0L_SENTSTALL)) {
628 		if (td->remainder == 0) {
629 			/*
630 			 * We are actually complete and have
631 			 * received the next SETUP
632 			 */
633 			DPRINTFN(4, "faking complete\n");
634 			return (0);	/* complete */
635 		}
636 		/*
637 	         * USB Host Aborted the transfer.
638 	         */
639 		td->error = 1;
640 		return (0);		/* complete */
641 	}
642 	if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
643 		return (1);		/* not complete */
644 	}
645 	/* get the packet byte count */
646 	count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
647 
648 	/* verify the packet byte count */
649 	if (count != td->max_frame_size) {
650 		if (count < td->max_frame_size) {
651 			/* we have a short packet */
652 			td->short_pkt = 1;
653 			got_short = 1;
654 		} else {
655 			/* invalid USB packet */
656 			td->error = 1;
657 			return (0);	/* we are complete */
658 		}
659 	}
660 	/* verify the packet byte count */
661 	if (count > td->remainder) {
662 		/* invalid USB packet */
663 		td->error = 1;
664 		return (0);		/* we are complete */
665 	}
666 	while (count > 0) {
667 		uint32_t temp;
668 
669 		usbd_get_page(td->pc, td->offset, &buf_res);
670 
671 		/* get correct length */
672 		if (buf_res.length > count) {
673 			buf_res.length = count;
674 		}
675 		/* check for unaligned memory address */
676 		if (USB_P2U(buf_res.buffer) & 3) {
677 
678 			temp = count & ~3;
679 
680 			if (temp) {
681 				/* receive data 4 bytes at a time */
682 				bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
683 				    MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
684 				    temp / 4);
685 			}
686 			temp = count & 3;
687 			if (temp) {
688 				/* receive data 1 byte at a time */
689 				bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
690 				    MUSB2_REG_EPFIFO(0),
691 				    (void *)(&sc->sc_bounce_buf[count / 4]), temp);
692 			}
693 			usbd_copy_in(td->pc, td->offset,
694 			    sc->sc_bounce_buf, count);
695 
696 			/* update offset and remainder */
697 			td->offset += count;
698 			td->remainder -= count;
699 			break;
700 		}
701 		/* check if we can optimise */
702 		if (buf_res.length >= 4) {
703 
704 			/* receive data 4 bytes at a time */
705 			bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
706 			    MUSB2_REG_EPFIFO(0), buf_res.buffer,
707 			    buf_res.length / 4);
708 
709 			temp = buf_res.length & ~3;
710 
711 			/* update counters */
712 			count -= temp;
713 			td->offset += temp;
714 			td->remainder -= temp;
715 			continue;
716 		}
717 		/* receive data */
718 		bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
719 		    MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
720 
721 		/* update counters */
722 		count -= buf_res.length;
723 		td->offset += buf_res.length;
724 		td->remainder -= buf_res.length;
725 	}
726 
727 	/* check if we are complete */
728 	if ((td->remainder == 0) || got_short) {
729 		if (td->short_pkt) {
730 			/* we are complete */
731 			sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
732 			return (0);
733 		}
734 		/* else need to receive a zero length packet */
735 	}
736 	/* write command - need more data */
737 	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
738 	    MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
739 	return (1);			/* not complete */
740 }
741 
742 static uint8_t
743 musbotg_dev_ctrl_data_tx(struct musbotg_td *td)
744 {
745 	struct usb_page_search buf_res;
746 	struct musbotg_softc *sc;
747 	uint16_t count;
748 	uint8_t csr;
749 
750 	/* get pointer to softc */
751 	sc = MUSBOTG_PC2SC(td->pc);
752 
753 	/* select endpoint 0 */
754 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
755 
756 	/* check if a command is pending */
757 	if (sc->sc_ep0_cmd) {
758 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
759 		sc->sc_ep0_cmd = 0;
760 	}
761 	/* read out FIFO status */
762 	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
763 
764 	DPRINTFN(4, "csr=0x%02x\n", csr);
765 
766 	if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
767 	    MUSB2_MASK_CSR0L_SENTSTALL)) {
768 		/*
769 	         * The current transfer was aborted
770 	         * by the USB Host
771 	         */
772 		td->error = 1;
773 		return (0);		/* complete */
774 	}
775 	if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
776 		return (1);		/* not complete */
777 	}
778 	count = td->max_frame_size;
779 	if (td->remainder < count) {
780 		/* we have a short packet */
781 		td->short_pkt = 1;
782 		count = td->remainder;
783 	}
784 	while (count > 0) {
785 		uint32_t temp;
786 
787 		usbd_get_page(td->pc, td->offset, &buf_res);
788 
789 		/* get correct length */
790 		if (buf_res.length > count) {
791 			buf_res.length = count;
792 		}
793 		/* check for unaligned memory address */
794 		if (USB_P2U(buf_res.buffer) & 3) {
795 
796 			usbd_copy_out(td->pc, td->offset,
797 			    sc->sc_bounce_buf, count);
798 
799 			temp = count & ~3;
800 
801 			if (temp) {
802 				/* transmit data 4 bytes at a time */
803 				bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
804 				    MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
805 				    temp / 4);
806 			}
807 			temp = count & 3;
808 			if (temp) {
809 				/* receive data 1 byte at a time */
810 				bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
811 				    MUSB2_REG_EPFIFO(0),
812 				    ((void *)&sc->sc_bounce_buf[count / 4]), temp);
813 			}
814 			/* update offset and remainder */
815 			td->offset += count;
816 			td->remainder -= count;
817 			break;
818 		}
819 		/* check if we can optimise */
820 		if (buf_res.length >= 4) {
821 
822 			/* transmit data 4 bytes at a time */
823 			bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
824 			    MUSB2_REG_EPFIFO(0), buf_res.buffer,
825 			    buf_res.length / 4);
826 
827 			temp = buf_res.length & ~3;
828 
829 			/* update counters */
830 			count -= temp;
831 			td->offset += temp;
832 			td->remainder -= temp;
833 			continue;
834 		}
835 		/* transmit data */
836 		bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
837 		    MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
838 
839 		/* update counters */
840 		count -= buf_res.length;
841 		td->offset += buf_res.length;
842 		td->remainder -= buf_res.length;
843 	}
844 
845 	/* check remainder */
846 	if (td->remainder == 0) {
847 		if (td->short_pkt) {
848 			sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY;
849 			return (0);	/* complete */
850 		}
851 		/* else we need to transmit a short packet */
852 	}
853 	/* write command */
854 	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
855 	    MUSB2_MASK_CSR0L_TXPKTRDY);
856 
857 	return (1);			/* not complete */
858 }
859 
860 static uint8_t
861 musbotg_host_ctrl_data_rx(struct musbotg_td *td)
862 {
863 	struct usb_page_search buf_res;
864 	struct musbotg_softc *sc;
865 	uint16_t count;
866 	uint8_t csr;
867 	uint8_t got_short;
868 
869 	/* get pointer to softc */
870 	sc = MUSBOTG_PC2SC(td->pc);
871 
872 	if (td->channel == -1)
873 		td->channel = musbotg_channel_alloc(sc, td);
874 
875 	/* EP0 is busy, wait */
876 	if (td->channel == -1)
877 		return (1);
878 
879 	DPRINTFN(1, "ep_no=%d\n", td->channel);
880 
881 	/* select endpoint 0 */
882 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
883 
884 	/* read out FIFO status */
885 	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
886 
887 	DPRINTFN(4, "csr=0x%02x\n", csr);
888 
889 	got_short = 0;
890 	if (!td->transaction_started) {
891 		td->transaction_started = 1;
892 
893 		MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
894 
895 		MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
896 		    td->dev_addr);
897 		MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
898 		MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
899 		MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
900 
901 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
902 		    MUSB2_MASK_CSR0L_REQPKT);
903 
904 		return (1);
905 	}
906 
907 	if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
908 		csr &= ~MUSB2_MASK_CSR0L_REQPKT;
909 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
910 
911 		csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
912 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
913 
914 		td->error = 1;
915 	}
916 
917 	/* Failed */
918 	if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
919 	    MUSB2_MASK_CSR0L_ERROR))
920 	{
921 		/* Clear status bit */
922 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
923 		DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
924 		td->error = 1;
925 	}
926 
927 	if (td->error) {
928 		musbotg_channel_free(sc, td);
929 		return (0);	/* we are complete */
930 	}
931 
932 	if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY))
933 		return (1); /* not yet */
934 
935 	/* get the packet byte count */
936 	count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
937 
938 	/* verify the packet byte count */
939 	if (count != td->max_frame_size) {
940 		if (count < td->max_frame_size) {
941 			/* we have a short packet */
942 			td->short_pkt = 1;
943 			got_short = 1;
944 		} else {
945 			/* invalid USB packet */
946 			td->error = 1;
947 			musbotg_channel_free(sc, td);
948 			return (0);	/* we are complete */
949 		}
950 	}
951 	/* verify the packet byte count */
952 	if (count > td->remainder) {
953 		/* invalid USB packet */
954 		td->error = 1;
955 		musbotg_channel_free(sc, td);
956 		return (0);		/* we are complete */
957 	}
958 	while (count > 0) {
959 		uint32_t temp;
960 
961 		usbd_get_page(td->pc, td->offset, &buf_res);
962 
963 		/* get correct length */
964 		if (buf_res.length > count) {
965 			buf_res.length = count;
966 		}
967 		/* check for unaligned memory address */
968 		if (USB_P2U(buf_res.buffer) & 3) {
969 
970 			temp = count & ~3;
971 
972 			if (temp) {
973 				/* receive data 4 bytes at a time */
974 				bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
975 				    MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
976 				    temp / 4);
977 			}
978 			temp = count & 3;
979 			if (temp) {
980 				/* receive data 1 byte at a time */
981 				bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
982 				    MUSB2_REG_EPFIFO(0),
983 				    (void *)(&sc->sc_bounce_buf[count / 4]), temp);
984 			}
985 			usbd_copy_in(td->pc, td->offset,
986 			    sc->sc_bounce_buf, count);
987 
988 			/* update offset and remainder */
989 			td->offset += count;
990 			td->remainder -= count;
991 			break;
992 		}
993 		/* check if we can optimise */
994 		if (buf_res.length >= 4) {
995 
996 			/* receive data 4 bytes at a time */
997 			bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
998 			    MUSB2_REG_EPFIFO(0), buf_res.buffer,
999 			    buf_res.length / 4);
1000 
1001 			temp = buf_res.length & ~3;
1002 
1003 			/* update counters */
1004 			count -= temp;
1005 			td->offset += temp;
1006 			td->remainder -= temp;
1007 			continue;
1008 		}
1009 		/* receive data */
1010 		bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1011 		    MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
1012 
1013 		/* update counters */
1014 		count -= buf_res.length;
1015 		td->offset += buf_res.length;
1016 		td->remainder -= buf_res.length;
1017 	}
1018 
1019 	csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY;
1020 	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1021 
1022 	/* check if we are complete */
1023 	if ((td->remainder == 0) || got_short) {
1024 		if (td->short_pkt) {
1025 			/* we are complete */
1026 
1027 			musbotg_channel_free(sc, td);
1028 			return (0);
1029 		}
1030 		/* else need to receive a zero length packet */
1031 	}
1032 
1033 	td->transaction_started = 1;
1034 	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1035 	    MUSB2_MASK_CSR0L_REQPKT);
1036 
1037 	return (1);			/* not complete */
1038 }
1039 
1040 static uint8_t
1041 musbotg_host_ctrl_data_tx(struct musbotg_td *td)
1042 {
1043 	struct usb_page_search buf_res;
1044 	struct musbotg_softc *sc;
1045 	uint16_t count;
1046 	uint8_t csr, csrh;
1047 
1048 	/* get pointer to softc */
1049 	sc = MUSBOTG_PC2SC(td->pc);
1050 
1051 	if (td->channel == -1)
1052 		td->channel = musbotg_channel_alloc(sc, td);
1053 
1054 	/* No free EPs */
1055 	if (td->channel == -1)
1056 		return (1);
1057 
1058 	DPRINTFN(1, "ep_no=%d\n", td->channel);
1059 
1060 	/* select endpoint */
1061 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1062 
1063 	/* read out FIFO status */
1064 	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1065 	DPRINTFN(4, "csr=0x%02x\n", csr);
1066 
1067 	if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1068 	    MUSB2_MASK_CSR0L_ERROR)) {
1069 		/* clear status bits */
1070 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1071 		td->error = 1;
1072 	}
1073 
1074 	if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) {
1075 
1076 		if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1077 			csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1078 			csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1079 			MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1080 			csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1081 			if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1082 				csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1083 				csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1084 				MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1085 				csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1086 			}
1087 		}
1088 
1089 		csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1090 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1091 
1092 		td->error = 1;
1093 	}
1094 
1095 
1096 	if (td->error) {
1097 		musbotg_channel_free(sc, td);
1098 		return (0);	/* complete */
1099 	}
1100 
1101 	/*
1102 	 * Wait while FIFO is empty.
1103 	 * Do not flush it because it will cause transactions
1104 	 * with size more then packet size. It might upset
1105 	 * some devices
1106 	 */
1107 	if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY)
1108 		return (1);
1109 
1110 	/* Packet still being processed */
1111 	if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1112 		return (1);
1113 
1114 	if (td->transaction_started) {
1115 		/* check remainder */
1116 		if (td->remainder == 0) {
1117 			if (td->short_pkt) {
1118 				musbotg_channel_free(sc, td);
1119 				return (0);	/* complete */
1120 			}
1121 			/* else we need to transmit a short packet */
1122 		}
1123 
1124 		/* We're not complete - more transactions required */
1125 		td->transaction_started = 0;
1126 	}
1127 
1128 	/* check for short packet */
1129 	count = td->max_frame_size;
1130 	if (td->remainder < count) {
1131 		/* we have a short packet */
1132 		td->short_pkt = 1;
1133 		count = td->remainder;
1134 	}
1135 
1136 	while (count > 0) {
1137 		uint32_t temp;
1138 
1139 		usbd_get_page(td->pc, td->offset, &buf_res);
1140 
1141 		/* get correct length */
1142 		if (buf_res.length > count) {
1143 			buf_res.length = count;
1144 		}
1145 		/* check for unaligned memory address */
1146 		if (USB_P2U(buf_res.buffer) & 3) {
1147 
1148 			usbd_copy_out(td->pc, td->offset,
1149 			    sc->sc_bounce_buf, count);
1150 
1151 			temp = count & ~3;
1152 
1153 			if (temp) {
1154 				/* transmit data 4 bytes at a time */
1155 				bus_space_write_multi_4(sc->sc_io_tag,
1156 				    sc->sc_io_hdl, MUSB2_REG_EPFIFO(0),
1157 				    sc->sc_bounce_buf, temp / 4);
1158 			}
1159 			temp = count & 3;
1160 			if (temp) {
1161 				/* receive data 1 byte at a time */
1162 				bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1163 				    MUSB2_REG_EPFIFO(0),
1164 				    ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1165 			}
1166 			/* update offset and remainder */
1167 			td->offset += count;
1168 			td->remainder -= count;
1169 			break;
1170 		}
1171 		/* check if we can optimise */
1172 		if (buf_res.length >= 4) {
1173 
1174 			/* transmit data 4 bytes at a time */
1175 			bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1176 			    MUSB2_REG_EPFIFO(0), buf_res.buffer,
1177 			    buf_res.length / 4);
1178 
1179 			temp = buf_res.length & ~3;
1180 
1181 			/* update counters */
1182 			count -= temp;
1183 			td->offset += temp;
1184 			td->remainder -= temp;
1185 			continue;
1186 		}
1187 		/* transmit data */
1188 		bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1189 		    MUSB2_REG_EPFIFO(0), buf_res.buffer,
1190 		    buf_res.length);
1191 
1192 		/* update counters */
1193 		count -= buf_res.length;
1194 		td->offset += buf_res.length;
1195 		td->remainder -= buf_res.length;
1196 	}
1197 
1198 	/* Function address */
1199 	MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1200 	MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1201 	MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1202 	MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1203 
1204 	/* TX NAK timeout */
1205 	MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1206 
1207 	/* write command */
1208 	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1209 	    MUSB2_MASK_CSR0L_TXPKTRDY);
1210 
1211 	td->transaction_started = 1;
1212 
1213 	return (1);			/* not complete */
1214 }
1215 
1216 static uint8_t
1217 musbotg_dev_ctrl_status(struct musbotg_td *td)
1218 {
1219 	struct musbotg_softc *sc;
1220 	uint8_t csr;
1221 
1222 	/* get pointer to softc */
1223 	sc = MUSBOTG_PC2SC(td->pc);
1224 
1225 	/* select endpoint 0 */
1226 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1227 
1228 	if (sc->sc_ep0_busy) {
1229 		sc->sc_ep0_busy = 0;
1230 		sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND;
1231 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
1232 		sc->sc_ep0_cmd = 0;
1233 	}
1234 	/* read out FIFO status */
1235 	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1236 
1237 	DPRINTFN(4, "csr=0x%02x\n", csr);
1238 
1239 	if (csr & MUSB2_MASK_CSR0L_DATAEND) {
1240 		/* wait for interrupt */
1241 		return (1);		/* not complete */
1242 	}
1243 	if (sc->sc_dv_addr != 0xFF) {
1244 		/* write function address */
1245 		musbotg_set_address(sc, sc->sc_dv_addr);
1246 	}
1247 
1248 	musbotg_channel_free(sc, td);
1249 	return (0);			/* complete */
1250 }
1251 
1252 static uint8_t
1253 musbotg_host_ctrl_status_rx(struct musbotg_td *td)
1254 {
1255 	struct musbotg_softc *sc;
1256 	uint8_t csr, csrh;
1257 
1258 	/* get pointer to softc */
1259 	sc = MUSBOTG_PC2SC(td->pc);
1260 
1261 	if (td->channel == -1)
1262 		td->channel = musbotg_channel_alloc(sc, td);
1263 
1264 	/* EP0 is busy, wait */
1265 	if (td->channel == -1)
1266 		return (1);
1267 
1268 	DPRINTFN(1, "ep_no=%d\n", td->channel);
1269 
1270 	/* select endpoint 0 */
1271 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1272 
1273 	if (!td->transaction_started) {
1274 		MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
1275 		    td->dev_addr);
1276 
1277 		MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
1278 		MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
1279 		MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1280 
1281 		/* RX NAK timeout */
1282 		MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1283 
1284 		td->transaction_started = 1;
1285 
1286 		/* Disable PING */
1287 		csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1288 		csrh |= MUSB2_MASK_CSR0H_PING_DIS;
1289 		MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1290 
1291 		/* write command */
1292 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1293 		    MUSB2_MASK_CSR0L_STATUSPKT |
1294 		    MUSB2_MASK_CSR0L_REQPKT);
1295 
1296 		return (1); /* Just started */
1297 
1298 	}
1299 
1300 	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1301 
1302 	DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr);
1303 
1304 	if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) {
1305 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1306 		    MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
1307 		musbotg_channel_free(sc, td);
1308 		return (0); /* complete */
1309 	}
1310 
1311 	if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
1312 		csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT |
1313 		    MUSB2_MASK_CSR0L_REQPKT);
1314 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1315 
1316 		csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1317 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1318 		td->error = 1;
1319 	}
1320 
1321 	/* Failed */
1322 	if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1323 	    MUSB2_MASK_CSR0L_ERROR))
1324 	{
1325 		/* Clear status bit */
1326 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1327 		DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1328 		td->error = 1;
1329 	}
1330 
1331 	if (td->error) {
1332 		musbotg_channel_free(sc, td);
1333 		return (0);
1334 	}
1335 
1336 	return (1);			/* Not ready yet */
1337 }
1338 
1339 static uint8_t
1340 musbotg_host_ctrl_status_tx(struct musbotg_td *td)
1341 {
1342 	struct musbotg_softc *sc;
1343 	uint8_t csr;
1344 
1345 	/* get pointer to softc */
1346 	sc = MUSBOTG_PC2SC(td->pc);
1347 
1348 	if (td->channel == -1)
1349 		td->channel = musbotg_channel_alloc(sc, td);
1350 
1351 	/* EP0 is busy, wait */
1352 	if (td->channel == -1)
1353 		return (1);
1354 
1355 	DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started,
1356 			td->dev_addr,td->haddr,td->hport, td->transfer_type);
1357 
1358 	/* select endpoint 0 */
1359 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1360 
1361 	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1362 	DPRINTFN(4, "csr=0x%02x\n", csr);
1363 
1364 	/* Not yet */
1365 	if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1366 		return (1);
1367 
1368 	/* Failed */
1369 	if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1370 	    MUSB2_MASK_CSR0L_ERROR))
1371 	{
1372 		/* Clear status bit */
1373 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1374 		DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1375 		td->error = 1;
1376 		musbotg_channel_free(sc, td);
1377 		return (0); /* complete */
1378 	}
1379 
1380 	if (td->transaction_started) {
1381 		musbotg_channel_free(sc, td);
1382 		return (0); /* complete */
1383 	}
1384 
1385 	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS);
1386 
1387 	MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1388 	MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1389 	MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1390 	MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1391 
1392 	/* TX NAK timeout */
1393 	MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1394 
1395 	td->transaction_started = 1;
1396 
1397 	/* write command */
1398 	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1399 	    MUSB2_MASK_CSR0L_STATUSPKT |
1400 	    MUSB2_MASK_CSR0L_TXPKTRDY);
1401 
1402 	return (1);			/* wait for interrupt */
1403 }
1404 
1405 static uint8_t
1406 musbotg_dev_data_rx(struct musbotg_td *td)
1407 {
1408 	struct usb_page_search buf_res;
1409 	struct musbotg_softc *sc;
1410 	uint16_t count;
1411 	uint8_t csr;
1412 	uint8_t to;
1413 	uint8_t got_short;
1414 
1415 	to = 8;				/* don't loop forever! */
1416 	got_short = 0;
1417 
1418 	/* get pointer to softc */
1419 	sc = MUSBOTG_PC2SC(td->pc);
1420 
1421 	if (td->channel == -1)
1422 		td->channel = musbotg_channel_alloc(sc, td);
1423 
1424 	/* EP0 is busy, wait */
1425 	if (td->channel == -1)
1426 		return (1);
1427 
1428 	/* select endpoint */
1429 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1430 
1431 repeat:
1432 	/* read out FIFO status */
1433 	csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1434 
1435 	DPRINTFN(4, "csr=0x%02x\n", csr);
1436 
1437 	/* clear overrun */
1438 	if (csr & MUSB2_MASK_CSRL_RXOVERRUN) {
1439 		/* make sure we don't clear "RXPKTRDY" */
1440 		MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1441 		    MUSB2_MASK_CSRL_RXPKTRDY);
1442 	}
1443 
1444 	/* check status */
1445 	if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY))
1446 		return (1); /* not complete */
1447 
1448 	/* get the packet byte count */
1449 	count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1450 
1451 	DPRINTFN(4, "count=0x%04x\n", count);
1452 
1453 	/*
1454 	 * Check for short or invalid packet:
1455 	 */
1456 	if (count != td->max_frame_size) {
1457 		if (count < td->max_frame_size) {
1458 			/* we have a short packet */
1459 			td->short_pkt = 1;
1460 			got_short = 1;
1461 		} else {
1462 			/* invalid USB packet */
1463 			td->error = 1;
1464 			musbotg_channel_free(sc, td);
1465 			return (0);	/* we are complete */
1466 		}
1467 	}
1468 	/* verify the packet byte count */
1469 	if (count > td->remainder) {
1470 		/* invalid USB packet */
1471 		td->error = 1;
1472 		musbotg_channel_free(sc, td);
1473 		return (0);		/* we are complete */
1474 	}
1475 	while (count > 0) {
1476 		uint32_t temp;
1477 
1478 		usbd_get_page(td->pc, td->offset, &buf_res);
1479 
1480 		/* get correct length */
1481 		if (buf_res.length > count) {
1482 			buf_res.length = count;
1483 		}
1484 		/* check for unaligned memory address */
1485 		if (USB_P2U(buf_res.buffer) & 3) {
1486 
1487 			temp = count & ~3;
1488 
1489 			if (temp) {
1490 				/* receive data 4 bytes at a time */
1491 				bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1492 				    MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1493 				    temp / 4);
1494 			}
1495 			temp = count & 3;
1496 			if (temp) {
1497 				/* receive data 1 byte at a time */
1498 				bus_space_read_multi_1(sc->sc_io_tag,
1499 				    sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1500 				    ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1501 			}
1502 			usbd_copy_in(td->pc, td->offset,
1503 			    sc->sc_bounce_buf, count);
1504 
1505 			/* update offset and remainder */
1506 			td->offset += count;
1507 			td->remainder -= count;
1508 			break;
1509 		}
1510 		/* check if we can optimise */
1511 		if (buf_res.length >= 4) {
1512 
1513 			/* receive data 4 bytes at a time */
1514 			bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1515 			    MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1516 			    buf_res.length / 4);
1517 
1518 			temp = buf_res.length & ~3;
1519 
1520 			/* update counters */
1521 			count -= temp;
1522 			td->offset += temp;
1523 			td->remainder -= temp;
1524 			continue;
1525 		}
1526 		/* receive data */
1527 		bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1528 		    MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1529 		    buf_res.length);
1530 
1531 		/* update counters */
1532 		count -= buf_res.length;
1533 		td->offset += buf_res.length;
1534 		td->remainder -= buf_res.length;
1535 	}
1536 
1537 	/* clear status bits */
1538 	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1539 
1540 	/* check if we are complete */
1541 	if ((td->remainder == 0) || got_short) {
1542 		if (td->short_pkt) {
1543 			/* we are complete */
1544 			musbotg_channel_free(sc, td);
1545 			return (0);
1546 		}
1547 		/* else need to receive a zero length packet */
1548 	}
1549 	if (--to) {
1550 		goto repeat;
1551 	}
1552 	return (1);			/* not complete */
1553 }
1554 
1555 static uint8_t
1556 musbotg_dev_data_tx(struct musbotg_td *td)
1557 {
1558 	struct usb_page_search buf_res;
1559 	struct musbotg_softc *sc;
1560 	uint16_t count;
1561 	uint8_t csr;
1562 	uint8_t to;
1563 
1564 	to = 8;				/* don't loop forever! */
1565 
1566 	/* get pointer to softc */
1567 	sc = MUSBOTG_PC2SC(td->pc);
1568 
1569 	if (td->channel == -1)
1570 		td->channel = musbotg_channel_alloc(sc, td);
1571 
1572 	/* EP0 is busy, wait */
1573 	if (td->channel == -1)
1574 		return (1);
1575 
1576 	/* select endpoint */
1577 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1578 
1579 repeat:
1580 
1581 	/* read out FIFO status */
1582 	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1583 
1584 	DPRINTFN(4, "csr=0x%02x\n", csr);
1585 
1586 	if (csr & (MUSB2_MASK_CSRL_TXINCOMP |
1587 	    MUSB2_MASK_CSRL_TXUNDERRUN)) {
1588 		/* clear status bits */
1589 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1590 	}
1591 	if (csr & MUSB2_MASK_CSRL_TXPKTRDY) {
1592 		return (1);		/* not complete */
1593 	}
1594 	/* check for short packet */
1595 	count = td->max_frame_size;
1596 	if (td->remainder < count) {
1597 		/* we have a short packet */
1598 		td->short_pkt = 1;
1599 		count = td->remainder;
1600 	}
1601 	while (count > 0) {
1602 		uint32_t temp;
1603 
1604 		usbd_get_page(td->pc, td->offset, &buf_res);
1605 
1606 		/* get correct length */
1607 		if (buf_res.length > count) {
1608 			buf_res.length = count;
1609 		}
1610 		/* check for unaligned memory address */
1611 		if (USB_P2U(buf_res.buffer) & 3) {
1612 
1613 			usbd_copy_out(td->pc, td->offset,
1614 			    sc->sc_bounce_buf, count);
1615 
1616 			temp = count & ~3;
1617 
1618 			if (temp) {
1619 				/* transmit data 4 bytes at a time */
1620 				bus_space_write_multi_4(sc->sc_io_tag,
1621 				    sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1622 				    sc->sc_bounce_buf, temp / 4);
1623 			}
1624 			temp = count & 3;
1625 			if (temp) {
1626 				/* receive data 1 byte at a time */
1627 				bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1628 				    MUSB2_REG_EPFIFO(td->channel),
1629 				    ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1630 			}
1631 			/* update offset and remainder */
1632 			td->offset += count;
1633 			td->remainder -= count;
1634 			break;
1635 		}
1636 		/* check if we can optimise */
1637 		if (buf_res.length >= 4) {
1638 
1639 			/* transmit data 4 bytes at a time */
1640 			bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1641 			    MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1642 			    buf_res.length / 4);
1643 
1644 			temp = buf_res.length & ~3;
1645 
1646 			/* update counters */
1647 			count -= temp;
1648 			td->offset += temp;
1649 			td->remainder -= temp;
1650 			continue;
1651 		}
1652 		/* transmit data */
1653 		bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1654 		    MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1655 		    buf_res.length);
1656 
1657 		/* update counters */
1658 		count -= buf_res.length;
1659 		td->offset += buf_res.length;
1660 		td->remainder -= buf_res.length;
1661 	}
1662 
1663 	/* Max packet size */
1664 	MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
1665 
1666 	/* write command */
1667 	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1668 	    MUSB2_MASK_CSRL_TXPKTRDY);
1669 
1670 	/* check remainder */
1671 	if (td->remainder == 0) {
1672 		if (td->short_pkt) {
1673 			musbotg_channel_free(sc, td);
1674 			return (0);	/* complete */
1675 		}
1676 		/* else we need to transmit a short packet */
1677 	}
1678 	if (--to) {
1679 		goto repeat;
1680 	}
1681 	return (1);			/* not complete */
1682 }
1683 
1684 static uint8_t
1685 musbotg_host_data_rx(struct musbotg_td *td)
1686 {
1687 	struct usb_page_search buf_res;
1688 	struct musbotg_softc *sc;
1689 	uint16_t count;
1690 	uint8_t csr, csrh;
1691 	uint8_t to;
1692 	uint8_t got_short;
1693 
1694 	/* get pointer to softc */
1695 	sc = MUSBOTG_PC2SC(td->pc);
1696 
1697 	if (td->channel == -1)
1698 		td->channel = musbotg_channel_alloc(sc, td);
1699 
1700 	/* No free EPs */
1701 	if (td->channel == -1)
1702 		return (1);
1703 
1704 	DPRINTFN(1, "ep_no=%d\n", td->channel);
1705 
1706 	to = 8;				/* don't loop forever! */
1707 	got_short = 0;
1708 
1709 	/* select endpoint */
1710 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1711 
1712 repeat:
1713 	/* read out FIFO status */
1714 	csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1715 	DPRINTFN(4, "csr=0x%02x\n", csr);
1716 
1717 	if (!td->transaction_started) {
1718 		/* Function address */
1719 		MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel),
1720 		    td->dev_addr);
1721 
1722 		/* SPLIT transaction */
1723 		MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel),
1724 		    td->haddr);
1725 		MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel),
1726 		    td->hport);
1727 
1728 		/* RX NAK timeout */
1729 		if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
1730 			MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0);
1731 		else
1732 			MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1733 
1734 		/* Protocol, speed, device endpoint */
1735 		MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1736 
1737 		/* Max packet size */
1738 		MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet);
1739 
1740 		/* Data Toggle */
1741 		csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1742 		DPRINTFN(4, "csrh=0x%02x\n", csrh);
1743 
1744 		csrh |= MUSB2_MASK_CSRH_RXDT_WREN;
1745 		if (td->toggle)
1746 			csrh |= MUSB2_MASK_CSRH_RXDT_VAL;
1747 		else
1748 			csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL;
1749 
1750 		/* Set data toggle */
1751 		MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1752 
1753 		/* write command */
1754 		MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1755 		    MUSB2_MASK_CSRL_RXREQPKT);
1756 
1757 		td->transaction_started = 1;
1758 		return (1);
1759 	}
1760 
1761 	/* clear NAK timeout */
1762 	if (csr & MUSB2_MASK_CSRL_RXNAKTO) {
1763 		DPRINTFN(4, "NAK Timeout\n");
1764 		if (csr & MUSB2_MASK_CSRL_RXREQPKT) {
1765 			csr &= ~MUSB2_MASK_CSRL_RXREQPKT;
1766 			MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1767 
1768 			csr &= ~MUSB2_MASK_CSRL_RXNAKTO;
1769 			MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1770 		}
1771 
1772 		td->error = 1;
1773 	}
1774 
1775 	if (csr & MUSB2_MASK_CSRL_RXERROR) {
1776 		DPRINTFN(4, "RXERROR\n");
1777 		td->error = 1;
1778 	}
1779 
1780 	if (csr & MUSB2_MASK_CSRL_RXSTALL) {
1781 		DPRINTFN(4, "RXSTALL\n");
1782 		td->error = 1;
1783 	}
1784 
1785 	if (td->error) {
1786 		musbotg_channel_free(sc, td);
1787 		return (0);	/* we are complete */
1788 	}
1789 
1790 	if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) {
1791 		/* No data available yet */
1792 		return (1);
1793 	}
1794 
1795 	td->toggle ^= 1;
1796 	/* get the packet byte count */
1797 	count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1798 	DPRINTFN(4, "count=0x%04x\n", count);
1799 
1800 	/*
1801 	 * Check for short or invalid packet:
1802 	 */
1803 	if (count != td->max_frame_size) {
1804 		if (count < td->max_frame_size) {
1805 			/* we have a short packet */
1806 			td->short_pkt = 1;
1807 			got_short = 1;
1808 		} else {
1809 			/* invalid USB packet */
1810 			td->error = 1;
1811 			musbotg_channel_free(sc, td);
1812 			return (0);	/* we are complete */
1813 		}
1814 	}
1815 
1816 	/* verify the packet byte count */
1817 	if (count > td->remainder) {
1818 		/* invalid USB packet */
1819 		td->error = 1;
1820 		musbotg_channel_free(sc, td);
1821 		return (0);		/* we are complete */
1822 	}
1823 
1824 	while (count > 0) {
1825 		uint32_t temp;
1826 
1827 		usbd_get_page(td->pc, td->offset, &buf_res);
1828 
1829 		/* get correct length */
1830 		if (buf_res.length > count) {
1831 			buf_res.length = count;
1832 		}
1833 		/* check for unaligned memory address */
1834 		if (USB_P2U(buf_res.buffer) & 3) {
1835 
1836 			temp = count & ~3;
1837 
1838 			if (temp) {
1839 				/* receive data 4 bytes at a time */
1840 				bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1841 				    MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1842 				    temp / 4);
1843 			}
1844 			temp = count & 3;
1845 			if (temp) {
1846 				/* receive data 1 byte at a time */
1847 				bus_space_read_multi_1(sc->sc_io_tag,
1848 				    sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1849 				    ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1850 			}
1851 			usbd_copy_in(td->pc, td->offset,
1852 			    sc->sc_bounce_buf, count);
1853 
1854 			/* update offset and remainder */
1855 			td->offset += count;
1856 			td->remainder -= count;
1857 			break;
1858 		}
1859 		/* check if we can optimise */
1860 		if (buf_res.length >= 4) {
1861 
1862 			/* receive data 4 bytes at a time */
1863 			bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1864 			    MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1865 			    buf_res.length / 4);
1866 
1867 			temp = buf_res.length & ~3;
1868 
1869 			/* update counters */
1870 			count -= temp;
1871 			td->offset += temp;
1872 			td->remainder -= temp;
1873 			continue;
1874 		}
1875 		/* receive data */
1876 		bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1877 		    MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1878 		    buf_res.length);
1879 
1880 		/* update counters */
1881 		count -= buf_res.length;
1882 		td->offset += buf_res.length;
1883 		td->remainder -= buf_res.length;
1884 	}
1885 
1886 	/* clear status bits */
1887 	MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1888 
1889 	/* check if we are complete */
1890 	if ((td->remainder == 0) || got_short) {
1891 		if (td->short_pkt) {
1892 			/* we are complete */
1893 			musbotg_channel_free(sc, td);
1894 			return (0);
1895 		}
1896 		/* else need to receive a zero length packet */
1897 	}
1898 
1899 	/* Reset transaction state and restart */
1900 	td->transaction_started = 0;
1901 
1902 	if (--to)
1903 		goto repeat;
1904 
1905 	return (1);			/* not complete */
1906 }
1907 
1908 static uint8_t
1909 musbotg_host_data_tx(struct musbotg_td *td)
1910 {
1911 	struct usb_page_search buf_res;
1912 	struct musbotg_softc *sc;
1913 	uint16_t count;
1914 	uint8_t csr, csrh;
1915 
1916 	/* get pointer to softc */
1917 	sc = MUSBOTG_PC2SC(td->pc);
1918 
1919 	if (td->channel == -1)
1920 		td->channel = musbotg_channel_alloc(sc, td);
1921 
1922 	/* No free EPs */
1923 	if (td->channel == -1)
1924 		return (1);
1925 
1926 	DPRINTFN(1, "ep_no=%d\n", td->channel);
1927 
1928 	/* select endpoint */
1929 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1930 
1931 	/* read out FIFO status */
1932 	csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1933 	DPRINTFN(4, "csr=0x%02x\n", csr);
1934 
1935 	if (csr & (MUSB2_MASK_CSRL_TXSTALLED |
1936 	    MUSB2_MASK_CSRL_TXERROR)) {
1937 		/* clear status bits */
1938 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1939 		td->error = 1;
1940 		musbotg_channel_free(sc, td);
1941 		return (0);	/* complete */
1942 	}
1943 
1944 	if (csr & MUSB2_MASK_CSRL_TXNAKTO) {
1945 		/*
1946 		 * Flush TX FIFO before clearing NAK TO
1947 		 */
1948 		if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1949 			csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1950 			MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1951 			csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1952 			if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1953 				csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1954 				MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1955 				csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1956 			}
1957 		}
1958 
1959 		csr &= ~MUSB2_MASK_CSRL_TXNAKTO;
1960 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1961 
1962 		td->error = 1;
1963 		musbotg_channel_free(sc, td);
1964 		return (0);	/* complete */
1965 	}
1966 
1967 	/*
1968 	 * Wait while FIFO is empty.
1969 	 * Do not flush it because it will cause transactions
1970 	 * with size more then packet size. It might upset
1971 	 * some devices
1972 	 */
1973 	if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY)
1974 		return (1);
1975 
1976 	/* Packet still being processed */
1977 	if (csr & MUSB2_MASK_CSRL_TXPKTRDY)
1978 		return (1);
1979 
1980 	if (td->transaction_started) {
1981 		/* check remainder */
1982 		if (td->remainder == 0) {
1983 			if (td->short_pkt) {
1984 				musbotg_channel_free(sc, td);
1985 				return (0);	/* complete */
1986 			}
1987 			/* else we need to transmit a short packet */
1988 		}
1989 
1990 		/* We're not complete - more transactions required */
1991 		td->transaction_started = 0;
1992 	}
1993 
1994 	/* check for short packet */
1995 	count = td->max_frame_size;
1996 	if (td->remainder < count) {
1997 		/* we have a short packet */
1998 		td->short_pkt = 1;
1999 		count = td->remainder;
2000 	}
2001 
2002 	while (count > 0) {
2003 		uint32_t temp;
2004 
2005 		usbd_get_page(td->pc, td->offset, &buf_res);
2006 
2007 		/* get correct length */
2008 		if (buf_res.length > count) {
2009 			buf_res.length = count;
2010 		}
2011 		/* check for unaligned memory address */
2012 		if (USB_P2U(buf_res.buffer) & 3) {
2013 
2014 			usbd_copy_out(td->pc, td->offset,
2015 			    sc->sc_bounce_buf, count);
2016 
2017 			temp = count & ~3;
2018 
2019 			if (temp) {
2020 				/* transmit data 4 bytes at a time */
2021 				bus_space_write_multi_4(sc->sc_io_tag,
2022 				    sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
2023 				    sc->sc_bounce_buf, temp / 4);
2024 			}
2025 			temp = count & 3;
2026 			if (temp) {
2027 				/* receive data 1 byte at a time */
2028 				bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2029 				    MUSB2_REG_EPFIFO(td->channel),
2030 				    ((void *)&sc->sc_bounce_buf[count / 4]), temp);
2031 			}
2032 			/* update offset and remainder */
2033 			td->offset += count;
2034 			td->remainder -= count;
2035 			break;
2036 		}
2037 		/* check if we can optimise */
2038 		if (buf_res.length >= 4) {
2039 
2040 			/* transmit data 4 bytes at a time */
2041 			bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
2042 			    MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2043 			    buf_res.length / 4);
2044 
2045 			temp = buf_res.length & ~3;
2046 
2047 			/* update counters */
2048 			count -= temp;
2049 			td->offset += temp;
2050 			td->remainder -= temp;
2051 			continue;
2052 		}
2053 		/* transmit data */
2054 		bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2055 		    MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2056 		    buf_res.length);
2057 
2058 		/* update counters */
2059 		count -= buf_res.length;
2060 		td->offset += buf_res.length;
2061 		td->remainder -= buf_res.length;
2062 	}
2063 
2064 	/* Function address */
2065 	MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel),
2066 	    td->dev_addr);
2067 
2068 	/* SPLIT transaction */
2069 	MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel),
2070 	    td->haddr);
2071 	MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel),
2072 	    td->hport);
2073 
2074 	/* TX NAK timeout */
2075 	if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
2076 		MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0);
2077 	else
2078 		MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
2079 
2080 	/* Protocol, speed, device endpoint */
2081 	MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
2082 
2083 	/* Max packet size */
2084 	MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
2085 
2086 	if (!td->transaction_started) {
2087 		csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
2088 		DPRINTFN(4, "csrh=0x%02x\n", csrh);
2089 
2090 		csrh |= MUSB2_MASK_CSRH_TXDT_WREN;
2091 		if (td->toggle)
2092 			csrh |= MUSB2_MASK_CSRH_TXDT_VAL;
2093 		else
2094 			csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL;
2095 
2096 		/* Set data toggle */
2097 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
2098 	}
2099 
2100 	/* write command */
2101 	MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2102 	    MUSB2_MASK_CSRL_TXPKTRDY);
2103 
2104 	/* Update Data Toggle */
2105 	td->toggle ^= 1;
2106 	td->transaction_started = 1;
2107 
2108 	return (1);			/* not complete */
2109 }
2110 
2111 static uint8_t
2112 musbotg_xfer_do_fifo(struct usb_xfer *xfer)
2113 {
2114 	struct musbotg_softc *sc;
2115 	struct musbotg_td *td;
2116 
2117 	DPRINTFN(8, "\n");
2118 	sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2119 
2120 	td = xfer->td_transfer_cache;
2121 	while (1) {
2122 
2123 		if ((td->func) (td)) {
2124 			/* operation in progress */
2125 			break;
2126 		}
2127 
2128 		if (((void *)td) == xfer->td_transfer_last) {
2129 			goto done;
2130 		}
2131 		if (td->error) {
2132 			goto done;
2133 		} else if (td->remainder > 0) {
2134 			/*
2135 			 * We had a short transfer. If there is no alternate
2136 			 * next, stop processing !
2137 			 */
2138 			if (!td->alt_next) {
2139 				goto done;
2140 			}
2141 		}
2142 		/*
2143 		 * Fetch the next transfer descriptor and transfer
2144 		 * some flags to the next transfer descriptor
2145 		 */
2146 		td = td->obj_next;
2147 		xfer->td_transfer_cache = td;
2148 	}
2149 
2150 	return (1);			/* not complete */
2151 done:
2152 	/* compute all actual lengths */
2153 	musbotg_standard_done(xfer);
2154 
2155 	return (0);			/* complete */
2156 }
2157 
2158 static void
2159 musbotg_interrupt_poll(struct musbotg_softc *sc)
2160 {
2161 	struct usb_xfer *xfer;
2162 
2163 repeat:
2164 	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2165 		if (!musbotg_xfer_do_fifo(xfer)) {
2166 			/* queue has been modified */
2167 			goto repeat;
2168 		}
2169 	}
2170 }
2171 
2172 void
2173 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
2174 {
2175 	DPRINTFN(4, "vbus = %u\n", is_on);
2176 
2177 	USB_BUS_LOCK(&sc->sc_bus);
2178 	if (is_on) {
2179 		if (!sc->sc_flags.status_vbus) {
2180 			sc->sc_flags.status_vbus = 1;
2181 
2182 			/* complete root HUB interrupt endpoint */
2183 			musbotg_root_intr(sc);
2184 		}
2185 	} else {
2186 		if (sc->sc_flags.status_vbus) {
2187 			sc->sc_flags.status_vbus = 0;
2188 			sc->sc_flags.status_bus_reset = 0;
2189 			sc->sc_flags.status_suspend = 0;
2190 			sc->sc_flags.change_suspend = 0;
2191 			sc->sc_flags.change_connect = 1;
2192 
2193 			/* complete root HUB interrupt endpoint */
2194 			musbotg_root_intr(sc);
2195 		}
2196 	}
2197 
2198 	USB_BUS_UNLOCK(&sc->sc_bus);
2199 }
2200 
2201 void
2202 musbotg_connect_interrupt(struct musbotg_softc *sc)
2203 {
2204 	USB_BUS_LOCK(&sc->sc_bus);
2205 	sc->sc_flags.change_connect = 1;
2206 
2207 	/* complete root HUB interrupt endpoint */
2208 	musbotg_root_intr(sc);
2209 	USB_BUS_UNLOCK(&sc->sc_bus);
2210 }
2211 
2212 void
2213 musbotg_interrupt(struct musbotg_softc *sc,
2214     uint16_t rxstat, uint16_t txstat, uint8_t stat)
2215 {
2216 	uint16_t rx_status;
2217 	uint16_t tx_status;
2218 	uint8_t usb_status;
2219 	uint8_t temp;
2220 	uint8_t to = 2;
2221 
2222 	USB_BUS_LOCK(&sc->sc_bus);
2223 
2224 repeat:
2225 
2226 	/* read all interrupt registers */
2227 	usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB);
2228 
2229 	/* read all FIFO interrupts */
2230 	rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX);
2231 	tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX);
2232 	rx_status |= rxstat;
2233 	tx_status |= txstat;
2234 	usb_status |= stat;
2235 
2236 	/* Clear platform flags after first time */
2237 	rxstat = 0;
2238 	txstat = 0;
2239 	stat = 0;
2240 
2241 	/* check for any bus state change interrupts */
2242 
2243 	if (usb_status & (MUSB2_MASK_IRESET |
2244 	    MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP |
2245 	    MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) {
2246 
2247 		DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status);
2248 
2249 		if (usb_status & MUSB2_MASK_IRESET) {
2250 
2251 			/* set correct state */
2252 			sc->sc_flags.status_bus_reset = 1;
2253 			sc->sc_flags.status_suspend = 0;
2254 			sc->sc_flags.change_suspend = 0;
2255 			sc->sc_flags.change_connect = 1;
2256 
2257 			/* determine line speed */
2258 			temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
2259 			if (temp & MUSB2_MASK_HSMODE)
2260 				sc->sc_flags.status_high_speed = 1;
2261 			else
2262 				sc->sc_flags.status_high_speed = 0;
2263 
2264 			/*
2265 			 * After reset all interrupts are on and we need to
2266 			 * turn them off!
2267 			 */
2268 			temp = MUSB2_MASK_IRESET;
2269 			/* disable resume interrupt */
2270 			temp &= ~MUSB2_MASK_IRESUME;
2271 			/* enable suspend interrupt */
2272 			temp |= MUSB2_MASK_ISUSP;
2273 			MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2274 			/* disable TX and RX interrupts */
2275 			MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
2276 			MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
2277 		}
2278 		/*
2279 	         * If RXRSM and RXSUSP is set at the same time we interpret
2280 	         * that like RESUME. Resume is set when there is at least 3
2281 	         * milliseconds of inactivity on the USB BUS.
2282 	         */
2283 		if (usb_status & MUSB2_MASK_IRESUME) {
2284 			if (sc->sc_flags.status_suspend) {
2285 				sc->sc_flags.status_suspend = 0;
2286 				sc->sc_flags.change_suspend = 1;
2287 
2288 				temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2289 				/* disable resume interrupt */
2290 				temp &= ~MUSB2_MASK_IRESUME;
2291 				/* enable suspend interrupt */
2292 				temp |= MUSB2_MASK_ISUSP;
2293 				MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2294 			}
2295 		} else if (usb_status & MUSB2_MASK_ISUSP) {
2296 			if (!sc->sc_flags.status_suspend) {
2297 				sc->sc_flags.status_suspend = 1;
2298 				sc->sc_flags.change_suspend = 1;
2299 
2300 				temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2301 				/* disable suspend interrupt */
2302 				temp &= ~MUSB2_MASK_ISUSP;
2303 				/* enable resume interrupt */
2304 				temp |= MUSB2_MASK_IRESUME;
2305 				MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2306 			}
2307 		}
2308 		if (usb_status &
2309 		    (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC))
2310 			sc->sc_flags.change_connect = 1;
2311 
2312 		/*
2313 		 * Host Mode: There is no IRESET so assume bus is
2314 		 * always in reset state once device is connected.
2315 		 */
2316 		if (sc->sc_mode == MUSB2_HOST_MODE) {
2317 		    if (usb_status & MUSB2_MASK_ICONN)
2318 			sc->sc_flags.status_bus_reset = 1;
2319 		    if (usb_status & MUSB2_MASK_IDISC)
2320 			sc->sc_flags.status_bus_reset = 0;
2321 		}
2322 
2323 		/* complete root HUB interrupt endpoint */
2324 		musbotg_root_intr(sc);
2325 	}
2326 	/* check for any endpoint interrupts */
2327 
2328 	if (rx_status || tx_status) {
2329 		DPRINTFN(4, "real endpoint interrupt "
2330 		    "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status);
2331 	}
2332 	/* poll one time regardless of FIFO status */
2333 
2334 	musbotg_interrupt_poll(sc);
2335 
2336 	if (--to)
2337 		goto repeat;
2338 
2339 	USB_BUS_UNLOCK(&sc->sc_bus);
2340 }
2341 
2342 static void
2343 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp)
2344 {
2345 	struct musbotg_td *td;
2346 
2347 	/* get current Transfer Descriptor */
2348 	td = temp->td_next;
2349 	temp->td = td;
2350 
2351 	/* prepare for next TD */
2352 	temp->td_next = td->obj_next;
2353 
2354 	/* fill out the Transfer Descriptor */
2355 	td->func = temp->func;
2356 	td->pc = temp->pc;
2357 	td->offset = temp->offset;
2358 	td->remainder = temp->len;
2359 	td->error = 0;
2360 	td->transaction_started = 0;
2361 	td->did_stall = temp->did_stall;
2362 	td->short_pkt = temp->short_pkt;
2363 	td->alt_next = temp->setup_alt_next;
2364 	td->channel = temp->channel;
2365 	td->dev_addr = temp->dev_addr;
2366 	td->haddr = temp->haddr;
2367 	td->hport = temp->hport;
2368 	td->transfer_type = temp->transfer_type;
2369 }
2370 
2371 static void
2372 musbotg_setup_standard_chain(struct usb_xfer *xfer)
2373 {
2374 	struct musbotg_std_temp temp;
2375 	struct musbotg_softc *sc;
2376 	struct musbotg_td *td;
2377 	uint32_t x;
2378 	uint8_t ep_no;
2379 	uint8_t xfer_type;
2380 	enum usb_dev_speed speed;
2381 	int tx;
2382 	int dev_addr;
2383 
2384 	DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n",
2385 	    xfer->address, UE_GET_ADDR(xfer->endpointno),
2386 	    xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
2387 
2388 	sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2389 	ep_no = (xfer->endpointno & UE_ADDR);
2390 
2391 	temp.max_frame_size = xfer->max_frame_size;
2392 
2393 	td = xfer->td_start[0];
2394 	xfer->td_transfer_first = td;
2395 	xfer->td_transfer_cache = td;
2396 
2397 	/* setup temp */
2398 	dev_addr = xfer->address;
2399 
2400 	xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE;
2401 
2402 	temp.pc = NULL;
2403 	temp.td = NULL;
2404 	temp.td_next = xfer->td_start[0];
2405 	temp.offset = 0;
2406 	temp.setup_alt_next = xfer->flags_int.short_frames_ok;
2407 	temp.did_stall = !xfer->flags_int.control_stall;
2408 	temp.channel = -1;
2409 	temp.dev_addr = dev_addr;
2410 	temp.haddr = xfer->xroot->udev->hs_hub_addr;
2411 	temp.hport = xfer->xroot->udev->hs_port_no;
2412 
2413 	if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2414 		speed =  usbd_get_speed(xfer->xroot->udev);
2415 
2416 		switch (speed) {
2417 			case USB_SPEED_LOW:
2418 				temp.transfer_type = MUSB2_MASK_TI_SPEED_LO;
2419 				break;
2420 			case USB_SPEED_FULL:
2421 				temp.transfer_type = MUSB2_MASK_TI_SPEED_FS;
2422 				break;
2423 			case USB_SPEED_HIGH:
2424 				temp.transfer_type = MUSB2_MASK_TI_SPEED_HS;
2425 				break;
2426 			default:
2427 				temp.transfer_type = 0;
2428 				DPRINTFN(-1, "Invalid USB speed: %d\n", speed);
2429 				break;
2430 		}
2431 
2432 		switch (xfer_type) {
2433 			case UE_CONTROL:
2434 				temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL;
2435 				break;
2436 			case UE_ISOCHRONOUS:
2437 				temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC;
2438 				break;
2439 			case UE_BULK:
2440 				temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK;
2441 				break;
2442 			case UE_INTERRUPT:
2443 				temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR;
2444 				break;
2445 			default:
2446 				DPRINTFN(-1, "Invalid USB transfer type: %d\n",
2447 						xfer_type);
2448 				break;
2449 		}
2450 
2451 		temp.transfer_type |= ep_no;
2452 		td->toggle = xfer->endpoint->toggle_next;
2453 	}
2454 
2455 	/* check if we should prepend a setup message */
2456 
2457 	if (xfer->flags_int.control_xfr) {
2458 		if (xfer->flags_int.control_hdr) {
2459 
2460 			if (xfer->flags_int.usb_mode == USB_MODE_DEVICE)
2461 				temp.func = &musbotg_dev_ctrl_setup_rx;
2462 			else
2463 				temp.func = &musbotg_host_ctrl_setup_tx;
2464 
2465 			temp.len = xfer->frlengths[0];
2466 			temp.pc = xfer->frbuffers + 0;
2467 			temp.short_pkt = temp.len ? 1 : 0;
2468 
2469 			musbotg_setup_standard_chain_sub(&temp);
2470 		}
2471 		x = 1;
2472 	} else {
2473 		x = 0;
2474 	}
2475 
2476 	tx = 0;
2477 
2478 	if (x != xfer->nframes) {
2479 		if (xfer->endpointno & UE_DIR_IN)
2480 		    	tx = 1;
2481 
2482 		if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2483 			tx = !tx;
2484 
2485 			if (tx) {
2486 				if (xfer->flags_int.control_xfr)
2487 					temp.func = &musbotg_host_ctrl_data_tx;
2488 				else
2489 					temp.func = &musbotg_host_data_tx;
2490 			} else {
2491 				if (xfer->flags_int.control_xfr)
2492 					temp.func = &musbotg_host_ctrl_data_rx;
2493 				else
2494 					temp.func = &musbotg_host_data_rx;
2495 			}
2496 
2497 		} else {
2498 			if (tx) {
2499 				if (xfer->flags_int.control_xfr)
2500 					temp.func = &musbotg_dev_ctrl_data_tx;
2501 				else
2502 					temp.func = &musbotg_dev_data_tx;
2503 			} else {
2504 				if (xfer->flags_int.control_xfr)
2505 					temp.func = &musbotg_dev_ctrl_data_rx;
2506 				else
2507 					temp.func = &musbotg_dev_data_rx;
2508 			}
2509 		}
2510 
2511 		/* setup "pc" pointer */
2512 		temp.pc = xfer->frbuffers + x;
2513 	}
2514 	while (x != xfer->nframes) {
2515 
2516 		/* DATA0 / DATA1 message */
2517 
2518 		temp.len = xfer->frlengths[x];
2519 
2520 		x++;
2521 
2522 		if (x == xfer->nframes) {
2523 			if (xfer->flags_int.control_xfr) {
2524 				if (xfer->flags_int.control_act) {
2525 					temp.setup_alt_next = 0;
2526 				}
2527 			} else {
2528 				temp.setup_alt_next = 0;
2529 			}
2530 		}
2531 		if (temp.len == 0) {
2532 
2533 			/* make sure that we send an USB packet */
2534 
2535 			temp.short_pkt = 0;
2536 
2537 		} else {
2538 
2539 			if (xfer->flags_int.isochronous_xfr) {
2540 				/* isochronous data transfer */
2541 				/* don't force short */
2542 				temp.short_pkt = 1;
2543 			} else {
2544 				/* regular data transfer */
2545 				temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
2546 			}
2547 		}
2548 
2549 		musbotg_setup_standard_chain_sub(&temp);
2550 
2551 		if (xfer->flags_int.isochronous_xfr) {
2552 			temp.offset += temp.len;
2553 		} else {
2554 			/* get next Page Cache pointer */
2555 			temp.pc = xfer->frbuffers + x;
2556 		}
2557 	}
2558 
2559 	/* check for control transfer */
2560 	if (xfer->flags_int.control_xfr) {
2561 
2562 		/* always setup a valid "pc" pointer for status and sync */
2563 		temp.pc = xfer->frbuffers + 0;
2564 		temp.len = 0;
2565 		temp.short_pkt = 0;
2566 		temp.setup_alt_next = 0;
2567 
2568 		/* check if we should append a status stage */
2569 		if (!xfer->flags_int.control_act) {
2570 			/*
2571 			 * Send a DATA1 message and invert the current
2572 			 * endpoint direction.
2573 			 */
2574 			if (sc->sc_mode == MUSB2_DEVICE_MODE)
2575 				temp.func = &musbotg_dev_ctrl_status;
2576 			else {
2577 				if (xfer->endpointno & UE_DIR_IN)
2578 					temp.func = musbotg_host_ctrl_status_tx;
2579 				else
2580 					temp.func = musbotg_host_ctrl_status_rx;
2581 			}
2582 			musbotg_setup_standard_chain_sub(&temp);
2583 		}
2584 	}
2585 	/* must have at least one frame! */
2586 	td = temp.td;
2587 	xfer->td_transfer_last = td;
2588 }
2589 
2590 static void
2591 musbotg_timeout(void *arg)
2592 {
2593 	struct usb_xfer *xfer = arg;
2594 
2595 	DPRINTFN(1, "xfer=%p\n", xfer);
2596 
2597 	USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2598 
2599 	/* transfer is transferred */
2600 	musbotg_device_done(xfer, USB_ERR_TIMEOUT);
2601 }
2602 
2603 static void
2604 musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on)
2605 {
2606 	uint16_t temp;
2607 
2608 	/*
2609 	 * Only enable the endpoint interrupt when we are
2610 	 * actually waiting for data, hence we are dealing
2611 	 * with level triggered interrupts !
2612 	 */
2613 	DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on);
2614 
2615 	if (channel == -1)
2616 		return;
2617 
2618 	if (channel == 0) {
2619 		temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2620 		if (on)
2621 			temp |= MUSB2_MASK_EPINT(0);
2622 		else
2623 			temp &= ~MUSB2_MASK_EPINT(0);
2624 
2625 		MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2626 	} else {
2627 		temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE);
2628 		if (on)
2629 			temp |= MUSB2_MASK_EPINT(channel);
2630 		else
2631 			temp &= ~MUSB2_MASK_EPINT(channel);
2632 		MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp);
2633 
2634 		temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2635 		if (on)
2636 			temp |= MUSB2_MASK_EPINT(channel);
2637 		else
2638 			temp &= ~MUSB2_MASK_EPINT(channel);
2639 		MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2640 	}
2641 
2642 	if (sc->sc_ep_int_set)
2643 		sc->sc_ep_int_set(sc, channel, on);
2644 }
2645 
2646 static void
2647 musbotg_start_standard_chain(struct usb_xfer *xfer)
2648 {
2649 	DPRINTFN(8, "\n");
2650 
2651 	/* poll one time */
2652 	if (musbotg_xfer_do_fifo(xfer)) {
2653 
2654 		DPRINTFN(14, "enabled interrupts on endpoint\n");
2655 
2656 		/* put transfer on interrupt queue */
2657 		usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2658 
2659 		/* start timeout, if any */
2660 		if (xfer->timeout != 0) {
2661 			usbd_transfer_timeout_ms(xfer,
2662 			    &musbotg_timeout, xfer->timeout);
2663 		}
2664 	}
2665 }
2666 
2667 static void
2668 musbotg_root_intr(struct musbotg_softc *sc)
2669 {
2670 	DPRINTFN(8, "\n");
2671 
2672 	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2673 
2674 	/* set port bit */
2675 	sc->sc_hub_idata[0] = 0x02;	/* we only have one port */
2676 
2677 	uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2678 	    sizeof(sc->sc_hub_idata));
2679 }
2680 
2681 static usb_error_t
2682 musbotg_standard_done_sub(struct usb_xfer *xfer)
2683 {
2684 	struct musbotg_td *td;
2685 	uint32_t len;
2686 	uint8_t error;
2687 
2688 	DPRINTFN(8, "\n");
2689 
2690 	td = xfer->td_transfer_cache;
2691 
2692 	do {
2693 		len = td->remainder;
2694 
2695 		xfer->endpoint->toggle_next = td->toggle;
2696 
2697 		if (xfer->aframes != xfer->nframes) {
2698 			/*
2699 		         * Verify the length and subtract
2700 		         * the remainder from "frlengths[]":
2701 		         */
2702 			if (len > xfer->frlengths[xfer->aframes]) {
2703 				td->error = 1;
2704 			} else {
2705 				xfer->frlengths[xfer->aframes] -= len;
2706 			}
2707 		}
2708 		/* Check for transfer error */
2709 		if (td->error) {
2710 			/* the transfer is finished */
2711 			error = 1;
2712 			td = NULL;
2713 			break;
2714 		}
2715 		/* Check for short transfer */
2716 		if (len > 0) {
2717 			if (xfer->flags_int.short_frames_ok) {
2718 				/* follow alt next */
2719 				if (td->alt_next) {
2720 					td = td->obj_next;
2721 				} else {
2722 					td = NULL;
2723 				}
2724 			} else {
2725 				/* the transfer is finished */
2726 				td = NULL;
2727 			}
2728 			error = 0;
2729 			break;
2730 		}
2731 		td = td->obj_next;
2732 
2733 		/* this USB frame is complete */
2734 		error = 0;
2735 		break;
2736 
2737 	} while (0);
2738 
2739 	/* update transfer cache */
2740 
2741 	xfer->td_transfer_cache = td;
2742 
2743 	return (error ?
2744 	    USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
2745 }
2746 
2747 static void
2748 musbotg_standard_done(struct usb_xfer *xfer)
2749 {
2750 	usb_error_t err = 0;
2751 
2752 	DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n",
2753 	    xfer, xfer->endpoint);
2754 
2755 	/* reset scanner */
2756 
2757 	xfer->td_transfer_cache = xfer->td_transfer_first;
2758 
2759 	if (xfer->flags_int.control_xfr) {
2760 
2761 		if (xfer->flags_int.control_hdr) {
2762 
2763 			err = musbotg_standard_done_sub(xfer);
2764 		}
2765 		xfer->aframes = 1;
2766 
2767 		if (xfer->td_transfer_cache == NULL) {
2768 			goto done;
2769 		}
2770 	}
2771 	while (xfer->aframes != xfer->nframes) {
2772 
2773 		err = musbotg_standard_done_sub(xfer);
2774 		xfer->aframes++;
2775 
2776 		if (xfer->td_transfer_cache == NULL) {
2777 			goto done;
2778 		}
2779 	}
2780 
2781 	if (xfer->flags_int.control_xfr &&
2782 	    !xfer->flags_int.control_act) {
2783 
2784 		err = musbotg_standard_done_sub(xfer);
2785 	}
2786 done:
2787 	musbotg_device_done(xfer, err);
2788 }
2789 
2790 /*------------------------------------------------------------------------*
2791  *	musbotg_device_done
2792  *
2793  * NOTE: this function can be called more than one time on the
2794  * same USB transfer!
2795  *------------------------------------------------------------------------*/
2796 static void
2797 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error)
2798 {
2799 	struct musbotg_td *td;
2800 	struct musbotg_softc *sc;
2801 
2802 	USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2803 
2804 	DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n",
2805 	    xfer, xfer->endpoint, error);
2806 
2807 	DPRINTFN(14, "disabled interrupts on endpoint\n");
2808 
2809 	sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2810 	td = xfer->td_transfer_cache;
2811 
2812 	if (td && (td->channel != -1))
2813 		musbotg_channel_free(sc, td);
2814 
2815 	/* dequeue transfer and start next transfer */
2816 	usbd_transfer_done(xfer, error);
2817 }
2818 
2819 static void
2820 musbotg_xfer_stall(struct usb_xfer *xfer)
2821 {
2822 	musbotg_device_done(xfer, USB_ERR_STALLED);
2823 }
2824 
2825 static void
2826 musbotg_set_stall(struct usb_device *udev,
2827     struct usb_endpoint *ep, uint8_t *did_stall)
2828 {
2829 	struct musbotg_softc *sc;
2830 	uint8_t ep_no;
2831 
2832 	USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2833 
2834 	DPRINTFN(4, "endpoint=%p\n", ep);
2835 
2836 	/* set FORCESTALL */
2837 	sc = MUSBOTG_BUS2SC(udev->bus);
2838 
2839 	ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2840 
2841 	/* select endpoint */
2842 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2843 
2844 	if (ep->edesc->bEndpointAddress & UE_DIR_IN) {
2845 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2846 		    MUSB2_MASK_CSRL_TXSENDSTALL);
2847 	} else {
2848 		MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2849 		    MUSB2_MASK_CSRL_RXSENDSTALL);
2850 	}
2851 }
2852 
2853 static void
2854 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket,
2855     uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2856 {
2857 	uint16_t mps;
2858 	uint16_t temp;
2859 	uint8_t csr;
2860 
2861 	if (ep_type == UE_CONTROL) {
2862 		/* clearing stall is not needed */
2863 		return;
2864 	}
2865 	/* select endpoint */
2866 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2867 
2868 	/* compute max frame size */
2869 	mps = wMaxPacket & 0x7FF;
2870 	switch ((wMaxPacket >> 11) & 3) {
2871 	case 1:
2872 		mps *= 2;
2873 		break;
2874 	case 2:
2875 		mps *= 3;
2876 		break;
2877 	default:
2878 		break;
2879 	}
2880 
2881 	if (ep_dir == UE_DIR_IN) {
2882 
2883 		temp = 0;
2884 
2885 		/* Configure endpoint */
2886 		switch (ep_type) {
2887 		case UE_INTERRUPT:
2888 			MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2889 			MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2890 			    MUSB2_MASK_CSRH_TXMODE | temp);
2891 			break;
2892 		case UE_ISOCHRONOUS:
2893 			MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2894 			MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2895 			    MUSB2_MASK_CSRH_TXMODE |
2896 			    MUSB2_MASK_CSRH_TXISO | temp);
2897 			break;
2898 		case UE_BULK:
2899 			MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2900 			MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2901 			    MUSB2_MASK_CSRH_TXMODE | temp);
2902 			break;
2903 		default:
2904 			break;
2905 		}
2906 
2907 		/* Need to flush twice in case of double bufring */
2908 		csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2909 		if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2910 			MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2911 			    MUSB2_MASK_CSRL_TXFFLUSH);
2912 			csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2913 			if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2914 				MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2915 				    MUSB2_MASK_CSRL_TXFFLUSH);
2916 				csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2917 			}
2918 		}
2919 		/* reset data toggle */
2920 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2921 		    MUSB2_MASK_CSRL_TXDT_CLR);
2922 		MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2923 		csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2924 
2925 		/* set double/single buffering */
2926 		temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS);
2927 		if (mps <= (sc->sc_hw_ep_profile[ep_no].
2928 		    max_in_frame_size / 2)) {
2929 			/* double buffer */
2930 			temp &= ~(1 << ep_no);
2931 		} else {
2932 			/* single buffer */
2933 			temp |= (1 << ep_no);
2934 		}
2935 		MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp);
2936 
2937 		/* clear sent stall */
2938 		if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) {
2939 			MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2940 			csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2941 		}
2942 	} else {
2943 
2944 		temp = 0;
2945 
2946 		/* Configure endpoint */
2947 		switch (ep_type) {
2948 		case UE_INTERRUPT:
2949 			MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2950 			MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2951 			    MUSB2_MASK_CSRH_RXNYET | temp);
2952 			break;
2953 		case UE_ISOCHRONOUS:
2954 			MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2955 			MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2956 			    MUSB2_MASK_CSRH_RXNYET |
2957 			    MUSB2_MASK_CSRH_RXISO | temp);
2958 			break;
2959 		case UE_BULK:
2960 			MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2961 			MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp);
2962 			break;
2963 		default:
2964 			break;
2965 		}
2966 
2967 		/* Need to flush twice in case of double bufring */
2968 		csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2969 		if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2970 			MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2971 			    MUSB2_MASK_CSRL_RXFFLUSH);
2972 			csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2973 			if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2974 				MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2975 				    MUSB2_MASK_CSRL_RXFFLUSH);
2976 				csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2977 			}
2978 		}
2979 		/* reset data toggle */
2980 		MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2981 		    MUSB2_MASK_CSRL_RXDT_CLR);
2982 		MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
2983 		csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2984 
2985 		/* set double/single buffering */
2986 		temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS);
2987 		if (mps <= (sc->sc_hw_ep_profile[ep_no].
2988 		    max_out_frame_size / 2)) {
2989 			/* double buffer */
2990 			temp &= ~(1 << ep_no);
2991 		} else {
2992 			/* single buffer */
2993 			temp |= (1 << ep_no);
2994 		}
2995 		MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp);
2996 
2997 		/* clear sent stall */
2998 		if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) {
2999 			MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3000 		}
3001 	}
3002 }
3003 
3004 static void
3005 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3006 {
3007 	struct musbotg_softc *sc;
3008 	struct usb_endpoint_descriptor *ed;
3009 
3010 	DPRINTFN(4, "endpoint=%p\n", ep);
3011 
3012 	USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3013 
3014 	/* check mode */
3015 	if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3016 		/* not supported */
3017 		return;
3018 	}
3019 	/* get softc */
3020 	sc = MUSBOTG_BUS2SC(udev->bus);
3021 
3022 	/* get endpoint descriptor */
3023 	ed = ep->edesc;
3024 
3025 	/* reset endpoint */
3026 	musbotg_clear_stall_sub(sc,
3027 	    UGETW(ed->wMaxPacketSize),
3028 	    (ed->bEndpointAddress & UE_ADDR),
3029 	    (ed->bmAttributes & UE_XFERTYPE),
3030 	    (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3031 }
3032 
3033 usb_error_t
3034 musbotg_init(struct musbotg_softc *sc)
3035 {
3036 	struct usb_hw_ep_profile *pf;
3037 	uint16_t offset;
3038 	uint8_t nrx;
3039 	uint8_t ntx;
3040 	uint8_t temp;
3041 	uint8_t fsize;
3042 	uint8_t frx;
3043 	uint8_t ftx;
3044 	uint8_t dynfifo;
3045 
3046 	DPRINTFN(1, "start\n");
3047 
3048 	/* set up the bus structure */
3049 	sc->sc_bus.usbrev = USB_REV_2_0;
3050 	sc->sc_bus.methods = &musbotg_bus_methods;
3051 
3052 	USB_BUS_LOCK(&sc->sc_bus);
3053 
3054 	/* turn on clocks */
3055 
3056 	if (sc->sc_clocks_on) {
3057 		(sc->sc_clocks_on) (sc->sc_clocks_arg);
3058 	}
3059 
3060 	/* wait a little for things to stabilise */
3061 	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
3062 
3063 	/* disable all interrupts */
3064 
3065 	temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3066 	DPRINTF("pre-DEVCTL=0x%02x\n", temp);
3067 
3068 	MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3069 	MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3070 	MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3071 
3072 	/* disable pullup */
3073 
3074 	musbotg_pull_common(sc, 0);
3075 
3076 	/* wait a little bit (10ms) */
3077 	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3078 
3079 
3080 	/* disable double packet buffering */
3081 	MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF);
3082 	MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF);
3083 
3084 	/* enable HighSpeed and ISO Update flags */
3085 
3086 	MUSB2_WRITE_1(sc, MUSB2_REG_POWER,
3087 	    MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD);
3088 
3089 	if (sc->sc_mode == MUSB2_DEVICE_MODE) {
3090 		/* clear Session bit, if set */
3091 		temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3092 		temp &= ~MUSB2_MASK_SESS;
3093 		MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3094 	} else {
3095 		/* Enter session for Host mode */
3096 		temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3097 		temp |= MUSB2_MASK_SESS;
3098 		MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3099 	}
3100 
3101 	/* wait a little for things to stabilise */
3102 	usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
3103 
3104 	DPRINTF("DEVCTL=0x%02x\n", temp);
3105 
3106 	/* disable testmode */
3107 
3108 	MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0);
3109 
3110 	/* set default value */
3111 
3112 	MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0);
3113 
3114 	/* select endpoint index 0 */
3115 
3116 	MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
3117 
3118 	/* read out number of endpoints */
3119 
3120 	nrx =
3121 	    (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16);
3122 
3123 	ntx =
3124 	    (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16);
3125 
3126 	/* these numbers exclude the control endpoint */
3127 
3128 	DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx);
3129 
3130 	sc->sc_ep_max = (nrx > ntx) ? nrx : ntx;
3131 	if (sc->sc_ep_max == 0) {
3132 		DPRINTFN(2, "ERROR: Looks like the clocks are off!\n");
3133 	}
3134 	/* read out configuration data */
3135 
3136 	sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA);
3137 
3138 	DPRINTFN(2, "Config Data: 0x%02x\n",
3139 	    sc->sc_conf_data);
3140 
3141 	dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0;
3142 
3143 	if (dynfifo) {
3144 		device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, "
3145 		    "assuming 16Kbytes of FIFO RAM\n");
3146 	}
3147 
3148 	DPRINTFN(2, "HW version: 0x%04x\n",
3149 	    MUSB2_READ_1(sc, MUSB2_REG_HWVERS));
3150 
3151 	/* initialise endpoint profiles */
3152 
3153 	offset = 0;
3154 
3155 	for (temp = 1; temp <= sc->sc_ep_max; temp++) {
3156 		pf = sc->sc_hw_ep_profile + temp;
3157 
3158 		/* select endpoint */
3159 		MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp);
3160 
3161 		fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE);
3162 		frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;
3163 		ftx = (fsize & MUSB2_MASK_TX_FSIZE);
3164 
3165 		DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n",
3166 		    temp, ftx, frx, dynfifo);
3167 
3168 		if (dynfifo) {
3169 			if (frx && (temp <= nrx)) {
3170 				if (temp == 1) {
3171 					frx = 12;	/* 4K */
3172 					MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3173 					    MUSB2_VAL_FIFOSZ_4096 |
3174 					    MUSB2_MASK_FIFODB);
3175 				} else if (temp < 8) {
3176 					frx = 10;	/* 1K */
3177 					MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3178 					    MUSB2_VAL_FIFOSZ_512 |
3179 					    MUSB2_MASK_FIFODB);
3180 				} else {
3181 					frx = 7;	/* 128 bytes */
3182 					MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3183 					    MUSB2_VAL_FIFOSZ_128);
3184 				}
3185 
3186 				MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD,
3187 				    offset >> 3);
3188 
3189 				offset += (1 << frx);
3190 			}
3191 			if (ftx && (temp <= ntx)) {
3192 				if (temp == 1) {
3193 					ftx = 12;	/* 4K */
3194 					MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3195 	 				    MUSB2_VAL_FIFOSZ_4096 |
3196 	 				    MUSB2_MASK_FIFODB);
3197 				} else if (temp < 8) {
3198 					ftx = 10;	/* 1K */
3199 					MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3200 	 				    MUSB2_VAL_FIFOSZ_512 |
3201 	 				    MUSB2_MASK_FIFODB);
3202 				} else {
3203 					ftx = 7;	/* 128 bytes */
3204 					MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3205 	 				    MUSB2_VAL_FIFOSZ_128);
3206 				}
3207 
3208 				MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD,
3209 				    offset >> 3);
3210 
3211 				offset += (1 << ftx);
3212 			}
3213 		}
3214 
3215 		if (frx && ftx && (temp <= nrx) && (temp <= ntx)) {
3216 			pf->max_in_frame_size = 1 << ftx;
3217 			pf->max_out_frame_size = 1 << frx;
3218 			pf->is_simplex = 0;	/* duplex */
3219 			pf->support_multi_buffer = 1;
3220 			pf->support_bulk = 1;
3221 			pf->support_interrupt = 1;
3222 			pf->support_isochronous = 1;
3223 			pf->support_in = 1;
3224 			pf->support_out = 1;
3225 		} else if (frx && (temp <= nrx)) {
3226 			pf->max_out_frame_size = 1 << frx;
3227 			pf->is_simplex = 1;	/* simplex */
3228 			pf->support_multi_buffer = 1;
3229 			pf->support_bulk = 1;
3230 			pf->support_interrupt = 1;
3231 			pf->support_isochronous = 1;
3232 			pf->support_out = 1;
3233 		} else if (ftx && (temp <= ntx)) {
3234 			pf->max_in_frame_size = 1 << ftx;
3235 			pf->is_simplex = 1;	/* simplex */
3236 			pf->support_multi_buffer = 1;
3237 			pf->support_bulk = 1;
3238 			pf->support_interrupt = 1;
3239 			pf->support_isochronous = 1;
3240 			pf->support_in = 1;
3241 		}
3242 	}
3243 
3244 	DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset);
3245 
3246 	/* turn on default interrupts */
3247 
3248 	if (sc->sc_mode == MUSB2_HOST_MODE)
3249 		MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff);
3250 	else
3251 		MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE,
3252 		    MUSB2_MASK_IRESET);
3253 
3254 	musbotg_clocks_off(sc);
3255 
3256 	USB_BUS_UNLOCK(&sc->sc_bus);
3257 
3258 	/* catch any lost interrupts */
3259 
3260 	musbotg_do_poll(&sc->sc_bus);
3261 
3262 	return (0);			/* success */
3263 }
3264 
3265 void
3266 musbotg_uninit(struct musbotg_softc *sc)
3267 {
3268 	USB_BUS_LOCK(&sc->sc_bus);
3269 
3270 	/* disable all interrupts */
3271 	MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3272 	MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3273 	MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3274 
3275 	sc->sc_flags.port_powered = 0;
3276 	sc->sc_flags.status_vbus = 0;
3277 	sc->sc_flags.status_bus_reset = 0;
3278 	sc->sc_flags.status_suspend = 0;
3279 	sc->sc_flags.change_suspend = 0;
3280 	sc->sc_flags.change_connect = 1;
3281 
3282 	musbotg_pull_down(sc);
3283 	musbotg_clocks_off(sc);
3284 	USB_BUS_UNLOCK(&sc->sc_bus);
3285 }
3286 
3287 static void
3288 musbotg_suspend(struct musbotg_softc *sc)
3289 {
3290 	/* TODO */
3291 }
3292 
3293 static void
3294 musbotg_resume(struct musbotg_softc *sc)
3295 {
3296 	/* TODO */
3297 }
3298 
3299 static void
3300 musbotg_do_poll(struct usb_bus *bus)
3301 {
3302 	struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
3303 
3304 	USB_BUS_LOCK(&sc->sc_bus);
3305 	musbotg_interrupt_poll(sc);
3306 	USB_BUS_UNLOCK(&sc->sc_bus);
3307 }
3308 
3309 /*------------------------------------------------------------------------*
3310  * musbotg bulk support
3311  *------------------------------------------------------------------------*/
3312 static void
3313 musbotg_device_bulk_open(struct usb_xfer *xfer)
3314 {
3315 	return;
3316 }
3317 
3318 static void
3319 musbotg_device_bulk_close(struct usb_xfer *xfer)
3320 {
3321 	musbotg_device_done(xfer, USB_ERR_CANCELLED);
3322 }
3323 
3324 static void
3325 musbotg_device_bulk_enter(struct usb_xfer *xfer)
3326 {
3327 	return;
3328 }
3329 
3330 static void
3331 musbotg_device_bulk_start(struct usb_xfer *xfer)
3332 {
3333 	/* setup TDs */
3334 	musbotg_setup_standard_chain(xfer);
3335 	musbotg_start_standard_chain(xfer);
3336 }
3337 
3338 struct usb_pipe_methods musbotg_device_bulk_methods =
3339 {
3340 	.open = musbotg_device_bulk_open,
3341 	.close = musbotg_device_bulk_close,
3342 	.enter = musbotg_device_bulk_enter,
3343 	.start = musbotg_device_bulk_start,
3344 };
3345 
3346 /*------------------------------------------------------------------------*
3347  * musbotg control support
3348  *------------------------------------------------------------------------*/
3349 static void
3350 musbotg_device_ctrl_open(struct usb_xfer *xfer)
3351 {
3352 	return;
3353 }
3354 
3355 static void
3356 musbotg_device_ctrl_close(struct usb_xfer *xfer)
3357 {
3358 	musbotg_device_done(xfer, USB_ERR_CANCELLED);
3359 }
3360 
3361 static void
3362 musbotg_device_ctrl_enter(struct usb_xfer *xfer)
3363 {
3364 	return;
3365 }
3366 
3367 static void
3368 musbotg_device_ctrl_start(struct usb_xfer *xfer)
3369 {
3370 	/* setup TDs */
3371 	musbotg_setup_standard_chain(xfer);
3372 	musbotg_start_standard_chain(xfer);
3373 }
3374 
3375 struct usb_pipe_methods musbotg_device_ctrl_methods =
3376 {
3377 	.open = musbotg_device_ctrl_open,
3378 	.close = musbotg_device_ctrl_close,
3379 	.enter = musbotg_device_ctrl_enter,
3380 	.start = musbotg_device_ctrl_start,
3381 };
3382 
3383 /*------------------------------------------------------------------------*
3384  * musbotg interrupt support
3385  *------------------------------------------------------------------------*/
3386 static void
3387 musbotg_device_intr_open(struct usb_xfer *xfer)
3388 {
3389 	return;
3390 }
3391 
3392 static void
3393 musbotg_device_intr_close(struct usb_xfer *xfer)
3394 {
3395 	musbotg_device_done(xfer, USB_ERR_CANCELLED);
3396 }
3397 
3398 static void
3399 musbotg_device_intr_enter(struct usb_xfer *xfer)
3400 {
3401 	return;
3402 }
3403 
3404 static void
3405 musbotg_device_intr_start(struct usb_xfer *xfer)
3406 {
3407 	/* setup TDs */
3408 	musbotg_setup_standard_chain(xfer);
3409 	musbotg_start_standard_chain(xfer);
3410 }
3411 
3412 struct usb_pipe_methods musbotg_device_intr_methods =
3413 {
3414 	.open = musbotg_device_intr_open,
3415 	.close = musbotg_device_intr_close,
3416 	.enter = musbotg_device_intr_enter,
3417 	.start = musbotg_device_intr_start,
3418 };
3419 
3420 /*------------------------------------------------------------------------*
3421  * musbotg full speed isochronous support
3422  *------------------------------------------------------------------------*/
3423 static void
3424 musbotg_device_isoc_open(struct usb_xfer *xfer)
3425 {
3426 	return;
3427 }
3428 
3429 static void
3430 musbotg_device_isoc_close(struct usb_xfer *xfer)
3431 {
3432 	musbotg_device_done(xfer, USB_ERR_CANCELLED);
3433 }
3434 
3435 static void
3436 musbotg_device_isoc_enter(struct usb_xfer *xfer)
3437 {
3438 	struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
3439 	uint32_t temp;
3440 	uint32_t nframes;
3441 	uint32_t fs_frames;
3442 
3443 	DPRINTFN(5, "xfer=%p next=%d nframes=%d\n",
3444 	    xfer, xfer->endpoint->isoc_next, xfer->nframes);
3445 
3446 	/* get the current frame index */
3447 
3448 	nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME);
3449 
3450 	/*
3451 	 * check if the frame index is within the window where the frames
3452 	 * will be inserted
3453 	 */
3454 	temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME;
3455 
3456 	if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
3457 		fs_frames = (xfer->nframes + 7) / 8;
3458 	} else {
3459 		fs_frames = xfer->nframes;
3460 	}
3461 
3462 	if ((xfer->endpoint->is_synced == 0) ||
3463 	    (temp < fs_frames)) {
3464 		/*
3465 		 * If there is data underflow or the pipe queue is
3466 		 * empty we schedule the transfer a few frames ahead
3467 		 * of the current frame position. Else two isochronous
3468 		 * transfers might overlap.
3469 		 */
3470 		xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME;
3471 		xfer->endpoint->is_synced = 1;
3472 		DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next);
3473 	}
3474 	/*
3475 	 * compute how many milliseconds the insertion is ahead of the
3476 	 * current frame position:
3477 	 */
3478 	temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME;
3479 
3480 	/*
3481 	 * pre-compute when the isochronous transfer will be finished:
3482 	 */
3483 	xfer->isoc_time_complete =
3484 	    usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
3485 	    fs_frames;
3486 
3487 	/* compute frame number for next insertion */
3488 	xfer->endpoint->isoc_next += fs_frames;
3489 
3490 	/* setup TDs */
3491 	musbotg_setup_standard_chain(xfer);
3492 }
3493 
3494 static void
3495 musbotg_device_isoc_start(struct usb_xfer *xfer)
3496 {
3497 	/* start TD chain */
3498 	musbotg_start_standard_chain(xfer);
3499 }
3500 
3501 struct usb_pipe_methods musbotg_device_isoc_methods =
3502 {
3503 	.open = musbotg_device_isoc_open,
3504 	.close = musbotg_device_isoc_close,
3505 	.enter = musbotg_device_isoc_enter,
3506 	.start = musbotg_device_isoc_start,
3507 };
3508 
3509 /*------------------------------------------------------------------------*
3510  * musbotg root control support
3511  *------------------------------------------------------------------------*
3512  * Simulate a hardware HUB by handling all the necessary requests.
3513  *------------------------------------------------------------------------*/
3514 
3515 static const struct usb_device_descriptor musbotg_devd = {
3516 	.bLength = sizeof(struct usb_device_descriptor),
3517 	.bDescriptorType = UDESC_DEVICE,
3518 	.bcdUSB = {0x00, 0x02},
3519 	.bDeviceClass = UDCLASS_HUB,
3520 	.bDeviceSubClass = UDSUBCLASS_HUB,
3521 	.bDeviceProtocol = UDPROTO_HSHUBSTT,
3522 	.bMaxPacketSize = 64,
3523 	.bcdDevice = {0x00, 0x01},
3524 	.iManufacturer = 1,
3525 	.iProduct = 2,
3526 	.bNumConfigurations = 1,
3527 };
3528 
3529 static const struct usb_device_qualifier musbotg_odevd = {
3530 	.bLength = sizeof(struct usb_device_qualifier),
3531 	.bDescriptorType = UDESC_DEVICE_QUALIFIER,
3532 	.bcdUSB = {0x00, 0x02},
3533 	.bDeviceClass = UDCLASS_HUB,
3534 	.bDeviceSubClass = UDSUBCLASS_HUB,
3535 	.bDeviceProtocol = UDPROTO_FSHUB,
3536 	.bMaxPacketSize0 = 0,
3537 	.bNumConfigurations = 0,
3538 };
3539 
3540 static const struct musbotg_config_desc musbotg_confd = {
3541 	.confd = {
3542 		.bLength = sizeof(struct usb_config_descriptor),
3543 		.bDescriptorType = UDESC_CONFIG,
3544 		.wTotalLength[0] = sizeof(musbotg_confd),
3545 		.bNumInterface = 1,
3546 		.bConfigurationValue = 1,
3547 		.iConfiguration = 0,
3548 		.bmAttributes = UC_SELF_POWERED,
3549 		.bMaxPower = 0,
3550 	},
3551 	.ifcd = {
3552 		.bLength = sizeof(struct usb_interface_descriptor),
3553 		.bDescriptorType = UDESC_INTERFACE,
3554 		.bNumEndpoints = 1,
3555 		.bInterfaceClass = UICLASS_HUB,
3556 		.bInterfaceSubClass = UISUBCLASS_HUB,
3557 		.bInterfaceProtocol = 0,
3558 	},
3559 	.endpd = {
3560 		.bLength = sizeof(struct usb_endpoint_descriptor),
3561 		.bDescriptorType = UDESC_ENDPOINT,
3562 		.bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT),
3563 		.bmAttributes = UE_INTERRUPT,
3564 		.wMaxPacketSize[0] = 8,
3565 		.bInterval = 255,
3566 	},
3567 };
3568 
3569 #define	HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3570 
3571 static const struct usb_hub_descriptor_min musbotg_hubd = {
3572 	.bDescLength = sizeof(musbotg_hubd),
3573 	.bDescriptorType = UDESC_HUB,
3574 	.bNbrPorts = 1,
3575 	HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
3576 	.bPwrOn2PwrGood = 50,
3577 	.bHubContrCurrent = 0,
3578 	.DeviceRemovable = {0},		/* port is removable */
3579 };
3580 
3581 #define	STRING_VENDOR \
3582   "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s"
3583 
3584 #define	STRING_PRODUCT \
3585   "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
3586 
3587 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor);
3588 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product);
3589 
3590 static usb_error_t
3591 musbotg_roothub_exec(struct usb_device *udev,
3592     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3593 {
3594 	struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
3595 	const void *ptr;
3596 	uint16_t len;
3597 	uint16_t value;
3598 	uint16_t index;
3599 	uint8_t reg;
3600 	usb_error_t err;
3601 
3602 	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3603 
3604 	/* buffer reset */
3605 	ptr = (const void *)&sc->sc_hub_temp;
3606 	len = 0;
3607 	err = 0;
3608 
3609 	value = UGETW(req->wValue);
3610 	index = UGETW(req->wIndex);
3611 
3612 	/* demultiplex the control request */
3613 
3614 	switch (req->bmRequestType) {
3615 	case UT_READ_DEVICE:
3616 		switch (req->bRequest) {
3617 		case UR_GET_DESCRIPTOR:
3618 			goto tr_handle_get_descriptor;
3619 		case UR_GET_CONFIG:
3620 			goto tr_handle_get_config;
3621 		case UR_GET_STATUS:
3622 			goto tr_handle_get_status;
3623 		default:
3624 			goto tr_stalled;
3625 		}
3626 		break;
3627 
3628 	case UT_WRITE_DEVICE:
3629 		switch (req->bRequest) {
3630 		case UR_SET_ADDRESS:
3631 			goto tr_handle_set_address;
3632 		case UR_SET_CONFIG:
3633 			goto tr_handle_set_config;
3634 		case UR_CLEAR_FEATURE:
3635 			goto tr_valid;	/* nop */
3636 		case UR_SET_DESCRIPTOR:
3637 			goto tr_valid;	/* nop */
3638 		case UR_SET_FEATURE:
3639 		default:
3640 			goto tr_stalled;
3641 		}
3642 		break;
3643 
3644 	case UT_WRITE_ENDPOINT:
3645 		switch (req->bRequest) {
3646 		case UR_CLEAR_FEATURE:
3647 			switch (UGETW(req->wValue)) {
3648 			case UF_ENDPOINT_HALT:
3649 				goto tr_handle_clear_halt;
3650 			case UF_DEVICE_REMOTE_WAKEUP:
3651 				goto tr_handle_clear_wakeup;
3652 			default:
3653 				goto tr_stalled;
3654 			}
3655 			break;
3656 		case UR_SET_FEATURE:
3657 			switch (UGETW(req->wValue)) {
3658 			case UF_ENDPOINT_HALT:
3659 				goto tr_handle_set_halt;
3660 			case UF_DEVICE_REMOTE_WAKEUP:
3661 				goto tr_handle_set_wakeup;
3662 			default:
3663 				goto tr_stalled;
3664 			}
3665 			break;
3666 		case UR_SYNCH_FRAME:
3667 			goto tr_valid;	/* nop */
3668 		default:
3669 			goto tr_stalled;
3670 		}
3671 		break;
3672 
3673 	case UT_READ_ENDPOINT:
3674 		switch (req->bRequest) {
3675 		case UR_GET_STATUS:
3676 			goto tr_handle_get_ep_status;
3677 		default:
3678 			goto tr_stalled;
3679 		}
3680 		break;
3681 
3682 	case UT_WRITE_INTERFACE:
3683 		switch (req->bRequest) {
3684 		case UR_SET_INTERFACE:
3685 			goto tr_handle_set_interface;
3686 		case UR_CLEAR_FEATURE:
3687 			goto tr_valid;	/* nop */
3688 		case UR_SET_FEATURE:
3689 		default:
3690 			goto tr_stalled;
3691 		}
3692 		break;
3693 
3694 	case UT_READ_INTERFACE:
3695 		switch (req->bRequest) {
3696 		case UR_GET_INTERFACE:
3697 			goto tr_handle_get_interface;
3698 		case UR_GET_STATUS:
3699 			goto tr_handle_get_iface_status;
3700 		default:
3701 			goto tr_stalled;
3702 		}
3703 		break;
3704 
3705 	case UT_WRITE_CLASS_INTERFACE:
3706 	case UT_WRITE_VENDOR_INTERFACE:
3707 		/* XXX forward */
3708 		break;
3709 
3710 	case UT_READ_CLASS_INTERFACE:
3711 	case UT_READ_VENDOR_INTERFACE:
3712 		/* XXX forward */
3713 		break;
3714 
3715 	case UT_WRITE_CLASS_DEVICE:
3716 		switch (req->bRequest) {
3717 		case UR_CLEAR_FEATURE:
3718 			goto tr_valid;
3719 		case UR_SET_DESCRIPTOR:
3720 		case UR_SET_FEATURE:
3721 			break;
3722 		default:
3723 			goto tr_stalled;
3724 		}
3725 		break;
3726 
3727 	case UT_WRITE_CLASS_OTHER:
3728 		switch (req->bRequest) {
3729 		case UR_CLEAR_FEATURE:
3730 			goto tr_handle_clear_port_feature;
3731 		case UR_SET_FEATURE:
3732 			goto tr_handle_set_port_feature;
3733 		case UR_CLEAR_TT_BUFFER:
3734 		case UR_RESET_TT:
3735 		case UR_STOP_TT:
3736 			goto tr_valid;
3737 
3738 		default:
3739 			goto tr_stalled;
3740 		}
3741 		break;
3742 
3743 	case UT_READ_CLASS_OTHER:
3744 		switch (req->bRequest) {
3745 		case UR_GET_TT_STATE:
3746 			goto tr_handle_get_tt_state;
3747 		case UR_GET_STATUS:
3748 			goto tr_handle_get_port_status;
3749 		default:
3750 			goto tr_stalled;
3751 		}
3752 		break;
3753 
3754 	case UT_READ_CLASS_DEVICE:
3755 		switch (req->bRequest) {
3756 		case UR_GET_DESCRIPTOR:
3757 			goto tr_handle_get_class_descriptor;
3758 		case UR_GET_STATUS:
3759 			goto tr_handle_get_class_status;
3760 
3761 		default:
3762 			goto tr_stalled;
3763 		}
3764 		break;
3765 	default:
3766 		goto tr_stalled;
3767 	}
3768 	goto tr_valid;
3769 
3770 tr_handle_get_descriptor:
3771 	switch (value >> 8) {
3772 	case UDESC_DEVICE:
3773 		if (value & 0xff) {
3774 			goto tr_stalled;
3775 		}
3776 		len = sizeof(musbotg_devd);
3777 		ptr = (const void *)&musbotg_devd;
3778 		goto tr_valid;
3779 	case UDESC_CONFIG:
3780 		if (value & 0xff) {
3781 			goto tr_stalled;
3782 		}
3783 		len = sizeof(musbotg_confd);
3784 		ptr = (const void *)&musbotg_confd;
3785 		goto tr_valid;
3786 	case UDESC_STRING:
3787 		switch (value & 0xff) {
3788 		case 0:		/* Language table */
3789 			len = sizeof(usb_string_lang_en);
3790 			ptr = (const void *)&usb_string_lang_en;
3791 			goto tr_valid;
3792 
3793 		case 1:		/* Vendor */
3794 			len = sizeof(musbotg_vendor);
3795 			ptr = (const void *)&musbotg_vendor;
3796 			goto tr_valid;
3797 
3798 		case 2:		/* Product */
3799 			len = sizeof(musbotg_product);
3800 			ptr = (const void *)&musbotg_product;
3801 			goto tr_valid;
3802 		default:
3803 			break;
3804 		}
3805 		break;
3806 	default:
3807 		goto tr_stalled;
3808 	}
3809 	goto tr_stalled;
3810 
3811 tr_handle_get_config:
3812 	len = 1;
3813 	sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3814 	goto tr_valid;
3815 
3816 tr_handle_get_status:
3817 	len = 2;
3818 	USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3819 	goto tr_valid;
3820 
3821 tr_handle_set_address:
3822 	if (value & 0xFF00) {
3823 		goto tr_stalled;
3824 	}
3825 	sc->sc_rt_addr = value;
3826 	goto tr_valid;
3827 
3828 tr_handle_set_config:
3829 	if (value >= 2) {
3830 		goto tr_stalled;
3831 	}
3832 	sc->sc_conf = value;
3833 	goto tr_valid;
3834 
3835 tr_handle_get_interface:
3836 	len = 1;
3837 	sc->sc_hub_temp.wValue[0] = 0;
3838 	goto tr_valid;
3839 
3840 tr_handle_get_tt_state:
3841 tr_handle_get_class_status:
3842 tr_handle_get_iface_status:
3843 tr_handle_get_ep_status:
3844 	len = 2;
3845 	USETW(sc->sc_hub_temp.wValue, 0);
3846 	goto tr_valid;
3847 
3848 tr_handle_set_halt:
3849 tr_handle_set_interface:
3850 tr_handle_set_wakeup:
3851 tr_handle_clear_wakeup:
3852 tr_handle_clear_halt:
3853 	goto tr_valid;
3854 
3855 tr_handle_clear_port_feature:
3856 	if (index != 1) {
3857 		goto tr_stalled;
3858 	}
3859 	DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
3860 
3861 	switch (value) {
3862 	case UHF_PORT_SUSPEND:
3863 		if (sc->sc_mode == MUSB2_HOST_MODE)
3864 			musbotg_wakeup_host(sc);
3865 		else
3866 			musbotg_wakeup_peer(sc);
3867 		break;
3868 
3869 	case UHF_PORT_ENABLE:
3870 		sc->sc_flags.port_enabled = 0;
3871 		break;
3872 
3873 	case UHF_C_PORT_ENABLE:
3874 		sc->sc_flags.change_enabled = 0;
3875 		break;
3876 
3877 	case UHF_C_PORT_OVER_CURRENT:
3878 		sc->sc_flags.change_over_current = 0;
3879 		break;
3880 
3881 	case UHF_C_PORT_RESET:
3882 		sc->sc_flags.change_reset = 0;
3883 		break;
3884 
3885 	case UHF_PORT_TEST:
3886 	case UHF_PORT_INDICATOR:
3887 		/* nops */
3888 		break;
3889 
3890 	case UHF_PORT_POWER:
3891 		sc->sc_flags.port_powered = 0;
3892 		musbotg_pull_down(sc);
3893 		musbotg_clocks_off(sc);
3894 		break;
3895 	case UHF_C_PORT_CONNECTION:
3896 		sc->sc_flags.change_connect = 0;
3897 		break;
3898 	case UHF_C_PORT_SUSPEND:
3899 		sc->sc_flags.change_suspend = 0;
3900 		break;
3901 	default:
3902 		err = USB_ERR_IOERROR;
3903 		goto done;
3904 	}
3905 	goto tr_valid;
3906 
3907 tr_handle_set_port_feature:
3908 	if (index != 1) {
3909 		goto tr_stalled;
3910 	}
3911 	DPRINTFN(8, "UR_SET_PORT_FEATURE\n");
3912 
3913 	switch (value) {
3914 	case UHF_PORT_ENABLE:
3915 		sc->sc_flags.port_enabled = 1;
3916 		break;
3917 	case UHF_PORT_SUSPEND:
3918 		if (sc->sc_mode == MUSB2_HOST_MODE)
3919 			musbotg_suspend_host(sc);
3920 		break;
3921 
3922 	case UHF_PORT_RESET:
3923 		if (sc->sc_mode == MUSB2_HOST_MODE) {
3924 			reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3925 			reg |= MUSB2_MASK_RESET;
3926 			MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3927 
3928 			/* Wait for 20 msec */
3929 			usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5);
3930 
3931 			reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3932 			reg &= ~MUSB2_MASK_RESET;
3933 			MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3934 
3935 			/* determine line speed */
3936 			reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3937 			if (reg & MUSB2_MASK_HSMODE)
3938 				sc->sc_flags.status_high_speed = 1;
3939 			else
3940 				sc->sc_flags.status_high_speed = 0;
3941 
3942 			sc->sc_flags.change_reset = 1;
3943 		} else
3944 			err = USB_ERR_IOERROR;
3945 		break;
3946 
3947 	case UHF_PORT_TEST:
3948 	case UHF_PORT_INDICATOR:
3949 		/* nops */
3950 		break;
3951 	case UHF_PORT_POWER:
3952 		sc->sc_flags.port_powered = 1;
3953 		break;
3954 	default:
3955 		err = USB_ERR_IOERROR;
3956 		goto done;
3957 	}
3958 	goto tr_valid;
3959 
3960 tr_handle_get_port_status:
3961 
3962 	DPRINTFN(8, "UR_GET_PORT_STATUS\n");
3963 
3964 	if (index != 1) {
3965 		goto tr_stalled;
3966 	}
3967 	if (sc->sc_flags.status_vbus) {
3968 		musbotg_clocks_on(sc);
3969 		musbotg_pull_up(sc);
3970 	} else {
3971 		musbotg_pull_down(sc);
3972 		musbotg_clocks_off(sc);
3973 	}
3974 
3975 	/* Select Device Side Mode */
3976 	if (sc->sc_mode == MUSB2_DEVICE_MODE)
3977 		value = UPS_PORT_MODE_DEVICE;
3978 	else
3979 		value = 0;
3980 
3981 	if (sc->sc_flags.status_high_speed) {
3982 		value |= UPS_HIGH_SPEED;
3983 	}
3984 	if (sc->sc_flags.port_powered) {
3985 		value |= UPS_PORT_POWER;
3986 	}
3987 	if (sc->sc_flags.port_enabled) {
3988 		value |= UPS_PORT_ENABLED;
3989 	}
3990 
3991 	if (sc->sc_flags.port_over_current)
3992 		value |= UPS_OVERCURRENT_INDICATOR;
3993 
3994 	if (sc->sc_flags.status_vbus &&
3995 	    sc->sc_flags.status_bus_reset) {
3996 		value |= UPS_CURRENT_CONNECT_STATUS;
3997 	}
3998 	if (sc->sc_flags.status_suspend) {
3999 		value |= UPS_SUSPEND;
4000 	}
4001 	USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4002 
4003 	value = 0;
4004 
4005 	if (sc->sc_flags.change_connect) {
4006 		value |= UPS_C_CONNECT_STATUS;
4007 
4008 		if (sc->sc_mode == MUSB2_DEVICE_MODE) {
4009 			if (sc->sc_flags.status_vbus &&
4010 			    sc->sc_flags.status_bus_reset) {
4011 				/* reset EP0 state */
4012 				sc->sc_ep0_busy = 0;
4013 				sc->sc_ep0_cmd = 0;
4014 			}
4015 		}
4016 	}
4017 	if (sc->sc_flags.change_suspend)
4018 		value |= UPS_C_SUSPEND;
4019 	if (sc->sc_flags.change_reset)
4020 		value |= UPS_C_PORT_RESET;
4021 	if (sc->sc_flags.change_over_current)
4022 		value |= UPS_C_OVERCURRENT_INDICATOR;
4023 
4024 	USETW(sc->sc_hub_temp.ps.wPortChange, value);
4025 	len = sizeof(sc->sc_hub_temp.ps);
4026 	goto tr_valid;
4027 
4028 tr_handle_get_class_descriptor:
4029 	if (value & 0xFF) {
4030 		goto tr_stalled;
4031 	}
4032 	ptr = (const void *)&musbotg_hubd;
4033 	len = sizeof(musbotg_hubd);
4034 	goto tr_valid;
4035 
4036 tr_stalled:
4037 	err = USB_ERR_STALLED;
4038 tr_valid:
4039 done:
4040 	*plength = len;
4041 	*pptr = ptr;
4042 	return (err);
4043 }
4044 
4045 static void
4046 musbotg_xfer_setup(struct usb_setup_params *parm)
4047 {
4048 	struct musbotg_softc *sc;
4049 	struct usb_xfer *xfer;
4050 	void *last_obj;
4051 	uint32_t ntd;
4052 	uint32_t n;
4053 	uint8_t ep_no;
4054 
4055 	sc = MUSBOTG_BUS2SC(parm->udev->bus);
4056 	xfer = parm->curr_xfer;
4057 
4058 	/*
4059 	 * NOTE: This driver does not use any of the parameters that
4060 	 * are computed from the following values. Just set some
4061 	 * reasonable dummies:
4062 	 */
4063 	parm->hc_max_packet_size = 0x400;
4064 	parm->hc_max_frame_size = 0xc00;
4065 
4066 	if ((parm->methods == &musbotg_device_isoc_methods) ||
4067 	    (parm->methods == &musbotg_device_intr_methods))
4068 		parm->hc_max_packet_count = 3;
4069 	else
4070 		parm->hc_max_packet_count = 1;
4071 
4072 	usbd_transfer_setup_sub(parm);
4073 
4074 	/*
4075 	 * compute maximum number of TDs
4076 	 */
4077 	if (parm->methods == &musbotg_device_ctrl_methods) {
4078 
4079 		ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
4080 
4081 	} else if (parm->methods == &musbotg_device_bulk_methods) {
4082 
4083 		ntd = xfer->nframes + 1 /* SYNC */ ;
4084 
4085 	} else if (parm->methods == &musbotg_device_intr_methods) {
4086 
4087 		ntd = xfer->nframes + 1 /* SYNC */ ;
4088 
4089 	} else if (parm->methods == &musbotg_device_isoc_methods) {
4090 
4091 		ntd = xfer->nframes + 1 /* SYNC */ ;
4092 
4093 	} else {
4094 
4095 		ntd = 0;
4096 	}
4097 
4098 	/*
4099 	 * check if "usbd_transfer_setup_sub" set an error
4100 	 */
4101 	if (parm->err) {
4102 		return;
4103 	}
4104 	/*
4105 	 * allocate transfer descriptors
4106 	 */
4107 	last_obj = NULL;
4108 
4109 	ep_no = xfer->endpointno & UE_ADDR;
4110 
4111 	/*
4112 	 * Check for a valid endpoint profile in USB device mode:
4113 	 */
4114 	if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4115 		const struct usb_hw_ep_profile *pf;
4116 
4117 		musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4118 
4119 		if (pf == NULL) {
4120 			/* should not happen */
4121 			parm->err = USB_ERR_INVAL;
4122 			return;
4123 		}
4124 	}
4125 
4126 	/* align data */
4127 	parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4128 
4129 	for (n = 0; n != ntd; n++) {
4130 
4131 		struct musbotg_td *td;
4132 
4133 		if (parm->buf) {
4134 
4135 			td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4136 
4137 			/* init TD */
4138 			td->max_frame_size = xfer->max_frame_size;
4139 			td->reg_max_packet = xfer->max_packet_size |
4140 			    ((xfer->max_packet_count - 1) << 11);
4141 			td->ep_no = ep_no;
4142 			td->obj_next = last_obj;
4143 
4144 			last_obj = td;
4145 		}
4146 		parm->size[0] += sizeof(*td);
4147 	}
4148 
4149 	xfer->td_start[0] = last_obj;
4150 }
4151 
4152 static void
4153 musbotg_xfer_unsetup(struct usb_xfer *xfer)
4154 {
4155 	return;
4156 }
4157 
4158 static void
4159 musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4160 {
4161 	struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4162 
4163 	if (sc->sc_mode == MUSB2_HOST_MODE)
4164 	        *pus = 2000;                   /* microseconds */
4165 	else
4166 		*pus = 0;
4167 }
4168 
4169 static void
4170 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4171     struct usb_endpoint *ep)
4172 {
4173 	struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4174 
4175 	DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
4176 	    ep, udev->address,
4177 	    edesc->bEndpointAddress, udev->flags.usb_mode,
4178 	    sc->sc_rt_addr);
4179 
4180 	if (udev->device_index != sc->sc_rt_addr) {
4181 		switch (edesc->bmAttributes & UE_XFERTYPE) {
4182 		case UE_CONTROL:
4183 			ep->methods = &musbotg_device_ctrl_methods;
4184 			break;
4185 		case UE_INTERRUPT:
4186 			ep->methods = &musbotg_device_intr_methods;
4187 			break;
4188 		case UE_ISOCHRONOUS:
4189 			ep->methods = &musbotg_device_isoc_methods;
4190 			break;
4191 		case UE_BULK:
4192 			ep->methods = &musbotg_device_bulk_methods;
4193 			break;
4194 		default:
4195 			/* do nothing */
4196 			break;
4197 		}
4198 	}
4199 }
4200 
4201 static void
4202 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4203 {
4204 	struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
4205 
4206 	switch (state) {
4207 	case USB_HW_POWER_SUSPEND:
4208 		musbotg_suspend(sc);
4209 		break;
4210 	case USB_HW_POWER_SHUTDOWN:
4211 		musbotg_uninit(sc);
4212 		break;
4213 	case USB_HW_POWER_RESUME:
4214 		musbotg_resume(sc);
4215 		break;
4216 	default:
4217 		break;
4218 	}
4219 }
4220 
4221 struct usb_bus_methods musbotg_bus_methods =
4222 {
4223 	.endpoint_init = &musbotg_ep_init,
4224 	.get_dma_delay = &musbotg_get_dma_delay,
4225 	.xfer_setup = &musbotg_xfer_setup,
4226 	.xfer_unsetup = &musbotg_xfer_unsetup,
4227 	.get_hw_ep_profile = &musbotg_get_hw_ep_profile,
4228 	.xfer_stall = &musbotg_xfer_stall,
4229 	.set_stall = &musbotg_set_stall,
4230 	.clear_stall = &musbotg_clear_stall,
4231 	.roothub_exec = &musbotg_roothub_exec,
4232 	.xfer_poll = &musbotg_do_poll,
4233 	.set_hw_power_sleep = &musbotg_set_hw_power_sleep,
4234 };
4235