1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip 29 * at their homepage. 30 */ 31 32 /* 33 * This file contains the driver for the Mentor Graphics Inventra USB 34 * 2.0 High Speed Dual-Role controller. 35 * 36 * NOTE: The current implementation only supports Device Side Mode! 37 */ 38 39 #ifdef USB_GLOBAL_INCLUDE_FILE 40 #include USB_GLOBAL_INCLUDE_FILE 41 #else 42 #include <sys/stdint.h> 43 #include <sys/stddef.h> 44 #include <sys/param.h> 45 #include <sys/queue.h> 46 #include <sys/types.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/module.h> 51 #include <sys/lock.h> 52 #include <sys/mutex.h> 53 #include <sys/condvar.h> 54 #include <sys/sysctl.h> 55 #include <sys/sx.h> 56 #include <sys/unistd.h> 57 #include <sys/callout.h> 58 #include <sys/malloc.h> 59 #include <sys/priv.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 64 #define USB_DEBUG_VAR musbotgdebug 65 66 #include <dev/usb/usb_core.h> 67 #include <dev/usb/usb_debug.h> 68 #include <dev/usb/usb_busdma.h> 69 #include <dev/usb/usb_process.h> 70 #include <dev/usb/usb_transfer.h> 71 #include <dev/usb/usb_device.h> 72 #include <dev/usb/usb_hub.h> 73 #include <dev/usb/usb_util.h> 74 75 #include <dev/usb/usb_controller.h> 76 #include <dev/usb/usb_bus.h> 77 #endif /* USB_GLOBAL_INCLUDE_FILE */ 78 79 #include <dev/usb/controller/musb_otg.h> 80 81 #define MUSBOTG_INTR_ENDPT 1 82 83 #define MUSBOTG_BUS2SC(bus) \ 84 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \ 85 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus)))) 86 87 #define MUSBOTG_PC2SC(pc) \ 88 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 89 90 #ifdef USB_DEBUG 91 static int musbotgdebug = 0; 92 93 static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg"); 94 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RW, 95 &musbotgdebug, 0, "Debug level"); 96 #endif 97 98 #define MAX_NAK_TO 16 99 100 /* prototypes */ 101 102 static const struct usb_bus_methods musbotg_bus_methods; 103 static const struct usb_pipe_methods musbotg_device_bulk_methods; 104 static const struct usb_pipe_methods musbotg_device_ctrl_methods; 105 static const struct usb_pipe_methods musbotg_device_intr_methods; 106 static const struct usb_pipe_methods musbotg_device_isoc_methods; 107 108 /* Control transfers: Device mode */ 109 static musbotg_cmd_t musbotg_dev_ctrl_setup_rx; 110 static musbotg_cmd_t musbotg_dev_ctrl_data_rx; 111 static musbotg_cmd_t musbotg_dev_ctrl_data_tx; 112 static musbotg_cmd_t musbotg_dev_ctrl_status; 113 114 /* Control transfers: Host mode */ 115 static musbotg_cmd_t musbotg_host_ctrl_setup_tx; 116 static musbotg_cmd_t musbotg_host_ctrl_data_rx; 117 static musbotg_cmd_t musbotg_host_ctrl_data_tx; 118 static musbotg_cmd_t musbotg_host_ctrl_status_rx; 119 static musbotg_cmd_t musbotg_host_ctrl_status_tx; 120 121 /* Bulk, Interrupt, Isochronous: Device mode */ 122 static musbotg_cmd_t musbotg_dev_data_rx; 123 static musbotg_cmd_t musbotg_dev_data_tx; 124 125 /* Bulk, Interrupt, Isochronous: Host mode */ 126 static musbotg_cmd_t musbotg_host_data_rx; 127 static musbotg_cmd_t musbotg_host_data_tx; 128 129 static void musbotg_device_done(struct usb_xfer *, usb_error_t); 130 static void musbotg_do_poll(struct usb_bus *); 131 static void musbotg_standard_done(struct usb_xfer *); 132 static void musbotg_interrupt_poll(struct musbotg_softc *); 133 static void musbotg_root_intr(struct musbotg_softc *); 134 static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td); 135 static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td); 136 static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on); 137 138 /* 139 * Here is a configuration that the chip supports. 140 */ 141 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = { 142 143 [0] = { 144 .max_in_frame_size = 64,/* fixed */ 145 .max_out_frame_size = 64, /* fixed */ 146 .is_simplex = 1, 147 .support_control = 1, 148 } 149 }; 150 151 static int 152 musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td) 153 { 154 int ch; 155 int ep; 156 157 ep = td->ep_no; 158 159 /* In device mode each EP got its own channel */ 160 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 161 musbotg_ep_int_set(sc, ep, 1); 162 return (ep); 163 } 164 165 /* 166 * All control transactions go through EP0 167 */ 168 if (ep == 0) { 169 if (sc->sc_channel_mask & (1 << 0)) 170 return (-1); 171 sc->sc_channel_mask |= (1 << 0); 172 musbotg_ep_int_set(sc, ep, 1); 173 return (0); 174 } 175 176 for (ch = 1; ch < MUSB2_EP_MAX; ch++) { 177 if (!(sc->sc_channel_mask & (1 << ch))) { 178 sc->sc_channel_mask |= (1 << ch); 179 musbotg_ep_int_set(sc, ch, 1); 180 return (ch); 181 } 182 } 183 184 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask); 185 186 return (-1); 187 } 188 189 static void 190 musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td) 191 { 192 193 DPRINTFN(1, "ep_no=%d\n", td->channel); 194 195 if (sc->sc_mode == MUSB2_DEVICE_MODE) 196 return; 197 198 if (td == NULL) 199 return; 200 if (td->channel == -1) 201 return; 202 203 musbotg_ep_int_set(sc, td->channel, 0); 204 sc->sc_channel_mask &= ~(1 << td->channel); 205 206 td->channel = -1; 207 } 208 209 static void 210 musbotg_get_hw_ep_profile(struct usb_device *udev, 211 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 212 { 213 struct musbotg_softc *sc; 214 215 sc = MUSBOTG_BUS2SC(udev->bus); 216 217 if (ep_addr == 0) { 218 /* control endpoint */ 219 *ppf = musbotg_ep_profile; 220 } else if (ep_addr <= sc->sc_ep_max) { 221 /* other endpoints */ 222 *ppf = sc->sc_hw_ep_profile + ep_addr; 223 } else { 224 *ppf = NULL; 225 } 226 } 227 228 static void 229 musbotg_clocks_on(struct musbotg_softc *sc) 230 { 231 if (sc->sc_flags.clocks_off && 232 sc->sc_flags.port_powered) { 233 234 DPRINTFN(4, "\n"); 235 236 if (sc->sc_clocks_on) { 237 (sc->sc_clocks_on) (sc->sc_clocks_arg); 238 } 239 sc->sc_flags.clocks_off = 0; 240 241 /* XXX enable Transceiver */ 242 } 243 } 244 245 static void 246 musbotg_clocks_off(struct musbotg_softc *sc) 247 { 248 if (!sc->sc_flags.clocks_off) { 249 250 DPRINTFN(4, "\n"); 251 252 /* XXX disable Transceiver */ 253 254 if (sc->sc_clocks_off) { 255 (sc->sc_clocks_off) (sc->sc_clocks_arg); 256 } 257 sc->sc_flags.clocks_off = 1; 258 } 259 } 260 261 static void 262 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on) 263 { 264 uint8_t temp; 265 266 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 267 if (on) 268 temp |= MUSB2_MASK_SOFTC; 269 else 270 temp &= ~MUSB2_MASK_SOFTC; 271 272 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 273 } 274 275 static void 276 musbotg_pull_up(struct musbotg_softc *sc) 277 { 278 /* pullup D+, if possible */ 279 280 if (!sc->sc_flags.d_pulled_up && 281 sc->sc_flags.port_powered) { 282 sc->sc_flags.d_pulled_up = 1; 283 musbotg_pull_common(sc, 1); 284 } 285 } 286 287 static void 288 musbotg_pull_down(struct musbotg_softc *sc) 289 { 290 /* pulldown D+, if possible */ 291 292 if (sc->sc_flags.d_pulled_up) { 293 sc->sc_flags.d_pulled_up = 0; 294 musbotg_pull_common(sc, 0); 295 } 296 } 297 298 static void 299 musbotg_suspend_host(struct musbotg_softc *sc) 300 { 301 uint8_t temp; 302 303 if (sc->sc_flags.status_suspend) { 304 return; 305 } 306 307 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 308 temp |= MUSB2_MASK_SUSPMODE; 309 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 310 sc->sc_flags.status_suspend = 1; 311 } 312 313 static void 314 musbotg_wakeup_host(struct musbotg_softc *sc) 315 { 316 uint8_t temp; 317 318 if (!(sc->sc_flags.status_suspend)) { 319 return; 320 } 321 322 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 323 temp &= ~MUSB2_MASK_SUSPMODE; 324 temp |= MUSB2_MASK_RESUME; 325 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 326 327 /* wait 20 milliseconds */ 328 /* Wait for reset to complete. */ 329 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 330 331 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 332 temp &= ~MUSB2_MASK_RESUME; 333 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 334 335 sc->sc_flags.status_suspend = 0; 336 } 337 338 static void 339 musbotg_wakeup_peer(struct musbotg_softc *sc) 340 { 341 uint8_t temp; 342 343 if (!(sc->sc_flags.status_suspend)) { 344 return; 345 } 346 347 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 348 temp |= MUSB2_MASK_RESUME; 349 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 350 351 /* wait 8 milliseconds */ 352 /* Wait for reset to complete. */ 353 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 354 355 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 356 temp &= ~MUSB2_MASK_RESUME; 357 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp); 358 } 359 360 static void 361 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr) 362 { 363 DPRINTFN(4, "addr=%d\n", addr); 364 addr &= 0x7F; 365 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr); 366 } 367 368 static uint8_t 369 musbotg_dev_ctrl_setup_rx(struct musbotg_td *td) 370 { 371 struct musbotg_softc *sc; 372 struct usb_device_request req; 373 uint16_t count; 374 uint8_t csr; 375 376 /* get pointer to softc */ 377 sc = MUSBOTG_PC2SC(td->pc); 378 379 if (td->channel == -1) 380 td->channel = musbotg_channel_alloc(sc, td); 381 382 /* EP0 is busy, wait */ 383 if (td->channel == -1) 384 return (1); 385 386 DPRINTFN(1, "ep_no=%d\n", td->channel); 387 388 /* select endpoint 0 */ 389 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 390 391 /* read out FIFO status */ 392 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 393 394 DPRINTFN(4, "csr=0x%02x\n", csr); 395 396 /* 397 * NOTE: If DATAEND is set we should not call the 398 * callback, hence the status stage is not complete. 399 */ 400 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 401 /* do not stall at this point */ 402 td->did_stall = 1; 403 /* wait for interrupt */ 404 DPRINTFN(0, "CSR0 DATAEND\n"); 405 goto not_complete; 406 } 407 408 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) { 409 /* clear SENTSTALL */ 410 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 411 /* get latest status */ 412 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 413 /* update EP0 state */ 414 sc->sc_ep0_busy = 0; 415 } 416 if (csr & MUSB2_MASK_CSR0L_SETUPEND) { 417 /* clear SETUPEND */ 418 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 419 MUSB2_MASK_CSR0L_SETUPEND_CLR); 420 /* get latest status */ 421 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 422 /* update EP0 state */ 423 sc->sc_ep0_busy = 0; 424 } 425 if (sc->sc_ep0_busy) { 426 DPRINTFN(0, "EP0 BUSY\n"); 427 goto not_complete; 428 } 429 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 430 goto not_complete; 431 } 432 /* clear did stall flag */ 433 td->did_stall = 0; 434 /* get the packet byte count */ 435 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 436 437 /* verify data length */ 438 if (count != td->remainder) { 439 DPRINTFN(0, "Invalid SETUP packet " 440 "length, %d bytes\n", count); 441 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 442 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 443 goto not_complete; 444 } 445 if (count != sizeof(req)) { 446 DPRINTFN(0, "Unsupported SETUP packet " 447 "length, %d bytes\n", count); 448 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 449 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 450 goto not_complete; 451 } 452 /* receive data */ 453 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 454 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 455 456 /* copy data into real buffer */ 457 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 458 459 td->offset = sizeof(req); 460 td->remainder = 0; 461 462 /* set pending command */ 463 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 464 465 /* we need set stall or dataend after this */ 466 sc->sc_ep0_busy = 1; 467 468 /* sneak peek the set address */ 469 if ((req.bmRequestType == UT_WRITE_DEVICE) && 470 (req.bRequest == UR_SET_ADDRESS)) { 471 sc->sc_dv_addr = req.wValue[0] & 0x7F; 472 } else { 473 sc->sc_dv_addr = 0xFF; 474 } 475 476 musbotg_channel_free(sc, td); 477 return (0); /* complete */ 478 479 not_complete: 480 /* abort any ongoing transfer */ 481 if (!td->did_stall) { 482 DPRINTFN(4, "stalling\n"); 483 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 484 MUSB2_MASK_CSR0L_SENDSTALL); 485 td->did_stall = 1; 486 } 487 return (1); /* not complete */ 488 } 489 490 static uint8_t 491 musbotg_host_ctrl_setup_tx(struct musbotg_td *td) 492 { 493 struct musbotg_softc *sc; 494 struct usb_device_request req; 495 uint8_t csr, csrh; 496 497 /* get pointer to softc */ 498 sc = MUSBOTG_PC2SC(td->pc); 499 500 if (td->channel == -1) 501 td->channel = musbotg_channel_alloc(sc, td); 502 503 /* EP0 is busy, wait */ 504 if (td->channel == -1) 505 return (1); 506 507 DPRINTFN(1, "ep_no=%d\n", td->channel); 508 509 /* select endpoint 0 */ 510 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 511 512 /* read out FIFO status */ 513 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 514 DPRINTFN(4, "csr=0x%02x\n", csr); 515 516 /* Not ready yet yet */ 517 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 518 return (1); 519 520 /* Failed */ 521 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 522 MUSB2_MASK_CSR0L_ERROR)) 523 { 524 /* Clear status bit */ 525 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 526 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 527 td->error = 1; 528 } 529 530 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 531 DPRINTFN(1, "NAK timeout\n"); 532 533 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 534 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 535 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 536 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 537 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 538 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 539 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 540 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 541 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 542 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 543 } 544 } 545 546 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 547 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 548 549 td->error = 1; 550 } 551 552 if (td->error) { 553 musbotg_channel_free(sc, td); 554 return (0); 555 } 556 557 /* Fifo is not empty and there is no NAK timeout */ 558 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 559 return (1); 560 561 /* check if we are complete */ 562 if (td->remainder == 0) { 563 /* we are complete */ 564 musbotg_channel_free(sc, td); 565 return (0); 566 } 567 568 /* copy data into real buffer */ 569 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 570 571 /* send data */ 572 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 573 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req)); 574 575 /* update offset and remainder */ 576 td->offset += sizeof(req); 577 td->remainder -= sizeof(req); 578 579 580 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 581 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 582 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 583 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 584 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 585 586 /* write command */ 587 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 588 MUSB2_MASK_CSR0L_TXPKTRDY | 589 MUSB2_MASK_CSR0L_SETUPPKT); 590 591 /* Just to be consistent, not used above */ 592 td->transaction_started = 1; 593 594 return (1); /* in progress */ 595 } 596 597 /* Control endpoint only data handling functions (RX/TX/SYNC) */ 598 599 static uint8_t 600 musbotg_dev_ctrl_data_rx(struct musbotg_td *td) 601 { 602 struct usb_page_search buf_res; 603 struct musbotg_softc *sc; 604 uint16_t count; 605 uint8_t csr; 606 uint8_t got_short; 607 608 /* get pointer to softc */ 609 sc = MUSBOTG_PC2SC(td->pc); 610 611 /* select endpoint 0 */ 612 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 613 614 /* check if a command is pending */ 615 if (sc->sc_ep0_cmd) { 616 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 617 sc->sc_ep0_cmd = 0; 618 } 619 /* read out FIFO status */ 620 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 621 622 DPRINTFN(4, "csr=0x%02x\n", csr); 623 624 got_short = 0; 625 626 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 627 MUSB2_MASK_CSR0L_SENTSTALL)) { 628 if (td->remainder == 0) { 629 /* 630 * We are actually complete and have 631 * received the next SETUP 632 */ 633 DPRINTFN(4, "faking complete\n"); 634 return (0); /* complete */ 635 } 636 /* 637 * USB Host Aborted the transfer. 638 */ 639 td->error = 1; 640 return (0); /* complete */ 641 } 642 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) { 643 return (1); /* not complete */ 644 } 645 /* get the packet byte count */ 646 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 647 648 /* verify the packet byte count */ 649 if (count != td->max_frame_size) { 650 if (count < td->max_frame_size) { 651 /* we have a short packet */ 652 td->short_pkt = 1; 653 got_short = 1; 654 } else { 655 /* invalid USB packet */ 656 td->error = 1; 657 return (0); /* we are complete */ 658 } 659 } 660 /* verify the packet byte count */ 661 if (count > td->remainder) { 662 /* invalid USB packet */ 663 td->error = 1; 664 return (0); /* we are complete */ 665 } 666 while (count > 0) { 667 uint32_t temp; 668 669 usbd_get_page(td->pc, td->offset, &buf_res); 670 671 /* get correct length */ 672 if (buf_res.length > count) { 673 buf_res.length = count; 674 } 675 /* check for unaligned memory address */ 676 if (USB_P2U(buf_res.buffer) & 3) { 677 678 temp = count & ~3; 679 680 if (temp) { 681 /* receive data 4 bytes at a time */ 682 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 683 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 684 temp / 4); 685 } 686 temp = count & 3; 687 if (temp) { 688 /* receive data 1 byte at a time */ 689 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 690 MUSB2_REG_EPFIFO(0), 691 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 692 } 693 usbd_copy_in(td->pc, td->offset, 694 sc->sc_bounce_buf, count); 695 696 /* update offset and remainder */ 697 td->offset += count; 698 td->remainder -= count; 699 break; 700 } 701 /* check if we can optimise */ 702 if (buf_res.length >= 4) { 703 704 /* receive data 4 bytes at a time */ 705 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 706 MUSB2_REG_EPFIFO(0), buf_res.buffer, 707 buf_res.length / 4); 708 709 temp = buf_res.length & ~3; 710 711 /* update counters */ 712 count -= temp; 713 td->offset += temp; 714 td->remainder -= temp; 715 continue; 716 } 717 /* receive data */ 718 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 719 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 720 721 /* update counters */ 722 count -= buf_res.length; 723 td->offset += buf_res.length; 724 td->remainder -= buf_res.length; 725 } 726 727 /* check if we are complete */ 728 if ((td->remainder == 0) || got_short) { 729 if (td->short_pkt) { 730 /* we are complete */ 731 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR; 732 return (0); 733 } 734 /* else need to receive a zero length packet */ 735 } 736 /* write command - need more data */ 737 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 738 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 739 return (1); /* not complete */ 740 } 741 742 static uint8_t 743 musbotg_dev_ctrl_data_tx(struct musbotg_td *td) 744 { 745 struct usb_page_search buf_res; 746 struct musbotg_softc *sc; 747 uint16_t count; 748 uint8_t csr; 749 750 /* get pointer to softc */ 751 sc = MUSBOTG_PC2SC(td->pc); 752 753 /* select endpoint 0 */ 754 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 755 756 /* check if a command is pending */ 757 if (sc->sc_ep0_cmd) { 758 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 759 sc->sc_ep0_cmd = 0; 760 } 761 /* read out FIFO status */ 762 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 763 764 DPRINTFN(4, "csr=0x%02x\n", csr); 765 766 if (csr & (MUSB2_MASK_CSR0L_SETUPEND | 767 MUSB2_MASK_CSR0L_SENTSTALL)) { 768 /* 769 * The current transfer was aborted 770 * by the USB Host 771 */ 772 td->error = 1; 773 return (0); /* complete */ 774 } 775 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) { 776 return (1); /* not complete */ 777 } 778 count = td->max_frame_size; 779 if (td->remainder < count) { 780 /* we have a short packet */ 781 td->short_pkt = 1; 782 count = td->remainder; 783 } 784 while (count > 0) { 785 uint32_t temp; 786 787 usbd_get_page(td->pc, td->offset, &buf_res); 788 789 /* get correct length */ 790 if (buf_res.length > count) { 791 buf_res.length = count; 792 } 793 /* check for unaligned memory address */ 794 if (USB_P2U(buf_res.buffer) & 3) { 795 796 usbd_copy_out(td->pc, td->offset, 797 sc->sc_bounce_buf, count); 798 799 temp = count & ~3; 800 801 if (temp) { 802 /* transmit data 4 bytes at a time */ 803 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 804 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 805 temp / 4); 806 } 807 temp = count & 3; 808 if (temp) { 809 /* receive data 1 byte at a time */ 810 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 811 MUSB2_REG_EPFIFO(0), 812 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 813 } 814 /* update offset and remainder */ 815 td->offset += count; 816 td->remainder -= count; 817 break; 818 } 819 /* check if we can optimise */ 820 if (buf_res.length >= 4) { 821 822 /* transmit data 4 bytes at a time */ 823 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 824 MUSB2_REG_EPFIFO(0), buf_res.buffer, 825 buf_res.length / 4); 826 827 temp = buf_res.length & ~3; 828 829 /* update counters */ 830 count -= temp; 831 td->offset += temp; 832 td->remainder -= temp; 833 continue; 834 } 835 /* transmit data */ 836 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 837 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 838 839 /* update counters */ 840 count -= buf_res.length; 841 td->offset += buf_res.length; 842 td->remainder -= buf_res.length; 843 } 844 845 /* check remainder */ 846 if (td->remainder == 0) { 847 if (td->short_pkt) { 848 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY; 849 return (0); /* complete */ 850 } 851 /* else we need to transmit a short packet */ 852 } 853 /* write command */ 854 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 855 MUSB2_MASK_CSR0L_TXPKTRDY); 856 857 return (1); /* not complete */ 858 } 859 860 static uint8_t 861 musbotg_host_ctrl_data_rx(struct musbotg_td *td) 862 { 863 struct usb_page_search buf_res; 864 struct musbotg_softc *sc; 865 uint16_t count; 866 uint8_t csr; 867 uint8_t got_short; 868 869 /* get pointer to softc */ 870 sc = MUSBOTG_PC2SC(td->pc); 871 872 if (td->channel == -1) 873 td->channel = musbotg_channel_alloc(sc, td); 874 875 /* EP0 is busy, wait */ 876 if (td->channel == -1) 877 return (1); 878 879 DPRINTFN(1, "ep_no=%d\n", td->channel); 880 881 /* select endpoint 0 */ 882 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 883 884 /* read out FIFO status */ 885 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 886 887 DPRINTFN(4, "csr=0x%02x\n", csr); 888 889 got_short = 0; 890 if (!td->transaction_started) { 891 td->transaction_started = 1; 892 893 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 894 895 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 896 td->dev_addr); 897 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 898 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 899 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 900 901 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 902 MUSB2_MASK_CSR0L_REQPKT); 903 904 return (1); 905 } 906 907 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 908 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 909 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 910 911 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 912 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 913 914 td->error = 1; 915 } 916 917 /* Failed */ 918 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 919 MUSB2_MASK_CSR0L_ERROR)) 920 { 921 /* Clear status bit */ 922 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 923 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 924 td->error = 1; 925 } 926 927 if (td->error) { 928 musbotg_channel_free(sc, td); 929 return (0); /* we are complete */ 930 } 931 932 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) 933 return (1); /* not yet */ 934 935 /* get the packet byte count */ 936 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 937 938 /* verify the packet byte count */ 939 if (count != td->max_frame_size) { 940 if (count < td->max_frame_size) { 941 /* we have a short packet */ 942 td->short_pkt = 1; 943 got_short = 1; 944 } else { 945 /* invalid USB packet */ 946 td->error = 1; 947 musbotg_channel_free(sc, td); 948 return (0); /* we are complete */ 949 } 950 } 951 /* verify the packet byte count */ 952 if (count > td->remainder) { 953 /* invalid USB packet */ 954 td->error = 1; 955 musbotg_channel_free(sc, td); 956 return (0); /* we are complete */ 957 } 958 while (count > 0) { 959 uint32_t temp; 960 961 usbd_get_page(td->pc, td->offset, &buf_res); 962 963 /* get correct length */ 964 if (buf_res.length > count) { 965 buf_res.length = count; 966 } 967 /* check for unaligned memory address */ 968 if (USB_P2U(buf_res.buffer) & 3) { 969 970 temp = count & ~3; 971 972 if (temp) { 973 /* receive data 4 bytes at a time */ 974 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 975 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf, 976 temp / 4); 977 } 978 temp = count & 3; 979 if (temp) { 980 /* receive data 1 byte at a time */ 981 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 982 MUSB2_REG_EPFIFO(0), 983 (void *)(&sc->sc_bounce_buf[count / 4]), temp); 984 } 985 usbd_copy_in(td->pc, td->offset, 986 sc->sc_bounce_buf, count); 987 988 /* update offset and remainder */ 989 td->offset += count; 990 td->remainder -= count; 991 break; 992 } 993 /* check if we can optimise */ 994 if (buf_res.length >= 4) { 995 996 /* receive data 4 bytes at a time */ 997 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 998 MUSB2_REG_EPFIFO(0), buf_res.buffer, 999 buf_res.length / 4); 1000 1001 temp = buf_res.length & ~3; 1002 1003 /* update counters */ 1004 count -= temp; 1005 td->offset += temp; 1006 td->remainder -= temp; 1007 continue; 1008 } 1009 /* receive data */ 1010 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1011 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length); 1012 1013 /* update counters */ 1014 count -= buf_res.length; 1015 td->offset += buf_res.length; 1016 td->remainder -= buf_res.length; 1017 } 1018 1019 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY; 1020 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1021 1022 /* check if we are complete */ 1023 if ((td->remainder == 0) || got_short) { 1024 if (td->short_pkt) { 1025 /* we are complete */ 1026 1027 musbotg_channel_free(sc, td); 1028 return (0); 1029 } 1030 /* else need to receive a zero length packet */ 1031 } 1032 1033 td->transaction_started = 1; 1034 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1035 MUSB2_MASK_CSR0L_REQPKT); 1036 1037 return (1); /* not complete */ 1038 } 1039 1040 static uint8_t 1041 musbotg_host_ctrl_data_tx(struct musbotg_td *td) 1042 { 1043 struct usb_page_search buf_res; 1044 struct musbotg_softc *sc; 1045 uint16_t count; 1046 uint8_t csr, csrh; 1047 1048 /* get pointer to softc */ 1049 sc = MUSBOTG_PC2SC(td->pc); 1050 1051 if (td->channel == -1) 1052 td->channel = musbotg_channel_alloc(sc, td); 1053 1054 /* No free EPs */ 1055 if (td->channel == -1) 1056 return (1); 1057 1058 DPRINTFN(1, "ep_no=%d\n", td->channel); 1059 1060 /* select endpoint */ 1061 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1062 1063 /* read out FIFO status */ 1064 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1065 DPRINTFN(4, "csr=0x%02x\n", csr); 1066 1067 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1068 MUSB2_MASK_CSR0L_ERROR)) { 1069 /* clear status bits */ 1070 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1071 td->error = 1; 1072 } 1073 1074 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) { 1075 1076 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1077 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1078 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1079 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1080 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1081 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1082 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 1083 csrh |= MUSB2_MASK_CSR0H_FFLUSH; 1084 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 1085 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1086 } 1087 } 1088 1089 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1090 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1091 1092 td->error = 1; 1093 } 1094 1095 1096 if (td->error) { 1097 musbotg_channel_free(sc, td); 1098 return (0); /* complete */ 1099 } 1100 1101 /* 1102 * Wait while FIFO is empty. 1103 * Do not flush it because it will cause transactions 1104 * with size more then packet size. It might upset 1105 * some devices 1106 */ 1107 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) 1108 return (1); 1109 1110 /* Packet still being processed */ 1111 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1112 return (1); 1113 1114 if (td->transaction_started) { 1115 /* check remainder */ 1116 if (td->remainder == 0) { 1117 if (td->short_pkt) { 1118 musbotg_channel_free(sc, td); 1119 return (0); /* complete */ 1120 } 1121 /* else we need to transmit a short packet */ 1122 } 1123 1124 /* We're not complete - more transactions required */ 1125 td->transaction_started = 0; 1126 } 1127 1128 /* check for short packet */ 1129 count = td->max_frame_size; 1130 if (td->remainder < count) { 1131 /* we have a short packet */ 1132 td->short_pkt = 1; 1133 count = td->remainder; 1134 } 1135 1136 while (count > 0) { 1137 uint32_t temp; 1138 1139 usbd_get_page(td->pc, td->offset, &buf_res); 1140 1141 /* get correct length */ 1142 if (buf_res.length > count) { 1143 buf_res.length = count; 1144 } 1145 /* check for unaligned memory address */ 1146 if (USB_P2U(buf_res.buffer) & 3) { 1147 1148 usbd_copy_out(td->pc, td->offset, 1149 sc->sc_bounce_buf, count); 1150 1151 temp = count & ~3; 1152 1153 if (temp) { 1154 /* transmit data 4 bytes at a time */ 1155 bus_space_write_multi_4(sc->sc_io_tag, 1156 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0), 1157 sc->sc_bounce_buf, temp / 4); 1158 } 1159 temp = count & 3; 1160 if (temp) { 1161 /* receive data 1 byte at a time */ 1162 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1163 MUSB2_REG_EPFIFO(0), 1164 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1165 } 1166 /* update offset and remainder */ 1167 td->offset += count; 1168 td->remainder -= count; 1169 break; 1170 } 1171 /* check if we can optimise */ 1172 if (buf_res.length >= 4) { 1173 1174 /* transmit data 4 bytes at a time */ 1175 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1176 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1177 buf_res.length / 4); 1178 1179 temp = buf_res.length & ~3; 1180 1181 /* update counters */ 1182 count -= temp; 1183 td->offset += temp; 1184 td->remainder -= temp; 1185 continue; 1186 } 1187 /* transmit data */ 1188 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1189 MUSB2_REG_EPFIFO(0), buf_res.buffer, 1190 buf_res.length); 1191 1192 /* update counters */ 1193 count -= buf_res.length; 1194 td->offset += buf_res.length; 1195 td->remainder -= buf_res.length; 1196 } 1197 1198 /* Function address */ 1199 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1200 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1201 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1202 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1203 1204 /* TX NAK timeout */ 1205 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1206 1207 /* write command */ 1208 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1209 MUSB2_MASK_CSR0L_TXPKTRDY); 1210 1211 td->transaction_started = 1; 1212 1213 return (1); /* not complete */ 1214 } 1215 1216 static uint8_t 1217 musbotg_dev_ctrl_status(struct musbotg_td *td) 1218 { 1219 struct musbotg_softc *sc; 1220 uint8_t csr; 1221 1222 /* get pointer to softc */ 1223 sc = MUSBOTG_PC2SC(td->pc); 1224 1225 /* select endpoint 0 */ 1226 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1227 1228 if (sc->sc_ep0_busy) { 1229 sc->sc_ep0_busy = 0; 1230 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND; 1231 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd); 1232 sc->sc_ep0_cmd = 0; 1233 } 1234 /* read out FIFO status */ 1235 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1236 1237 DPRINTFN(4, "csr=0x%02x\n", csr); 1238 1239 if (csr & MUSB2_MASK_CSR0L_DATAEND) { 1240 /* wait for interrupt */ 1241 return (1); /* not complete */ 1242 } 1243 if (sc->sc_dv_addr != 0xFF) { 1244 /* write function address */ 1245 musbotg_set_address(sc, sc->sc_dv_addr); 1246 } 1247 1248 musbotg_channel_free(sc, td); 1249 return (0); /* complete */ 1250 } 1251 1252 static uint8_t 1253 musbotg_host_ctrl_status_rx(struct musbotg_td *td) 1254 { 1255 struct musbotg_softc *sc; 1256 uint8_t csr, csrh; 1257 1258 /* get pointer to softc */ 1259 sc = MUSBOTG_PC2SC(td->pc); 1260 1261 if (td->channel == -1) 1262 td->channel = musbotg_channel_alloc(sc, td); 1263 1264 /* EP0 is busy, wait */ 1265 if (td->channel == -1) 1266 return (1); 1267 1268 DPRINTFN(1, "ep_no=%d\n", td->channel); 1269 1270 /* select endpoint 0 */ 1271 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1272 1273 if (!td->transaction_started) { 1274 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0), 1275 td->dev_addr); 1276 1277 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr); 1278 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport); 1279 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1280 1281 /* RX NAK timeout */ 1282 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1283 1284 td->transaction_started = 1; 1285 1286 /* Disable PING */ 1287 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1288 csrh |= MUSB2_MASK_CSR0H_PING_DIS; 1289 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1290 1291 /* write command */ 1292 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1293 MUSB2_MASK_CSR0L_STATUSPKT | 1294 MUSB2_MASK_CSR0L_REQPKT); 1295 1296 return (1); /* Just started */ 1297 1298 } 1299 1300 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1301 1302 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr); 1303 1304 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) { 1305 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1306 MUSB2_MASK_CSR0L_RXPKTRDY_CLR); 1307 musbotg_channel_free(sc, td); 1308 return (0); /* complete */ 1309 } 1310 1311 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1312 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT | 1313 MUSB2_MASK_CSR0L_REQPKT); 1314 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1315 1316 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1317 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1318 td->error = 1; 1319 } 1320 1321 /* Failed */ 1322 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1323 MUSB2_MASK_CSR0L_ERROR)) 1324 { 1325 /* Clear status bit */ 1326 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1327 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1328 td->error = 1; 1329 } 1330 1331 if (td->error) { 1332 musbotg_channel_free(sc, td); 1333 return (0); 1334 } 1335 1336 return (1); /* Not ready yet */ 1337 } 1338 1339 static uint8_t 1340 musbotg_host_ctrl_status_tx(struct musbotg_td *td) 1341 { 1342 struct musbotg_softc *sc; 1343 uint8_t csr; 1344 1345 /* get pointer to softc */ 1346 sc = MUSBOTG_PC2SC(td->pc); 1347 1348 if (td->channel == -1) 1349 td->channel = musbotg_channel_alloc(sc, td); 1350 1351 /* EP0 is busy, wait */ 1352 if (td->channel == -1) 1353 return (1); 1354 1355 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started, 1356 td->dev_addr,td->haddr,td->hport, td->transfer_type); 1357 1358 /* select endpoint 0 */ 1359 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 1360 1361 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1362 DPRINTFN(4, "csr=0x%02x\n", csr); 1363 1364 /* Not yet */ 1365 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) 1366 return (1); 1367 1368 /* Failed */ 1369 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | 1370 MUSB2_MASK_CSR0L_ERROR)) 1371 { 1372 /* Clear status bit */ 1373 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1374 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr); 1375 td->error = 1; 1376 musbotg_channel_free(sc, td); 1377 return (0); /* complete */ 1378 } 1379 1380 if (td->transaction_started) { 1381 musbotg_channel_free(sc, td); 1382 return (0); /* complete */ 1383 } 1384 1385 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS); 1386 1387 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr); 1388 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr); 1389 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport); 1390 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 1391 1392 /* TX NAK timeout */ 1393 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 1394 1395 td->transaction_started = 1; 1396 1397 /* write command */ 1398 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1399 MUSB2_MASK_CSR0L_STATUSPKT | 1400 MUSB2_MASK_CSR0L_TXPKTRDY); 1401 1402 return (1); /* wait for interrupt */ 1403 } 1404 1405 static uint8_t 1406 musbotg_dev_data_rx(struct musbotg_td *td) 1407 { 1408 struct usb_page_search buf_res; 1409 struct musbotg_softc *sc; 1410 uint16_t count; 1411 uint8_t csr; 1412 uint8_t to; 1413 uint8_t got_short; 1414 1415 to = 8; /* don't loop forever! */ 1416 got_short = 0; 1417 1418 /* get pointer to softc */ 1419 sc = MUSBOTG_PC2SC(td->pc); 1420 1421 if (td->channel == -1) 1422 td->channel = musbotg_channel_alloc(sc, td); 1423 1424 /* EP0 is busy, wait */ 1425 if (td->channel == -1) 1426 return (1); 1427 1428 /* select endpoint */ 1429 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1430 1431 repeat: 1432 /* read out FIFO status */ 1433 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1434 1435 DPRINTFN(4, "csr=0x%02x\n", csr); 1436 1437 /* clear overrun */ 1438 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) { 1439 /* make sure we don't clear "RXPKTRDY" */ 1440 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1441 MUSB2_MASK_CSRL_RXPKTRDY); 1442 } 1443 1444 /* check status */ 1445 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) 1446 return (1); /* not complete */ 1447 1448 /* get the packet byte count */ 1449 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1450 1451 DPRINTFN(4, "count=0x%04x\n", count); 1452 1453 /* 1454 * Check for short or invalid packet: 1455 */ 1456 if (count != td->max_frame_size) { 1457 if (count < td->max_frame_size) { 1458 /* we have a short packet */ 1459 td->short_pkt = 1; 1460 got_short = 1; 1461 } else { 1462 /* invalid USB packet */ 1463 td->error = 1; 1464 musbotg_channel_free(sc, td); 1465 return (0); /* we are complete */ 1466 } 1467 } 1468 /* verify the packet byte count */ 1469 if (count > td->remainder) { 1470 /* invalid USB packet */ 1471 td->error = 1; 1472 musbotg_channel_free(sc, td); 1473 return (0); /* we are complete */ 1474 } 1475 while (count > 0) { 1476 uint32_t temp; 1477 1478 usbd_get_page(td->pc, td->offset, &buf_res); 1479 1480 /* get correct length */ 1481 if (buf_res.length > count) { 1482 buf_res.length = count; 1483 } 1484 /* check for unaligned memory address */ 1485 if (USB_P2U(buf_res.buffer) & 3) { 1486 1487 temp = count & ~3; 1488 1489 if (temp) { 1490 /* receive data 4 bytes at a time */ 1491 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1492 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1493 temp / 4); 1494 } 1495 temp = count & 3; 1496 if (temp) { 1497 /* receive data 1 byte at a time */ 1498 bus_space_read_multi_1(sc->sc_io_tag, 1499 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1500 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1501 } 1502 usbd_copy_in(td->pc, td->offset, 1503 sc->sc_bounce_buf, count); 1504 1505 /* update offset and remainder */ 1506 td->offset += count; 1507 td->remainder -= count; 1508 break; 1509 } 1510 /* check if we can optimise */ 1511 if (buf_res.length >= 4) { 1512 1513 /* receive data 4 bytes at a time */ 1514 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1515 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1516 buf_res.length / 4); 1517 1518 temp = buf_res.length & ~3; 1519 1520 /* update counters */ 1521 count -= temp; 1522 td->offset += temp; 1523 td->remainder -= temp; 1524 continue; 1525 } 1526 /* receive data */ 1527 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1528 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1529 buf_res.length); 1530 1531 /* update counters */ 1532 count -= buf_res.length; 1533 td->offset += buf_res.length; 1534 td->remainder -= buf_res.length; 1535 } 1536 1537 /* clear status bits */ 1538 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1539 1540 /* check if we are complete */ 1541 if ((td->remainder == 0) || got_short) { 1542 if (td->short_pkt) { 1543 /* we are complete */ 1544 musbotg_channel_free(sc, td); 1545 return (0); 1546 } 1547 /* else need to receive a zero length packet */ 1548 } 1549 if (--to) { 1550 goto repeat; 1551 } 1552 return (1); /* not complete */ 1553 } 1554 1555 static uint8_t 1556 musbotg_dev_data_tx(struct musbotg_td *td) 1557 { 1558 struct usb_page_search buf_res; 1559 struct musbotg_softc *sc; 1560 uint16_t count; 1561 uint8_t csr; 1562 uint8_t to; 1563 1564 to = 8; /* don't loop forever! */ 1565 1566 /* get pointer to softc */ 1567 sc = MUSBOTG_PC2SC(td->pc); 1568 1569 if (td->channel == -1) 1570 td->channel = musbotg_channel_alloc(sc, td); 1571 1572 /* EP0 is busy, wait */ 1573 if (td->channel == -1) 1574 return (1); 1575 1576 /* select endpoint */ 1577 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1578 1579 repeat: 1580 1581 /* read out FIFO status */ 1582 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1583 1584 DPRINTFN(4, "csr=0x%02x\n", csr); 1585 1586 if (csr & (MUSB2_MASK_CSRL_TXINCOMP | 1587 MUSB2_MASK_CSRL_TXUNDERRUN)) { 1588 /* clear status bits */ 1589 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1590 } 1591 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) { 1592 return (1); /* not complete */ 1593 } 1594 /* check for short packet */ 1595 count = td->max_frame_size; 1596 if (td->remainder < count) { 1597 /* we have a short packet */ 1598 td->short_pkt = 1; 1599 count = td->remainder; 1600 } 1601 while (count > 0) { 1602 uint32_t temp; 1603 1604 usbd_get_page(td->pc, td->offset, &buf_res); 1605 1606 /* get correct length */ 1607 if (buf_res.length > count) { 1608 buf_res.length = count; 1609 } 1610 /* check for unaligned memory address */ 1611 if (USB_P2U(buf_res.buffer) & 3) { 1612 1613 usbd_copy_out(td->pc, td->offset, 1614 sc->sc_bounce_buf, count); 1615 1616 temp = count & ~3; 1617 1618 if (temp) { 1619 /* transmit data 4 bytes at a time */ 1620 bus_space_write_multi_4(sc->sc_io_tag, 1621 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1622 sc->sc_bounce_buf, temp / 4); 1623 } 1624 temp = count & 3; 1625 if (temp) { 1626 /* receive data 1 byte at a time */ 1627 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1628 MUSB2_REG_EPFIFO(td->channel), 1629 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1630 } 1631 /* update offset and remainder */ 1632 td->offset += count; 1633 td->remainder -= count; 1634 break; 1635 } 1636 /* check if we can optimise */ 1637 if (buf_res.length >= 4) { 1638 1639 /* transmit data 4 bytes at a time */ 1640 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1641 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1642 buf_res.length / 4); 1643 1644 temp = buf_res.length & ~3; 1645 1646 /* update counters */ 1647 count -= temp; 1648 td->offset += temp; 1649 td->remainder -= temp; 1650 continue; 1651 } 1652 /* transmit data */ 1653 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1654 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1655 buf_res.length); 1656 1657 /* update counters */ 1658 count -= buf_res.length; 1659 td->offset += buf_res.length; 1660 td->remainder -= buf_res.length; 1661 } 1662 1663 /* Max packet size */ 1664 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); 1665 1666 /* write command */ 1667 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 1668 MUSB2_MASK_CSRL_TXPKTRDY); 1669 1670 /* check remainder */ 1671 if (td->remainder == 0) { 1672 if (td->short_pkt) { 1673 musbotg_channel_free(sc, td); 1674 return (0); /* complete */ 1675 } 1676 /* else we need to transmit a short packet */ 1677 } 1678 if (--to) { 1679 goto repeat; 1680 } 1681 return (1); /* not complete */ 1682 } 1683 1684 static uint8_t 1685 musbotg_host_data_rx(struct musbotg_td *td) 1686 { 1687 struct usb_page_search buf_res; 1688 struct musbotg_softc *sc; 1689 uint16_t count; 1690 uint8_t csr, csrh; 1691 uint8_t to; 1692 uint8_t got_short; 1693 1694 /* get pointer to softc */ 1695 sc = MUSBOTG_PC2SC(td->pc); 1696 1697 if (td->channel == -1) 1698 td->channel = musbotg_channel_alloc(sc, td); 1699 1700 /* No free EPs */ 1701 if (td->channel == -1) 1702 return (1); 1703 1704 DPRINTFN(1, "ep_no=%d\n", td->channel); 1705 1706 to = 8; /* don't loop forever! */ 1707 got_short = 0; 1708 1709 /* select endpoint */ 1710 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1711 1712 repeat: 1713 /* read out FIFO status */ 1714 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 1715 DPRINTFN(4, "csr=0x%02x\n", csr); 1716 1717 if (!td->transaction_started) { 1718 /* Function address */ 1719 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel), 1720 td->dev_addr); 1721 1722 /* SPLIT transaction */ 1723 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel), 1724 td->haddr); 1725 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel), 1726 td->hport); 1727 1728 /* RX NAK timeout */ 1729 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) 1730 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0); 1731 else 1732 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO); 1733 1734 /* Protocol, speed, device endpoint */ 1735 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type); 1736 1737 /* Max packet size */ 1738 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet); 1739 1740 /* Data Toggle */ 1741 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH); 1742 DPRINTFN(4, "csrh=0x%02x\n", csrh); 1743 1744 csrh |= MUSB2_MASK_CSRH_RXDT_WREN; 1745 if (td->toggle) 1746 csrh |= MUSB2_MASK_CSRH_RXDT_VAL; 1747 else 1748 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1749 1750 /* Set data toggle */ 1751 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh); 1752 1753 /* write command */ 1754 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 1755 MUSB2_MASK_CSRL_RXREQPKT); 1756 1757 td->transaction_started = 1; 1758 return (1); 1759 } 1760 1761 /* clear NAK timeout */ 1762 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1763 DPRINTFN(4, "NAK Timeout\n"); 1764 if (csr & MUSB2_MASK_CSRL_RXREQPKT) { 1765 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1766 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1767 1768 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1769 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr); 1770 } 1771 1772 td->error = 1; 1773 } 1774 1775 if (csr & MUSB2_MASK_CSRL_RXERROR) { 1776 DPRINTFN(4, "RXERROR\n"); 1777 td->error = 1; 1778 } 1779 1780 if (csr & MUSB2_MASK_CSRL_RXSTALL) { 1781 DPRINTFN(4, "RXSTALL\n"); 1782 td->error = 1; 1783 } 1784 1785 if (td->error) { 1786 musbotg_channel_free(sc, td); 1787 return (0); /* we are complete */ 1788 } 1789 1790 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) { 1791 /* No data available yet */ 1792 return (1); 1793 } 1794 1795 td->toggle ^= 1; 1796 /* get the packet byte count */ 1797 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT); 1798 DPRINTFN(4, "count=0x%04x\n", count); 1799 1800 /* 1801 * Check for short or invalid packet: 1802 */ 1803 if (count != td->max_frame_size) { 1804 if (count < td->max_frame_size) { 1805 /* we have a short packet */ 1806 td->short_pkt = 1; 1807 got_short = 1; 1808 } else { 1809 /* invalid USB packet */ 1810 td->error = 1; 1811 musbotg_channel_free(sc, td); 1812 return (0); /* we are complete */ 1813 } 1814 } 1815 1816 /* verify the packet byte count */ 1817 if (count > td->remainder) { 1818 /* invalid USB packet */ 1819 td->error = 1; 1820 musbotg_channel_free(sc, td); 1821 return (0); /* we are complete */ 1822 } 1823 1824 while (count > 0) { 1825 uint32_t temp; 1826 1827 usbd_get_page(td->pc, td->offset, &buf_res); 1828 1829 /* get correct length */ 1830 if (buf_res.length > count) { 1831 buf_res.length = count; 1832 } 1833 /* check for unaligned memory address */ 1834 if (USB_P2U(buf_res.buffer) & 3) { 1835 1836 temp = count & ~3; 1837 1838 if (temp) { 1839 /* receive data 4 bytes at a time */ 1840 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1841 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf, 1842 temp / 4); 1843 } 1844 temp = count & 3; 1845 if (temp) { 1846 /* receive data 1 byte at a time */ 1847 bus_space_read_multi_1(sc->sc_io_tag, 1848 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 1849 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 1850 } 1851 usbd_copy_in(td->pc, td->offset, 1852 sc->sc_bounce_buf, count); 1853 1854 /* update offset and remainder */ 1855 td->offset += count; 1856 td->remainder -= count; 1857 break; 1858 } 1859 /* check if we can optimise */ 1860 if (buf_res.length >= 4) { 1861 1862 /* receive data 4 bytes at a time */ 1863 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 1864 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1865 buf_res.length / 4); 1866 1867 temp = buf_res.length & ~3; 1868 1869 /* update counters */ 1870 count -= temp; 1871 td->offset += temp; 1872 td->remainder -= temp; 1873 continue; 1874 } 1875 /* receive data */ 1876 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 1877 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 1878 buf_res.length); 1879 1880 /* update counters */ 1881 count -= buf_res.length; 1882 td->offset += buf_res.length; 1883 td->remainder -= buf_res.length; 1884 } 1885 1886 /* clear status bits */ 1887 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 1888 1889 /* check if we are complete */ 1890 if ((td->remainder == 0) || got_short) { 1891 if (td->short_pkt) { 1892 /* we are complete */ 1893 musbotg_channel_free(sc, td); 1894 return (0); 1895 } 1896 /* else need to receive a zero length packet */ 1897 } 1898 1899 /* Reset transaction state and restart */ 1900 td->transaction_started = 0; 1901 1902 if (--to) 1903 goto repeat; 1904 1905 return (1); /* not complete */ 1906 } 1907 1908 static uint8_t 1909 musbotg_host_data_tx(struct musbotg_td *td) 1910 { 1911 struct usb_page_search buf_res; 1912 struct musbotg_softc *sc; 1913 uint16_t count; 1914 uint8_t csr, csrh; 1915 1916 /* get pointer to softc */ 1917 sc = MUSBOTG_PC2SC(td->pc); 1918 1919 if (td->channel == -1) 1920 td->channel = musbotg_channel_alloc(sc, td); 1921 1922 /* No free EPs */ 1923 if (td->channel == -1) 1924 return (1); 1925 1926 DPRINTFN(1, "ep_no=%d\n", td->channel); 1927 1928 /* select endpoint */ 1929 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel); 1930 1931 /* read out FIFO status */ 1932 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1933 DPRINTFN(4, "csr=0x%02x\n", csr); 1934 1935 if (csr & (MUSB2_MASK_CSRL_TXSTALLED | 1936 MUSB2_MASK_CSRL_TXERROR)) { 1937 /* clear status bits */ 1938 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 1939 td->error = 1; 1940 musbotg_channel_free(sc, td); 1941 return (0); /* complete */ 1942 } 1943 1944 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 1945 /* 1946 * Flush TX FIFO before clearing NAK TO 1947 */ 1948 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1949 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1950 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1951 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1952 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 1953 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 1954 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1955 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 1956 } 1957 } 1958 1959 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 1960 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr); 1961 1962 td->error = 1; 1963 musbotg_channel_free(sc, td); 1964 return (0); /* complete */ 1965 } 1966 1967 /* 1968 * Wait while FIFO is empty. 1969 * Do not flush it because it will cause transactions 1970 * with size more then packet size. It might upset 1971 * some devices 1972 */ 1973 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) 1974 return (1); 1975 1976 /* Packet still being processed */ 1977 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) 1978 return (1); 1979 1980 if (td->transaction_started) { 1981 /* check remainder */ 1982 if (td->remainder == 0) { 1983 if (td->short_pkt) { 1984 musbotg_channel_free(sc, td); 1985 return (0); /* complete */ 1986 } 1987 /* else we need to transmit a short packet */ 1988 } 1989 1990 /* We're not complete - more transactions required */ 1991 td->transaction_started = 0; 1992 } 1993 1994 /* check for short packet */ 1995 count = td->max_frame_size; 1996 if (td->remainder < count) { 1997 /* we have a short packet */ 1998 td->short_pkt = 1; 1999 count = td->remainder; 2000 } 2001 2002 while (count > 0) { 2003 uint32_t temp; 2004 2005 usbd_get_page(td->pc, td->offset, &buf_res); 2006 2007 /* get correct length */ 2008 if (buf_res.length > count) { 2009 buf_res.length = count; 2010 } 2011 /* check for unaligned memory address */ 2012 if (USB_P2U(buf_res.buffer) & 3) { 2013 2014 usbd_copy_out(td->pc, td->offset, 2015 sc->sc_bounce_buf, count); 2016 2017 temp = count & ~3; 2018 2019 if (temp) { 2020 /* transmit data 4 bytes at a time */ 2021 bus_space_write_multi_4(sc->sc_io_tag, 2022 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel), 2023 sc->sc_bounce_buf, temp / 4); 2024 } 2025 temp = count & 3; 2026 if (temp) { 2027 /* receive data 1 byte at a time */ 2028 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2029 MUSB2_REG_EPFIFO(td->channel), 2030 ((void *)&sc->sc_bounce_buf[count / 4]), temp); 2031 } 2032 /* update offset and remainder */ 2033 td->offset += count; 2034 td->remainder -= count; 2035 break; 2036 } 2037 /* check if we can optimise */ 2038 if (buf_res.length >= 4) { 2039 2040 /* transmit data 4 bytes at a time */ 2041 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl, 2042 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2043 buf_res.length / 4); 2044 2045 temp = buf_res.length & ~3; 2046 2047 /* update counters */ 2048 count -= temp; 2049 td->offset += temp; 2050 td->remainder -= temp; 2051 continue; 2052 } 2053 /* transmit data */ 2054 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl, 2055 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer, 2056 buf_res.length); 2057 2058 /* update counters */ 2059 count -= buf_res.length; 2060 td->offset += buf_res.length; 2061 td->remainder -= buf_res.length; 2062 } 2063 2064 /* Function address */ 2065 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel), 2066 td->dev_addr); 2067 2068 /* SPLIT transaction */ 2069 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel), 2070 td->haddr); 2071 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel), 2072 td->hport); 2073 2074 /* TX NAK timeout */ 2075 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC) 2076 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0); 2077 else 2078 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO); 2079 2080 /* Protocol, speed, device endpoint */ 2081 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type); 2082 2083 /* Max packet size */ 2084 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet); 2085 2086 if (!td->transaction_started) { 2087 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH); 2088 DPRINTFN(4, "csrh=0x%02x\n", csrh); 2089 2090 csrh |= MUSB2_MASK_CSRH_TXDT_WREN; 2091 if (td->toggle) 2092 csrh |= MUSB2_MASK_CSRH_TXDT_VAL; 2093 else 2094 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2095 2096 /* Set data toggle */ 2097 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh); 2098 } 2099 2100 /* write command */ 2101 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2102 MUSB2_MASK_CSRL_TXPKTRDY); 2103 2104 /* Update Data Toggle */ 2105 td->toggle ^= 1; 2106 td->transaction_started = 1; 2107 2108 return (1); /* not complete */ 2109 } 2110 2111 static uint8_t 2112 musbotg_xfer_do_fifo(struct usb_xfer *xfer) 2113 { 2114 struct musbotg_softc *sc; 2115 struct musbotg_td *td; 2116 2117 DPRINTFN(8, "\n"); 2118 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2119 2120 td = xfer->td_transfer_cache; 2121 while (1) { 2122 2123 if ((td->func) (td)) { 2124 /* operation in progress */ 2125 break; 2126 } 2127 2128 if (((void *)td) == xfer->td_transfer_last) { 2129 goto done; 2130 } 2131 if (td->error) { 2132 goto done; 2133 } else if (td->remainder > 0) { 2134 /* 2135 * We had a short transfer. If there is no alternate 2136 * next, stop processing ! 2137 */ 2138 if (!td->alt_next) { 2139 goto done; 2140 } 2141 } 2142 /* 2143 * Fetch the next transfer descriptor and transfer 2144 * some flags to the next transfer descriptor 2145 */ 2146 td = td->obj_next; 2147 xfer->td_transfer_cache = td; 2148 } 2149 2150 return (1); /* not complete */ 2151 done: 2152 /* compute all actual lengths */ 2153 musbotg_standard_done(xfer); 2154 2155 return (0); /* complete */ 2156 } 2157 2158 static void 2159 musbotg_interrupt_poll(struct musbotg_softc *sc) 2160 { 2161 struct usb_xfer *xfer; 2162 2163 repeat: 2164 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2165 if (!musbotg_xfer_do_fifo(xfer)) { 2166 /* queue has been modified */ 2167 goto repeat; 2168 } 2169 } 2170 } 2171 2172 void 2173 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on) 2174 { 2175 DPRINTFN(4, "vbus = %u\n", is_on); 2176 2177 USB_BUS_LOCK(&sc->sc_bus); 2178 if (is_on) { 2179 if (!sc->sc_flags.status_vbus) { 2180 sc->sc_flags.status_vbus = 1; 2181 2182 /* complete root HUB interrupt endpoint */ 2183 musbotg_root_intr(sc); 2184 } 2185 } else { 2186 if (sc->sc_flags.status_vbus) { 2187 sc->sc_flags.status_vbus = 0; 2188 sc->sc_flags.status_bus_reset = 0; 2189 sc->sc_flags.status_suspend = 0; 2190 sc->sc_flags.change_suspend = 0; 2191 sc->sc_flags.change_connect = 1; 2192 2193 /* complete root HUB interrupt endpoint */ 2194 musbotg_root_intr(sc); 2195 } 2196 } 2197 2198 USB_BUS_UNLOCK(&sc->sc_bus); 2199 } 2200 2201 void 2202 musbotg_connect_interrupt(struct musbotg_softc *sc) 2203 { 2204 USB_BUS_LOCK(&sc->sc_bus); 2205 sc->sc_flags.change_connect = 1; 2206 2207 /* complete root HUB interrupt endpoint */ 2208 musbotg_root_intr(sc); 2209 USB_BUS_UNLOCK(&sc->sc_bus); 2210 } 2211 2212 void 2213 musbotg_interrupt(struct musbotg_softc *sc, 2214 uint16_t rxstat, uint16_t txstat, uint8_t stat) 2215 { 2216 uint16_t rx_status; 2217 uint16_t tx_status; 2218 uint8_t usb_status; 2219 uint8_t temp; 2220 uint8_t to = 2; 2221 2222 USB_BUS_LOCK(&sc->sc_bus); 2223 2224 repeat: 2225 2226 /* read all interrupt registers */ 2227 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB); 2228 2229 /* read all FIFO interrupts */ 2230 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX); 2231 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX); 2232 rx_status |= rxstat; 2233 tx_status |= txstat; 2234 usb_status |= stat; 2235 2236 /* Clear platform flags after first time */ 2237 rxstat = 0; 2238 txstat = 0; 2239 stat = 0; 2240 2241 /* check for any bus state change interrupts */ 2242 2243 if (usb_status & (MUSB2_MASK_IRESET | 2244 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 2245 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 2246 2247 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status); 2248 2249 if (usb_status & MUSB2_MASK_IRESET) { 2250 2251 /* set correct state */ 2252 sc->sc_flags.status_bus_reset = 1; 2253 sc->sc_flags.status_suspend = 0; 2254 sc->sc_flags.change_suspend = 0; 2255 sc->sc_flags.change_connect = 1; 2256 2257 /* determine line speed */ 2258 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER); 2259 if (temp & MUSB2_MASK_HSMODE) 2260 sc->sc_flags.status_high_speed = 1; 2261 else 2262 sc->sc_flags.status_high_speed = 0; 2263 2264 /* 2265 * After reset all interrupts are on and we need to 2266 * turn them off! 2267 */ 2268 temp = MUSB2_MASK_IRESET; 2269 /* disable resume interrupt */ 2270 temp &= ~MUSB2_MASK_IRESUME; 2271 /* enable suspend interrupt */ 2272 temp |= MUSB2_MASK_ISUSP; 2273 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2274 /* disable TX and RX interrupts */ 2275 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 2276 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 2277 } 2278 /* 2279 * If RXRSM and RXSUSP is set at the same time we interpret 2280 * that like RESUME. Resume is set when there is at least 3 2281 * milliseconds of inactivity on the USB BUS. 2282 */ 2283 if (usb_status & MUSB2_MASK_IRESUME) { 2284 if (sc->sc_flags.status_suspend) { 2285 sc->sc_flags.status_suspend = 0; 2286 sc->sc_flags.change_suspend = 1; 2287 2288 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2289 /* disable resume interrupt */ 2290 temp &= ~MUSB2_MASK_IRESUME; 2291 /* enable suspend interrupt */ 2292 temp |= MUSB2_MASK_ISUSP; 2293 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2294 } 2295 } else if (usb_status & MUSB2_MASK_ISUSP) { 2296 if (!sc->sc_flags.status_suspend) { 2297 sc->sc_flags.status_suspend = 1; 2298 sc->sc_flags.change_suspend = 1; 2299 2300 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE); 2301 /* disable suspend interrupt */ 2302 temp &= ~MUSB2_MASK_ISUSP; 2303 /* enable resume interrupt */ 2304 temp |= MUSB2_MASK_IRESUME; 2305 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp); 2306 } 2307 } 2308 if (usb_status & 2309 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) 2310 sc->sc_flags.change_connect = 1; 2311 2312 /* 2313 * Host Mode: There is no IRESET so assume bus is 2314 * always in reset state once device is connected. 2315 */ 2316 if (sc->sc_mode == MUSB2_HOST_MODE) { 2317 if (usb_status & MUSB2_MASK_ICONN) 2318 sc->sc_flags.status_bus_reset = 1; 2319 if (usb_status & MUSB2_MASK_IDISC) 2320 sc->sc_flags.status_bus_reset = 0; 2321 } 2322 2323 /* complete root HUB interrupt endpoint */ 2324 musbotg_root_intr(sc); 2325 } 2326 /* check for any endpoint interrupts */ 2327 2328 if (rx_status || tx_status) { 2329 DPRINTFN(4, "real endpoint interrupt " 2330 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status); 2331 } 2332 /* poll one time regardless of FIFO status */ 2333 2334 musbotg_interrupt_poll(sc); 2335 2336 if (--to) 2337 goto repeat; 2338 2339 USB_BUS_UNLOCK(&sc->sc_bus); 2340 } 2341 2342 static void 2343 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp) 2344 { 2345 struct musbotg_td *td; 2346 2347 /* get current Transfer Descriptor */ 2348 td = temp->td_next; 2349 temp->td = td; 2350 2351 /* prepare for next TD */ 2352 temp->td_next = td->obj_next; 2353 2354 /* fill out the Transfer Descriptor */ 2355 td->func = temp->func; 2356 td->pc = temp->pc; 2357 td->offset = temp->offset; 2358 td->remainder = temp->len; 2359 td->error = 0; 2360 td->transaction_started = 0; 2361 td->did_stall = temp->did_stall; 2362 td->short_pkt = temp->short_pkt; 2363 td->alt_next = temp->setup_alt_next; 2364 td->channel = temp->channel; 2365 td->dev_addr = temp->dev_addr; 2366 td->haddr = temp->haddr; 2367 td->hport = temp->hport; 2368 td->transfer_type = temp->transfer_type; 2369 } 2370 2371 static void 2372 musbotg_setup_standard_chain(struct usb_xfer *xfer) 2373 { 2374 struct musbotg_std_temp temp; 2375 struct musbotg_softc *sc; 2376 struct musbotg_td *td; 2377 uint32_t x; 2378 uint8_t ep_no; 2379 uint8_t xfer_type; 2380 enum usb_dev_speed speed; 2381 int tx; 2382 int dev_addr; 2383 2384 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2385 xfer->address, UE_GET_ADDR(xfer->endpointno), 2386 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2387 2388 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2389 ep_no = (xfer->endpointno & UE_ADDR); 2390 2391 temp.max_frame_size = xfer->max_frame_size; 2392 2393 td = xfer->td_start[0]; 2394 xfer->td_transfer_first = td; 2395 xfer->td_transfer_cache = td; 2396 2397 /* setup temp */ 2398 dev_addr = xfer->address; 2399 2400 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 2401 2402 temp.pc = NULL; 2403 temp.td = NULL; 2404 temp.td_next = xfer->td_start[0]; 2405 temp.offset = 0; 2406 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 2407 xfer->flags_int.isochronous_xfr; 2408 temp.did_stall = !xfer->flags_int.control_stall; 2409 temp.channel = -1; 2410 temp.dev_addr = dev_addr; 2411 temp.haddr = xfer->xroot->udev->hs_hub_addr; 2412 temp.hport = xfer->xroot->udev->hs_port_no; 2413 2414 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2415 speed = usbd_get_speed(xfer->xroot->udev); 2416 2417 switch (speed) { 2418 case USB_SPEED_LOW: 2419 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO; 2420 break; 2421 case USB_SPEED_FULL: 2422 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS; 2423 break; 2424 case USB_SPEED_HIGH: 2425 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS; 2426 break; 2427 default: 2428 temp.transfer_type = 0; 2429 DPRINTFN(-1, "Invalid USB speed: %d\n", speed); 2430 break; 2431 } 2432 2433 switch (xfer_type) { 2434 case UE_CONTROL: 2435 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL; 2436 break; 2437 case UE_ISOCHRONOUS: 2438 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC; 2439 break; 2440 case UE_BULK: 2441 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK; 2442 break; 2443 case UE_INTERRUPT: 2444 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR; 2445 break; 2446 default: 2447 DPRINTFN(-1, "Invalid USB transfer type: %d\n", 2448 xfer_type); 2449 break; 2450 } 2451 2452 temp.transfer_type |= ep_no; 2453 td->toggle = xfer->endpoint->toggle_next; 2454 } 2455 2456 /* check if we should prepend a setup message */ 2457 2458 if (xfer->flags_int.control_xfr) { 2459 if (xfer->flags_int.control_hdr) { 2460 2461 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) 2462 temp.func = &musbotg_dev_ctrl_setup_rx; 2463 else 2464 temp.func = &musbotg_host_ctrl_setup_tx; 2465 2466 temp.len = xfer->frlengths[0]; 2467 temp.pc = xfer->frbuffers + 0; 2468 temp.short_pkt = temp.len ? 1 : 0; 2469 2470 musbotg_setup_standard_chain_sub(&temp); 2471 } 2472 x = 1; 2473 } else { 2474 x = 0; 2475 } 2476 2477 tx = 0; 2478 2479 if (x != xfer->nframes) { 2480 if (xfer->endpointno & UE_DIR_IN) 2481 tx = 1; 2482 2483 if (xfer->flags_int.usb_mode == USB_MODE_HOST) { 2484 tx = !tx; 2485 2486 if (tx) { 2487 if (xfer->flags_int.control_xfr) 2488 temp.func = &musbotg_host_ctrl_data_tx; 2489 else 2490 temp.func = &musbotg_host_data_tx; 2491 } else { 2492 if (xfer->flags_int.control_xfr) 2493 temp.func = &musbotg_host_ctrl_data_rx; 2494 else 2495 temp.func = &musbotg_host_data_rx; 2496 } 2497 2498 } else { 2499 if (tx) { 2500 if (xfer->flags_int.control_xfr) 2501 temp.func = &musbotg_dev_ctrl_data_tx; 2502 else 2503 temp.func = &musbotg_dev_data_tx; 2504 } else { 2505 if (xfer->flags_int.control_xfr) 2506 temp.func = &musbotg_dev_ctrl_data_rx; 2507 else 2508 temp.func = &musbotg_dev_data_rx; 2509 } 2510 } 2511 2512 /* setup "pc" pointer */ 2513 temp.pc = xfer->frbuffers + x; 2514 } 2515 while (x != xfer->nframes) { 2516 2517 /* DATA0 / DATA1 message */ 2518 2519 temp.len = xfer->frlengths[x]; 2520 2521 x++; 2522 2523 if (x == xfer->nframes) { 2524 if (xfer->flags_int.control_xfr) { 2525 if (xfer->flags_int.control_act) { 2526 temp.setup_alt_next = 0; 2527 } 2528 } else { 2529 temp.setup_alt_next = 0; 2530 } 2531 } 2532 if (temp.len == 0) { 2533 2534 /* make sure that we send an USB packet */ 2535 2536 temp.short_pkt = 0; 2537 2538 } else { 2539 2540 if (xfer->flags_int.isochronous_xfr) { 2541 /* isochronous data transfer */ 2542 /* don't force short */ 2543 temp.short_pkt = 1; 2544 } else { 2545 /* regular data transfer */ 2546 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 2547 } 2548 } 2549 2550 musbotg_setup_standard_chain_sub(&temp); 2551 2552 if (xfer->flags_int.isochronous_xfr) { 2553 temp.offset += temp.len; 2554 } else { 2555 /* get next Page Cache pointer */ 2556 temp.pc = xfer->frbuffers + x; 2557 } 2558 } 2559 2560 /* check for control transfer */ 2561 if (xfer->flags_int.control_xfr) { 2562 2563 /* always setup a valid "pc" pointer for status and sync */ 2564 temp.pc = xfer->frbuffers + 0; 2565 temp.len = 0; 2566 temp.short_pkt = 0; 2567 temp.setup_alt_next = 0; 2568 2569 /* check if we should append a status stage */ 2570 if (!xfer->flags_int.control_act) { 2571 /* 2572 * Send a DATA1 message and invert the current 2573 * endpoint direction. 2574 */ 2575 if (sc->sc_mode == MUSB2_DEVICE_MODE) 2576 temp.func = &musbotg_dev_ctrl_status; 2577 else { 2578 if (xfer->endpointno & UE_DIR_IN) 2579 temp.func = musbotg_host_ctrl_status_tx; 2580 else 2581 temp.func = musbotg_host_ctrl_status_rx; 2582 } 2583 musbotg_setup_standard_chain_sub(&temp); 2584 } 2585 } 2586 /* must have at least one frame! */ 2587 td = temp.td; 2588 xfer->td_transfer_last = td; 2589 } 2590 2591 static void 2592 musbotg_timeout(void *arg) 2593 { 2594 struct usb_xfer *xfer = arg; 2595 2596 DPRINTFN(1, "xfer=%p\n", xfer); 2597 2598 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2599 2600 /* transfer is transferred */ 2601 musbotg_device_done(xfer, USB_ERR_TIMEOUT); 2602 } 2603 2604 static void 2605 musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on) 2606 { 2607 uint16_t temp; 2608 2609 /* 2610 * Only enable the endpoint interrupt when we are 2611 * actually waiting for data, hence we are dealing 2612 * with level triggered interrupts ! 2613 */ 2614 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on); 2615 2616 if (channel == -1) 2617 return; 2618 2619 if (channel == 0) { 2620 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2621 if (on) 2622 temp |= MUSB2_MASK_EPINT(0); 2623 else 2624 temp &= ~MUSB2_MASK_EPINT(0); 2625 2626 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2627 } else { 2628 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE); 2629 if (on) 2630 temp |= MUSB2_MASK_EPINT(channel); 2631 else 2632 temp &= ~MUSB2_MASK_EPINT(channel); 2633 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp); 2634 2635 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE); 2636 if (on) 2637 temp |= MUSB2_MASK_EPINT(channel); 2638 else 2639 temp &= ~MUSB2_MASK_EPINT(channel); 2640 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp); 2641 } 2642 2643 if (sc->sc_ep_int_set) 2644 sc->sc_ep_int_set(sc, channel, on); 2645 } 2646 2647 static void 2648 musbotg_start_standard_chain(struct usb_xfer *xfer) 2649 { 2650 DPRINTFN(8, "\n"); 2651 2652 /* poll one time */ 2653 if (musbotg_xfer_do_fifo(xfer)) { 2654 2655 DPRINTFN(14, "enabled interrupts on endpoint\n"); 2656 2657 /* put transfer on interrupt queue */ 2658 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2659 2660 /* start timeout, if any */ 2661 if (xfer->timeout != 0) { 2662 usbd_transfer_timeout_ms(xfer, 2663 &musbotg_timeout, xfer->timeout); 2664 } 2665 } 2666 } 2667 2668 static void 2669 musbotg_root_intr(struct musbotg_softc *sc) 2670 { 2671 DPRINTFN(8, "\n"); 2672 2673 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2674 2675 /* set port bit */ 2676 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 2677 2678 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2679 sizeof(sc->sc_hub_idata)); 2680 } 2681 2682 static usb_error_t 2683 musbotg_standard_done_sub(struct usb_xfer *xfer) 2684 { 2685 struct musbotg_td *td; 2686 uint32_t len; 2687 uint8_t error; 2688 2689 DPRINTFN(8, "\n"); 2690 2691 td = xfer->td_transfer_cache; 2692 2693 do { 2694 len = td->remainder; 2695 2696 xfer->endpoint->toggle_next = td->toggle; 2697 2698 if (xfer->aframes != xfer->nframes) { 2699 /* 2700 * Verify the length and subtract 2701 * the remainder from "frlengths[]": 2702 */ 2703 if (len > xfer->frlengths[xfer->aframes]) { 2704 td->error = 1; 2705 } else { 2706 xfer->frlengths[xfer->aframes] -= len; 2707 } 2708 } 2709 /* Check for transfer error */ 2710 if (td->error) { 2711 /* the transfer is finished */ 2712 error = 1; 2713 td = NULL; 2714 break; 2715 } 2716 /* Check for short transfer */ 2717 if (len > 0) { 2718 if (xfer->flags_int.short_frames_ok || 2719 xfer->flags_int.isochronous_xfr) { 2720 /* follow alt next */ 2721 if (td->alt_next) { 2722 td = td->obj_next; 2723 } else { 2724 td = NULL; 2725 } 2726 } else { 2727 /* the transfer is finished */ 2728 td = NULL; 2729 } 2730 error = 0; 2731 break; 2732 } 2733 td = td->obj_next; 2734 2735 /* this USB frame is complete */ 2736 error = 0; 2737 break; 2738 2739 } while (0); 2740 2741 /* update transfer cache */ 2742 2743 xfer->td_transfer_cache = td; 2744 2745 return (error ? 2746 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 2747 } 2748 2749 static void 2750 musbotg_standard_done(struct usb_xfer *xfer) 2751 { 2752 usb_error_t err = 0; 2753 2754 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n", 2755 xfer, xfer->endpoint); 2756 2757 /* reset scanner */ 2758 2759 xfer->td_transfer_cache = xfer->td_transfer_first; 2760 2761 if (xfer->flags_int.control_xfr) { 2762 2763 if (xfer->flags_int.control_hdr) { 2764 2765 err = musbotg_standard_done_sub(xfer); 2766 } 2767 xfer->aframes = 1; 2768 2769 if (xfer->td_transfer_cache == NULL) { 2770 goto done; 2771 } 2772 } 2773 while (xfer->aframes != xfer->nframes) { 2774 2775 err = musbotg_standard_done_sub(xfer); 2776 xfer->aframes++; 2777 2778 if (xfer->td_transfer_cache == NULL) { 2779 goto done; 2780 } 2781 } 2782 2783 if (xfer->flags_int.control_xfr && 2784 !xfer->flags_int.control_act) { 2785 2786 err = musbotg_standard_done_sub(xfer); 2787 } 2788 done: 2789 musbotg_device_done(xfer, err); 2790 } 2791 2792 /*------------------------------------------------------------------------* 2793 * musbotg_device_done 2794 * 2795 * NOTE: this function can be called more than one time on the 2796 * same USB transfer! 2797 *------------------------------------------------------------------------*/ 2798 static void 2799 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error) 2800 { 2801 struct musbotg_td *td; 2802 struct musbotg_softc *sc; 2803 2804 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2805 2806 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n", 2807 xfer, xfer->endpoint, error); 2808 2809 DPRINTFN(14, "disabled interrupts on endpoint\n"); 2810 2811 sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 2812 td = xfer->td_transfer_cache; 2813 2814 if (td && (td->channel != -1)) 2815 musbotg_channel_free(sc, td); 2816 2817 /* dequeue transfer and start next transfer */ 2818 usbd_transfer_done(xfer, error); 2819 } 2820 2821 static void 2822 musbotg_xfer_stall(struct usb_xfer *xfer) 2823 { 2824 musbotg_device_done(xfer, USB_ERR_STALLED); 2825 } 2826 2827 static void 2828 musbotg_set_stall(struct usb_device *udev, 2829 struct usb_endpoint *ep, uint8_t *did_stall) 2830 { 2831 struct musbotg_softc *sc; 2832 uint8_t ep_no; 2833 2834 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2835 2836 DPRINTFN(4, "endpoint=%p\n", ep); 2837 2838 /* set FORCESTALL */ 2839 sc = MUSBOTG_BUS2SC(udev->bus); 2840 2841 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 2842 2843 /* select endpoint */ 2844 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2845 2846 if (ep->edesc->bEndpointAddress & UE_DIR_IN) { 2847 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2848 MUSB2_MASK_CSRL_TXSENDSTALL); 2849 } else { 2850 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2851 MUSB2_MASK_CSRL_RXSENDSTALL); 2852 } 2853 } 2854 2855 static void 2856 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket, 2857 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 2858 { 2859 uint16_t mps; 2860 uint16_t temp; 2861 uint8_t csr; 2862 2863 if (ep_type == UE_CONTROL) { 2864 /* clearing stall is not needed */ 2865 return; 2866 } 2867 /* select endpoint */ 2868 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no); 2869 2870 /* compute max frame size */ 2871 mps = wMaxPacket & 0x7FF; 2872 switch ((wMaxPacket >> 11) & 3) { 2873 case 1: 2874 mps *= 2; 2875 break; 2876 case 2: 2877 mps *= 3; 2878 break; 2879 default: 2880 break; 2881 } 2882 2883 if (ep_dir == UE_DIR_IN) { 2884 2885 temp = 0; 2886 2887 /* Configure endpoint */ 2888 switch (ep_type) { 2889 case UE_INTERRUPT: 2890 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2891 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2892 MUSB2_MASK_CSRH_TXMODE | temp); 2893 break; 2894 case UE_ISOCHRONOUS: 2895 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2896 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2897 MUSB2_MASK_CSRH_TXMODE | 2898 MUSB2_MASK_CSRH_TXISO | temp); 2899 break; 2900 case UE_BULK: 2901 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket); 2902 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, 2903 MUSB2_MASK_CSRH_TXMODE | temp); 2904 break; 2905 default: 2906 break; 2907 } 2908 2909 /* Need to flush twice in case of double bufring */ 2910 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2911 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2912 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2913 MUSB2_MASK_CSRL_TXFFLUSH); 2914 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2915 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2916 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2917 MUSB2_MASK_CSRL_TXFFLUSH); 2918 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2919 } 2920 } 2921 /* reset data toggle */ 2922 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 2923 MUSB2_MASK_CSRL_TXDT_CLR); 2924 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2925 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2926 2927 /* set double/single buffering */ 2928 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS); 2929 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 2930 max_in_frame_size / 2)) { 2931 /* double buffer */ 2932 temp &= ~(1 << ep_no); 2933 } else { 2934 /* single buffer */ 2935 temp |= (1 << ep_no); 2936 } 2937 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp); 2938 2939 /* clear sent stall */ 2940 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) { 2941 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0); 2942 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL); 2943 } 2944 } else { 2945 2946 temp = 0; 2947 2948 /* Configure endpoint */ 2949 switch (ep_type) { 2950 case UE_INTERRUPT: 2951 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2952 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2953 MUSB2_MASK_CSRH_RXNYET | temp); 2954 break; 2955 case UE_ISOCHRONOUS: 2956 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2957 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, 2958 MUSB2_MASK_CSRH_RXNYET | 2959 MUSB2_MASK_CSRH_RXISO | temp); 2960 break; 2961 case UE_BULK: 2962 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket); 2963 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp); 2964 break; 2965 default: 2966 break; 2967 } 2968 2969 /* Need to flush twice in case of double bufring */ 2970 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2971 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2972 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2973 MUSB2_MASK_CSRL_RXFFLUSH); 2974 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2975 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2976 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2977 MUSB2_MASK_CSRL_RXFFLUSH); 2978 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2979 } 2980 } 2981 /* reset data toggle */ 2982 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 2983 MUSB2_MASK_CSRL_RXDT_CLR); 2984 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 2985 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL); 2986 2987 /* set double/single buffering */ 2988 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS); 2989 if (mps <= (sc->sc_hw_ep_profile[ep_no]. 2990 max_out_frame_size / 2)) { 2991 /* double buffer */ 2992 temp &= ~(1 << ep_no); 2993 } else { 2994 /* single buffer */ 2995 temp |= (1 << ep_no); 2996 } 2997 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp); 2998 2999 /* clear sent stall */ 3000 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) { 3001 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0); 3002 } 3003 } 3004 } 3005 3006 static void 3007 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3008 { 3009 struct musbotg_softc *sc; 3010 struct usb_endpoint_descriptor *ed; 3011 3012 DPRINTFN(4, "endpoint=%p\n", ep); 3013 3014 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3015 3016 /* check mode */ 3017 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3018 /* not supported */ 3019 return; 3020 } 3021 /* get softc */ 3022 sc = MUSBOTG_BUS2SC(udev->bus); 3023 3024 /* get endpoint descriptor */ 3025 ed = ep->edesc; 3026 3027 /* reset endpoint */ 3028 musbotg_clear_stall_sub(sc, 3029 UGETW(ed->wMaxPacketSize), 3030 (ed->bEndpointAddress & UE_ADDR), 3031 (ed->bmAttributes & UE_XFERTYPE), 3032 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3033 } 3034 3035 usb_error_t 3036 musbotg_init(struct musbotg_softc *sc) 3037 { 3038 struct usb_hw_ep_profile *pf; 3039 uint16_t offset; 3040 uint8_t nrx; 3041 uint8_t ntx; 3042 uint8_t temp; 3043 uint8_t fsize; 3044 uint8_t frx; 3045 uint8_t ftx; 3046 uint8_t dynfifo; 3047 3048 DPRINTFN(1, "start\n"); 3049 3050 /* set up the bus structure */ 3051 sc->sc_bus.usbrev = USB_REV_2_0; 3052 sc->sc_bus.methods = &musbotg_bus_methods; 3053 3054 USB_BUS_LOCK(&sc->sc_bus); 3055 3056 /* turn on clocks */ 3057 3058 if (sc->sc_clocks_on) { 3059 (sc->sc_clocks_on) (sc->sc_clocks_arg); 3060 } 3061 3062 /* wait a little for things to stabilise */ 3063 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 3064 3065 /* disable all interrupts */ 3066 3067 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3068 DPRINTF("pre-DEVCTL=0x%02x\n", temp); 3069 3070 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3071 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3072 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3073 3074 /* disable pullup */ 3075 3076 musbotg_pull_common(sc, 0); 3077 3078 /* wait a little bit (10ms) */ 3079 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3080 3081 3082 /* disable double packet buffering */ 3083 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 3084 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 3085 3086 /* enable HighSpeed and ISO Update flags */ 3087 3088 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, 3089 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 3090 3091 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 3092 /* clear Session bit, if set */ 3093 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3094 temp &= ~MUSB2_MASK_SESS; 3095 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3096 } else { 3097 /* Enter session for Host mode */ 3098 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL); 3099 temp |= MUSB2_MASK_SESS; 3100 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp); 3101 } 3102 3103 /* wait a little for things to stabilise */ 3104 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 3105 3106 DPRINTF("DEVCTL=0x%02x\n", temp); 3107 3108 /* disable testmode */ 3109 3110 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0); 3111 3112 /* set default value */ 3113 3114 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0); 3115 3116 /* select endpoint index 0 */ 3117 3118 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0); 3119 3120 /* read out number of endpoints */ 3121 3122 nrx = 3123 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16); 3124 3125 ntx = 3126 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16); 3127 3128 /* these numbers exclude the control endpoint */ 3129 3130 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx); 3131 3132 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx; 3133 if (sc->sc_ep_max == 0) { 3134 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n"); 3135 } 3136 /* read out configuration data */ 3137 3138 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA); 3139 3140 DPRINTFN(2, "Config Data: 0x%02x\n", 3141 sc->sc_conf_data); 3142 3143 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 3144 3145 if (dynfifo) { 3146 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, " 3147 "assuming 16Kbytes of FIFO RAM\n"); 3148 } 3149 3150 DPRINTFN(2, "HW version: 0x%04x\n", 3151 MUSB2_READ_1(sc, MUSB2_REG_HWVERS)); 3152 3153 /* initialise endpoint profiles */ 3154 3155 offset = 0; 3156 3157 for (temp = 1; temp <= sc->sc_ep_max; temp++) { 3158 pf = sc->sc_hw_ep_profile + temp; 3159 3160 /* select endpoint */ 3161 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp); 3162 3163 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE); 3164 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16; 3165 ftx = (fsize & MUSB2_MASK_TX_FSIZE); 3166 3167 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 3168 temp, ftx, frx, dynfifo); 3169 3170 if (dynfifo) { 3171 if (frx && (temp <= nrx)) { 3172 if (temp == 1) { 3173 frx = 12; /* 4K */ 3174 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 3175 MUSB2_VAL_FIFOSZ_4096 | 3176 MUSB2_MASK_FIFODB); 3177 } else if (temp < 8) { 3178 frx = 10; /* 1K */ 3179 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 3180 MUSB2_VAL_FIFOSZ_512 | 3181 MUSB2_MASK_FIFODB); 3182 } else { 3183 frx = 7; /* 128 bytes */ 3184 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ, 3185 MUSB2_VAL_FIFOSZ_128); 3186 } 3187 3188 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD, 3189 offset >> 3); 3190 3191 offset += (1 << frx); 3192 } 3193 if (ftx && (temp <= ntx)) { 3194 if (temp == 1) { 3195 ftx = 12; /* 4K */ 3196 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 3197 MUSB2_VAL_FIFOSZ_4096 | 3198 MUSB2_MASK_FIFODB); 3199 } else if (temp < 8) { 3200 ftx = 10; /* 1K */ 3201 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 3202 MUSB2_VAL_FIFOSZ_512 | 3203 MUSB2_MASK_FIFODB); 3204 } else { 3205 ftx = 7; /* 128 bytes */ 3206 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ, 3207 MUSB2_VAL_FIFOSZ_128); 3208 } 3209 3210 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD, 3211 offset >> 3); 3212 3213 offset += (1 << ftx); 3214 } 3215 } 3216 3217 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) { 3218 pf->max_in_frame_size = 1 << ftx; 3219 pf->max_out_frame_size = 1 << frx; 3220 pf->is_simplex = 0; /* duplex */ 3221 pf->support_multi_buffer = 1; 3222 pf->support_bulk = 1; 3223 pf->support_interrupt = 1; 3224 pf->support_isochronous = 1; 3225 pf->support_in = 1; 3226 pf->support_out = 1; 3227 } else if (frx && (temp <= nrx)) { 3228 pf->max_out_frame_size = 1 << frx; 3229 pf->is_simplex = 1; /* simplex */ 3230 pf->support_multi_buffer = 1; 3231 pf->support_bulk = 1; 3232 pf->support_interrupt = 1; 3233 pf->support_isochronous = 1; 3234 pf->support_out = 1; 3235 } else if (ftx && (temp <= ntx)) { 3236 pf->max_in_frame_size = 1 << ftx; 3237 pf->is_simplex = 1; /* simplex */ 3238 pf->support_multi_buffer = 1; 3239 pf->support_bulk = 1; 3240 pf->support_interrupt = 1; 3241 pf->support_isochronous = 1; 3242 pf->support_in = 1; 3243 } 3244 } 3245 3246 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset); 3247 3248 /* turn on default interrupts */ 3249 3250 if (sc->sc_mode == MUSB2_HOST_MODE) 3251 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff); 3252 else 3253 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 3254 MUSB2_MASK_IRESET); 3255 3256 musbotg_clocks_off(sc); 3257 3258 USB_BUS_UNLOCK(&sc->sc_bus); 3259 3260 /* catch any lost interrupts */ 3261 3262 musbotg_do_poll(&sc->sc_bus); 3263 3264 return (0); /* success */ 3265 } 3266 3267 void 3268 musbotg_uninit(struct musbotg_softc *sc) 3269 { 3270 USB_BUS_LOCK(&sc->sc_bus); 3271 3272 /* disable all interrupts */ 3273 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0); 3274 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0); 3275 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0); 3276 3277 sc->sc_flags.port_powered = 0; 3278 sc->sc_flags.status_vbus = 0; 3279 sc->sc_flags.status_bus_reset = 0; 3280 sc->sc_flags.status_suspend = 0; 3281 sc->sc_flags.change_suspend = 0; 3282 sc->sc_flags.change_connect = 1; 3283 3284 musbotg_pull_down(sc); 3285 musbotg_clocks_off(sc); 3286 USB_BUS_UNLOCK(&sc->sc_bus); 3287 } 3288 3289 static void 3290 musbotg_suspend(struct musbotg_softc *sc) 3291 { 3292 /* TODO */ 3293 } 3294 3295 static void 3296 musbotg_resume(struct musbotg_softc *sc) 3297 { 3298 /* TODO */ 3299 } 3300 3301 static void 3302 musbotg_do_poll(struct usb_bus *bus) 3303 { 3304 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 3305 3306 USB_BUS_LOCK(&sc->sc_bus); 3307 musbotg_interrupt_poll(sc); 3308 USB_BUS_UNLOCK(&sc->sc_bus); 3309 } 3310 3311 /*------------------------------------------------------------------------* 3312 * musbotg bulk support 3313 *------------------------------------------------------------------------*/ 3314 static void 3315 musbotg_device_bulk_open(struct usb_xfer *xfer) 3316 { 3317 return; 3318 } 3319 3320 static void 3321 musbotg_device_bulk_close(struct usb_xfer *xfer) 3322 { 3323 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3324 } 3325 3326 static void 3327 musbotg_device_bulk_enter(struct usb_xfer *xfer) 3328 { 3329 return; 3330 } 3331 3332 static void 3333 musbotg_device_bulk_start(struct usb_xfer *xfer) 3334 { 3335 /* setup TDs */ 3336 musbotg_setup_standard_chain(xfer); 3337 musbotg_start_standard_chain(xfer); 3338 } 3339 3340 static const struct usb_pipe_methods musbotg_device_bulk_methods = 3341 { 3342 .open = musbotg_device_bulk_open, 3343 .close = musbotg_device_bulk_close, 3344 .enter = musbotg_device_bulk_enter, 3345 .start = musbotg_device_bulk_start, 3346 }; 3347 3348 /*------------------------------------------------------------------------* 3349 * musbotg control support 3350 *------------------------------------------------------------------------*/ 3351 static void 3352 musbotg_device_ctrl_open(struct usb_xfer *xfer) 3353 { 3354 return; 3355 } 3356 3357 static void 3358 musbotg_device_ctrl_close(struct usb_xfer *xfer) 3359 { 3360 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3361 } 3362 3363 static void 3364 musbotg_device_ctrl_enter(struct usb_xfer *xfer) 3365 { 3366 return; 3367 } 3368 3369 static void 3370 musbotg_device_ctrl_start(struct usb_xfer *xfer) 3371 { 3372 /* setup TDs */ 3373 musbotg_setup_standard_chain(xfer); 3374 musbotg_start_standard_chain(xfer); 3375 } 3376 3377 static const struct usb_pipe_methods musbotg_device_ctrl_methods = 3378 { 3379 .open = musbotg_device_ctrl_open, 3380 .close = musbotg_device_ctrl_close, 3381 .enter = musbotg_device_ctrl_enter, 3382 .start = musbotg_device_ctrl_start, 3383 }; 3384 3385 /*------------------------------------------------------------------------* 3386 * musbotg interrupt support 3387 *------------------------------------------------------------------------*/ 3388 static void 3389 musbotg_device_intr_open(struct usb_xfer *xfer) 3390 { 3391 return; 3392 } 3393 3394 static void 3395 musbotg_device_intr_close(struct usb_xfer *xfer) 3396 { 3397 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3398 } 3399 3400 static void 3401 musbotg_device_intr_enter(struct usb_xfer *xfer) 3402 { 3403 return; 3404 } 3405 3406 static void 3407 musbotg_device_intr_start(struct usb_xfer *xfer) 3408 { 3409 /* setup TDs */ 3410 musbotg_setup_standard_chain(xfer); 3411 musbotg_start_standard_chain(xfer); 3412 } 3413 3414 static const struct usb_pipe_methods musbotg_device_intr_methods = 3415 { 3416 .open = musbotg_device_intr_open, 3417 .close = musbotg_device_intr_close, 3418 .enter = musbotg_device_intr_enter, 3419 .start = musbotg_device_intr_start, 3420 }; 3421 3422 /*------------------------------------------------------------------------* 3423 * musbotg full speed isochronous support 3424 *------------------------------------------------------------------------*/ 3425 static void 3426 musbotg_device_isoc_open(struct usb_xfer *xfer) 3427 { 3428 return; 3429 } 3430 3431 static void 3432 musbotg_device_isoc_close(struct usb_xfer *xfer) 3433 { 3434 musbotg_device_done(xfer, USB_ERR_CANCELLED); 3435 } 3436 3437 static void 3438 musbotg_device_isoc_enter(struct usb_xfer *xfer) 3439 { 3440 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus); 3441 uint32_t temp; 3442 uint32_t nframes; 3443 uint32_t fs_frames; 3444 3445 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n", 3446 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3447 3448 /* get the current frame index */ 3449 3450 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME); 3451 3452 /* 3453 * check if the frame index is within the window where the frames 3454 * will be inserted 3455 */ 3456 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME; 3457 3458 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 3459 fs_frames = (xfer->nframes + 7) / 8; 3460 } else { 3461 fs_frames = xfer->nframes; 3462 } 3463 3464 if ((xfer->endpoint->is_synced == 0) || 3465 (temp < fs_frames)) { 3466 /* 3467 * If there is data underflow or the pipe queue is 3468 * empty we schedule the transfer a few frames ahead 3469 * of the current frame position. Else two isochronous 3470 * transfers might overlap. 3471 */ 3472 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME; 3473 xfer->endpoint->is_synced = 1; 3474 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next); 3475 } 3476 /* 3477 * compute how many milliseconds the insertion is ahead of the 3478 * current frame position: 3479 */ 3480 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME; 3481 3482 /* 3483 * pre-compute when the isochronous transfer will be finished: 3484 */ 3485 xfer->isoc_time_complete = 3486 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 3487 fs_frames; 3488 3489 /* compute frame number for next insertion */ 3490 xfer->endpoint->isoc_next += fs_frames; 3491 3492 /* setup TDs */ 3493 musbotg_setup_standard_chain(xfer); 3494 } 3495 3496 static void 3497 musbotg_device_isoc_start(struct usb_xfer *xfer) 3498 { 3499 /* start TD chain */ 3500 musbotg_start_standard_chain(xfer); 3501 } 3502 3503 static const struct usb_pipe_methods musbotg_device_isoc_methods = 3504 { 3505 .open = musbotg_device_isoc_open, 3506 .close = musbotg_device_isoc_close, 3507 .enter = musbotg_device_isoc_enter, 3508 .start = musbotg_device_isoc_start, 3509 }; 3510 3511 /*------------------------------------------------------------------------* 3512 * musbotg root control support 3513 *------------------------------------------------------------------------* 3514 * Simulate a hardware HUB by handling all the necessary requests. 3515 *------------------------------------------------------------------------*/ 3516 3517 static const struct usb_device_descriptor musbotg_devd = { 3518 .bLength = sizeof(struct usb_device_descriptor), 3519 .bDescriptorType = UDESC_DEVICE, 3520 .bcdUSB = {0x00, 0x02}, 3521 .bDeviceClass = UDCLASS_HUB, 3522 .bDeviceSubClass = UDSUBCLASS_HUB, 3523 .bDeviceProtocol = UDPROTO_HSHUBSTT, 3524 .bMaxPacketSize = 64, 3525 .bcdDevice = {0x00, 0x01}, 3526 .iManufacturer = 1, 3527 .iProduct = 2, 3528 .bNumConfigurations = 1, 3529 }; 3530 3531 static const struct usb_device_qualifier musbotg_odevd = { 3532 .bLength = sizeof(struct usb_device_qualifier), 3533 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 3534 .bcdUSB = {0x00, 0x02}, 3535 .bDeviceClass = UDCLASS_HUB, 3536 .bDeviceSubClass = UDSUBCLASS_HUB, 3537 .bDeviceProtocol = UDPROTO_FSHUB, 3538 .bMaxPacketSize0 = 0, 3539 .bNumConfigurations = 0, 3540 }; 3541 3542 static const struct musbotg_config_desc musbotg_confd = { 3543 .confd = { 3544 .bLength = sizeof(struct usb_config_descriptor), 3545 .bDescriptorType = UDESC_CONFIG, 3546 .wTotalLength[0] = sizeof(musbotg_confd), 3547 .bNumInterface = 1, 3548 .bConfigurationValue = 1, 3549 .iConfiguration = 0, 3550 .bmAttributes = UC_SELF_POWERED, 3551 .bMaxPower = 0, 3552 }, 3553 .ifcd = { 3554 .bLength = sizeof(struct usb_interface_descriptor), 3555 .bDescriptorType = UDESC_INTERFACE, 3556 .bNumEndpoints = 1, 3557 .bInterfaceClass = UICLASS_HUB, 3558 .bInterfaceSubClass = UISUBCLASS_HUB, 3559 .bInterfaceProtocol = 0, 3560 }, 3561 .endpd = { 3562 .bLength = sizeof(struct usb_endpoint_descriptor), 3563 .bDescriptorType = UDESC_ENDPOINT, 3564 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT), 3565 .bmAttributes = UE_INTERRUPT, 3566 .wMaxPacketSize[0] = 8, 3567 .bInterval = 255, 3568 }, 3569 }; 3570 3571 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3572 3573 static const struct usb_hub_descriptor_min musbotg_hubd = { 3574 .bDescLength = sizeof(musbotg_hubd), 3575 .bDescriptorType = UDESC_HUB, 3576 .bNbrPorts = 1, 3577 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 3578 .bPwrOn2PwrGood = 50, 3579 .bHubContrCurrent = 0, 3580 .DeviceRemovable = {0}, /* port is removable */ 3581 }; 3582 3583 #define STRING_VENDOR \ 3584 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s" 3585 3586 #define STRING_PRODUCT \ 3587 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 3588 3589 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor); 3590 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product); 3591 3592 static usb_error_t 3593 musbotg_roothub_exec(struct usb_device *udev, 3594 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3595 { 3596 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 3597 const void *ptr; 3598 uint16_t len; 3599 uint16_t value; 3600 uint16_t index; 3601 uint8_t reg; 3602 usb_error_t err; 3603 3604 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3605 3606 /* buffer reset */ 3607 ptr = (const void *)&sc->sc_hub_temp; 3608 len = 0; 3609 err = 0; 3610 3611 value = UGETW(req->wValue); 3612 index = UGETW(req->wIndex); 3613 3614 /* demultiplex the control request */ 3615 3616 switch (req->bmRequestType) { 3617 case UT_READ_DEVICE: 3618 switch (req->bRequest) { 3619 case UR_GET_DESCRIPTOR: 3620 goto tr_handle_get_descriptor; 3621 case UR_GET_CONFIG: 3622 goto tr_handle_get_config; 3623 case UR_GET_STATUS: 3624 goto tr_handle_get_status; 3625 default: 3626 goto tr_stalled; 3627 } 3628 break; 3629 3630 case UT_WRITE_DEVICE: 3631 switch (req->bRequest) { 3632 case UR_SET_ADDRESS: 3633 goto tr_handle_set_address; 3634 case UR_SET_CONFIG: 3635 goto tr_handle_set_config; 3636 case UR_CLEAR_FEATURE: 3637 goto tr_valid; /* nop */ 3638 case UR_SET_DESCRIPTOR: 3639 goto tr_valid; /* nop */ 3640 case UR_SET_FEATURE: 3641 default: 3642 goto tr_stalled; 3643 } 3644 break; 3645 3646 case UT_WRITE_ENDPOINT: 3647 switch (req->bRequest) { 3648 case UR_CLEAR_FEATURE: 3649 switch (UGETW(req->wValue)) { 3650 case UF_ENDPOINT_HALT: 3651 goto tr_handle_clear_halt; 3652 case UF_DEVICE_REMOTE_WAKEUP: 3653 goto tr_handle_clear_wakeup; 3654 default: 3655 goto tr_stalled; 3656 } 3657 break; 3658 case UR_SET_FEATURE: 3659 switch (UGETW(req->wValue)) { 3660 case UF_ENDPOINT_HALT: 3661 goto tr_handle_set_halt; 3662 case UF_DEVICE_REMOTE_WAKEUP: 3663 goto tr_handle_set_wakeup; 3664 default: 3665 goto tr_stalled; 3666 } 3667 break; 3668 case UR_SYNCH_FRAME: 3669 goto tr_valid; /* nop */ 3670 default: 3671 goto tr_stalled; 3672 } 3673 break; 3674 3675 case UT_READ_ENDPOINT: 3676 switch (req->bRequest) { 3677 case UR_GET_STATUS: 3678 goto tr_handle_get_ep_status; 3679 default: 3680 goto tr_stalled; 3681 } 3682 break; 3683 3684 case UT_WRITE_INTERFACE: 3685 switch (req->bRequest) { 3686 case UR_SET_INTERFACE: 3687 goto tr_handle_set_interface; 3688 case UR_CLEAR_FEATURE: 3689 goto tr_valid; /* nop */ 3690 case UR_SET_FEATURE: 3691 default: 3692 goto tr_stalled; 3693 } 3694 break; 3695 3696 case UT_READ_INTERFACE: 3697 switch (req->bRequest) { 3698 case UR_GET_INTERFACE: 3699 goto tr_handle_get_interface; 3700 case UR_GET_STATUS: 3701 goto tr_handle_get_iface_status; 3702 default: 3703 goto tr_stalled; 3704 } 3705 break; 3706 3707 case UT_WRITE_CLASS_INTERFACE: 3708 case UT_WRITE_VENDOR_INTERFACE: 3709 /* XXX forward */ 3710 break; 3711 3712 case UT_READ_CLASS_INTERFACE: 3713 case UT_READ_VENDOR_INTERFACE: 3714 /* XXX forward */ 3715 break; 3716 3717 case UT_WRITE_CLASS_DEVICE: 3718 switch (req->bRequest) { 3719 case UR_CLEAR_FEATURE: 3720 goto tr_valid; 3721 case UR_SET_DESCRIPTOR: 3722 case UR_SET_FEATURE: 3723 break; 3724 default: 3725 goto tr_stalled; 3726 } 3727 break; 3728 3729 case UT_WRITE_CLASS_OTHER: 3730 switch (req->bRequest) { 3731 case UR_CLEAR_FEATURE: 3732 goto tr_handle_clear_port_feature; 3733 case UR_SET_FEATURE: 3734 goto tr_handle_set_port_feature; 3735 case UR_CLEAR_TT_BUFFER: 3736 case UR_RESET_TT: 3737 case UR_STOP_TT: 3738 goto tr_valid; 3739 3740 default: 3741 goto tr_stalled; 3742 } 3743 break; 3744 3745 case UT_READ_CLASS_OTHER: 3746 switch (req->bRequest) { 3747 case UR_GET_TT_STATE: 3748 goto tr_handle_get_tt_state; 3749 case UR_GET_STATUS: 3750 goto tr_handle_get_port_status; 3751 default: 3752 goto tr_stalled; 3753 } 3754 break; 3755 3756 case UT_READ_CLASS_DEVICE: 3757 switch (req->bRequest) { 3758 case UR_GET_DESCRIPTOR: 3759 goto tr_handle_get_class_descriptor; 3760 case UR_GET_STATUS: 3761 goto tr_handle_get_class_status; 3762 3763 default: 3764 goto tr_stalled; 3765 } 3766 break; 3767 default: 3768 goto tr_stalled; 3769 } 3770 goto tr_valid; 3771 3772 tr_handle_get_descriptor: 3773 switch (value >> 8) { 3774 case UDESC_DEVICE: 3775 if (value & 0xff) { 3776 goto tr_stalled; 3777 } 3778 len = sizeof(musbotg_devd); 3779 ptr = (const void *)&musbotg_devd; 3780 goto tr_valid; 3781 case UDESC_DEVICE_QUALIFIER: 3782 if (value & 0xff) { 3783 goto tr_stalled; 3784 } 3785 len = sizeof(musbotg_odevd); 3786 ptr = (const void *)&musbotg_odevd; 3787 goto tr_valid; 3788 case UDESC_CONFIG: 3789 if (value & 0xff) { 3790 goto tr_stalled; 3791 } 3792 len = sizeof(musbotg_confd); 3793 ptr = (const void *)&musbotg_confd; 3794 goto tr_valid; 3795 case UDESC_STRING: 3796 switch (value & 0xff) { 3797 case 0: /* Language table */ 3798 len = sizeof(usb_string_lang_en); 3799 ptr = (const void *)&usb_string_lang_en; 3800 goto tr_valid; 3801 3802 case 1: /* Vendor */ 3803 len = sizeof(musbotg_vendor); 3804 ptr = (const void *)&musbotg_vendor; 3805 goto tr_valid; 3806 3807 case 2: /* Product */ 3808 len = sizeof(musbotg_product); 3809 ptr = (const void *)&musbotg_product; 3810 goto tr_valid; 3811 default: 3812 break; 3813 } 3814 break; 3815 default: 3816 goto tr_stalled; 3817 } 3818 goto tr_stalled; 3819 3820 tr_handle_get_config: 3821 len = 1; 3822 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 3823 goto tr_valid; 3824 3825 tr_handle_get_status: 3826 len = 2; 3827 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 3828 goto tr_valid; 3829 3830 tr_handle_set_address: 3831 if (value & 0xFF00) { 3832 goto tr_stalled; 3833 } 3834 sc->sc_rt_addr = value; 3835 goto tr_valid; 3836 3837 tr_handle_set_config: 3838 if (value >= 2) { 3839 goto tr_stalled; 3840 } 3841 sc->sc_conf = value; 3842 goto tr_valid; 3843 3844 tr_handle_get_interface: 3845 len = 1; 3846 sc->sc_hub_temp.wValue[0] = 0; 3847 goto tr_valid; 3848 3849 tr_handle_get_tt_state: 3850 tr_handle_get_class_status: 3851 tr_handle_get_iface_status: 3852 tr_handle_get_ep_status: 3853 len = 2; 3854 USETW(sc->sc_hub_temp.wValue, 0); 3855 goto tr_valid; 3856 3857 tr_handle_set_halt: 3858 tr_handle_set_interface: 3859 tr_handle_set_wakeup: 3860 tr_handle_clear_wakeup: 3861 tr_handle_clear_halt: 3862 goto tr_valid; 3863 3864 tr_handle_clear_port_feature: 3865 if (index != 1) { 3866 goto tr_stalled; 3867 } 3868 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 3869 3870 switch (value) { 3871 case UHF_PORT_SUSPEND: 3872 if (sc->sc_mode == MUSB2_HOST_MODE) 3873 musbotg_wakeup_host(sc); 3874 else 3875 musbotg_wakeup_peer(sc); 3876 break; 3877 3878 case UHF_PORT_ENABLE: 3879 sc->sc_flags.port_enabled = 0; 3880 break; 3881 3882 case UHF_C_PORT_ENABLE: 3883 sc->sc_flags.change_enabled = 0; 3884 break; 3885 3886 case UHF_C_PORT_OVER_CURRENT: 3887 sc->sc_flags.change_over_current = 0; 3888 break; 3889 3890 case UHF_C_PORT_RESET: 3891 sc->sc_flags.change_reset = 0; 3892 break; 3893 3894 case UHF_PORT_TEST: 3895 case UHF_PORT_INDICATOR: 3896 /* nops */ 3897 break; 3898 3899 case UHF_PORT_POWER: 3900 sc->sc_flags.port_powered = 0; 3901 musbotg_pull_down(sc); 3902 musbotg_clocks_off(sc); 3903 break; 3904 case UHF_C_PORT_CONNECTION: 3905 sc->sc_flags.change_connect = 0; 3906 break; 3907 case UHF_C_PORT_SUSPEND: 3908 sc->sc_flags.change_suspend = 0; 3909 break; 3910 default: 3911 err = USB_ERR_IOERROR; 3912 goto done; 3913 } 3914 goto tr_valid; 3915 3916 tr_handle_set_port_feature: 3917 if (index != 1) { 3918 goto tr_stalled; 3919 } 3920 DPRINTFN(8, "UR_SET_PORT_FEATURE\n"); 3921 3922 switch (value) { 3923 case UHF_PORT_ENABLE: 3924 sc->sc_flags.port_enabled = 1; 3925 break; 3926 case UHF_PORT_SUSPEND: 3927 if (sc->sc_mode == MUSB2_HOST_MODE) 3928 musbotg_suspend_host(sc); 3929 break; 3930 3931 case UHF_PORT_RESET: 3932 if (sc->sc_mode == MUSB2_HOST_MODE) { 3933 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3934 reg |= MUSB2_MASK_RESET; 3935 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3936 3937 /* Wait for 20 msec */ 3938 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5); 3939 3940 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3941 reg &= ~MUSB2_MASK_RESET; 3942 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg); 3943 3944 /* determine line speed */ 3945 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER); 3946 if (reg & MUSB2_MASK_HSMODE) 3947 sc->sc_flags.status_high_speed = 1; 3948 else 3949 sc->sc_flags.status_high_speed = 0; 3950 3951 sc->sc_flags.change_reset = 1; 3952 } else 3953 err = USB_ERR_IOERROR; 3954 break; 3955 3956 case UHF_PORT_TEST: 3957 case UHF_PORT_INDICATOR: 3958 /* nops */ 3959 break; 3960 case UHF_PORT_POWER: 3961 sc->sc_flags.port_powered = 1; 3962 break; 3963 default: 3964 err = USB_ERR_IOERROR; 3965 goto done; 3966 } 3967 goto tr_valid; 3968 3969 tr_handle_get_port_status: 3970 3971 DPRINTFN(8, "UR_GET_PORT_STATUS\n"); 3972 3973 if (index != 1) { 3974 goto tr_stalled; 3975 } 3976 if (sc->sc_flags.status_vbus) { 3977 musbotg_clocks_on(sc); 3978 musbotg_pull_up(sc); 3979 } else { 3980 musbotg_pull_down(sc); 3981 musbotg_clocks_off(sc); 3982 } 3983 3984 /* Select Device Side Mode */ 3985 if (sc->sc_mode == MUSB2_DEVICE_MODE) 3986 value = UPS_PORT_MODE_DEVICE; 3987 else 3988 value = 0; 3989 3990 if (sc->sc_flags.status_high_speed) { 3991 value |= UPS_HIGH_SPEED; 3992 } 3993 if (sc->sc_flags.port_powered) { 3994 value |= UPS_PORT_POWER; 3995 } 3996 if (sc->sc_flags.port_enabled) { 3997 value |= UPS_PORT_ENABLED; 3998 } 3999 4000 if (sc->sc_flags.port_over_current) 4001 value |= UPS_OVERCURRENT_INDICATOR; 4002 4003 if (sc->sc_flags.status_vbus && 4004 sc->sc_flags.status_bus_reset) { 4005 value |= UPS_CURRENT_CONNECT_STATUS; 4006 } 4007 if (sc->sc_flags.status_suspend) { 4008 value |= UPS_SUSPEND; 4009 } 4010 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4011 4012 value = 0; 4013 4014 if (sc->sc_flags.change_connect) { 4015 value |= UPS_C_CONNECT_STATUS; 4016 4017 if (sc->sc_mode == MUSB2_DEVICE_MODE) { 4018 if (sc->sc_flags.status_vbus && 4019 sc->sc_flags.status_bus_reset) { 4020 /* reset EP0 state */ 4021 sc->sc_ep0_busy = 0; 4022 sc->sc_ep0_cmd = 0; 4023 } 4024 } 4025 } 4026 if (sc->sc_flags.change_suspend) 4027 value |= UPS_C_SUSPEND; 4028 if (sc->sc_flags.change_reset) 4029 value |= UPS_C_PORT_RESET; 4030 if (sc->sc_flags.change_over_current) 4031 value |= UPS_C_OVERCURRENT_INDICATOR; 4032 4033 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4034 len = sizeof(sc->sc_hub_temp.ps); 4035 goto tr_valid; 4036 4037 tr_handle_get_class_descriptor: 4038 if (value & 0xFF) { 4039 goto tr_stalled; 4040 } 4041 ptr = (const void *)&musbotg_hubd; 4042 len = sizeof(musbotg_hubd); 4043 goto tr_valid; 4044 4045 tr_stalled: 4046 err = USB_ERR_STALLED; 4047 tr_valid: 4048 done: 4049 *plength = len; 4050 *pptr = ptr; 4051 return (err); 4052 } 4053 4054 static void 4055 musbotg_xfer_setup(struct usb_setup_params *parm) 4056 { 4057 struct musbotg_softc *sc; 4058 struct usb_xfer *xfer; 4059 void *last_obj; 4060 uint32_t ntd; 4061 uint32_t n; 4062 uint8_t ep_no; 4063 4064 sc = MUSBOTG_BUS2SC(parm->udev->bus); 4065 xfer = parm->curr_xfer; 4066 4067 /* 4068 * NOTE: This driver does not use any of the parameters that 4069 * are computed from the following values. Just set some 4070 * reasonable dummies: 4071 */ 4072 parm->hc_max_packet_size = 0x400; 4073 parm->hc_max_frame_size = 0xc00; 4074 4075 if ((parm->methods == &musbotg_device_isoc_methods) || 4076 (parm->methods == &musbotg_device_intr_methods)) 4077 parm->hc_max_packet_count = 3; 4078 else 4079 parm->hc_max_packet_count = 1; 4080 4081 usbd_transfer_setup_sub(parm); 4082 4083 /* 4084 * compute maximum number of TDs 4085 */ 4086 if (parm->methods == &musbotg_device_ctrl_methods) { 4087 4088 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ; 4089 4090 } else if (parm->methods == &musbotg_device_bulk_methods) { 4091 4092 ntd = xfer->nframes + 1 /* SYNC */ ; 4093 4094 } else if (parm->methods == &musbotg_device_intr_methods) { 4095 4096 ntd = xfer->nframes + 1 /* SYNC */ ; 4097 4098 } else if (parm->methods == &musbotg_device_isoc_methods) { 4099 4100 ntd = xfer->nframes + 1 /* SYNC */ ; 4101 4102 } else { 4103 4104 ntd = 0; 4105 } 4106 4107 /* 4108 * check if "usbd_transfer_setup_sub" set an error 4109 */ 4110 if (parm->err) { 4111 return; 4112 } 4113 /* 4114 * allocate transfer descriptors 4115 */ 4116 last_obj = NULL; 4117 4118 ep_no = xfer->endpointno & UE_ADDR; 4119 4120 /* 4121 * Check for a valid endpoint profile in USB device mode: 4122 */ 4123 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4124 const struct usb_hw_ep_profile *pf; 4125 4126 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4127 4128 if (pf == NULL) { 4129 /* should not happen */ 4130 parm->err = USB_ERR_INVAL; 4131 return; 4132 } 4133 } 4134 4135 /* align data */ 4136 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4137 4138 for (n = 0; n != ntd; n++) { 4139 4140 struct musbotg_td *td; 4141 4142 if (parm->buf) { 4143 4144 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4145 4146 /* init TD */ 4147 td->max_frame_size = xfer->max_frame_size; 4148 td->reg_max_packet = xfer->max_packet_size | 4149 ((xfer->max_packet_count - 1) << 11); 4150 td->ep_no = ep_no; 4151 td->obj_next = last_obj; 4152 4153 last_obj = td; 4154 } 4155 parm->size[0] += sizeof(*td); 4156 } 4157 4158 xfer->td_start[0] = last_obj; 4159 } 4160 4161 static void 4162 musbotg_xfer_unsetup(struct usb_xfer *xfer) 4163 { 4164 return; 4165 } 4166 4167 static void 4168 musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4169 { 4170 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4171 4172 if (sc->sc_mode == MUSB2_HOST_MODE) 4173 *pus = 2000; /* microseconds */ 4174 else 4175 *pus = 0; 4176 } 4177 4178 static void 4179 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4180 struct usb_endpoint *ep) 4181 { 4182 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus); 4183 4184 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 4185 ep, udev->address, 4186 edesc->bEndpointAddress, udev->flags.usb_mode, 4187 sc->sc_rt_addr); 4188 4189 if (udev->device_index != sc->sc_rt_addr) { 4190 switch (edesc->bmAttributes & UE_XFERTYPE) { 4191 case UE_CONTROL: 4192 ep->methods = &musbotg_device_ctrl_methods; 4193 break; 4194 case UE_INTERRUPT: 4195 ep->methods = &musbotg_device_intr_methods; 4196 break; 4197 case UE_ISOCHRONOUS: 4198 ep->methods = &musbotg_device_isoc_methods; 4199 break; 4200 case UE_BULK: 4201 ep->methods = &musbotg_device_bulk_methods; 4202 break; 4203 default: 4204 /* do nothing */ 4205 break; 4206 } 4207 } 4208 } 4209 4210 static void 4211 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4212 { 4213 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus); 4214 4215 switch (state) { 4216 case USB_HW_POWER_SUSPEND: 4217 musbotg_suspend(sc); 4218 break; 4219 case USB_HW_POWER_SHUTDOWN: 4220 musbotg_uninit(sc); 4221 break; 4222 case USB_HW_POWER_RESUME: 4223 musbotg_resume(sc); 4224 break; 4225 default: 4226 break; 4227 } 4228 } 4229 4230 static const struct usb_bus_methods musbotg_bus_methods = 4231 { 4232 .endpoint_init = &musbotg_ep_init, 4233 .get_dma_delay = &musbotg_get_dma_delay, 4234 .xfer_setup = &musbotg_xfer_setup, 4235 .xfer_unsetup = &musbotg_xfer_unsetup, 4236 .get_hw_ep_profile = &musbotg_get_hw_ep_profile, 4237 .xfer_stall = &musbotg_xfer_stall, 4238 .set_stall = &musbotg_set_stall, 4239 .clear_stall = &musbotg_clear_stall, 4240 .roothub_exec = &musbotg_roothub_exec, 4241 .xfer_poll = &musbotg_do_poll, 4242 .set_hw_power_sleep = &musbotg_set_hw_power_sleep, 4243 }; 4244