1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 31 * 32 * The EHCI 0.96 spec can be found at 33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 34 * The EHCI 1.0 spec can be found at 35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 36 * and the USB 2.0 spec at 37 * http://www.usb.org/developers/docs/usb_20.zip 38 * 39 */ 40 41 /* 42 * TODO: 43 * 1) command failures are not recovered correctly 44 */ 45 46 #include <sys/cdefs.h> 47 __FBSDID("$FreeBSD$"); 48 49 #include <dev/usb/usb.h> 50 #include <dev/usb/usb_mfunc.h> 51 #include <dev/usb/usb_error.h> 52 #include <dev/usb/usb_defs.h> 53 54 #define USB_DEBUG_VAR ehcidebug 55 56 #include <dev/usb/usb_core.h> 57 #include <dev/usb/usb_debug.h> 58 #include <dev/usb/usb_busdma.h> 59 #include <dev/usb/usb_process.h> 60 #include <dev/usb/usb_sw_transfer.h> 61 #include <dev/usb/usb_transfer.h> 62 #include <dev/usb/usb_device.h> 63 #include <dev/usb/usb_hub.h> 64 #include <dev/usb/usb_util.h> 65 66 #include <dev/usb/usb_controller.h> 67 #include <dev/usb/usb_bus.h> 68 #include <dev/usb/controller/ehci.h> 69 70 #define EHCI_BUS2SC(bus) ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 71 USB_P2U(&(((ehci_softc_t *)0)->sc_bus)))) 72 73 #if USB_DEBUG 74 static int ehcidebug = 0; 75 static int ehcinohighspeed = 0; 76 77 SYSCTL_NODE(_hw_usb2, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 78 SYSCTL_INT(_hw_usb2_ehci, OID_AUTO, debug, CTLFLAG_RW, 79 &ehcidebug, 0, "Debug level"); 80 SYSCTL_INT(_hw_usb2_ehci, OID_AUTO, no_hs, CTLFLAG_RW, 81 &ehcinohighspeed, 0, "Disable High Speed USB"); 82 83 static void ehci_dump_regs(ehci_softc_t *sc); 84 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 85 86 #endif 87 88 #define EHCI_INTR_ENDPT 1 89 90 extern struct usb2_bus_methods ehci_bus_methods; 91 extern struct usb2_pipe_methods ehci_device_bulk_methods; 92 extern struct usb2_pipe_methods ehci_device_ctrl_methods; 93 extern struct usb2_pipe_methods ehci_device_intr_methods; 94 extern struct usb2_pipe_methods ehci_device_isoc_fs_methods; 95 extern struct usb2_pipe_methods ehci_device_isoc_hs_methods; 96 extern struct usb2_pipe_methods ehci_root_ctrl_methods; 97 extern struct usb2_pipe_methods ehci_root_intr_methods; 98 99 static void ehci_do_poll(struct usb2_bus *bus); 100 static void ehci_root_ctrl_poll(ehci_softc_t *sc); 101 static void ehci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 102 static uint8_t ehci_check_transfer(struct usb2_xfer *xfer); 103 static void ehci_timeout(void *arg); 104 105 static usb2_sw_transfer_func_t ehci_root_intr_done; 106 static usb2_sw_transfer_func_t ehci_root_ctrl_done; 107 108 struct ehci_std_temp { 109 ehci_softc_t *sc; 110 struct usb2_page_cache *pc; 111 ehci_qtd_t *td; 112 ehci_qtd_t *td_next; 113 uint32_t average; 114 uint32_t qtd_status; 115 uint32_t len; 116 uint16_t max_frame_size; 117 uint8_t shortpkt; 118 uint8_t auto_data_toggle; 119 uint8_t setup_alt_next; 120 uint8_t short_frames_ok; 121 }; 122 123 void 124 ehci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 125 { 126 ehci_softc_t *sc = EHCI_BUS2SC(bus); 127 uint32_t i; 128 129 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 130 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 131 132 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 133 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 134 135 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 136 cb(bus, sc->sc_hw.intr_start_pc + i, 137 sc->sc_hw.intr_start_pg + i, 138 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 139 } 140 141 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 142 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 143 sc->sc_hw.isoc_hs_start_pg + i, 144 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 145 } 146 147 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 148 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 149 sc->sc_hw.isoc_fs_start_pg + i, 150 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 151 } 152 } 153 154 usb2_error_t 155 ehci_reset(ehci_softc_t *sc) 156 { 157 uint32_t hcr; 158 int i; 159 160 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 161 for (i = 0; i < 100; i++) { 162 usb2_pause_mtx(NULL, hz / 1000); 163 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 164 if (!hcr) { 165 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) { 166 /* 167 * Force USBMODE as requested. Controllers 168 * may have multiple operating modes. 169 */ 170 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE); 171 if (sc->sc_flags & EHCI_SCFLG_SETMODE) { 172 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST; 173 device_printf(sc->sc_bus.bdev, 174 "set host controller mode\n"); 175 } 176 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) { 177 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE; 178 device_printf(sc->sc_bus.bdev, 179 "set big-endian mode\n"); 180 } 181 EOWRITE4(sc, EHCI_USBMODE, usbmode); 182 } 183 return (0); 184 } 185 } 186 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 187 return (USB_ERR_IOERROR); 188 } 189 190 static usb2_error_t 191 ehci_hcreset(ehci_softc_t *sc) 192 { 193 uint32_t hcr; 194 int i; 195 196 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 197 for (i = 0; i < 100; i++) { 198 usb2_pause_mtx(NULL, hz / 1000); 199 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 200 if (hcr) 201 break; 202 } 203 if (!hcr) 204 /* 205 * Fall through and try reset anyway even though 206 * Table 2-9 in the EHCI spec says this will result 207 * in undefined behavior. 208 */ 209 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 210 211 return ehci_reset(sc); 212 } 213 214 usb2_error_t 215 ehci_init(ehci_softc_t *sc) 216 { 217 struct usb2_page_search buf_res; 218 uint32_t version; 219 uint32_t sparams; 220 uint32_t cparams; 221 uint32_t hcr; 222 uint16_t i; 223 uint16_t x; 224 uint16_t y; 225 uint16_t bit; 226 usb2_error_t err = 0; 227 228 DPRINTF("start\n"); 229 230 usb2_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 231 232 #if USB_DEBUG 233 if (ehcidebug > 2) { 234 ehci_dump_regs(sc); 235 } 236 #endif 237 238 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 239 240 version = EREAD2(sc, EHCI_HCIVERSION); 241 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 242 version >> 8, version & 0xff); 243 244 sparams = EREAD4(sc, EHCI_HCSPARAMS); 245 DPRINTF("sparams=0x%x\n", sparams); 246 247 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 248 cparams = EREAD4(sc, EHCI_HCCPARAMS); 249 DPRINTF("cparams=0x%x\n", cparams); 250 251 if (EHCI_HCC_64BIT(cparams)) { 252 DPRINTF("HCC uses 64-bit structures\n"); 253 254 /* MUST clear segment register if 64 bit capable */ 255 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 256 } 257 sc->sc_bus.usbrev = USB_REV_2_0; 258 259 /* Reset the controller */ 260 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 261 262 err = ehci_hcreset(sc); 263 if (err) { 264 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 265 return (err); 266 } 267 /* 268 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 269 * bytes 2: 256*4 bytes 3: unknown 270 */ 271 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 272 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 273 return (USB_ERR_IOERROR); 274 } 275 /* set up the bus struct */ 276 sc->sc_bus.methods = &ehci_bus_methods; 277 278 sc->sc_eintrs = EHCI_NORMAL_INTRS; 279 280 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 281 ehci_qh_t *qh; 282 283 usb2_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 284 285 qh = buf_res.buffer; 286 287 /* initialize page cache pointer */ 288 289 qh->page_cache = sc->sc_hw.intr_start_pc + i; 290 291 /* store a pointer to queue head */ 292 293 sc->sc_intr_p_last[i] = qh; 294 295 qh->qh_self = 296 htohc32(sc, buf_res.physaddr) | 297 htohc32(sc, EHCI_LINK_QH); 298 299 qh->qh_endp = 300 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 301 qh->qh_endphub = 302 htohc32(sc, EHCI_QH_SET_MULT(1)); 303 qh->qh_curqtd = 0; 304 305 qh->qh_qtd.qtd_next = 306 htohc32(sc, EHCI_LINK_TERMINATE); 307 qh->qh_qtd.qtd_altnext = 308 htohc32(sc, EHCI_LINK_TERMINATE); 309 qh->qh_qtd.qtd_status = 310 htohc32(sc, EHCI_QTD_HALTED); 311 } 312 313 /* 314 * the QHs are arranged to give poll intervals that are 315 * powers of 2 times 1ms 316 */ 317 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 318 while (bit) { 319 x = bit; 320 while (x & bit) { 321 ehci_qh_t *qh_x; 322 ehci_qh_t *qh_y; 323 324 y = (x ^ bit) | (bit / 2); 325 326 qh_x = sc->sc_intr_p_last[x]; 327 qh_y = sc->sc_intr_p_last[y]; 328 329 /* 330 * the next QH has half the poll interval 331 */ 332 qh_x->qh_link = qh_y->qh_self; 333 334 x++; 335 } 336 bit >>= 1; 337 } 338 339 if (1) { 340 ehci_qh_t *qh; 341 342 qh = sc->sc_intr_p_last[0]; 343 344 /* the last (1ms) QH terminates */ 345 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 346 } 347 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 348 ehci_sitd_t *sitd; 349 ehci_itd_t *itd; 350 351 usb2_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 352 353 sitd = buf_res.buffer; 354 355 /* initialize page cache pointer */ 356 357 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 358 359 /* store a pointer to the transfer descriptor */ 360 361 sc->sc_isoc_fs_p_last[i] = sitd; 362 363 /* initialize full speed isochronous */ 364 365 sitd->sitd_self = 366 htohc32(sc, buf_res.physaddr) | 367 htohc32(sc, EHCI_LINK_SITD); 368 369 sitd->sitd_back = 370 htohc32(sc, EHCI_LINK_TERMINATE); 371 372 sitd->sitd_next = 373 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 374 375 376 usb2_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 377 378 itd = buf_res.buffer; 379 380 /* initialize page cache pointer */ 381 382 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 383 384 /* store a pointer to the transfer descriptor */ 385 386 sc->sc_isoc_hs_p_last[i] = itd; 387 388 /* initialize high speed isochronous */ 389 390 itd->itd_self = 391 htohc32(sc, buf_res.physaddr) | 392 htohc32(sc, EHCI_LINK_ITD); 393 394 itd->itd_next = 395 sitd->sitd_self; 396 } 397 398 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 399 400 if (1) { 401 uint32_t *pframes; 402 403 pframes = buf_res.buffer; 404 405 /* 406 * execution order: 407 * pframes -> high speed isochronous -> 408 * full speed isochronous -> interrupt QH's 409 */ 410 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 411 pframes[i] = sc->sc_isoc_hs_p_last 412 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 413 } 414 } 415 /* setup sync list pointer */ 416 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 417 418 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 419 420 if (1) { 421 422 ehci_qh_t *qh; 423 424 qh = buf_res.buffer; 425 426 /* initialize page cache pointer */ 427 428 qh->page_cache = &sc->sc_hw.async_start_pc; 429 430 /* store a pointer to the queue head */ 431 432 sc->sc_async_p_last = qh; 433 434 /* init dummy QH that starts the async list */ 435 436 qh->qh_self = 437 htohc32(sc, buf_res.physaddr) | 438 htohc32(sc, EHCI_LINK_QH); 439 440 /* fill the QH */ 441 qh->qh_endp = 442 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 443 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 444 qh->qh_link = qh->qh_self; 445 qh->qh_curqtd = 0; 446 447 /* fill the overlay qTD */ 448 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 449 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 450 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 451 } 452 /* flush all cache into memory */ 453 454 usb2_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 455 456 #if USB_DEBUG 457 if (ehcidebug) { 458 ehci_dump_sqh(sc, sc->sc_async_p_last); 459 } 460 #endif 461 462 /* setup async list pointer */ 463 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 464 465 466 /* enable interrupts */ 467 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 468 469 /* turn on controller */ 470 EOWRITE4(sc, EHCI_USBCMD, 471 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 472 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 473 EHCI_CMD_ASE | 474 EHCI_CMD_PSE | 475 EHCI_CMD_RS); 476 477 /* Take over port ownership */ 478 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 479 480 for (i = 0; i < 100; i++) { 481 usb2_pause_mtx(NULL, hz / 1000); 482 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 483 if (!hcr) { 484 break; 485 } 486 } 487 if (hcr) { 488 device_printf(sc->sc_bus.bdev, "run timeout\n"); 489 return (USB_ERR_IOERROR); 490 } 491 492 if (!err) { 493 /* catch any lost interrupts */ 494 ehci_do_poll(&sc->sc_bus); 495 } 496 return (err); 497 } 498 499 /* 500 * shut down the controller when the system is going down 501 */ 502 void 503 ehci_detach(ehci_softc_t *sc) 504 { 505 USB_BUS_LOCK(&sc->sc_bus); 506 507 usb2_callout_stop(&sc->sc_tmo_pcd); 508 509 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 510 USB_BUS_UNLOCK(&sc->sc_bus); 511 512 if (ehci_hcreset(sc)) { 513 DPRINTF("reset failed!\n"); 514 } 515 516 /* XXX let stray task complete */ 517 usb2_pause_mtx(NULL, hz / 20); 518 519 usb2_callout_drain(&sc->sc_tmo_pcd); 520 } 521 522 void 523 ehci_suspend(ehci_softc_t *sc) 524 { 525 uint32_t cmd; 526 uint32_t hcr; 527 uint8_t i; 528 529 USB_BUS_LOCK(&sc->sc_bus); 530 531 for (i = 1; i <= sc->sc_noport; i++) { 532 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 533 if (((cmd & EHCI_PS_PO) == 0) && 534 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) { 535 EOWRITE4(sc, EHCI_PORTSC(i), 536 cmd | EHCI_PS_SUSP); 537 } 538 } 539 540 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 541 542 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 543 EOWRITE4(sc, EHCI_USBCMD, cmd); 544 545 for (i = 0; i < 100; i++) { 546 hcr = EOREAD4(sc, EHCI_USBSTS) & 547 (EHCI_STS_ASS | EHCI_STS_PSS); 548 549 if (hcr == 0) { 550 break; 551 } 552 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 553 } 554 555 if (hcr != 0) { 556 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 557 } 558 cmd &= ~EHCI_CMD_RS; 559 EOWRITE4(sc, EHCI_USBCMD, cmd); 560 561 for (i = 0; i < 100; i++) { 562 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 563 if (hcr == EHCI_STS_HCH) { 564 break; 565 } 566 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 567 } 568 569 if (hcr != EHCI_STS_HCH) { 570 device_printf(sc->sc_bus.bdev, 571 "config timeout\n"); 572 } 573 USB_BUS_UNLOCK(&sc->sc_bus); 574 } 575 576 void 577 ehci_resume(ehci_softc_t *sc) 578 { 579 struct usb2_page_search buf_res; 580 uint32_t cmd; 581 uint32_t hcr; 582 uint8_t i; 583 584 USB_BUS_LOCK(&sc->sc_bus); 585 586 /* restore things in case the bios doesn't */ 587 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 588 589 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 590 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 591 592 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 593 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 594 595 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 596 597 hcr = 0; 598 for (i = 1; i <= sc->sc_noport; i++) { 599 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 600 if (((cmd & EHCI_PS_PO) == 0) && 601 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 602 EOWRITE4(sc, EHCI_PORTSC(i), 603 cmd | EHCI_PS_FPR); 604 hcr = 1; 605 } 606 } 607 608 if (hcr) { 609 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 610 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 611 612 for (i = 1; i <= sc->sc_noport; i++) { 613 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 614 if (((cmd & EHCI_PS_PO) == 0) && 615 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 616 EOWRITE4(sc, EHCI_PORTSC(i), 617 cmd & ~EHCI_PS_FPR); 618 } 619 } 620 } 621 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 622 623 for (i = 0; i < 100; i++) { 624 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 625 if (hcr != EHCI_STS_HCH) { 626 break; 627 } 628 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 629 } 630 if (hcr == EHCI_STS_HCH) { 631 device_printf(sc->sc_bus.bdev, "config timeout\n"); 632 } 633 634 USB_BUS_UNLOCK(&sc->sc_bus); 635 636 usb2_pause_mtx(NULL, 637 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 638 639 /* catch any lost interrupts */ 640 ehci_do_poll(&sc->sc_bus); 641 } 642 643 void 644 ehci_shutdown(ehci_softc_t *sc) 645 { 646 DPRINTF("stopping the HC\n"); 647 648 if (ehci_hcreset(sc)) { 649 DPRINTF("reset failed!\n"); 650 } 651 } 652 653 #if USB_DEBUG 654 static void 655 ehci_dump_regs(ehci_softc_t *sc) 656 { 657 uint32_t i; 658 659 i = EOREAD4(sc, EHCI_USBCMD); 660 printf("cmd=0x%08x\n", i); 661 662 if (i & EHCI_CMD_ITC_1) 663 printf(" EHCI_CMD_ITC_1\n"); 664 if (i & EHCI_CMD_ITC_2) 665 printf(" EHCI_CMD_ITC_2\n"); 666 if (i & EHCI_CMD_ITC_4) 667 printf(" EHCI_CMD_ITC_4\n"); 668 if (i & EHCI_CMD_ITC_8) 669 printf(" EHCI_CMD_ITC_8\n"); 670 if (i & EHCI_CMD_ITC_16) 671 printf(" EHCI_CMD_ITC_16\n"); 672 if (i & EHCI_CMD_ITC_32) 673 printf(" EHCI_CMD_ITC_32\n"); 674 if (i & EHCI_CMD_ITC_64) 675 printf(" EHCI_CMD_ITC_64\n"); 676 if (i & EHCI_CMD_ASPME) 677 printf(" EHCI_CMD_ASPME\n"); 678 if (i & EHCI_CMD_ASPMC) 679 printf(" EHCI_CMD_ASPMC\n"); 680 if (i & EHCI_CMD_LHCR) 681 printf(" EHCI_CMD_LHCR\n"); 682 if (i & EHCI_CMD_IAAD) 683 printf(" EHCI_CMD_IAAD\n"); 684 if (i & EHCI_CMD_ASE) 685 printf(" EHCI_CMD_ASE\n"); 686 if (i & EHCI_CMD_PSE) 687 printf(" EHCI_CMD_PSE\n"); 688 if (i & EHCI_CMD_FLS_M) 689 printf(" EHCI_CMD_FLS_M\n"); 690 if (i & EHCI_CMD_HCRESET) 691 printf(" EHCI_CMD_HCRESET\n"); 692 if (i & EHCI_CMD_RS) 693 printf(" EHCI_CMD_RS\n"); 694 695 i = EOREAD4(sc, EHCI_USBSTS); 696 697 printf("sts=0x%08x\n", i); 698 699 if (i & EHCI_STS_ASS) 700 printf(" EHCI_STS_ASS\n"); 701 if (i & EHCI_STS_PSS) 702 printf(" EHCI_STS_PSS\n"); 703 if (i & EHCI_STS_REC) 704 printf(" EHCI_STS_REC\n"); 705 if (i & EHCI_STS_HCH) 706 printf(" EHCI_STS_HCH\n"); 707 if (i & EHCI_STS_IAA) 708 printf(" EHCI_STS_IAA\n"); 709 if (i & EHCI_STS_HSE) 710 printf(" EHCI_STS_HSE\n"); 711 if (i & EHCI_STS_FLR) 712 printf(" EHCI_STS_FLR\n"); 713 if (i & EHCI_STS_PCD) 714 printf(" EHCI_STS_PCD\n"); 715 if (i & EHCI_STS_ERRINT) 716 printf(" EHCI_STS_ERRINT\n"); 717 if (i & EHCI_STS_INT) 718 printf(" EHCI_STS_INT\n"); 719 720 printf("ien=0x%08x\n", 721 EOREAD4(sc, EHCI_USBINTR)); 722 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 723 EOREAD4(sc, EHCI_FRINDEX), 724 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 725 EOREAD4(sc, EHCI_PERIODICLISTBASE), 726 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 727 for (i = 1; i <= sc->sc_noport; i++) { 728 printf("port %d status=0x%08x\n", i, 729 EOREAD4(sc, EHCI_PORTSC(i))); 730 } 731 } 732 733 static void 734 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 735 { 736 link = hc32toh(sc, link); 737 printf("0x%08x", link); 738 if (link & EHCI_LINK_TERMINATE) 739 printf("<T>"); 740 else { 741 printf("<"); 742 if (type) { 743 switch (EHCI_LINK_TYPE(link)) { 744 case EHCI_LINK_ITD: 745 printf("ITD"); 746 break; 747 case EHCI_LINK_QH: 748 printf("QH"); 749 break; 750 case EHCI_LINK_SITD: 751 printf("SITD"); 752 break; 753 case EHCI_LINK_FSTN: 754 printf("FSTN"); 755 break; 756 } 757 } 758 printf(">"); 759 } 760 } 761 762 static void 763 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 764 { 765 uint32_t s; 766 767 printf(" next="); 768 ehci_dump_link(sc, qtd->qtd_next, 0); 769 printf(" altnext="); 770 ehci_dump_link(sc, qtd->qtd_altnext, 0); 771 printf("\n"); 772 s = hc32toh(sc, qtd->qtd_status); 773 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 774 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 775 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 776 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 777 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 778 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 779 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 780 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 781 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 782 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 783 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 784 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 785 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 786 787 for (s = 0; s < 5; s++) { 788 printf(" buffer[%d]=0x%08x\n", s, 789 hc32toh(sc, qtd->qtd_buffer[s])); 790 } 791 for (s = 0; s < 5; s++) { 792 printf(" buffer_hi[%d]=0x%08x\n", s, 793 hc32toh(sc, qtd->qtd_buffer_hi[s])); 794 } 795 } 796 797 static uint8_t 798 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 799 { 800 uint8_t temp; 801 802 usb2_pc_cpu_invalidate(sqtd->page_cache); 803 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 804 ehci_dump_qtd(sc, sqtd); 805 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 806 return (temp); 807 } 808 809 static void 810 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 811 { 812 uint16_t i; 813 uint8_t stop; 814 815 stop = 0; 816 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 817 stop = ehci_dump_sqtd(sc, sqtd); 818 } 819 if (sqtd) { 820 printf("dump aborted, too many TDs\n"); 821 } 822 } 823 824 static void 825 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 826 { 827 uint32_t endp; 828 uint32_t endphub; 829 830 usb2_pc_cpu_invalidate(qh->page_cache); 831 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 832 printf(" link="); 833 ehci_dump_link(sc, qh->qh_link, 1); 834 printf("\n"); 835 endp = hc32toh(sc, qh->qh_endp); 836 printf(" endp=0x%08x\n", endp); 837 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 838 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 839 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 840 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 841 printf(" mpl=0x%x ctl=%d nrl=%d\n", 842 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 843 EHCI_QH_GET_NRL(endp)); 844 endphub = hc32toh(sc, qh->qh_endphub); 845 printf(" endphub=0x%08x\n", endphub); 846 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 847 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 848 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 849 EHCI_QH_GET_MULT(endphub)); 850 printf(" curqtd="); 851 ehci_dump_link(sc, qh->qh_curqtd, 0); 852 printf("\n"); 853 printf("Overlay qTD:\n"); 854 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 855 } 856 857 static void 858 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 859 { 860 usb2_pc_cpu_invalidate(sitd->page_cache); 861 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 862 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 863 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 864 hc32toh(sc, sitd->sitd_portaddr), 865 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 866 ? "in" : "out", 867 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 868 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 869 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 870 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 871 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 872 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 873 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 874 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 875 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 876 hc32toh(sc, sitd->sitd_back), 877 hc32toh(sc, sitd->sitd_bp[0]), 878 hc32toh(sc, sitd->sitd_bp[1]), 879 hc32toh(sc, sitd->sitd_bp_hi[0]), 880 hc32toh(sc, sitd->sitd_bp_hi[1])); 881 } 882 883 static void 884 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 885 { 886 usb2_pc_cpu_invalidate(itd->page_cache); 887 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 888 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 889 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 890 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 891 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 892 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 893 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 894 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 895 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 896 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 897 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 898 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 899 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 900 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 901 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 902 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 903 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 904 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 905 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 906 printf(" addr=0x%02x; endpt=0x%01x\n", 907 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 908 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 909 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 910 printf(" dir=%s; mpl=0x%02x\n", 911 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 912 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 913 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 914 hc32toh(sc, itd->itd_bp[2]), 915 hc32toh(sc, itd->itd_bp[3]), 916 hc32toh(sc, itd->itd_bp[4]), 917 hc32toh(sc, itd->itd_bp[5]), 918 hc32toh(sc, itd->itd_bp[6])); 919 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 920 " 0x%08x,0x%08x,0x%08x\n", 921 hc32toh(sc, itd->itd_bp_hi[0]), 922 hc32toh(sc, itd->itd_bp_hi[1]), 923 hc32toh(sc, itd->itd_bp_hi[2]), 924 hc32toh(sc, itd->itd_bp_hi[3]), 925 hc32toh(sc, itd->itd_bp_hi[4]), 926 hc32toh(sc, itd->itd_bp_hi[5]), 927 hc32toh(sc, itd->itd_bp_hi[6])); 928 } 929 930 static void 931 ehci_dump_isoc(ehci_softc_t *sc) 932 { 933 ehci_itd_t *itd; 934 ehci_sitd_t *sitd; 935 uint16_t max = 1000; 936 uint16_t pos; 937 938 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 939 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 940 941 printf("%s: isochronous dump from frame 0x%03x:\n", 942 __FUNCTION__, pos); 943 944 itd = sc->sc_isoc_hs_p_last[pos]; 945 sitd = sc->sc_isoc_fs_p_last[pos]; 946 947 while (itd && max && max--) { 948 ehci_dump_itd(sc, itd); 949 itd = itd->prev; 950 } 951 952 while (sitd && max && max--) { 953 ehci_dump_sitd(sc, sitd); 954 sitd = sitd->prev; 955 } 956 } 957 958 #endif 959 960 static void 961 ehci_transfer_intr_enqueue(struct usb2_xfer *xfer) 962 { 963 /* check for early completion */ 964 if (ehci_check_transfer(xfer)) { 965 return; 966 } 967 /* put transfer on interrupt queue */ 968 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 969 970 /* start timeout, if any */ 971 if (xfer->timeout != 0) { 972 usb2_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 973 } 974 } 975 976 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 977 static ehci_sitd_t * 978 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 979 { 980 DPRINTFN(11, "%p to %p\n", std, last); 981 982 /* (sc->sc_bus.mtx) must be locked */ 983 984 std->next = last->next; 985 std->sitd_next = last->sitd_next; 986 987 std->prev = last; 988 989 usb2_pc_cpu_flush(std->page_cache); 990 991 /* 992 * the last->next->prev is never followed: std->next->prev = std; 993 */ 994 last->next = std; 995 last->sitd_next = std->sitd_self; 996 997 usb2_pc_cpu_flush(last->page_cache); 998 999 return (std); 1000 } 1001 1002 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 1003 static ehci_itd_t * 1004 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1005 { 1006 DPRINTFN(11, "%p to %p\n", std, last); 1007 1008 /* (sc->sc_bus.mtx) must be locked */ 1009 1010 std->next = last->next; 1011 std->itd_next = last->itd_next; 1012 1013 std->prev = last; 1014 1015 usb2_pc_cpu_flush(std->page_cache); 1016 1017 /* 1018 * the last->next->prev is never followed: std->next->prev = std; 1019 */ 1020 last->next = std; 1021 last->itd_next = std->itd_self; 1022 1023 usb2_pc_cpu_flush(last->page_cache); 1024 1025 return (std); 1026 } 1027 1028 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 1029 static ehci_qh_t * 1030 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1031 { 1032 DPRINTFN(11, "%p to %p\n", sqh, last); 1033 1034 if (sqh->prev != NULL) { 1035 /* should not happen */ 1036 DPRINTFN(0, "QH already linked!\n"); 1037 return (last); 1038 } 1039 /* (sc->sc_bus.mtx) must be locked */ 1040 1041 sqh->next = last->next; 1042 sqh->qh_link = last->qh_link; 1043 1044 sqh->prev = last; 1045 1046 usb2_pc_cpu_flush(sqh->page_cache); 1047 1048 /* 1049 * the last->next->prev is never followed: sqh->next->prev = sqh; 1050 */ 1051 1052 last->next = sqh; 1053 last->qh_link = sqh->qh_self; 1054 1055 usb2_pc_cpu_flush(last->page_cache); 1056 1057 return (sqh); 1058 } 1059 1060 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1061 static ehci_sitd_t * 1062 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1063 { 1064 DPRINTFN(11, "%p from %p\n", std, last); 1065 1066 /* (sc->sc_bus.mtx) must be locked */ 1067 1068 std->prev->next = std->next; 1069 std->prev->sitd_next = std->sitd_next; 1070 1071 usb2_pc_cpu_flush(std->prev->page_cache); 1072 1073 if (std->next) { 1074 std->next->prev = std->prev; 1075 usb2_pc_cpu_flush(std->next->page_cache); 1076 } 1077 return ((last == std) ? std->prev : last); 1078 } 1079 1080 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1081 static ehci_itd_t * 1082 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1083 { 1084 DPRINTFN(11, "%p from %p\n", std, last); 1085 1086 /* (sc->sc_bus.mtx) must be locked */ 1087 1088 std->prev->next = std->next; 1089 std->prev->itd_next = std->itd_next; 1090 1091 usb2_pc_cpu_flush(std->prev->page_cache); 1092 1093 if (std->next) { 1094 std->next->prev = std->prev; 1095 usb2_pc_cpu_flush(std->next->page_cache); 1096 } 1097 return ((last == std) ? std->prev : last); 1098 } 1099 1100 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1101 static ehci_qh_t * 1102 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1103 { 1104 DPRINTFN(11, "%p from %p\n", sqh, last); 1105 1106 /* (sc->sc_bus.mtx) must be locked */ 1107 1108 /* only remove if not removed from a queue */ 1109 if (sqh->prev) { 1110 1111 sqh->prev->next = sqh->next; 1112 sqh->prev->qh_link = sqh->qh_link; 1113 1114 usb2_pc_cpu_flush(sqh->prev->page_cache); 1115 1116 if (sqh->next) { 1117 sqh->next->prev = sqh->prev; 1118 usb2_pc_cpu_flush(sqh->next->page_cache); 1119 } 1120 last = ((last == sqh) ? sqh->prev : last); 1121 1122 sqh->prev = 0; 1123 1124 usb2_pc_cpu_flush(sqh->page_cache); 1125 } 1126 return (last); 1127 } 1128 1129 static usb2_error_t 1130 ehci_non_isoc_done_sub(struct usb2_xfer *xfer) 1131 { 1132 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1133 ehci_qtd_t *td; 1134 ehci_qtd_t *td_alt_next; 1135 uint32_t status; 1136 uint16_t len; 1137 1138 td = xfer->td_transfer_cache; 1139 td_alt_next = td->alt_next; 1140 1141 if (xfer->aframes != xfer->nframes) { 1142 xfer->frlengths[xfer->aframes] = 0; 1143 } 1144 while (1) { 1145 1146 usb2_pc_cpu_invalidate(td->page_cache); 1147 status = hc32toh(sc, td->qtd_status); 1148 1149 len = EHCI_QTD_GET_BYTES(status); 1150 1151 /* 1152 * Verify the status length and 1153 * add the length to "frlengths[]": 1154 */ 1155 if (len > td->len) { 1156 /* should not happen */ 1157 DPRINTF("Invalid status length, " 1158 "0x%04x/0x%04x bytes\n", len, td->len); 1159 status |= EHCI_QTD_HALTED; 1160 } else if (xfer->aframes != xfer->nframes) { 1161 xfer->frlengths[xfer->aframes] += td->len - len; 1162 } 1163 /* Check for last transfer */ 1164 if (((void *)td) == xfer->td_transfer_last) { 1165 if (len == 0) { 1166 /* 1167 * Halt is ok if descriptor is last, 1168 * and complete: 1169 */ 1170 status &= ~EHCI_QTD_HALTED; 1171 } 1172 td = NULL; 1173 break; 1174 } 1175 /* Check for transfer error */ 1176 if (status & EHCI_QTD_HALTED) { 1177 /* the transfer is finished */ 1178 td = NULL; 1179 break; 1180 } 1181 /* Check for short transfer */ 1182 if (len > 0) { 1183 if (xfer->flags_int.short_frames_ok) { 1184 /* follow alt next */ 1185 td = td->alt_next; 1186 } else { 1187 /* the transfer is finished */ 1188 td = NULL; 1189 } 1190 break; 1191 } 1192 td = td->obj_next; 1193 1194 if (td->alt_next != td_alt_next) { 1195 /* this USB frame is complete */ 1196 break; 1197 } 1198 } 1199 1200 /* update transfer cache */ 1201 1202 xfer->td_transfer_cache = td; 1203 1204 /* update data toggle */ 1205 1206 xfer->pipe->toggle_next = 1207 (status & EHCI_QTD_TOGGLE_MASK) ? 1 : 0; 1208 1209 #if USB_DEBUG 1210 if (status & EHCI_QTD_STATERRS) { 1211 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1212 "status=%s%s%s%s%s%s%s%s\n", 1213 xfer->address, xfer->endpoint, xfer->aframes, 1214 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1215 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1216 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1217 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1218 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1219 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1220 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1221 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1222 } 1223 #endif 1224 1225 return ((status & EHCI_QTD_HALTED) ? 1226 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1227 } 1228 1229 static void 1230 ehci_non_isoc_done(struct usb2_xfer *xfer) 1231 { 1232 usb2_error_t err = 0; 1233 1234 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1235 xfer, xfer->pipe); 1236 1237 #if USB_DEBUG 1238 if (ehcidebug > 10) { 1239 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1240 1241 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1242 } 1243 #endif 1244 1245 /* reset scanner */ 1246 1247 xfer->td_transfer_cache = xfer->td_transfer_first; 1248 1249 if (xfer->flags_int.control_xfr) { 1250 1251 if (xfer->flags_int.control_hdr) { 1252 1253 err = ehci_non_isoc_done_sub(xfer); 1254 } 1255 xfer->aframes = 1; 1256 1257 if (xfer->td_transfer_cache == NULL) { 1258 goto done; 1259 } 1260 } 1261 while (xfer->aframes != xfer->nframes) { 1262 1263 err = ehci_non_isoc_done_sub(xfer); 1264 xfer->aframes++; 1265 1266 if (xfer->td_transfer_cache == NULL) { 1267 goto done; 1268 } 1269 } 1270 1271 if (xfer->flags_int.control_xfr && 1272 !xfer->flags_int.control_act) { 1273 1274 err = ehci_non_isoc_done_sub(xfer); 1275 } 1276 done: 1277 ehci_device_done(xfer, err); 1278 } 1279 1280 /*------------------------------------------------------------------------* 1281 * ehci_check_transfer 1282 * 1283 * Return values: 1284 * 0: USB transfer is not finished 1285 * Else: USB transfer is finished 1286 *------------------------------------------------------------------------*/ 1287 static uint8_t 1288 ehci_check_transfer(struct usb2_xfer *xfer) 1289 { 1290 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1291 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1292 1293 uint32_t status; 1294 1295 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1296 1297 if (methods == &ehci_device_isoc_fs_methods) { 1298 ehci_sitd_t *td; 1299 1300 /* isochronous full speed transfer */ 1301 1302 td = xfer->td_transfer_last; 1303 usb2_pc_cpu_invalidate(td->page_cache); 1304 status = hc32toh(sc, td->sitd_status); 1305 1306 /* also check if first is complete */ 1307 1308 td = xfer->td_transfer_first; 1309 usb2_pc_cpu_invalidate(td->page_cache); 1310 status |= hc32toh(sc, td->sitd_status); 1311 1312 if (!(status & EHCI_SITD_ACTIVE)) { 1313 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1314 goto transferred; 1315 } 1316 } else if (methods == &ehci_device_isoc_hs_methods) { 1317 ehci_itd_t *td; 1318 1319 /* isochronous high speed transfer */ 1320 1321 td = xfer->td_transfer_last; 1322 usb2_pc_cpu_invalidate(td->page_cache); 1323 status = 1324 td->itd_status[0] | td->itd_status[1] | 1325 td->itd_status[2] | td->itd_status[3] | 1326 td->itd_status[4] | td->itd_status[5] | 1327 td->itd_status[6] | td->itd_status[7]; 1328 1329 /* also check first transfer */ 1330 td = xfer->td_transfer_first; 1331 usb2_pc_cpu_invalidate(td->page_cache); 1332 status |= 1333 td->itd_status[0] | td->itd_status[1] | 1334 td->itd_status[2] | td->itd_status[3] | 1335 td->itd_status[4] | td->itd_status[5] | 1336 td->itd_status[6] | td->itd_status[7]; 1337 1338 /* if no transactions are active we continue */ 1339 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1340 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1341 goto transferred; 1342 } 1343 } else { 1344 ehci_qtd_t *td; 1345 1346 /* non-isochronous transfer */ 1347 1348 /* 1349 * check whether there is an error somewhere in the middle, 1350 * or whether there was a short packet (SPD and not ACTIVE) 1351 */ 1352 td = xfer->td_transfer_cache; 1353 1354 while (1) { 1355 usb2_pc_cpu_invalidate(td->page_cache); 1356 status = hc32toh(sc, td->qtd_status); 1357 1358 /* 1359 * if there is an active TD the transfer isn't done 1360 */ 1361 if (status & EHCI_QTD_ACTIVE) { 1362 /* update cache */ 1363 xfer->td_transfer_cache = td; 1364 goto done; 1365 } 1366 /* 1367 * last transfer descriptor makes the transfer done 1368 */ 1369 if (((void *)td) == xfer->td_transfer_last) { 1370 break; 1371 } 1372 /* 1373 * any kind of error makes the transfer done 1374 */ 1375 if (status & EHCI_QTD_HALTED) { 1376 break; 1377 } 1378 /* 1379 * if there is no alternate next transfer, a short 1380 * packet also makes the transfer done 1381 */ 1382 if (EHCI_QTD_GET_BYTES(status)) { 1383 if (xfer->flags_int.short_frames_ok) { 1384 /* follow alt next */ 1385 if (td->alt_next) { 1386 td = td->alt_next; 1387 continue; 1388 } 1389 } 1390 /* transfer is done */ 1391 break; 1392 } 1393 td = td->obj_next; 1394 } 1395 ehci_non_isoc_done(xfer); 1396 goto transferred; 1397 } 1398 1399 done: 1400 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1401 return (0); 1402 1403 transferred: 1404 return (1); 1405 } 1406 1407 static void 1408 ehci_pcd_enable(ehci_softc_t *sc) 1409 { 1410 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1411 1412 sc->sc_eintrs |= EHCI_STS_PCD; 1413 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1414 1415 /* acknowledge any PCD interrupt */ 1416 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1417 1418 usb2_sw_transfer(&sc->sc_root_intr, 1419 &ehci_root_intr_done); 1420 } 1421 1422 static void 1423 ehci_interrupt_poll(ehci_softc_t *sc) 1424 { 1425 struct usb2_xfer *xfer; 1426 1427 repeat: 1428 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1429 /* 1430 * check if transfer is transferred 1431 */ 1432 if (ehci_check_transfer(xfer)) { 1433 /* queue has been modified */ 1434 goto repeat; 1435 } 1436 } 1437 } 1438 1439 /*------------------------------------------------------------------------* 1440 * ehci_interrupt - EHCI interrupt handler 1441 * 1442 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1443 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1444 * is present ! 1445 *------------------------------------------------------------------------*/ 1446 void 1447 ehci_interrupt(ehci_softc_t *sc) 1448 { 1449 uint32_t status; 1450 1451 USB_BUS_LOCK(&sc->sc_bus); 1452 1453 DPRINTFN(16, "real interrupt\n"); 1454 1455 #if USB_DEBUG 1456 if (ehcidebug > 15) { 1457 ehci_dump_regs(sc); 1458 } 1459 #endif 1460 1461 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1462 if (status == 0) { 1463 /* the interrupt was not for us */ 1464 goto done; 1465 } 1466 if (!(status & sc->sc_eintrs)) { 1467 goto done; 1468 } 1469 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1470 1471 status &= sc->sc_eintrs; 1472 1473 if (status & EHCI_STS_HSE) { 1474 printf("%s: unrecoverable error, " 1475 "controller halted\n", __FUNCTION__); 1476 #if USB_DEBUG 1477 ehci_dump_regs(sc); 1478 ehci_dump_isoc(sc); 1479 #endif 1480 } 1481 if (status & EHCI_STS_PCD) { 1482 /* 1483 * Disable PCD interrupt for now, because it will be 1484 * on until the port has been reset. 1485 */ 1486 sc->sc_eintrs &= ~EHCI_STS_PCD; 1487 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1488 1489 usb2_sw_transfer(&sc->sc_root_intr, 1490 &ehci_root_intr_done); 1491 1492 /* do not allow RHSC interrupts > 1 per second */ 1493 usb2_callout_reset(&sc->sc_tmo_pcd, hz, 1494 (void *)&ehci_pcd_enable, sc); 1495 } 1496 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1497 1498 if (status != 0) { 1499 /* block unprocessed interrupts */ 1500 sc->sc_eintrs &= ~status; 1501 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1502 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1503 } 1504 /* poll all the USB transfers */ 1505 ehci_interrupt_poll(sc); 1506 1507 done: 1508 USB_BUS_UNLOCK(&sc->sc_bus); 1509 } 1510 1511 /* 1512 * called when a request does not complete 1513 */ 1514 static void 1515 ehci_timeout(void *arg) 1516 { 1517 struct usb2_xfer *xfer = arg; 1518 1519 DPRINTF("xfer=%p\n", xfer); 1520 1521 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1522 1523 /* transfer is transferred */ 1524 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1525 } 1526 1527 static void 1528 ehci_do_poll(struct usb2_bus *bus) 1529 { 1530 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1531 1532 USB_BUS_LOCK(&sc->sc_bus); 1533 ehci_interrupt_poll(sc); 1534 ehci_root_ctrl_poll(sc); 1535 USB_BUS_UNLOCK(&sc->sc_bus); 1536 } 1537 1538 static void 1539 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1540 { 1541 struct usb2_page_search buf_res; 1542 ehci_qtd_t *td; 1543 ehci_qtd_t *td_next; 1544 ehci_qtd_t *td_alt_next; 1545 uint32_t qtd_altnext; 1546 uint32_t buf_offset; 1547 uint32_t average; 1548 uint32_t len_old; 1549 uint8_t shortpkt_old; 1550 uint8_t precompute; 1551 1552 qtd_altnext = htohc32(temp->sc, EHCI_LINK_TERMINATE); 1553 td_alt_next = NULL; 1554 buf_offset = 0; 1555 shortpkt_old = temp->shortpkt; 1556 len_old = temp->len; 1557 precompute = 1; 1558 1559 restart: 1560 1561 td = temp->td; 1562 td_next = temp->td_next; 1563 1564 while (1) { 1565 1566 if (temp->len == 0) { 1567 1568 if (temp->shortpkt) { 1569 break; 1570 } 1571 /* send a Zero Length Packet, ZLP, last */ 1572 1573 temp->shortpkt = 1; 1574 average = 0; 1575 1576 } else { 1577 1578 average = temp->average; 1579 1580 if (temp->len < average) { 1581 if (temp->len % temp->max_frame_size) { 1582 temp->shortpkt = 1; 1583 } 1584 average = temp->len; 1585 } 1586 } 1587 1588 if (td_next == NULL) { 1589 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1590 } 1591 /* get next TD */ 1592 1593 td = td_next; 1594 td_next = td->obj_next; 1595 1596 /* check if we are pre-computing */ 1597 1598 if (precompute) { 1599 1600 /* update remaining length */ 1601 1602 temp->len -= average; 1603 1604 continue; 1605 } 1606 /* fill out current TD */ 1607 1608 td->qtd_status = 1609 temp->qtd_status | 1610 htohc32(temp->sc, EHCI_QTD_SET_BYTES(average)); 1611 1612 if (average == 0) { 1613 1614 if (temp->auto_data_toggle == 0) { 1615 1616 /* update data toggle, ZLP case */ 1617 1618 temp->qtd_status ^= 1619 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1620 } 1621 td->len = 0; 1622 1623 td->qtd_buffer[0] = 0; 1624 td->qtd_buffer_hi[0] = 0; 1625 1626 td->qtd_buffer[1] = 0; 1627 td->qtd_buffer_hi[1] = 0; 1628 1629 } else { 1630 1631 uint8_t x; 1632 1633 if (temp->auto_data_toggle == 0) { 1634 1635 /* update data toggle */ 1636 1637 if (((average + temp->max_frame_size - 1) / 1638 temp->max_frame_size) & 1) { 1639 temp->qtd_status ^= 1640 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1641 } 1642 } 1643 td->len = average; 1644 1645 /* update remaining length */ 1646 1647 temp->len -= average; 1648 1649 /* fill out buffer pointers */ 1650 1651 usb2_get_page(temp->pc, buf_offset, &buf_res); 1652 td->qtd_buffer[0] = 1653 htohc32(temp->sc, buf_res.physaddr); 1654 td->qtd_buffer_hi[0] = 0; 1655 1656 x = 1; 1657 1658 while (average > EHCI_PAGE_SIZE) { 1659 average -= EHCI_PAGE_SIZE; 1660 buf_offset += EHCI_PAGE_SIZE; 1661 usb2_get_page(temp->pc, buf_offset, &buf_res); 1662 td->qtd_buffer[x] = 1663 htohc32(temp->sc, 1664 buf_res.physaddr & (~0xFFF)); 1665 td->qtd_buffer_hi[x] = 0; 1666 x++; 1667 } 1668 1669 /* 1670 * NOTE: The "average" variable is never zero after 1671 * exiting the loop above ! 1672 * 1673 * NOTE: We have to subtract one from the offset to 1674 * ensure that we are computing the physical address 1675 * of a valid page ! 1676 */ 1677 buf_offset += average; 1678 usb2_get_page(temp->pc, buf_offset - 1, &buf_res); 1679 td->qtd_buffer[x] = 1680 htohc32(temp->sc, 1681 buf_res.physaddr & (~0xFFF)); 1682 td->qtd_buffer_hi[x] = 0; 1683 } 1684 1685 if (td_next) { 1686 /* link the current TD with the next one */ 1687 td->qtd_next = td_next->qtd_self; 1688 } 1689 td->qtd_altnext = qtd_altnext; 1690 td->alt_next = td_alt_next; 1691 1692 usb2_pc_cpu_flush(td->page_cache); 1693 } 1694 1695 if (precompute) { 1696 precompute = 0; 1697 1698 /* setup alt next pointer, if any */ 1699 if (temp->short_frames_ok) { 1700 if (temp->setup_alt_next) { 1701 td_alt_next = td_next; 1702 qtd_altnext = td_next->qtd_self; 1703 } 1704 } else { 1705 /* we use this field internally */ 1706 td_alt_next = td_next; 1707 } 1708 1709 /* restore */ 1710 temp->shortpkt = shortpkt_old; 1711 temp->len = len_old; 1712 goto restart; 1713 } 1714 temp->td = td; 1715 temp->td_next = td_next; 1716 } 1717 1718 static void 1719 ehci_setup_standard_chain(struct usb2_xfer *xfer, ehci_qh_t **qh_last) 1720 { 1721 struct ehci_std_temp temp; 1722 struct usb2_pipe_methods *methods; 1723 ehci_qh_t *qh; 1724 ehci_qtd_t *td; 1725 uint32_t qh_endp; 1726 uint32_t qh_endphub; 1727 uint32_t x; 1728 1729 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1730 xfer->address, UE_GET_ADDR(xfer->endpoint), 1731 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1732 1733 temp.average = xfer->max_usb2_frame_size; 1734 temp.max_frame_size = xfer->max_frame_size; 1735 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1736 1737 /* toggle the DMA set we are using */ 1738 xfer->flags_int.curr_dma_set ^= 1; 1739 1740 /* get next DMA set */ 1741 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1742 1743 xfer->td_transfer_first = td; 1744 xfer->td_transfer_cache = td; 1745 1746 temp.td = NULL; 1747 temp.td_next = td; 1748 temp.qtd_status = 0; 1749 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1750 temp.short_frames_ok = xfer->flags_int.short_frames_ok; 1751 1752 if (xfer->flags_int.control_xfr) { 1753 if (xfer->pipe->toggle_next) { 1754 /* DATA1 is next */ 1755 temp.qtd_status |= 1756 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1757 } 1758 temp.auto_data_toggle = 0; 1759 } else { 1760 temp.auto_data_toggle = 1; 1761 } 1762 1763 if (usb2_get_speed(xfer->xroot->udev) != USB_SPEED_HIGH) { 1764 /* max 3 retries */ 1765 temp.qtd_status |= 1766 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1767 } 1768 /* check if we should prepend a setup message */ 1769 1770 if (xfer->flags_int.control_xfr) { 1771 if (xfer->flags_int.control_hdr) { 1772 1773 temp.qtd_status &= 1774 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1775 temp.qtd_status |= htohc32(temp.sc, 1776 EHCI_QTD_ACTIVE | 1777 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1778 EHCI_QTD_SET_TOGGLE(0)); 1779 1780 temp.len = xfer->frlengths[0]; 1781 temp.pc = xfer->frbuffers + 0; 1782 temp.shortpkt = temp.len ? 1 : 0; 1783 1784 ehci_setup_standard_chain_sub(&temp); 1785 } 1786 x = 1; 1787 } else { 1788 x = 0; 1789 } 1790 1791 while (x != xfer->nframes) { 1792 1793 /* DATA0 / DATA1 message */ 1794 1795 temp.len = xfer->frlengths[x]; 1796 temp.pc = xfer->frbuffers + x; 1797 1798 x++; 1799 1800 if (x == xfer->nframes) { 1801 temp.setup_alt_next = 0; 1802 } 1803 /* keep previous data toggle and error count */ 1804 1805 temp.qtd_status &= 1806 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1807 EHCI_QTD_SET_TOGGLE(1)); 1808 1809 if (temp.len == 0) { 1810 1811 /* make sure that we send an USB packet */ 1812 1813 temp.shortpkt = 0; 1814 1815 } else { 1816 1817 /* regular data transfer */ 1818 1819 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1820 } 1821 1822 /* set endpoint direction */ 1823 1824 temp.qtd_status |= 1825 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 1826 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1827 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1828 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1829 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1830 1831 ehci_setup_standard_chain_sub(&temp); 1832 } 1833 1834 /* check if we should append a status stage */ 1835 1836 if (xfer->flags_int.control_xfr && 1837 !xfer->flags_int.control_act) { 1838 1839 /* 1840 * Send a DATA1 message and invert the current endpoint 1841 * direction. 1842 */ 1843 1844 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1845 EHCI_QTD_SET_TOGGLE(1)); 1846 temp.qtd_status |= 1847 (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) ? 1848 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1849 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1850 EHCI_QTD_SET_TOGGLE(1)) : 1851 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1852 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1853 EHCI_QTD_SET_TOGGLE(1)); 1854 1855 temp.len = 0; 1856 temp.pc = NULL; 1857 temp.shortpkt = 0; 1858 1859 ehci_setup_standard_chain_sub(&temp); 1860 } 1861 td = temp.td; 1862 1863 /* the last TD terminates the transfer: */ 1864 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1865 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1866 td->qtd_status |= htohc32(temp.sc, EHCI_QTD_IOC); 1867 1868 usb2_pc_cpu_flush(td->page_cache); 1869 1870 /* must have at least one frame! */ 1871 1872 xfer->td_transfer_last = td; 1873 1874 #if USB_DEBUG 1875 if (ehcidebug > 8) { 1876 DPRINTF("nexttog=%d; data before transfer:\n", 1877 xfer->pipe->toggle_next); 1878 ehci_dump_sqtds(temp.sc, 1879 xfer->td_transfer_first); 1880 } 1881 #endif 1882 1883 methods = xfer->pipe->methods; 1884 1885 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1886 1887 /* the "qh_link" field is filled when the QH is added */ 1888 1889 qh_endp = 1890 (EHCI_QH_SET_ADDR(xfer->address) | 1891 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpoint)) | 1892 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1893 1894 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1895 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | 1896 EHCI_QH_DTC); 1897 if (methods != &ehci_device_intr_methods) 1898 qh_endp |= EHCI_QH_SET_NRL(8); 1899 } else { 1900 1901 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1902 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL) | 1903 EHCI_QH_DTC); 1904 } else { 1905 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW) | 1906 EHCI_QH_DTC); 1907 } 1908 1909 if (methods == &ehci_device_ctrl_methods) { 1910 qh_endp |= EHCI_QH_CTL; 1911 } 1912 if (methods != &ehci_device_intr_methods) { 1913 /* Only try one time per microframe! */ 1914 qh_endp |= EHCI_QH_SET_NRL(1); 1915 } 1916 } 1917 1918 qh->qh_endp = htohc32(temp.sc, qh_endp); 1919 1920 qh_endphub = 1921 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1922 EHCI_QH_SET_CMASK(xfer->usb2_cmask) | 1923 EHCI_QH_SET_SMASK(xfer->usb2_smask) | 1924 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1925 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1926 1927 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 1928 qh->qh_curqtd = htohc32(temp.sc, 0); 1929 1930 /* fill the overlay qTD */ 1931 qh->qh_qtd.qtd_status = htohc32(temp.sc, 0); 1932 1933 if (temp.auto_data_toggle) { 1934 1935 /* let the hardware compute the data toggle */ 1936 1937 qh->qh_endp &= htohc32(temp.sc, ~EHCI_QH_DTC); 1938 1939 if (xfer->pipe->toggle_next) { 1940 /* DATA1 is next */ 1941 qh->qh_qtd.qtd_status |= 1942 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1943 } 1944 } 1945 td = xfer->td_transfer_first; 1946 1947 qh->qh_qtd.qtd_next = td->qtd_self; 1948 qh->qh_qtd.qtd_altnext = 1949 htohc32(temp.sc, EHCI_LINK_TERMINATE); 1950 1951 usb2_pc_cpu_flush(qh->page_cache); 1952 1953 if (xfer->xroot->udev->pwr_save.suspended == 0) { 1954 EHCI_APPEND_QH(qh, *qh_last); 1955 } 1956 } 1957 1958 static void 1959 ehci_root_intr_done(struct usb2_xfer *xfer, 1960 struct usb2_sw_transfer *std) 1961 { 1962 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1963 uint16_t i; 1964 uint16_t m; 1965 1966 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1967 1968 if (std->state != USB_SW_TR_PRE_DATA) { 1969 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1970 /* transfer transferred */ 1971 ehci_device_done(xfer, std->err); 1972 } 1973 goto done; 1974 } 1975 /* setup buffer */ 1976 std->ptr = sc->sc_hub_idata; 1977 std->len = sizeof(sc->sc_hub_idata); 1978 1979 /* clear any old interrupt data */ 1980 bzero(sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); 1981 1982 /* set bits */ 1983 m = (sc->sc_noport + 1); 1984 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1985 m = (8 * sizeof(sc->sc_hub_idata)); 1986 } 1987 for (i = 1; i < m; i++) { 1988 /* pick out CHANGE bits from the status register */ 1989 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 1990 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1991 DPRINTF("port %d changed\n", i); 1992 } 1993 } 1994 done: 1995 return; 1996 } 1997 1998 static void 1999 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb2_xfer *xfer) 2000 { 2001 uint32_t nframes = xfer->nframes; 2002 uint32_t status; 2003 uint32_t *plen = xfer->frlengths; 2004 uint16_t len = 0; 2005 ehci_sitd_t *td = xfer->td_transfer_first; 2006 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2007 2008 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 2009 xfer, xfer->pipe); 2010 2011 while (nframes--) { 2012 if (td == NULL) { 2013 panic("%s:%d: out of TD's\n", 2014 __FUNCTION__, __LINE__); 2015 } 2016 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2017 pp_last = &sc->sc_isoc_fs_p_last[0]; 2018 } 2019 #if USB_DEBUG 2020 if (ehcidebug > 15) { 2021 DPRINTF("isoc FS-TD\n"); 2022 ehci_dump_sitd(sc, td); 2023 } 2024 #endif 2025 usb2_pc_cpu_invalidate(td->page_cache); 2026 status = hc32toh(sc, td->sitd_status); 2027 2028 len = EHCI_SITD_GET_LEN(status); 2029 2030 if (*plen >= len) { 2031 len = *plen - len; 2032 } else { 2033 len = 0; 2034 } 2035 2036 *plen = len; 2037 2038 /* remove FS-TD from schedule */ 2039 EHCI_REMOVE_FS_TD(td, *pp_last); 2040 2041 pp_last++; 2042 plen++; 2043 td = td->obj_next; 2044 } 2045 2046 xfer->aframes = xfer->nframes; 2047 } 2048 2049 static void 2050 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb2_xfer *xfer) 2051 { 2052 uint32_t nframes = xfer->nframes; 2053 uint32_t status; 2054 uint32_t *plen = xfer->frlengths; 2055 uint16_t len = 0; 2056 uint8_t td_no = 0; 2057 ehci_itd_t *td = xfer->td_transfer_first; 2058 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2059 2060 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 2061 xfer, xfer->pipe); 2062 2063 while (nframes--) { 2064 if (td == NULL) { 2065 panic("%s:%d: out of TD's\n", 2066 __FUNCTION__, __LINE__); 2067 } 2068 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2069 pp_last = &sc->sc_isoc_hs_p_last[0]; 2070 } 2071 #if USB_DEBUG 2072 if (ehcidebug > 15) { 2073 DPRINTF("isoc HS-TD\n"); 2074 ehci_dump_itd(sc, td); 2075 } 2076 #endif 2077 2078 usb2_pc_cpu_invalidate(td->page_cache); 2079 status = hc32toh(sc, td->itd_status[td_no]); 2080 2081 len = EHCI_ITD_GET_LEN(status); 2082 2083 if (*plen >= len) { 2084 /* 2085 * The length is valid. NOTE: The complete 2086 * length is written back into the status 2087 * field, and not the remainder like with 2088 * other transfer descriptor types. 2089 */ 2090 } else { 2091 /* Invalid length - truncate */ 2092 len = 0; 2093 } 2094 2095 *plen = len; 2096 2097 plen++; 2098 td_no++; 2099 2100 if ((td_no == 8) || (nframes == 0)) { 2101 /* remove HS-TD from schedule */ 2102 EHCI_REMOVE_HS_TD(td, *pp_last); 2103 pp_last++; 2104 2105 td_no = 0; 2106 td = td->obj_next; 2107 } 2108 } 2109 xfer->aframes = xfer->nframes; 2110 } 2111 2112 /* NOTE: "done" can be run two times in a row, 2113 * from close and from interrupt 2114 */ 2115 static void 2116 ehci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 2117 { 2118 struct usb2_pipe_methods *methods = xfer->pipe->methods; 2119 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2120 2121 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2122 2123 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 2124 xfer, xfer->pipe, error); 2125 2126 if ((methods == &ehci_device_bulk_methods) || 2127 (methods == &ehci_device_ctrl_methods)) { 2128 #if USB_DEBUG 2129 if (ehcidebug > 8) { 2130 DPRINTF("nexttog=%d; data after transfer:\n", 2131 xfer->pipe->toggle_next); 2132 ehci_dump_sqtds(sc, 2133 xfer->td_transfer_first); 2134 } 2135 #endif 2136 2137 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2138 sc->sc_async_p_last); 2139 } 2140 if (methods == &ehci_device_intr_methods) { 2141 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2142 sc->sc_intr_p_last[xfer->qh_pos]); 2143 } 2144 /* 2145 * Only finish isochronous transfers once which will update 2146 * "xfer->frlengths". 2147 */ 2148 if (xfer->td_transfer_first && 2149 xfer->td_transfer_last) { 2150 if (methods == &ehci_device_isoc_fs_methods) { 2151 ehci_isoc_fs_done(sc, xfer); 2152 } 2153 if (methods == &ehci_device_isoc_hs_methods) { 2154 ehci_isoc_hs_done(sc, xfer); 2155 } 2156 xfer->td_transfer_first = NULL; 2157 xfer->td_transfer_last = NULL; 2158 } 2159 /* dequeue transfer and start next transfer */ 2160 usb2_transfer_done(xfer, error); 2161 } 2162 2163 /*------------------------------------------------------------------------* 2164 * ehci bulk support 2165 *------------------------------------------------------------------------*/ 2166 static void 2167 ehci_device_bulk_open(struct usb2_xfer *xfer) 2168 { 2169 return; 2170 } 2171 2172 static void 2173 ehci_device_bulk_close(struct usb2_xfer *xfer) 2174 { 2175 ehci_device_done(xfer, USB_ERR_CANCELLED); 2176 } 2177 2178 static void 2179 ehci_device_bulk_enter(struct usb2_xfer *xfer) 2180 { 2181 return; 2182 } 2183 2184 static void 2185 ehci_device_bulk_start(struct usb2_xfer *xfer) 2186 { 2187 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2188 uint32_t temp; 2189 2190 /* setup TD's and QH */ 2191 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2192 2193 /* put transfer on interrupt queue */ 2194 ehci_transfer_intr_enqueue(xfer); 2195 2196 /* XXX Performance quirk: Some Host Controllers have a too low 2197 * interrupt rate. Issue an IAAD to stimulate the Host 2198 * Controller after queueing the BULK transfer. 2199 */ 2200 temp = EOREAD4(sc, EHCI_USBCMD); 2201 if (!(temp & EHCI_CMD_IAAD)) 2202 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2203 } 2204 2205 struct usb2_pipe_methods ehci_device_bulk_methods = 2206 { 2207 .open = ehci_device_bulk_open, 2208 .close = ehci_device_bulk_close, 2209 .enter = ehci_device_bulk_enter, 2210 .start = ehci_device_bulk_start, 2211 .enter_is_cancelable = 1, 2212 .start_is_cancelable = 1, 2213 }; 2214 2215 /*------------------------------------------------------------------------* 2216 * ehci control support 2217 *------------------------------------------------------------------------*/ 2218 static void 2219 ehci_device_ctrl_open(struct usb2_xfer *xfer) 2220 { 2221 return; 2222 } 2223 2224 static void 2225 ehci_device_ctrl_close(struct usb2_xfer *xfer) 2226 { 2227 ehci_device_done(xfer, USB_ERR_CANCELLED); 2228 } 2229 2230 static void 2231 ehci_device_ctrl_enter(struct usb2_xfer *xfer) 2232 { 2233 return; 2234 } 2235 2236 static void 2237 ehci_device_ctrl_start(struct usb2_xfer *xfer) 2238 { 2239 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2240 2241 /* setup TD's and QH */ 2242 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2243 2244 /* put transfer on interrupt queue */ 2245 ehci_transfer_intr_enqueue(xfer); 2246 } 2247 2248 struct usb2_pipe_methods ehci_device_ctrl_methods = 2249 { 2250 .open = ehci_device_ctrl_open, 2251 .close = ehci_device_ctrl_close, 2252 .enter = ehci_device_ctrl_enter, 2253 .start = ehci_device_ctrl_start, 2254 .enter_is_cancelable = 1, 2255 .start_is_cancelable = 1, 2256 }; 2257 2258 /*------------------------------------------------------------------------* 2259 * ehci interrupt support 2260 *------------------------------------------------------------------------*/ 2261 static void 2262 ehci_device_intr_open(struct usb2_xfer *xfer) 2263 { 2264 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2265 uint16_t best; 2266 uint16_t bit; 2267 uint16_t x; 2268 uint8_t slot; 2269 2270 /* Allocate a microframe slot first: */ 2271 2272 slot = usb2_intr_schedule_adjust 2273 (xfer->xroot->udev, xfer->max_frame_size, USB_HS_MICRO_FRAMES_MAX); 2274 2275 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2276 xfer->usb2_uframe = slot; 2277 xfer->usb2_smask = (1 << slot) & 0xFF; 2278 xfer->usb2_cmask = 0; 2279 } else { 2280 xfer->usb2_uframe = slot; 2281 xfer->usb2_smask = (1 << slot) & 0x3F; 2282 xfer->usb2_cmask = (-(4 << slot)) & 0xFE; 2283 } 2284 2285 /* 2286 * Find the best QH position corresponding to the given interval: 2287 */ 2288 2289 best = 0; 2290 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2291 while (bit) { 2292 if (xfer->interval >= bit) { 2293 x = bit; 2294 best = bit; 2295 while (x & bit) { 2296 if (sc->sc_intr_stat[x] < 2297 sc->sc_intr_stat[best]) { 2298 best = x; 2299 } 2300 x++; 2301 } 2302 break; 2303 } 2304 bit >>= 1; 2305 } 2306 2307 sc->sc_intr_stat[best]++; 2308 xfer->qh_pos = best; 2309 2310 DPRINTFN(3, "best=%d interval=%d\n", 2311 best, xfer->interval); 2312 } 2313 2314 static void 2315 ehci_device_intr_close(struct usb2_xfer *xfer) 2316 { 2317 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2318 uint8_t slot; 2319 2320 slot = usb2_intr_schedule_adjust 2321 (xfer->xroot->udev, -(xfer->max_frame_size), xfer->usb2_uframe); 2322 2323 sc->sc_intr_stat[xfer->qh_pos]--; 2324 2325 ehci_device_done(xfer, USB_ERR_CANCELLED); 2326 } 2327 2328 static void 2329 ehci_device_intr_enter(struct usb2_xfer *xfer) 2330 { 2331 return; 2332 } 2333 2334 static void 2335 ehci_device_intr_start(struct usb2_xfer *xfer) 2336 { 2337 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2338 2339 /* setup TD's and QH */ 2340 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2341 2342 /* put transfer on interrupt queue */ 2343 ehci_transfer_intr_enqueue(xfer); 2344 } 2345 2346 struct usb2_pipe_methods ehci_device_intr_methods = 2347 { 2348 .open = ehci_device_intr_open, 2349 .close = ehci_device_intr_close, 2350 .enter = ehci_device_intr_enter, 2351 .start = ehci_device_intr_start, 2352 .enter_is_cancelable = 1, 2353 .start_is_cancelable = 1, 2354 }; 2355 2356 /*------------------------------------------------------------------------* 2357 * ehci full speed isochronous support 2358 *------------------------------------------------------------------------*/ 2359 static void 2360 ehci_device_isoc_fs_open(struct usb2_xfer *xfer) 2361 { 2362 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2363 ehci_sitd_t *td; 2364 uint32_t sitd_portaddr; 2365 uint8_t ds; 2366 2367 sitd_portaddr = 2368 EHCI_SITD_SET_ADDR(xfer->address) | 2369 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpoint)) | 2370 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2371 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2372 2373 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 2374 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2375 } 2376 sitd_portaddr = htohc32(sc, sitd_portaddr); 2377 2378 /* initialize all TD's */ 2379 2380 for (ds = 0; ds != 2; ds++) { 2381 2382 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2383 2384 td->sitd_portaddr = sitd_portaddr; 2385 2386 /* 2387 * TODO: make some kind of automatic 2388 * SMASK/CMASK selection based on micro-frame 2389 * usage 2390 * 2391 * micro-frame usage (8 microframes per 1ms) 2392 */ 2393 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2394 2395 usb2_pc_cpu_flush(td->page_cache); 2396 } 2397 } 2398 } 2399 2400 static void 2401 ehci_device_isoc_fs_close(struct usb2_xfer *xfer) 2402 { 2403 ehci_device_done(xfer, USB_ERR_CANCELLED); 2404 } 2405 2406 static void 2407 ehci_device_isoc_fs_enter(struct usb2_xfer *xfer) 2408 { 2409 struct usb2_page_search buf_res; 2410 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2411 struct usb2_fs_isoc_schedule *fss_start; 2412 struct usb2_fs_isoc_schedule *fss_end; 2413 struct usb2_fs_isoc_schedule *fss; 2414 ehci_sitd_t *td; 2415 ehci_sitd_t *td_last = NULL; 2416 ehci_sitd_t **pp_last; 2417 uint32_t *plen; 2418 uint32_t buf_offset; 2419 uint32_t nframes; 2420 uint32_t temp; 2421 uint32_t sitd_mask; 2422 uint16_t tlen; 2423 uint8_t sa; 2424 uint8_t sb; 2425 uint8_t error; 2426 2427 #if USB_DEBUG 2428 uint8_t once = 1; 2429 2430 #endif 2431 2432 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2433 xfer, xfer->pipe->isoc_next, xfer->nframes); 2434 2435 /* get the current frame index */ 2436 2437 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2438 2439 /* 2440 * check if the frame index is within the window where the frames 2441 * will be inserted 2442 */ 2443 buf_offset = (nframes - xfer->pipe->isoc_next) & 2444 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2445 2446 if ((xfer->pipe->is_synced == 0) || 2447 (buf_offset < xfer->nframes)) { 2448 /* 2449 * If there is data underflow or the pipe queue is empty we 2450 * schedule the transfer a few frames ahead of the current 2451 * frame position. Else two isochronous transfers might 2452 * overlap. 2453 */ 2454 xfer->pipe->isoc_next = (nframes + 3) & 2455 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2456 xfer->pipe->is_synced = 1; 2457 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2458 } 2459 /* 2460 * compute how many milliseconds the insertion is ahead of the 2461 * current frame position: 2462 */ 2463 buf_offset = (xfer->pipe->isoc_next - nframes) & 2464 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2465 2466 /* 2467 * pre-compute when the isochronous transfer will be finished: 2468 */ 2469 xfer->isoc_time_complete = 2470 usb2_fs_isoc_schedule_isoc_time_expand 2471 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset + 2472 xfer->nframes; 2473 2474 /* get the real number of frames */ 2475 2476 nframes = xfer->nframes; 2477 2478 buf_offset = 0; 2479 2480 plen = xfer->frlengths; 2481 2482 /* toggle the DMA set we are using */ 2483 xfer->flags_int.curr_dma_set ^= 1; 2484 2485 /* get next DMA set */ 2486 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2487 xfer->td_transfer_first = td; 2488 2489 pp_last = &sc->sc_isoc_fs_p_last[xfer->pipe->isoc_next]; 2490 2491 /* store starting position */ 2492 2493 xfer->qh_pos = xfer->pipe->isoc_next; 2494 2495 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX); 2496 2497 while (nframes--) { 2498 if (td == NULL) { 2499 panic("%s:%d: out of TD's\n", 2500 __FUNCTION__, __LINE__); 2501 } 2502 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2503 pp_last = &sc->sc_isoc_fs_p_last[0]; 2504 } 2505 if (fss >= fss_end) { 2506 fss = fss_start; 2507 } 2508 /* reuse sitd_portaddr and sitd_back from last transfer */ 2509 2510 if (*plen > xfer->max_frame_size) { 2511 #if USB_DEBUG 2512 if (once) { 2513 once = 0; 2514 printf("%s: frame length(%d) exceeds %d " 2515 "bytes (frame truncated)\n", 2516 __FUNCTION__, *plen, 2517 xfer->max_frame_size); 2518 } 2519 #endif 2520 *plen = xfer->max_frame_size; 2521 } 2522 /* 2523 * We currently don't care if the ISOCHRONOUS schedule is 2524 * full! 2525 */ 2526 error = usb2_fs_isoc_schedule_alloc(fss, &sa, *plen); 2527 if (error) { 2528 /* 2529 * The FULL speed schedule is FULL! Set length 2530 * to zero. 2531 */ 2532 *plen = 0; 2533 } 2534 if (*plen) { 2535 /* 2536 * only call "usb2_get_page()" when we have a 2537 * non-zero length 2538 */ 2539 usb2_get_page(xfer->frbuffers, buf_offset, &buf_res); 2540 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2541 buf_offset += *plen; 2542 /* 2543 * NOTE: We need to subtract one from the offset so 2544 * that we are on a valid page! 2545 */ 2546 usb2_get_page(xfer->frbuffers, buf_offset - 1, 2547 &buf_res); 2548 temp = buf_res.physaddr & ~0xFFF; 2549 } else { 2550 td->sitd_bp[0] = 0; 2551 temp = 0; 2552 } 2553 2554 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) { 2555 tlen = *plen; 2556 if (tlen <= 188) { 2557 temp |= 1; /* T-count = 1, TP = ALL */ 2558 tlen = 1; 2559 } else { 2560 tlen += 187; 2561 tlen /= 188; 2562 temp |= tlen; /* T-count = [1..6] */ 2563 temp |= 8; /* TP = Begin */ 2564 } 2565 2566 tlen += sa; 2567 2568 if (tlen >= 8) { 2569 sb = 0; 2570 } else { 2571 sb = (1 << tlen); 2572 } 2573 2574 sa = (1 << sa); 2575 sa = (sb - sa) & 0x3F; 2576 sb = 0; 2577 } else { 2578 sb = (-(4 << sa)) & 0xFE; 2579 sa = (1 << sa) & 0x3F; 2580 } 2581 2582 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2583 EHCI_SITD_SET_CMASK(sb)); 2584 2585 td->sitd_bp[1] = htohc32(sc, temp); 2586 2587 td->sitd_mask = htohc32(sc, sitd_mask); 2588 2589 if (nframes == 0) { 2590 td->sitd_status = htohc32(sc, 2591 EHCI_SITD_IOC | 2592 EHCI_SITD_ACTIVE | 2593 EHCI_SITD_SET_LEN(*plen)); 2594 } else { 2595 td->sitd_status = htohc32(sc, 2596 EHCI_SITD_ACTIVE | 2597 EHCI_SITD_SET_LEN(*plen)); 2598 } 2599 usb2_pc_cpu_flush(td->page_cache); 2600 2601 #if USB_DEBUG 2602 if (ehcidebug > 15) { 2603 DPRINTF("FS-TD %d\n", nframes); 2604 ehci_dump_sitd(sc, td); 2605 } 2606 #endif 2607 /* insert TD into schedule */ 2608 EHCI_APPEND_FS_TD(td, *pp_last); 2609 pp_last++; 2610 2611 plen++; 2612 fss++; 2613 td_last = td; 2614 td = td->obj_next; 2615 } 2616 2617 xfer->td_transfer_last = td_last; 2618 2619 /* update isoc_next */ 2620 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2621 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2622 } 2623 2624 static void 2625 ehci_device_isoc_fs_start(struct usb2_xfer *xfer) 2626 { 2627 /* put transfer on interrupt queue */ 2628 ehci_transfer_intr_enqueue(xfer); 2629 } 2630 2631 struct usb2_pipe_methods ehci_device_isoc_fs_methods = 2632 { 2633 .open = ehci_device_isoc_fs_open, 2634 .close = ehci_device_isoc_fs_close, 2635 .enter = ehci_device_isoc_fs_enter, 2636 .start = ehci_device_isoc_fs_start, 2637 .enter_is_cancelable = 1, 2638 .start_is_cancelable = 1, 2639 }; 2640 2641 /*------------------------------------------------------------------------* 2642 * ehci high speed isochronous support 2643 *------------------------------------------------------------------------*/ 2644 static void 2645 ehci_device_isoc_hs_open(struct usb2_xfer *xfer) 2646 { 2647 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2648 ehci_itd_t *td; 2649 uint32_t temp; 2650 uint8_t ds; 2651 2652 /* initialize all TD's */ 2653 2654 for (ds = 0; ds != 2; ds++) { 2655 2656 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2657 2658 /* set TD inactive */ 2659 td->itd_status[0] = 0; 2660 td->itd_status[1] = 0; 2661 td->itd_status[2] = 0; 2662 td->itd_status[3] = 0; 2663 td->itd_status[4] = 0; 2664 td->itd_status[5] = 0; 2665 td->itd_status[6] = 0; 2666 td->itd_status[7] = 0; 2667 2668 /* set endpoint and address */ 2669 td->itd_bp[0] = htohc32(sc, 2670 EHCI_ITD_SET_ADDR(xfer->address) | 2671 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpoint))); 2672 2673 temp = 2674 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2675 2676 /* set direction */ 2677 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 2678 temp |= EHCI_ITD_SET_DIR_IN; 2679 } 2680 /* set maximum packet size */ 2681 td->itd_bp[1] = htohc32(sc, temp); 2682 2683 /* set transfer multiplier */ 2684 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2685 2686 usb2_pc_cpu_flush(td->page_cache); 2687 } 2688 } 2689 } 2690 2691 static void 2692 ehci_device_isoc_hs_close(struct usb2_xfer *xfer) 2693 { 2694 ehci_device_done(xfer, USB_ERR_CANCELLED); 2695 } 2696 2697 static void 2698 ehci_device_isoc_hs_enter(struct usb2_xfer *xfer) 2699 { 2700 struct usb2_page_search buf_res; 2701 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2702 ehci_itd_t *td; 2703 ehci_itd_t *td_last = NULL; 2704 ehci_itd_t **pp_last; 2705 bus_size_t page_addr; 2706 uint32_t *plen; 2707 uint32_t status; 2708 uint32_t buf_offset; 2709 uint32_t nframes; 2710 uint32_t itd_offset[8 + 1]; 2711 uint8_t x; 2712 uint8_t td_no; 2713 uint8_t page_no; 2714 2715 #if USB_DEBUG 2716 uint8_t once = 1; 2717 2718 #endif 2719 2720 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2721 xfer, xfer->pipe->isoc_next, xfer->nframes); 2722 2723 /* get the current frame index */ 2724 2725 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2726 2727 /* 2728 * check if the frame index is within the window where the frames 2729 * will be inserted 2730 */ 2731 buf_offset = (nframes - xfer->pipe->isoc_next) & 2732 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2733 2734 if ((xfer->pipe->is_synced == 0) || 2735 (buf_offset < ((xfer->nframes + 7) / 8))) { 2736 /* 2737 * If there is data underflow or the pipe queue is empty we 2738 * schedule the transfer a few frames ahead of the current 2739 * frame position. Else two isochronous transfers might 2740 * overlap. 2741 */ 2742 xfer->pipe->isoc_next = (nframes + 3) & 2743 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2744 xfer->pipe->is_synced = 1; 2745 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2746 } 2747 /* 2748 * compute how many milliseconds the insertion is ahead of the 2749 * current frame position: 2750 */ 2751 buf_offset = (xfer->pipe->isoc_next - nframes) & 2752 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2753 2754 /* 2755 * pre-compute when the isochronous transfer will be finished: 2756 */ 2757 xfer->isoc_time_complete = 2758 usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2759 ((xfer->nframes + 7) / 8); 2760 2761 /* get the real number of frames */ 2762 2763 nframes = xfer->nframes; 2764 2765 buf_offset = 0; 2766 td_no = 0; 2767 2768 plen = xfer->frlengths; 2769 2770 /* toggle the DMA set we are using */ 2771 xfer->flags_int.curr_dma_set ^= 1; 2772 2773 /* get next DMA set */ 2774 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2775 xfer->td_transfer_first = td; 2776 2777 pp_last = &sc->sc_isoc_hs_p_last[xfer->pipe->isoc_next]; 2778 2779 /* store starting position */ 2780 2781 xfer->qh_pos = xfer->pipe->isoc_next; 2782 2783 while (nframes--) { 2784 if (td == NULL) { 2785 panic("%s:%d: out of TD's\n", 2786 __FUNCTION__, __LINE__); 2787 } 2788 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2789 pp_last = &sc->sc_isoc_hs_p_last[0]; 2790 } 2791 /* range check */ 2792 if (*plen > xfer->max_frame_size) { 2793 #if USB_DEBUG 2794 if (once) { 2795 once = 0; 2796 printf("%s: frame length(%d) exceeds %d bytes " 2797 "(frame truncated)\n", 2798 __FUNCTION__, *plen, xfer->max_frame_size); 2799 } 2800 #endif 2801 *plen = xfer->max_frame_size; 2802 } 2803 status = (EHCI_ITD_SET_LEN(*plen) | 2804 EHCI_ITD_ACTIVE | 2805 EHCI_ITD_SET_PG(0)); 2806 td->itd_status[td_no] = htohc32(sc, status); 2807 itd_offset[td_no] = buf_offset; 2808 buf_offset += *plen; 2809 plen++; 2810 td_no++; 2811 2812 if ((td_no == 8) || (nframes == 0)) { 2813 2814 /* the rest of the transfers are not active, if any */ 2815 for (x = td_no; x != 8; x++) { 2816 td->itd_status[x] = 0; /* not active */ 2817 } 2818 2819 /* check if there is any data to be transferred */ 2820 if (itd_offset[0] != buf_offset) { 2821 page_no = 0; 2822 itd_offset[td_no] = buf_offset; 2823 2824 /* get first page offset */ 2825 usb2_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2826 /* get page address */ 2827 page_addr = buf_res.physaddr & ~0xFFF; 2828 /* update page address */ 2829 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2830 td->itd_bp[0] |= htohc32(sc, page_addr); 2831 2832 for (x = 0; x != td_no; x++) { 2833 /* set page number and page offset */ 2834 status = (EHCI_ITD_SET_PG(page_no) | 2835 (buf_res.physaddr & 0xFFF)); 2836 td->itd_status[x] |= htohc32(sc, status); 2837 2838 /* get next page offset */ 2839 if (itd_offset[x + 1] == buf_offset) { 2840 /* 2841 * We subtract one so that 2842 * we don't go off the last 2843 * page! 2844 */ 2845 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2846 } else { 2847 usb2_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2848 } 2849 2850 /* check if we need a new page */ 2851 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2852 /* new page needed */ 2853 page_addr = buf_res.physaddr & ~0xFFF; 2854 if (page_no == 6) { 2855 panic("%s: too many pages\n", __FUNCTION__); 2856 } 2857 page_no++; 2858 /* update page address */ 2859 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2860 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2861 } 2862 } 2863 } 2864 /* set IOC bit if we are complete */ 2865 if (nframes == 0) { 2866 td->itd_status[7] |= htohc32(sc, EHCI_ITD_IOC); 2867 } 2868 usb2_pc_cpu_flush(td->page_cache); 2869 #if USB_DEBUG 2870 if (ehcidebug > 15) { 2871 DPRINTF("HS-TD %d\n", nframes); 2872 ehci_dump_itd(sc, td); 2873 } 2874 #endif 2875 /* insert TD into schedule */ 2876 EHCI_APPEND_HS_TD(td, *pp_last); 2877 pp_last++; 2878 2879 td_no = 0; 2880 td_last = td; 2881 td = td->obj_next; 2882 } 2883 } 2884 2885 xfer->td_transfer_last = td_last; 2886 2887 /* update isoc_next */ 2888 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2889 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2890 } 2891 2892 static void 2893 ehci_device_isoc_hs_start(struct usb2_xfer *xfer) 2894 { 2895 /* put transfer on interrupt queue */ 2896 ehci_transfer_intr_enqueue(xfer); 2897 } 2898 2899 struct usb2_pipe_methods ehci_device_isoc_hs_methods = 2900 { 2901 .open = ehci_device_isoc_hs_open, 2902 .close = ehci_device_isoc_hs_close, 2903 .enter = ehci_device_isoc_hs_enter, 2904 .start = ehci_device_isoc_hs_start, 2905 .enter_is_cancelable = 1, 2906 .start_is_cancelable = 1, 2907 }; 2908 2909 /*------------------------------------------------------------------------* 2910 * ehci root control support 2911 *------------------------------------------------------------------------* 2912 * simulate a hardware hub by handling 2913 * all the necessary requests 2914 *------------------------------------------------------------------------*/ 2915 2916 static void 2917 ehci_root_ctrl_open(struct usb2_xfer *xfer) 2918 { 2919 return; 2920 } 2921 2922 static void 2923 ehci_root_ctrl_close(struct usb2_xfer *xfer) 2924 { 2925 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2926 2927 if (sc->sc_root_ctrl.xfer == xfer) { 2928 sc->sc_root_ctrl.xfer = NULL; 2929 } 2930 ehci_device_done(xfer, USB_ERR_CANCELLED); 2931 } 2932 2933 /* data structures and routines 2934 * to emulate the root hub: 2935 */ 2936 2937 static const 2938 struct usb2_device_descriptor ehci_devd = 2939 { 2940 sizeof(struct usb2_device_descriptor), 2941 UDESC_DEVICE, /* type */ 2942 {0x00, 0x02}, /* USB version */ 2943 UDCLASS_HUB, /* class */ 2944 UDSUBCLASS_HUB, /* subclass */ 2945 UDPROTO_HSHUBSTT, /* protocol */ 2946 64, /* max packet */ 2947 {0}, {0}, {0x00, 0x01}, /* device id */ 2948 1, 2, 0, /* string indicies */ 2949 1 /* # of configurations */ 2950 }; 2951 2952 static const 2953 struct usb2_device_qualifier ehci_odevd = 2954 { 2955 sizeof(struct usb2_device_qualifier), 2956 UDESC_DEVICE_QUALIFIER, /* type */ 2957 {0x00, 0x02}, /* USB version */ 2958 UDCLASS_HUB, /* class */ 2959 UDSUBCLASS_HUB, /* subclass */ 2960 UDPROTO_FSHUB, /* protocol */ 2961 0, /* max packet */ 2962 0, /* # of configurations */ 2963 0 2964 }; 2965 2966 static const struct ehci_config_desc ehci_confd = { 2967 .confd = { 2968 .bLength = sizeof(struct usb2_config_descriptor), 2969 .bDescriptorType = UDESC_CONFIG, 2970 .wTotalLength[0] = sizeof(ehci_confd), 2971 .bNumInterface = 1, 2972 .bConfigurationValue = 1, 2973 .iConfiguration = 0, 2974 .bmAttributes = UC_SELF_POWERED, 2975 .bMaxPower = 0 /* max power */ 2976 }, 2977 2978 .ifcd = { 2979 .bLength = sizeof(struct usb2_interface_descriptor), 2980 .bDescriptorType = UDESC_INTERFACE, 2981 .bNumEndpoints = 1, 2982 .bInterfaceClass = UICLASS_HUB, 2983 .bInterfaceSubClass = UISUBCLASS_HUB, 2984 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2985 0 2986 }, 2987 2988 .endpd = { 2989 .bLength = sizeof(struct usb2_endpoint_descriptor), 2990 .bDescriptorType = UDESC_ENDPOINT, 2991 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 2992 .bmAttributes = UE_INTERRUPT, 2993 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2994 .bInterval = 255, 2995 }, 2996 }; 2997 2998 static const 2999 struct usb2_hub_descriptor ehci_hubd = 3000 { 3001 0, /* dynamic length */ 3002 UDESC_HUB, 3003 0, 3004 {0, 0}, 3005 0, 3006 0, 3007 {0}, 3008 }; 3009 3010 static void 3011 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3012 { 3013 uint32_t port; 3014 uint32_t v; 3015 3016 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3017 3018 port = EHCI_PORTSC(index); 3019 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3020 EOWRITE4(sc, port, v | EHCI_PS_PO); 3021 } 3022 3023 static void 3024 ehci_root_ctrl_enter(struct usb2_xfer *xfer) 3025 { 3026 return; 3027 } 3028 3029 static void 3030 ehci_root_ctrl_start(struct usb2_xfer *xfer) 3031 { 3032 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3033 3034 DPRINTF("\n"); 3035 3036 sc->sc_root_ctrl.xfer = xfer; 3037 3038 usb2_bus_roothub_exec(xfer->xroot->bus); 3039 } 3040 3041 static void 3042 ehci_root_ctrl_task(struct usb2_bus *bus) 3043 { 3044 ehci_root_ctrl_poll(EHCI_BUS2SC(bus)); 3045 } 3046 3047 static void 3048 ehci_root_ctrl_done(struct usb2_xfer *xfer, 3049 struct usb2_sw_transfer *std) 3050 { 3051 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3052 char *ptr; 3053 uint32_t port; 3054 uint32_t v; 3055 uint16_t i; 3056 uint16_t value; 3057 uint16_t index; 3058 uint8_t l; 3059 3060 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3061 3062 if (std->state != USB_SW_TR_SETUP) { 3063 if (std->state == USB_SW_TR_PRE_CALLBACK) { 3064 /* transfer transferred */ 3065 ehci_device_done(xfer, std->err); 3066 } 3067 goto done; 3068 } 3069 /* buffer reset */ 3070 std->ptr = sc->sc_hub_desc.temp; 3071 std->len = 0; 3072 3073 value = UGETW(std->req.wValue); 3074 index = UGETW(std->req.wIndex); 3075 3076 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3077 "wValue=0x%04x wIndex=0x%04x\n", 3078 std->req.bmRequestType, std->req.bRequest, 3079 UGETW(std->req.wLength), value, index); 3080 3081 #define C(x,y) ((x) | ((y) << 8)) 3082 switch (C(std->req.bRequest, std->req.bmRequestType)) { 3083 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3084 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3085 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3086 /* 3087 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3088 * for the integrated root hub. 3089 */ 3090 break; 3091 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3092 std->len = 1; 3093 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3094 break; 3095 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3096 switch (value >> 8) { 3097 case UDESC_DEVICE: 3098 if ((value & 0xff) != 0) { 3099 std->err = USB_ERR_IOERROR; 3100 goto done; 3101 } 3102 std->len = sizeof(ehci_devd); 3103 sc->sc_hub_desc.devd = ehci_devd; 3104 break; 3105 /* 3106 * We can't really operate at another speed, 3107 * but the specification says we need this 3108 * descriptor: 3109 */ 3110 case UDESC_DEVICE_QUALIFIER: 3111 if ((value & 0xff) != 0) { 3112 std->err = USB_ERR_IOERROR; 3113 goto done; 3114 } 3115 std->len = sizeof(ehci_odevd); 3116 sc->sc_hub_desc.odevd = ehci_odevd; 3117 break; 3118 3119 case UDESC_CONFIG: 3120 if ((value & 0xff) != 0) { 3121 std->err = USB_ERR_IOERROR; 3122 goto done; 3123 } 3124 std->len = sizeof(ehci_confd); 3125 std->ptr = USB_ADD_BYTES(&ehci_confd, 0); 3126 break; 3127 3128 case UDESC_STRING: 3129 switch (value & 0xff) { 3130 case 0: /* Language table */ 3131 ptr = "\001"; 3132 break; 3133 3134 case 1: /* Vendor */ 3135 ptr = sc->sc_vendor; 3136 break; 3137 3138 case 2: /* Product */ 3139 ptr = "EHCI root HUB"; 3140 break; 3141 3142 default: 3143 ptr = ""; 3144 break; 3145 } 3146 3147 std->len = usb2_make_str_desc 3148 (sc->sc_hub_desc.temp, 3149 sizeof(sc->sc_hub_desc.temp), 3150 ptr); 3151 break; 3152 default: 3153 std->err = USB_ERR_IOERROR; 3154 goto done; 3155 } 3156 break; 3157 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3158 std->len = 1; 3159 sc->sc_hub_desc.temp[0] = 0; 3160 break; 3161 case C(UR_GET_STATUS, UT_READ_DEVICE): 3162 std->len = 2; 3163 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3164 break; 3165 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3166 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3167 std->len = 2; 3168 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3169 break; 3170 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3171 if (value >= USB_MAX_DEVICES) { 3172 std->err = USB_ERR_IOERROR; 3173 goto done; 3174 } 3175 sc->sc_addr = value; 3176 break; 3177 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3178 if ((value != 0) && (value != 1)) { 3179 std->err = USB_ERR_IOERROR; 3180 goto done; 3181 } 3182 sc->sc_conf = value; 3183 break; 3184 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3185 break; 3186 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3187 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3188 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3189 std->err = USB_ERR_IOERROR; 3190 goto done; 3191 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3192 break; 3193 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3194 break; 3195 /* Hub requests */ 3196 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3197 break; 3198 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3199 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3200 3201 if ((index < 1) || 3202 (index > sc->sc_noport)) { 3203 std->err = USB_ERR_IOERROR; 3204 goto done; 3205 } 3206 port = EHCI_PORTSC(index); 3207 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3208 switch (value) { 3209 case UHF_PORT_ENABLE: 3210 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3211 break; 3212 case UHF_PORT_SUSPEND: 3213 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3214 3215 /* 3216 * waking up a High Speed device is rather 3217 * complicated if 3218 */ 3219 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3220 } 3221 /* wait 20ms for resume sequence to complete */ 3222 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3223 3224 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3225 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3226 3227 /* 4ms settle time */ 3228 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3229 break; 3230 case UHF_PORT_POWER: 3231 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3232 break; 3233 case UHF_PORT_TEST: 3234 DPRINTFN(3, "clear port test " 3235 "%d\n", index); 3236 break; 3237 case UHF_PORT_INDICATOR: 3238 DPRINTFN(3, "clear port ind " 3239 "%d\n", index); 3240 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3241 break; 3242 case UHF_C_PORT_CONNECTION: 3243 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3244 break; 3245 case UHF_C_PORT_ENABLE: 3246 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3247 break; 3248 case UHF_C_PORT_SUSPEND: 3249 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3250 break; 3251 case UHF_C_PORT_OVER_CURRENT: 3252 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3253 break; 3254 case UHF_C_PORT_RESET: 3255 sc->sc_isreset = 0; 3256 break; 3257 default: 3258 std->err = USB_ERR_IOERROR; 3259 goto done; 3260 } 3261 break; 3262 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3263 if ((value & 0xff) != 0) { 3264 std->err = USB_ERR_IOERROR; 3265 goto done; 3266 } 3267 v = EOREAD4(sc, EHCI_HCSPARAMS); 3268 3269 sc->sc_hub_desc.hubd = ehci_hubd; 3270 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3271 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 3272 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 3273 (EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) ? 3274 UHD_PORT_IND : 0)); 3275 /* XXX can't find out? */ 3276 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3277 for (l = 0; l < sc->sc_noport; l++) { 3278 /* XXX can't find out? */ 3279 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] &= ~(1 << (l % 8)); 3280 } 3281 sc->sc_hub_desc.hubd.bDescLength = 3282 8 + ((sc->sc_noport + 7) / 8); 3283 std->len = sc->sc_hub_desc.hubd.bDescLength; 3284 break; 3285 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3286 std->len = 16; 3287 bzero(sc->sc_hub_desc.temp, 16); 3288 break; 3289 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3290 DPRINTFN(9, "get port status i=%d\n", 3291 index); 3292 if ((index < 1) || 3293 (index > sc->sc_noport)) { 3294 std->err = USB_ERR_IOERROR; 3295 goto done; 3296 } 3297 v = EOREAD4(sc, EHCI_PORTSC(index)); 3298 DPRINTFN(9, "port status=0x%04x\n", v); 3299 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) { 3300 if ((v & 0xc000000) == 0x8000000) 3301 i = UPS_HIGH_SPEED; 3302 else if ((v & 0xc000000) == 0x4000000) 3303 i = UPS_LOW_SPEED; 3304 else 3305 i = 0; 3306 } else { 3307 i = UPS_HIGH_SPEED; 3308 } 3309 if (v & EHCI_PS_CS) 3310 i |= UPS_CURRENT_CONNECT_STATUS; 3311 if (v & EHCI_PS_PE) 3312 i |= UPS_PORT_ENABLED; 3313 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3314 i |= UPS_SUSPEND; 3315 if (v & EHCI_PS_OCA) 3316 i |= UPS_OVERCURRENT_INDICATOR; 3317 if (v & EHCI_PS_PR) 3318 i |= UPS_RESET; 3319 if (v & EHCI_PS_PP) 3320 i |= UPS_PORT_POWER; 3321 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3322 i = 0; 3323 if (v & EHCI_PS_CSC) 3324 i |= UPS_C_CONNECT_STATUS; 3325 if (v & EHCI_PS_PEC) 3326 i |= UPS_C_PORT_ENABLED; 3327 if (v & EHCI_PS_OCC) 3328 i |= UPS_C_OVERCURRENT_INDICATOR; 3329 if (v & EHCI_PS_FPR) 3330 i |= UPS_C_SUSPEND; 3331 if (sc->sc_isreset) 3332 i |= UPS_C_PORT_RESET; 3333 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3334 std->len = sizeof(sc->sc_hub_desc.ps); 3335 break; 3336 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3337 std->err = USB_ERR_IOERROR; 3338 goto done; 3339 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3340 break; 3341 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3342 if ((index < 1) || 3343 (index > sc->sc_noport)) { 3344 std->err = USB_ERR_IOERROR; 3345 goto done; 3346 } 3347 port = EHCI_PORTSC(index); 3348 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3349 switch (value) { 3350 case UHF_PORT_ENABLE: 3351 EOWRITE4(sc, port, v | EHCI_PS_PE); 3352 break; 3353 case UHF_PORT_SUSPEND: 3354 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3355 break; 3356 case UHF_PORT_RESET: 3357 DPRINTFN(6, "reset port %d\n", index); 3358 #if USB_DEBUG 3359 if (ehcinohighspeed) { 3360 /* 3361 * Connect USB device to companion 3362 * controller. 3363 */ 3364 ehci_disown(sc, index, 1); 3365 break; 3366 } 3367 #endif 3368 if (EHCI_PS_IS_LOWSPEED(v) && 3369 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3370 /* Low speed device, give up ownership. */ 3371 ehci_disown(sc, index, 1); 3372 break; 3373 } 3374 /* Start reset sequence. */ 3375 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3376 EOWRITE4(sc, port, v | EHCI_PS_PR); 3377 3378 /* Wait for reset to complete. */ 3379 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 3380 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 3381 3382 /* Terminate reset sequence. */ 3383 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3384 EOWRITE4(sc, port, v); 3385 3386 /* Wait for HC to complete reset. */ 3387 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 3388 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3389 3390 v = EOREAD4(sc, port); 3391 DPRINTF("ehci after reset, status=0x%08x\n", v); 3392 if (v & EHCI_PS_PR) { 3393 device_printf(sc->sc_bus.bdev, 3394 "port reset timeout\n"); 3395 std->err = USB_ERR_TIMEOUT; 3396 goto done; 3397 } 3398 if (!(v & EHCI_PS_PE) && 3399 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3400 /* Not a high speed device, give up ownership.*/ 3401 ehci_disown(sc, index, 0); 3402 break; 3403 } 3404 sc->sc_isreset = 1; 3405 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3406 index, v); 3407 break; 3408 3409 case UHF_PORT_POWER: 3410 DPRINTFN(3, "set port power %d\n", index); 3411 EOWRITE4(sc, port, v | EHCI_PS_PP); 3412 break; 3413 3414 case UHF_PORT_TEST: 3415 DPRINTFN(3, "set port test %d\n", index); 3416 break; 3417 3418 case UHF_PORT_INDICATOR: 3419 DPRINTFN(3, "set port ind %d\n", index); 3420 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3421 break; 3422 3423 default: 3424 std->err = USB_ERR_IOERROR; 3425 goto done; 3426 } 3427 break; 3428 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3429 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3430 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3431 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3432 break; 3433 default: 3434 std->err = USB_ERR_IOERROR; 3435 goto done; 3436 } 3437 done: 3438 return; 3439 } 3440 3441 static void 3442 ehci_root_ctrl_poll(ehci_softc_t *sc) 3443 { 3444 usb2_sw_transfer(&sc->sc_root_ctrl, 3445 &ehci_root_ctrl_done); 3446 } 3447 3448 struct usb2_pipe_methods ehci_root_ctrl_methods = 3449 { 3450 .open = ehci_root_ctrl_open, 3451 .close = ehci_root_ctrl_close, 3452 .enter = ehci_root_ctrl_enter, 3453 .start = ehci_root_ctrl_start, 3454 .enter_is_cancelable = 1, 3455 .start_is_cancelable = 0, 3456 }; 3457 3458 /*------------------------------------------------------------------------* 3459 * ehci root interrupt support 3460 *------------------------------------------------------------------------*/ 3461 static void 3462 ehci_root_intr_open(struct usb2_xfer *xfer) 3463 { 3464 return; 3465 } 3466 3467 static void 3468 ehci_root_intr_close(struct usb2_xfer *xfer) 3469 { 3470 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3471 3472 if (sc->sc_root_intr.xfer == xfer) { 3473 sc->sc_root_intr.xfer = NULL; 3474 } 3475 ehci_device_done(xfer, USB_ERR_CANCELLED); 3476 } 3477 3478 static void 3479 ehci_root_intr_enter(struct usb2_xfer *xfer) 3480 { 3481 return; 3482 } 3483 3484 static void 3485 ehci_root_intr_start(struct usb2_xfer *xfer) 3486 { 3487 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3488 3489 sc->sc_root_intr.xfer = xfer; 3490 } 3491 3492 struct usb2_pipe_methods ehci_root_intr_methods = 3493 { 3494 .open = ehci_root_intr_open, 3495 .close = ehci_root_intr_close, 3496 .enter = ehci_root_intr_enter, 3497 .start = ehci_root_intr_start, 3498 .enter_is_cancelable = 1, 3499 .start_is_cancelable = 1, 3500 }; 3501 3502 static void 3503 ehci_xfer_setup(struct usb2_setup_params *parm) 3504 { 3505 struct usb2_page_search page_info; 3506 struct usb2_page_cache *pc; 3507 ehci_softc_t *sc; 3508 struct usb2_xfer *xfer; 3509 void *last_obj; 3510 uint32_t nqtd; 3511 uint32_t nqh; 3512 uint32_t nsitd; 3513 uint32_t nitd; 3514 uint32_t n; 3515 3516 sc = EHCI_BUS2SC(parm->udev->bus); 3517 xfer = parm->curr_xfer; 3518 3519 nqtd = 0; 3520 nqh = 0; 3521 nsitd = 0; 3522 nitd = 0; 3523 3524 /* 3525 * compute maximum number of some structures 3526 */ 3527 if (parm->methods == &ehci_device_ctrl_methods) { 3528 3529 /* 3530 * The proof for the "nqtd" formula is illustrated like 3531 * this: 3532 * 3533 * +------------------------------------+ 3534 * | | 3535 * | |remainder -> | 3536 * | +-----+---+ | 3537 * | | xxx | x | frm 0 | 3538 * | +-----+---++ | 3539 * | | xxx | xx | frm 1 | 3540 * | +-----+----+ | 3541 * | ... | 3542 * +------------------------------------+ 3543 * 3544 * "xxx" means a completely full USB transfer descriptor 3545 * 3546 * "x" and "xx" means a short USB packet 3547 * 3548 * For the remainder of an USB transfer modulo 3549 * "max_data_length" we need two USB transfer descriptors. 3550 * One to transfer the remaining data and one to finalise 3551 * with a zero length packet in case the "force_short_xfer" 3552 * flag is set. We only need two USB transfer descriptors in 3553 * the case where the transfer length of the first one is a 3554 * factor of "max_frame_size". The rest of the needed USB 3555 * transfer descriptors is given by the buffer size divided 3556 * by the maximum data payload. 3557 */ 3558 parm->hc_max_packet_size = 0x400; 3559 parm->hc_max_packet_count = 1; 3560 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3561 xfer->flags_int.bdma_enable = 1; 3562 3563 usb2_transfer_setup_sub(parm); 3564 3565 nqh = 1; 3566 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3567 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3568 3569 } else if (parm->methods == &ehci_device_bulk_methods) { 3570 3571 parm->hc_max_packet_size = 0x400; 3572 parm->hc_max_packet_count = 1; 3573 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3574 xfer->flags_int.bdma_enable = 1; 3575 3576 usb2_transfer_setup_sub(parm); 3577 3578 nqh = 1; 3579 nqtd = ((2 * xfer->nframes) 3580 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3581 3582 } else if (parm->methods == &ehci_device_intr_methods) { 3583 3584 if (parm->speed == USB_SPEED_HIGH) { 3585 parm->hc_max_packet_size = 0x400; 3586 parm->hc_max_packet_count = 3; 3587 } else if (parm->speed == USB_SPEED_FULL) { 3588 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3589 parm->hc_max_packet_count = 1; 3590 } else { 3591 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3592 parm->hc_max_packet_count = 1; 3593 } 3594 3595 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3596 xfer->flags_int.bdma_enable = 1; 3597 3598 usb2_transfer_setup_sub(parm); 3599 3600 nqh = 1; 3601 nqtd = ((2 * xfer->nframes) 3602 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3603 3604 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3605 3606 parm->hc_max_packet_size = 0x3FF; 3607 parm->hc_max_packet_count = 1; 3608 parm->hc_max_frame_size = 0x3FF; 3609 xfer->flags_int.bdma_enable = 1; 3610 3611 usb2_transfer_setup_sub(parm); 3612 3613 nsitd = xfer->nframes; 3614 3615 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3616 3617 parm->hc_max_packet_size = 0x400; 3618 parm->hc_max_packet_count = 3; 3619 parm->hc_max_frame_size = 0xC00; 3620 xfer->flags_int.bdma_enable = 1; 3621 3622 usb2_transfer_setup_sub(parm); 3623 3624 nitd = (xfer->nframes + 7) / 8; 3625 3626 } else { 3627 3628 parm->hc_max_packet_size = 0x400; 3629 parm->hc_max_packet_count = 1; 3630 parm->hc_max_frame_size = 0x400; 3631 3632 usb2_transfer_setup_sub(parm); 3633 } 3634 3635 alloc_dma_set: 3636 3637 if (parm->err) { 3638 return; 3639 } 3640 /* 3641 * Allocate queue heads and transfer descriptors 3642 */ 3643 last_obj = NULL; 3644 3645 if (usb2_transfer_setup_sub_malloc( 3646 parm, &pc, sizeof(ehci_itd_t), 3647 EHCI_ITD_ALIGN, nitd)) { 3648 parm->err = USB_ERR_NOMEM; 3649 return; 3650 } 3651 if (parm->buf) { 3652 for (n = 0; n != nitd; n++) { 3653 ehci_itd_t *td; 3654 3655 usb2_get_page(pc + n, 0, &page_info); 3656 3657 td = page_info.buffer; 3658 3659 /* init TD */ 3660 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3661 td->obj_next = last_obj; 3662 td->page_cache = pc + n; 3663 3664 last_obj = td; 3665 3666 usb2_pc_cpu_flush(pc + n); 3667 } 3668 } 3669 if (usb2_transfer_setup_sub_malloc( 3670 parm, &pc, sizeof(ehci_sitd_t), 3671 EHCI_SITD_ALIGN, nsitd)) { 3672 parm->err = USB_ERR_NOMEM; 3673 return; 3674 } 3675 if (parm->buf) { 3676 for (n = 0; n != nsitd; n++) { 3677 ehci_sitd_t *td; 3678 3679 usb2_get_page(pc + n, 0, &page_info); 3680 3681 td = page_info.buffer; 3682 3683 /* init TD */ 3684 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3685 td->obj_next = last_obj; 3686 td->page_cache = pc + n; 3687 3688 last_obj = td; 3689 3690 usb2_pc_cpu_flush(pc + n); 3691 } 3692 } 3693 if (usb2_transfer_setup_sub_malloc( 3694 parm, &pc, sizeof(ehci_qtd_t), 3695 EHCI_QTD_ALIGN, nqtd)) { 3696 parm->err = USB_ERR_NOMEM; 3697 return; 3698 } 3699 if (parm->buf) { 3700 for (n = 0; n != nqtd; n++) { 3701 ehci_qtd_t *qtd; 3702 3703 usb2_get_page(pc + n, 0, &page_info); 3704 3705 qtd = page_info.buffer; 3706 3707 /* init TD */ 3708 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3709 qtd->obj_next = last_obj; 3710 qtd->page_cache = pc + n; 3711 3712 last_obj = qtd; 3713 3714 usb2_pc_cpu_flush(pc + n); 3715 } 3716 } 3717 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3718 3719 last_obj = NULL; 3720 3721 if (usb2_transfer_setup_sub_malloc( 3722 parm, &pc, sizeof(ehci_qh_t), 3723 EHCI_QH_ALIGN, nqh)) { 3724 parm->err = USB_ERR_NOMEM; 3725 return; 3726 } 3727 if (parm->buf) { 3728 for (n = 0; n != nqh; n++) { 3729 ehci_qh_t *qh; 3730 3731 usb2_get_page(pc + n, 0, &page_info); 3732 3733 qh = page_info.buffer; 3734 3735 /* init QH */ 3736 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3737 qh->obj_next = last_obj; 3738 qh->page_cache = pc + n; 3739 3740 last_obj = qh; 3741 3742 usb2_pc_cpu_flush(pc + n); 3743 } 3744 } 3745 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3746 3747 if (!xfer->flags_int.curr_dma_set) { 3748 xfer->flags_int.curr_dma_set = 1; 3749 goto alloc_dma_set; 3750 } 3751 } 3752 3753 static void 3754 ehci_xfer_unsetup(struct usb2_xfer *xfer) 3755 { 3756 return; 3757 } 3758 3759 static void 3760 ehci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 3761 struct usb2_pipe *pipe) 3762 { 3763 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3764 3765 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3766 pipe, udev->address, 3767 edesc->bEndpointAddress, udev->flags.usb2_mode, 3768 sc->sc_addr); 3769 3770 if (udev->flags.usb2_mode != USB_MODE_HOST) { 3771 /* not supported */ 3772 return; 3773 } 3774 if (udev->device_index == sc->sc_addr) { 3775 switch (edesc->bEndpointAddress) { 3776 case USB_CONTROL_ENDPOINT: 3777 pipe->methods = &ehci_root_ctrl_methods; 3778 break; 3779 case UE_DIR_IN | EHCI_INTR_ENDPT: 3780 pipe->methods = &ehci_root_intr_methods; 3781 break; 3782 default: 3783 /* do nothing */ 3784 break; 3785 } 3786 } else { 3787 if ((udev->speed != USB_SPEED_HIGH) && 3788 ((udev->hs_hub_addr == 0) || 3789 (udev->hs_port_no == 0) || 3790 (udev->bus->devices[udev->hs_hub_addr] == NULL) || 3791 (udev->bus->devices[udev->hs_hub_addr]->hub == NULL))) { 3792 /* We need a transaction translator */ 3793 goto done; 3794 } 3795 switch (edesc->bmAttributes & UE_XFERTYPE) { 3796 case UE_CONTROL: 3797 pipe->methods = &ehci_device_ctrl_methods; 3798 break; 3799 case UE_INTERRUPT: 3800 pipe->methods = &ehci_device_intr_methods; 3801 break; 3802 case UE_ISOCHRONOUS: 3803 if (udev->speed == USB_SPEED_HIGH) { 3804 pipe->methods = &ehci_device_isoc_hs_methods; 3805 } else if (udev->speed == USB_SPEED_FULL) { 3806 pipe->methods = &ehci_device_isoc_fs_methods; 3807 } 3808 break; 3809 case UE_BULK: 3810 if (udev->speed != USB_SPEED_LOW) { 3811 pipe->methods = &ehci_device_bulk_methods; 3812 } 3813 break; 3814 default: 3815 /* do nothing */ 3816 break; 3817 } 3818 } 3819 done: 3820 return; 3821 } 3822 3823 static void 3824 ehci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 3825 { 3826 /* 3827 * Wait until the hardware has finished any possible use of 3828 * the transfer descriptor(s) and QH 3829 */ 3830 *pus = (188); /* microseconds */ 3831 } 3832 3833 static void 3834 ehci_device_resume(struct usb2_device *udev) 3835 { 3836 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3837 struct usb2_xfer *xfer; 3838 struct usb2_pipe_methods *methods; 3839 3840 DPRINTF("\n"); 3841 3842 USB_BUS_LOCK(udev->bus); 3843 3844 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3845 3846 if (xfer->xroot->udev == udev) { 3847 3848 methods = xfer->pipe->methods; 3849 3850 if ((methods == &ehci_device_bulk_methods) || 3851 (methods == &ehci_device_ctrl_methods)) { 3852 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3853 sc->sc_async_p_last); 3854 } 3855 if (methods == &ehci_device_intr_methods) { 3856 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3857 sc->sc_intr_p_last[xfer->qh_pos]); 3858 } 3859 } 3860 } 3861 3862 USB_BUS_UNLOCK(udev->bus); 3863 3864 return; 3865 } 3866 3867 static void 3868 ehci_device_suspend(struct usb2_device *udev) 3869 { 3870 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3871 struct usb2_xfer *xfer; 3872 struct usb2_pipe_methods *methods; 3873 3874 DPRINTF("\n"); 3875 3876 USB_BUS_LOCK(udev->bus); 3877 3878 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3879 3880 if (xfer->xroot->udev == udev) { 3881 3882 methods = xfer->pipe->methods; 3883 3884 if ((methods == &ehci_device_bulk_methods) || 3885 (methods == &ehci_device_ctrl_methods)) { 3886 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3887 sc->sc_async_p_last); 3888 } 3889 if (methods == &ehci_device_intr_methods) { 3890 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3891 sc->sc_intr_p_last[xfer->qh_pos]); 3892 } 3893 } 3894 } 3895 3896 USB_BUS_UNLOCK(udev->bus); 3897 3898 return; 3899 } 3900 3901 static void 3902 ehci_set_hw_power(struct usb2_bus *bus) 3903 { 3904 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3905 uint32_t temp; 3906 uint32_t flags; 3907 3908 DPRINTF("\n"); 3909 3910 USB_BUS_LOCK(bus); 3911 3912 flags = bus->hw_power_state; 3913 3914 temp = EOREAD4(sc, EHCI_USBCMD); 3915 3916 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3917 3918 if (flags & (USB_HW_POWER_CONTROL | 3919 USB_HW_POWER_BULK)) { 3920 DPRINTF("Async is active\n"); 3921 temp |= EHCI_CMD_ASE; 3922 } 3923 if (flags & (USB_HW_POWER_INTERRUPT | 3924 USB_HW_POWER_ISOC)) { 3925 DPRINTF("Periodic is active\n"); 3926 temp |= EHCI_CMD_PSE; 3927 } 3928 EOWRITE4(sc, EHCI_USBCMD, temp); 3929 3930 USB_BUS_UNLOCK(bus); 3931 3932 return; 3933 } 3934 3935 struct usb2_bus_methods ehci_bus_methods = 3936 { 3937 .pipe_init = ehci_pipe_init, 3938 .xfer_setup = ehci_xfer_setup, 3939 .xfer_unsetup = ehci_xfer_unsetup, 3940 .get_dma_delay = ehci_get_dma_delay, 3941 .device_resume = ehci_device_resume, 3942 .device_suspend = ehci_device_suspend, 3943 .set_hw_power = ehci_set_hw_power, 3944 .roothub_exec = ehci_root_ctrl_task, 3945 }; 3946