1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 6 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 7 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 8 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 34 * 35 * The EHCI 0.96 spec can be found at 36 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 37 * The EHCI 1.0 spec can be found at 38 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/usb_20.zip 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) command failures are not recovered correctly 47 */ 48 49 #ifdef USB_GLOBAL_INCLUDE_FILE 50 #include USB_GLOBAL_INCLUDE_FILE 51 #else 52 #include <sys/stdint.h> 53 #include <sys/stddef.h> 54 #include <sys/param.h> 55 #include <sys/queue.h> 56 #include <sys/types.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/bus.h> 60 #include <sys/module.h> 61 #include <sys/lock.h> 62 #include <sys/mutex.h> 63 #include <sys/condvar.h> 64 #include <sys/sysctl.h> 65 #include <sys/sx.h> 66 #include <sys/unistd.h> 67 #include <sys/callout.h> 68 #include <sys/malloc.h> 69 #include <sys/priv.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 74 #define USB_DEBUG_VAR ehcidebug 75 76 #include <dev/usb/usb_core.h> 77 #include <dev/usb/usb_debug.h> 78 #include <dev/usb/usb_busdma.h> 79 #include <dev/usb/usb_process.h> 80 #include <dev/usb/usb_transfer.h> 81 #include <dev/usb/usb_device.h> 82 #include <dev/usb/usb_hub.h> 83 #include <dev/usb/usb_util.h> 84 85 #include <dev/usb/usb_controller.h> 86 #include <dev/usb/usb_bus.h> 87 #endif /* USB_GLOBAL_INCLUDE_FILE */ 88 89 #include <dev/usb/controller/ehci.h> 90 #include <dev/usb/controller/ehcireg.h> 91 92 #define EHCI_BUS2SC(bus) \ 93 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 94 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 95 96 #ifdef USB_DEBUG 97 static int ehcidebug = 0; 98 static int ehcinohighspeed = 0; 99 static int ehciiaadbug = 0; 100 static int ehcilostintrbug = 0; 101 102 static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 103 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RWTUN, 104 &ehcidebug, 0, "Debug level"); 105 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RWTUN, 106 &ehcinohighspeed, 0, "Disable High Speed USB"); 107 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RWTUN, 108 &ehciiaadbug, 0, "Enable doorbell bug workaround"); 109 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RWTUN, 110 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround"); 111 112 static void ehci_dump_regs(ehci_softc_t *sc); 113 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 114 115 #endif 116 117 #define EHCI_INTR_ENDPT 1 118 119 static const struct usb_bus_methods ehci_bus_methods; 120 static const struct usb_pipe_methods ehci_device_bulk_methods; 121 static const struct usb_pipe_methods ehci_device_ctrl_methods; 122 static const struct usb_pipe_methods ehci_device_intr_methods; 123 static const struct usb_pipe_methods ehci_device_isoc_fs_methods; 124 static const struct usb_pipe_methods ehci_device_isoc_hs_methods; 125 126 static void ehci_do_poll(struct usb_bus *); 127 static void ehci_device_done(struct usb_xfer *, usb_error_t); 128 static uint8_t ehci_check_transfer(struct usb_xfer *); 129 static void ehci_timeout(void *); 130 static void ehci_poll_timeout(void *); 131 132 static void ehci_root_intr(ehci_softc_t *sc); 133 134 struct ehci_std_temp { 135 ehci_softc_t *sc; 136 struct usb_page_cache *pc; 137 ehci_qtd_t *td; 138 ehci_qtd_t *td_next; 139 uint32_t average; 140 uint32_t qtd_status; 141 uint32_t len; 142 uint16_t max_frame_size; 143 uint8_t shortpkt; 144 uint8_t auto_data_toggle; 145 uint8_t setup_alt_next; 146 uint8_t last_frame; 147 }; 148 149 void 150 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 151 { 152 ehci_softc_t *sc = EHCI_BUS2SC(bus); 153 uint32_t i; 154 155 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 156 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 157 158 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 159 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 160 161 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 162 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 163 164 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 165 cb(bus, sc->sc_hw.intr_start_pc + i, 166 sc->sc_hw.intr_start_pg + i, 167 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 168 } 169 170 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 171 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 172 sc->sc_hw.isoc_hs_start_pg + i, 173 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 174 } 175 176 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 177 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 178 sc->sc_hw.isoc_fs_start_pg + i, 179 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 180 } 181 } 182 183 usb_error_t 184 ehci_reset(ehci_softc_t *sc) 185 { 186 uint32_t hcr; 187 int i; 188 189 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 190 for (i = 0; i < 100; i++) { 191 usb_pause_mtx(NULL, hz / 128); 192 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 193 if (!hcr) { 194 if (sc->sc_vendor_post_reset != NULL) 195 sc->sc_vendor_post_reset(sc); 196 return (0); 197 } 198 } 199 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 200 return (USB_ERR_IOERROR); 201 } 202 203 static usb_error_t 204 ehci_hcreset(ehci_softc_t *sc) 205 { 206 uint32_t hcr; 207 int i; 208 209 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 210 for (i = 0; i < 100; i++) { 211 usb_pause_mtx(NULL, hz / 128); 212 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 213 if (hcr) 214 break; 215 } 216 if (!hcr) 217 /* 218 * Fall through and try reset anyway even though 219 * Table 2-9 in the EHCI spec says this will result 220 * in undefined behavior. 221 */ 222 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 223 224 return (ehci_reset(sc)); 225 } 226 227 static int 228 ehci_init_sub(struct ehci_softc *sc) 229 { 230 struct usb_page_search buf_res; 231 uint32_t cparams; 232 uint32_t hcr; 233 uint8_t i; 234 235 cparams = EREAD4(sc, EHCI_HCCPARAMS); 236 237 DPRINTF("cparams=0x%x\n", cparams); 238 239 if (EHCI_HCC_64BIT(cparams)) { 240 DPRINTF("HCC uses 64-bit structures\n"); 241 242 /* MUST clear segment register if 64 bit capable */ 243 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 244 } 245 246 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 247 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 248 249 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 250 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 251 252 /* enable interrupts */ 253 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 254 255 /* turn on controller */ 256 EOWRITE4(sc, EHCI_USBCMD, 257 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 258 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 259 EHCI_CMD_ASE | 260 EHCI_CMD_PSE | 261 EHCI_CMD_RS); 262 263 /* Take over port ownership */ 264 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 265 266 for (i = 0; i < 100; i++) { 267 usb_pause_mtx(NULL, hz / 128); 268 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 269 if (!hcr) { 270 break; 271 } 272 } 273 if (hcr) { 274 device_printf(sc->sc_bus.bdev, "run timeout\n"); 275 return (USB_ERR_IOERROR); 276 } 277 return (USB_ERR_NORMAL_COMPLETION); 278 } 279 280 usb_error_t 281 ehci_init(ehci_softc_t *sc) 282 { 283 struct usb_page_search buf_res; 284 uint32_t version; 285 uint32_t sparams; 286 uint16_t i; 287 uint16_t x; 288 uint16_t y; 289 uint16_t bit; 290 usb_error_t err = 0; 291 292 DPRINTF("start\n"); 293 294 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 295 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0); 296 297 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 298 299 #ifdef USB_DEBUG 300 if (ehciiaadbug) 301 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 302 if (ehcilostintrbug) 303 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 304 if (ehcidebug > 2) { 305 ehci_dump_regs(sc); 306 } 307 #endif 308 309 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 310 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 311 version >> 8, version & 0xff); 312 313 sparams = EREAD4(sc, EHCI_HCSPARAMS); 314 DPRINTF("sparams=0x%x\n", sparams); 315 316 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 317 sc->sc_bus.usbrev = USB_REV_2_0; 318 319 if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) { 320 /* Reset the controller */ 321 DPRINTF("%s: resetting\n", 322 device_get_nameunit(sc->sc_bus.bdev)); 323 324 err = ehci_hcreset(sc); 325 if (err) { 326 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 327 return (err); 328 } 329 } 330 331 /* 332 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 333 * bytes 2: 256*4 bytes 3: unknown 334 */ 335 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 336 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 337 return (USB_ERR_IOERROR); 338 } 339 /* set up the bus struct */ 340 sc->sc_bus.methods = &ehci_bus_methods; 341 342 sc->sc_eintrs = EHCI_NORMAL_INTRS; 343 344 if (1) { 345 struct ehci_qh_sub *qh; 346 347 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 348 349 qh = buf_res.buffer; 350 351 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 352 353 /* init terminate TD */ 354 qh->qtd_next = 355 htohc32(sc, EHCI_LINK_TERMINATE); 356 qh->qtd_altnext = 357 htohc32(sc, EHCI_LINK_TERMINATE); 358 qh->qtd_status = 359 htohc32(sc, EHCI_QTD_HALTED); 360 } 361 362 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 363 ehci_qh_t *qh; 364 365 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 366 367 qh = buf_res.buffer; 368 369 /* initialize page cache pointer */ 370 371 qh->page_cache = sc->sc_hw.intr_start_pc + i; 372 373 /* store a pointer to queue head */ 374 375 sc->sc_intr_p_last[i] = qh; 376 377 qh->qh_self = 378 htohc32(sc, buf_res.physaddr) | 379 htohc32(sc, EHCI_LINK_QH); 380 381 qh->qh_endp = 382 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 383 qh->qh_endphub = 384 htohc32(sc, EHCI_QH_SET_MULT(1)); 385 qh->qh_curqtd = 0; 386 387 qh->qh_qtd.qtd_next = 388 htohc32(sc, EHCI_LINK_TERMINATE); 389 qh->qh_qtd.qtd_altnext = 390 htohc32(sc, EHCI_LINK_TERMINATE); 391 qh->qh_qtd.qtd_status = 392 htohc32(sc, EHCI_QTD_HALTED); 393 } 394 395 /* 396 * the QHs are arranged to give poll intervals that are 397 * powers of 2 times 1ms 398 */ 399 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 400 while (bit) { 401 x = bit; 402 while (x & bit) { 403 ehci_qh_t *qh_x; 404 ehci_qh_t *qh_y; 405 406 y = (x ^ bit) | (bit / 2); 407 408 qh_x = sc->sc_intr_p_last[x]; 409 qh_y = sc->sc_intr_p_last[y]; 410 411 /* 412 * the next QH has half the poll interval 413 */ 414 qh_x->qh_link = qh_y->qh_self; 415 416 x++; 417 } 418 bit >>= 1; 419 } 420 421 if (1) { 422 ehci_qh_t *qh; 423 424 qh = sc->sc_intr_p_last[0]; 425 426 /* the last (1ms) QH terminates */ 427 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 428 } 429 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 430 ehci_sitd_t *sitd; 431 ehci_itd_t *itd; 432 433 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 434 435 sitd = buf_res.buffer; 436 437 /* initialize page cache pointer */ 438 439 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 440 441 /* store a pointer to the transfer descriptor */ 442 443 sc->sc_isoc_fs_p_last[i] = sitd; 444 445 /* initialize full speed isochronous */ 446 447 sitd->sitd_self = 448 htohc32(sc, buf_res.physaddr) | 449 htohc32(sc, EHCI_LINK_SITD); 450 451 sitd->sitd_back = 452 htohc32(sc, EHCI_LINK_TERMINATE); 453 454 sitd->sitd_next = 455 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 456 457 458 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 459 460 itd = buf_res.buffer; 461 462 /* initialize page cache pointer */ 463 464 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 465 466 /* store a pointer to the transfer descriptor */ 467 468 sc->sc_isoc_hs_p_last[i] = itd; 469 470 /* initialize high speed isochronous */ 471 472 itd->itd_self = 473 htohc32(sc, buf_res.physaddr) | 474 htohc32(sc, EHCI_LINK_ITD); 475 476 itd->itd_next = 477 sitd->sitd_self; 478 } 479 480 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 481 482 if (1) { 483 uint32_t *pframes; 484 485 pframes = buf_res.buffer; 486 487 /* 488 * execution order: 489 * pframes -> high speed isochronous -> 490 * full speed isochronous -> interrupt QH's 491 */ 492 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 493 pframes[i] = sc->sc_isoc_hs_p_last 494 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 495 } 496 } 497 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 498 499 if (1) { 500 501 ehci_qh_t *qh; 502 503 qh = buf_res.buffer; 504 505 /* initialize page cache pointer */ 506 507 qh->page_cache = &sc->sc_hw.async_start_pc; 508 509 /* store a pointer to the queue head */ 510 511 sc->sc_async_p_last = qh; 512 513 /* init dummy QH that starts the async list */ 514 515 qh->qh_self = 516 htohc32(sc, buf_res.physaddr) | 517 htohc32(sc, EHCI_LINK_QH); 518 519 /* fill the QH */ 520 qh->qh_endp = 521 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 522 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 523 qh->qh_link = qh->qh_self; 524 qh->qh_curqtd = 0; 525 526 /* fill the overlay qTD */ 527 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 528 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 529 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 530 } 531 /* flush all cache into memory */ 532 533 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 534 535 #ifdef USB_DEBUG 536 if (ehcidebug) { 537 ehci_dump_sqh(sc, sc->sc_async_p_last); 538 } 539 #endif 540 541 /* finial setup */ 542 err = ehci_init_sub(sc); 543 544 if (!err) { 545 /* catch any lost interrupts */ 546 ehci_do_poll(&sc->sc_bus); 547 } 548 return (err); 549 } 550 551 /* 552 * shut down the controller when the system is going down 553 */ 554 void 555 ehci_detach(ehci_softc_t *sc) 556 { 557 USB_BUS_LOCK(&sc->sc_bus); 558 559 usb_callout_stop(&sc->sc_tmo_pcd); 560 usb_callout_stop(&sc->sc_tmo_poll); 561 562 EOWRITE4(sc, EHCI_USBINTR, 0); 563 USB_BUS_UNLOCK(&sc->sc_bus); 564 565 if (ehci_hcreset(sc)) { 566 DPRINTF("reset failed!\n"); 567 } 568 569 /* XXX let stray task complete */ 570 usb_pause_mtx(NULL, hz / 20); 571 572 usb_callout_drain(&sc->sc_tmo_pcd); 573 usb_callout_drain(&sc->sc_tmo_poll); 574 } 575 576 static void 577 ehci_suspend(ehci_softc_t *sc) 578 { 579 DPRINTF("stopping the HC\n"); 580 581 /* reset HC */ 582 ehci_hcreset(sc); 583 } 584 585 static void 586 ehci_resume(ehci_softc_t *sc) 587 { 588 /* reset HC */ 589 ehci_hcreset(sc); 590 591 /* setup HC */ 592 ehci_init_sub(sc); 593 594 /* catch any lost interrupts */ 595 ehci_do_poll(&sc->sc_bus); 596 } 597 598 #ifdef USB_DEBUG 599 static void 600 ehci_dump_regs(ehci_softc_t *sc) 601 { 602 uint32_t i; 603 604 i = EOREAD4(sc, EHCI_USBCMD); 605 printf("cmd=0x%08x\n", i); 606 607 if (i & EHCI_CMD_ITC_1) 608 printf(" EHCI_CMD_ITC_1\n"); 609 if (i & EHCI_CMD_ITC_2) 610 printf(" EHCI_CMD_ITC_2\n"); 611 if (i & EHCI_CMD_ITC_4) 612 printf(" EHCI_CMD_ITC_4\n"); 613 if (i & EHCI_CMD_ITC_8) 614 printf(" EHCI_CMD_ITC_8\n"); 615 if (i & EHCI_CMD_ITC_16) 616 printf(" EHCI_CMD_ITC_16\n"); 617 if (i & EHCI_CMD_ITC_32) 618 printf(" EHCI_CMD_ITC_32\n"); 619 if (i & EHCI_CMD_ITC_64) 620 printf(" EHCI_CMD_ITC_64\n"); 621 if (i & EHCI_CMD_ASPME) 622 printf(" EHCI_CMD_ASPME\n"); 623 if (i & EHCI_CMD_ASPMC) 624 printf(" EHCI_CMD_ASPMC\n"); 625 if (i & EHCI_CMD_LHCR) 626 printf(" EHCI_CMD_LHCR\n"); 627 if (i & EHCI_CMD_IAAD) 628 printf(" EHCI_CMD_IAAD\n"); 629 if (i & EHCI_CMD_ASE) 630 printf(" EHCI_CMD_ASE\n"); 631 if (i & EHCI_CMD_PSE) 632 printf(" EHCI_CMD_PSE\n"); 633 if (i & EHCI_CMD_FLS_M) 634 printf(" EHCI_CMD_FLS_M\n"); 635 if (i & EHCI_CMD_HCRESET) 636 printf(" EHCI_CMD_HCRESET\n"); 637 if (i & EHCI_CMD_RS) 638 printf(" EHCI_CMD_RS\n"); 639 640 i = EOREAD4(sc, EHCI_USBSTS); 641 642 printf("sts=0x%08x\n", i); 643 644 if (i & EHCI_STS_ASS) 645 printf(" EHCI_STS_ASS\n"); 646 if (i & EHCI_STS_PSS) 647 printf(" EHCI_STS_PSS\n"); 648 if (i & EHCI_STS_REC) 649 printf(" EHCI_STS_REC\n"); 650 if (i & EHCI_STS_HCH) 651 printf(" EHCI_STS_HCH\n"); 652 if (i & EHCI_STS_IAA) 653 printf(" EHCI_STS_IAA\n"); 654 if (i & EHCI_STS_HSE) 655 printf(" EHCI_STS_HSE\n"); 656 if (i & EHCI_STS_FLR) 657 printf(" EHCI_STS_FLR\n"); 658 if (i & EHCI_STS_PCD) 659 printf(" EHCI_STS_PCD\n"); 660 if (i & EHCI_STS_ERRINT) 661 printf(" EHCI_STS_ERRINT\n"); 662 if (i & EHCI_STS_INT) 663 printf(" EHCI_STS_INT\n"); 664 665 printf("ien=0x%08x\n", 666 EOREAD4(sc, EHCI_USBINTR)); 667 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 668 EOREAD4(sc, EHCI_FRINDEX), 669 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 670 EOREAD4(sc, EHCI_PERIODICLISTBASE), 671 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 672 for (i = 1; i <= sc->sc_noport; i++) { 673 printf("port %d status=0x%08x\n", i, 674 EOREAD4(sc, EHCI_PORTSC(i))); 675 } 676 } 677 678 static void 679 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 680 { 681 link = hc32toh(sc, link); 682 printf("0x%08x", link); 683 if (link & EHCI_LINK_TERMINATE) 684 printf("<T>"); 685 else { 686 printf("<"); 687 if (type) { 688 switch (EHCI_LINK_TYPE(link)) { 689 case EHCI_LINK_ITD: 690 printf("ITD"); 691 break; 692 case EHCI_LINK_QH: 693 printf("QH"); 694 break; 695 case EHCI_LINK_SITD: 696 printf("SITD"); 697 break; 698 case EHCI_LINK_FSTN: 699 printf("FSTN"); 700 break; 701 } 702 } 703 printf(">"); 704 } 705 } 706 707 static void 708 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 709 { 710 uint32_t s; 711 712 printf(" next="); 713 ehci_dump_link(sc, qtd->qtd_next, 0); 714 printf(" altnext="); 715 ehci_dump_link(sc, qtd->qtd_altnext, 0); 716 printf("\n"); 717 s = hc32toh(sc, qtd->qtd_status); 718 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 719 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 720 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 721 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 722 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 723 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 724 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 725 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 726 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 727 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 728 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 729 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 730 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 731 732 for (s = 0; s < 5; s++) { 733 printf(" buffer[%d]=0x%08x\n", s, 734 hc32toh(sc, qtd->qtd_buffer[s])); 735 } 736 for (s = 0; s < 5; s++) { 737 printf(" buffer_hi[%d]=0x%08x\n", s, 738 hc32toh(sc, qtd->qtd_buffer_hi[s])); 739 } 740 } 741 742 static uint8_t 743 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 744 { 745 uint8_t temp; 746 747 usb_pc_cpu_invalidate(sqtd->page_cache); 748 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 749 ehci_dump_qtd(sc, sqtd); 750 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 751 return (temp); 752 } 753 754 static void 755 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 756 { 757 uint16_t i; 758 uint8_t stop; 759 760 stop = 0; 761 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 762 stop = ehci_dump_sqtd(sc, sqtd); 763 } 764 if (sqtd) { 765 printf("dump aborted, too many TDs\n"); 766 } 767 } 768 769 static void 770 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 771 { 772 uint32_t endp; 773 uint32_t endphub; 774 775 usb_pc_cpu_invalidate(qh->page_cache); 776 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 777 printf(" link="); 778 ehci_dump_link(sc, qh->qh_link, 1); 779 printf("\n"); 780 endp = hc32toh(sc, qh->qh_endp); 781 printf(" endp=0x%08x\n", endp); 782 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 783 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 784 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 785 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 786 printf(" mpl=0x%x ctl=%d nrl=%d\n", 787 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 788 EHCI_QH_GET_NRL(endp)); 789 endphub = hc32toh(sc, qh->qh_endphub); 790 printf(" endphub=0x%08x\n", endphub); 791 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 792 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 793 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 794 EHCI_QH_GET_MULT(endphub)); 795 printf(" curqtd="); 796 ehci_dump_link(sc, qh->qh_curqtd, 0); 797 printf("\n"); 798 printf("Overlay qTD:\n"); 799 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 800 } 801 802 static void 803 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 804 { 805 usb_pc_cpu_invalidate(sitd->page_cache); 806 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 807 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 808 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 809 hc32toh(sc, sitd->sitd_portaddr), 810 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 811 ? "in" : "out", 812 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 813 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 814 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 815 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 816 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 817 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 818 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 819 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 820 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 821 hc32toh(sc, sitd->sitd_back), 822 hc32toh(sc, sitd->sitd_bp[0]), 823 hc32toh(sc, sitd->sitd_bp[1]), 824 hc32toh(sc, sitd->sitd_bp_hi[0]), 825 hc32toh(sc, sitd->sitd_bp_hi[1])); 826 } 827 828 static void 829 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 830 { 831 usb_pc_cpu_invalidate(itd->page_cache); 832 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 833 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 834 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 835 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 836 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 837 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 838 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 839 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 840 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 841 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 842 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 843 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 844 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 845 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 846 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 847 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 848 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 849 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 850 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 851 printf(" addr=0x%02x; endpt=0x%01x\n", 852 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 853 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 854 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 855 printf(" dir=%s; mpl=0x%02x\n", 856 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 857 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 858 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 859 hc32toh(sc, itd->itd_bp[2]), 860 hc32toh(sc, itd->itd_bp[3]), 861 hc32toh(sc, itd->itd_bp[4]), 862 hc32toh(sc, itd->itd_bp[5]), 863 hc32toh(sc, itd->itd_bp[6])); 864 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 865 " 0x%08x,0x%08x,0x%08x\n", 866 hc32toh(sc, itd->itd_bp_hi[0]), 867 hc32toh(sc, itd->itd_bp_hi[1]), 868 hc32toh(sc, itd->itd_bp_hi[2]), 869 hc32toh(sc, itd->itd_bp_hi[3]), 870 hc32toh(sc, itd->itd_bp_hi[4]), 871 hc32toh(sc, itd->itd_bp_hi[5]), 872 hc32toh(sc, itd->itd_bp_hi[6])); 873 } 874 875 static void 876 ehci_dump_isoc(ehci_softc_t *sc) 877 { 878 ehci_itd_t *itd; 879 ehci_sitd_t *sitd; 880 uint16_t max = 1000; 881 uint16_t pos; 882 883 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 884 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 885 886 printf("%s: isochronous dump from frame 0x%03x:\n", 887 __FUNCTION__, pos); 888 889 itd = sc->sc_isoc_hs_p_last[pos]; 890 sitd = sc->sc_isoc_fs_p_last[pos]; 891 892 while (itd && max && max--) { 893 ehci_dump_itd(sc, itd); 894 itd = itd->prev; 895 } 896 897 while (sitd && max && max--) { 898 ehci_dump_sitd(sc, sitd); 899 sitd = sitd->prev; 900 } 901 } 902 903 #endif 904 905 static void 906 ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 907 { 908 /* check for early completion */ 909 if (ehci_check_transfer(xfer)) { 910 return; 911 } 912 /* put transfer on interrupt queue */ 913 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 914 915 /* start timeout, if any */ 916 if (xfer->timeout != 0) { 917 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 918 } 919 } 920 921 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 922 static ehci_sitd_t * 923 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 924 { 925 DPRINTFN(11, "%p to %p\n", std, last); 926 927 /* (sc->sc_bus.mtx) must be locked */ 928 929 std->next = last->next; 930 std->sitd_next = last->sitd_next; 931 932 std->prev = last; 933 934 usb_pc_cpu_flush(std->page_cache); 935 936 /* 937 * the last->next->prev is never followed: std->next->prev = std; 938 */ 939 last->next = std; 940 last->sitd_next = std->sitd_self; 941 942 usb_pc_cpu_flush(last->page_cache); 943 944 return (std); 945 } 946 947 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 948 static ehci_itd_t * 949 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 950 { 951 DPRINTFN(11, "%p to %p\n", std, last); 952 953 /* (sc->sc_bus.mtx) must be locked */ 954 955 std->next = last->next; 956 std->itd_next = last->itd_next; 957 958 std->prev = last; 959 960 usb_pc_cpu_flush(std->page_cache); 961 962 /* 963 * the last->next->prev is never followed: std->next->prev = std; 964 */ 965 last->next = std; 966 last->itd_next = std->itd_self; 967 968 usb_pc_cpu_flush(last->page_cache); 969 970 return (std); 971 } 972 973 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 974 static ehci_qh_t * 975 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 976 { 977 DPRINTFN(11, "%p to %p\n", sqh, last); 978 979 if (sqh->prev != NULL) { 980 /* should not happen */ 981 DPRINTFN(0, "QH already linked!\n"); 982 return (last); 983 } 984 /* (sc->sc_bus.mtx) must be locked */ 985 986 sqh->next = last->next; 987 sqh->qh_link = last->qh_link; 988 989 sqh->prev = last; 990 991 usb_pc_cpu_flush(sqh->page_cache); 992 993 /* 994 * the last->next->prev is never followed: sqh->next->prev = sqh; 995 */ 996 997 last->next = sqh; 998 last->qh_link = sqh->qh_self; 999 1000 usb_pc_cpu_flush(last->page_cache); 1001 1002 return (sqh); 1003 } 1004 1005 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1006 static ehci_sitd_t * 1007 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1008 { 1009 DPRINTFN(11, "%p from %p\n", std, last); 1010 1011 /* (sc->sc_bus.mtx) must be locked */ 1012 1013 std->prev->next = std->next; 1014 std->prev->sitd_next = std->sitd_next; 1015 1016 usb_pc_cpu_flush(std->prev->page_cache); 1017 1018 if (std->next) { 1019 std->next->prev = std->prev; 1020 usb_pc_cpu_flush(std->next->page_cache); 1021 } 1022 return ((last == std) ? std->prev : last); 1023 } 1024 1025 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1026 static ehci_itd_t * 1027 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1028 { 1029 DPRINTFN(11, "%p from %p\n", std, last); 1030 1031 /* (sc->sc_bus.mtx) must be locked */ 1032 1033 std->prev->next = std->next; 1034 std->prev->itd_next = std->itd_next; 1035 1036 usb_pc_cpu_flush(std->prev->page_cache); 1037 1038 if (std->next) { 1039 std->next->prev = std->prev; 1040 usb_pc_cpu_flush(std->next->page_cache); 1041 } 1042 return ((last == std) ? std->prev : last); 1043 } 1044 1045 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1046 static ehci_qh_t * 1047 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1048 { 1049 DPRINTFN(11, "%p from %p\n", sqh, last); 1050 1051 /* (sc->sc_bus.mtx) must be locked */ 1052 1053 /* only remove if not removed from a queue */ 1054 if (sqh->prev) { 1055 1056 sqh->prev->next = sqh->next; 1057 sqh->prev->qh_link = sqh->qh_link; 1058 1059 usb_pc_cpu_flush(sqh->prev->page_cache); 1060 1061 if (sqh->next) { 1062 sqh->next->prev = sqh->prev; 1063 usb_pc_cpu_flush(sqh->next->page_cache); 1064 } 1065 last = ((last == sqh) ? sqh->prev : last); 1066 1067 sqh->prev = 0; 1068 1069 usb_pc_cpu_flush(sqh->page_cache); 1070 } 1071 return (last); 1072 } 1073 1074 static void 1075 ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen) 1076 { 1077 uint16_t rem; 1078 uint8_t dt; 1079 1080 /* count number of full packets */ 1081 dt = (actlen / xfer->max_packet_size) & 1; 1082 1083 /* compute remainder */ 1084 rem = actlen % xfer->max_packet_size; 1085 1086 if (rem > 0) 1087 dt ^= 1; /* short packet at the end */ 1088 else if (actlen != xlen) 1089 dt ^= 1; /* zero length packet at the end */ 1090 else if (xlen == 0) 1091 dt ^= 1; /* zero length transfer */ 1092 1093 xfer->endpoint->toggle_next ^= dt; 1094 } 1095 1096 static usb_error_t 1097 ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1098 { 1099 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1100 ehci_qtd_t *td; 1101 ehci_qtd_t *td_alt_next; 1102 uint32_t status; 1103 uint16_t len; 1104 1105 td = xfer->td_transfer_cache; 1106 td_alt_next = td->alt_next; 1107 1108 if (xfer->aframes != xfer->nframes) { 1109 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1110 } 1111 while (1) { 1112 1113 usb_pc_cpu_invalidate(td->page_cache); 1114 status = hc32toh(sc, td->qtd_status); 1115 1116 len = EHCI_QTD_GET_BYTES(status); 1117 1118 /* 1119 * Verify the status length and 1120 * add the length to "frlengths[]": 1121 */ 1122 if (len > td->len) { 1123 /* should not happen */ 1124 DPRINTF("Invalid status length, " 1125 "0x%04x/0x%04x bytes\n", len, td->len); 1126 status |= EHCI_QTD_HALTED; 1127 } else if (xfer->aframes != xfer->nframes) { 1128 xfer->frlengths[xfer->aframes] += td->len - len; 1129 /* manually update data toggle */ 1130 ehci_data_toggle_update(xfer, td->len - len, td->len); 1131 } 1132 1133 /* Check for last transfer */ 1134 if (((void *)td) == xfer->td_transfer_last) { 1135 td = NULL; 1136 break; 1137 } 1138 /* Check for transfer error */ 1139 if (status & EHCI_QTD_HALTED) { 1140 /* the transfer is finished */ 1141 td = NULL; 1142 break; 1143 } 1144 /* Check for short transfer */ 1145 if (len > 0) { 1146 if (xfer->flags_int.short_frames_ok) { 1147 /* follow alt next */ 1148 td = td->alt_next; 1149 } else { 1150 /* the transfer is finished */ 1151 td = NULL; 1152 } 1153 break; 1154 } 1155 td = td->obj_next; 1156 1157 if (td->alt_next != td_alt_next) { 1158 /* this USB frame is complete */ 1159 break; 1160 } 1161 } 1162 1163 /* update transfer cache */ 1164 1165 xfer->td_transfer_cache = td; 1166 1167 #ifdef USB_DEBUG 1168 if (status & EHCI_QTD_STATERRS) { 1169 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1170 "status=%s%s%s%s%s%s%s%s\n", 1171 xfer->address, xfer->endpointno, xfer->aframes, 1172 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1173 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1174 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1175 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1176 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1177 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1178 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1179 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1180 } 1181 #endif 1182 if (status & EHCI_QTD_HALTED) { 1183 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1184 (xfer->xroot->udev->address != 0)) { 1185 /* try to separate I/O errors from STALL */ 1186 if (EHCI_QTD_GET_CERR(status) == 0) 1187 return (USB_ERR_IOERROR); 1188 } 1189 return (USB_ERR_STALLED); 1190 } 1191 return (USB_ERR_NORMAL_COMPLETION); 1192 } 1193 1194 static void 1195 ehci_non_isoc_done(struct usb_xfer *xfer) 1196 { 1197 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1198 ehci_qh_t *qh; 1199 uint32_t status; 1200 usb_error_t err = 0; 1201 1202 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1203 xfer, xfer->endpoint); 1204 1205 #ifdef USB_DEBUG 1206 if (ehcidebug > 10) { 1207 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1208 1209 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1210 } 1211 #endif 1212 1213 /* extract data toggle directly from the QH's overlay area */ 1214 1215 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1216 1217 usb_pc_cpu_invalidate(qh->page_cache); 1218 1219 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1220 1221 /* reset scanner */ 1222 1223 xfer->td_transfer_cache = xfer->td_transfer_first; 1224 1225 if (xfer->flags_int.control_xfr) { 1226 1227 if (xfer->flags_int.control_hdr) { 1228 1229 err = ehci_non_isoc_done_sub(xfer); 1230 } 1231 xfer->aframes = 1; 1232 1233 if (xfer->td_transfer_cache == NULL) { 1234 goto done; 1235 } 1236 } 1237 while (xfer->aframes != xfer->nframes) { 1238 1239 err = ehci_non_isoc_done_sub(xfer); 1240 xfer->aframes++; 1241 1242 if (xfer->td_transfer_cache == NULL) { 1243 goto done; 1244 } 1245 } 1246 1247 if (xfer->flags_int.control_xfr && 1248 !xfer->flags_int.control_act) { 1249 1250 err = ehci_non_isoc_done_sub(xfer); 1251 } 1252 done: 1253 ehci_device_done(xfer, err); 1254 } 1255 1256 /*------------------------------------------------------------------------* 1257 * ehci_check_transfer 1258 * 1259 * Return values: 1260 * 0: USB transfer is not finished 1261 * Else: USB transfer is finished 1262 *------------------------------------------------------------------------*/ 1263 static uint8_t 1264 ehci_check_transfer(struct usb_xfer *xfer) 1265 { 1266 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1267 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1268 1269 uint32_t status; 1270 1271 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1272 1273 if (methods == &ehci_device_isoc_fs_methods) { 1274 ehci_sitd_t *td; 1275 1276 /* isochronous full speed transfer */ 1277 1278 td = xfer->td_transfer_last; 1279 usb_pc_cpu_invalidate(td->page_cache); 1280 status = hc32toh(sc, td->sitd_status); 1281 1282 /* also check if first is complete */ 1283 1284 td = xfer->td_transfer_first; 1285 usb_pc_cpu_invalidate(td->page_cache); 1286 status |= hc32toh(sc, td->sitd_status); 1287 1288 if (!(status & EHCI_SITD_ACTIVE)) { 1289 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1290 goto transferred; 1291 } 1292 } else if (methods == &ehci_device_isoc_hs_methods) { 1293 ehci_itd_t *td; 1294 1295 /* isochronous high speed transfer */ 1296 1297 /* check last transfer */ 1298 td = xfer->td_transfer_last; 1299 usb_pc_cpu_invalidate(td->page_cache); 1300 status = td->itd_status[0]; 1301 status |= td->itd_status[1]; 1302 status |= td->itd_status[2]; 1303 status |= td->itd_status[3]; 1304 status |= td->itd_status[4]; 1305 status |= td->itd_status[5]; 1306 status |= td->itd_status[6]; 1307 status |= td->itd_status[7]; 1308 1309 /* also check first transfer */ 1310 td = xfer->td_transfer_first; 1311 usb_pc_cpu_invalidate(td->page_cache); 1312 status |= td->itd_status[0]; 1313 status |= td->itd_status[1]; 1314 status |= td->itd_status[2]; 1315 status |= td->itd_status[3]; 1316 status |= td->itd_status[4]; 1317 status |= td->itd_status[5]; 1318 status |= td->itd_status[6]; 1319 status |= td->itd_status[7]; 1320 1321 /* if no transactions are active we continue */ 1322 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1323 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1324 goto transferred; 1325 } 1326 } else { 1327 ehci_qtd_t *td; 1328 ehci_qh_t *qh; 1329 1330 /* non-isochronous transfer */ 1331 1332 /* 1333 * check whether there is an error somewhere in the middle, 1334 * or whether there was a short packet (SPD and not ACTIVE) 1335 */ 1336 td = xfer->td_transfer_cache; 1337 1338 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1339 1340 usb_pc_cpu_invalidate(qh->page_cache); 1341 1342 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1343 if (status & EHCI_QTD_ACTIVE) { 1344 /* transfer is pending */ 1345 goto done; 1346 } 1347 1348 while (1) { 1349 usb_pc_cpu_invalidate(td->page_cache); 1350 status = hc32toh(sc, td->qtd_status); 1351 1352 /* 1353 * Check if there is an active TD which 1354 * indicates that the transfer isn't done. 1355 */ 1356 if (status & EHCI_QTD_ACTIVE) { 1357 /* update cache */ 1358 xfer->td_transfer_cache = td; 1359 goto done; 1360 } 1361 /* 1362 * last transfer descriptor makes the transfer done 1363 */ 1364 if (((void *)td) == xfer->td_transfer_last) { 1365 break; 1366 } 1367 /* 1368 * any kind of error makes the transfer done 1369 */ 1370 if (status & EHCI_QTD_HALTED) { 1371 break; 1372 } 1373 /* 1374 * if there is no alternate next transfer, a short 1375 * packet also makes the transfer done 1376 */ 1377 if (EHCI_QTD_GET_BYTES(status)) { 1378 if (xfer->flags_int.short_frames_ok) { 1379 /* follow alt next */ 1380 if (td->alt_next) { 1381 td = td->alt_next; 1382 continue; 1383 } 1384 } 1385 /* transfer is done */ 1386 break; 1387 } 1388 td = td->obj_next; 1389 } 1390 ehci_non_isoc_done(xfer); 1391 goto transferred; 1392 } 1393 1394 done: 1395 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1396 return (0); 1397 1398 transferred: 1399 return (1); 1400 } 1401 1402 static void 1403 ehci_pcd_enable(ehci_softc_t *sc) 1404 { 1405 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1406 1407 sc->sc_eintrs |= EHCI_STS_PCD; 1408 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1409 1410 /* acknowledge any PCD interrupt */ 1411 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1412 1413 ehci_root_intr(sc); 1414 } 1415 1416 static void 1417 ehci_interrupt_poll(ehci_softc_t *sc) 1418 { 1419 struct usb_xfer *xfer; 1420 1421 repeat: 1422 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1423 /* 1424 * check if transfer is transferred 1425 */ 1426 if (ehci_check_transfer(xfer)) { 1427 /* queue has been modified */ 1428 goto repeat; 1429 } 1430 } 1431 } 1432 1433 /* 1434 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1435 * writing back the qTD status, or miss signalling occasionally under 1436 * heavy load. If the host machine is too fast, we can miss 1437 * transaction completion - when we scan the active list the 1438 * transaction still seems to be active. This generally exhibits 1439 * itself as a umass stall that never recovers. 1440 * 1441 * We work around this behaviour by setting up this callback after any 1442 * softintr that completes with transactions still pending, giving us 1443 * another chance to check for completion after the writeback has 1444 * taken place. 1445 */ 1446 static void 1447 ehci_poll_timeout(void *arg) 1448 { 1449 ehci_softc_t *sc = arg; 1450 1451 DPRINTFN(3, "\n"); 1452 ehci_interrupt_poll(sc); 1453 } 1454 1455 /*------------------------------------------------------------------------* 1456 * ehci_interrupt - EHCI interrupt handler 1457 * 1458 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1459 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1460 * is present ! 1461 *------------------------------------------------------------------------*/ 1462 void 1463 ehci_interrupt(ehci_softc_t *sc) 1464 { 1465 uint32_t status; 1466 1467 USB_BUS_LOCK(&sc->sc_bus); 1468 1469 DPRINTFN(16, "real interrupt\n"); 1470 1471 #ifdef USB_DEBUG 1472 if (ehcidebug > 15) { 1473 ehci_dump_regs(sc); 1474 } 1475 #endif 1476 1477 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1478 if (status == 0) { 1479 /* the interrupt was not for us */ 1480 goto done; 1481 } 1482 if (!(status & sc->sc_eintrs)) { 1483 goto done; 1484 } 1485 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1486 1487 status &= sc->sc_eintrs; 1488 1489 if (status & EHCI_STS_HSE) { 1490 printf("%s: unrecoverable error, " 1491 "controller halted\n", __FUNCTION__); 1492 #ifdef USB_DEBUG 1493 ehci_dump_regs(sc); 1494 ehci_dump_isoc(sc); 1495 #endif 1496 } 1497 if (status & EHCI_STS_PCD) { 1498 /* 1499 * Disable PCD interrupt for now, because it will be 1500 * on until the port has been reset. 1501 */ 1502 sc->sc_eintrs &= ~EHCI_STS_PCD; 1503 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1504 1505 ehci_root_intr(sc); 1506 1507 /* do not allow RHSC interrupts > 1 per second */ 1508 usb_callout_reset(&sc->sc_tmo_pcd, hz, 1509 (void *)&ehci_pcd_enable, sc); 1510 } 1511 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1512 1513 if (status != 0) { 1514 /* block unprocessed interrupts */ 1515 sc->sc_eintrs &= ~status; 1516 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1517 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1518 } 1519 /* poll all the USB transfers */ 1520 ehci_interrupt_poll(sc); 1521 1522 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1523 usb_callout_reset(&sc->sc_tmo_poll, hz / 128, 1524 (void *)&ehci_poll_timeout, sc); 1525 } 1526 1527 done: 1528 USB_BUS_UNLOCK(&sc->sc_bus); 1529 } 1530 1531 /* 1532 * called when a request does not complete 1533 */ 1534 static void 1535 ehci_timeout(void *arg) 1536 { 1537 struct usb_xfer *xfer = arg; 1538 1539 DPRINTF("xfer=%p\n", xfer); 1540 1541 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1542 1543 /* transfer is transferred */ 1544 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1545 } 1546 1547 static void 1548 ehci_do_poll(struct usb_bus *bus) 1549 { 1550 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1551 1552 USB_BUS_LOCK(&sc->sc_bus); 1553 ehci_interrupt_poll(sc); 1554 USB_BUS_UNLOCK(&sc->sc_bus); 1555 } 1556 1557 static void 1558 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1559 { 1560 struct usb_page_search buf_res; 1561 ehci_qtd_t *td; 1562 ehci_qtd_t *td_next; 1563 ehci_qtd_t *td_alt_next; 1564 uint32_t buf_offset; 1565 uint32_t average; 1566 uint32_t len_old; 1567 uint32_t terminate; 1568 uint32_t qtd_altnext; 1569 uint8_t shortpkt_old; 1570 uint8_t precompute; 1571 1572 terminate = temp->sc->sc_terminate_self; 1573 qtd_altnext = temp->sc->sc_terminate_self; 1574 td_alt_next = NULL; 1575 buf_offset = 0; 1576 shortpkt_old = temp->shortpkt; 1577 len_old = temp->len; 1578 precompute = 1; 1579 1580 restart: 1581 1582 td = temp->td; 1583 td_next = temp->td_next; 1584 1585 while (1) { 1586 1587 if (temp->len == 0) { 1588 1589 if (temp->shortpkt) { 1590 break; 1591 } 1592 /* send a Zero Length Packet, ZLP, last */ 1593 1594 temp->shortpkt = 1; 1595 average = 0; 1596 1597 } else { 1598 1599 average = temp->average; 1600 1601 if (temp->len < average) { 1602 if (temp->len % temp->max_frame_size) { 1603 temp->shortpkt = 1; 1604 } 1605 average = temp->len; 1606 } 1607 } 1608 1609 if (td_next == NULL) { 1610 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1611 } 1612 /* get next TD */ 1613 1614 td = td_next; 1615 td_next = td->obj_next; 1616 1617 /* check if we are pre-computing */ 1618 1619 if (precompute) { 1620 1621 /* update remaining length */ 1622 1623 temp->len -= average; 1624 1625 continue; 1626 } 1627 /* fill out current TD */ 1628 1629 td->qtd_status = 1630 temp->qtd_status | 1631 htohc32(temp->sc, EHCI_QTD_IOC | 1632 EHCI_QTD_SET_BYTES(average)); 1633 1634 if (average == 0) { 1635 1636 if (temp->auto_data_toggle == 0) { 1637 1638 /* update data toggle, ZLP case */ 1639 1640 temp->qtd_status ^= 1641 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1642 } 1643 td->len = 0; 1644 1645 /* properly reset reserved fields */ 1646 td->qtd_buffer[0] = 0; 1647 td->qtd_buffer[1] = 0; 1648 td->qtd_buffer[2] = 0; 1649 td->qtd_buffer[3] = 0; 1650 td->qtd_buffer[4] = 0; 1651 td->qtd_buffer_hi[0] = 0; 1652 td->qtd_buffer_hi[1] = 0; 1653 td->qtd_buffer_hi[2] = 0; 1654 td->qtd_buffer_hi[3] = 0; 1655 td->qtd_buffer_hi[4] = 0; 1656 } else { 1657 1658 uint8_t x; 1659 1660 if (temp->auto_data_toggle == 0) { 1661 1662 /* update data toggle */ 1663 1664 if (howmany(average, temp->max_frame_size) & 1) { 1665 temp->qtd_status ^= 1666 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1667 } 1668 } 1669 td->len = average; 1670 1671 /* update remaining length */ 1672 1673 temp->len -= average; 1674 1675 /* fill out buffer pointers */ 1676 1677 usbd_get_page(temp->pc, buf_offset, &buf_res); 1678 td->qtd_buffer[0] = 1679 htohc32(temp->sc, buf_res.physaddr); 1680 td->qtd_buffer_hi[0] = 0; 1681 1682 x = 1; 1683 1684 while (average > EHCI_PAGE_SIZE) { 1685 average -= EHCI_PAGE_SIZE; 1686 buf_offset += EHCI_PAGE_SIZE; 1687 usbd_get_page(temp->pc, buf_offset, &buf_res); 1688 td->qtd_buffer[x] = 1689 htohc32(temp->sc, 1690 buf_res.physaddr & (~0xFFF)); 1691 td->qtd_buffer_hi[x] = 0; 1692 x++; 1693 } 1694 1695 /* 1696 * NOTE: The "average" variable is never zero after 1697 * exiting the loop above ! 1698 * 1699 * NOTE: We have to subtract one from the offset to 1700 * ensure that we are computing the physical address 1701 * of a valid page ! 1702 */ 1703 buf_offset += average; 1704 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1705 td->qtd_buffer[x] = 1706 htohc32(temp->sc, 1707 buf_res.physaddr & (~0xFFF)); 1708 td->qtd_buffer_hi[x] = 0; 1709 1710 /* properly reset reserved fields */ 1711 while (++x < EHCI_QTD_NBUFFERS) { 1712 td->qtd_buffer[x] = 0; 1713 td->qtd_buffer_hi[x] = 0; 1714 } 1715 } 1716 1717 if (td_next) { 1718 /* link the current TD with the next one */ 1719 td->qtd_next = td_next->qtd_self; 1720 } 1721 td->qtd_altnext = qtd_altnext; 1722 td->alt_next = td_alt_next; 1723 1724 usb_pc_cpu_flush(td->page_cache); 1725 } 1726 1727 if (precompute) { 1728 precompute = 0; 1729 1730 /* setup alt next pointer, if any */ 1731 if (temp->last_frame) { 1732 td_alt_next = NULL; 1733 qtd_altnext = terminate; 1734 } else { 1735 /* we use this field internally */ 1736 td_alt_next = td_next; 1737 if (temp->setup_alt_next) { 1738 qtd_altnext = td_next->qtd_self; 1739 } else { 1740 qtd_altnext = terminate; 1741 } 1742 } 1743 1744 /* restore */ 1745 temp->shortpkt = shortpkt_old; 1746 temp->len = len_old; 1747 goto restart; 1748 } 1749 temp->td = td; 1750 temp->td_next = td_next; 1751 } 1752 1753 static void 1754 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1755 { 1756 struct ehci_std_temp temp; 1757 const struct usb_pipe_methods *methods; 1758 ehci_qh_t *qh; 1759 ehci_qtd_t *td; 1760 uint32_t qh_endp; 1761 uint32_t qh_endphub; 1762 uint32_t x; 1763 1764 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1765 xfer->address, UE_GET_ADDR(xfer->endpointno), 1766 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1767 1768 temp.average = xfer->max_hc_frame_size; 1769 temp.max_frame_size = xfer->max_frame_size; 1770 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1771 1772 /* toggle the DMA set we are using */ 1773 xfer->flags_int.curr_dma_set ^= 1; 1774 1775 /* get next DMA set */ 1776 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1777 1778 xfer->td_transfer_first = td; 1779 xfer->td_transfer_cache = td; 1780 1781 temp.td = NULL; 1782 temp.td_next = td; 1783 temp.qtd_status = 0; 1784 temp.last_frame = 0; 1785 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1786 1787 if (xfer->flags_int.control_xfr) { 1788 if (xfer->endpoint->toggle_next) { 1789 /* DATA1 is next */ 1790 temp.qtd_status |= 1791 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1792 } 1793 temp.auto_data_toggle = 0; 1794 } else { 1795 temp.auto_data_toggle = 1; 1796 } 1797 1798 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1799 (xfer->xroot->udev->address != 0)) { 1800 /* max 3 retries */ 1801 temp.qtd_status |= 1802 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1803 } 1804 /* check if we should prepend a setup message */ 1805 1806 if (xfer->flags_int.control_xfr) { 1807 if (xfer->flags_int.control_hdr) { 1808 1809 xfer->endpoint->toggle_next = 0; 1810 1811 temp.qtd_status &= 1812 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1813 temp.qtd_status |= htohc32(temp.sc, 1814 EHCI_QTD_ACTIVE | 1815 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1816 EHCI_QTD_SET_TOGGLE(0)); 1817 1818 temp.len = xfer->frlengths[0]; 1819 temp.pc = xfer->frbuffers + 0; 1820 temp.shortpkt = temp.len ? 1 : 0; 1821 /* check for last frame */ 1822 if (xfer->nframes == 1) { 1823 /* no STATUS stage yet, SETUP is last */ 1824 if (xfer->flags_int.control_act) { 1825 temp.last_frame = 1; 1826 temp.setup_alt_next = 0; 1827 } 1828 } 1829 ehci_setup_standard_chain_sub(&temp); 1830 } 1831 x = 1; 1832 } else { 1833 x = 0; 1834 } 1835 1836 while (x != xfer->nframes) { 1837 1838 /* DATA0 / DATA1 message */ 1839 1840 temp.len = xfer->frlengths[x]; 1841 temp.pc = xfer->frbuffers + x; 1842 1843 x++; 1844 1845 if (x == xfer->nframes) { 1846 if (xfer->flags_int.control_xfr) { 1847 /* no STATUS stage yet, DATA is last */ 1848 if (xfer->flags_int.control_act) { 1849 temp.last_frame = 1; 1850 temp.setup_alt_next = 0; 1851 } 1852 } else { 1853 temp.last_frame = 1; 1854 temp.setup_alt_next = 0; 1855 } 1856 } 1857 /* keep previous data toggle and error count */ 1858 1859 temp.qtd_status &= 1860 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1861 EHCI_QTD_SET_TOGGLE(1)); 1862 1863 if (temp.len == 0) { 1864 1865 /* make sure that we send an USB packet */ 1866 1867 temp.shortpkt = 0; 1868 1869 } else { 1870 1871 /* regular data transfer */ 1872 1873 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1874 } 1875 1876 /* set endpoint direction */ 1877 1878 temp.qtd_status |= 1879 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1880 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1881 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1882 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1883 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1884 1885 ehci_setup_standard_chain_sub(&temp); 1886 } 1887 1888 /* check if we should append a status stage */ 1889 1890 if (xfer->flags_int.control_xfr && 1891 !xfer->flags_int.control_act) { 1892 1893 /* 1894 * Send a DATA1 message and invert the current endpoint 1895 * direction. 1896 */ 1897 1898 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1899 EHCI_QTD_SET_TOGGLE(1)); 1900 temp.qtd_status |= 1901 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1902 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1903 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1904 EHCI_QTD_SET_TOGGLE(1)) : 1905 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1906 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1907 EHCI_QTD_SET_TOGGLE(1)); 1908 1909 temp.len = 0; 1910 temp.pc = NULL; 1911 temp.shortpkt = 0; 1912 temp.last_frame = 1; 1913 temp.setup_alt_next = 0; 1914 1915 ehci_setup_standard_chain_sub(&temp); 1916 } 1917 td = temp.td; 1918 1919 /* the last TD terminates the transfer: */ 1920 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1921 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1922 1923 usb_pc_cpu_flush(td->page_cache); 1924 1925 /* must have at least one frame! */ 1926 1927 xfer->td_transfer_last = td; 1928 1929 #ifdef USB_DEBUG 1930 if (ehcidebug > 8) { 1931 DPRINTF("nexttog=%d; data before transfer:\n", 1932 xfer->endpoint->toggle_next); 1933 ehci_dump_sqtds(temp.sc, 1934 xfer->td_transfer_first); 1935 } 1936 #endif 1937 1938 methods = xfer->endpoint->methods; 1939 1940 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1941 1942 /* the "qh_link" field is filled when the QH is added */ 1943 1944 qh_endp = 1945 (EHCI_QH_SET_ADDR(xfer->address) | 1946 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 1947 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1948 1949 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1950 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 1951 if (methods != &ehci_device_intr_methods) 1952 qh_endp |= EHCI_QH_SET_NRL(8); 1953 } else { 1954 1955 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1956 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 1957 } else { 1958 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 1959 } 1960 1961 if (methods == &ehci_device_ctrl_methods) { 1962 qh_endp |= EHCI_QH_CTL; 1963 } 1964 if (methods != &ehci_device_intr_methods) { 1965 /* Only try one time per microframe! */ 1966 qh_endp |= EHCI_QH_SET_NRL(1); 1967 } 1968 } 1969 1970 if (temp.auto_data_toggle == 0) { 1971 /* software computes the data toggle */ 1972 qh_endp |= EHCI_QH_DTC; 1973 } 1974 1975 qh->qh_endp = htohc32(temp.sc, qh_endp); 1976 1977 qh_endphub = 1978 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1979 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 1980 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 1981 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1982 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1983 1984 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 1985 qh->qh_curqtd = 0; 1986 1987 /* fill the overlay qTD */ 1988 1989 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 1990 /* DATA1 is next */ 1991 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1992 } else { 1993 qh->qh_qtd.qtd_status = 0; 1994 } 1995 1996 td = xfer->td_transfer_first; 1997 1998 qh->qh_qtd.qtd_next = td->qtd_self; 1999 qh->qh_qtd.qtd_altnext = 2000 htohc32(temp.sc, EHCI_LINK_TERMINATE); 2001 2002 /* properly reset reserved fields */ 2003 qh->qh_qtd.qtd_buffer[0] = 0; 2004 qh->qh_qtd.qtd_buffer[1] = 0; 2005 qh->qh_qtd.qtd_buffer[2] = 0; 2006 qh->qh_qtd.qtd_buffer[3] = 0; 2007 qh->qh_qtd.qtd_buffer[4] = 0; 2008 qh->qh_qtd.qtd_buffer_hi[0] = 0; 2009 qh->qh_qtd.qtd_buffer_hi[1] = 0; 2010 qh->qh_qtd.qtd_buffer_hi[2] = 0; 2011 qh->qh_qtd.qtd_buffer_hi[3] = 0; 2012 qh->qh_qtd.qtd_buffer_hi[4] = 0; 2013 2014 usb_pc_cpu_flush(qh->page_cache); 2015 2016 if (xfer->xroot->udev->flags.self_suspended == 0) { 2017 EHCI_APPEND_QH(qh, *qh_last); 2018 } 2019 } 2020 2021 static void 2022 ehci_root_intr(ehci_softc_t *sc) 2023 { 2024 uint16_t i; 2025 uint16_t m; 2026 2027 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2028 2029 /* clear any old interrupt data */ 2030 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2031 2032 /* set bits */ 2033 m = (sc->sc_noport + 1); 2034 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2035 m = (8 * sizeof(sc->sc_hub_idata)); 2036 } 2037 for (i = 1; i < m; i++) { 2038 /* pick out CHANGE bits from the status register */ 2039 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2040 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2041 DPRINTF("port %d changed\n", i); 2042 } 2043 } 2044 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2045 sizeof(sc->sc_hub_idata)); 2046 } 2047 2048 static void 2049 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2050 { 2051 uint32_t nframes = xfer->nframes; 2052 uint32_t status; 2053 uint32_t *plen = xfer->frlengths; 2054 uint16_t len = 0; 2055 ehci_sitd_t *td = xfer->td_transfer_first; 2056 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2057 2058 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2059 xfer, xfer->endpoint); 2060 2061 while (nframes--) { 2062 if (td == NULL) { 2063 panic("%s:%d: out of TD's\n", 2064 __FUNCTION__, __LINE__); 2065 } 2066 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2067 pp_last = &sc->sc_isoc_fs_p_last[0]; 2068 } 2069 #ifdef USB_DEBUG 2070 if (ehcidebug > 15) { 2071 DPRINTF("isoc FS-TD\n"); 2072 ehci_dump_sitd(sc, td); 2073 } 2074 #endif 2075 usb_pc_cpu_invalidate(td->page_cache); 2076 status = hc32toh(sc, td->sitd_status); 2077 2078 len = EHCI_SITD_GET_LEN(status); 2079 2080 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2081 2082 if (*plen >= len) { 2083 len = *plen - len; 2084 } else { 2085 len = 0; 2086 } 2087 2088 *plen = len; 2089 2090 /* remove FS-TD from schedule */ 2091 EHCI_REMOVE_FS_TD(td, *pp_last); 2092 2093 pp_last++; 2094 plen++; 2095 td = td->obj_next; 2096 } 2097 2098 xfer->aframes = xfer->nframes; 2099 } 2100 2101 static void 2102 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2103 { 2104 uint32_t nframes = xfer->nframes; 2105 uint32_t status; 2106 uint32_t *plen = xfer->frlengths; 2107 uint16_t len = 0; 2108 uint8_t td_no = 0; 2109 ehci_itd_t *td = xfer->td_transfer_first; 2110 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2111 2112 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2113 xfer, xfer->endpoint); 2114 2115 while (nframes) { 2116 if (td == NULL) { 2117 panic("%s:%d: out of TD's\n", 2118 __FUNCTION__, __LINE__); 2119 } 2120 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2121 pp_last = &sc->sc_isoc_hs_p_last[0]; 2122 } 2123 #ifdef USB_DEBUG 2124 if (ehcidebug > 15) { 2125 DPRINTF("isoc HS-TD\n"); 2126 ehci_dump_itd(sc, td); 2127 } 2128 #endif 2129 2130 usb_pc_cpu_invalidate(td->page_cache); 2131 status = hc32toh(sc, td->itd_status[td_no]); 2132 2133 len = EHCI_ITD_GET_LEN(status); 2134 2135 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2136 2137 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2138 2139 if (*plen >= len) { 2140 /* 2141 * The length is valid. NOTE: The 2142 * complete length is written back 2143 * into the status field, and not the 2144 * remainder like with other transfer 2145 * descriptor types. 2146 */ 2147 } else { 2148 /* Invalid length - truncate */ 2149 len = 0; 2150 } 2151 2152 *plen = len; 2153 plen++; 2154 nframes--; 2155 } 2156 2157 td_no++; 2158 2159 if ((td_no == 8) || (nframes == 0)) { 2160 /* remove HS-TD from schedule */ 2161 EHCI_REMOVE_HS_TD(td, *pp_last); 2162 pp_last++; 2163 2164 td_no = 0; 2165 td = td->obj_next; 2166 } 2167 } 2168 xfer->aframes = xfer->nframes; 2169 } 2170 2171 /* NOTE: "done" can be run two times in a row, 2172 * from close and from interrupt 2173 */ 2174 static void 2175 ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2176 { 2177 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 2178 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2179 2180 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2181 2182 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2183 xfer, xfer->endpoint, error); 2184 2185 if ((methods == &ehci_device_bulk_methods) || 2186 (methods == &ehci_device_ctrl_methods)) { 2187 #ifdef USB_DEBUG 2188 if (ehcidebug > 8) { 2189 DPRINTF("nexttog=%d; data after transfer:\n", 2190 xfer->endpoint->toggle_next); 2191 ehci_dump_sqtds(sc, 2192 xfer->td_transfer_first); 2193 } 2194 #endif 2195 2196 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2197 sc->sc_async_p_last); 2198 } 2199 if (methods == &ehci_device_intr_methods) { 2200 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2201 sc->sc_intr_p_last[xfer->qh_pos]); 2202 } 2203 /* 2204 * Only finish isochronous transfers once which will update 2205 * "xfer->frlengths". 2206 */ 2207 if (xfer->td_transfer_first && 2208 xfer->td_transfer_last) { 2209 if (methods == &ehci_device_isoc_fs_methods) { 2210 ehci_isoc_fs_done(sc, xfer); 2211 } 2212 if (methods == &ehci_device_isoc_hs_methods) { 2213 ehci_isoc_hs_done(sc, xfer); 2214 } 2215 xfer->td_transfer_first = NULL; 2216 xfer->td_transfer_last = NULL; 2217 } 2218 /* dequeue transfer and start next transfer */ 2219 usbd_transfer_done(xfer, error); 2220 } 2221 2222 /*------------------------------------------------------------------------* 2223 * ehci bulk support 2224 *------------------------------------------------------------------------*/ 2225 static void 2226 ehci_device_bulk_open(struct usb_xfer *xfer) 2227 { 2228 return; 2229 } 2230 2231 static void 2232 ehci_device_bulk_close(struct usb_xfer *xfer) 2233 { 2234 ehci_device_done(xfer, USB_ERR_CANCELLED); 2235 } 2236 2237 static void 2238 ehci_device_bulk_enter(struct usb_xfer *xfer) 2239 { 2240 return; 2241 } 2242 2243 static void 2244 ehci_doorbell_async(struct ehci_softc *sc) 2245 { 2246 uint32_t temp; 2247 2248 /* 2249 * XXX Performance quirk: Some Host Controllers have a too low 2250 * interrupt rate. Issue an IAAD to stimulate the Host 2251 * Controller after queueing the BULK transfer. 2252 * 2253 * XXX Force the host controller to refresh any QH caches. 2254 */ 2255 temp = EOREAD4(sc, EHCI_USBCMD); 2256 if (!(temp & EHCI_CMD_IAAD)) 2257 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2258 } 2259 2260 static void 2261 ehci_device_bulk_start(struct usb_xfer *xfer) 2262 { 2263 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2264 2265 /* setup TD's and QH */ 2266 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2267 2268 /* put transfer on interrupt queue */ 2269 ehci_transfer_intr_enqueue(xfer); 2270 2271 /* 2272 * XXX Certain nVidia chipsets choke when using the IAAD 2273 * feature too frequently. 2274 */ 2275 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2276 return; 2277 2278 ehci_doorbell_async(sc); 2279 } 2280 2281 static const struct usb_pipe_methods ehci_device_bulk_methods = 2282 { 2283 .open = ehci_device_bulk_open, 2284 .close = ehci_device_bulk_close, 2285 .enter = ehci_device_bulk_enter, 2286 .start = ehci_device_bulk_start, 2287 }; 2288 2289 /*------------------------------------------------------------------------* 2290 * ehci control support 2291 *------------------------------------------------------------------------*/ 2292 static void 2293 ehci_device_ctrl_open(struct usb_xfer *xfer) 2294 { 2295 return; 2296 } 2297 2298 static void 2299 ehci_device_ctrl_close(struct usb_xfer *xfer) 2300 { 2301 ehci_device_done(xfer, USB_ERR_CANCELLED); 2302 } 2303 2304 static void 2305 ehci_device_ctrl_enter(struct usb_xfer *xfer) 2306 { 2307 return; 2308 } 2309 2310 static void 2311 ehci_device_ctrl_start(struct usb_xfer *xfer) 2312 { 2313 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2314 2315 /* setup TD's and QH */ 2316 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2317 2318 /* put transfer on interrupt queue */ 2319 ehci_transfer_intr_enqueue(xfer); 2320 } 2321 2322 static const struct usb_pipe_methods ehci_device_ctrl_methods = 2323 { 2324 .open = ehci_device_ctrl_open, 2325 .close = ehci_device_ctrl_close, 2326 .enter = ehci_device_ctrl_enter, 2327 .start = ehci_device_ctrl_start, 2328 }; 2329 2330 /*------------------------------------------------------------------------* 2331 * ehci interrupt support 2332 *------------------------------------------------------------------------*/ 2333 static void 2334 ehci_device_intr_open(struct usb_xfer *xfer) 2335 { 2336 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2337 uint16_t best; 2338 uint16_t bit; 2339 uint16_t x; 2340 2341 usb_hs_bandwidth_alloc(xfer); 2342 2343 /* 2344 * Find the best QH position corresponding to the given interval: 2345 */ 2346 2347 best = 0; 2348 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2349 while (bit) { 2350 if (xfer->interval >= bit) { 2351 x = bit; 2352 best = bit; 2353 while (x & bit) { 2354 if (sc->sc_intr_stat[x] < 2355 sc->sc_intr_stat[best]) { 2356 best = x; 2357 } 2358 x++; 2359 } 2360 break; 2361 } 2362 bit >>= 1; 2363 } 2364 2365 sc->sc_intr_stat[best]++; 2366 xfer->qh_pos = best; 2367 2368 DPRINTFN(3, "best=%d interval=%d\n", 2369 best, xfer->interval); 2370 } 2371 2372 static void 2373 ehci_device_intr_close(struct usb_xfer *xfer) 2374 { 2375 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2376 2377 sc->sc_intr_stat[xfer->qh_pos]--; 2378 2379 ehci_device_done(xfer, USB_ERR_CANCELLED); 2380 2381 /* bandwidth must be freed after device done */ 2382 usb_hs_bandwidth_free(xfer); 2383 } 2384 2385 static void 2386 ehci_device_intr_enter(struct usb_xfer *xfer) 2387 { 2388 return; 2389 } 2390 2391 static void 2392 ehci_device_intr_start(struct usb_xfer *xfer) 2393 { 2394 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2395 2396 /* setup TD's and QH */ 2397 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2398 2399 /* put transfer on interrupt queue */ 2400 ehci_transfer_intr_enqueue(xfer); 2401 } 2402 2403 static const struct usb_pipe_methods ehci_device_intr_methods = 2404 { 2405 .open = ehci_device_intr_open, 2406 .close = ehci_device_intr_close, 2407 .enter = ehci_device_intr_enter, 2408 .start = ehci_device_intr_start, 2409 }; 2410 2411 /*------------------------------------------------------------------------* 2412 * ehci full speed isochronous support 2413 *------------------------------------------------------------------------*/ 2414 static void 2415 ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2416 { 2417 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2418 ehci_sitd_t *td; 2419 uint32_t sitd_portaddr; 2420 uint8_t ds; 2421 2422 sitd_portaddr = 2423 EHCI_SITD_SET_ADDR(xfer->address) | 2424 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2425 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2426 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2427 2428 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2429 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2430 2431 sitd_portaddr = htohc32(sc, sitd_portaddr); 2432 2433 /* initialize all TD's */ 2434 2435 for (ds = 0; ds != 2; ds++) { 2436 2437 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2438 2439 td->sitd_portaddr = sitd_portaddr; 2440 2441 /* 2442 * TODO: make some kind of automatic 2443 * SMASK/CMASK selection based on micro-frame 2444 * usage 2445 * 2446 * micro-frame usage (8 microframes per 1ms) 2447 */ 2448 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2449 2450 usb_pc_cpu_flush(td->page_cache); 2451 } 2452 } 2453 } 2454 2455 static void 2456 ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2457 { 2458 ehci_device_done(xfer, USB_ERR_CANCELLED); 2459 } 2460 2461 static void 2462 ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2463 { 2464 struct usb_page_search buf_res; 2465 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2466 ehci_sitd_t *td; 2467 ehci_sitd_t *td_last = NULL; 2468 ehci_sitd_t **pp_last; 2469 uint32_t *plen; 2470 uint32_t buf_offset; 2471 uint32_t nframes; 2472 uint32_t temp; 2473 uint32_t sitd_mask; 2474 uint16_t tlen; 2475 uint8_t sa; 2476 uint8_t sb; 2477 2478 #ifdef USB_DEBUG 2479 uint8_t once = 1; 2480 2481 #endif 2482 2483 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2484 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2485 2486 /* get the current frame index */ 2487 2488 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2489 2490 /* 2491 * check if the frame index is within the window where the frames 2492 * will be inserted 2493 */ 2494 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2495 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2496 2497 if ((xfer->endpoint->is_synced == 0) || 2498 (buf_offset < xfer->nframes)) { 2499 /* 2500 * If there is data underflow or the pipe queue is empty we 2501 * schedule the transfer a few frames ahead of the current 2502 * frame position. Else two isochronous transfers might 2503 * overlap. 2504 */ 2505 xfer->endpoint->isoc_next = (nframes + 3) & 2506 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2507 xfer->endpoint->is_synced = 1; 2508 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2509 } 2510 /* 2511 * compute how many milliseconds the insertion is ahead of the 2512 * current frame position: 2513 */ 2514 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2515 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2516 2517 /* 2518 * pre-compute when the isochronous transfer will be finished: 2519 */ 2520 xfer->isoc_time_complete = 2521 usb_isoc_time_expand(&sc->sc_bus, nframes) + 2522 buf_offset + xfer->nframes; 2523 2524 /* get the real number of frames */ 2525 2526 nframes = xfer->nframes; 2527 2528 buf_offset = 0; 2529 2530 plen = xfer->frlengths; 2531 2532 /* toggle the DMA set we are using */ 2533 xfer->flags_int.curr_dma_set ^= 1; 2534 2535 /* get next DMA set */ 2536 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2537 xfer->td_transfer_first = td; 2538 2539 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2540 2541 /* store starting position */ 2542 2543 xfer->qh_pos = xfer->endpoint->isoc_next; 2544 2545 while (nframes--) { 2546 if (td == NULL) { 2547 panic("%s:%d: out of TD's\n", 2548 __FUNCTION__, __LINE__); 2549 } 2550 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) 2551 pp_last = &sc->sc_isoc_fs_p_last[0]; 2552 2553 /* reuse sitd_portaddr and sitd_back from last transfer */ 2554 2555 if (*plen > xfer->max_frame_size) { 2556 #ifdef USB_DEBUG 2557 if (once) { 2558 once = 0; 2559 printf("%s: frame length(%d) exceeds %d " 2560 "bytes (frame truncated)\n", 2561 __FUNCTION__, *plen, 2562 xfer->max_frame_size); 2563 } 2564 #endif 2565 *plen = xfer->max_frame_size; 2566 } 2567 2568 /* allocate a slot */ 2569 2570 sa = usbd_fs_isoc_schedule_alloc_slot(xfer, 2571 xfer->isoc_time_complete - nframes - 1); 2572 2573 if (sa == 255) { 2574 /* 2575 * Schedule is FULL, set length to zero: 2576 */ 2577 2578 *plen = 0; 2579 sa = USB_FS_ISOC_UFRAME_MAX - 1; 2580 } 2581 if (*plen) { 2582 /* 2583 * only call "usbd_get_page()" when we have a 2584 * non-zero length 2585 */ 2586 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2587 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2588 buf_offset += *plen; 2589 /* 2590 * NOTE: We need to subtract one from the offset so 2591 * that we are on a valid page! 2592 */ 2593 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2594 &buf_res); 2595 temp = buf_res.physaddr & ~0xFFF; 2596 } else { 2597 td->sitd_bp[0] = 0; 2598 temp = 0; 2599 } 2600 2601 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2602 tlen = *plen; 2603 if (tlen <= 188) { 2604 temp |= 1; /* T-count = 1, TP = ALL */ 2605 tlen = 1; 2606 } else { 2607 tlen += 187; 2608 tlen /= 188; 2609 temp |= tlen; /* T-count = [1..6] */ 2610 temp |= 8; /* TP = Begin */ 2611 } 2612 2613 tlen += sa; 2614 2615 if (tlen >= 8) { 2616 sb = 0; 2617 } else { 2618 sb = (1 << tlen); 2619 } 2620 2621 sa = (1 << sa); 2622 sa = (sb - sa) & 0x3F; 2623 sb = 0; 2624 } else { 2625 sb = (-(4 << sa)) & 0xFE; 2626 sa = (1 << sa) & 0x3F; 2627 } 2628 2629 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2630 EHCI_SITD_SET_CMASK(sb)); 2631 2632 td->sitd_bp[1] = htohc32(sc, temp); 2633 2634 td->sitd_mask = htohc32(sc, sitd_mask); 2635 2636 if (nframes == 0) { 2637 td->sitd_status = htohc32(sc, 2638 EHCI_SITD_IOC | 2639 EHCI_SITD_ACTIVE | 2640 EHCI_SITD_SET_LEN(*plen)); 2641 } else { 2642 td->sitd_status = htohc32(sc, 2643 EHCI_SITD_ACTIVE | 2644 EHCI_SITD_SET_LEN(*plen)); 2645 } 2646 usb_pc_cpu_flush(td->page_cache); 2647 2648 #ifdef USB_DEBUG 2649 if (ehcidebug > 15) { 2650 DPRINTF("FS-TD %d\n", nframes); 2651 ehci_dump_sitd(sc, td); 2652 } 2653 #endif 2654 /* insert TD into schedule */ 2655 EHCI_APPEND_FS_TD(td, *pp_last); 2656 pp_last++; 2657 2658 plen++; 2659 td_last = td; 2660 td = td->obj_next; 2661 } 2662 2663 xfer->td_transfer_last = td_last; 2664 2665 /* update isoc_next */ 2666 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2667 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2668 2669 /* 2670 * We don't allow cancelling of the SPLIT transaction USB FULL 2671 * speed transfer, because it disturbs the bandwidth 2672 * computation algorithm. 2673 */ 2674 xfer->flags_int.can_cancel_immed = 0; 2675 } 2676 2677 static void 2678 ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2679 { 2680 /* 2681 * We don't allow cancelling of the SPLIT transaction USB FULL 2682 * speed transfer, because it disturbs the bandwidth 2683 * computation algorithm. 2684 */ 2685 xfer->flags_int.can_cancel_immed = 0; 2686 2687 /* set a default timeout */ 2688 if (xfer->timeout == 0) 2689 xfer->timeout = 500; /* ms */ 2690 2691 /* put transfer on interrupt queue */ 2692 ehci_transfer_intr_enqueue(xfer); 2693 } 2694 2695 static const struct usb_pipe_methods ehci_device_isoc_fs_methods = 2696 { 2697 .open = ehci_device_isoc_fs_open, 2698 .close = ehci_device_isoc_fs_close, 2699 .enter = ehci_device_isoc_fs_enter, 2700 .start = ehci_device_isoc_fs_start, 2701 }; 2702 2703 /*------------------------------------------------------------------------* 2704 * ehci high speed isochronous support 2705 *------------------------------------------------------------------------*/ 2706 static void 2707 ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2708 { 2709 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2710 ehci_itd_t *td; 2711 uint32_t temp; 2712 uint8_t ds; 2713 2714 usb_hs_bandwidth_alloc(xfer); 2715 2716 /* initialize all TD's */ 2717 2718 for (ds = 0; ds != 2; ds++) { 2719 2720 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2721 2722 /* set TD inactive */ 2723 td->itd_status[0] = 0; 2724 td->itd_status[1] = 0; 2725 td->itd_status[2] = 0; 2726 td->itd_status[3] = 0; 2727 td->itd_status[4] = 0; 2728 td->itd_status[5] = 0; 2729 td->itd_status[6] = 0; 2730 td->itd_status[7] = 0; 2731 2732 /* set endpoint and address */ 2733 td->itd_bp[0] = htohc32(sc, 2734 EHCI_ITD_SET_ADDR(xfer->address) | 2735 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2736 2737 temp = 2738 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2739 2740 /* set direction */ 2741 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2742 temp |= EHCI_ITD_SET_DIR_IN; 2743 } 2744 /* set maximum packet size */ 2745 td->itd_bp[1] = htohc32(sc, temp); 2746 2747 /* set transfer multiplier */ 2748 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2749 2750 usb_pc_cpu_flush(td->page_cache); 2751 } 2752 } 2753 } 2754 2755 static void 2756 ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2757 { 2758 ehci_device_done(xfer, USB_ERR_CANCELLED); 2759 2760 /* bandwidth must be freed after device done */ 2761 usb_hs_bandwidth_free(xfer); 2762 } 2763 2764 static void 2765 ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2766 { 2767 struct usb_page_search buf_res; 2768 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2769 ehci_itd_t *td; 2770 ehci_itd_t *td_last = NULL; 2771 ehci_itd_t **pp_last; 2772 bus_size_t page_addr; 2773 uint32_t *plen; 2774 uint32_t status; 2775 uint32_t buf_offset; 2776 uint32_t nframes; 2777 uint32_t itd_offset[8 + 1]; 2778 uint8_t x; 2779 uint8_t td_no; 2780 uint8_t page_no; 2781 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 2782 2783 #ifdef USB_DEBUG 2784 uint8_t once = 1; 2785 2786 #endif 2787 2788 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2789 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift); 2790 2791 /* get the current frame index */ 2792 2793 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2794 2795 /* 2796 * check if the frame index is within the window where the frames 2797 * will be inserted 2798 */ 2799 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2800 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2801 2802 if ((xfer->endpoint->is_synced == 0) || 2803 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) { 2804 /* 2805 * If there is data underflow or the pipe queue is empty we 2806 * schedule the transfer a few frames ahead of the current 2807 * frame position. Else two isochronous transfers might 2808 * overlap. 2809 */ 2810 xfer->endpoint->isoc_next = (nframes + 3) & 2811 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2812 xfer->endpoint->is_synced = 1; 2813 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2814 } 2815 /* 2816 * compute how many milliseconds the insertion is ahead of the 2817 * current frame position: 2818 */ 2819 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2820 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2821 2822 /* 2823 * pre-compute when the isochronous transfer will be finished: 2824 */ 2825 xfer->isoc_time_complete = 2826 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2827 (((xfer->nframes << shift) + 7) / 8); 2828 2829 /* get the real number of frames */ 2830 2831 nframes = xfer->nframes; 2832 2833 buf_offset = 0; 2834 td_no = 0; 2835 2836 plen = xfer->frlengths; 2837 2838 /* toggle the DMA set we are using */ 2839 xfer->flags_int.curr_dma_set ^= 1; 2840 2841 /* get next DMA set */ 2842 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2843 xfer->td_transfer_first = td; 2844 2845 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2846 2847 /* store starting position */ 2848 2849 xfer->qh_pos = xfer->endpoint->isoc_next; 2850 2851 while (nframes) { 2852 if (td == NULL) { 2853 panic("%s:%d: out of TD's\n", 2854 __FUNCTION__, __LINE__); 2855 } 2856 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2857 pp_last = &sc->sc_isoc_hs_p_last[0]; 2858 } 2859 /* range check */ 2860 if (*plen > xfer->max_frame_size) { 2861 #ifdef USB_DEBUG 2862 if (once) { 2863 once = 0; 2864 printf("%s: frame length(%d) exceeds %d bytes " 2865 "(frame truncated)\n", 2866 __FUNCTION__, *plen, xfer->max_frame_size); 2867 } 2868 #endif 2869 *plen = xfer->max_frame_size; 2870 } 2871 2872 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2873 status = (EHCI_ITD_SET_LEN(*plen) | 2874 EHCI_ITD_ACTIVE | 2875 EHCI_ITD_SET_PG(0)); 2876 td->itd_status[td_no] = htohc32(sc, status); 2877 itd_offset[td_no] = buf_offset; 2878 buf_offset += *plen; 2879 plen++; 2880 nframes --; 2881 } else { 2882 td->itd_status[td_no] = 0; /* not active */ 2883 itd_offset[td_no] = buf_offset; 2884 } 2885 2886 td_no++; 2887 2888 if ((td_no == 8) || (nframes == 0)) { 2889 2890 /* the rest of the transfers are not active, if any */ 2891 for (x = td_no; x != 8; x++) { 2892 td->itd_status[x] = 0; /* not active */ 2893 } 2894 2895 /* check if there is any data to be transferred */ 2896 if (itd_offset[0] != buf_offset) { 2897 page_no = 0; 2898 itd_offset[td_no] = buf_offset; 2899 2900 /* get first page offset */ 2901 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2902 /* get page address */ 2903 page_addr = buf_res.physaddr & ~0xFFF; 2904 /* update page address */ 2905 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2906 td->itd_bp[0] |= htohc32(sc, page_addr); 2907 2908 for (x = 0; x != td_no; x++) { 2909 /* set page number and page offset */ 2910 status = (EHCI_ITD_SET_PG(page_no) | 2911 (buf_res.physaddr & 0xFFF)); 2912 td->itd_status[x] |= htohc32(sc, status); 2913 2914 /* get next page offset */ 2915 if (itd_offset[x + 1] == buf_offset) { 2916 /* 2917 * We subtract one so that 2918 * we don't go off the last 2919 * page! 2920 */ 2921 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2922 } else { 2923 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2924 } 2925 2926 /* check if we need a new page */ 2927 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2928 /* new page needed */ 2929 page_addr = buf_res.physaddr & ~0xFFF; 2930 if (page_no == 6) { 2931 panic("%s: too many pages\n", __FUNCTION__); 2932 } 2933 page_no++; 2934 /* update page address */ 2935 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2936 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2937 } 2938 } 2939 } 2940 /* set IOC bit if we are complete */ 2941 if (nframes == 0) { 2942 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 2943 } 2944 usb_pc_cpu_flush(td->page_cache); 2945 #ifdef USB_DEBUG 2946 if (ehcidebug > 15) { 2947 DPRINTF("HS-TD %d\n", nframes); 2948 ehci_dump_itd(sc, td); 2949 } 2950 #endif 2951 /* insert TD into schedule */ 2952 EHCI_APPEND_HS_TD(td, *pp_last); 2953 pp_last++; 2954 2955 td_no = 0; 2956 td_last = td; 2957 td = td->obj_next; 2958 } 2959 } 2960 2961 xfer->td_transfer_last = td_last; 2962 2963 /* update isoc_next */ 2964 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2965 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2966 } 2967 2968 static void 2969 ehci_device_isoc_hs_start(struct usb_xfer *xfer) 2970 { 2971 /* put transfer on interrupt queue */ 2972 ehci_transfer_intr_enqueue(xfer); 2973 } 2974 2975 static const struct usb_pipe_methods ehci_device_isoc_hs_methods = 2976 { 2977 .open = ehci_device_isoc_hs_open, 2978 .close = ehci_device_isoc_hs_close, 2979 .enter = ehci_device_isoc_hs_enter, 2980 .start = ehci_device_isoc_hs_start, 2981 }; 2982 2983 /*------------------------------------------------------------------------* 2984 * ehci root control support 2985 *------------------------------------------------------------------------* 2986 * Simulate a hardware hub by handling all the necessary requests. 2987 *------------------------------------------------------------------------*/ 2988 2989 static const 2990 struct usb_device_descriptor ehci_devd = 2991 { 2992 sizeof(struct usb_device_descriptor), 2993 UDESC_DEVICE, /* type */ 2994 {0x00, 0x02}, /* USB version */ 2995 UDCLASS_HUB, /* class */ 2996 UDSUBCLASS_HUB, /* subclass */ 2997 UDPROTO_HSHUBSTT, /* protocol */ 2998 64, /* max packet */ 2999 {0}, {0}, {0x00, 0x01}, /* device id */ 3000 1, 2, 0, /* string indexes */ 3001 1 /* # of configurations */ 3002 }; 3003 3004 static const 3005 struct usb_device_qualifier ehci_odevd = 3006 { 3007 sizeof(struct usb_device_qualifier), 3008 UDESC_DEVICE_QUALIFIER, /* type */ 3009 {0x00, 0x02}, /* USB version */ 3010 UDCLASS_HUB, /* class */ 3011 UDSUBCLASS_HUB, /* subclass */ 3012 UDPROTO_FSHUB, /* protocol */ 3013 0, /* max packet */ 3014 0, /* # of configurations */ 3015 0 3016 }; 3017 3018 static const struct ehci_config_desc ehci_confd = { 3019 .confd = { 3020 .bLength = sizeof(struct usb_config_descriptor), 3021 .bDescriptorType = UDESC_CONFIG, 3022 .wTotalLength[0] = sizeof(ehci_confd), 3023 .bNumInterface = 1, 3024 .bConfigurationValue = 1, 3025 .iConfiguration = 0, 3026 .bmAttributes = UC_SELF_POWERED, 3027 .bMaxPower = 0 /* max power */ 3028 }, 3029 .ifcd = { 3030 .bLength = sizeof(struct usb_interface_descriptor), 3031 .bDescriptorType = UDESC_INTERFACE, 3032 .bNumEndpoints = 1, 3033 .bInterfaceClass = UICLASS_HUB, 3034 .bInterfaceSubClass = UISUBCLASS_HUB, 3035 .bInterfaceProtocol = 0, 3036 }, 3037 .endpd = { 3038 .bLength = sizeof(struct usb_endpoint_descriptor), 3039 .bDescriptorType = UDESC_ENDPOINT, 3040 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 3041 .bmAttributes = UE_INTERRUPT, 3042 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3043 .bInterval = 255, 3044 }, 3045 }; 3046 3047 static const 3048 struct usb_hub_descriptor ehci_hubd = 3049 { 3050 .bDescLength = 0, /* dynamic length */ 3051 .bDescriptorType = UDESC_HUB, 3052 }; 3053 3054 uint16_t 3055 ehci_get_port_speed_portsc(struct ehci_softc *sc, uint16_t index) 3056 { 3057 uint32_t v; 3058 3059 v = EOREAD4(sc, EHCI_PORTSC(index)); 3060 v = (v >> EHCI_PORTSC_PSPD_SHIFT) & EHCI_PORTSC_PSPD_MASK; 3061 3062 if (v == EHCI_PORT_SPEED_HIGH) 3063 return (UPS_HIGH_SPEED); 3064 if (v == EHCI_PORT_SPEED_LOW) 3065 return (UPS_LOW_SPEED); 3066 return (0); 3067 } 3068 3069 uint16_t 3070 ehci_get_port_speed_hostc(struct ehci_softc *sc, uint16_t index) 3071 { 3072 uint32_t v; 3073 3074 v = EOREAD4(sc, EHCI_HOSTC(index)); 3075 v = (v >> EHCI_HOSTC_PSPD_SHIFT) & EHCI_HOSTC_PSPD_MASK; 3076 3077 if (v == EHCI_PORT_SPEED_HIGH) 3078 return (UPS_HIGH_SPEED); 3079 if (v == EHCI_PORT_SPEED_LOW) 3080 return (UPS_LOW_SPEED); 3081 return (0); 3082 } 3083 3084 static void 3085 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3086 { 3087 uint32_t port; 3088 uint32_t v; 3089 3090 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3091 3092 port = EHCI_PORTSC(index); 3093 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3094 EOWRITE4(sc, port, v | EHCI_PS_PO); 3095 } 3096 3097 static usb_error_t 3098 ehci_roothub_exec(struct usb_device *udev, 3099 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3100 { 3101 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3102 const char *str_ptr; 3103 const void *ptr; 3104 uint32_t port; 3105 uint32_t v; 3106 uint16_t len; 3107 uint16_t i; 3108 uint16_t value; 3109 uint16_t index; 3110 usb_error_t err; 3111 3112 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3113 3114 /* buffer reset */ 3115 ptr = (const void *)&sc->sc_hub_desc; 3116 len = 0; 3117 err = 0; 3118 3119 value = UGETW(req->wValue); 3120 index = UGETW(req->wIndex); 3121 3122 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3123 "wValue=0x%04x wIndex=0x%04x\n", 3124 req->bmRequestType, req->bRequest, 3125 UGETW(req->wLength), value, index); 3126 3127 #define C(x,y) ((x) | ((y) << 8)) 3128 switch (C(req->bRequest, req->bmRequestType)) { 3129 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3130 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3131 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3132 /* 3133 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3134 * for the integrated root hub. 3135 */ 3136 break; 3137 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3138 len = 1; 3139 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3140 break; 3141 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3142 switch (value >> 8) { 3143 case UDESC_DEVICE: 3144 if ((value & 0xff) != 0) { 3145 err = USB_ERR_IOERROR; 3146 goto done; 3147 } 3148 len = sizeof(ehci_devd); 3149 ptr = (const void *)&ehci_devd; 3150 break; 3151 /* 3152 * We can't really operate at another speed, 3153 * but the specification says we need this 3154 * descriptor: 3155 */ 3156 case UDESC_DEVICE_QUALIFIER: 3157 if ((value & 0xff) != 0) { 3158 err = USB_ERR_IOERROR; 3159 goto done; 3160 } 3161 len = sizeof(ehci_odevd); 3162 ptr = (const void *)&ehci_odevd; 3163 break; 3164 3165 case UDESC_CONFIG: 3166 if ((value & 0xff) != 0) { 3167 err = USB_ERR_IOERROR; 3168 goto done; 3169 } 3170 len = sizeof(ehci_confd); 3171 ptr = (const void *)&ehci_confd; 3172 break; 3173 3174 case UDESC_STRING: 3175 switch (value & 0xff) { 3176 case 0: /* Language table */ 3177 str_ptr = "\001"; 3178 break; 3179 3180 case 1: /* Vendor */ 3181 str_ptr = sc->sc_vendor; 3182 break; 3183 3184 case 2: /* Product */ 3185 str_ptr = "EHCI root HUB"; 3186 break; 3187 3188 default: 3189 str_ptr = ""; 3190 break; 3191 } 3192 3193 len = usb_make_str_desc( 3194 sc->sc_hub_desc.temp, 3195 sizeof(sc->sc_hub_desc.temp), 3196 str_ptr); 3197 break; 3198 default: 3199 err = USB_ERR_IOERROR; 3200 goto done; 3201 } 3202 break; 3203 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3204 len = 1; 3205 sc->sc_hub_desc.temp[0] = 0; 3206 break; 3207 case C(UR_GET_STATUS, UT_READ_DEVICE): 3208 len = 2; 3209 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3210 break; 3211 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3212 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3213 len = 2; 3214 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3215 break; 3216 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3217 if (value >= EHCI_MAX_DEVICES) { 3218 err = USB_ERR_IOERROR; 3219 goto done; 3220 } 3221 sc->sc_addr = value; 3222 break; 3223 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3224 if ((value != 0) && (value != 1)) { 3225 err = USB_ERR_IOERROR; 3226 goto done; 3227 } 3228 sc->sc_conf = value; 3229 break; 3230 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3231 break; 3232 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3233 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3234 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3235 err = USB_ERR_IOERROR; 3236 goto done; 3237 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3238 break; 3239 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3240 break; 3241 /* Hub requests */ 3242 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3243 break; 3244 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3245 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3246 3247 if ((index < 1) || 3248 (index > sc->sc_noport)) { 3249 err = USB_ERR_IOERROR; 3250 goto done; 3251 } 3252 port = EHCI_PORTSC(index); 3253 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3254 switch (value) { 3255 case UHF_PORT_ENABLE: 3256 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3257 break; 3258 case UHF_PORT_SUSPEND: 3259 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3260 3261 /* 3262 * waking up a High Speed device is rather 3263 * complicated if 3264 */ 3265 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3266 } 3267 /* wait 20ms for resume sequence to complete */ 3268 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3269 3270 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3271 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3272 3273 /* 4ms settle time */ 3274 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3275 break; 3276 case UHF_PORT_POWER: 3277 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3278 break; 3279 case UHF_PORT_TEST: 3280 DPRINTFN(3, "clear port test " 3281 "%d\n", index); 3282 break; 3283 case UHF_PORT_INDICATOR: 3284 DPRINTFN(3, "clear port ind " 3285 "%d\n", index); 3286 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3287 break; 3288 case UHF_C_PORT_CONNECTION: 3289 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3290 break; 3291 case UHF_C_PORT_ENABLE: 3292 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3293 break; 3294 case UHF_C_PORT_SUSPEND: 3295 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3296 break; 3297 case UHF_C_PORT_OVER_CURRENT: 3298 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3299 break; 3300 case UHF_C_PORT_RESET: 3301 sc->sc_isreset = 0; 3302 break; 3303 default: 3304 err = USB_ERR_IOERROR; 3305 goto done; 3306 } 3307 break; 3308 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3309 if ((value & 0xff) != 0) { 3310 err = USB_ERR_IOERROR; 3311 goto done; 3312 } 3313 v = EREAD4(sc, EHCI_HCSPARAMS); 3314 3315 sc->sc_hub_desc.hubd = ehci_hubd; 3316 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3317 3318 if (EHCI_HCS_PPC(v)) 3319 i = UHD_PWR_INDIVIDUAL; 3320 else 3321 i = UHD_PWR_NO_SWITCH; 3322 3323 if (EHCI_HCS_P_INDICATOR(v)) 3324 i |= UHD_PORT_IND; 3325 3326 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3327 /* XXX can't find out? */ 3328 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3329 /* XXX don't know if ports are removable or not */ 3330 sc->sc_hub_desc.hubd.bDescLength = 3331 8 + ((sc->sc_noport + 7) / 8); 3332 len = sc->sc_hub_desc.hubd.bDescLength; 3333 break; 3334 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3335 len = 16; 3336 memset(sc->sc_hub_desc.temp, 0, 16); 3337 break; 3338 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3339 DPRINTFN(9, "get port status i=%d\n", 3340 index); 3341 if ((index < 1) || 3342 (index > sc->sc_noport)) { 3343 err = USB_ERR_IOERROR; 3344 goto done; 3345 } 3346 v = EOREAD4(sc, EHCI_PORTSC(index)); 3347 DPRINTFN(9, "port status=0x%04x\n", v); 3348 if (sc->sc_flags & EHCI_SCFLG_TT) { 3349 if (sc->sc_vendor_get_port_speed != NULL) { 3350 i = sc->sc_vendor_get_port_speed(sc, index); 3351 } else { 3352 device_printf(sc->sc_bus.bdev, 3353 "EHCI_SCFLG_TT quirk is set but " 3354 "sc_vendor_get_hub_speed() is NULL\n"); 3355 i = UPS_HIGH_SPEED; 3356 } 3357 } else { 3358 i = UPS_HIGH_SPEED; 3359 } 3360 if (v & EHCI_PS_CS) 3361 i |= UPS_CURRENT_CONNECT_STATUS; 3362 if (v & EHCI_PS_PE) 3363 i |= UPS_PORT_ENABLED; 3364 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3365 i |= UPS_SUSPEND; 3366 if (v & EHCI_PS_OCA) 3367 i |= UPS_OVERCURRENT_INDICATOR; 3368 if (v & EHCI_PS_PR) 3369 i |= UPS_RESET; 3370 if (v & EHCI_PS_PP) 3371 i |= UPS_PORT_POWER; 3372 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3373 i = 0; 3374 if (v & EHCI_PS_CSC) 3375 i |= UPS_C_CONNECT_STATUS; 3376 if (v & EHCI_PS_PEC) 3377 i |= UPS_C_PORT_ENABLED; 3378 if (v & EHCI_PS_OCC) 3379 i |= UPS_C_OVERCURRENT_INDICATOR; 3380 if (v & EHCI_PS_FPR) 3381 i |= UPS_C_SUSPEND; 3382 if (sc->sc_isreset) 3383 i |= UPS_C_PORT_RESET; 3384 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3385 len = sizeof(sc->sc_hub_desc.ps); 3386 break; 3387 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3388 err = USB_ERR_IOERROR; 3389 goto done; 3390 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3391 break; 3392 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3393 if ((index < 1) || 3394 (index > sc->sc_noport)) { 3395 err = USB_ERR_IOERROR; 3396 goto done; 3397 } 3398 port = EHCI_PORTSC(index); 3399 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3400 switch (value) { 3401 case UHF_PORT_ENABLE: 3402 EOWRITE4(sc, port, v | EHCI_PS_PE); 3403 break; 3404 case UHF_PORT_SUSPEND: 3405 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3406 break; 3407 case UHF_PORT_RESET: 3408 DPRINTFN(6, "reset port %d\n", index); 3409 #ifdef USB_DEBUG 3410 if (ehcinohighspeed) { 3411 /* 3412 * Connect USB device to companion 3413 * controller. 3414 */ 3415 ehci_disown(sc, index, 1); 3416 break; 3417 } 3418 #endif 3419 if (EHCI_PS_IS_LOWSPEED(v) && 3420 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3421 /* Low speed device, give up ownership. */ 3422 ehci_disown(sc, index, 1); 3423 break; 3424 } 3425 /* Start reset sequence. */ 3426 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3427 EOWRITE4(sc, port, v | EHCI_PS_PR); 3428 3429 /* Wait for reset to complete. */ 3430 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3431 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 3432 3433 /* Terminate reset sequence. */ 3434 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3435 EOWRITE4(sc, port, v); 3436 3437 /* Wait for HC to complete reset. */ 3438 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3439 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3440 3441 v = EOREAD4(sc, port); 3442 DPRINTF("ehci after reset, status=0x%08x\n", v); 3443 if (v & EHCI_PS_PR) { 3444 device_printf(sc->sc_bus.bdev, 3445 "port reset timeout\n"); 3446 err = USB_ERR_TIMEOUT; 3447 goto done; 3448 } 3449 if (!(v & EHCI_PS_PE) && 3450 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3451 /* Not a high speed device, give up ownership.*/ 3452 ehci_disown(sc, index, 0); 3453 break; 3454 } 3455 sc->sc_isreset = 1; 3456 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3457 index, v); 3458 break; 3459 3460 case UHF_PORT_POWER: 3461 DPRINTFN(3, "set port power %d\n", index); 3462 EOWRITE4(sc, port, v | EHCI_PS_PP); 3463 break; 3464 3465 case UHF_PORT_TEST: 3466 DPRINTFN(3, "set port test %d\n", index); 3467 break; 3468 3469 case UHF_PORT_INDICATOR: 3470 DPRINTFN(3, "set port ind %d\n", index); 3471 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3472 break; 3473 3474 default: 3475 err = USB_ERR_IOERROR; 3476 goto done; 3477 } 3478 break; 3479 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3480 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3481 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3482 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3483 break; 3484 default: 3485 err = USB_ERR_IOERROR; 3486 goto done; 3487 } 3488 done: 3489 *plength = len; 3490 *pptr = ptr; 3491 return (err); 3492 } 3493 3494 static void 3495 ehci_xfer_setup(struct usb_setup_params *parm) 3496 { 3497 struct usb_page_search page_info; 3498 struct usb_page_cache *pc; 3499 ehci_softc_t *sc; 3500 struct usb_xfer *xfer; 3501 void *last_obj; 3502 uint32_t nqtd; 3503 uint32_t nqh; 3504 uint32_t nsitd; 3505 uint32_t nitd; 3506 uint32_t n; 3507 3508 sc = EHCI_BUS2SC(parm->udev->bus); 3509 xfer = parm->curr_xfer; 3510 3511 nqtd = 0; 3512 nqh = 0; 3513 nsitd = 0; 3514 nitd = 0; 3515 3516 /* 3517 * compute maximum number of some structures 3518 */ 3519 if (parm->methods == &ehci_device_ctrl_methods) { 3520 3521 /* 3522 * The proof for the "nqtd" formula is illustrated like 3523 * this: 3524 * 3525 * +------------------------------------+ 3526 * | | 3527 * | |remainder -> | 3528 * | +-----+---+ | 3529 * | | xxx | x | frm 0 | 3530 * | +-----+---++ | 3531 * | | xxx | xx | frm 1 | 3532 * | +-----+----+ | 3533 * | ... | 3534 * +------------------------------------+ 3535 * 3536 * "xxx" means a completely full USB transfer descriptor 3537 * 3538 * "x" and "xx" means a short USB packet 3539 * 3540 * For the remainder of an USB transfer modulo 3541 * "max_data_length" we need two USB transfer descriptors. 3542 * One to transfer the remaining data and one to finalise 3543 * with a zero length packet in case the "force_short_xfer" 3544 * flag is set. We only need two USB transfer descriptors in 3545 * the case where the transfer length of the first one is a 3546 * factor of "max_frame_size". The rest of the needed USB 3547 * transfer descriptors is given by the buffer size divided 3548 * by the maximum data payload. 3549 */ 3550 parm->hc_max_packet_size = 0x400; 3551 parm->hc_max_packet_count = 1; 3552 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3553 xfer->flags_int.bdma_enable = 1; 3554 3555 usbd_transfer_setup_sub(parm); 3556 3557 nqh = 1; 3558 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3559 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3560 3561 } else if (parm->methods == &ehci_device_bulk_methods) { 3562 3563 parm->hc_max_packet_size = 0x400; 3564 parm->hc_max_packet_count = 1; 3565 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3566 xfer->flags_int.bdma_enable = 1; 3567 3568 usbd_transfer_setup_sub(parm); 3569 3570 nqh = 1; 3571 nqtd = ((2 * xfer->nframes) 3572 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3573 3574 } else if (parm->methods == &ehci_device_intr_methods) { 3575 3576 if (parm->speed == USB_SPEED_HIGH) { 3577 parm->hc_max_packet_size = 0x400; 3578 parm->hc_max_packet_count = 3; 3579 } else if (parm->speed == USB_SPEED_FULL) { 3580 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3581 parm->hc_max_packet_count = 1; 3582 } else { 3583 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3584 parm->hc_max_packet_count = 1; 3585 } 3586 3587 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3588 xfer->flags_int.bdma_enable = 1; 3589 3590 usbd_transfer_setup_sub(parm); 3591 3592 nqh = 1; 3593 nqtd = ((2 * xfer->nframes) 3594 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3595 3596 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3597 3598 parm->hc_max_packet_size = 0x3FF; 3599 parm->hc_max_packet_count = 1; 3600 parm->hc_max_frame_size = 0x3FF; 3601 xfer->flags_int.bdma_enable = 1; 3602 3603 usbd_transfer_setup_sub(parm); 3604 3605 nsitd = xfer->nframes; 3606 3607 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3608 3609 parm->hc_max_packet_size = 0x400; 3610 parm->hc_max_packet_count = 3; 3611 parm->hc_max_frame_size = 0xC00; 3612 xfer->flags_int.bdma_enable = 1; 3613 3614 usbd_transfer_setup_sub(parm); 3615 3616 nitd = ((xfer->nframes + 7) / 8) << 3617 usbd_xfer_get_fps_shift(xfer); 3618 3619 } else { 3620 3621 parm->hc_max_packet_size = 0x400; 3622 parm->hc_max_packet_count = 1; 3623 parm->hc_max_frame_size = 0x400; 3624 3625 usbd_transfer_setup_sub(parm); 3626 } 3627 3628 alloc_dma_set: 3629 3630 if (parm->err) { 3631 return; 3632 } 3633 /* 3634 * Allocate queue heads and transfer descriptors 3635 */ 3636 last_obj = NULL; 3637 3638 if (usbd_transfer_setup_sub_malloc( 3639 parm, &pc, sizeof(ehci_itd_t), 3640 EHCI_ITD_ALIGN, nitd)) { 3641 parm->err = USB_ERR_NOMEM; 3642 return; 3643 } 3644 if (parm->buf) { 3645 for (n = 0; n != nitd; n++) { 3646 ehci_itd_t *td; 3647 3648 usbd_get_page(pc + n, 0, &page_info); 3649 3650 td = page_info.buffer; 3651 3652 /* init TD */ 3653 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3654 td->obj_next = last_obj; 3655 td->page_cache = pc + n; 3656 3657 last_obj = td; 3658 3659 usb_pc_cpu_flush(pc + n); 3660 } 3661 } 3662 if (usbd_transfer_setup_sub_malloc( 3663 parm, &pc, sizeof(ehci_sitd_t), 3664 EHCI_SITD_ALIGN, nsitd)) { 3665 parm->err = USB_ERR_NOMEM; 3666 return; 3667 } 3668 if (parm->buf) { 3669 for (n = 0; n != nsitd; n++) { 3670 ehci_sitd_t *td; 3671 3672 usbd_get_page(pc + n, 0, &page_info); 3673 3674 td = page_info.buffer; 3675 3676 /* init TD */ 3677 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3678 td->obj_next = last_obj; 3679 td->page_cache = pc + n; 3680 3681 last_obj = td; 3682 3683 usb_pc_cpu_flush(pc + n); 3684 } 3685 } 3686 if (usbd_transfer_setup_sub_malloc( 3687 parm, &pc, sizeof(ehci_qtd_t), 3688 EHCI_QTD_ALIGN, nqtd)) { 3689 parm->err = USB_ERR_NOMEM; 3690 return; 3691 } 3692 if (parm->buf) { 3693 for (n = 0; n != nqtd; n++) { 3694 ehci_qtd_t *qtd; 3695 3696 usbd_get_page(pc + n, 0, &page_info); 3697 3698 qtd = page_info.buffer; 3699 3700 /* init TD */ 3701 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3702 qtd->obj_next = last_obj; 3703 qtd->page_cache = pc + n; 3704 3705 last_obj = qtd; 3706 3707 usb_pc_cpu_flush(pc + n); 3708 } 3709 } 3710 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3711 3712 last_obj = NULL; 3713 3714 if (usbd_transfer_setup_sub_malloc( 3715 parm, &pc, sizeof(ehci_qh_t), 3716 EHCI_QH_ALIGN, nqh)) { 3717 parm->err = USB_ERR_NOMEM; 3718 return; 3719 } 3720 if (parm->buf) { 3721 for (n = 0; n != nqh; n++) { 3722 ehci_qh_t *qh; 3723 3724 usbd_get_page(pc + n, 0, &page_info); 3725 3726 qh = page_info.buffer; 3727 3728 /* init QH */ 3729 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3730 qh->obj_next = last_obj; 3731 qh->page_cache = pc + n; 3732 3733 last_obj = qh; 3734 3735 usb_pc_cpu_flush(pc + n); 3736 } 3737 } 3738 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3739 3740 if (!xfer->flags_int.curr_dma_set) { 3741 xfer->flags_int.curr_dma_set = 1; 3742 goto alloc_dma_set; 3743 } 3744 } 3745 3746 static void 3747 ehci_xfer_unsetup(struct usb_xfer *xfer) 3748 { 3749 return; 3750 } 3751 3752 static void 3753 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3754 struct usb_endpoint *ep) 3755 { 3756 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3757 3758 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3759 ep, udev->address, 3760 edesc->bEndpointAddress, udev->flags.usb_mode, 3761 sc->sc_addr); 3762 3763 if (udev->device_index != sc->sc_addr) { 3764 3765 if ((udev->speed != USB_SPEED_HIGH) && 3766 ((udev->hs_hub_addr == 0) || 3767 (udev->hs_port_no == 0) || 3768 (udev->parent_hs_hub == NULL) || 3769 (udev->parent_hs_hub->hub == NULL))) { 3770 /* We need a transaction translator */ 3771 goto done; 3772 } 3773 switch (edesc->bmAttributes & UE_XFERTYPE) { 3774 case UE_CONTROL: 3775 ep->methods = &ehci_device_ctrl_methods; 3776 break; 3777 case UE_INTERRUPT: 3778 ep->methods = &ehci_device_intr_methods; 3779 break; 3780 case UE_ISOCHRONOUS: 3781 if (udev->speed == USB_SPEED_HIGH) { 3782 ep->methods = &ehci_device_isoc_hs_methods; 3783 } else if (udev->speed == USB_SPEED_FULL) { 3784 ep->methods = &ehci_device_isoc_fs_methods; 3785 } 3786 break; 3787 case UE_BULK: 3788 ep->methods = &ehci_device_bulk_methods; 3789 break; 3790 default: 3791 /* do nothing */ 3792 break; 3793 } 3794 } 3795 done: 3796 return; 3797 } 3798 3799 static void 3800 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3801 { 3802 /* 3803 * Wait until the hardware has finished any possible use of 3804 * the transfer descriptor(s) and QH 3805 */ 3806 *pus = (1125); /* microseconds */ 3807 } 3808 3809 static void 3810 ehci_device_resume(struct usb_device *udev) 3811 { 3812 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3813 struct usb_xfer *xfer; 3814 const struct usb_pipe_methods *methods; 3815 3816 DPRINTF("\n"); 3817 3818 USB_BUS_LOCK(udev->bus); 3819 3820 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3821 3822 if (xfer->xroot->udev == udev) { 3823 3824 methods = xfer->endpoint->methods; 3825 3826 if ((methods == &ehci_device_bulk_methods) || 3827 (methods == &ehci_device_ctrl_methods)) { 3828 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3829 sc->sc_async_p_last); 3830 } 3831 if (methods == &ehci_device_intr_methods) { 3832 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3833 sc->sc_intr_p_last[xfer->qh_pos]); 3834 } 3835 } 3836 } 3837 3838 USB_BUS_UNLOCK(udev->bus); 3839 3840 return; 3841 } 3842 3843 static void 3844 ehci_device_suspend(struct usb_device *udev) 3845 { 3846 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3847 struct usb_xfer *xfer; 3848 const struct usb_pipe_methods *methods; 3849 3850 DPRINTF("\n"); 3851 3852 USB_BUS_LOCK(udev->bus); 3853 3854 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3855 3856 if (xfer->xroot->udev == udev) { 3857 3858 methods = xfer->endpoint->methods; 3859 3860 if ((methods == &ehci_device_bulk_methods) || 3861 (methods == &ehci_device_ctrl_methods)) { 3862 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3863 sc->sc_async_p_last); 3864 } 3865 if (methods == &ehci_device_intr_methods) { 3866 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3867 sc->sc_intr_p_last[xfer->qh_pos]); 3868 } 3869 } 3870 } 3871 3872 USB_BUS_UNLOCK(udev->bus); 3873 } 3874 3875 static void 3876 ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3877 { 3878 struct ehci_softc *sc = EHCI_BUS2SC(bus); 3879 3880 switch (state) { 3881 case USB_HW_POWER_SUSPEND: 3882 case USB_HW_POWER_SHUTDOWN: 3883 ehci_suspend(sc); 3884 break; 3885 case USB_HW_POWER_RESUME: 3886 ehci_resume(sc); 3887 break; 3888 default: 3889 break; 3890 } 3891 } 3892 3893 static void 3894 ehci_set_hw_power(struct usb_bus *bus) 3895 { 3896 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3897 uint32_t temp; 3898 uint32_t flags; 3899 3900 DPRINTF("\n"); 3901 3902 USB_BUS_LOCK(bus); 3903 3904 flags = bus->hw_power_state; 3905 3906 temp = EOREAD4(sc, EHCI_USBCMD); 3907 3908 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3909 3910 if (flags & (USB_HW_POWER_CONTROL | 3911 USB_HW_POWER_BULK)) { 3912 DPRINTF("Async is active\n"); 3913 temp |= EHCI_CMD_ASE; 3914 } 3915 if (flags & (USB_HW_POWER_INTERRUPT | 3916 USB_HW_POWER_ISOC)) { 3917 DPRINTF("Periodic is active\n"); 3918 temp |= EHCI_CMD_PSE; 3919 } 3920 EOWRITE4(sc, EHCI_USBCMD, temp); 3921 3922 USB_BUS_UNLOCK(bus); 3923 3924 return; 3925 } 3926 3927 static void 3928 ehci_start_dma_delay_second(struct usb_xfer *xfer) 3929 { 3930 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3931 3932 DPRINTF("\n"); 3933 3934 /* trigger doorbell */ 3935 ehci_doorbell_async(sc); 3936 3937 /* give the doorbell 4ms */ 3938 usbd_transfer_timeout_ms(xfer, 3939 (void (*)(void *))&usb_dma_delay_done_cb, 4); 3940 } 3941 3942 /* 3943 * Ring the doorbell twice before freeing any DMA descriptors. Some host 3944 * controllers apparently cache the QH descriptors and need a message 3945 * that the cache needs to be discarded. 3946 */ 3947 static void 3948 ehci_start_dma_delay(struct usb_xfer *xfer) 3949 { 3950 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3951 3952 DPRINTF("\n"); 3953 3954 /* trigger doorbell */ 3955 ehci_doorbell_async(sc); 3956 3957 /* give the doorbell 4ms */ 3958 usbd_transfer_timeout_ms(xfer, 3959 (void (*)(void *))&ehci_start_dma_delay_second, 4); 3960 } 3961 3962 static const struct usb_bus_methods ehci_bus_methods = 3963 { 3964 .endpoint_init = ehci_ep_init, 3965 .xfer_setup = ehci_xfer_setup, 3966 .xfer_unsetup = ehci_xfer_unsetup, 3967 .get_dma_delay = ehci_get_dma_delay, 3968 .device_resume = ehci_device_resume, 3969 .device_suspend = ehci_device_suspend, 3970 .set_hw_power = ehci_set_hw_power, 3971 .set_hw_power_sleep = ehci_set_hw_power_sleep, 3972 .roothub_exec = ehci_roothub_exec, 3973 .xfer_poll = ehci_do_poll, 3974 .start_dma_delay = ehci_start_dma_delay, 3975 }; 3976