1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 31 * 32 * The EHCI 0.96 spec can be found at 33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 34 * The EHCI 1.0 spec can be found at 35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 36 * and the USB 2.0 spec at 37 * http://www.usb.org/developers/docs/usb_20.zip 38 * 39 */ 40 41 /* 42 * TODO: 43 * 1) command failures are not recovered correctly 44 */ 45 46 #include <sys/cdefs.h> 47 __FBSDID("$FreeBSD$"); 48 49 #include <dev/usb/usb.h> 50 #include <dev/usb/usb_mfunc.h> 51 #include <dev/usb/usb_error.h> 52 53 #define USB_DEBUG_VAR ehcidebug 54 55 #include <dev/usb/usb_core.h> 56 #include <dev/usb/usb_debug.h> 57 #include <dev/usb/usb_busdma.h> 58 #include <dev/usb/usb_process.h> 59 #include <dev/usb/usb_transfer.h> 60 #include <dev/usb/usb_device.h> 61 #include <dev/usb/usb_hub.h> 62 #include <dev/usb/usb_util.h> 63 64 #include <dev/usb/usb_controller.h> 65 #include <dev/usb/usb_bus.h> 66 #include <dev/usb/controller/ehci.h> 67 68 #define EHCI_BUS2SC(bus) \ 69 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 70 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 71 72 #if USB_DEBUG 73 static int ehcidebug = 0; 74 static int ehcinohighspeed = 0; 75 76 SYSCTL_NODE(_hw_usb2, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 77 SYSCTL_INT(_hw_usb2_ehci, OID_AUTO, debug, CTLFLAG_RW, 78 &ehcidebug, 0, "Debug level"); 79 SYSCTL_INT(_hw_usb2_ehci, OID_AUTO, no_hs, CTLFLAG_RW, 80 &ehcinohighspeed, 0, "Disable High Speed USB"); 81 82 static void ehci_dump_regs(ehci_softc_t *sc); 83 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 84 85 #endif 86 87 #define EHCI_INTR_ENDPT 1 88 89 extern struct usb2_bus_methods ehci_bus_methods; 90 extern struct usb2_pipe_methods ehci_device_bulk_methods; 91 extern struct usb2_pipe_methods ehci_device_ctrl_methods; 92 extern struct usb2_pipe_methods ehci_device_intr_methods; 93 extern struct usb2_pipe_methods ehci_device_isoc_fs_methods; 94 extern struct usb2_pipe_methods ehci_device_isoc_hs_methods; 95 96 static void ehci_do_poll(struct usb2_bus *bus); 97 static void ehci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 98 static uint8_t ehci_check_transfer(struct usb2_xfer *xfer); 99 static void ehci_timeout(void *arg); 100 static void ehci_root_intr(ehci_softc_t *sc); 101 102 struct ehci_std_temp { 103 ehci_softc_t *sc; 104 struct usb2_page_cache *pc; 105 ehci_qtd_t *td; 106 ehci_qtd_t *td_next; 107 uint32_t average; 108 uint32_t qtd_status; 109 uint32_t len; 110 uint16_t max_frame_size; 111 uint8_t shortpkt; 112 uint8_t auto_data_toggle; 113 uint8_t setup_alt_next; 114 uint8_t last_frame; 115 }; 116 117 void 118 ehci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 119 { 120 ehci_softc_t *sc = EHCI_BUS2SC(bus); 121 uint32_t i; 122 123 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 124 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 125 126 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 127 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 128 129 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 130 cb(bus, sc->sc_hw.intr_start_pc + i, 131 sc->sc_hw.intr_start_pg + i, 132 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 133 } 134 135 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 136 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 137 sc->sc_hw.isoc_hs_start_pg + i, 138 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 139 } 140 141 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 142 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 143 sc->sc_hw.isoc_fs_start_pg + i, 144 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 145 } 146 } 147 148 usb2_error_t 149 ehci_reset(ehci_softc_t *sc) 150 { 151 uint32_t hcr; 152 int i; 153 154 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 155 for (i = 0; i < 100; i++) { 156 usb2_pause_mtx(NULL, hz / 1000); 157 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 158 if (!hcr) { 159 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) { 160 /* 161 * Force USBMODE as requested. Controllers 162 * may have multiple operating modes. 163 */ 164 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE); 165 if (sc->sc_flags & EHCI_SCFLG_SETMODE) { 166 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST; 167 device_printf(sc->sc_bus.bdev, 168 "set host controller mode\n"); 169 } 170 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) { 171 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE; 172 device_printf(sc->sc_bus.bdev, 173 "set big-endian mode\n"); 174 } 175 EOWRITE4(sc, EHCI_USBMODE, usbmode); 176 } 177 return (0); 178 } 179 } 180 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 181 return (USB_ERR_IOERROR); 182 } 183 184 static usb2_error_t 185 ehci_hcreset(ehci_softc_t *sc) 186 { 187 uint32_t hcr; 188 int i; 189 190 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 191 for (i = 0; i < 100; i++) { 192 usb2_pause_mtx(NULL, hz / 1000); 193 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 194 if (hcr) 195 break; 196 } 197 if (!hcr) 198 /* 199 * Fall through and try reset anyway even though 200 * Table 2-9 in the EHCI spec says this will result 201 * in undefined behavior. 202 */ 203 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 204 205 return ehci_reset(sc); 206 } 207 208 usb2_error_t 209 ehci_init(ehci_softc_t *sc) 210 { 211 struct usb2_page_search buf_res; 212 uint32_t version; 213 uint32_t sparams; 214 uint32_t cparams; 215 uint32_t hcr; 216 uint16_t i; 217 uint16_t x; 218 uint16_t y; 219 uint16_t bit; 220 usb2_error_t err = 0; 221 222 DPRINTF("start\n"); 223 224 usb2_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 225 226 #if USB_DEBUG 227 if (ehcidebug > 2) { 228 ehci_dump_regs(sc); 229 } 230 #endif 231 232 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 233 234 version = EREAD2(sc, EHCI_HCIVERSION); 235 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 236 version >> 8, version & 0xff); 237 238 sparams = EREAD4(sc, EHCI_HCSPARAMS); 239 DPRINTF("sparams=0x%x\n", sparams); 240 241 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 242 cparams = EREAD4(sc, EHCI_HCCPARAMS); 243 DPRINTF("cparams=0x%x\n", cparams); 244 245 if (EHCI_HCC_64BIT(cparams)) { 246 DPRINTF("HCC uses 64-bit structures\n"); 247 248 /* MUST clear segment register if 64 bit capable */ 249 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 250 } 251 sc->sc_bus.usbrev = USB_REV_2_0; 252 253 /* Reset the controller */ 254 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 255 256 err = ehci_hcreset(sc); 257 if (err) { 258 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 259 return (err); 260 } 261 /* 262 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 263 * bytes 2: 256*4 bytes 3: unknown 264 */ 265 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 266 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 267 return (USB_ERR_IOERROR); 268 } 269 /* set up the bus struct */ 270 sc->sc_bus.methods = &ehci_bus_methods; 271 272 sc->sc_eintrs = EHCI_NORMAL_INTRS; 273 274 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 275 ehci_qh_t *qh; 276 277 usb2_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 278 279 qh = buf_res.buffer; 280 281 /* initialize page cache pointer */ 282 283 qh->page_cache = sc->sc_hw.intr_start_pc + i; 284 285 /* store a pointer to queue head */ 286 287 sc->sc_intr_p_last[i] = qh; 288 289 qh->qh_self = 290 htohc32(sc, buf_res.physaddr) | 291 htohc32(sc, EHCI_LINK_QH); 292 293 qh->qh_endp = 294 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 295 qh->qh_endphub = 296 htohc32(sc, EHCI_QH_SET_MULT(1)); 297 qh->qh_curqtd = 0; 298 299 qh->qh_qtd.qtd_next = 300 htohc32(sc, EHCI_LINK_TERMINATE); 301 qh->qh_qtd.qtd_altnext = 302 htohc32(sc, EHCI_LINK_TERMINATE); 303 qh->qh_qtd.qtd_status = 304 htohc32(sc, EHCI_QTD_HALTED); 305 } 306 307 /* 308 * the QHs are arranged to give poll intervals that are 309 * powers of 2 times 1ms 310 */ 311 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 312 while (bit) { 313 x = bit; 314 while (x & bit) { 315 ehci_qh_t *qh_x; 316 ehci_qh_t *qh_y; 317 318 y = (x ^ bit) | (bit / 2); 319 320 qh_x = sc->sc_intr_p_last[x]; 321 qh_y = sc->sc_intr_p_last[y]; 322 323 /* 324 * the next QH has half the poll interval 325 */ 326 qh_x->qh_link = qh_y->qh_self; 327 328 x++; 329 } 330 bit >>= 1; 331 } 332 333 if (1) { 334 ehci_qh_t *qh; 335 336 qh = sc->sc_intr_p_last[0]; 337 338 /* the last (1ms) QH terminates */ 339 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 340 } 341 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 342 ehci_sitd_t *sitd; 343 ehci_itd_t *itd; 344 345 usb2_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 346 347 sitd = buf_res.buffer; 348 349 /* initialize page cache pointer */ 350 351 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 352 353 /* store a pointer to the transfer descriptor */ 354 355 sc->sc_isoc_fs_p_last[i] = sitd; 356 357 /* initialize full speed isochronous */ 358 359 sitd->sitd_self = 360 htohc32(sc, buf_res.physaddr) | 361 htohc32(sc, EHCI_LINK_SITD); 362 363 sitd->sitd_back = 364 htohc32(sc, EHCI_LINK_TERMINATE); 365 366 sitd->sitd_next = 367 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 368 369 370 usb2_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 371 372 itd = buf_res.buffer; 373 374 /* initialize page cache pointer */ 375 376 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 377 378 /* store a pointer to the transfer descriptor */ 379 380 sc->sc_isoc_hs_p_last[i] = itd; 381 382 /* initialize high speed isochronous */ 383 384 itd->itd_self = 385 htohc32(sc, buf_res.physaddr) | 386 htohc32(sc, EHCI_LINK_ITD); 387 388 itd->itd_next = 389 sitd->sitd_self; 390 } 391 392 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 393 394 if (1) { 395 uint32_t *pframes; 396 397 pframes = buf_res.buffer; 398 399 /* 400 * execution order: 401 * pframes -> high speed isochronous -> 402 * full speed isochronous -> interrupt QH's 403 */ 404 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 405 pframes[i] = sc->sc_isoc_hs_p_last 406 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 407 } 408 } 409 /* setup sync list pointer */ 410 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 411 412 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 413 414 if (1) { 415 416 ehci_qh_t *qh; 417 418 qh = buf_res.buffer; 419 420 /* initialize page cache pointer */ 421 422 qh->page_cache = &sc->sc_hw.async_start_pc; 423 424 /* store a pointer to the queue head */ 425 426 sc->sc_async_p_last = qh; 427 428 /* init dummy QH that starts the async list */ 429 430 qh->qh_self = 431 htohc32(sc, buf_res.physaddr) | 432 htohc32(sc, EHCI_LINK_QH); 433 434 /* fill the QH */ 435 qh->qh_endp = 436 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 437 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 438 qh->qh_link = qh->qh_self; 439 qh->qh_curqtd = 0; 440 441 /* fill the overlay qTD */ 442 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 443 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 444 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 445 } 446 /* flush all cache into memory */ 447 448 usb2_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 449 450 #if USB_DEBUG 451 if (ehcidebug) { 452 ehci_dump_sqh(sc, sc->sc_async_p_last); 453 } 454 #endif 455 456 /* setup async list pointer */ 457 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 458 459 460 /* enable interrupts */ 461 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 462 463 /* turn on controller */ 464 EOWRITE4(sc, EHCI_USBCMD, 465 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 466 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 467 EHCI_CMD_ASE | 468 EHCI_CMD_PSE | 469 EHCI_CMD_RS); 470 471 /* Take over port ownership */ 472 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 473 474 for (i = 0; i < 100; i++) { 475 usb2_pause_mtx(NULL, hz / 1000); 476 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 477 if (!hcr) { 478 break; 479 } 480 } 481 if (hcr) { 482 device_printf(sc->sc_bus.bdev, "run timeout\n"); 483 return (USB_ERR_IOERROR); 484 } 485 486 if (!err) { 487 /* catch any lost interrupts */ 488 ehci_do_poll(&sc->sc_bus); 489 } 490 return (err); 491 } 492 493 /* 494 * shut down the controller when the system is going down 495 */ 496 void 497 ehci_detach(ehci_softc_t *sc) 498 { 499 USB_BUS_LOCK(&sc->sc_bus); 500 501 usb2_callout_stop(&sc->sc_tmo_pcd); 502 503 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 504 USB_BUS_UNLOCK(&sc->sc_bus); 505 506 if (ehci_hcreset(sc)) { 507 DPRINTF("reset failed!\n"); 508 } 509 510 /* XXX let stray task complete */ 511 usb2_pause_mtx(NULL, hz / 20); 512 513 usb2_callout_drain(&sc->sc_tmo_pcd); 514 } 515 516 void 517 ehci_suspend(ehci_softc_t *sc) 518 { 519 uint32_t cmd; 520 uint32_t hcr; 521 uint8_t i; 522 523 USB_BUS_LOCK(&sc->sc_bus); 524 525 for (i = 1; i <= sc->sc_noport; i++) { 526 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 527 if (((cmd & EHCI_PS_PO) == 0) && 528 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) { 529 EOWRITE4(sc, EHCI_PORTSC(i), 530 cmd | EHCI_PS_SUSP); 531 } 532 } 533 534 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 535 536 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 537 EOWRITE4(sc, EHCI_USBCMD, cmd); 538 539 for (i = 0; i < 100; i++) { 540 hcr = EOREAD4(sc, EHCI_USBSTS) & 541 (EHCI_STS_ASS | EHCI_STS_PSS); 542 543 if (hcr == 0) { 544 break; 545 } 546 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 547 } 548 549 if (hcr != 0) { 550 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 551 } 552 cmd &= ~EHCI_CMD_RS; 553 EOWRITE4(sc, EHCI_USBCMD, cmd); 554 555 for (i = 0; i < 100; i++) { 556 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 557 if (hcr == EHCI_STS_HCH) { 558 break; 559 } 560 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 561 } 562 563 if (hcr != EHCI_STS_HCH) { 564 device_printf(sc->sc_bus.bdev, 565 "config timeout\n"); 566 } 567 USB_BUS_UNLOCK(&sc->sc_bus); 568 } 569 570 void 571 ehci_resume(ehci_softc_t *sc) 572 { 573 struct usb2_page_search buf_res; 574 uint32_t cmd; 575 uint32_t hcr; 576 uint8_t i; 577 578 USB_BUS_LOCK(&sc->sc_bus); 579 580 /* restore things in case the bios doesn't */ 581 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 582 583 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 584 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 585 586 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 587 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 588 589 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 590 591 hcr = 0; 592 for (i = 1; i <= sc->sc_noport; i++) { 593 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 594 if (((cmd & EHCI_PS_PO) == 0) && 595 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 596 EOWRITE4(sc, EHCI_PORTSC(i), 597 cmd | EHCI_PS_FPR); 598 hcr = 1; 599 } 600 } 601 602 if (hcr) { 603 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 604 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 605 606 for (i = 1; i <= sc->sc_noport; i++) { 607 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 608 if (((cmd & EHCI_PS_PO) == 0) && 609 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 610 EOWRITE4(sc, EHCI_PORTSC(i), 611 cmd & ~EHCI_PS_FPR); 612 } 613 } 614 } 615 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 616 617 for (i = 0; i < 100; i++) { 618 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 619 if (hcr != EHCI_STS_HCH) { 620 break; 621 } 622 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 623 } 624 if (hcr == EHCI_STS_HCH) { 625 device_printf(sc->sc_bus.bdev, "config timeout\n"); 626 } 627 628 USB_BUS_UNLOCK(&sc->sc_bus); 629 630 usb2_pause_mtx(NULL, 631 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 632 633 /* catch any lost interrupts */ 634 ehci_do_poll(&sc->sc_bus); 635 } 636 637 void 638 ehci_shutdown(ehci_softc_t *sc) 639 { 640 DPRINTF("stopping the HC\n"); 641 642 if (ehci_hcreset(sc)) { 643 DPRINTF("reset failed!\n"); 644 } 645 } 646 647 #if USB_DEBUG 648 static void 649 ehci_dump_regs(ehci_softc_t *sc) 650 { 651 uint32_t i; 652 653 i = EOREAD4(sc, EHCI_USBCMD); 654 printf("cmd=0x%08x\n", i); 655 656 if (i & EHCI_CMD_ITC_1) 657 printf(" EHCI_CMD_ITC_1\n"); 658 if (i & EHCI_CMD_ITC_2) 659 printf(" EHCI_CMD_ITC_2\n"); 660 if (i & EHCI_CMD_ITC_4) 661 printf(" EHCI_CMD_ITC_4\n"); 662 if (i & EHCI_CMD_ITC_8) 663 printf(" EHCI_CMD_ITC_8\n"); 664 if (i & EHCI_CMD_ITC_16) 665 printf(" EHCI_CMD_ITC_16\n"); 666 if (i & EHCI_CMD_ITC_32) 667 printf(" EHCI_CMD_ITC_32\n"); 668 if (i & EHCI_CMD_ITC_64) 669 printf(" EHCI_CMD_ITC_64\n"); 670 if (i & EHCI_CMD_ASPME) 671 printf(" EHCI_CMD_ASPME\n"); 672 if (i & EHCI_CMD_ASPMC) 673 printf(" EHCI_CMD_ASPMC\n"); 674 if (i & EHCI_CMD_LHCR) 675 printf(" EHCI_CMD_LHCR\n"); 676 if (i & EHCI_CMD_IAAD) 677 printf(" EHCI_CMD_IAAD\n"); 678 if (i & EHCI_CMD_ASE) 679 printf(" EHCI_CMD_ASE\n"); 680 if (i & EHCI_CMD_PSE) 681 printf(" EHCI_CMD_PSE\n"); 682 if (i & EHCI_CMD_FLS_M) 683 printf(" EHCI_CMD_FLS_M\n"); 684 if (i & EHCI_CMD_HCRESET) 685 printf(" EHCI_CMD_HCRESET\n"); 686 if (i & EHCI_CMD_RS) 687 printf(" EHCI_CMD_RS\n"); 688 689 i = EOREAD4(sc, EHCI_USBSTS); 690 691 printf("sts=0x%08x\n", i); 692 693 if (i & EHCI_STS_ASS) 694 printf(" EHCI_STS_ASS\n"); 695 if (i & EHCI_STS_PSS) 696 printf(" EHCI_STS_PSS\n"); 697 if (i & EHCI_STS_REC) 698 printf(" EHCI_STS_REC\n"); 699 if (i & EHCI_STS_HCH) 700 printf(" EHCI_STS_HCH\n"); 701 if (i & EHCI_STS_IAA) 702 printf(" EHCI_STS_IAA\n"); 703 if (i & EHCI_STS_HSE) 704 printf(" EHCI_STS_HSE\n"); 705 if (i & EHCI_STS_FLR) 706 printf(" EHCI_STS_FLR\n"); 707 if (i & EHCI_STS_PCD) 708 printf(" EHCI_STS_PCD\n"); 709 if (i & EHCI_STS_ERRINT) 710 printf(" EHCI_STS_ERRINT\n"); 711 if (i & EHCI_STS_INT) 712 printf(" EHCI_STS_INT\n"); 713 714 printf("ien=0x%08x\n", 715 EOREAD4(sc, EHCI_USBINTR)); 716 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 717 EOREAD4(sc, EHCI_FRINDEX), 718 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 719 EOREAD4(sc, EHCI_PERIODICLISTBASE), 720 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 721 for (i = 1; i <= sc->sc_noport; i++) { 722 printf("port %d status=0x%08x\n", i, 723 EOREAD4(sc, EHCI_PORTSC(i))); 724 } 725 } 726 727 static void 728 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 729 { 730 link = hc32toh(sc, link); 731 printf("0x%08x", link); 732 if (link & EHCI_LINK_TERMINATE) 733 printf("<T>"); 734 else { 735 printf("<"); 736 if (type) { 737 switch (EHCI_LINK_TYPE(link)) { 738 case EHCI_LINK_ITD: 739 printf("ITD"); 740 break; 741 case EHCI_LINK_QH: 742 printf("QH"); 743 break; 744 case EHCI_LINK_SITD: 745 printf("SITD"); 746 break; 747 case EHCI_LINK_FSTN: 748 printf("FSTN"); 749 break; 750 } 751 } 752 printf(">"); 753 } 754 } 755 756 static void 757 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 758 { 759 uint32_t s; 760 761 printf(" next="); 762 ehci_dump_link(sc, qtd->qtd_next, 0); 763 printf(" altnext="); 764 ehci_dump_link(sc, qtd->qtd_altnext, 0); 765 printf("\n"); 766 s = hc32toh(sc, qtd->qtd_status); 767 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 768 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 769 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 770 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 771 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 772 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 773 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 774 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 775 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 776 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 777 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 778 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 779 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 780 781 for (s = 0; s < 5; s++) { 782 printf(" buffer[%d]=0x%08x\n", s, 783 hc32toh(sc, qtd->qtd_buffer[s])); 784 } 785 for (s = 0; s < 5; s++) { 786 printf(" buffer_hi[%d]=0x%08x\n", s, 787 hc32toh(sc, qtd->qtd_buffer_hi[s])); 788 } 789 } 790 791 static uint8_t 792 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 793 { 794 uint8_t temp; 795 796 usb2_pc_cpu_invalidate(sqtd->page_cache); 797 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 798 ehci_dump_qtd(sc, sqtd); 799 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 800 return (temp); 801 } 802 803 static void 804 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 805 { 806 uint16_t i; 807 uint8_t stop; 808 809 stop = 0; 810 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 811 stop = ehci_dump_sqtd(sc, sqtd); 812 } 813 if (sqtd) { 814 printf("dump aborted, too many TDs\n"); 815 } 816 } 817 818 static void 819 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 820 { 821 uint32_t endp; 822 uint32_t endphub; 823 824 usb2_pc_cpu_invalidate(qh->page_cache); 825 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 826 printf(" link="); 827 ehci_dump_link(sc, qh->qh_link, 1); 828 printf("\n"); 829 endp = hc32toh(sc, qh->qh_endp); 830 printf(" endp=0x%08x\n", endp); 831 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 832 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 833 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 834 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 835 printf(" mpl=0x%x ctl=%d nrl=%d\n", 836 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 837 EHCI_QH_GET_NRL(endp)); 838 endphub = hc32toh(sc, qh->qh_endphub); 839 printf(" endphub=0x%08x\n", endphub); 840 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 841 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 842 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 843 EHCI_QH_GET_MULT(endphub)); 844 printf(" curqtd="); 845 ehci_dump_link(sc, qh->qh_curqtd, 0); 846 printf("\n"); 847 printf("Overlay qTD:\n"); 848 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 849 } 850 851 static void 852 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 853 { 854 usb2_pc_cpu_invalidate(sitd->page_cache); 855 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 856 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 857 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 858 hc32toh(sc, sitd->sitd_portaddr), 859 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 860 ? "in" : "out", 861 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 862 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 863 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 864 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 865 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 866 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 867 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 868 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 869 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 870 hc32toh(sc, sitd->sitd_back), 871 hc32toh(sc, sitd->sitd_bp[0]), 872 hc32toh(sc, sitd->sitd_bp[1]), 873 hc32toh(sc, sitd->sitd_bp_hi[0]), 874 hc32toh(sc, sitd->sitd_bp_hi[1])); 875 } 876 877 static void 878 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 879 { 880 usb2_pc_cpu_invalidate(itd->page_cache); 881 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 882 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 883 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 884 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 885 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 886 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 887 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 888 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 889 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 890 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 891 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 892 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 893 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 894 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 895 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 896 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 897 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 898 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 899 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 900 printf(" addr=0x%02x; endpt=0x%01x\n", 901 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 902 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 903 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 904 printf(" dir=%s; mpl=0x%02x\n", 905 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 906 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 907 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 908 hc32toh(sc, itd->itd_bp[2]), 909 hc32toh(sc, itd->itd_bp[3]), 910 hc32toh(sc, itd->itd_bp[4]), 911 hc32toh(sc, itd->itd_bp[5]), 912 hc32toh(sc, itd->itd_bp[6])); 913 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 914 " 0x%08x,0x%08x,0x%08x\n", 915 hc32toh(sc, itd->itd_bp_hi[0]), 916 hc32toh(sc, itd->itd_bp_hi[1]), 917 hc32toh(sc, itd->itd_bp_hi[2]), 918 hc32toh(sc, itd->itd_bp_hi[3]), 919 hc32toh(sc, itd->itd_bp_hi[4]), 920 hc32toh(sc, itd->itd_bp_hi[5]), 921 hc32toh(sc, itd->itd_bp_hi[6])); 922 } 923 924 static void 925 ehci_dump_isoc(ehci_softc_t *sc) 926 { 927 ehci_itd_t *itd; 928 ehci_sitd_t *sitd; 929 uint16_t max = 1000; 930 uint16_t pos; 931 932 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 933 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 934 935 printf("%s: isochronous dump from frame 0x%03x:\n", 936 __FUNCTION__, pos); 937 938 itd = sc->sc_isoc_hs_p_last[pos]; 939 sitd = sc->sc_isoc_fs_p_last[pos]; 940 941 while (itd && max && max--) { 942 ehci_dump_itd(sc, itd); 943 itd = itd->prev; 944 } 945 946 while (sitd && max && max--) { 947 ehci_dump_sitd(sc, sitd); 948 sitd = sitd->prev; 949 } 950 } 951 952 #endif 953 954 static void 955 ehci_transfer_intr_enqueue(struct usb2_xfer *xfer) 956 { 957 /* check for early completion */ 958 if (ehci_check_transfer(xfer)) { 959 return; 960 } 961 /* put transfer on interrupt queue */ 962 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 963 964 /* start timeout, if any */ 965 if (xfer->timeout != 0) { 966 usb2_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 967 } 968 } 969 970 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 971 static ehci_sitd_t * 972 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 973 { 974 DPRINTFN(11, "%p to %p\n", std, last); 975 976 /* (sc->sc_bus.mtx) must be locked */ 977 978 std->next = last->next; 979 std->sitd_next = last->sitd_next; 980 981 std->prev = last; 982 983 usb2_pc_cpu_flush(std->page_cache); 984 985 /* 986 * the last->next->prev is never followed: std->next->prev = std; 987 */ 988 last->next = std; 989 last->sitd_next = std->sitd_self; 990 991 usb2_pc_cpu_flush(last->page_cache); 992 993 return (std); 994 } 995 996 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 997 static ehci_itd_t * 998 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 999 { 1000 DPRINTFN(11, "%p to %p\n", std, last); 1001 1002 /* (sc->sc_bus.mtx) must be locked */ 1003 1004 std->next = last->next; 1005 std->itd_next = last->itd_next; 1006 1007 std->prev = last; 1008 1009 usb2_pc_cpu_flush(std->page_cache); 1010 1011 /* 1012 * the last->next->prev is never followed: std->next->prev = std; 1013 */ 1014 last->next = std; 1015 last->itd_next = std->itd_self; 1016 1017 usb2_pc_cpu_flush(last->page_cache); 1018 1019 return (std); 1020 } 1021 1022 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 1023 static ehci_qh_t * 1024 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1025 { 1026 DPRINTFN(11, "%p to %p\n", sqh, last); 1027 1028 if (sqh->prev != NULL) { 1029 /* should not happen */ 1030 DPRINTFN(0, "QH already linked!\n"); 1031 return (last); 1032 } 1033 /* (sc->sc_bus.mtx) must be locked */ 1034 1035 sqh->next = last->next; 1036 sqh->qh_link = last->qh_link; 1037 1038 sqh->prev = last; 1039 1040 usb2_pc_cpu_flush(sqh->page_cache); 1041 1042 /* 1043 * the last->next->prev is never followed: sqh->next->prev = sqh; 1044 */ 1045 1046 last->next = sqh; 1047 last->qh_link = sqh->qh_self; 1048 1049 usb2_pc_cpu_flush(last->page_cache); 1050 1051 return (sqh); 1052 } 1053 1054 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1055 static ehci_sitd_t * 1056 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1057 { 1058 DPRINTFN(11, "%p from %p\n", std, last); 1059 1060 /* (sc->sc_bus.mtx) must be locked */ 1061 1062 std->prev->next = std->next; 1063 std->prev->sitd_next = std->sitd_next; 1064 1065 usb2_pc_cpu_flush(std->prev->page_cache); 1066 1067 if (std->next) { 1068 std->next->prev = std->prev; 1069 usb2_pc_cpu_flush(std->next->page_cache); 1070 } 1071 return ((last == std) ? std->prev : last); 1072 } 1073 1074 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1075 static ehci_itd_t * 1076 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1077 { 1078 DPRINTFN(11, "%p from %p\n", std, last); 1079 1080 /* (sc->sc_bus.mtx) must be locked */ 1081 1082 std->prev->next = std->next; 1083 std->prev->itd_next = std->itd_next; 1084 1085 usb2_pc_cpu_flush(std->prev->page_cache); 1086 1087 if (std->next) { 1088 std->next->prev = std->prev; 1089 usb2_pc_cpu_flush(std->next->page_cache); 1090 } 1091 return ((last == std) ? std->prev : last); 1092 } 1093 1094 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1095 static ehci_qh_t * 1096 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1097 { 1098 DPRINTFN(11, "%p from %p\n", sqh, last); 1099 1100 /* (sc->sc_bus.mtx) must be locked */ 1101 1102 /* only remove if not removed from a queue */ 1103 if (sqh->prev) { 1104 1105 sqh->prev->next = sqh->next; 1106 sqh->prev->qh_link = sqh->qh_link; 1107 1108 usb2_pc_cpu_flush(sqh->prev->page_cache); 1109 1110 if (sqh->next) { 1111 sqh->next->prev = sqh->prev; 1112 usb2_pc_cpu_flush(sqh->next->page_cache); 1113 } 1114 last = ((last == sqh) ? sqh->prev : last); 1115 1116 sqh->prev = 0; 1117 1118 usb2_pc_cpu_flush(sqh->page_cache); 1119 } 1120 return (last); 1121 } 1122 1123 static usb2_error_t 1124 ehci_non_isoc_done_sub(struct usb2_xfer *xfer) 1125 { 1126 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1127 ehci_qtd_t *td; 1128 ehci_qtd_t *td_alt_next; 1129 uint32_t status; 1130 uint16_t len; 1131 1132 td = xfer->td_transfer_cache; 1133 td_alt_next = td->alt_next; 1134 1135 if (xfer->aframes != xfer->nframes) { 1136 xfer->frlengths[xfer->aframes] = 0; 1137 } 1138 while (1) { 1139 1140 usb2_pc_cpu_invalidate(td->page_cache); 1141 status = hc32toh(sc, td->qtd_status); 1142 1143 len = EHCI_QTD_GET_BYTES(status); 1144 1145 /* 1146 * Verify the status length and 1147 * add the length to "frlengths[]": 1148 */ 1149 if (len > td->len) { 1150 /* should not happen */ 1151 DPRINTF("Invalid status length, " 1152 "0x%04x/0x%04x bytes\n", len, td->len); 1153 status |= EHCI_QTD_HALTED; 1154 } else if (xfer->aframes != xfer->nframes) { 1155 xfer->frlengths[xfer->aframes] += td->len - len; 1156 } 1157 /* Check for last transfer */ 1158 if (((void *)td) == xfer->td_transfer_last) { 1159 if (len == 0) { 1160 /* 1161 * Halt is ok if descriptor is last, 1162 * and complete: 1163 */ 1164 status &= ~EHCI_QTD_HALTED; 1165 } 1166 td = NULL; 1167 break; 1168 } 1169 /* Check for transfer error */ 1170 if (status & EHCI_QTD_HALTED) { 1171 /* the transfer is finished */ 1172 td = NULL; 1173 break; 1174 } 1175 /* Check for short transfer */ 1176 if (len > 0) { 1177 if (xfer->flags_int.short_frames_ok) { 1178 /* follow alt next */ 1179 td = td->alt_next; 1180 } else { 1181 /* the transfer is finished */ 1182 td = NULL; 1183 } 1184 break; 1185 } 1186 td = td->obj_next; 1187 1188 if (td->alt_next != td_alt_next) { 1189 /* this USB frame is complete */ 1190 break; 1191 } 1192 } 1193 1194 /* update transfer cache */ 1195 1196 xfer->td_transfer_cache = td; 1197 1198 /* update data toggle */ 1199 1200 xfer->pipe->toggle_next = 1201 (status & EHCI_QTD_TOGGLE_MASK) ? 1 : 0; 1202 1203 #if USB_DEBUG 1204 if (status & EHCI_QTD_STATERRS) { 1205 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1206 "status=%s%s%s%s%s%s%s%s\n", 1207 xfer->address, xfer->endpoint, xfer->aframes, 1208 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1209 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1210 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1211 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1212 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1213 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1214 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1215 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1216 } 1217 #endif 1218 1219 return ((status & EHCI_QTD_HALTED) ? 1220 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1221 } 1222 1223 static void 1224 ehci_non_isoc_done(struct usb2_xfer *xfer) 1225 { 1226 usb2_error_t err = 0; 1227 1228 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1229 xfer, xfer->pipe); 1230 1231 #if USB_DEBUG 1232 if (ehcidebug > 10) { 1233 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1234 1235 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1236 } 1237 #endif 1238 1239 /* reset scanner */ 1240 1241 xfer->td_transfer_cache = xfer->td_transfer_first; 1242 1243 if (xfer->flags_int.control_xfr) { 1244 1245 if (xfer->flags_int.control_hdr) { 1246 1247 err = ehci_non_isoc_done_sub(xfer); 1248 } 1249 xfer->aframes = 1; 1250 1251 if (xfer->td_transfer_cache == NULL) { 1252 goto done; 1253 } 1254 } 1255 while (xfer->aframes != xfer->nframes) { 1256 1257 err = ehci_non_isoc_done_sub(xfer); 1258 xfer->aframes++; 1259 1260 if (xfer->td_transfer_cache == NULL) { 1261 goto done; 1262 } 1263 } 1264 1265 if (xfer->flags_int.control_xfr && 1266 !xfer->flags_int.control_act) { 1267 1268 err = ehci_non_isoc_done_sub(xfer); 1269 } 1270 done: 1271 ehci_device_done(xfer, err); 1272 } 1273 1274 /*------------------------------------------------------------------------* 1275 * ehci_check_transfer 1276 * 1277 * Return values: 1278 * 0: USB transfer is not finished 1279 * Else: USB transfer is finished 1280 *------------------------------------------------------------------------*/ 1281 static uint8_t 1282 ehci_check_transfer(struct usb2_xfer *xfer) 1283 { 1284 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1285 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1286 1287 uint32_t status; 1288 1289 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1290 1291 if (methods == &ehci_device_isoc_fs_methods) { 1292 ehci_sitd_t *td; 1293 1294 /* isochronous full speed transfer */ 1295 1296 td = xfer->td_transfer_last; 1297 usb2_pc_cpu_invalidate(td->page_cache); 1298 status = hc32toh(sc, td->sitd_status); 1299 1300 /* also check if first is complete */ 1301 1302 td = xfer->td_transfer_first; 1303 usb2_pc_cpu_invalidate(td->page_cache); 1304 status |= hc32toh(sc, td->sitd_status); 1305 1306 if (!(status & EHCI_SITD_ACTIVE)) { 1307 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1308 goto transferred; 1309 } 1310 } else if (methods == &ehci_device_isoc_hs_methods) { 1311 ehci_itd_t *td; 1312 1313 /* isochronous high speed transfer */ 1314 1315 td = xfer->td_transfer_last; 1316 usb2_pc_cpu_invalidate(td->page_cache); 1317 status = 1318 td->itd_status[0] | td->itd_status[1] | 1319 td->itd_status[2] | td->itd_status[3] | 1320 td->itd_status[4] | td->itd_status[5] | 1321 td->itd_status[6] | td->itd_status[7]; 1322 1323 /* also check first transfer */ 1324 td = xfer->td_transfer_first; 1325 usb2_pc_cpu_invalidate(td->page_cache); 1326 status |= 1327 td->itd_status[0] | td->itd_status[1] | 1328 td->itd_status[2] | td->itd_status[3] | 1329 td->itd_status[4] | td->itd_status[5] | 1330 td->itd_status[6] | td->itd_status[7]; 1331 1332 /* if no transactions are active we continue */ 1333 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1334 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1335 goto transferred; 1336 } 1337 } else { 1338 ehci_qtd_t *td; 1339 1340 /* non-isochronous transfer */ 1341 1342 /* 1343 * check whether there is an error somewhere in the middle, 1344 * or whether there was a short packet (SPD and not ACTIVE) 1345 */ 1346 td = xfer->td_transfer_cache; 1347 1348 while (1) { 1349 usb2_pc_cpu_invalidate(td->page_cache); 1350 status = hc32toh(sc, td->qtd_status); 1351 1352 /* 1353 * if there is an active TD the transfer isn't done 1354 */ 1355 if (status & EHCI_QTD_ACTIVE) { 1356 /* update cache */ 1357 xfer->td_transfer_cache = td; 1358 goto done; 1359 } 1360 /* 1361 * last transfer descriptor makes the transfer done 1362 */ 1363 if (((void *)td) == xfer->td_transfer_last) { 1364 break; 1365 } 1366 /* 1367 * any kind of error makes the transfer done 1368 */ 1369 if (status & EHCI_QTD_HALTED) { 1370 break; 1371 } 1372 /* 1373 * if there is no alternate next transfer, a short 1374 * packet also makes the transfer done 1375 */ 1376 if (EHCI_QTD_GET_BYTES(status)) { 1377 if (xfer->flags_int.short_frames_ok) { 1378 /* follow alt next */ 1379 if (td->alt_next) { 1380 td = td->alt_next; 1381 continue; 1382 } 1383 } 1384 /* transfer is done */ 1385 break; 1386 } 1387 td = td->obj_next; 1388 } 1389 ehci_non_isoc_done(xfer); 1390 goto transferred; 1391 } 1392 1393 done: 1394 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1395 return (0); 1396 1397 transferred: 1398 return (1); 1399 } 1400 1401 static void 1402 ehci_pcd_enable(ehci_softc_t *sc) 1403 { 1404 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1405 1406 sc->sc_eintrs |= EHCI_STS_PCD; 1407 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1408 1409 /* acknowledge any PCD interrupt */ 1410 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1411 1412 ehci_root_intr(sc); 1413 } 1414 1415 static void 1416 ehci_interrupt_poll(ehci_softc_t *sc) 1417 { 1418 struct usb2_xfer *xfer; 1419 1420 repeat: 1421 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1422 /* 1423 * check if transfer is transferred 1424 */ 1425 if (ehci_check_transfer(xfer)) { 1426 /* queue has been modified */ 1427 goto repeat; 1428 } 1429 } 1430 } 1431 1432 /*------------------------------------------------------------------------* 1433 * ehci_interrupt - EHCI interrupt handler 1434 * 1435 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1436 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1437 * is present ! 1438 *------------------------------------------------------------------------*/ 1439 void 1440 ehci_interrupt(ehci_softc_t *sc) 1441 { 1442 uint32_t status; 1443 1444 USB_BUS_LOCK(&sc->sc_bus); 1445 1446 DPRINTFN(16, "real interrupt\n"); 1447 1448 #if USB_DEBUG 1449 if (ehcidebug > 15) { 1450 ehci_dump_regs(sc); 1451 } 1452 #endif 1453 1454 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1455 if (status == 0) { 1456 /* the interrupt was not for us */ 1457 goto done; 1458 } 1459 if (!(status & sc->sc_eintrs)) { 1460 goto done; 1461 } 1462 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1463 1464 status &= sc->sc_eintrs; 1465 1466 if (status & EHCI_STS_HSE) { 1467 printf("%s: unrecoverable error, " 1468 "controller halted\n", __FUNCTION__); 1469 #if USB_DEBUG 1470 ehci_dump_regs(sc); 1471 ehci_dump_isoc(sc); 1472 #endif 1473 } 1474 if (status & EHCI_STS_PCD) { 1475 /* 1476 * Disable PCD interrupt for now, because it will be 1477 * on until the port has been reset. 1478 */ 1479 sc->sc_eintrs &= ~EHCI_STS_PCD; 1480 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1481 1482 ehci_root_intr(sc); 1483 1484 /* do not allow RHSC interrupts > 1 per second */ 1485 usb2_callout_reset(&sc->sc_tmo_pcd, hz, 1486 (void *)&ehci_pcd_enable, sc); 1487 } 1488 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1489 1490 if (status != 0) { 1491 /* block unprocessed interrupts */ 1492 sc->sc_eintrs &= ~status; 1493 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1494 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1495 } 1496 /* poll all the USB transfers */ 1497 ehci_interrupt_poll(sc); 1498 1499 done: 1500 USB_BUS_UNLOCK(&sc->sc_bus); 1501 } 1502 1503 /* 1504 * called when a request does not complete 1505 */ 1506 static void 1507 ehci_timeout(void *arg) 1508 { 1509 struct usb2_xfer *xfer = arg; 1510 1511 DPRINTF("xfer=%p\n", xfer); 1512 1513 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1514 1515 /* transfer is transferred */ 1516 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1517 } 1518 1519 static void 1520 ehci_do_poll(struct usb2_bus *bus) 1521 { 1522 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1523 1524 USB_BUS_LOCK(&sc->sc_bus); 1525 ehci_interrupt_poll(sc); 1526 USB_BUS_UNLOCK(&sc->sc_bus); 1527 } 1528 1529 static void 1530 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1531 { 1532 struct usb2_page_search buf_res; 1533 ehci_qtd_t *td; 1534 ehci_qtd_t *td_next; 1535 ehci_qtd_t *td_alt_next; 1536 uint32_t qtd_altnext; 1537 uint32_t buf_offset; 1538 uint32_t average; 1539 uint32_t len_old; 1540 uint32_t terminate; 1541 uint8_t shortpkt_old; 1542 uint8_t precompute; 1543 1544 terminate = htohc32(temp->sc, EHCI_LINK_TERMINATE); 1545 qtd_altnext = terminate; 1546 td_alt_next = NULL; 1547 buf_offset = 0; 1548 shortpkt_old = temp->shortpkt; 1549 len_old = temp->len; 1550 precompute = 1; 1551 1552 restart: 1553 1554 td = temp->td; 1555 td_next = temp->td_next; 1556 1557 while (1) { 1558 1559 if (temp->len == 0) { 1560 1561 if (temp->shortpkt) { 1562 break; 1563 } 1564 /* send a Zero Length Packet, ZLP, last */ 1565 1566 temp->shortpkt = 1; 1567 average = 0; 1568 1569 } else { 1570 1571 average = temp->average; 1572 1573 if (temp->len < average) { 1574 if (temp->len % temp->max_frame_size) { 1575 temp->shortpkt = 1; 1576 } 1577 average = temp->len; 1578 } 1579 } 1580 1581 if (td_next == NULL) { 1582 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1583 } 1584 /* get next TD */ 1585 1586 td = td_next; 1587 td_next = td->obj_next; 1588 1589 /* check if we are pre-computing */ 1590 1591 if (precompute) { 1592 1593 /* update remaining length */ 1594 1595 temp->len -= average; 1596 1597 continue; 1598 } 1599 /* fill out current TD */ 1600 1601 td->qtd_status = 1602 temp->qtd_status | 1603 htohc32(temp->sc, EHCI_QTD_SET_BYTES(average)); 1604 1605 if (average == 0) { 1606 1607 if (temp->auto_data_toggle == 0) { 1608 1609 /* update data toggle, ZLP case */ 1610 1611 temp->qtd_status ^= 1612 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1613 } 1614 td->len = 0; 1615 1616 td->qtd_buffer[0] = 0; 1617 td->qtd_buffer_hi[0] = 0; 1618 1619 td->qtd_buffer[1] = 0; 1620 td->qtd_buffer_hi[1] = 0; 1621 1622 } else { 1623 1624 uint8_t x; 1625 1626 if (temp->auto_data_toggle == 0) { 1627 1628 /* update data toggle */ 1629 1630 if (((average + temp->max_frame_size - 1) / 1631 temp->max_frame_size) & 1) { 1632 temp->qtd_status ^= 1633 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1634 } 1635 } 1636 td->len = average; 1637 1638 /* update remaining length */ 1639 1640 temp->len -= average; 1641 1642 /* fill out buffer pointers */ 1643 1644 usb2_get_page(temp->pc, buf_offset, &buf_res); 1645 td->qtd_buffer[0] = 1646 htohc32(temp->sc, buf_res.physaddr); 1647 td->qtd_buffer_hi[0] = 0; 1648 1649 x = 1; 1650 1651 while (average > EHCI_PAGE_SIZE) { 1652 average -= EHCI_PAGE_SIZE; 1653 buf_offset += EHCI_PAGE_SIZE; 1654 usb2_get_page(temp->pc, buf_offset, &buf_res); 1655 td->qtd_buffer[x] = 1656 htohc32(temp->sc, 1657 buf_res.physaddr & (~0xFFF)); 1658 td->qtd_buffer_hi[x] = 0; 1659 x++; 1660 } 1661 1662 /* 1663 * NOTE: The "average" variable is never zero after 1664 * exiting the loop above ! 1665 * 1666 * NOTE: We have to subtract one from the offset to 1667 * ensure that we are computing the physical address 1668 * of a valid page ! 1669 */ 1670 buf_offset += average; 1671 usb2_get_page(temp->pc, buf_offset - 1, &buf_res); 1672 td->qtd_buffer[x] = 1673 htohc32(temp->sc, 1674 buf_res.physaddr & (~0xFFF)); 1675 td->qtd_buffer_hi[x] = 0; 1676 } 1677 1678 if (td_next) { 1679 /* link the current TD with the next one */ 1680 td->qtd_next = td_next->qtd_self; 1681 } 1682 td->qtd_altnext = qtd_altnext; 1683 td->alt_next = td_alt_next; 1684 1685 usb2_pc_cpu_flush(td->page_cache); 1686 } 1687 1688 if (precompute) { 1689 precompute = 0; 1690 1691 /* setup alt next pointer, if any */ 1692 if (temp->last_frame) { 1693 td_alt_next = NULL; 1694 qtd_altnext = terminate; 1695 } else { 1696 /* we use this field internally */ 1697 td_alt_next = td_next; 1698 if (temp->setup_alt_next) { 1699 qtd_altnext = td_next->qtd_self; 1700 } else { 1701 qtd_altnext = terminate; 1702 } 1703 } 1704 1705 /* restore */ 1706 temp->shortpkt = shortpkt_old; 1707 temp->len = len_old; 1708 goto restart; 1709 } 1710 temp->td = td; 1711 temp->td_next = td_next; 1712 } 1713 1714 static void 1715 ehci_setup_standard_chain(struct usb2_xfer *xfer, ehci_qh_t **qh_last) 1716 { 1717 struct ehci_std_temp temp; 1718 struct usb2_pipe_methods *methods; 1719 ehci_qh_t *qh; 1720 ehci_qtd_t *td; 1721 uint32_t qh_endp; 1722 uint32_t qh_endphub; 1723 uint32_t x; 1724 1725 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1726 xfer->address, UE_GET_ADDR(xfer->endpoint), 1727 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1728 1729 temp.average = xfer->max_hc_frame_size; 1730 temp.max_frame_size = xfer->max_frame_size; 1731 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1732 1733 /* toggle the DMA set we are using */ 1734 xfer->flags_int.curr_dma_set ^= 1; 1735 1736 /* get next DMA set */ 1737 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1738 1739 xfer->td_transfer_first = td; 1740 xfer->td_transfer_cache = td; 1741 1742 temp.td = NULL; 1743 temp.td_next = td; 1744 temp.qtd_status = 0; 1745 temp.last_frame = 0; 1746 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1747 1748 if (xfer->flags_int.control_xfr) { 1749 if (xfer->pipe->toggle_next) { 1750 /* DATA1 is next */ 1751 temp.qtd_status |= 1752 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1753 } 1754 temp.auto_data_toggle = 0; 1755 } else { 1756 temp.auto_data_toggle = 1; 1757 } 1758 1759 if (usb2_get_speed(xfer->xroot->udev) != USB_SPEED_HIGH) { 1760 /* max 3 retries */ 1761 temp.qtd_status |= 1762 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1763 } 1764 /* check if we should prepend a setup message */ 1765 1766 if (xfer->flags_int.control_xfr) { 1767 if (xfer->flags_int.control_hdr) { 1768 1769 temp.qtd_status &= 1770 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1771 temp.qtd_status |= htohc32(temp.sc, 1772 EHCI_QTD_ACTIVE | 1773 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1774 EHCI_QTD_SET_TOGGLE(0)); 1775 1776 temp.len = xfer->frlengths[0]; 1777 temp.pc = xfer->frbuffers + 0; 1778 temp.shortpkt = temp.len ? 1 : 0; 1779 /* check for last frame */ 1780 if (xfer->nframes == 1) { 1781 /* no STATUS stage yet, SETUP is last */ 1782 if (xfer->flags_int.control_act) { 1783 temp.last_frame = 1; 1784 temp.setup_alt_next = 0; 1785 } 1786 } 1787 ehci_setup_standard_chain_sub(&temp); 1788 } 1789 x = 1; 1790 } else { 1791 x = 0; 1792 } 1793 1794 while (x != xfer->nframes) { 1795 1796 /* DATA0 / DATA1 message */ 1797 1798 temp.len = xfer->frlengths[x]; 1799 temp.pc = xfer->frbuffers + x; 1800 1801 x++; 1802 1803 if (x == xfer->nframes) { 1804 if (xfer->flags_int.control_xfr) { 1805 /* no STATUS stage yet, DATA is last */ 1806 if (xfer->flags_int.control_act) { 1807 temp.last_frame = 1; 1808 temp.setup_alt_next = 0; 1809 } 1810 } else { 1811 temp.last_frame = 1; 1812 temp.setup_alt_next = 0; 1813 } 1814 } 1815 /* keep previous data toggle and error count */ 1816 1817 temp.qtd_status &= 1818 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1819 EHCI_QTD_SET_TOGGLE(1)); 1820 1821 if (temp.len == 0) { 1822 1823 /* make sure that we send an USB packet */ 1824 1825 temp.shortpkt = 0; 1826 1827 } else { 1828 1829 /* regular data transfer */ 1830 1831 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1832 } 1833 1834 /* set endpoint direction */ 1835 1836 temp.qtd_status |= 1837 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 1838 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1839 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1840 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1841 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1842 1843 ehci_setup_standard_chain_sub(&temp); 1844 } 1845 1846 /* check if we should append a status stage */ 1847 1848 if (xfer->flags_int.control_xfr && 1849 !xfer->flags_int.control_act) { 1850 1851 /* 1852 * Send a DATA1 message and invert the current endpoint 1853 * direction. 1854 */ 1855 1856 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1857 EHCI_QTD_SET_TOGGLE(1)); 1858 temp.qtd_status |= 1859 (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) ? 1860 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1861 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1862 EHCI_QTD_SET_TOGGLE(1)) : 1863 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1864 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1865 EHCI_QTD_SET_TOGGLE(1)); 1866 1867 temp.len = 0; 1868 temp.pc = NULL; 1869 temp.shortpkt = 0; 1870 temp.last_frame = 1; 1871 temp.setup_alt_next = 0; 1872 1873 ehci_setup_standard_chain_sub(&temp); 1874 } 1875 td = temp.td; 1876 1877 /* the last TD terminates the transfer: */ 1878 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1879 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1880 td->qtd_status |= htohc32(temp.sc, EHCI_QTD_IOC); 1881 1882 usb2_pc_cpu_flush(td->page_cache); 1883 1884 /* must have at least one frame! */ 1885 1886 xfer->td_transfer_last = td; 1887 1888 #if USB_DEBUG 1889 if (ehcidebug > 8) { 1890 DPRINTF("nexttog=%d; data before transfer:\n", 1891 xfer->pipe->toggle_next); 1892 ehci_dump_sqtds(temp.sc, 1893 xfer->td_transfer_first); 1894 } 1895 #endif 1896 1897 methods = xfer->pipe->methods; 1898 1899 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1900 1901 /* the "qh_link" field is filled when the QH is added */ 1902 1903 qh_endp = 1904 (EHCI_QH_SET_ADDR(xfer->address) | 1905 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpoint)) | 1906 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1907 1908 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1909 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | 1910 EHCI_QH_DTC); 1911 if (methods != &ehci_device_intr_methods) 1912 qh_endp |= EHCI_QH_SET_NRL(8); 1913 } else { 1914 1915 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1916 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL) | 1917 EHCI_QH_DTC); 1918 } else { 1919 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW) | 1920 EHCI_QH_DTC); 1921 } 1922 1923 if (methods == &ehci_device_ctrl_methods) { 1924 qh_endp |= EHCI_QH_CTL; 1925 } 1926 if (methods != &ehci_device_intr_methods) { 1927 /* Only try one time per microframe! */ 1928 qh_endp |= EHCI_QH_SET_NRL(1); 1929 } 1930 } 1931 1932 qh->qh_endp = htohc32(temp.sc, qh_endp); 1933 1934 qh_endphub = 1935 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1936 EHCI_QH_SET_CMASK(xfer->usb2_cmask) | 1937 EHCI_QH_SET_SMASK(xfer->usb2_smask) | 1938 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1939 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1940 1941 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 1942 qh->qh_curqtd = htohc32(temp.sc, 0); 1943 1944 /* fill the overlay qTD */ 1945 qh->qh_qtd.qtd_status = htohc32(temp.sc, 0); 1946 1947 if (temp.auto_data_toggle) { 1948 1949 /* let the hardware compute the data toggle */ 1950 1951 qh->qh_endp &= htohc32(temp.sc, ~EHCI_QH_DTC); 1952 1953 if (xfer->pipe->toggle_next) { 1954 /* DATA1 is next */ 1955 qh->qh_qtd.qtd_status |= 1956 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1957 } 1958 } 1959 td = xfer->td_transfer_first; 1960 1961 qh->qh_qtd.qtd_next = td->qtd_self; 1962 qh->qh_qtd.qtd_altnext = 1963 htohc32(temp.sc, EHCI_LINK_TERMINATE); 1964 1965 usb2_pc_cpu_flush(qh->page_cache); 1966 1967 if (xfer->xroot->udev->pwr_save.suspended == 0) { 1968 EHCI_APPEND_QH(qh, *qh_last); 1969 } 1970 } 1971 1972 static void 1973 ehci_root_intr(ehci_softc_t *sc) 1974 { 1975 uint16_t i; 1976 uint16_t m; 1977 1978 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1979 1980 /* clear any old interrupt data */ 1981 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 1982 1983 /* set bits */ 1984 m = (sc->sc_noport + 1); 1985 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1986 m = (8 * sizeof(sc->sc_hub_idata)); 1987 } 1988 for (i = 1; i < m; i++) { 1989 /* pick out CHANGE bits from the status register */ 1990 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 1991 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1992 DPRINTF("port %d changed\n", i); 1993 } 1994 } 1995 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1996 sizeof(sc->sc_hub_idata)); 1997 } 1998 1999 static void 2000 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb2_xfer *xfer) 2001 { 2002 uint32_t nframes = xfer->nframes; 2003 uint32_t status; 2004 uint32_t *plen = xfer->frlengths; 2005 uint16_t len = 0; 2006 ehci_sitd_t *td = xfer->td_transfer_first; 2007 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2008 2009 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 2010 xfer, xfer->pipe); 2011 2012 while (nframes--) { 2013 if (td == NULL) { 2014 panic("%s:%d: out of TD's\n", 2015 __FUNCTION__, __LINE__); 2016 } 2017 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2018 pp_last = &sc->sc_isoc_fs_p_last[0]; 2019 } 2020 #if USB_DEBUG 2021 if (ehcidebug > 15) { 2022 DPRINTF("isoc FS-TD\n"); 2023 ehci_dump_sitd(sc, td); 2024 } 2025 #endif 2026 usb2_pc_cpu_invalidate(td->page_cache); 2027 status = hc32toh(sc, td->sitd_status); 2028 2029 len = EHCI_SITD_GET_LEN(status); 2030 2031 if (*plen >= len) { 2032 len = *plen - len; 2033 } else { 2034 len = 0; 2035 } 2036 2037 *plen = len; 2038 2039 /* remove FS-TD from schedule */ 2040 EHCI_REMOVE_FS_TD(td, *pp_last); 2041 2042 pp_last++; 2043 plen++; 2044 td = td->obj_next; 2045 } 2046 2047 xfer->aframes = xfer->nframes; 2048 } 2049 2050 static void 2051 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb2_xfer *xfer) 2052 { 2053 uint32_t nframes = xfer->nframes; 2054 uint32_t status; 2055 uint32_t *plen = xfer->frlengths; 2056 uint16_t len = 0; 2057 uint8_t td_no = 0; 2058 ehci_itd_t *td = xfer->td_transfer_first; 2059 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2060 2061 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 2062 xfer, xfer->pipe); 2063 2064 while (nframes--) { 2065 if (td == NULL) { 2066 panic("%s:%d: out of TD's\n", 2067 __FUNCTION__, __LINE__); 2068 } 2069 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2070 pp_last = &sc->sc_isoc_hs_p_last[0]; 2071 } 2072 #if USB_DEBUG 2073 if (ehcidebug > 15) { 2074 DPRINTF("isoc HS-TD\n"); 2075 ehci_dump_itd(sc, td); 2076 } 2077 #endif 2078 2079 usb2_pc_cpu_invalidate(td->page_cache); 2080 status = hc32toh(sc, td->itd_status[td_no]); 2081 2082 len = EHCI_ITD_GET_LEN(status); 2083 2084 if (*plen >= len) { 2085 /* 2086 * The length is valid. NOTE: The complete 2087 * length is written back into the status 2088 * field, and not the remainder like with 2089 * other transfer descriptor types. 2090 */ 2091 } else { 2092 /* Invalid length - truncate */ 2093 len = 0; 2094 } 2095 2096 *plen = len; 2097 2098 plen++; 2099 td_no++; 2100 2101 if ((td_no == 8) || (nframes == 0)) { 2102 /* remove HS-TD from schedule */ 2103 EHCI_REMOVE_HS_TD(td, *pp_last); 2104 pp_last++; 2105 2106 td_no = 0; 2107 td = td->obj_next; 2108 } 2109 } 2110 xfer->aframes = xfer->nframes; 2111 } 2112 2113 /* NOTE: "done" can be run two times in a row, 2114 * from close and from interrupt 2115 */ 2116 static void 2117 ehci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 2118 { 2119 struct usb2_pipe_methods *methods = xfer->pipe->methods; 2120 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2121 2122 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2123 2124 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 2125 xfer, xfer->pipe, error); 2126 2127 if ((methods == &ehci_device_bulk_methods) || 2128 (methods == &ehci_device_ctrl_methods)) { 2129 #if USB_DEBUG 2130 if (ehcidebug > 8) { 2131 DPRINTF("nexttog=%d; data after transfer:\n", 2132 xfer->pipe->toggle_next); 2133 ehci_dump_sqtds(sc, 2134 xfer->td_transfer_first); 2135 } 2136 #endif 2137 2138 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2139 sc->sc_async_p_last); 2140 } 2141 if (methods == &ehci_device_intr_methods) { 2142 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2143 sc->sc_intr_p_last[xfer->qh_pos]); 2144 } 2145 /* 2146 * Only finish isochronous transfers once which will update 2147 * "xfer->frlengths". 2148 */ 2149 if (xfer->td_transfer_first && 2150 xfer->td_transfer_last) { 2151 if (methods == &ehci_device_isoc_fs_methods) { 2152 ehci_isoc_fs_done(sc, xfer); 2153 } 2154 if (methods == &ehci_device_isoc_hs_methods) { 2155 ehci_isoc_hs_done(sc, xfer); 2156 } 2157 xfer->td_transfer_first = NULL; 2158 xfer->td_transfer_last = NULL; 2159 } 2160 /* dequeue transfer and start next transfer */ 2161 usb2_transfer_done(xfer, error); 2162 } 2163 2164 /*------------------------------------------------------------------------* 2165 * ehci bulk support 2166 *------------------------------------------------------------------------*/ 2167 static void 2168 ehci_device_bulk_open(struct usb2_xfer *xfer) 2169 { 2170 return; 2171 } 2172 2173 static void 2174 ehci_device_bulk_close(struct usb2_xfer *xfer) 2175 { 2176 ehci_device_done(xfer, USB_ERR_CANCELLED); 2177 } 2178 2179 static void 2180 ehci_device_bulk_enter(struct usb2_xfer *xfer) 2181 { 2182 return; 2183 } 2184 2185 static void 2186 ehci_device_bulk_start(struct usb2_xfer *xfer) 2187 { 2188 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2189 uint32_t temp; 2190 2191 /* setup TD's and QH */ 2192 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2193 2194 /* put transfer on interrupt queue */ 2195 ehci_transfer_intr_enqueue(xfer); 2196 2197 /* XXX Performance quirk: Some Host Controllers have a too low 2198 * interrupt rate. Issue an IAAD to stimulate the Host 2199 * Controller after queueing the BULK transfer. 2200 */ 2201 temp = EOREAD4(sc, EHCI_USBCMD); 2202 if (!(temp & EHCI_CMD_IAAD)) 2203 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2204 } 2205 2206 struct usb2_pipe_methods ehci_device_bulk_methods = 2207 { 2208 .open = ehci_device_bulk_open, 2209 .close = ehci_device_bulk_close, 2210 .enter = ehci_device_bulk_enter, 2211 .start = ehci_device_bulk_start, 2212 }; 2213 2214 /*------------------------------------------------------------------------* 2215 * ehci control support 2216 *------------------------------------------------------------------------*/ 2217 static void 2218 ehci_device_ctrl_open(struct usb2_xfer *xfer) 2219 { 2220 return; 2221 } 2222 2223 static void 2224 ehci_device_ctrl_close(struct usb2_xfer *xfer) 2225 { 2226 ehci_device_done(xfer, USB_ERR_CANCELLED); 2227 } 2228 2229 static void 2230 ehci_device_ctrl_enter(struct usb2_xfer *xfer) 2231 { 2232 return; 2233 } 2234 2235 static void 2236 ehci_device_ctrl_start(struct usb2_xfer *xfer) 2237 { 2238 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2239 2240 /* setup TD's and QH */ 2241 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2242 2243 /* put transfer on interrupt queue */ 2244 ehci_transfer_intr_enqueue(xfer); 2245 } 2246 2247 struct usb2_pipe_methods ehci_device_ctrl_methods = 2248 { 2249 .open = ehci_device_ctrl_open, 2250 .close = ehci_device_ctrl_close, 2251 .enter = ehci_device_ctrl_enter, 2252 .start = ehci_device_ctrl_start, 2253 }; 2254 2255 /*------------------------------------------------------------------------* 2256 * ehci interrupt support 2257 *------------------------------------------------------------------------*/ 2258 static void 2259 ehci_device_intr_open(struct usb2_xfer *xfer) 2260 { 2261 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2262 uint16_t best; 2263 uint16_t bit; 2264 uint16_t x; 2265 uint8_t slot; 2266 2267 /* Allocate a microframe slot first: */ 2268 2269 slot = usb2_intr_schedule_adjust 2270 (xfer->xroot->udev, xfer->max_frame_size, USB_HS_MICRO_FRAMES_MAX); 2271 2272 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2273 xfer->usb2_uframe = slot; 2274 xfer->usb2_smask = (1 << slot) & 0xFF; 2275 xfer->usb2_cmask = 0; 2276 } else { 2277 xfer->usb2_uframe = slot; 2278 xfer->usb2_smask = (1 << slot) & 0x3F; 2279 xfer->usb2_cmask = (-(4 << slot)) & 0xFE; 2280 } 2281 2282 /* 2283 * Find the best QH position corresponding to the given interval: 2284 */ 2285 2286 best = 0; 2287 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2288 while (bit) { 2289 if (xfer->interval >= bit) { 2290 x = bit; 2291 best = bit; 2292 while (x & bit) { 2293 if (sc->sc_intr_stat[x] < 2294 sc->sc_intr_stat[best]) { 2295 best = x; 2296 } 2297 x++; 2298 } 2299 break; 2300 } 2301 bit >>= 1; 2302 } 2303 2304 sc->sc_intr_stat[best]++; 2305 xfer->qh_pos = best; 2306 2307 DPRINTFN(3, "best=%d interval=%d\n", 2308 best, xfer->interval); 2309 } 2310 2311 static void 2312 ehci_device_intr_close(struct usb2_xfer *xfer) 2313 { 2314 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2315 uint8_t slot; 2316 2317 slot = usb2_intr_schedule_adjust 2318 (xfer->xroot->udev, -(xfer->max_frame_size), xfer->usb2_uframe); 2319 2320 sc->sc_intr_stat[xfer->qh_pos]--; 2321 2322 ehci_device_done(xfer, USB_ERR_CANCELLED); 2323 } 2324 2325 static void 2326 ehci_device_intr_enter(struct usb2_xfer *xfer) 2327 { 2328 return; 2329 } 2330 2331 static void 2332 ehci_device_intr_start(struct usb2_xfer *xfer) 2333 { 2334 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2335 2336 /* setup TD's and QH */ 2337 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2338 2339 /* put transfer on interrupt queue */ 2340 ehci_transfer_intr_enqueue(xfer); 2341 } 2342 2343 struct usb2_pipe_methods ehci_device_intr_methods = 2344 { 2345 .open = ehci_device_intr_open, 2346 .close = ehci_device_intr_close, 2347 .enter = ehci_device_intr_enter, 2348 .start = ehci_device_intr_start, 2349 }; 2350 2351 /*------------------------------------------------------------------------* 2352 * ehci full speed isochronous support 2353 *------------------------------------------------------------------------*/ 2354 static void 2355 ehci_device_isoc_fs_open(struct usb2_xfer *xfer) 2356 { 2357 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2358 ehci_sitd_t *td; 2359 uint32_t sitd_portaddr; 2360 uint8_t ds; 2361 2362 sitd_portaddr = 2363 EHCI_SITD_SET_ADDR(xfer->address) | 2364 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpoint)) | 2365 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2366 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2367 2368 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 2369 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2370 } 2371 sitd_portaddr = htohc32(sc, sitd_portaddr); 2372 2373 /* initialize all TD's */ 2374 2375 for (ds = 0; ds != 2; ds++) { 2376 2377 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2378 2379 td->sitd_portaddr = sitd_portaddr; 2380 2381 /* 2382 * TODO: make some kind of automatic 2383 * SMASK/CMASK selection based on micro-frame 2384 * usage 2385 * 2386 * micro-frame usage (8 microframes per 1ms) 2387 */ 2388 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2389 2390 usb2_pc_cpu_flush(td->page_cache); 2391 } 2392 } 2393 } 2394 2395 static void 2396 ehci_device_isoc_fs_close(struct usb2_xfer *xfer) 2397 { 2398 ehci_device_done(xfer, USB_ERR_CANCELLED); 2399 } 2400 2401 static void 2402 ehci_device_isoc_fs_enter(struct usb2_xfer *xfer) 2403 { 2404 struct usb2_page_search buf_res; 2405 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2406 struct usb2_fs_isoc_schedule *fss_start; 2407 struct usb2_fs_isoc_schedule *fss_end; 2408 struct usb2_fs_isoc_schedule *fss; 2409 ehci_sitd_t *td; 2410 ehci_sitd_t *td_last = NULL; 2411 ehci_sitd_t **pp_last; 2412 uint32_t *plen; 2413 uint32_t buf_offset; 2414 uint32_t nframes; 2415 uint32_t temp; 2416 uint32_t sitd_mask; 2417 uint16_t tlen; 2418 uint8_t sa; 2419 uint8_t sb; 2420 uint8_t error; 2421 2422 #if USB_DEBUG 2423 uint8_t once = 1; 2424 2425 #endif 2426 2427 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2428 xfer, xfer->pipe->isoc_next, xfer->nframes); 2429 2430 /* get the current frame index */ 2431 2432 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2433 2434 /* 2435 * check if the frame index is within the window where the frames 2436 * will be inserted 2437 */ 2438 buf_offset = (nframes - xfer->pipe->isoc_next) & 2439 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2440 2441 if ((xfer->pipe->is_synced == 0) || 2442 (buf_offset < xfer->nframes)) { 2443 /* 2444 * If there is data underflow or the pipe queue is empty we 2445 * schedule the transfer a few frames ahead of the current 2446 * frame position. Else two isochronous transfers might 2447 * overlap. 2448 */ 2449 xfer->pipe->isoc_next = (nframes + 3) & 2450 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2451 xfer->pipe->is_synced = 1; 2452 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2453 } 2454 /* 2455 * compute how many milliseconds the insertion is ahead of the 2456 * current frame position: 2457 */ 2458 buf_offset = (xfer->pipe->isoc_next - nframes) & 2459 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2460 2461 /* 2462 * pre-compute when the isochronous transfer will be finished: 2463 */ 2464 xfer->isoc_time_complete = 2465 usb2_fs_isoc_schedule_isoc_time_expand 2466 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset + 2467 xfer->nframes; 2468 2469 /* get the real number of frames */ 2470 2471 nframes = xfer->nframes; 2472 2473 buf_offset = 0; 2474 2475 plen = xfer->frlengths; 2476 2477 /* toggle the DMA set we are using */ 2478 xfer->flags_int.curr_dma_set ^= 1; 2479 2480 /* get next DMA set */ 2481 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2482 xfer->td_transfer_first = td; 2483 2484 pp_last = &sc->sc_isoc_fs_p_last[xfer->pipe->isoc_next]; 2485 2486 /* store starting position */ 2487 2488 xfer->qh_pos = xfer->pipe->isoc_next; 2489 2490 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX); 2491 2492 while (nframes--) { 2493 if (td == NULL) { 2494 panic("%s:%d: out of TD's\n", 2495 __FUNCTION__, __LINE__); 2496 } 2497 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2498 pp_last = &sc->sc_isoc_fs_p_last[0]; 2499 } 2500 if (fss >= fss_end) { 2501 fss = fss_start; 2502 } 2503 /* reuse sitd_portaddr and sitd_back from last transfer */ 2504 2505 if (*plen > xfer->max_frame_size) { 2506 #if USB_DEBUG 2507 if (once) { 2508 once = 0; 2509 printf("%s: frame length(%d) exceeds %d " 2510 "bytes (frame truncated)\n", 2511 __FUNCTION__, *plen, 2512 xfer->max_frame_size); 2513 } 2514 #endif 2515 *plen = xfer->max_frame_size; 2516 } 2517 /* 2518 * We currently don't care if the ISOCHRONOUS schedule is 2519 * full! 2520 */ 2521 error = usb2_fs_isoc_schedule_alloc(fss, &sa, *plen); 2522 if (error) { 2523 /* 2524 * The FULL speed schedule is FULL! Set length 2525 * to zero. 2526 */ 2527 *plen = 0; 2528 } 2529 if (*plen) { 2530 /* 2531 * only call "usb2_get_page()" when we have a 2532 * non-zero length 2533 */ 2534 usb2_get_page(xfer->frbuffers, buf_offset, &buf_res); 2535 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2536 buf_offset += *plen; 2537 /* 2538 * NOTE: We need to subtract one from the offset so 2539 * that we are on a valid page! 2540 */ 2541 usb2_get_page(xfer->frbuffers, buf_offset - 1, 2542 &buf_res); 2543 temp = buf_res.physaddr & ~0xFFF; 2544 } else { 2545 td->sitd_bp[0] = 0; 2546 temp = 0; 2547 } 2548 2549 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) { 2550 tlen = *plen; 2551 if (tlen <= 188) { 2552 temp |= 1; /* T-count = 1, TP = ALL */ 2553 tlen = 1; 2554 } else { 2555 tlen += 187; 2556 tlen /= 188; 2557 temp |= tlen; /* T-count = [1..6] */ 2558 temp |= 8; /* TP = Begin */ 2559 } 2560 2561 tlen += sa; 2562 2563 if (tlen >= 8) { 2564 sb = 0; 2565 } else { 2566 sb = (1 << tlen); 2567 } 2568 2569 sa = (1 << sa); 2570 sa = (sb - sa) & 0x3F; 2571 sb = 0; 2572 } else { 2573 sb = (-(4 << sa)) & 0xFE; 2574 sa = (1 << sa) & 0x3F; 2575 } 2576 2577 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2578 EHCI_SITD_SET_CMASK(sb)); 2579 2580 td->sitd_bp[1] = htohc32(sc, temp); 2581 2582 td->sitd_mask = htohc32(sc, sitd_mask); 2583 2584 if (nframes == 0) { 2585 td->sitd_status = htohc32(sc, 2586 EHCI_SITD_IOC | 2587 EHCI_SITD_ACTIVE | 2588 EHCI_SITD_SET_LEN(*plen)); 2589 } else { 2590 td->sitd_status = htohc32(sc, 2591 EHCI_SITD_ACTIVE | 2592 EHCI_SITD_SET_LEN(*plen)); 2593 } 2594 usb2_pc_cpu_flush(td->page_cache); 2595 2596 #if USB_DEBUG 2597 if (ehcidebug > 15) { 2598 DPRINTF("FS-TD %d\n", nframes); 2599 ehci_dump_sitd(sc, td); 2600 } 2601 #endif 2602 /* insert TD into schedule */ 2603 EHCI_APPEND_FS_TD(td, *pp_last); 2604 pp_last++; 2605 2606 plen++; 2607 fss++; 2608 td_last = td; 2609 td = td->obj_next; 2610 } 2611 2612 xfer->td_transfer_last = td_last; 2613 2614 /* update isoc_next */ 2615 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2616 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2617 } 2618 2619 static void 2620 ehci_device_isoc_fs_start(struct usb2_xfer *xfer) 2621 { 2622 /* put transfer on interrupt queue */ 2623 ehci_transfer_intr_enqueue(xfer); 2624 } 2625 2626 struct usb2_pipe_methods ehci_device_isoc_fs_methods = 2627 { 2628 .open = ehci_device_isoc_fs_open, 2629 .close = ehci_device_isoc_fs_close, 2630 .enter = ehci_device_isoc_fs_enter, 2631 .start = ehci_device_isoc_fs_start, 2632 }; 2633 2634 /*------------------------------------------------------------------------* 2635 * ehci high speed isochronous support 2636 *------------------------------------------------------------------------*/ 2637 static void 2638 ehci_device_isoc_hs_open(struct usb2_xfer *xfer) 2639 { 2640 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2641 ehci_itd_t *td; 2642 uint32_t temp; 2643 uint8_t ds; 2644 2645 /* initialize all TD's */ 2646 2647 for (ds = 0; ds != 2; ds++) { 2648 2649 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2650 2651 /* set TD inactive */ 2652 td->itd_status[0] = 0; 2653 td->itd_status[1] = 0; 2654 td->itd_status[2] = 0; 2655 td->itd_status[3] = 0; 2656 td->itd_status[4] = 0; 2657 td->itd_status[5] = 0; 2658 td->itd_status[6] = 0; 2659 td->itd_status[7] = 0; 2660 2661 /* set endpoint and address */ 2662 td->itd_bp[0] = htohc32(sc, 2663 EHCI_ITD_SET_ADDR(xfer->address) | 2664 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpoint))); 2665 2666 temp = 2667 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2668 2669 /* set direction */ 2670 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 2671 temp |= EHCI_ITD_SET_DIR_IN; 2672 } 2673 /* set maximum packet size */ 2674 td->itd_bp[1] = htohc32(sc, temp); 2675 2676 /* set transfer multiplier */ 2677 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2678 2679 usb2_pc_cpu_flush(td->page_cache); 2680 } 2681 } 2682 } 2683 2684 static void 2685 ehci_device_isoc_hs_close(struct usb2_xfer *xfer) 2686 { 2687 ehci_device_done(xfer, USB_ERR_CANCELLED); 2688 } 2689 2690 static void 2691 ehci_device_isoc_hs_enter(struct usb2_xfer *xfer) 2692 { 2693 struct usb2_page_search buf_res; 2694 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2695 ehci_itd_t *td; 2696 ehci_itd_t *td_last = NULL; 2697 ehci_itd_t **pp_last; 2698 bus_size_t page_addr; 2699 uint32_t *plen; 2700 uint32_t status; 2701 uint32_t buf_offset; 2702 uint32_t nframes; 2703 uint32_t itd_offset[8 + 1]; 2704 uint8_t x; 2705 uint8_t td_no; 2706 uint8_t page_no; 2707 2708 #if USB_DEBUG 2709 uint8_t once = 1; 2710 2711 #endif 2712 2713 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2714 xfer, xfer->pipe->isoc_next, xfer->nframes); 2715 2716 /* get the current frame index */ 2717 2718 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2719 2720 /* 2721 * check if the frame index is within the window where the frames 2722 * will be inserted 2723 */ 2724 buf_offset = (nframes - xfer->pipe->isoc_next) & 2725 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2726 2727 if ((xfer->pipe->is_synced == 0) || 2728 (buf_offset < ((xfer->nframes + 7) / 8))) { 2729 /* 2730 * If there is data underflow or the pipe queue is empty we 2731 * schedule the transfer a few frames ahead of the current 2732 * frame position. Else two isochronous transfers might 2733 * overlap. 2734 */ 2735 xfer->pipe->isoc_next = (nframes + 3) & 2736 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2737 xfer->pipe->is_synced = 1; 2738 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2739 } 2740 /* 2741 * compute how many milliseconds the insertion is ahead of the 2742 * current frame position: 2743 */ 2744 buf_offset = (xfer->pipe->isoc_next - nframes) & 2745 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2746 2747 /* 2748 * pre-compute when the isochronous transfer will be finished: 2749 */ 2750 xfer->isoc_time_complete = 2751 usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2752 ((xfer->nframes + 7) / 8); 2753 2754 /* get the real number of frames */ 2755 2756 nframes = xfer->nframes; 2757 2758 buf_offset = 0; 2759 td_no = 0; 2760 2761 plen = xfer->frlengths; 2762 2763 /* toggle the DMA set we are using */ 2764 xfer->flags_int.curr_dma_set ^= 1; 2765 2766 /* get next DMA set */ 2767 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2768 xfer->td_transfer_first = td; 2769 2770 pp_last = &sc->sc_isoc_hs_p_last[xfer->pipe->isoc_next]; 2771 2772 /* store starting position */ 2773 2774 xfer->qh_pos = xfer->pipe->isoc_next; 2775 2776 while (nframes--) { 2777 if (td == NULL) { 2778 panic("%s:%d: out of TD's\n", 2779 __FUNCTION__, __LINE__); 2780 } 2781 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2782 pp_last = &sc->sc_isoc_hs_p_last[0]; 2783 } 2784 /* range check */ 2785 if (*plen > xfer->max_frame_size) { 2786 #if USB_DEBUG 2787 if (once) { 2788 once = 0; 2789 printf("%s: frame length(%d) exceeds %d bytes " 2790 "(frame truncated)\n", 2791 __FUNCTION__, *plen, xfer->max_frame_size); 2792 } 2793 #endif 2794 *plen = xfer->max_frame_size; 2795 } 2796 status = (EHCI_ITD_SET_LEN(*plen) | 2797 EHCI_ITD_ACTIVE | 2798 EHCI_ITD_SET_PG(0)); 2799 td->itd_status[td_no] = htohc32(sc, status); 2800 itd_offset[td_no] = buf_offset; 2801 buf_offset += *plen; 2802 plen++; 2803 td_no++; 2804 2805 if ((td_no == 8) || (nframes == 0)) { 2806 2807 /* the rest of the transfers are not active, if any */ 2808 for (x = td_no; x != 8; x++) { 2809 td->itd_status[x] = 0; /* not active */ 2810 } 2811 2812 /* check if there is any data to be transferred */ 2813 if (itd_offset[0] != buf_offset) { 2814 page_no = 0; 2815 itd_offset[td_no] = buf_offset; 2816 2817 /* get first page offset */ 2818 usb2_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2819 /* get page address */ 2820 page_addr = buf_res.physaddr & ~0xFFF; 2821 /* update page address */ 2822 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2823 td->itd_bp[0] |= htohc32(sc, page_addr); 2824 2825 for (x = 0; x != td_no; x++) { 2826 /* set page number and page offset */ 2827 status = (EHCI_ITD_SET_PG(page_no) | 2828 (buf_res.physaddr & 0xFFF)); 2829 td->itd_status[x] |= htohc32(sc, status); 2830 2831 /* get next page offset */ 2832 if (itd_offset[x + 1] == buf_offset) { 2833 /* 2834 * We subtract one so that 2835 * we don't go off the last 2836 * page! 2837 */ 2838 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2839 } else { 2840 usb2_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2841 } 2842 2843 /* check if we need a new page */ 2844 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2845 /* new page needed */ 2846 page_addr = buf_res.physaddr & ~0xFFF; 2847 if (page_no == 6) { 2848 panic("%s: too many pages\n", __FUNCTION__); 2849 } 2850 page_no++; 2851 /* update page address */ 2852 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2853 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2854 } 2855 } 2856 } 2857 /* set IOC bit if we are complete */ 2858 if (nframes == 0) { 2859 td->itd_status[7] |= htohc32(sc, EHCI_ITD_IOC); 2860 } 2861 usb2_pc_cpu_flush(td->page_cache); 2862 #if USB_DEBUG 2863 if (ehcidebug > 15) { 2864 DPRINTF("HS-TD %d\n", nframes); 2865 ehci_dump_itd(sc, td); 2866 } 2867 #endif 2868 /* insert TD into schedule */ 2869 EHCI_APPEND_HS_TD(td, *pp_last); 2870 pp_last++; 2871 2872 td_no = 0; 2873 td_last = td; 2874 td = td->obj_next; 2875 } 2876 } 2877 2878 xfer->td_transfer_last = td_last; 2879 2880 /* update isoc_next */ 2881 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2882 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2883 } 2884 2885 static void 2886 ehci_device_isoc_hs_start(struct usb2_xfer *xfer) 2887 { 2888 /* put transfer on interrupt queue */ 2889 ehci_transfer_intr_enqueue(xfer); 2890 } 2891 2892 struct usb2_pipe_methods ehci_device_isoc_hs_methods = 2893 { 2894 .open = ehci_device_isoc_hs_open, 2895 .close = ehci_device_isoc_hs_close, 2896 .enter = ehci_device_isoc_hs_enter, 2897 .start = ehci_device_isoc_hs_start, 2898 }; 2899 2900 /*------------------------------------------------------------------------* 2901 * ehci root control support 2902 *------------------------------------------------------------------------* 2903 * Simulate a hardware hub by handling all the necessary requests. 2904 *------------------------------------------------------------------------*/ 2905 2906 static const 2907 struct usb2_device_descriptor ehci_devd = 2908 { 2909 sizeof(struct usb2_device_descriptor), 2910 UDESC_DEVICE, /* type */ 2911 {0x00, 0x02}, /* USB version */ 2912 UDCLASS_HUB, /* class */ 2913 UDSUBCLASS_HUB, /* subclass */ 2914 UDPROTO_HSHUBSTT, /* protocol */ 2915 64, /* max packet */ 2916 {0}, {0}, {0x00, 0x01}, /* device id */ 2917 1, 2, 0, /* string indicies */ 2918 1 /* # of configurations */ 2919 }; 2920 2921 static const 2922 struct usb2_device_qualifier ehci_odevd = 2923 { 2924 sizeof(struct usb2_device_qualifier), 2925 UDESC_DEVICE_QUALIFIER, /* type */ 2926 {0x00, 0x02}, /* USB version */ 2927 UDCLASS_HUB, /* class */ 2928 UDSUBCLASS_HUB, /* subclass */ 2929 UDPROTO_FSHUB, /* protocol */ 2930 0, /* max packet */ 2931 0, /* # of configurations */ 2932 0 2933 }; 2934 2935 static const struct ehci_config_desc ehci_confd = { 2936 .confd = { 2937 .bLength = sizeof(struct usb2_config_descriptor), 2938 .bDescriptorType = UDESC_CONFIG, 2939 .wTotalLength[0] = sizeof(ehci_confd), 2940 .bNumInterface = 1, 2941 .bConfigurationValue = 1, 2942 .iConfiguration = 0, 2943 .bmAttributes = UC_SELF_POWERED, 2944 .bMaxPower = 0 /* max power */ 2945 }, 2946 .ifcd = { 2947 .bLength = sizeof(struct usb2_interface_descriptor), 2948 .bDescriptorType = UDESC_INTERFACE, 2949 .bNumEndpoints = 1, 2950 .bInterfaceClass = UICLASS_HUB, 2951 .bInterfaceSubClass = UISUBCLASS_HUB, 2952 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2953 0 2954 }, 2955 .endpd = { 2956 .bLength = sizeof(struct usb2_endpoint_descriptor), 2957 .bDescriptorType = UDESC_ENDPOINT, 2958 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 2959 .bmAttributes = UE_INTERRUPT, 2960 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2961 .bInterval = 255, 2962 }, 2963 }; 2964 2965 static const 2966 struct usb2_hub_descriptor ehci_hubd = 2967 { 2968 0, /* dynamic length */ 2969 UDESC_HUB, 2970 0, 2971 {0, 0}, 2972 0, 2973 0, 2974 {0}, 2975 }; 2976 2977 static void 2978 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 2979 { 2980 uint32_t port; 2981 uint32_t v; 2982 2983 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 2984 2985 port = EHCI_PORTSC(index); 2986 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 2987 EOWRITE4(sc, port, v | EHCI_PS_PO); 2988 } 2989 2990 static void 2991 ehci_roothub_exec(struct usb2_bus *bus) 2992 { 2993 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2994 struct usb2_sw_transfer *std = &sc->sc_bus.roothub_req; 2995 char *ptr; 2996 uint32_t port; 2997 uint32_t v; 2998 uint16_t i; 2999 uint16_t value; 3000 uint16_t index; 3001 uint8_t l; 3002 3003 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3004 3005 /* buffer reset */ 3006 std->ptr = sc->sc_hub_desc.temp; 3007 std->len = 0; 3008 3009 value = UGETW(std->req.wValue); 3010 index = UGETW(std->req.wIndex); 3011 3012 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3013 "wValue=0x%04x wIndex=0x%04x\n", 3014 std->req.bmRequestType, std->req.bRequest, 3015 UGETW(std->req.wLength), value, index); 3016 3017 #define C(x,y) ((x) | ((y) << 8)) 3018 switch (C(std->req.bRequest, std->req.bmRequestType)) { 3019 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3020 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3021 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3022 /* 3023 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3024 * for the integrated root hub. 3025 */ 3026 break; 3027 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3028 std->len = 1; 3029 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3030 break; 3031 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3032 switch (value >> 8) { 3033 case UDESC_DEVICE: 3034 if ((value & 0xff) != 0) { 3035 std->err = USB_ERR_IOERROR; 3036 goto done; 3037 } 3038 std->len = sizeof(ehci_devd); 3039 sc->sc_hub_desc.devd = ehci_devd; 3040 break; 3041 /* 3042 * We can't really operate at another speed, 3043 * but the specification says we need this 3044 * descriptor: 3045 */ 3046 case UDESC_DEVICE_QUALIFIER: 3047 if ((value & 0xff) != 0) { 3048 std->err = USB_ERR_IOERROR; 3049 goto done; 3050 } 3051 std->len = sizeof(ehci_odevd); 3052 sc->sc_hub_desc.odevd = ehci_odevd; 3053 break; 3054 3055 case UDESC_CONFIG: 3056 if ((value & 0xff) != 0) { 3057 std->err = USB_ERR_IOERROR; 3058 goto done; 3059 } 3060 std->len = sizeof(ehci_confd); 3061 std->ptr = USB_ADD_BYTES(&ehci_confd, 0); 3062 break; 3063 3064 case UDESC_STRING: 3065 switch (value & 0xff) { 3066 case 0: /* Language table */ 3067 ptr = "\001"; 3068 break; 3069 3070 case 1: /* Vendor */ 3071 ptr = sc->sc_vendor; 3072 break; 3073 3074 case 2: /* Product */ 3075 ptr = "EHCI root HUB"; 3076 break; 3077 3078 default: 3079 ptr = ""; 3080 break; 3081 } 3082 3083 std->len = usb2_make_str_desc 3084 (sc->sc_hub_desc.temp, 3085 sizeof(sc->sc_hub_desc.temp), 3086 ptr); 3087 break; 3088 default: 3089 std->err = USB_ERR_IOERROR; 3090 goto done; 3091 } 3092 break; 3093 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3094 std->len = 1; 3095 sc->sc_hub_desc.temp[0] = 0; 3096 break; 3097 case C(UR_GET_STATUS, UT_READ_DEVICE): 3098 std->len = 2; 3099 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3100 break; 3101 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3102 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3103 std->len = 2; 3104 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3105 break; 3106 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3107 if (value >= EHCI_MAX_DEVICES) { 3108 std->err = USB_ERR_IOERROR; 3109 goto done; 3110 } 3111 sc->sc_addr = value; 3112 break; 3113 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3114 if ((value != 0) && (value != 1)) { 3115 std->err = USB_ERR_IOERROR; 3116 goto done; 3117 } 3118 sc->sc_conf = value; 3119 break; 3120 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3121 break; 3122 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3123 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3124 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3125 std->err = USB_ERR_IOERROR; 3126 goto done; 3127 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3128 break; 3129 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3130 break; 3131 /* Hub requests */ 3132 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3133 break; 3134 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3135 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3136 3137 if ((index < 1) || 3138 (index > sc->sc_noport)) { 3139 std->err = USB_ERR_IOERROR; 3140 goto done; 3141 } 3142 port = EHCI_PORTSC(index); 3143 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3144 switch (value) { 3145 case UHF_PORT_ENABLE: 3146 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3147 break; 3148 case UHF_PORT_SUSPEND: 3149 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3150 3151 /* 3152 * waking up a High Speed device is rather 3153 * complicated if 3154 */ 3155 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3156 } 3157 /* wait 20ms for resume sequence to complete */ 3158 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3159 3160 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3161 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3162 3163 /* 4ms settle time */ 3164 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3165 break; 3166 case UHF_PORT_POWER: 3167 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3168 break; 3169 case UHF_PORT_TEST: 3170 DPRINTFN(3, "clear port test " 3171 "%d\n", index); 3172 break; 3173 case UHF_PORT_INDICATOR: 3174 DPRINTFN(3, "clear port ind " 3175 "%d\n", index); 3176 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3177 break; 3178 case UHF_C_PORT_CONNECTION: 3179 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3180 break; 3181 case UHF_C_PORT_ENABLE: 3182 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3183 break; 3184 case UHF_C_PORT_SUSPEND: 3185 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3186 break; 3187 case UHF_C_PORT_OVER_CURRENT: 3188 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3189 break; 3190 case UHF_C_PORT_RESET: 3191 sc->sc_isreset = 0; 3192 break; 3193 default: 3194 std->err = USB_ERR_IOERROR; 3195 goto done; 3196 } 3197 break; 3198 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3199 if ((value & 0xff) != 0) { 3200 std->err = USB_ERR_IOERROR; 3201 goto done; 3202 } 3203 v = EOREAD4(sc, EHCI_HCSPARAMS); 3204 3205 sc->sc_hub_desc.hubd = ehci_hubd; 3206 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3207 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 3208 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 3209 (EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) ? 3210 UHD_PORT_IND : 0)); 3211 /* XXX can't find out? */ 3212 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3213 for (l = 0; l < sc->sc_noport; l++) { 3214 /* XXX can't find out? */ 3215 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] &= ~(1 << (l % 8)); 3216 } 3217 sc->sc_hub_desc.hubd.bDescLength = 3218 8 + ((sc->sc_noport + 7) / 8); 3219 std->len = sc->sc_hub_desc.hubd.bDescLength; 3220 break; 3221 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3222 std->len = 16; 3223 bzero(sc->sc_hub_desc.temp, 16); 3224 break; 3225 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3226 DPRINTFN(9, "get port status i=%d\n", 3227 index); 3228 if ((index < 1) || 3229 (index > sc->sc_noport)) { 3230 std->err = USB_ERR_IOERROR; 3231 goto done; 3232 } 3233 v = EOREAD4(sc, EHCI_PORTSC(index)); 3234 DPRINTFN(9, "port status=0x%04x\n", v); 3235 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) { 3236 if ((v & 0xc000000) == 0x8000000) 3237 i = UPS_HIGH_SPEED; 3238 else if ((v & 0xc000000) == 0x4000000) 3239 i = UPS_LOW_SPEED; 3240 else 3241 i = 0; 3242 } else { 3243 i = UPS_HIGH_SPEED; 3244 } 3245 if (v & EHCI_PS_CS) 3246 i |= UPS_CURRENT_CONNECT_STATUS; 3247 if (v & EHCI_PS_PE) 3248 i |= UPS_PORT_ENABLED; 3249 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3250 i |= UPS_SUSPEND; 3251 if (v & EHCI_PS_OCA) 3252 i |= UPS_OVERCURRENT_INDICATOR; 3253 if (v & EHCI_PS_PR) 3254 i |= UPS_RESET; 3255 if (v & EHCI_PS_PP) 3256 i |= UPS_PORT_POWER; 3257 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3258 i = 0; 3259 if (v & EHCI_PS_CSC) 3260 i |= UPS_C_CONNECT_STATUS; 3261 if (v & EHCI_PS_PEC) 3262 i |= UPS_C_PORT_ENABLED; 3263 if (v & EHCI_PS_OCC) 3264 i |= UPS_C_OVERCURRENT_INDICATOR; 3265 if (v & EHCI_PS_FPR) 3266 i |= UPS_C_SUSPEND; 3267 if (sc->sc_isreset) 3268 i |= UPS_C_PORT_RESET; 3269 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3270 std->len = sizeof(sc->sc_hub_desc.ps); 3271 break; 3272 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3273 std->err = USB_ERR_IOERROR; 3274 goto done; 3275 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3276 break; 3277 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3278 if ((index < 1) || 3279 (index > sc->sc_noport)) { 3280 std->err = USB_ERR_IOERROR; 3281 goto done; 3282 } 3283 port = EHCI_PORTSC(index); 3284 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3285 switch (value) { 3286 case UHF_PORT_ENABLE: 3287 EOWRITE4(sc, port, v | EHCI_PS_PE); 3288 break; 3289 case UHF_PORT_SUSPEND: 3290 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3291 break; 3292 case UHF_PORT_RESET: 3293 DPRINTFN(6, "reset port %d\n", index); 3294 #if USB_DEBUG 3295 if (ehcinohighspeed) { 3296 /* 3297 * Connect USB device to companion 3298 * controller. 3299 */ 3300 ehci_disown(sc, index, 1); 3301 break; 3302 } 3303 #endif 3304 if (EHCI_PS_IS_LOWSPEED(v) && 3305 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3306 /* Low speed device, give up ownership. */ 3307 ehci_disown(sc, index, 1); 3308 break; 3309 } 3310 /* Start reset sequence. */ 3311 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3312 EOWRITE4(sc, port, v | EHCI_PS_PR); 3313 3314 /* Wait for reset to complete. */ 3315 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 3316 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 3317 3318 /* Terminate reset sequence. */ 3319 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3320 EOWRITE4(sc, port, v); 3321 3322 /* Wait for HC to complete reset. */ 3323 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 3324 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3325 3326 v = EOREAD4(sc, port); 3327 DPRINTF("ehci after reset, status=0x%08x\n", v); 3328 if (v & EHCI_PS_PR) { 3329 device_printf(sc->sc_bus.bdev, 3330 "port reset timeout\n"); 3331 std->err = USB_ERR_TIMEOUT; 3332 goto done; 3333 } 3334 if (!(v & EHCI_PS_PE) && 3335 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3336 /* Not a high speed device, give up ownership.*/ 3337 ehci_disown(sc, index, 0); 3338 break; 3339 } 3340 sc->sc_isreset = 1; 3341 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3342 index, v); 3343 break; 3344 3345 case UHF_PORT_POWER: 3346 DPRINTFN(3, "set port power %d\n", index); 3347 EOWRITE4(sc, port, v | EHCI_PS_PP); 3348 break; 3349 3350 case UHF_PORT_TEST: 3351 DPRINTFN(3, "set port test %d\n", index); 3352 break; 3353 3354 case UHF_PORT_INDICATOR: 3355 DPRINTFN(3, "set port ind %d\n", index); 3356 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3357 break; 3358 3359 default: 3360 std->err = USB_ERR_IOERROR; 3361 goto done; 3362 } 3363 break; 3364 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3365 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3366 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3367 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3368 break; 3369 default: 3370 std->err = USB_ERR_IOERROR; 3371 goto done; 3372 } 3373 done: 3374 return; 3375 } 3376 3377 static void 3378 ehci_xfer_setup(struct usb2_setup_params *parm) 3379 { 3380 struct usb2_page_search page_info; 3381 struct usb2_page_cache *pc; 3382 ehci_softc_t *sc; 3383 struct usb2_xfer *xfer; 3384 void *last_obj; 3385 uint32_t nqtd; 3386 uint32_t nqh; 3387 uint32_t nsitd; 3388 uint32_t nitd; 3389 uint32_t n; 3390 3391 sc = EHCI_BUS2SC(parm->udev->bus); 3392 xfer = parm->curr_xfer; 3393 3394 nqtd = 0; 3395 nqh = 0; 3396 nsitd = 0; 3397 nitd = 0; 3398 3399 /* 3400 * compute maximum number of some structures 3401 */ 3402 if (parm->methods == &ehci_device_ctrl_methods) { 3403 3404 /* 3405 * The proof for the "nqtd" formula is illustrated like 3406 * this: 3407 * 3408 * +------------------------------------+ 3409 * | | 3410 * | |remainder -> | 3411 * | +-----+---+ | 3412 * | | xxx | x | frm 0 | 3413 * | +-----+---++ | 3414 * | | xxx | xx | frm 1 | 3415 * | +-----+----+ | 3416 * | ... | 3417 * +------------------------------------+ 3418 * 3419 * "xxx" means a completely full USB transfer descriptor 3420 * 3421 * "x" and "xx" means a short USB packet 3422 * 3423 * For the remainder of an USB transfer modulo 3424 * "max_data_length" we need two USB transfer descriptors. 3425 * One to transfer the remaining data and one to finalise 3426 * with a zero length packet in case the "force_short_xfer" 3427 * flag is set. We only need two USB transfer descriptors in 3428 * the case where the transfer length of the first one is a 3429 * factor of "max_frame_size". The rest of the needed USB 3430 * transfer descriptors is given by the buffer size divided 3431 * by the maximum data payload. 3432 */ 3433 parm->hc_max_packet_size = 0x400; 3434 parm->hc_max_packet_count = 1; 3435 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3436 xfer->flags_int.bdma_enable = 1; 3437 3438 usb2_transfer_setup_sub(parm); 3439 3440 nqh = 1; 3441 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3442 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3443 3444 } else if (parm->methods == &ehci_device_bulk_methods) { 3445 3446 parm->hc_max_packet_size = 0x400; 3447 parm->hc_max_packet_count = 1; 3448 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3449 xfer->flags_int.bdma_enable = 1; 3450 3451 usb2_transfer_setup_sub(parm); 3452 3453 nqh = 1; 3454 nqtd = ((2 * xfer->nframes) 3455 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3456 3457 } else if (parm->methods == &ehci_device_intr_methods) { 3458 3459 if (parm->speed == USB_SPEED_HIGH) { 3460 parm->hc_max_packet_size = 0x400; 3461 parm->hc_max_packet_count = 3; 3462 } else if (parm->speed == USB_SPEED_FULL) { 3463 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3464 parm->hc_max_packet_count = 1; 3465 } else { 3466 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3467 parm->hc_max_packet_count = 1; 3468 } 3469 3470 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3471 xfer->flags_int.bdma_enable = 1; 3472 3473 usb2_transfer_setup_sub(parm); 3474 3475 nqh = 1; 3476 nqtd = ((2 * xfer->nframes) 3477 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3478 3479 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3480 3481 parm->hc_max_packet_size = 0x3FF; 3482 parm->hc_max_packet_count = 1; 3483 parm->hc_max_frame_size = 0x3FF; 3484 xfer->flags_int.bdma_enable = 1; 3485 3486 usb2_transfer_setup_sub(parm); 3487 3488 nsitd = xfer->nframes; 3489 3490 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3491 3492 parm->hc_max_packet_size = 0x400; 3493 parm->hc_max_packet_count = 3; 3494 parm->hc_max_frame_size = 0xC00; 3495 xfer->flags_int.bdma_enable = 1; 3496 3497 usb2_transfer_setup_sub(parm); 3498 3499 nitd = (xfer->nframes + 7) / 8; 3500 3501 } else { 3502 3503 parm->hc_max_packet_size = 0x400; 3504 parm->hc_max_packet_count = 1; 3505 parm->hc_max_frame_size = 0x400; 3506 3507 usb2_transfer_setup_sub(parm); 3508 } 3509 3510 alloc_dma_set: 3511 3512 if (parm->err) { 3513 return; 3514 } 3515 /* 3516 * Allocate queue heads and transfer descriptors 3517 */ 3518 last_obj = NULL; 3519 3520 if (usb2_transfer_setup_sub_malloc( 3521 parm, &pc, sizeof(ehci_itd_t), 3522 EHCI_ITD_ALIGN, nitd)) { 3523 parm->err = USB_ERR_NOMEM; 3524 return; 3525 } 3526 if (parm->buf) { 3527 for (n = 0; n != nitd; n++) { 3528 ehci_itd_t *td; 3529 3530 usb2_get_page(pc + n, 0, &page_info); 3531 3532 td = page_info.buffer; 3533 3534 /* init TD */ 3535 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3536 td->obj_next = last_obj; 3537 td->page_cache = pc + n; 3538 3539 last_obj = td; 3540 3541 usb2_pc_cpu_flush(pc + n); 3542 } 3543 } 3544 if (usb2_transfer_setup_sub_malloc( 3545 parm, &pc, sizeof(ehci_sitd_t), 3546 EHCI_SITD_ALIGN, nsitd)) { 3547 parm->err = USB_ERR_NOMEM; 3548 return; 3549 } 3550 if (parm->buf) { 3551 for (n = 0; n != nsitd; n++) { 3552 ehci_sitd_t *td; 3553 3554 usb2_get_page(pc + n, 0, &page_info); 3555 3556 td = page_info.buffer; 3557 3558 /* init TD */ 3559 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3560 td->obj_next = last_obj; 3561 td->page_cache = pc + n; 3562 3563 last_obj = td; 3564 3565 usb2_pc_cpu_flush(pc + n); 3566 } 3567 } 3568 if (usb2_transfer_setup_sub_malloc( 3569 parm, &pc, sizeof(ehci_qtd_t), 3570 EHCI_QTD_ALIGN, nqtd)) { 3571 parm->err = USB_ERR_NOMEM; 3572 return; 3573 } 3574 if (parm->buf) { 3575 for (n = 0; n != nqtd; n++) { 3576 ehci_qtd_t *qtd; 3577 3578 usb2_get_page(pc + n, 0, &page_info); 3579 3580 qtd = page_info.buffer; 3581 3582 /* init TD */ 3583 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3584 qtd->obj_next = last_obj; 3585 qtd->page_cache = pc + n; 3586 3587 last_obj = qtd; 3588 3589 usb2_pc_cpu_flush(pc + n); 3590 } 3591 } 3592 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3593 3594 last_obj = NULL; 3595 3596 if (usb2_transfer_setup_sub_malloc( 3597 parm, &pc, sizeof(ehci_qh_t), 3598 EHCI_QH_ALIGN, nqh)) { 3599 parm->err = USB_ERR_NOMEM; 3600 return; 3601 } 3602 if (parm->buf) { 3603 for (n = 0; n != nqh; n++) { 3604 ehci_qh_t *qh; 3605 3606 usb2_get_page(pc + n, 0, &page_info); 3607 3608 qh = page_info.buffer; 3609 3610 /* init QH */ 3611 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3612 qh->obj_next = last_obj; 3613 qh->page_cache = pc + n; 3614 3615 last_obj = qh; 3616 3617 usb2_pc_cpu_flush(pc + n); 3618 } 3619 } 3620 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3621 3622 if (!xfer->flags_int.curr_dma_set) { 3623 xfer->flags_int.curr_dma_set = 1; 3624 goto alloc_dma_set; 3625 } 3626 } 3627 3628 static void 3629 ehci_xfer_unsetup(struct usb2_xfer *xfer) 3630 { 3631 return; 3632 } 3633 3634 static void 3635 ehci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 3636 struct usb2_pipe *pipe) 3637 { 3638 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3639 3640 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3641 pipe, udev->address, 3642 edesc->bEndpointAddress, udev->flags.usb2_mode, 3643 sc->sc_addr); 3644 3645 if (udev->flags.usb2_mode != USB_MODE_HOST) { 3646 /* not supported */ 3647 return; 3648 } 3649 if (udev->device_index != sc->sc_addr) { 3650 3651 if ((udev->speed != USB_SPEED_HIGH) && 3652 ((udev->hs_hub_addr == 0) || 3653 (udev->hs_port_no == 0) || 3654 (udev->bus->devices[udev->hs_hub_addr] == NULL) || 3655 (udev->bus->devices[udev->hs_hub_addr]->hub == NULL))) { 3656 /* We need a transaction translator */ 3657 goto done; 3658 } 3659 switch (edesc->bmAttributes & UE_XFERTYPE) { 3660 case UE_CONTROL: 3661 pipe->methods = &ehci_device_ctrl_methods; 3662 break; 3663 case UE_INTERRUPT: 3664 pipe->methods = &ehci_device_intr_methods; 3665 break; 3666 case UE_ISOCHRONOUS: 3667 if (udev->speed == USB_SPEED_HIGH) { 3668 pipe->methods = &ehci_device_isoc_hs_methods; 3669 } else if (udev->speed == USB_SPEED_FULL) { 3670 pipe->methods = &ehci_device_isoc_fs_methods; 3671 } 3672 break; 3673 case UE_BULK: 3674 if (udev->speed != USB_SPEED_LOW) { 3675 pipe->methods = &ehci_device_bulk_methods; 3676 } 3677 break; 3678 default: 3679 /* do nothing */ 3680 break; 3681 } 3682 } 3683 done: 3684 return; 3685 } 3686 3687 static void 3688 ehci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 3689 { 3690 /* 3691 * Wait until the hardware has finished any possible use of 3692 * the transfer descriptor(s) and QH 3693 */ 3694 *pus = (188); /* microseconds */ 3695 } 3696 3697 static void 3698 ehci_device_resume(struct usb2_device *udev) 3699 { 3700 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3701 struct usb2_xfer *xfer; 3702 struct usb2_pipe_methods *methods; 3703 3704 DPRINTF("\n"); 3705 3706 USB_BUS_LOCK(udev->bus); 3707 3708 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3709 3710 if (xfer->xroot->udev == udev) { 3711 3712 methods = xfer->pipe->methods; 3713 3714 if ((methods == &ehci_device_bulk_methods) || 3715 (methods == &ehci_device_ctrl_methods)) { 3716 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3717 sc->sc_async_p_last); 3718 } 3719 if (methods == &ehci_device_intr_methods) { 3720 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3721 sc->sc_intr_p_last[xfer->qh_pos]); 3722 } 3723 } 3724 } 3725 3726 USB_BUS_UNLOCK(udev->bus); 3727 3728 return; 3729 } 3730 3731 static void 3732 ehci_device_suspend(struct usb2_device *udev) 3733 { 3734 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3735 struct usb2_xfer *xfer; 3736 struct usb2_pipe_methods *methods; 3737 3738 DPRINTF("\n"); 3739 3740 USB_BUS_LOCK(udev->bus); 3741 3742 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3743 3744 if (xfer->xroot->udev == udev) { 3745 3746 methods = xfer->pipe->methods; 3747 3748 if ((methods == &ehci_device_bulk_methods) || 3749 (methods == &ehci_device_ctrl_methods)) { 3750 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3751 sc->sc_async_p_last); 3752 } 3753 if (methods == &ehci_device_intr_methods) { 3754 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3755 sc->sc_intr_p_last[xfer->qh_pos]); 3756 } 3757 } 3758 } 3759 3760 USB_BUS_UNLOCK(udev->bus); 3761 3762 return; 3763 } 3764 3765 static void 3766 ehci_set_hw_power(struct usb2_bus *bus) 3767 { 3768 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3769 uint32_t temp; 3770 uint32_t flags; 3771 3772 DPRINTF("\n"); 3773 3774 USB_BUS_LOCK(bus); 3775 3776 flags = bus->hw_power_state; 3777 3778 temp = EOREAD4(sc, EHCI_USBCMD); 3779 3780 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3781 3782 if (flags & (USB_HW_POWER_CONTROL | 3783 USB_HW_POWER_BULK)) { 3784 DPRINTF("Async is active\n"); 3785 temp |= EHCI_CMD_ASE; 3786 } 3787 if (flags & (USB_HW_POWER_INTERRUPT | 3788 USB_HW_POWER_ISOC)) { 3789 DPRINTF("Periodic is active\n"); 3790 temp |= EHCI_CMD_PSE; 3791 } 3792 EOWRITE4(sc, EHCI_USBCMD, temp); 3793 3794 USB_BUS_UNLOCK(bus); 3795 3796 return; 3797 } 3798 3799 struct usb2_bus_methods ehci_bus_methods = 3800 { 3801 .pipe_init = ehci_pipe_init, 3802 .xfer_setup = ehci_xfer_setup, 3803 .xfer_unsetup = ehci_xfer_unsetup, 3804 .get_dma_delay = ehci_get_dma_delay, 3805 .device_resume = ehci_device_resume, 3806 .device_suspend = ehci_device_suspend, 3807 .set_hw_power = ehci_set_hw_power, 3808 .roothub_exec = ehci_roothub_exec, 3809 }; 3810