xref: /freebsd/sys/dev/usb/controller/ehci.c (revision d9f0ce31900a48d1a2bfc1c8c86f79d1e831451a)
1 /* $FreeBSD$ */
2 /*-
3  * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
4  * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved.
5  * Copyright (c) 2004 Lennart Augustsson. All rights reserved.
6  * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 /*
31  * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
32  *
33  * The EHCI 0.96 spec can be found at
34  * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
35  * The EHCI 1.0 spec can be found at
36  * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
37  * and the USB 2.0 spec at
38  * http://www.usb.org/developers/docs/usb_20.zip
39  *
40  */
41 
42 /*
43  * TODO:
44  * 1) command failures are not recovered correctly
45  */
46 
47 #ifdef USB_GLOBAL_INCLUDE_FILE
48 #include USB_GLOBAL_INCLUDE_FILE
49 #else
50 #include <sys/stdint.h>
51 #include <sys/stddef.h>
52 #include <sys/param.h>
53 #include <sys/queue.h>
54 #include <sys/types.h>
55 #include <sys/systm.h>
56 #include <sys/kernel.h>
57 #include <sys/bus.h>
58 #include <sys/module.h>
59 #include <sys/lock.h>
60 #include <sys/mutex.h>
61 #include <sys/condvar.h>
62 #include <sys/sysctl.h>
63 #include <sys/sx.h>
64 #include <sys/unistd.h>
65 #include <sys/callout.h>
66 #include <sys/malloc.h>
67 #include <sys/priv.h>
68 
69 #include <dev/usb/usb.h>
70 #include <dev/usb/usbdi.h>
71 
72 #define	USB_DEBUG_VAR ehcidebug
73 
74 #include <dev/usb/usb_core.h>
75 #include <dev/usb/usb_debug.h>
76 #include <dev/usb/usb_busdma.h>
77 #include <dev/usb/usb_process.h>
78 #include <dev/usb/usb_transfer.h>
79 #include <dev/usb/usb_device.h>
80 #include <dev/usb/usb_hub.h>
81 #include <dev/usb/usb_util.h>
82 
83 #include <dev/usb/usb_controller.h>
84 #include <dev/usb/usb_bus.h>
85 #endif			/* USB_GLOBAL_INCLUDE_FILE */
86 
87 #include <dev/usb/controller/ehci.h>
88 #include <dev/usb/controller/ehcireg.h>
89 
90 #define	EHCI_BUS2SC(bus) \
91    ((ehci_softc_t *)(((uint8_t *)(bus)) - \
92     ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus))))
93 
94 #ifdef USB_DEBUG
95 static int ehcidebug = 0;
96 static int ehcinohighspeed = 0;
97 static int ehciiaadbug = 0;
98 static int ehcilostintrbug = 0;
99 
100 static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
101 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RWTUN,
102     &ehcidebug, 0, "Debug level");
103 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RWTUN,
104     &ehcinohighspeed, 0, "Disable High Speed USB");
105 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RWTUN,
106     &ehciiaadbug, 0, "Enable doorbell bug workaround");
107 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RWTUN,
108     &ehcilostintrbug, 0, "Enable lost interrupt bug workaround");
109 
110 static void ehci_dump_regs(ehci_softc_t *sc);
111 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh);
112 
113 #endif
114 
115 #define	EHCI_INTR_ENDPT 1
116 
117 static const struct usb_bus_methods ehci_bus_methods;
118 static const struct usb_pipe_methods ehci_device_bulk_methods;
119 static const struct usb_pipe_methods ehci_device_ctrl_methods;
120 static const struct usb_pipe_methods ehci_device_intr_methods;
121 static const struct usb_pipe_methods ehci_device_isoc_fs_methods;
122 static const struct usb_pipe_methods ehci_device_isoc_hs_methods;
123 
124 static void ehci_do_poll(struct usb_bus *);
125 static void ehci_device_done(struct usb_xfer *, usb_error_t);
126 static uint8_t ehci_check_transfer(struct usb_xfer *);
127 static void ehci_timeout(void *);
128 static void ehci_poll_timeout(void *);
129 
130 static void ehci_root_intr(ehci_softc_t *sc);
131 
132 struct ehci_std_temp {
133 	ehci_softc_t *sc;
134 	struct usb_page_cache *pc;
135 	ehci_qtd_t *td;
136 	ehci_qtd_t *td_next;
137 	uint32_t average;
138 	uint32_t qtd_status;
139 	uint32_t len;
140 	uint16_t max_frame_size;
141 	uint8_t	shortpkt;
142 	uint8_t	auto_data_toggle;
143 	uint8_t	setup_alt_next;
144 	uint8_t	last_frame;
145 };
146 
147 void
148 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
149 {
150 	ehci_softc_t *sc = EHCI_BUS2SC(bus);
151 	uint32_t i;
152 
153 	cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
154 	    sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN);
155 
156 	cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg,
157 	    sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN);
158 
159 	cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg,
160 	    sizeof(ehci_qh_t), EHCI_QH_ALIGN);
161 
162 	for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
163 		cb(bus, sc->sc_hw.intr_start_pc + i,
164 		    sc->sc_hw.intr_start_pg + i,
165 		    sizeof(ehci_qh_t), EHCI_QH_ALIGN);
166 	}
167 
168 	for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
169 		cb(bus, sc->sc_hw.isoc_hs_start_pc + i,
170 		    sc->sc_hw.isoc_hs_start_pg + i,
171 		    sizeof(ehci_itd_t), EHCI_ITD_ALIGN);
172 	}
173 
174 	for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
175 		cb(bus, sc->sc_hw.isoc_fs_start_pc + i,
176 		    sc->sc_hw.isoc_fs_start_pg + i,
177 		    sizeof(ehci_sitd_t), EHCI_SITD_ALIGN);
178 	}
179 }
180 
181 usb_error_t
182 ehci_reset(ehci_softc_t *sc)
183 {
184 	uint32_t hcr;
185 	int i;
186 
187 	EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
188 	for (i = 0; i < 100; i++) {
189 		usb_pause_mtx(NULL, hz / 128);
190 		hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
191 		if (!hcr) {
192 			if (sc->sc_vendor_post_reset != NULL)
193 				sc->sc_vendor_post_reset(sc);
194 			return (0);
195 		}
196 	}
197 	device_printf(sc->sc_bus.bdev, "reset timeout\n");
198 	return (USB_ERR_IOERROR);
199 }
200 
201 static usb_error_t
202 ehci_hcreset(ehci_softc_t *sc)
203 {
204 	uint32_t hcr;
205 	int i;
206 
207 	EOWRITE4(sc, EHCI_USBCMD, 0);	/* Halt controller */
208 	for (i = 0; i < 100; i++) {
209 		usb_pause_mtx(NULL, hz / 128);
210 		hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
211 		if (hcr)
212 			break;
213 	}
214 	if (!hcr)
215 		/*
216                  * Fall through and try reset anyway even though
217                  * Table 2-9 in the EHCI spec says this will result
218                  * in undefined behavior.
219                  */
220 		device_printf(sc->sc_bus.bdev, "stop timeout\n");
221 
222 	return (ehci_reset(sc));
223 }
224 
225 static int
226 ehci_init_sub(struct ehci_softc *sc)
227 {
228 	struct usb_page_search buf_res;
229 	uint32_t cparams;
230   	uint32_t hcr;
231 	uint8_t i;
232 
233 	cparams = EREAD4(sc, EHCI_HCCPARAMS);
234 
235 	DPRINTF("cparams=0x%x\n", cparams);
236 
237 	if (EHCI_HCC_64BIT(cparams)) {
238 		DPRINTF("HCC uses 64-bit structures\n");
239 
240 		/* MUST clear segment register if 64 bit capable */
241 		EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
242 	}
243 
244 	usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
245 	EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
246 
247 	usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
248 	EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
249 
250 	/* enable interrupts */
251 	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
252 
253 	/* turn on controller */
254 	EOWRITE4(sc, EHCI_USBCMD,
255 	    EHCI_CMD_ITC_1 |		/* 1 microframes interrupt delay */
256 	    (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
257 	    EHCI_CMD_ASE |
258 	    EHCI_CMD_PSE |
259 	    EHCI_CMD_RS);
260 
261 	/* Take over port ownership */
262 	EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
263 
264 	for (i = 0; i < 100; i++) {
265 		usb_pause_mtx(NULL, hz / 128);
266 		hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
267 		if (!hcr) {
268 			break;
269 		}
270 	}
271 	if (hcr) {
272 		device_printf(sc->sc_bus.bdev, "run timeout\n");
273 		return (USB_ERR_IOERROR);
274 	}
275 	return (USB_ERR_NORMAL_COMPLETION);
276 }
277 
278 usb_error_t
279 ehci_init(ehci_softc_t *sc)
280 {
281 	struct usb_page_search buf_res;
282 	uint32_t version;
283 	uint32_t sparams;
284 	uint16_t i;
285 	uint16_t x;
286 	uint16_t y;
287 	uint16_t bit;
288 	usb_error_t err = 0;
289 
290 	DPRINTF("start\n");
291 
292 	usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0);
293 	usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0);
294 
295 	sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
296 
297 #ifdef USB_DEBUG
298 	if (ehciiaadbug)
299 		sc->sc_flags |= EHCI_SCFLG_IAADBUG;
300 	if (ehcilostintrbug)
301 		sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG;
302 	if (ehcidebug > 2) {
303 		ehci_dump_regs(sc);
304 	}
305 #endif
306 
307 	version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
308 	device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
309 	    version >> 8, version & 0xff);
310 
311 	sparams = EREAD4(sc, EHCI_HCSPARAMS);
312 	DPRINTF("sparams=0x%x\n", sparams);
313 
314 	sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
315 	sc->sc_bus.usbrev = USB_REV_2_0;
316 
317 	if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) {
318 		/* Reset the controller */
319 		DPRINTF("%s: resetting\n",
320 		    device_get_nameunit(sc->sc_bus.bdev));
321 
322 		err = ehci_hcreset(sc);
323 		if (err) {
324 			device_printf(sc->sc_bus.bdev, "reset timeout\n");
325 			return (err);
326 		}
327 	}
328 
329 	/*
330 	 * use current frame-list-size selection 0: 1024*4 bytes 1:  512*4
331 	 * bytes 2:  256*4 bytes 3:      unknown
332 	 */
333 	if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) {
334 		device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n");
335 		return (USB_ERR_IOERROR);
336 	}
337 	/* set up the bus struct */
338 	sc->sc_bus.methods = &ehci_bus_methods;
339 
340 	sc->sc_eintrs = EHCI_NORMAL_INTRS;
341 
342 	if (1) {
343 		struct ehci_qh_sub *qh;
344 
345 		usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res);
346 
347 		qh = buf_res.buffer;
348 
349 		sc->sc_terminate_self = htohc32(sc, buf_res.physaddr);
350 
351 		/* init terminate TD */
352 		qh->qtd_next =
353 		    htohc32(sc, EHCI_LINK_TERMINATE);
354 		qh->qtd_altnext =
355 		    htohc32(sc, EHCI_LINK_TERMINATE);
356 		qh->qtd_status =
357 		    htohc32(sc, EHCI_QTD_HALTED);
358 	}
359 
360 	for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
361 		ehci_qh_t *qh;
362 
363 		usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res);
364 
365 		qh = buf_res.buffer;
366 
367 		/* initialize page cache pointer */
368 
369 		qh->page_cache = sc->sc_hw.intr_start_pc + i;
370 
371 		/* store a pointer to queue head */
372 
373 		sc->sc_intr_p_last[i] = qh;
374 
375 		qh->qh_self =
376 		    htohc32(sc, buf_res.physaddr) |
377 		    htohc32(sc, EHCI_LINK_QH);
378 
379 		qh->qh_endp =
380 		    htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
381 		qh->qh_endphub =
382 		    htohc32(sc, EHCI_QH_SET_MULT(1));
383 		qh->qh_curqtd = 0;
384 
385 		qh->qh_qtd.qtd_next =
386 		    htohc32(sc, EHCI_LINK_TERMINATE);
387 		qh->qh_qtd.qtd_altnext =
388 		    htohc32(sc, EHCI_LINK_TERMINATE);
389 		qh->qh_qtd.qtd_status =
390 		    htohc32(sc, EHCI_QTD_HALTED);
391 	}
392 
393 	/*
394 	 * the QHs are arranged to give poll intervals that are
395 	 * powers of 2 times 1ms
396 	 */
397 	bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
398 	while (bit) {
399 		x = bit;
400 		while (x & bit) {
401 			ehci_qh_t *qh_x;
402 			ehci_qh_t *qh_y;
403 
404 			y = (x ^ bit) | (bit / 2);
405 
406 			qh_x = sc->sc_intr_p_last[x];
407 			qh_y = sc->sc_intr_p_last[y];
408 
409 			/*
410 			 * the next QH has half the poll interval
411 			 */
412 			qh_x->qh_link = qh_y->qh_self;
413 
414 			x++;
415 		}
416 		bit >>= 1;
417 	}
418 
419 	if (1) {
420 		ehci_qh_t *qh;
421 
422 		qh = sc->sc_intr_p_last[0];
423 
424 		/* the last (1ms) QH terminates */
425 		qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE);
426 	}
427 	for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
428 		ehci_sitd_t *sitd;
429 		ehci_itd_t *itd;
430 
431 		usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res);
432 
433 		sitd = buf_res.buffer;
434 
435 		/* initialize page cache pointer */
436 
437 		sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i;
438 
439 		/* store a pointer to the transfer descriptor */
440 
441 		sc->sc_isoc_fs_p_last[i] = sitd;
442 
443 		/* initialize full speed isochronous */
444 
445 		sitd->sitd_self =
446 		    htohc32(sc, buf_res.physaddr) |
447 		    htohc32(sc, EHCI_LINK_SITD);
448 
449 		sitd->sitd_back =
450 		    htohc32(sc, EHCI_LINK_TERMINATE);
451 
452 		sitd->sitd_next =
453 		    sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self;
454 
455 
456 		usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res);
457 
458 		itd = buf_res.buffer;
459 
460 		/* initialize page cache pointer */
461 
462 		itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i;
463 
464 		/* store a pointer to the transfer descriptor */
465 
466 		sc->sc_isoc_hs_p_last[i] = itd;
467 
468 		/* initialize high speed isochronous */
469 
470 		itd->itd_self =
471 		    htohc32(sc, buf_res.physaddr) |
472 		    htohc32(sc, EHCI_LINK_ITD);
473 
474 		itd->itd_next =
475 		    sitd->sitd_self;
476 	}
477 
478 	usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
479 
480 	if (1) {
481 		uint32_t *pframes;
482 
483 		pframes = buf_res.buffer;
484 
485 		/*
486 		 * execution order:
487 		 * pframes -> high speed isochronous ->
488 		 *    full speed isochronous -> interrupt QH's
489 		 */
490 		for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) {
491 			pframes[i] = sc->sc_isoc_hs_p_last
492 			    [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
493 		}
494 	}
495 	usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
496 
497 	if (1) {
498 
499 		ehci_qh_t *qh;
500 
501 		qh = buf_res.buffer;
502 
503 		/* initialize page cache pointer */
504 
505 		qh->page_cache = &sc->sc_hw.async_start_pc;
506 
507 		/* store a pointer to the queue head */
508 
509 		sc->sc_async_p_last = qh;
510 
511 		/* init dummy QH that starts the async list */
512 
513 		qh->qh_self =
514 		    htohc32(sc, buf_res.physaddr) |
515 		    htohc32(sc, EHCI_LINK_QH);
516 
517 		/* fill the QH */
518 		qh->qh_endp =
519 		    htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
520 		qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1));
521 		qh->qh_link = qh->qh_self;
522 		qh->qh_curqtd = 0;
523 
524 		/* fill the overlay qTD */
525 		qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE);
526 		qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE);
527 		qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED);
528 	}
529 	/* flush all cache into memory */
530 
531 	usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc);
532 
533 #ifdef USB_DEBUG
534 	if (ehcidebug) {
535 		ehci_dump_sqh(sc, sc->sc_async_p_last);
536 	}
537 #endif
538 
539 	/* finial setup */
540  	err = ehci_init_sub(sc);
541 
542 	if (!err) {
543 		/* catch any lost interrupts */
544 		ehci_do_poll(&sc->sc_bus);
545 	}
546 	return (err);
547 }
548 
549 /*
550  * shut down the controller when the system is going down
551  */
552 void
553 ehci_detach(ehci_softc_t *sc)
554 {
555 	USB_BUS_LOCK(&sc->sc_bus);
556 
557 	usb_callout_stop(&sc->sc_tmo_pcd);
558 	usb_callout_stop(&sc->sc_tmo_poll);
559 
560 	EOWRITE4(sc, EHCI_USBINTR, 0);
561 	USB_BUS_UNLOCK(&sc->sc_bus);
562 
563 	if (ehci_hcreset(sc)) {
564 		DPRINTF("reset failed!\n");
565 	}
566 
567 	/* XXX let stray task complete */
568 	usb_pause_mtx(NULL, hz / 20);
569 
570 	usb_callout_drain(&sc->sc_tmo_pcd);
571 	usb_callout_drain(&sc->sc_tmo_poll);
572 }
573 
574 static void
575 ehci_suspend(ehci_softc_t *sc)
576 {
577 	DPRINTF("stopping the HC\n");
578 
579 	/* reset HC */
580 	ehci_hcreset(sc);
581 }
582 
583 static void
584 ehci_resume(ehci_softc_t *sc)
585 {
586 	/* reset HC */
587 	ehci_hcreset(sc);
588 
589 	/* setup HC */
590 	ehci_init_sub(sc);
591 
592 	/* catch any lost interrupts */
593 	ehci_do_poll(&sc->sc_bus);
594 }
595 
596 #ifdef USB_DEBUG
597 static void
598 ehci_dump_regs(ehci_softc_t *sc)
599 {
600 	uint32_t i;
601 
602 	i = EOREAD4(sc, EHCI_USBCMD);
603 	printf("cmd=0x%08x\n", i);
604 
605 	if (i & EHCI_CMD_ITC_1)
606 		printf(" EHCI_CMD_ITC_1\n");
607 	if (i & EHCI_CMD_ITC_2)
608 		printf(" EHCI_CMD_ITC_2\n");
609 	if (i & EHCI_CMD_ITC_4)
610 		printf(" EHCI_CMD_ITC_4\n");
611 	if (i & EHCI_CMD_ITC_8)
612 		printf(" EHCI_CMD_ITC_8\n");
613 	if (i & EHCI_CMD_ITC_16)
614 		printf(" EHCI_CMD_ITC_16\n");
615 	if (i & EHCI_CMD_ITC_32)
616 		printf(" EHCI_CMD_ITC_32\n");
617 	if (i & EHCI_CMD_ITC_64)
618 		printf(" EHCI_CMD_ITC_64\n");
619 	if (i & EHCI_CMD_ASPME)
620 		printf(" EHCI_CMD_ASPME\n");
621 	if (i & EHCI_CMD_ASPMC)
622 		printf(" EHCI_CMD_ASPMC\n");
623 	if (i & EHCI_CMD_LHCR)
624 		printf(" EHCI_CMD_LHCR\n");
625 	if (i & EHCI_CMD_IAAD)
626 		printf(" EHCI_CMD_IAAD\n");
627 	if (i & EHCI_CMD_ASE)
628 		printf(" EHCI_CMD_ASE\n");
629 	if (i & EHCI_CMD_PSE)
630 		printf(" EHCI_CMD_PSE\n");
631 	if (i & EHCI_CMD_FLS_M)
632 		printf(" EHCI_CMD_FLS_M\n");
633 	if (i & EHCI_CMD_HCRESET)
634 		printf(" EHCI_CMD_HCRESET\n");
635 	if (i & EHCI_CMD_RS)
636 		printf(" EHCI_CMD_RS\n");
637 
638 	i = EOREAD4(sc, EHCI_USBSTS);
639 
640 	printf("sts=0x%08x\n", i);
641 
642 	if (i & EHCI_STS_ASS)
643 		printf(" EHCI_STS_ASS\n");
644 	if (i & EHCI_STS_PSS)
645 		printf(" EHCI_STS_PSS\n");
646 	if (i & EHCI_STS_REC)
647 		printf(" EHCI_STS_REC\n");
648 	if (i & EHCI_STS_HCH)
649 		printf(" EHCI_STS_HCH\n");
650 	if (i & EHCI_STS_IAA)
651 		printf(" EHCI_STS_IAA\n");
652 	if (i & EHCI_STS_HSE)
653 		printf(" EHCI_STS_HSE\n");
654 	if (i & EHCI_STS_FLR)
655 		printf(" EHCI_STS_FLR\n");
656 	if (i & EHCI_STS_PCD)
657 		printf(" EHCI_STS_PCD\n");
658 	if (i & EHCI_STS_ERRINT)
659 		printf(" EHCI_STS_ERRINT\n");
660 	if (i & EHCI_STS_INT)
661 		printf(" EHCI_STS_INT\n");
662 
663 	printf("ien=0x%08x\n",
664 	    EOREAD4(sc, EHCI_USBINTR));
665 	printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
666 	    EOREAD4(sc, EHCI_FRINDEX),
667 	    EOREAD4(sc, EHCI_CTRLDSSEGMENT),
668 	    EOREAD4(sc, EHCI_PERIODICLISTBASE),
669 	    EOREAD4(sc, EHCI_ASYNCLISTADDR));
670 	for (i = 1; i <= sc->sc_noport; i++) {
671 		printf("port %d status=0x%08x\n", i,
672 		    EOREAD4(sc, EHCI_PORTSC(i)));
673 	}
674 }
675 
676 static void
677 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type)
678 {
679 	link = hc32toh(sc, link);
680 	printf("0x%08x", link);
681 	if (link & EHCI_LINK_TERMINATE)
682 		printf("<T>");
683 	else {
684 		printf("<");
685 		if (type) {
686 			switch (EHCI_LINK_TYPE(link)) {
687 			case EHCI_LINK_ITD:
688 				printf("ITD");
689 				break;
690 			case EHCI_LINK_QH:
691 				printf("QH");
692 				break;
693 			case EHCI_LINK_SITD:
694 				printf("SITD");
695 				break;
696 			case EHCI_LINK_FSTN:
697 				printf("FSTN");
698 				break;
699 			}
700 		}
701 		printf(">");
702 	}
703 }
704 
705 static void
706 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd)
707 {
708 	uint32_t s;
709 
710 	printf("  next=");
711 	ehci_dump_link(sc, qtd->qtd_next, 0);
712 	printf(" altnext=");
713 	ehci_dump_link(sc, qtd->qtd_altnext, 0);
714 	printf("\n");
715 	s = hc32toh(sc, qtd->qtd_status);
716 	printf("  status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
717 	    s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
718 	    EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
719 	printf("    cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n",
720 	    EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s),
721 	    (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE",
722 	    (s & EHCI_QTD_HALTED) ? "-HALTED" : "",
723 	    (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "",
724 	    (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "",
725 	    (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "",
726 	    (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "",
727 	    (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "",
728 	    (s & EHCI_QTD_PINGSTATE) ? "-PING" : "");
729 
730 	for (s = 0; s < 5; s++) {
731 		printf("  buffer[%d]=0x%08x\n", s,
732 		    hc32toh(sc, qtd->qtd_buffer[s]));
733 	}
734 	for (s = 0; s < 5; s++) {
735 		printf("  buffer_hi[%d]=0x%08x\n", s,
736 		    hc32toh(sc, qtd->qtd_buffer_hi[s]));
737 	}
738 }
739 
740 static uint8_t
741 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd)
742 {
743 	uint8_t temp;
744 
745 	usb_pc_cpu_invalidate(sqtd->page_cache);
746 	printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self));
747 	ehci_dump_qtd(sc, sqtd);
748 	temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0;
749 	return (temp);
750 }
751 
752 static void
753 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd)
754 {
755 	uint16_t i;
756 	uint8_t stop;
757 
758 	stop = 0;
759 	for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) {
760 		stop = ehci_dump_sqtd(sc, sqtd);
761 	}
762 	if (sqtd) {
763 		printf("dump aborted, too many TDs\n");
764 	}
765 }
766 
767 static void
768 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh)
769 {
770 	uint32_t endp;
771 	uint32_t endphub;
772 
773 	usb_pc_cpu_invalidate(qh->page_cache);
774 	printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F);
775 	printf("  link=");
776 	ehci_dump_link(sc, qh->qh_link, 1);
777 	printf("\n");
778 	endp = hc32toh(sc, qh->qh_endp);
779 	printf("  endp=0x%08x\n", endp);
780 	printf("    addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
781 	    EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
782 	    EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
783 	    EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
784 	printf("    mpl=0x%x ctl=%d nrl=%d\n",
785 	    EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
786 	    EHCI_QH_GET_NRL(endp));
787 	endphub = hc32toh(sc, qh->qh_endphub);
788 	printf("  endphub=0x%08x\n", endphub);
789 	printf("    smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
790 	    EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
791 	    EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
792 	    EHCI_QH_GET_MULT(endphub));
793 	printf("  curqtd=");
794 	ehci_dump_link(sc, qh->qh_curqtd, 0);
795 	printf("\n");
796 	printf("Overlay qTD:\n");
797 	ehci_dump_qtd(sc, (void *)&qh->qh_qtd);
798 }
799 
800 static void
801 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd)
802 {
803 	usb_pc_cpu_invalidate(sitd->page_cache);
804 	printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F);
805 	printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next));
806 	printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n",
807 	    hc32toh(sc, sitd->sitd_portaddr),
808 	    (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN))
809 	    ? "in" : "out",
810 	    EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)),
811 	    EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)),
812 	    EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)),
813 	    EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr)));
814 	printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask));
815 	printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status),
816 	    (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "",
817 	    EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status)));
818 	printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n",
819 	    hc32toh(sc, sitd->sitd_back),
820 	    hc32toh(sc, sitd->sitd_bp[0]),
821 	    hc32toh(sc, sitd->sitd_bp[1]),
822 	    hc32toh(sc, sitd->sitd_bp_hi[0]),
823 	    hc32toh(sc, sitd->sitd_bp_hi[1]));
824 }
825 
826 static void
827 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd)
828 {
829 	usb_pc_cpu_invalidate(itd->page_cache);
830 	printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F);
831 	printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next));
832 	printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]),
833 	    (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
834 	printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]),
835 	    (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
836 	printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]),
837 	    (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
838 	printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]),
839 	    (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
840 	printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]),
841 	    (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
842 	printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]),
843 	    (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
844 	printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]),
845 	    (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
846 	printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]),
847 	    (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
848 	printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0]));
849 	printf("  addr=0x%02x; endpt=0x%01x\n",
850 	    EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])),
851 	    EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0])));
852 	printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1]));
853 	printf(" dir=%s; mpl=0x%02x\n",
854 	    (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out",
855 	    EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1])));
856 	printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n",
857 	    hc32toh(sc, itd->itd_bp[2]),
858 	    hc32toh(sc, itd->itd_bp[3]),
859 	    hc32toh(sc, itd->itd_bp[4]),
860 	    hc32toh(sc, itd->itd_bp[5]),
861 	    hc32toh(sc, itd->itd_bp[6]));
862 	printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n"
863 	    "       0x%08x,0x%08x,0x%08x\n",
864 	    hc32toh(sc, itd->itd_bp_hi[0]),
865 	    hc32toh(sc, itd->itd_bp_hi[1]),
866 	    hc32toh(sc, itd->itd_bp_hi[2]),
867 	    hc32toh(sc, itd->itd_bp_hi[3]),
868 	    hc32toh(sc, itd->itd_bp_hi[4]),
869 	    hc32toh(sc, itd->itd_bp_hi[5]),
870 	    hc32toh(sc, itd->itd_bp_hi[6]));
871 }
872 
873 static void
874 ehci_dump_isoc(ehci_softc_t *sc)
875 {
876 	ehci_itd_t *itd;
877 	ehci_sitd_t *sitd;
878 	uint16_t max = 1000;
879 	uint16_t pos;
880 
881 	pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) &
882 	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
883 
884 	printf("%s: isochronous dump from frame 0x%03x:\n",
885 	    __FUNCTION__, pos);
886 
887 	itd = sc->sc_isoc_hs_p_last[pos];
888 	sitd = sc->sc_isoc_fs_p_last[pos];
889 
890 	while (itd && max && max--) {
891 		ehci_dump_itd(sc, itd);
892 		itd = itd->prev;
893 	}
894 
895 	while (sitd && max && max--) {
896 		ehci_dump_sitd(sc, sitd);
897 		sitd = sitd->prev;
898 	}
899 }
900 
901 #endif
902 
903 static void
904 ehci_transfer_intr_enqueue(struct usb_xfer *xfer)
905 {
906 	/* check for early completion */
907 	if (ehci_check_transfer(xfer)) {
908 		return;
909 	}
910 	/* put transfer on interrupt queue */
911 	usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
912 
913 	/* start timeout, if any */
914 	if (xfer->timeout != 0) {
915 		usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout);
916 	}
917 }
918 
919 #define	EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last)
920 static ehci_sitd_t *
921 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
922 {
923 	DPRINTFN(11, "%p to %p\n", std, last);
924 
925 	/* (sc->sc_bus.mtx) must be locked */
926 
927 	std->next = last->next;
928 	std->sitd_next = last->sitd_next;
929 
930 	std->prev = last;
931 
932 	usb_pc_cpu_flush(std->page_cache);
933 
934 	/*
935 	 * the last->next->prev is never followed: std->next->prev = std;
936 	 */
937 	last->next = std;
938 	last->sitd_next = std->sitd_self;
939 
940 	usb_pc_cpu_flush(last->page_cache);
941 
942 	return (std);
943 }
944 
945 #define	EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last)
946 static ehci_itd_t *
947 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last)
948 {
949 	DPRINTFN(11, "%p to %p\n", std, last);
950 
951 	/* (sc->sc_bus.mtx) must be locked */
952 
953 	std->next = last->next;
954 	std->itd_next = last->itd_next;
955 
956 	std->prev = last;
957 
958 	usb_pc_cpu_flush(std->page_cache);
959 
960 	/*
961 	 * the last->next->prev is never followed: std->next->prev = std;
962 	 */
963 	last->next = std;
964 	last->itd_next = std->itd_self;
965 
966 	usb_pc_cpu_flush(last->page_cache);
967 
968 	return (std);
969 }
970 
971 #define	EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last)
972 static ehci_qh_t *
973 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last)
974 {
975 	DPRINTFN(11, "%p to %p\n", sqh, last);
976 
977 	if (sqh->prev != NULL) {
978 		/* should not happen */
979 		DPRINTFN(0, "QH already linked!\n");
980 		return (last);
981 	}
982 	/* (sc->sc_bus.mtx) must be locked */
983 
984 	sqh->next = last->next;
985 	sqh->qh_link = last->qh_link;
986 
987 	sqh->prev = last;
988 
989 	usb_pc_cpu_flush(sqh->page_cache);
990 
991 	/*
992 	 * the last->next->prev is never followed: sqh->next->prev = sqh;
993 	 */
994 
995 	last->next = sqh;
996 	last->qh_link = sqh->qh_self;
997 
998 	usb_pc_cpu_flush(last->page_cache);
999 
1000 	return (sqh);
1001 }
1002 
1003 #define	EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last)
1004 static ehci_sitd_t *
1005 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1006 {
1007 	DPRINTFN(11, "%p from %p\n", std, last);
1008 
1009 	/* (sc->sc_bus.mtx) must be locked */
1010 
1011 	std->prev->next = std->next;
1012 	std->prev->sitd_next = std->sitd_next;
1013 
1014 	usb_pc_cpu_flush(std->prev->page_cache);
1015 
1016 	if (std->next) {
1017 		std->next->prev = std->prev;
1018 		usb_pc_cpu_flush(std->next->page_cache);
1019 	}
1020 	return ((last == std) ? std->prev : last);
1021 }
1022 
1023 #define	EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last)
1024 static ehci_itd_t *
1025 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1026 {
1027 	DPRINTFN(11, "%p from %p\n", std, last);
1028 
1029 	/* (sc->sc_bus.mtx) must be locked */
1030 
1031 	std->prev->next = std->next;
1032 	std->prev->itd_next = std->itd_next;
1033 
1034 	usb_pc_cpu_flush(std->prev->page_cache);
1035 
1036 	if (std->next) {
1037 		std->next->prev = std->prev;
1038 		usb_pc_cpu_flush(std->next->page_cache);
1039 	}
1040 	return ((last == std) ? std->prev : last);
1041 }
1042 
1043 #define	EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last)
1044 static ehci_qh_t *
1045 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1046 {
1047 	DPRINTFN(11, "%p from %p\n", sqh, last);
1048 
1049 	/* (sc->sc_bus.mtx) must be locked */
1050 
1051 	/* only remove if not removed from a queue */
1052 	if (sqh->prev) {
1053 
1054 		sqh->prev->next = sqh->next;
1055 		sqh->prev->qh_link = sqh->qh_link;
1056 
1057 		usb_pc_cpu_flush(sqh->prev->page_cache);
1058 
1059 		if (sqh->next) {
1060 			sqh->next->prev = sqh->prev;
1061 			usb_pc_cpu_flush(sqh->next->page_cache);
1062 		}
1063 		last = ((last == sqh) ? sqh->prev : last);
1064 
1065 		sqh->prev = 0;
1066 
1067 		usb_pc_cpu_flush(sqh->page_cache);
1068 	}
1069 	return (last);
1070 }
1071 
1072 static void
1073 ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen)
1074 {
1075 	uint16_t rem;
1076 	uint8_t dt;
1077 
1078 	/* count number of full packets */
1079 	dt = (actlen / xfer->max_packet_size) & 1;
1080 
1081 	/* compute remainder */
1082 	rem = actlen % xfer->max_packet_size;
1083 
1084 	if (rem > 0)
1085 		dt ^= 1;	/* short packet at the end */
1086 	else if (actlen != xlen)
1087 		dt ^= 1;	/* zero length packet at the end */
1088 	else if (xlen == 0)
1089 		dt ^= 1;	/* zero length transfer */
1090 
1091 	xfer->endpoint->toggle_next ^= dt;
1092 }
1093 
1094 static usb_error_t
1095 ehci_non_isoc_done_sub(struct usb_xfer *xfer)
1096 {
1097 	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1098 	ehci_qtd_t *td;
1099 	ehci_qtd_t *td_alt_next;
1100 	uint32_t status;
1101 	uint16_t len;
1102 
1103 	td = xfer->td_transfer_cache;
1104 	td_alt_next = td->alt_next;
1105 
1106 	if (xfer->aframes != xfer->nframes) {
1107 		usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1108 	}
1109 	while (1) {
1110 
1111 		usb_pc_cpu_invalidate(td->page_cache);
1112 		status = hc32toh(sc, td->qtd_status);
1113 
1114 		len = EHCI_QTD_GET_BYTES(status);
1115 
1116 		/*
1117 	         * Verify the status length and
1118 		 * add the length to "frlengths[]":
1119 	         */
1120 		if (len > td->len) {
1121 			/* should not happen */
1122 			DPRINTF("Invalid status length, "
1123 			    "0x%04x/0x%04x bytes\n", len, td->len);
1124 			status |= EHCI_QTD_HALTED;
1125 		} else if (xfer->aframes != xfer->nframes) {
1126 			xfer->frlengths[xfer->aframes] += td->len - len;
1127 			/* manually update data toggle */
1128 			ehci_data_toggle_update(xfer, td->len - len, td->len);
1129 		}
1130 
1131 		/* Check for last transfer */
1132 		if (((void *)td) == xfer->td_transfer_last) {
1133 			td = NULL;
1134 			break;
1135 		}
1136 		/* Check for transfer error */
1137 		if (status & EHCI_QTD_HALTED) {
1138 			/* the transfer is finished */
1139 			td = NULL;
1140 			break;
1141 		}
1142 		/* Check for short transfer */
1143 		if (len > 0) {
1144 			if (xfer->flags_int.short_frames_ok) {
1145 				/* follow alt next */
1146 				td = td->alt_next;
1147 			} else {
1148 				/* the transfer is finished */
1149 				td = NULL;
1150 			}
1151 			break;
1152 		}
1153 		td = td->obj_next;
1154 
1155 		if (td->alt_next != td_alt_next) {
1156 			/* this USB frame is complete */
1157 			break;
1158 		}
1159 	}
1160 
1161 	/* update transfer cache */
1162 
1163 	xfer->td_transfer_cache = td;
1164 
1165 #ifdef USB_DEBUG
1166 	if (status & EHCI_QTD_STATERRS) {
1167 		DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x"
1168 		    "status=%s%s%s%s%s%s%s%s\n",
1169 		    xfer->address, xfer->endpointno, xfer->aframes,
1170 		    (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1171 		    (status & EHCI_QTD_HALTED) ? "[HALTED]" : "",
1172 		    (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "",
1173 		    (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "",
1174 		    (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "",
1175 		    (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "",
1176 		    (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "",
1177 		    (status & EHCI_QTD_PINGSTATE) ? "[PING]" : "");
1178 	}
1179 #endif
1180 	if (status & EHCI_QTD_HALTED) {
1181 		if ((xfer->xroot->udev->parent_hs_hub != NULL) ||
1182 		    (xfer->xroot->udev->address != 0)) {
1183 			/* try to separate I/O errors from STALL */
1184 			if (EHCI_QTD_GET_CERR(status) == 0)
1185 				return (USB_ERR_IOERROR);
1186 		}
1187 		return (USB_ERR_STALLED);
1188 	}
1189 	return (USB_ERR_NORMAL_COMPLETION);
1190 }
1191 
1192 static void
1193 ehci_non_isoc_done(struct usb_xfer *xfer)
1194 {
1195 	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1196 	ehci_qh_t *qh;
1197 	uint32_t status;
1198 	usb_error_t err = 0;
1199 
1200 	DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1201 	    xfer, xfer->endpoint);
1202 
1203 #ifdef USB_DEBUG
1204 	if (ehcidebug > 10) {
1205 		ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1206 
1207 		ehci_dump_sqtds(sc, xfer->td_transfer_first);
1208 	}
1209 #endif
1210 
1211 	/* extract data toggle directly from the QH's overlay area */
1212 
1213 	qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1214 
1215 	usb_pc_cpu_invalidate(qh->page_cache);
1216 
1217 	status = hc32toh(sc, qh->qh_qtd.qtd_status);
1218 
1219 	/* reset scanner */
1220 
1221 	xfer->td_transfer_cache = xfer->td_transfer_first;
1222 
1223 	if (xfer->flags_int.control_xfr) {
1224 
1225 		if (xfer->flags_int.control_hdr) {
1226 
1227 			err = ehci_non_isoc_done_sub(xfer);
1228 		}
1229 		xfer->aframes = 1;
1230 
1231 		if (xfer->td_transfer_cache == NULL) {
1232 			goto done;
1233 		}
1234 	}
1235 	while (xfer->aframes != xfer->nframes) {
1236 
1237 		err = ehci_non_isoc_done_sub(xfer);
1238 		xfer->aframes++;
1239 
1240 		if (xfer->td_transfer_cache == NULL) {
1241 			goto done;
1242 		}
1243 	}
1244 
1245 	if (xfer->flags_int.control_xfr &&
1246 	    !xfer->flags_int.control_act) {
1247 
1248 		err = ehci_non_isoc_done_sub(xfer);
1249 	}
1250 done:
1251 	ehci_device_done(xfer, err);
1252 }
1253 
1254 /*------------------------------------------------------------------------*
1255  *	ehci_check_transfer
1256  *
1257  * Return values:
1258  *    0: USB transfer is not finished
1259  * Else: USB transfer is finished
1260  *------------------------------------------------------------------------*/
1261 static uint8_t
1262 ehci_check_transfer(struct usb_xfer *xfer)
1263 {
1264 	const struct usb_pipe_methods *methods = xfer->endpoint->methods;
1265 	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1266 
1267 	uint32_t status;
1268 
1269 	DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1270 
1271 	if (methods == &ehci_device_isoc_fs_methods) {
1272 		ehci_sitd_t *td;
1273 
1274 		/* isochronous full speed transfer */
1275 
1276 		td = xfer->td_transfer_last;
1277 		usb_pc_cpu_invalidate(td->page_cache);
1278 		status = hc32toh(sc, td->sitd_status);
1279 
1280 		/* also check if first is complete */
1281 
1282 		td = xfer->td_transfer_first;
1283 		usb_pc_cpu_invalidate(td->page_cache);
1284 		status |= hc32toh(sc, td->sitd_status);
1285 
1286 		if (!(status & EHCI_SITD_ACTIVE)) {
1287 			ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1288 			goto transferred;
1289 		}
1290 	} else if (methods == &ehci_device_isoc_hs_methods) {
1291 		ehci_itd_t *td;
1292 
1293 		/* isochronous high speed transfer */
1294 
1295 		/* check last transfer */
1296 		td = xfer->td_transfer_last;
1297 		usb_pc_cpu_invalidate(td->page_cache);
1298 		status = td->itd_status[0];
1299 		status |= td->itd_status[1];
1300 		status |= td->itd_status[2];
1301 		status |= td->itd_status[3];
1302 		status |= td->itd_status[4];
1303 		status |= td->itd_status[5];
1304 		status |= td->itd_status[6];
1305 		status |= td->itd_status[7];
1306 
1307 		/* also check first transfer */
1308 		td = xfer->td_transfer_first;
1309 		usb_pc_cpu_invalidate(td->page_cache);
1310 		status |= td->itd_status[0];
1311 		status |= td->itd_status[1];
1312 		status |= td->itd_status[2];
1313 		status |= td->itd_status[3];
1314 		status |= td->itd_status[4];
1315 		status |= td->itd_status[5];
1316 		status |= td->itd_status[6];
1317 		status |= td->itd_status[7];
1318 
1319 		/* if no transactions are active we continue */
1320 		if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) {
1321 			ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1322 			goto transferred;
1323 		}
1324 	} else {
1325 		ehci_qtd_t *td;
1326 		ehci_qh_t *qh;
1327 
1328 		/* non-isochronous transfer */
1329 
1330 		/*
1331 		 * check whether there is an error somewhere in the middle,
1332 		 * or whether there was a short packet (SPD and not ACTIVE)
1333 		 */
1334 		td = xfer->td_transfer_cache;
1335 
1336 		qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1337 
1338 		usb_pc_cpu_invalidate(qh->page_cache);
1339 
1340 		status = hc32toh(sc, qh->qh_qtd.qtd_status);
1341 		if (status & EHCI_QTD_ACTIVE) {
1342 			/* transfer is pending */
1343 			goto done;
1344 		}
1345 
1346 		while (1) {
1347 			usb_pc_cpu_invalidate(td->page_cache);
1348 			status = hc32toh(sc, td->qtd_status);
1349 
1350 			/*
1351 			 * Check if there is an active TD which
1352 			 * indicates that the transfer isn't done.
1353 			 */
1354 			if (status & EHCI_QTD_ACTIVE) {
1355 				/* update cache */
1356 				xfer->td_transfer_cache = td;
1357 				goto done;
1358 			}
1359 			/*
1360 			 * last transfer descriptor makes the transfer done
1361 			 */
1362 			if (((void *)td) == xfer->td_transfer_last) {
1363 				break;
1364 			}
1365 			/*
1366 			 * any kind of error makes the transfer done
1367 			 */
1368 			if (status & EHCI_QTD_HALTED) {
1369 				break;
1370 			}
1371 			/*
1372 			 * if there is no alternate next transfer, a short
1373 			 * packet also makes the transfer done
1374 			 */
1375 			if (EHCI_QTD_GET_BYTES(status)) {
1376 				if (xfer->flags_int.short_frames_ok) {
1377 					/* follow alt next */
1378 					if (td->alt_next) {
1379 						td = td->alt_next;
1380 						continue;
1381 					}
1382 				}
1383 				/* transfer is done */
1384 				break;
1385 			}
1386 			td = td->obj_next;
1387 		}
1388 		ehci_non_isoc_done(xfer);
1389 		goto transferred;
1390 	}
1391 
1392 done:
1393 	DPRINTFN(13, "xfer=%p is still active\n", xfer);
1394 	return (0);
1395 
1396 transferred:
1397 	return (1);
1398 }
1399 
1400 static void
1401 ehci_pcd_enable(ehci_softc_t *sc)
1402 {
1403 	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1404 
1405 	sc->sc_eintrs |= EHCI_STS_PCD;
1406 	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1407 
1408 	/* acknowledge any PCD interrupt */
1409 	EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD);
1410 
1411 	ehci_root_intr(sc);
1412 }
1413 
1414 static void
1415 ehci_interrupt_poll(ehci_softc_t *sc)
1416 {
1417 	struct usb_xfer *xfer;
1418 
1419 repeat:
1420 	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1421 		/*
1422 		 * check if transfer is transferred
1423 		 */
1424 		if (ehci_check_transfer(xfer)) {
1425 			/* queue has been modified */
1426 			goto repeat;
1427 		}
1428 	}
1429 }
1430 
1431 /*
1432  * Some EHCI chips from VIA / ATI seem to trigger interrupts before
1433  * writing back the qTD status, or miss signalling occasionally under
1434  * heavy load.  If the host machine is too fast, we can miss
1435  * transaction completion - when we scan the active list the
1436  * transaction still seems to be active. This generally exhibits
1437  * itself as a umass stall that never recovers.
1438  *
1439  * We work around this behaviour by setting up this callback after any
1440  * softintr that completes with transactions still pending, giving us
1441  * another chance to check for completion after the writeback has
1442  * taken place.
1443  */
1444 static void
1445 ehci_poll_timeout(void *arg)
1446 {
1447 	ehci_softc_t *sc = arg;
1448 
1449 	DPRINTFN(3, "\n");
1450 	ehci_interrupt_poll(sc);
1451 }
1452 
1453 /*------------------------------------------------------------------------*
1454  *	ehci_interrupt - EHCI interrupt handler
1455  *
1456  * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1457  * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1458  * is present !
1459  *------------------------------------------------------------------------*/
1460 void
1461 ehci_interrupt(ehci_softc_t *sc)
1462 {
1463 	uint32_t status;
1464 
1465 	USB_BUS_LOCK(&sc->sc_bus);
1466 
1467 	DPRINTFN(16, "real interrupt\n");
1468 
1469 #ifdef USB_DEBUG
1470 	if (ehcidebug > 15) {
1471 		ehci_dump_regs(sc);
1472 	}
1473 #endif
1474 
1475 	status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1476 	if (status == 0) {
1477 		/* the interrupt was not for us */
1478 		goto done;
1479 	}
1480 	if (!(status & sc->sc_eintrs)) {
1481 		goto done;
1482 	}
1483 	EOWRITE4(sc, EHCI_USBSTS, status);	/* acknowledge */
1484 
1485 	status &= sc->sc_eintrs;
1486 
1487 	if (status & EHCI_STS_HSE) {
1488 		printf("%s: unrecoverable error, "
1489 		    "controller halted\n", __FUNCTION__);
1490 #ifdef USB_DEBUG
1491 		ehci_dump_regs(sc);
1492 		ehci_dump_isoc(sc);
1493 #endif
1494 	}
1495 	if (status & EHCI_STS_PCD) {
1496 		/*
1497 		 * Disable PCD interrupt for now, because it will be
1498 		 * on until the port has been reset.
1499 		 */
1500 		sc->sc_eintrs &= ~EHCI_STS_PCD;
1501 		EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1502 
1503 		ehci_root_intr(sc);
1504 
1505 		/* do not allow RHSC interrupts > 1 per second */
1506 		usb_callout_reset(&sc->sc_tmo_pcd, hz,
1507 		    (void *)&ehci_pcd_enable, sc);
1508 	}
1509 	status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA);
1510 
1511 	if (status != 0) {
1512 		/* block unprocessed interrupts */
1513 		sc->sc_eintrs &= ~status;
1514 		EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1515 		printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status);
1516 	}
1517 	/* poll all the USB transfers */
1518 	ehci_interrupt_poll(sc);
1519 
1520 	if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) {
1521 		usb_callout_reset(&sc->sc_tmo_poll, hz / 128,
1522 		    (void *)&ehci_poll_timeout, sc);
1523 	}
1524 
1525 done:
1526 	USB_BUS_UNLOCK(&sc->sc_bus);
1527 }
1528 
1529 /*
1530  * called when a request does not complete
1531  */
1532 static void
1533 ehci_timeout(void *arg)
1534 {
1535 	struct usb_xfer *xfer = arg;
1536 
1537 	DPRINTF("xfer=%p\n", xfer);
1538 
1539 	USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1540 
1541 	/* transfer is transferred */
1542 	ehci_device_done(xfer, USB_ERR_TIMEOUT);
1543 }
1544 
1545 static void
1546 ehci_do_poll(struct usb_bus *bus)
1547 {
1548 	ehci_softc_t *sc = EHCI_BUS2SC(bus);
1549 
1550 	USB_BUS_LOCK(&sc->sc_bus);
1551 	ehci_interrupt_poll(sc);
1552 	USB_BUS_UNLOCK(&sc->sc_bus);
1553 }
1554 
1555 static void
1556 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp)
1557 {
1558 	struct usb_page_search buf_res;
1559 	ehci_qtd_t *td;
1560 	ehci_qtd_t *td_next;
1561 	ehci_qtd_t *td_alt_next;
1562 	uint32_t buf_offset;
1563 	uint32_t average;
1564 	uint32_t len_old;
1565 	uint32_t terminate;
1566 	uint32_t qtd_altnext;
1567 	uint8_t shortpkt_old;
1568 	uint8_t precompute;
1569 
1570 	terminate = temp->sc->sc_terminate_self;
1571 	qtd_altnext = temp->sc->sc_terminate_self;
1572 	td_alt_next = NULL;
1573 	buf_offset = 0;
1574 	shortpkt_old = temp->shortpkt;
1575 	len_old = temp->len;
1576 	precompute = 1;
1577 
1578 restart:
1579 
1580 	td = temp->td;
1581 	td_next = temp->td_next;
1582 
1583 	while (1) {
1584 
1585 		if (temp->len == 0) {
1586 
1587 			if (temp->shortpkt) {
1588 				break;
1589 			}
1590 			/* send a Zero Length Packet, ZLP, last */
1591 
1592 			temp->shortpkt = 1;
1593 			average = 0;
1594 
1595 		} else {
1596 
1597 			average = temp->average;
1598 
1599 			if (temp->len < average) {
1600 				if (temp->len % temp->max_frame_size) {
1601 					temp->shortpkt = 1;
1602 				}
1603 				average = temp->len;
1604 			}
1605 		}
1606 
1607 		if (td_next == NULL) {
1608 			panic("%s: out of EHCI transfer descriptors!", __FUNCTION__);
1609 		}
1610 		/* get next TD */
1611 
1612 		td = td_next;
1613 		td_next = td->obj_next;
1614 
1615 		/* check if we are pre-computing */
1616 
1617 		if (precompute) {
1618 
1619 			/* update remaining length */
1620 
1621 			temp->len -= average;
1622 
1623 			continue;
1624 		}
1625 		/* fill out current TD */
1626 
1627 		td->qtd_status =
1628 		    temp->qtd_status |
1629 		    htohc32(temp->sc, EHCI_QTD_IOC |
1630 			EHCI_QTD_SET_BYTES(average));
1631 
1632 		if (average == 0) {
1633 
1634 			if (temp->auto_data_toggle == 0) {
1635 
1636 				/* update data toggle, ZLP case */
1637 
1638 				temp->qtd_status ^=
1639 				    htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1640 			}
1641 			td->len = 0;
1642 
1643 			/* properly reset reserved fields */
1644 			td->qtd_buffer[0] = 0;
1645 			td->qtd_buffer[1] = 0;
1646 			td->qtd_buffer[2] = 0;
1647 			td->qtd_buffer[3] = 0;
1648 			td->qtd_buffer[4] = 0;
1649 			td->qtd_buffer_hi[0] = 0;
1650 			td->qtd_buffer_hi[1] = 0;
1651 			td->qtd_buffer_hi[2] = 0;
1652 			td->qtd_buffer_hi[3] = 0;
1653 			td->qtd_buffer_hi[4] = 0;
1654 		} else {
1655 
1656 			uint8_t x;
1657 
1658 			if (temp->auto_data_toggle == 0) {
1659 
1660 				/* update data toggle */
1661 
1662 				if (((average + temp->max_frame_size - 1) /
1663 				    temp->max_frame_size) & 1) {
1664 					temp->qtd_status ^=
1665 					    htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1666 				}
1667 			}
1668 			td->len = average;
1669 
1670 			/* update remaining length */
1671 
1672 			temp->len -= average;
1673 
1674 			/* fill out buffer pointers */
1675 
1676 			usbd_get_page(temp->pc, buf_offset, &buf_res);
1677 			td->qtd_buffer[0] =
1678 			    htohc32(temp->sc, buf_res.physaddr);
1679 			td->qtd_buffer_hi[0] = 0;
1680 
1681 			x = 1;
1682 
1683 			while (average > EHCI_PAGE_SIZE) {
1684 				average -= EHCI_PAGE_SIZE;
1685 				buf_offset += EHCI_PAGE_SIZE;
1686 				usbd_get_page(temp->pc, buf_offset, &buf_res);
1687 				td->qtd_buffer[x] =
1688 				    htohc32(temp->sc,
1689 				    buf_res.physaddr & (~0xFFF));
1690 				td->qtd_buffer_hi[x] = 0;
1691 				x++;
1692 			}
1693 
1694 			/*
1695 			 * NOTE: The "average" variable is never zero after
1696 			 * exiting the loop above !
1697 			 *
1698 			 * NOTE: We have to subtract one from the offset to
1699 			 * ensure that we are computing the physical address
1700 			 * of a valid page !
1701 			 */
1702 			buf_offset += average;
1703 			usbd_get_page(temp->pc, buf_offset - 1, &buf_res);
1704 			td->qtd_buffer[x] =
1705 			    htohc32(temp->sc,
1706 			    buf_res.physaddr & (~0xFFF));
1707 			td->qtd_buffer_hi[x] = 0;
1708 
1709 			/* properly reset reserved fields */
1710 			while (++x < EHCI_QTD_NBUFFERS) {
1711 				td->qtd_buffer[x] = 0;
1712 				td->qtd_buffer_hi[x] = 0;
1713 			}
1714 		}
1715 
1716 		if (td_next) {
1717 			/* link the current TD with the next one */
1718 			td->qtd_next = td_next->qtd_self;
1719 		}
1720 		td->qtd_altnext = qtd_altnext;
1721 		td->alt_next = td_alt_next;
1722 
1723 		usb_pc_cpu_flush(td->page_cache);
1724 	}
1725 
1726 	if (precompute) {
1727 		precompute = 0;
1728 
1729 		/* setup alt next pointer, if any */
1730 		if (temp->last_frame) {
1731 			td_alt_next = NULL;
1732 			qtd_altnext = terminate;
1733 		} else {
1734 			/* we use this field internally */
1735 			td_alt_next = td_next;
1736 			if (temp->setup_alt_next) {
1737 				qtd_altnext = td_next->qtd_self;
1738 			} else {
1739 				qtd_altnext = terminate;
1740 			}
1741 		}
1742 
1743 		/* restore */
1744 		temp->shortpkt = shortpkt_old;
1745 		temp->len = len_old;
1746 		goto restart;
1747 	}
1748 	temp->td = td;
1749 	temp->td_next = td_next;
1750 }
1751 
1752 static void
1753 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last)
1754 {
1755 	struct ehci_std_temp temp;
1756 	const struct usb_pipe_methods *methods;
1757 	ehci_qh_t *qh;
1758 	ehci_qtd_t *td;
1759 	uint32_t qh_endp;
1760 	uint32_t qh_endphub;
1761 	uint32_t x;
1762 
1763 	DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1764 	    xfer->address, UE_GET_ADDR(xfer->endpointno),
1765 	    xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1766 
1767 	temp.average = xfer->max_hc_frame_size;
1768 	temp.max_frame_size = xfer->max_frame_size;
1769 	temp.sc = EHCI_BUS2SC(xfer->xroot->bus);
1770 
1771 	/* toggle the DMA set we are using */
1772 	xfer->flags_int.curr_dma_set ^= 1;
1773 
1774 	/* get next DMA set */
1775 	td = xfer->td_start[xfer->flags_int.curr_dma_set];
1776 
1777 	xfer->td_transfer_first = td;
1778 	xfer->td_transfer_cache = td;
1779 
1780 	temp.td = NULL;
1781 	temp.td_next = td;
1782 	temp.qtd_status = 0;
1783 	temp.last_frame = 0;
1784 	temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1785 
1786 	if (xfer->flags_int.control_xfr) {
1787 		if (xfer->endpoint->toggle_next) {
1788 			/* DATA1 is next */
1789 			temp.qtd_status |=
1790 			    htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1791 		}
1792 		temp.auto_data_toggle = 0;
1793 	} else {
1794 		temp.auto_data_toggle = 1;
1795 	}
1796 
1797 	if ((xfer->xroot->udev->parent_hs_hub != NULL) ||
1798 	    (xfer->xroot->udev->address != 0)) {
1799 		/* max 3 retries */
1800 		temp.qtd_status |=
1801 		    htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1802 	}
1803 	/* check if we should prepend a setup message */
1804 
1805 	if (xfer->flags_int.control_xfr) {
1806 		if (xfer->flags_int.control_hdr) {
1807 
1808 			xfer->endpoint->toggle_next = 0;
1809 
1810 			temp.qtd_status &=
1811 			    htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1812 			temp.qtd_status |= htohc32(temp.sc,
1813 			    EHCI_QTD_ACTIVE |
1814 			    EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
1815 			    EHCI_QTD_SET_TOGGLE(0));
1816 
1817 			temp.len = xfer->frlengths[0];
1818 			temp.pc = xfer->frbuffers + 0;
1819 			temp.shortpkt = temp.len ? 1 : 0;
1820 			/* check for last frame */
1821 			if (xfer->nframes == 1) {
1822 				/* no STATUS stage yet, SETUP is last */
1823 				if (xfer->flags_int.control_act) {
1824 					temp.last_frame = 1;
1825 					temp.setup_alt_next = 0;
1826 				}
1827 			}
1828 			ehci_setup_standard_chain_sub(&temp);
1829 		}
1830 		x = 1;
1831 	} else {
1832 		x = 0;
1833 	}
1834 
1835 	while (x != xfer->nframes) {
1836 
1837 		/* DATA0 / DATA1 message */
1838 
1839 		temp.len = xfer->frlengths[x];
1840 		temp.pc = xfer->frbuffers + x;
1841 
1842 		x++;
1843 
1844 		if (x == xfer->nframes) {
1845 			if (xfer->flags_int.control_xfr) {
1846 				/* no STATUS stage yet, DATA is last */
1847 				if (xfer->flags_int.control_act) {
1848 					temp.last_frame = 1;
1849 					temp.setup_alt_next = 0;
1850 				}
1851 			} else {
1852 				temp.last_frame = 1;
1853 				temp.setup_alt_next = 0;
1854 			}
1855 		}
1856 		/* keep previous data toggle and error count */
1857 
1858 		temp.qtd_status &=
1859 		    htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1860 		    EHCI_QTD_SET_TOGGLE(1));
1861 
1862 		if (temp.len == 0) {
1863 
1864 			/* make sure that we send an USB packet */
1865 
1866 			temp.shortpkt = 0;
1867 
1868 		} else {
1869 
1870 			/* regular data transfer */
1871 
1872 			temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1873 		}
1874 
1875 		/* set endpoint direction */
1876 
1877 		temp.qtd_status |=
1878 		    (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1879 		    htohc32(temp.sc, EHCI_QTD_ACTIVE |
1880 		    EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) :
1881 		    htohc32(temp.sc, EHCI_QTD_ACTIVE |
1882 		    EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT));
1883 
1884 		ehci_setup_standard_chain_sub(&temp);
1885 	}
1886 
1887 	/* check if we should append a status stage */
1888 
1889 	if (xfer->flags_int.control_xfr &&
1890 	    !xfer->flags_int.control_act) {
1891 
1892 		/*
1893 		 * Send a DATA1 message and invert the current endpoint
1894 		 * direction.
1895 		 */
1896 
1897 		temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1898 		    EHCI_QTD_SET_TOGGLE(1));
1899 		temp.qtd_status |=
1900 		    (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1901 		    htohc32(temp.sc, EHCI_QTD_ACTIVE |
1902 		    EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) |
1903 		    EHCI_QTD_SET_TOGGLE(1)) :
1904 		    htohc32(temp.sc, EHCI_QTD_ACTIVE |
1905 		    EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) |
1906 		    EHCI_QTD_SET_TOGGLE(1));
1907 
1908 		temp.len = 0;
1909 		temp.pc = NULL;
1910 		temp.shortpkt = 0;
1911 		temp.last_frame = 1;
1912 		temp.setup_alt_next = 0;
1913 
1914 		ehci_setup_standard_chain_sub(&temp);
1915 	}
1916 	td = temp.td;
1917 
1918 	/* the last TD terminates the transfer: */
1919 	td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1920 	td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1921 
1922 	usb_pc_cpu_flush(td->page_cache);
1923 
1924 	/* must have at least one frame! */
1925 
1926 	xfer->td_transfer_last = td;
1927 
1928 #ifdef USB_DEBUG
1929 	if (ehcidebug > 8) {
1930 		DPRINTF("nexttog=%d; data before transfer:\n",
1931 		    xfer->endpoint->toggle_next);
1932 		ehci_dump_sqtds(temp.sc,
1933 		    xfer->td_transfer_first);
1934 	}
1935 #endif
1936 
1937 	methods = xfer->endpoint->methods;
1938 
1939 	qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1940 
1941 	/* the "qh_link" field is filled when the QH is added */
1942 
1943 	qh_endp =
1944 	    (EHCI_QH_SET_ADDR(xfer->address) |
1945 	    EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
1946 	    EHCI_QH_SET_MPL(xfer->max_packet_size));
1947 
1948 	if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
1949 		qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH);
1950 		if (methods != &ehci_device_intr_methods)
1951 			qh_endp |= EHCI_QH_SET_NRL(8);
1952 	} else {
1953 
1954 		if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) {
1955 			qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL);
1956 		} else {
1957 			qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW);
1958 		}
1959 
1960 		if (methods == &ehci_device_ctrl_methods) {
1961 			qh_endp |= EHCI_QH_CTL;
1962 		}
1963 		if (methods != &ehci_device_intr_methods) {
1964 			/* Only try one time per microframe! */
1965 			qh_endp |= EHCI_QH_SET_NRL(1);
1966 		}
1967 	}
1968 
1969 	if (temp.auto_data_toggle == 0) {
1970 		/* software computes the data toggle */
1971 		qh_endp |= EHCI_QH_DTC;
1972 	}
1973 
1974 	qh->qh_endp = htohc32(temp.sc, qh_endp);
1975 
1976 	qh_endphub =
1977 	    (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) |
1978 	    EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) |
1979 	    EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) |
1980 	    EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
1981 	    EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no));
1982 
1983 	qh->qh_endphub = htohc32(temp.sc, qh_endphub);
1984 	qh->qh_curqtd = 0;
1985 
1986 	/* fill the overlay qTD */
1987 
1988 	if (temp.auto_data_toggle && xfer->endpoint->toggle_next) {
1989 		/* DATA1 is next */
1990 		qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1991 	} else {
1992 		qh->qh_qtd.qtd_status = 0;
1993 	}
1994 
1995 	td = xfer->td_transfer_first;
1996 
1997 	qh->qh_qtd.qtd_next = td->qtd_self;
1998 	qh->qh_qtd.qtd_altnext =
1999 	    htohc32(temp.sc, EHCI_LINK_TERMINATE);
2000 
2001 	/* properly reset reserved fields */
2002 	qh->qh_qtd.qtd_buffer[0] = 0;
2003 	qh->qh_qtd.qtd_buffer[1] = 0;
2004 	qh->qh_qtd.qtd_buffer[2] = 0;
2005 	qh->qh_qtd.qtd_buffer[3] = 0;
2006 	qh->qh_qtd.qtd_buffer[4] = 0;
2007 	qh->qh_qtd.qtd_buffer_hi[0] = 0;
2008 	qh->qh_qtd.qtd_buffer_hi[1] = 0;
2009 	qh->qh_qtd.qtd_buffer_hi[2] = 0;
2010 	qh->qh_qtd.qtd_buffer_hi[3] = 0;
2011 	qh->qh_qtd.qtd_buffer_hi[4] = 0;
2012 
2013 	usb_pc_cpu_flush(qh->page_cache);
2014 
2015 	if (xfer->xroot->udev->flags.self_suspended == 0) {
2016 		EHCI_APPEND_QH(qh, *qh_last);
2017 	}
2018 }
2019 
2020 static void
2021 ehci_root_intr(ehci_softc_t *sc)
2022 {
2023 	uint16_t i;
2024 	uint16_t m;
2025 
2026 	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2027 
2028 	/* clear any old interrupt data */
2029 	memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2030 
2031 	/* set bits */
2032 	m = (sc->sc_noport + 1);
2033 	if (m > (8 * sizeof(sc->sc_hub_idata))) {
2034 		m = (8 * sizeof(sc->sc_hub_idata));
2035 	}
2036 	for (i = 1; i < m; i++) {
2037 		/* pick out CHANGE bits from the status register */
2038 		if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) {
2039 			sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2040 			DPRINTF("port %d changed\n", i);
2041 		}
2042 	}
2043 	uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2044 	    sizeof(sc->sc_hub_idata));
2045 }
2046 
2047 static void
2048 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2049 {
2050 	uint32_t nframes = xfer->nframes;
2051 	uint32_t status;
2052 	uint32_t *plen = xfer->frlengths;
2053 	uint16_t len = 0;
2054 	ehci_sitd_t *td = xfer->td_transfer_first;
2055 	ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos];
2056 
2057 	DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2058 	    xfer, xfer->endpoint);
2059 
2060 	while (nframes--) {
2061 		if (td == NULL) {
2062 			panic("%s:%d: out of TD's\n",
2063 			    __FUNCTION__, __LINE__);
2064 		}
2065 		if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2066 			pp_last = &sc->sc_isoc_fs_p_last[0];
2067 		}
2068 #ifdef USB_DEBUG
2069 		if (ehcidebug > 15) {
2070 			DPRINTF("isoc FS-TD\n");
2071 			ehci_dump_sitd(sc, td);
2072 		}
2073 #endif
2074 		usb_pc_cpu_invalidate(td->page_cache);
2075 		status = hc32toh(sc, td->sitd_status);
2076 
2077 		len = EHCI_SITD_GET_LEN(status);
2078 
2079 		DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len);
2080 
2081 		if (*plen >= len) {
2082 			len = *plen - len;
2083 		} else {
2084 			len = 0;
2085 		}
2086 
2087 		*plen = len;
2088 
2089 		/* remove FS-TD from schedule */
2090 		EHCI_REMOVE_FS_TD(td, *pp_last);
2091 
2092 		pp_last++;
2093 		plen++;
2094 		td = td->obj_next;
2095 	}
2096 
2097 	xfer->aframes = xfer->nframes;
2098 }
2099 
2100 static void
2101 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2102 {
2103 	uint32_t nframes = xfer->nframes;
2104 	uint32_t status;
2105 	uint32_t *plen = xfer->frlengths;
2106 	uint16_t len = 0;
2107 	uint8_t td_no = 0;
2108 	ehci_itd_t *td = xfer->td_transfer_first;
2109 	ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos];
2110 
2111 	DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2112 	    xfer, xfer->endpoint);
2113 
2114 	while (nframes) {
2115 		if (td == NULL) {
2116 			panic("%s:%d: out of TD's\n",
2117 			    __FUNCTION__, __LINE__);
2118 		}
2119 		if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2120 			pp_last = &sc->sc_isoc_hs_p_last[0];
2121 		}
2122 #ifdef USB_DEBUG
2123 		if (ehcidebug > 15) {
2124 			DPRINTF("isoc HS-TD\n");
2125 			ehci_dump_itd(sc, td);
2126 		}
2127 #endif
2128 
2129 		usb_pc_cpu_invalidate(td->page_cache);
2130 		status = hc32toh(sc, td->itd_status[td_no]);
2131 
2132 		len = EHCI_ITD_GET_LEN(status);
2133 
2134 		DPRINTFN(2, "status=0x%08x, len=%u\n", status, len);
2135 
2136 		if (xfer->endpoint->usb_smask & (1 << td_no)) {
2137 
2138 			if (*plen >= len) {
2139 				/*
2140 				 * The length is valid. NOTE: The
2141 				 * complete length is written back
2142 				 * into the status field, and not the
2143 				 * remainder like with other transfer
2144 				 * descriptor types.
2145 				 */
2146 			} else {
2147 				/* Invalid length - truncate */
2148 				len = 0;
2149 			}
2150 
2151 			*plen = len;
2152 			plen++;
2153 			nframes--;
2154 		}
2155 
2156 		td_no++;
2157 
2158 		if ((td_no == 8) || (nframes == 0)) {
2159 			/* remove HS-TD from schedule */
2160 			EHCI_REMOVE_HS_TD(td, *pp_last);
2161 			pp_last++;
2162 
2163 			td_no = 0;
2164 			td = td->obj_next;
2165 		}
2166 	}
2167 	xfer->aframes = xfer->nframes;
2168 }
2169 
2170 /* NOTE: "done" can be run two times in a row,
2171  * from close and from interrupt
2172  */
2173 static void
2174 ehci_device_done(struct usb_xfer *xfer, usb_error_t error)
2175 {
2176 	const struct usb_pipe_methods *methods = xfer->endpoint->methods;
2177 	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2178 
2179 	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2180 
2181 	DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2182 	    xfer, xfer->endpoint, error);
2183 
2184 	if ((methods == &ehci_device_bulk_methods) ||
2185 	    (methods == &ehci_device_ctrl_methods)) {
2186 #ifdef USB_DEBUG
2187 		if (ehcidebug > 8) {
2188 			DPRINTF("nexttog=%d; data after transfer:\n",
2189 			    xfer->endpoint->toggle_next);
2190 			ehci_dump_sqtds(sc,
2191 			    xfer->td_transfer_first);
2192 		}
2193 #endif
2194 
2195 		EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2196 		    sc->sc_async_p_last);
2197 	}
2198 	if (methods == &ehci_device_intr_methods) {
2199 		EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2200 		    sc->sc_intr_p_last[xfer->qh_pos]);
2201 	}
2202 	/*
2203 	 * Only finish isochronous transfers once which will update
2204 	 * "xfer->frlengths".
2205 	 */
2206 	if (xfer->td_transfer_first &&
2207 	    xfer->td_transfer_last) {
2208 		if (methods == &ehci_device_isoc_fs_methods) {
2209 			ehci_isoc_fs_done(sc, xfer);
2210 		}
2211 		if (methods == &ehci_device_isoc_hs_methods) {
2212 			ehci_isoc_hs_done(sc, xfer);
2213 		}
2214 		xfer->td_transfer_first = NULL;
2215 		xfer->td_transfer_last = NULL;
2216 	}
2217 	/* dequeue transfer and start next transfer */
2218 	usbd_transfer_done(xfer, error);
2219 }
2220 
2221 /*------------------------------------------------------------------------*
2222  * ehci bulk support
2223  *------------------------------------------------------------------------*/
2224 static void
2225 ehci_device_bulk_open(struct usb_xfer *xfer)
2226 {
2227 	return;
2228 }
2229 
2230 static void
2231 ehci_device_bulk_close(struct usb_xfer *xfer)
2232 {
2233 	ehci_device_done(xfer, USB_ERR_CANCELLED);
2234 }
2235 
2236 static void
2237 ehci_device_bulk_enter(struct usb_xfer *xfer)
2238 {
2239 	return;
2240 }
2241 
2242 static void
2243 ehci_doorbell_async(struct ehci_softc *sc)
2244 {
2245 	uint32_t temp;
2246 
2247 	/*
2248 	 * XXX Performance quirk: Some Host Controllers have a too low
2249 	 * interrupt rate. Issue an IAAD to stimulate the Host
2250 	 * Controller after queueing the BULK transfer.
2251 	 *
2252 	 * XXX Force the host controller to refresh any QH caches.
2253 	 */
2254 	temp = EOREAD4(sc, EHCI_USBCMD);
2255 	if (!(temp & EHCI_CMD_IAAD))
2256 		EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD);
2257 }
2258 
2259 static void
2260 ehci_device_bulk_start(struct usb_xfer *xfer)
2261 {
2262 	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2263 
2264 	/* setup TD's and QH */
2265 	ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2266 
2267 	/* put transfer on interrupt queue */
2268 	ehci_transfer_intr_enqueue(xfer);
2269 
2270 	/*
2271 	 * XXX Certain nVidia chipsets choke when using the IAAD
2272 	 * feature too frequently.
2273 	 */
2274 	if (sc->sc_flags & EHCI_SCFLG_IAADBUG)
2275 		return;
2276 
2277 	ehci_doorbell_async(sc);
2278 }
2279 
2280 static const struct usb_pipe_methods ehci_device_bulk_methods =
2281 {
2282 	.open = ehci_device_bulk_open,
2283 	.close = ehci_device_bulk_close,
2284 	.enter = ehci_device_bulk_enter,
2285 	.start = ehci_device_bulk_start,
2286 };
2287 
2288 /*------------------------------------------------------------------------*
2289  * ehci control support
2290  *------------------------------------------------------------------------*/
2291 static void
2292 ehci_device_ctrl_open(struct usb_xfer *xfer)
2293 {
2294 	return;
2295 }
2296 
2297 static void
2298 ehci_device_ctrl_close(struct usb_xfer *xfer)
2299 {
2300 	ehci_device_done(xfer, USB_ERR_CANCELLED);
2301 }
2302 
2303 static void
2304 ehci_device_ctrl_enter(struct usb_xfer *xfer)
2305 {
2306 	return;
2307 }
2308 
2309 static void
2310 ehci_device_ctrl_start(struct usb_xfer *xfer)
2311 {
2312 	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2313 
2314 	/* setup TD's and QH */
2315 	ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2316 
2317 	/* put transfer on interrupt queue */
2318 	ehci_transfer_intr_enqueue(xfer);
2319 }
2320 
2321 static const struct usb_pipe_methods ehci_device_ctrl_methods =
2322 {
2323 	.open = ehci_device_ctrl_open,
2324 	.close = ehci_device_ctrl_close,
2325 	.enter = ehci_device_ctrl_enter,
2326 	.start = ehci_device_ctrl_start,
2327 };
2328 
2329 /*------------------------------------------------------------------------*
2330  * ehci interrupt support
2331  *------------------------------------------------------------------------*/
2332 static void
2333 ehci_device_intr_open(struct usb_xfer *xfer)
2334 {
2335 	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2336 	uint16_t best;
2337 	uint16_t bit;
2338 	uint16_t x;
2339 
2340 	usb_hs_bandwidth_alloc(xfer);
2341 
2342 	/*
2343 	 * Find the best QH position corresponding to the given interval:
2344 	 */
2345 
2346 	best = 0;
2347 	bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
2348 	while (bit) {
2349 		if (xfer->interval >= bit) {
2350 			x = bit;
2351 			best = bit;
2352 			while (x & bit) {
2353 				if (sc->sc_intr_stat[x] <
2354 				    sc->sc_intr_stat[best]) {
2355 					best = x;
2356 				}
2357 				x++;
2358 			}
2359 			break;
2360 		}
2361 		bit >>= 1;
2362 	}
2363 
2364 	sc->sc_intr_stat[best]++;
2365 	xfer->qh_pos = best;
2366 
2367 	DPRINTFN(3, "best=%d interval=%d\n",
2368 	    best, xfer->interval);
2369 }
2370 
2371 static void
2372 ehci_device_intr_close(struct usb_xfer *xfer)
2373 {
2374 	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2375 
2376 	sc->sc_intr_stat[xfer->qh_pos]--;
2377 
2378 	ehci_device_done(xfer, USB_ERR_CANCELLED);
2379 
2380 	/* bandwidth must be freed after device done */
2381 	usb_hs_bandwidth_free(xfer);
2382 }
2383 
2384 static void
2385 ehci_device_intr_enter(struct usb_xfer *xfer)
2386 {
2387 	return;
2388 }
2389 
2390 static void
2391 ehci_device_intr_start(struct usb_xfer *xfer)
2392 {
2393 	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2394 
2395 	/* setup TD's and QH */
2396 	ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
2397 
2398 	/* put transfer on interrupt queue */
2399 	ehci_transfer_intr_enqueue(xfer);
2400 }
2401 
2402 static const struct usb_pipe_methods ehci_device_intr_methods =
2403 {
2404 	.open = ehci_device_intr_open,
2405 	.close = ehci_device_intr_close,
2406 	.enter = ehci_device_intr_enter,
2407 	.start = ehci_device_intr_start,
2408 };
2409 
2410 /*------------------------------------------------------------------------*
2411  * ehci full speed isochronous support
2412  *------------------------------------------------------------------------*/
2413 static void
2414 ehci_device_isoc_fs_open(struct usb_xfer *xfer)
2415 {
2416 	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2417 	ehci_sitd_t *td;
2418 	uint32_t sitd_portaddr;
2419 	uint8_t ds;
2420 
2421 	sitd_portaddr =
2422 	    EHCI_SITD_SET_ADDR(xfer->address) |
2423 	    EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2424 	    EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2425 	    EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no);
2426 
2427 	if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN)
2428 		sitd_portaddr |= EHCI_SITD_SET_DIR_IN;
2429 
2430 	sitd_portaddr = htohc32(sc, sitd_portaddr);
2431 
2432 	/* initialize all TD's */
2433 
2434 	for (ds = 0; ds != 2; ds++) {
2435 
2436 		for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2437 
2438 			td->sitd_portaddr = sitd_portaddr;
2439 
2440 			/*
2441 			 * TODO: make some kind of automatic
2442 			 * SMASK/CMASK selection based on micro-frame
2443 			 * usage
2444 			 *
2445 			 * micro-frame usage (8 microframes per 1ms)
2446 			 */
2447 			td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE);
2448 
2449 			usb_pc_cpu_flush(td->page_cache);
2450 		}
2451 	}
2452 }
2453 
2454 static void
2455 ehci_device_isoc_fs_close(struct usb_xfer *xfer)
2456 {
2457 	ehci_device_done(xfer, USB_ERR_CANCELLED);
2458 }
2459 
2460 static void
2461 ehci_device_isoc_fs_enter(struct usb_xfer *xfer)
2462 {
2463 	struct usb_page_search buf_res;
2464 	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2465 	ehci_sitd_t *td;
2466 	ehci_sitd_t *td_last = NULL;
2467 	ehci_sitd_t **pp_last;
2468 	uint32_t *plen;
2469 	uint32_t buf_offset;
2470 	uint32_t nframes;
2471 	uint32_t temp;
2472 	uint32_t sitd_mask;
2473 	uint16_t tlen;
2474 	uint8_t sa;
2475 	uint8_t sb;
2476 
2477 #ifdef USB_DEBUG
2478 	uint8_t once = 1;
2479 
2480 #endif
2481 
2482 	DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2483 	    xfer, xfer->endpoint->isoc_next, xfer->nframes);
2484 
2485 	/* get the current frame index */
2486 
2487 	nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2488 
2489 	/*
2490 	 * check if the frame index is within the window where the frames
2491 	 * will be inserted
2492 	 */
2493 	buf_offset = (nframes - xfer->endpoint->isoc_next) &
2494 	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2495 
2496 	if ((xfer->endpoint->is_synced == 0) ||
2497 	    (buf_offset < xfer->nframes)) {
2498 		/*
2499 		 * If there is data underflow or the pipe queue is empty we
2500 		 * schedule the transfer a few frames ahead of the current
2501 		 * frame position. Else two isochronous transfers might
2502 		 * overlap.
2503 		 */
2504 		xfer->endpoint->isoc_next = (nframes + 3) &
2505 		    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2506 		xfer->endpoint->is_synced = 1;
2507 		DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2508 	}
2509 	/*
2510 	 * compute how many milliseconds the insertion is ahead of the
2511 	 * current frame position:
2512 	 */
2513 	buf_offset = (xfer->endpoint->isoc_next - nframes) &
2514 	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2515 
2516 	/*
2517 	 * pre-compute when the isochronous transfer will be finished:
2518 	 */
2519 	xfer->isoc_time_complete =
2520 	    usb_isoc_time_expand(&sc->sc_bus, nframes) +
2521 	    buf_offset + xfer->nframes;
2522 
2523 	/* get the real number of frames */
2524 
2525 	nframes = xfer->nframes;
2526 
2527 	buf_offset = 0;
2528 
2529 	plen = xfer->frlengths;
2530 
2531 	/* toggle the DMA set we are using */
2532 	xfer->flags_int.curr_dma_set ^= 1;
2533 
2534 	/* get next DMA set */
2535 	td = xfer->td_start[xfer->flags_int.curr_dma_set];
2536 	xfer->td_transfer_first = td;
2537 
2538 	pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next];
2539 
2540 	/* store starting position */
2541 
2542 	xfer->qh_pos = xfer->endpoint->isoc_next;
2543 
2544 	while (nframes--) {
2545 		if (td == NULL) {
2546 			panic("%s:%d: out of TD's\n",
2547 			    __FUNCTION__, __LINE__);
2548 		}
2549 		if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT])
2550 			pp_last = &sc->sc_isoc_fs_p_last[0];
2551 
2552 		/* reuse sitd_portaddr and sitd_back from last transfer */
2553 
2554 		if (*plen > xfer->max_frame_size) {
2555 #ifdef USB_DEBUG
2556 			if (once) {
2557 				once = 0;
2558 				printf("%s: frame length(%d) exceeds %d "
2559 				    "bytes (frame truncated)\n",
2560 				    __FUNCTION__, *plen,
2561 				    xfer->max_frame_size);
2562 			}
2563 #endif
2564 			*plen = xfer->max_frame_size;
2565 		}
2566 
2567 		/* allocate a slot */
2568 
2569 		sa = usbd_fs_isoc_schedule_alloc_slot(xfer,
2570 		    xfer->isoc_time_complete - nframes - 1);
2571 
2572 		if (sa == 255) {
2573 			/*
2574 			 * Schedule is FULL, set length to zero:
2575 			 */
2576 
2577 			*plen = 0;
2578 			sa = USB_FS_ISOC_UFRAME_MAX - 1;
2579 		}
2580 		if (*plen) {
2581 			/*
2582 			 * only call "usbd_get_page()" when we have a
2583 			 * non-zero length
2584 			 */
2585 			usbd_get_page(xfer->frbuffers, buf_offset, &buf_res);
2586 			td->sitd_bp[0] = htohc32(sc, buf_res.physaddr);
2587 			buf_offset += *plen;
2588 			/*
2589 			 * NOTE: We need to subtract one from the offset so
2590 			 * that we are on a valid page!
2591 			 */
2592 			usbd_get_page(xfer->frbuffers, buf_offset - 1,
2593 			    &buf_res);
2594 			temp = buf_res.physaddr & ~0xFFF;
2595 		} else {
2596 			td->sitd_bp[0] = 0;
2597 			temp = 0;
2598 		}
2599 
2600 		if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) {
2601 			tlen = *plen;
2602 			if (tlen <= 188) {
2603 				temp |= 1;	/* T-count = 1, TP = ALL */
2604 				tlen = 1;
2605 			} else {
2606 				tlen += 187;
2607 				tlen /= 188;
2608 				temp |= tlen;	/* T-count = [1..6] */
2609 				temp |= 8;	/* TP = Begin */
2610 			}
2611 
2612 			tlen += sa;
2613 
2614 			if (tlen >= 8) {
2615 				sb = 0;
2616 			} else {
2617 				sb = (1 << tlen);
2618 			}
2619 
2620 			sa = (1 << sa);
2621 			sa = (sb - sa) & 0x3F;
2622 			sb = 0;
2623 		} else {
2624 			sb = (-(4 << sa)) & 0xFE;
2625 			sa = (1 << sa) & 0x3F;
2626 		}
2627 
2628 		sitd_mask = (EHCI_SITD_SET_SMASK(sa) |
2629 		    EHCI_SITD_SET_CMASK(sb));
2630 
2631 		td->sitd_bp[1] = htohc32(sc, temp);
2632 
2633 		td->sitd_mask = htohc32(sc, sitd_mask);
2634 
2635 		if (nframes == 0) {
2636 			td->sitd_status = htohc32(sc,
2637 			    EHCI_SITD_IOC |
2638 			    EHCI_SITD_ACTIVE |
2639 			    EHCI_SITD_SET_LEN(*plen));
2640 		} else {
2641 			td->sitd_status = htohc32(sc,
2642 			    EHCI_SITD_ACTIVE |
2643 			    EHCI_SITD_SET_LEN(*plen));
2644 		}
2645 		usb_pc_cpu_flush(td->page_cache);
2646 
2647 #ifdef USB_DEBUG
2648 		if (ehcidebug > 15) {
2649 			DPRINTF("FS-TD %d\n", nframes);
2650 			ehci_dump_sitd(sc, td);
2651 		}
2652 #endif
2653 		/* insert TD into schedule */
2654 		EHCI_APPEND_FS_TD(td, *pp_last);
2655 		pp_last++;
2656 
2657 		plen++;
2658 		td_last = td;
2659 		td = td->obj_next;
2660 	}
2661 
2662 	xfer->td_transfer_last = td_last;
2663 
2664 	/* update isoc_next */
2665 	xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) &
2666 	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2667 
2668 	/*
2669 	 * We don't allow cancelling of the SPLIT transaction USB FULL
2670 	 * speed transfer, because it disturbs the bandwidth
2671 	 * computation algorithm.
2672 	 */
2673 	xfer->flags_int.can_cancel_immed = 0;
2674 }
2675 
2676 static void
2677 ehci_device_isoc_fs_start(struct usb_xfer *xfer)
2678 {
2679 	/*
2680 	 * We don't allow cancelling of the SPLIT transaction USB FULL
2681 	 * speed transfer, because it disturbs the bandwidth
2682 	 * computation algorithm.
2683 	 */
2684 	xfer->flags_int.can_cancel_immed = 0;
2685 
2686 	/* set a default timeout */
2687 	if (xfer->timeout == 0)
2688 		xfer->timeout = 500; /* ms */
2689 
2690 	/* put transfer on interrupt queue */
2691 	ehci_transfer_intr_enqueue(xfer);
2692 }
2693 
2694 static const struct usb_pipe_methods ehci_device_isoc_fs_methods =
2695 {
2696 	.open = ehci_device_isoc_fs_open,
2697 	.close = ehci_device_isoc_fs_close,
2698 	.enter = ehci_device_isoc_fs_enter,
2699 	.start = ehci_device_isoc_fs_start,
2700 };
2701 
2702 /*------------------------------------------------------------------------*
2703  * ehci high speed isochronous support
2704  *------------------------------------------------------------------------*/
2705 static void
2706 ehci_device_isoc_hs_open(struct usb_xfer *xfer)
2707 {
2708 	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2709 	ehci_itd_t *td;
2710 	uint32_t temp;
2711 	uint8_t ds;
2712 
2713 	usb_hs_bandwidth_alloc(xfer);
2714 
2715 	/* initialize all TD's */
2716 
2717 	for (ds = 0; ds != 2; ds++) {
2718 
2719 		for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2720 
2721 			/* set TD inactive */
2722 			td->itd_status[0] = 0;
2723 			td->itd_status[1] = 0;
2724 			td->itd_status[2] = 0;
2725 			td->itd_status[3] = 0;
2726 			td->itd_status[4] = 0;
2727 			td->itd_status[5] = 0;
2728 			td->itd_status[6] = 0;
2729 			td->itd_status[7] = 0;
2730 
2731 			/* set endpoint and address */
2732 			td->itd_bp[0] = htohc32(sc,
2733 			    EHCI_ITD_SET_ADDR(xfer->address) |
2734 			    EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)));
2735 
2736 			temp =
2737 			    EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF);
2738 
2739 			/* set direction */
2740 			if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2741 				temp |= EHCI_ITD_SET_DIR_IN;
2742 			}
2743 			/* set maximum packet size */
2744 			td->itd_bp[1] = htohc32(sc, temp);
2745 
2746 			/* set transfer multiplier */
2747 			td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3);
2748 
2749 			usb_pc_cpu_flush(td->page_cache);
2750 		}
2751 	}
2752 }
2753 
2754 static void
2755 ehci_device_isoc_hs_close(struct usb_xfer *xfer)
2756 {
2757 	ehci_device_done(xfer, USB_ERR_CANCELLED);
2758 
2759 	/* bandwidth must be freed after device done */
2760 	usb_hs_bandwidth_free(xfer);
2761 }
2762 
2763 static void
2764 ehci_device_isoc_hs_enter(struct usb_xfer *xfer)
2765 {
2766 	struct usb_page_search buf_res;
2767 	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2768 	ehci_itd_t *td;
2769 	ehci_itd_t *td_last = NULL;
2770 	ehci_itd_t **pp_last;
2771 	bus_size_t page_addr;
2772 	uint32_t *plen;
2773 	uint32_t status;
2774 	uint32_t buf_offset;
2775 	uint32_t nframes;
2776 	uint32_t itd_offset[8 + 1];
2777 	uint8_t x;
2778 	uint8_t td_no;
2779 	uint8_t page_no;
2780 	uint8_t shift = usbd_xfer_get_fps_shift(xfer);
2781 
2782 #ifdef USB_DEBUG
2783 	uint8_t once = 1;
2784 
2785 #endif
2786 
2787 	DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n",
2788 	    xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift);
2789 
2790 	/* get the current frame index */
2791 
2792 	nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2793 
2794 	/*
2795 	 * check if the frame index is within the window where the frames
2796 	 * will be inserted
2797 	 */
2798 	buf_offset = (nframes - xfer->endpoint->isoc_next) &
2799 	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2800 
2801 	if ((xfer->endpoint->is_synced == 0) ||
2802 	    (buf_offset < (((xfer->nframes << shift) + 7) / 8))) {
2803 		/*
2804 		 * If there is data underflow or the pipe queue is empty we
2805 		 * schedule the transfer a few frames ahead of the current
2806 		 * frame position. Else two isochronous transfers might
2807 		 * overlap.
2808 		 */
2809 		xfer->endpoint->isoc_next = (nframes + 3) &
2810 		    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2811 		xfer->endpoint->is_synced = 1;
2812 		DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2813 	}
2814 	/*
2815 	 * compute how many milliseconds the insertion is ahead of the
2816 	 * current frame position:
2817 	 */
2818 	buf_offset = (xfer->endpoint->isoc_next - nframes) &
2819 	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2820 
2821 	/*
2822 	 * pre-compute when the isochronous transfer will be finished:
2823 	 */
2824 	xfer->isoc_time_complete =
2825 	    usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
2826 	    (((xfer->nframes << shift) + 7) / 8);
2827 
2828 	/* get the real number of frames */
2829 
2830 	nframes = xfer->nframes;
2831 
2832 	buf_offset = 0;
2833 	td_no = 0;
2834 
2835 	plen = xfer->frlengths;
2836 
2837 	/* toggle the DMA set we are using */
2838 	xfer->flags_int.curr_dma_set ^= 1;
2839 
2840 	/* get next DMA set */
2841 	td = xfer->td_start[xfer->flags_int.curr_dma_set];
2842 	xfer->td_transfer_first = td;
2843 
2844 	pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next];
2845 
2846 	/* store starting position */
2847 
2848 	xfer->qh_pos = xfer->endpoint->isoc_next;
2849 
2850 	while (nframes) {
2851 		if (td == NULL) {
2852 			panic("%s:%d: out of TD's\n",
2853 			    __FUNCTION__, __LINE__);
2854 		}
2855 		if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2856 			pp_last = &sc->sc_isoc_hs_p_last[0];
2857 		}
2858 		/* range check */
2859 		if (*plen > xfer->max_frame_size) {
2860 #ifdef USB_DEBUG
2861 			if (once) {
2862 				once = 0;
2863 				printf("%s: frame length(%d) exceeds %d bytes "
2864 				    "(frame truncated)\n",
2865 				    __FUNCTION__, *plen, xfer->max_frame_size);
2866 			}
2867 #endif
2868 			*plen = xfer->max_frame_size;
2869 		}
2870 
2871 		if (xfer->endpoint->usb_smask & (1 << td_no)) {
2872 			status = (EHCI_ITD_SET_LEN(*plen) |
2873 			    EHCI_ITD_ACTIVE |
2874 			    EHCI_ITD_SET_PG(0));
2875 			td->itd_status[td_no] = htohc32(sc, status);
2876 			itd_offset[td_no] = buf_offset;
2877 			buf_offset += *plen;
2878 			plen++;
2879 			nframes --;
2880 		} else {
2881 			td->itd_status[td_no] = 0;	/* not active */
2882 			itd_offset[td_no] = buf_offset;
2883 		}
2884 
2885 		td_no++;
2886 
2887 		if ((td_no == 8) || (nframes == 0)) {
2888 
2889 			/* the rest of the transfers are not active, if any */
2890 			for (x = td_no; x != 8; x++) {
2891 				td->itd_status[x] = 0;	/* not active */
2892 			}
2893 
2894 			/* check if there is any data to be transferred */
2895 			if (itd_offset[0] != buf_offset) {
2896 				page_no = 0;
2897 				itd_offset[td_no] = buf_offset;
2898 
2899 				/* get first page offset */
2900 				usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res);
2901 				/* get page address */
2902 				page_addr = buf_res.physaddr & ~0xFFF;
2903 				/* update page address */
2904 				td->itd_bp[0] &= htohc32(sc, 0xFFF);
2905 				td->itd_bp[0] |= htohc32(sc, page_addr);
2906 
2907 				for (x = 0; x != td_no; x++) {
2908 					/* set page number and page offset */
2909 					status = (EHCI_ITD_SET_PG(page_no) |
2910 					    (buf_res.physaddr & 0xFFF));
2911 					td->itd_status[x] |= htohc32(sc, status);
2912 
2913 					/* get next page offset */
2914 					if (itd_offset[x + 1] == buf_offset) {
2915 						/*
2916 						 * We subtract one so that
2917 						 * we don't go off the last
2918 						 * page!
2919 						 */
2920 						usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
2921 					} else {
2922 						usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res);
2923 					}
2924 
2925 					/* check if we need a new page */
2926 					if ((buf_res.physaddr ^ page_addr) & ~0xFFF) {
2927 						/* new page needed */
2928 						page_addr = buf_res.physaddr & ~0xFFF;
2929 						if (page_no == 6) {
2930 							panic("%s: too many pages\n", __FUNCTION__);
2931 						}
2932 						page_no++;
2933 						/* update page address */
2934 						td->itd_bp[page_no] &= htohc32(sc, 0xFFF);
2935 						td->itd_bp[page_no] |= htohc32(sc, page_addr);
2936 					}
2937 				}
2938 			}
2939 			/* set IOC bit if we are complete */
2940 			if (nframes == 0) {
2941 				td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC);
2942 			}
2943 			usb_pc_cpu_flush(td->page_cache);
2944 #ifdef USB_DEBUG
2945 			if (ehcidebug > 15) {
2946 				DPRINTF("HS-TD %d\n", nframes);
2947 				ehci_dump_itd(sc, td);
2948 			}
2949 #endif
2950 			/* insert TD into schedule */
2951 			EHCI_APPEND_HS_TD(td, *pp_last);
2952 			pp_last++;
2953 
2954 			td_no = 0;
2955 			td_last = td;
2956 			td = td->obj_next;
2957 		}
2958 	}
2959 
2960 	xfer->td_transfer_last = td_last;
2961 
2962 	/* update isoc_next */
2963 	xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) &
2964 	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2965 }
2966 
2967 static void
2968 ehci_device_isoc_hs_start(struct usb_xfer *xfer)
2969 {
2970 	/* put transfer on interrupt queue */
2971 	ehci_transfer_intr_enqueue(xfer);
2972 }
2973 
2974 static const struct usb_pipe_methods ehci_device_isoc_hs_methods =
2975 {
2976 	.open = ehci_device_isoc_hs_open,
2977 	.close = ehci_device_isoc_hs_close,
2978 	.enter = ehci_device_isoc_hs_enter,
2979 	.start = ehci_device_isoc_hs_start,
2980 };
2981 
2982 /*------------------------------------------------------------------------*
2983  * ehci root control support
2984  *------------------------------------------------------------------------*
2985  * Simulate a hardware hub by handling all the necessary requests.
2986  *------------------------------------------------------------------------*/
2987 
2988 static const
2989 struct usb_device_descriptor ehci_devd =
2990 {
2991 	sizeof(struct usb_device_descriptor),
2992 	UDESC_DEVICE,			/* type */
2993 	{0x00, 0x02},			/* USB version */
2994 	UDCLASS_HUB,			/* class */
2995 	UDSUBCLASS_HUB,			/* subclass */
2996 	UDPROTO_HSHUBSTT,		/* protocol */
2997 	64,				/* max packet */
2998 	{0}, {0}, {0x00, 0x01},		/* device id */
2999 	1, 2, 0,			/* string indicies */
3000 	1				/* # of configurations */
3001 };
3002 
3003 static const
3004 struct usb_device_qualifier ehci_odevd =
3005 {
3006 	sizeof(struct usb_device_qualifier),
3007 	UDESC_DEVICE_QUALIFIER,		/* type */
3008 	{0x00, 0x02},			/* USB version */
3009 	UDCLASS_HUB,			/* class */
3010 	UDSUBCLASS_HUB,			/* subclass */
3011 	UDPROTO_FSHUB,			/* protocol */
3012 	0,				/* max packet */
3013 	0,				/* # of configurations */
3014 	0
3015 };
3016 
3017 static const struct ehci_config_desc ehci_confd = {
3018 	.confd = {
3019 		.bLength = sizeof(struct usb_config_descriptor),
3020 		.bDescriptorType = UDESC_CONFIG,
3021 		.wTotalLength[0] = sizeof(ehci_confd),
3022 		.bNumInterface = 1,
3023 		.bConfigurationValue = 1,
3024 		.iConfiguration = 0,
3025 		.bmAttributes = UC_SELF_POWERED,
3026 		.bMaxPower = 0		/* max power */
3027 	},
3028 	.ifcd = {
3029 		.bLength = sizeof(struct usb_interface_descriptor),
3030 		.bDescriptorType = UDESC_INTERFACE,
3031 		.bNumEndpoints = 1,
3032 		.bInterfaceClass = UICLASS_HUB,
3033 		.bInterfaceSubClass = UISUBCLASS_HUB,
3034 		.bInterfaceProtocol = 0,
3035 	},
3036 	.endpd = {
3037 		.bLength = sizeof(struct usb_endpoint_descriptor),
3038 		.bDescriptorType = UDESC_ENDPOINT,
3039 		.bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT,
3040 		.bmAttributes = UE_INTERRUPT,
3041 		.wMaxPacketSize[0] = 8,	/* max packet (63 ports) */
3042 		.bInterval = 255,
3043 	},
3044 };
3045 
3046 static const
3047 struct usb_hub_descriptor ehci_hubd =
3048 {
3049 	.bDescLength = 0,		/* dynamic length */
3050 	.bDescriptorType = UDESC_HUB,
3051 };
3052 
3053 uint16_t
3054 ehci_get_port_speed_portsc(struct ehci_softc *sc, uint16_t index)
3055 {
3056 	uint32_t v;
3057 
3058 	v = EOREAD4(sc, EHCI_PORTSC(index));
3059 	v = (v >> EHCI_PORTSC_PSPD_SHIFT) & EHCI_PORTSC_PSPD_MASK;
3060 
3061 	if (v == EHCI_PORT_SPEED_HIGH)
3062 		return (UPS_HIGH_SPEED);
3063 	if (v == EHCI_PORT_SPEED_LOW)
3064 		return (UPS_LOW_SPEED);
3065 	return (0);
3066 }
3067 
3068 uint16_t
3069 ehci_get_port_speed_hostc(struct ehci_softc *sc, uint16_t index)
3070 {
3071 	uint32_t v;
3072 
3073 	v = EOREAD4(sc, EHCI_HOSTC(index));
3074 	v = (v >> EHCI_HOSTC_PSPD_SHIFT) & EHCI_HOSTC_PSPD_MASK;
3075 
3076 	if (v == EHCI_PORT_SPEED_HIGH)
3077 		return (UPS_HIGH_SPEED);
3078 	if (v == EHCI_PORT_SPEED_LOW)
3079 		return (UPS_LOW_SPEED);
3080 	return (0);
3081 }
3082 
3083 static void
3084 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed)
3085 {
3086 	uint32_t port;
3087 	uint32_t v;
3088 
3089 	DPRINTF("index=%d lowspeed=%d\n", index, lowspeed);
3090 
3091 	port = EHCI_PORTSC(index);
3092 	v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3093 	EOWRITE4(sc, port, v | EHCI_PS_PO);
3094 }
3095 
3096 static usb_error_t
3097 ehci_roothub_exec(struct usb_device *udev,
3098     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3099 {
3100 	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3101 	const char *str_ptr;
3102 	const void *ptr;
3103 	uint32_t port;
3104 	uint32_t v;
3105 	uint16_t len;
3106 	uint16_t i;
3107 	uint16_t value;
3108 	uint16_t index;
3109 	usb_error_t err;
3110 
3111 	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3112 
3113 	/* buffer reset */
3114 	ptr = (const void *)&sc->sc_hub_desc;
3115 	len = 0;
3116 	err = 0;
3117 
3118 	value = UGETW(req->wValue);
3119 	index = UGETW(req->wIndex);
3120 
3121 	DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3122 	    "wValue=0x%04x wIndex=0x%04x\n",
3123 	    req->bmRequestType, req->bRequest,
3124 	    UGETW(req->wLength), value, index);
3125 
3126 #define	C(x,y) ((x) | ((y) << 8))
3127 	switch (C(req->bRequest, req->bmRequestType)) {
3128 	case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3129 	case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3130 	case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3131 		/*
3132 		 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3133 		 * for the integrated root hub.
3134 		 */
3135 		break;
3136 	case C(UR_GET_CONFIG, UT_READ_DEVICE):
3137 		len = 1;
3138 		sc->sc_hub_desc.temp[0] = sc->sc_conf;
3139 		break;
3140 	case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3141 		switch (value >> 8) {
3142 		case UDESC_DEVICE:
3143 			if ((value & 0xff) != 0) {
3144 				err = USB_ERR_IOERROR;
3145 				goto done;
3146 			}
3147 			len = sizeof(ehci_devd);
3148 			ptr = (const void *)&ehci_devd;
3149 			break;
3150 			/*
3151 			 * We can't really operate at another speed,
3152 			 * but the specification says we need this
3153 			 * descriptor:
3154 			 */
3155 		case UDESC_DEVICE_QUALIFIER:
3156 			if ((value & 0xff) != 0) {
3157 				err = USB_ERR_IOERROR;
3158 				goto done;
3159 			}
3160 			len = sizeof(ehci_odevd);
3161 			ptr = (const void *)&ehci_odevd;
3162 			break;
3163 
3164 		case UDESC_CONFIG:
3165 			if ((value & 0xff) != 0) {
3166 				err = USB_ERR_IOERROR;
3167 				goto done;
3168 			}
3169 			len = sizeof(ehci_confd);
3170 			ptr = (const void *)&ehci_confd;
3171 			break;
3172 
3173 		case UDESC_STRING:
3174 			switch (value & 0xff) {
3175 			case 0:	/* Language table */
3176 				str_ptr = "\001";
3177 				break;
3178 
3179 			case 1:	/* Vendor */
3180 				str_ptr = sc->sc_vendor;
3181 				break;
3182 
3183 			case 2:	/* Product */
3184 				str_ptr = "EHCI root HUB";
3185 				break;
3186 
3187 			default:
3188 				str_ptr = "";
3189 				break;
3190 			}
3191 
3192 			len = usb_make_str_desc(
3193 			    sc->sc_hub_desc.temp,
3194 			    sizeof(sc->sc_hub_desc.temp),
3195 			    str_ptr);
3196 			break;
3197 		default:
3198 			err = USB_ERR_IOERROR;
3199 			goto done;
3200 		}
3201 		break;
3202 	case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3203 		len = 1;
3204 		sc->sc_hub_desc.temp[0] = 0;
3205 		break;
3206 	case C(UR_GET_STATUS, UT_READ_DEVICE):
3207 		len = 2;
3208 		USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3209 		break;
3210 	case C(UR_GET_STATUS, UT_READ_INTERFACE):
3211 	case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3212 		len = 2;
3213 		USETW(sc->sc_hub_desc.stat.wStatus, 0);
3214 		break;
3215 	case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3216 		if (value >= EHCI_MAX_DEVICES) {
3217 			err = USB_ERR_IOERROR;
3218 			goto done;
3219 		}
3220 		sc->sc_addr = value;
3221 		break;
3222 	case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3223 		if ((value != 0) && (value != 1)) {
3224 			err = USB_ERR_IOERROR;
3225 			goto done;
3226 		}
3227 		sc->sc_conf = value;
3228 		break;
3229 	case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3230 		break;
3231 	case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3232 	case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3233 	case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3234 		err = USB_ERR_IOERROR;
3235 		goto done;
3236 	case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3237 		break;
3238 	case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3239 		break;
3240 		/* Hub requests */
3241 	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3242 		break;
3243 	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3244 		DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3245 
3246 		if ((index < 1) ||
3247 		    (index > sc->sc_noport)) {
3248 			err = USB_ERR_IOERROR;
3249 			goto done;
3250 		}
3251 		port = EHCI_PORTSC(index);
3252 		v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3253 		switch (value) {
3254 		case UHF_PORT_ENABLE:
3255 			EOWRITE4(sc, port, v & ~EHCI_PS_PE);
3256 			break;
3257 		case UHF_PORT_SUSPEND:
3258 			if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) {
3259 
3260 				/*
3261 				 * waking up a High Speed device is rather
3262 				 * complicated if
3263 				 */
3264 				EOWRITE4(sc, port, v | EHCI_PS_FPR);
3265 			}
3266 			/* wait 20ms for resume sequence to complete */
3267 			usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3268 
3269 			EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP |
3270 			    EHCI_PS_FPR | (3 << 10) /* High Speed */ ));
3271 
3272 			/* 4ms settle time */
3273 			usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3274 			break;
3275 		case UHF_PORT_POWER:
3276 			EOWRITE4(sc, port, v & ~EHCI_PS_PP);
3277 			break;
3278 		case UHF_PORT_TEST:
3279 			DPRINTFN(3, "clear port test "
3280 			    "%d\n", index);
3281 			break;
3282 		case UHF_PORT_INDICATOR:
3283 			DPRINTFN(3, "clear port ind "
3284 			    "%d\n", index);
3285 			EOWRITE4(sc, port, v & ~EHCI_PS_PIC);
3286 			break;
3287 		case UHF_C_PORT_CONNECTION:
3288 			EOWRITE4(sc, port, v | EHCI_PS_CSC);
3289 			break;
3290 		case UHF_C_PORT_ENABLE:
3291 			EOWRITE4(sc, port, v | EHCI_PS_PEC);
3292 			break;
3293 		case UHF_C_PORT_SUSPEND:
3294 			EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3295 			break;
3296 		case UHF_C_PORT_OVER_CURRENT:
3297 			EOWRITE4(sc, port, v | EHCI_PS_OCC);
3298 			break;
3299 		case UHF_C_PORT_RESET:
3300 			sc->sc_isreset = 0;
3301 			break;
3302 		default:
3303 			err = USB_ERR_IOERROR;
3304 			goto done;
3305 		}
3306 		break;
3307 	case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3308 		if ((value & 0xff) != 0) {
3309 			err = USB_ERR_IOERROR;
3310 			goto done;
3311 		}
3312 		v = EREAD4(sc, EHCI_HCSPARAMS);
3313 
3314 		sc->sc_hub_desc.hubd = ehci_hubd;
3315 		sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3316 
3317 		if (EHCI_HCS_PPC(v))
3318 			i = UHD_PWR_INDIVIDUAL;
3319 		else
3320 			i = UHD_PWR_NO_SWITCH;
3321 
3322 		if (EHCI_HCS_P_INDICATOR(v))
3323 			i |= UHD_PORT_IND;
3324 
3325 		USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3326 		/* XXX can't find out? */
3327 		sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200;
3328 		/* XXX don't know if ports are removable or not */
3329 		sc->sc_hub_desc.hubd.bDescLength =
3330 		    8 + ((sc->sc_noport + 7) / 8);
3331 		len = sc->sc_hub_desc.hubd.bDescLength;
3332 		break;
3333 	case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3334 		len = 16;
3335 		memset(sc->sc_hub_desc.temp, 0, 16);
3336 		break;
3337 	case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3338 		DPRINTFN(9, "get port status i=%d\n",
3339 		    index);
3340 		if ((index < 1) ||
3341 		    (index > sc->sc_noport)) {
3342 			err = USB_ERR_IOERROR;
3343 			goto done;
3344 		}
3345 		v = EOREAD4(sc, EHCI_PORTSC(index));
3346 		DPRINTFN(9, "port status=0x%04x\n", v);
3347 		if (sc->sc_flags & EHCI_SCFLG_TT) {
3348 			if (sc->sc_vendor_get_port_speed != NULL) {
3349 				i = sc->sc_vendor_get_port_speed(sc, index);
3350 			} else {
3351 				device_printf(sc->sc_bus.bdev,
3352 				    "EHCI_SCFLG_TT quirk is set but "
3353 				    "sc_vendor_get_hub_speed() is NULL\n");
3354 				i = UPS_HIGH_SPEED;
3355 			}
3356 		} else {
3357 			i = UPS_HIGH_SPEED;
3358 		}
3359 		if (v & EHCI_PS_CS)
3360 			i |= UPS_CURRENT_CONNECT_STATUS;
3361 		if (v & EHCI_PS_PE)
3362 			i |= UPS_PORT_ENABLED;
3363 		if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR))
3364 			i |= UPS_SUSPEND;
3365 		if (v & EHCI_PS_OCA)
3366 			i |= UPS_OVERCURRENT_INDICATOR;
3367 		if (v & EHCI_PS_PR)
3368 			i |= UPS_RESET;
3369 		if (v & EHCI_PS_PP)
3370 			i |= UPS_PORT_POWER;
3371 		USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3372 		i = 0;
3373 		if (v & EHCI_PS_CSC)
3374 			i |= UPS_C_CONNECT_STATUS;
3375 		if (v & EHCI_PS_PEC)
3376 			i |= UPS_C_PORT_ENABLED;
3377 		if (v & EHCI_PS_OCC)
3378 			i |= UPS_C_OVERCURRENT_INDICATOR;
3379 		if (v & EHCI_PS_FPR)
3380 			i |= UPS_C_SUSPEND;
3381 		if (sc->sc_isreset)
3382 			i |= UPS_C_PORT_RESET;
3383 		USETW(sc->sc_hub_desc.ps.wPortChange, i);
3384 		len = sizeof(sc->sc_hub_desc.ps);
3385 		break;
3386 	case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3387 		err = USB_ERR_IOERROR;
3388 		goto done;
3389 	case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3390 		break;
3391 	case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3392 		if ((index < 1) ||
3393 		    (index > sc->sc_noport)) {
3394 			err = USB_ERR_IOERROR;
3395 			goto done;
3396 		}
3397 		port = EHCI_PORTSC(index);
3398 		v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3399 		switch (value) {
3400 		case UHF_PORT_ENABLE:
3401 			EOWRITE4(sc, port, v | EHCI_PS_PE);
3402 			break;
3403 		case UHF_PORT_SUSPEND:
3404 			EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3405 			break;
3406 		case UHF_PORT_RESET:
3407 			DPRINTFN(6, "reset port %d\n", index);
3408 #ifdef USB_DEBUG
3409 			if (ehcinohighspeed) {
3410 				/*
3411 				 * Connect USB device to companion
3412 				 * controller.
3413 				 */
3414 				ehci_disown(sc, index, 1);
3415 				break;
3416 			}
3417 #endif
3418 			if (EHCI_PS_IS_LOWSPEED(v) &&
3419 			    (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3420 				/* Low speed device, give up ownership. */
3421 				ehci_disown(sc, index, 1);
3422 				break;
3423 			}
3424 			/* Start reset sequence. */
3425 			v &= ~(EHCI_PS_PE | EHCI_PS_PR);
3426 			EOWRITE4(sc, port, v | EHCI_PS_PR);
3427 
3428 			/* Wait for reset to complete. */
3429 			usb_pause_mtx(&sc->sc_bus.bus_mtx,
3430 			    USB_MS_TO_TICKS(usb_port_root_reset_delay));
3431 
3432 			/* Terminate reset sequence. */
3433 			if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
3434 				EOWRITE4(sc, port, v);
3435 
3436 			/* Wait for HC to complete reset. */
3437 			usb_pause_mtx(&sc->sc_bus.bus_mtx,
3438 			    USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
3439 
3440 			v = EOREAD4(sc, port);
3441 			DPRINTF("ehci after reset, status=0x%08x\n", v);
3442 			if (v & EHCI_PS_PR) {
3443 				device_printf(sc->sc_bus.bdev,
3444 				    "port reset timeout\n");
3445 				err = USB_ERR_TIMEOUT;
3446 				goto done;
3447 			}
3448 			if (!(v & EHCI_PS_PE) &&
3449 			    (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3450 				/* Not a high speed device, give up ownership.*/
3451 				ehci_disown(sc, index, 0);
3452 				break;
3453 			}
3454 			sc->sc_isreset = 1;
3455 			DPRINTF("ehci port %d reset, status = 0x%08x\n",
3456 			    index, v);
3457 			break;
3458 
3459 		case UHF_PORT_POWER:
3460 			DPRINTFN(3, "set port power %d\n", index);
3461 			EOWRITE4(sc, port, v | EHCI_PS_PP);
3462 			break;
3463 
3464 		case UHF_PORT_TEST:
3465 			DPRINTFN(3, "set port test %d\n", index);
3466 			break;
3467 
3468 		case UHF_PORT_INDICATOR:
3469 			DPRINTFN(3, "set port ind %d\n", index);
3470 			EOWRITE4(sc, port, v | EHCI_PS_PIC);
3471 			break;
3472 
3473 		default:
3474 			err = USB_ERR_IOERROR;
3475 			goto done;
3476 		}
3477 		break;
3478 	case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3479 	case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3480 	case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3481 	case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3482 		break;
3483 	default:
3484 		err = USB_ERR_IOERROR;
3485 		goto done;
3486 	}
3487 done:
3488 	*plength = len;
3489 	*pptr = ptr;
3490 	return (err);
3491 }
3492 
3493 static void
3494 ehci_xfer_setup(struct usb_setup_params *parm)
3495 {
3496 	struct usb_page_search page_info;
3497 	struct usb_page_cache *pc;
3498 	ehci_softc_t *sc;
3499 	struct usb_xfer *xfer;
3500 	void *last_obj;
3501 	uint32_t nqtd;
3502 	uint32_t nqh;
3503 	uint32_t nsitd;
3504 	uint32_t nitd;
3505 	uint32_t n;
3506 
3507 	sc = EHCI_BUS2SC(parm->udev->bus);
3508 	xfer = parm->curr_xfer;
3509 
3510 	nqtd = 0;
3511 	nqh = 0;
3512 	nsitd = 0;
3513 	nitd = 0;
3514 
3515 	/*
3516 	 * compute maximum number of some structures
3517 	 */
3518 	if (parm->methods == &ehci_device_ctrl_methods) {
3519 
3520 		/*
3521 		 * The proof for the "nqtd" formula is illustrated like
3522 		 * this:
3523 		 *
3524 		 * +------------------------------------+
3525 		 * |                                    |
3526 		 * |         |remainder ->              |
3527 		 * |   +-----+---+                      |
3528 		 * |   | xxx | x | frm 0                |
3529 		 * |   +-----+---++                     |
3530 		 * |   | xxx | xx | frm 1               |
3531 		 * |   +-----+----+                     |
3532 		 * |            ...                     |
3533 		 * +------------------------------------+
3534 		 *
3535 		 * "xxx" means a completely full USB transfer descriptor
3536 		 *
3537 		 * "x" and "xx" means a short USB packet
3538 		 *
3539 		 * For the remainder of an USB transfer modulo
3540 		 * "max_data_length" we need two USB transfer descriptors.
3541 		 * One to transfer the remaining data and one to finalise
3542 		 * with a zero length packet in case the "force_short_xfer"
3543 		 * flag is set. We only need two USB transfer descriptors in
3544 		 * the case where the transfer length of the first one is a
3545 		 * factor of "max_frame_size". The rest of the needed USB
3546 		 * transfer descriptors is given by the buffer size divided
3547 		 * by the maximum data payload.
3548 		 */
3549 		parm->hc_max_packet_size = 0x400;
3550 		parm->hc_max_packet_count = 1;
3551 		parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3552 		xfer->flags_int.bdma_enable = 1;
3553 
3554 		usbd_transfer_setup_sub(parm);
3555 
3556 		nqh = 1;
3557 		nqtd = ((2 * xfer->nframes) + 1	/* STATUS */
3558 		    + (xfer->max_data_length / xfer->max_hc_frame_size));
3559 
3560 	} else if (parm->methods == &ehci_device_bulk_methods) {
3561 
3562 		parm->hc_max_packet_size = 0x400;
3563 		parm->hc_max_packet_count = 1;
3564 		parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3565 		xfer->flags_int.bdma_enable = 1;
3566 
3567 		usbd_transfer_setup_sub(parm);
3568 
3569 		nqh = 1;
3570 		nqtd = ((2 * xfer->nframes)
3571 		    + (xfer->max_data_length / xfer->max_hc_frame_size));
3572 
3573 	} else if (parm->methods == &ehci_device_intr_methods) {
3574 
3575 		if (parm->speed == USB_SPEED_HIGH) {
3576 			parm->hc_max_packet_size = 0x400;
3577 			parm->hc_max_packet_count = 3;
3578 		} else if (parm->speed == USB_SPEED_FULL) {
3579 			parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME;
3580 			parm->hc_max_packet_count = 1;
3581 		} else {
3582 			parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8;
3583 			parm->hc_max_packet_count = 1;
3584 		}
3585 
3586 		parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3587 		xfer->flags_int.bdma_enable = 1;
3588 
3589 		usbd_transfer_setup_sub(parm);
3590 
3591 		nqh = 1;
3592 		nqtd = ((2 * xfer->nframes)
3593 		    + (xfer->max_data_length / xfer->max_hc_frame_size));
3594 
3595 	} else if (parm->methods == &ehci_device_isoc_fs_methods) {
3596 
3597 		parm->hc_max_packet_size = 0x3FF;
3598 		parm->hc_max_packet_count = 1;
3599 		parm->hc_max_frame_size = 0x3FF;
3600 		xfer->flags_int.bdma_enable = 1;
3601 
3602 		usbd_transfer_setup_sub(parm);
3603 
3604 		nsitd = xfer->nframes;
3605 
3606 	} else if (parm->methods == &ehci_device_isoc_hs_methods) {
3607 
3608 		parm->hc_max_packet_size = 0x400;
3609 		parm->hc_max_packet_count = 3;
3610 		parm->hc_max_frame_size = 0xC00;
3611 		xfer->flags_int.bdma_enable = 1;
3612 
3613 		usbd_transfer_setup_sub(parm);
3614 
3615 		nitd = ((xfer->nframes + 7) / 8) <<
3616 		    usbd_xfer_get_fps_shift(xfer);
3617 
3618 	} else {
3619 
3620 		parm->hc_max_packet_size = 0x400;
3621 		parm->hc_max_packet_count = 1;
3622 		parm->hc_max_frame_size = 0x400;
3623 
3624 		usbd_transfer_setup_sub(parm);
3625 	}
3626 
3627 alloc_dma_set:
3628 
3629 	if (parm->err) {
3630 		return;
3631 	}
3632 	/*
3633 	 * Allocate queue heads and transfer descriptors
3634 	 */
3635 	last_obj = NULL;
3636 
3637 	if (usbd_transfer_setup_sub_malloc(
3638 	    parm, &pc, sizeof(ehci_itd_t),
3639 	    EHCI_ITD_ALIGN, nitd)) {
3640 		parm->err = USB_ERR_NOMEM;
3641 		return;
3642 	}
3643 	if (parm->buf) {
3644 		for (n = 0; n != nitd; n++) {
3645 			ehci_itd_t *td;
3646 
3647 			usbd_get_page(pc + n, 0, &page_info);
3648 
3649 			td = page_info.buffer;
3650 
3651 			/* init TD */
3652 			td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD);
3653 			td->obj_next = last_obj;
3654 			td->page_cache = pc + n;
3655 
3656 			last_obj = td;
3657 
3658 			usb_pc_cpu_flush(pc + n);
3659 		}
3660 	}
3661 	if (usbd_transfer_setup_sub_malloc(
3662 	    parm, &pc, sizeof(ehci_sitd_t),
3663 	    EHCI_SITD_ALIGN, nsitd)) {
3664 		parm->err = USB_ERR_NOMEM;
3665 		return;
3666 	}
3667 	if (parm->buf) {
3668 		for (n = 0; n != nsitd; n++) {
3669 			ehci_sitd_t *td;
3670 
3671 			usbd_get_page(pc + n, 0, &page_info);
3672 
3673 			td = page_info.buffer;
3674 
3675 			/* init TD */
3676 			td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD);
3677 			td->obj_next = last_obj;
3678 			td->page_cache = pc + n;
3679 
3680 			last_obj = td;
3681 
3682 			usb_pc_cpu_flush(pc + n);
3683 		}
3684 	}
3685 	if (usbd_transfer_setup_sub_malloc(
3686 	    parm, &pc, sizeof(ehci_qtd_t),
3687 	    EHCI_QTD_ALIGN, nqtd)) {
3688 		parm->err = USB_ERR_NOMEM;
3689 		return;
3690 	}
3691 	if (parm->buf) {
3692 		for (n = 0; n != nqtd; n++) {
3693 			ehci_qtd_t *qtd;
3694 
3695 			usbd_get_page(pc + n, 0, &page_info);
3696 
3697 			qtd = page_info.buffer;
3698 
3699 			/* init TD */
3700 			qtd->qtd_self = htohc32(sc, page_info.physaddr);
3701 			qtd->obj_next = last_obj;
3702 			qtd->page_cache = pc + n;
3703 
3704 			last_obj = qtd;
3705 
3706 			usb_pc_cpu_flush(pc + n);
3707 		}
3708 	}
3709 	xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3710 
3711 	last_obj = NULL;
3712 
3713 	if (usbd_transfer_setup_sub_malloc(
3714 	    parm, &pc, sizeof(ehci_qh_t),
3715 	    EHCI_QH_ALIGN, nqh)) {
3716 		parm->err = USB_ERR_NOMEM;
3717 		return;
3718 	}
3719 	if (parm->buf) {
3720 		for (n = 0; n != nqh; n++) {
3721 			ehci_qh_t *qh;
3722 
3723 			usbd_get_page(pc + n, 0, &page_info);
3724 
3725 			qh = page_info.buffer;
3726 
3727 			/* init QH */
3728 			qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH);
3729 			qh->obj_next = last_obj;
3730 			qh->page_cache = pc + n;
3731 
3732 			last_obj = qh;
3733 
3734 			usb_pc_cpu_flush(pc + n);
3735 		}
3736 	}
3737 	xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3738 
3739 	if (!xfer->flags_int.curr_dma_set) {
3740 		xfer->flags_int.curr_dma_set = 1;
3741 		goto alloc_dma_set;
3742 	}
3743 }
3744 
3745 static void
3746 ehci_xfer_unsetup(struct usb_xfer *xfer)
3747 {
3748 	return;
3749 }
3750 
3751 static void
3752 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3753     struct usb_endpoint *ep)
3754 {
3755 	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3756 
3757 	DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3758 	    ep, udev->address,
3759 	    edesc->bEndpointAddress, udev->flags.usb_mode,
3760 	    sc->sc_addr);
3761 
3762 	if (udev->device_index != sc->sc_addr) {
3763 
3764 		if ((udev->speed != USB_SPEED_HIGH) &&
3765 		    ((udev->hs_hub_addr == 0) ||
3766 		    (udev->hs_port_no == 0) ||
3767 		    (udev->parent_hs_hub == NULL) ||
3768 		    (udev->parent_hs_hub->hub == NULL))) {
3769 			/* We need a transaction translator */
3770 			goto done;
3771 		}
3772 		switch (edesc->bmAttributes & UE_XFERTYPE) {
3773 		case UE_CONTROL:
3774 			ep->methods = &ehci_device_ctrl_methods;
3775 			break;
3776 		case UE_INTERRUPT:
3777 			ep->methods = &ehci_device_intr_methods;
3778 			break;
3779 		case UE_ISOCHRONOUS:
3780 			if (udev->speed == USB_SPEED_HIGH) {
3781 				ep->methods = &ehci_device_isoc_hs_methods;
3782 			} else if (udev->speed == USB_SPEED_FULL) {
3783 				ep->methods = &ehci_device_isoc_fs_methods;
3784 			}
3785 			break;
3786 		case UE_BULK:
3787 			ep->methods = &ehci_device_bulk_methods;
3788 			break;
3789 		default:
3790 			/* do nothing */
3791 			break;
3792 		}
3793 	}
3794 done:
3795 	return;
3796 }
3797 
3798 static void
3799 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3800 {
3801 	/*
3802 	 * Wait until the hardware has finished any possible use of
3803 	 * the transfer descriptor(s) and QH
3804 	 */
3805 	*pus = (1125);			/* microseconds */
3806 }
3807 
3808 static void
3809 ehci_device_resume(struct usb_device *udev)
3810 {
3811 	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3812 	struct usb_xfer *xfer;
3813 	const struct usb_pipe_methods *methods;
3814 
3815 	DPRINTF("\n");
3816 
3817 	USB_BUS_LOCK(udev->bus);
3818 
3819 	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3820 
3821 		if (xfer->xroot->udev == udev) {
3822 
3823 			methods = xfer->endpoint->methods;
3824 
3825 			if ((methods == &ehci_device_bulk_methods) ||
3826 			    (methods == &ehci_device_ctrl_methods)) {
3827 				EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3828 				    sc->sc_async_p_last);
3829 			}
3830 			if (methods == &ehci_device_intr_methods) {
3831 				EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3832 				    sc->sc_intr_p_last[xfer->qh_pos]);
3833 			}
3834 		}
3835 	}
3836 
3837 	USB_BUS_UNLOCK(udev->bus);
3838 
3839 	return;
3840 }
3841 
3842 static void
3843 ehci_device_suspend(struct usb_device *udev)
3844 {
3845 	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3846 	struct usb_xfer *xfer;
3847 	const struct usb_pipe_methods *methods;
3848 
3849 	DPRINTF("\n");
3850 
3851 	USB_BUS_LOCK(udev->bus);
3852 
3853 	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3854 
3855 		if (xfer->xroot->udev == udev) {
3856 
3857 			methods = xfer->endpoint->methods;
3858 
3859 			if ((methods == &ehci_device_bulk_methods) ||
3860 			    (methods == &ehci_device_ctrl_methods)) {
3861 				EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3862 				    sc->sc_async_p_last);
3863 			}
3864 			if (methods == &ehci_device_intr_methods) {
3865 				EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3866 				    sc->sc_intr_p_last[xfer->qh_pos]);
3867 			}
3868 		}
3869 	}
3870 
3871 	USB_BUS_UNLOCK(udev->bus);
3872 }
3873 
3874 static void
3875 ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3876 {
3877 	struct ehci_softc *sc = EHCI_BUS2SC(bus);
3878 
3879 	switch (state) {
3880 	case USB_HW_POWER_SUSPEND:
3881 	case USB_HW_POWER_SHUTDOWN:
3882 		ehci_suspend(sc);
3883 		break;
3884 	case USB_HW_POWER_RESUME:
3885 		ehci_resume(sc);
3886 		break;
3887 	default:
3888 		break;
3889 	}
3890 }
3891 
3892 static void
3893 ehci_set_hw_power(struct usb_bus *bus)
3894 {
3895 	ehci_softc_t *sc = EHCI_BUS2SC(bus);
3896 	uint32_t temp;
3897 	uint32_t flags;
3898 
3899 	DPRINTF("\n");
3900 
3901 	USB_BUS_LOCK(bus);
3902 
3903 	flags = bus->hw_power_state;
3904 
3905 	temp = EOREAD4(sc, EHCI_USBCMD);
3906 
3907 	temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
3908 
3909 	if (flags & (USB_HW_POWER_CONTROL |
3910 	    USB_HW_POWER_BULK)) {
3911 		DPRINTF("Async is active\n");
3912 		temp |= EHCI_CMD_ASE;
3913 	}
3914 	if (flags & (USB_HW_POWER_INTERRUPT |
3915 	    USB_HW_POWER_ISOC)) {
3916 		DPRINTF("Periodic is active\n");
3917 		temp |= EHCI_CMD_PSE;
3918 	}
3919 	EOWRITE4(sc, EHCI_USBCMD, temp);
3920 
3921 	USB_BUS_UNLOCK(bus);
3922 
3923 	return;
3924 }
3925 
3926 static void
3927 ehci_start_dma_delay_second(struct usb_xfer *xfer)
3928 {
3929 	struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus);
3930 
3931 	DPRINTF("\n");
3932 
3933 	/* trigger doorbell */
3934 	ehci_doorbell_async(sc);
3935 
3936 	/* give the doorbell 4ms */
3937 	usbd_transfer_timeout_ms(xfer,
3938 	    (void (*)(void *))&usb_dma_delay_done_cb, 4);
3939 }
3940 
3941 /*
3942  * Ring the doorbell twice before freeing any DMA descriptors. Some host
3943  * controllers apparently cache the QH descriptors and need a message
3944  * that the cache needs to be discarded.
3945  */
3946 static void
3947 ehci_start_dma_delay(struct usb_xfer *xfer)
3948 {
3949 	struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus);
3950 
3951 	DPRINTF("\n");
3952 
3953 	/* trigger doorbell */
3954 	ehci_doorbell_async(sc);
3955 
3956 	/* give the doorbell 4ms */
3957 	usbd_transfer_timeout_ms(xfer,
3958 	    (void (*)(void *))&ehci_start_dma_delay_second, 4);
3959 }
3960 
3961 static const struct usb_bus_methods ehci_bus_methods =
3962 {
3963 	.endpoint_init = ehci_ep_init,
3964 	.xfer_setup = ehci_xfer_setup,
3965 	.xfer_unsetup = ehci_xfer_unsetup,
3966 	.get_dma_delay = ehci_get_dma_delay,
3967 	.device_resume = ehci_device_resume,
3968 	.device_suspend = ehci_device_suspend,
3969 	.set_hw_power = ehci_set_hw_power,
3970 	.set_hw_power_sleep = ehci_set_hw_power_sleep,
3971 	.roothub_exec = ehci_roothub_exec,
3972 	.xfer_poll = ehci_do_poll,
3973 	.start_dma_delay = ehci_start_dma_delay,
3974 };
3975